1/*- 2 * Copyright (C) 2013 Emulex 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Emulex Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 * 31 * Contact Information: 32 * freebsd-drivers@emulex.com 33 * 34 * Emulex 35 * 3333 Susan Street 36 * Costa Mesa, CA 92626 37 */ 38 39/* $FreeBSD: stable/11/sys/dev/oce/oce_if.h 356090 2019-12-26 16:58:11Z markj $ */ 40 41#include <sys/param.h> 42#include <sys/endian.h> 43#include <sys/eventhandler.h> 44#include <sys/malloc.h> 45#include <sys/module.h> 46#include <sys/kernel.h> 47#include <sys/bus.h> 48#include <sys/mbuf.h> 49#include <sys/priv.h> 50#include <sys/rman.h> 51#include <sys/socket.h> 52#include <sys/sockio.h> 53#include <sys/sockopt.h> 54#include <sys/queue.h> 55#include <sys/taskqueue.h> 56#include <sys/lock.h> 57#include <sys/mutex.h> 58#include <sys/sysctl.h> 59#include <sys/random.h> 60#include <sys/firmware.h> 61#include <sys/systm.h> 62#include <sys/proc.h> 63 64#include <dev/pci/pcireg.h> 65#include <dev/pci/pcivar.h> 66 67#include <net/bpf.h> 68#include <net/ethernet.h> 69#include <net/if.h> 70#include <net/if_var.h> 71#include <net/if_types.h> 72#include <net/if_media.h> 73#include <net/if_vlan_var.h> 74#include <net/if_dl.h> 75 76#include <netinet/in.h> 77#include <netinet/in_systm.h> 78#include <netinet/in_var.h> 79#include <netinet/if_ether.h> 80#include <netinet/ip.h> 81#include <netinet/ip6.h> 82#include <netinet6/in6_var.h> 83#include <netinet6/ip6_mroute.h> 84 85#include <netinet/udp.h> 86#include <netinet/tcp.h> 87#include <netinet/sctp.h> 88#include <netinet/tcp_lro.h> 89#include <netinet/icmp6.h> 90 91#include <machine/bus.h> 92 93#include "oce_hw.h" 94 95/* OCE device driver module component revision informaiton */ 96#define COMPONENT_REVISION "11.0.50.0" 97 98/* OCE devices supported by this driver */ 99#define PCI_VENDOR_EMULEX 0x10df /* Emulex */ 100#define PCI_VENDOR_SERVERENGINES 0x19a2 /* ServerEngines (BE) */ 101#define PCI_PRODUCT_BE2 0x0700 /* BE2 network adapter */ 102#define PCI_PRODUCT_BE3 0x0710 /* BE3 network adapter */ 103#define PCI_PRODUCT_XE201 0xe220 /* XE201 network adapter */ 104#define PCI_PRODUCT_XE201_VF 0xe228 /* XE201 with VF in Lancer */ 105#define PCI_PRODUCT_SH 0x0720 /* Skyhawk network adapter */ 106 107#define IS_BE(sc) (((sc->flags & OCE_FLAGS_BE3) | \ 108 (sc->flags & OCE_FLAGS_BE2))? 1:0) 109#define IS_BE3(sc) (sc->flags & OCE_FLAGS_BE3) 110#define IS_BE2(sc) (sc->flags & OCE_FLAGS_BE2) 111#define IS_XE201(sc) ((sc->flags & OCE_FLAGS_XE201) ? 1:0) 112#define HAS_A0_CHIP(sc) ((sc->flags & OCE_FLAGS_HAS_A0_CHIP) ? 1:0) 113#define IS_SH(sc) ((sc->flags & OCE_FLAGS_SH) ? 1 : 0) 114 115#define is_be_mode_mc(sc) ((sc->function_mode & FNM_FLEX10_MODE) || \ 116 (sc->function_mode & FNM_UMC_MODE) || \ 117 (sc->function_mode & FNM_VNIC_MODE)) 118#define OCE_FUNCTION_CAPS_SUPER_NIC 0x40 119#define IS_PROFILE_SUPER_NIC(sc) (sc->function_caps & OCE_FUNCTION_CAPS_SUPER_NIC) 120 121 122/* proportion Service Level Interface queues */ 123#define OCE_MAX_UNITS 2 124#define OCE_MAX_PPORT OCE_MAX_UNITS 125#define OCE_MAX_VPORT OCE_MAX_UNITS 126 127extern int mp_ncpus; /* system's total active cpu cores */ 128#define OCE_NCPUS mp_ncpus 129 130/* This should be powers of 2. Like 2,4,8 & 16 */ 131#define OCE_MAX_RSS 8 132#define OCE_LEGACY_MODE_RSS 4 /* For BE3 Legacy mode*/ 133#define is_rss_enabled(sc) ((sc->function_caps & FNC_RSS) && !is_be_mode_mc(sc)) 134 135#define OCE_MIN_RQ 1 136#define OCE_MIN_WQ 1 137 138#define OCE_MAX_RQ OCE_MAX_RSS + 1 /* one default queue */ 139#define OCE_MAX_WQ 8 140 141#define OCE_MAX_EQ 32 142#define OCE_MAX_CQ OCE_MAX_RQ + OCE_MAX_WQ + 1 /* one MCC queue */ 143#define OCE_MAX_CQ_EQ 8 /* Max CQ that can attached to an EQ */ 144 145#define OCE_DEFAULT_WQ_EQD 16 146#define OCE_MAX_PACKET_Q 16 147#define OCE_LSO_MAX_SIZE (64 * 1024) 148#define LONG_TIMEOUT 30 149#define OCE_MAX_JUMBO_FRAME_SIZE 9018 150#define OCE_MAX_MTU (OCE_MAX_JUMBO_FRAME_SIZE - \ 151 ETHER_VLAN_ENCAP_LEN - \ 152 ETHER_HDR_LEN) 153 154#define OCE_RDMA_VECTORS 2 155 156#define OCE_MAX_TX_ELEMENTS 29 157#define OCE_MAX_TX_DESC 1024 158#define OCE_MAX_TX_SIZE 65535 159#define OCE_MAX_TSO_SIZE (65535 - ETHER_HDR_LEN) 160#define OCE_MAX_RX_SIZE 4096 161#define OCE_MAX_RQ_POSTS 255 162#define OCE_HWLRO_MAX_RQ_POSTS 64 163#define OCE_DEFAULT_PROMISCUOUS 0 164 165 166#define RSS_ENABLE_IPV4 0x1 167#define RSS_ENABLE_TCP_IPV4 0x2 168#define RSS_ENABLE_IPV6 0x4 169#define RSS_ENABLE_TCP_IPV6 0x8 170 171#define INDIRECTION_TABLE_ENTRIES 128 172 173/* flow control definitions */ 174#define OCE_FC_NONE 0x00000000 175#define OCE_FC_TX 0x00000001 176#define OCE_FC_RX 0x00000002 177#define OCE_DEFAULT_FLOW_CONTROL (OCE_FC_TX | OCE_FC_RX) 178 179 180/* Interface capabilities to give device when creating interface */ 181#define OCE_CAPAB_FLAGS (MBX_RX_IFACE_FLAGS_BROADCAST | \ 182 MBX_RX_IFACE_FLAGS_UNTAGGED | \ 183 MBX_RX_IFACE_FLAGS_PROMISCUOUS | \ 184 MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS | \ 185 MBX_RX_IFACE_FLAGS_MCAST_PROMISCUOUS | \ 186 MBX_RX_IFACE_FLAGS_RSS | \ 187 MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR) 188 189/* Interface capabilities to enable by default (others set dynamically) */ 190#define OCE_CAPAB_ENABLE (MBX_RX_IFACE_FLAGS_BROADCAST | \ 191 MBX_RX_IFACE_FLAGS_UNTAGGED | \ 192 MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR) 193 194#define OCE_IF_HWASSIST (CSUM_IP | CSUM_TCP | CSUM_UDP) 195#define OCE_IF_CAPABILITIES (IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 196 IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | \ 197 IFCAP_JUMBO_MTU | IFCAP_VLAN_MTU) 198#define OCE_IF_HWASSIST_NONE 0 199#define OCE_IF_CAPABILITIES_NONE 0 200 201 202#define ETH_ADDR_LEN 6 203#define MAX_VLANFILTER_SIZE 64 204#define MAX_VLANS 4096 205 206#define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16)) 207#define BSWAP_8(x) ((x) & 0xff) 208#define BSWAP_16(x) ((BSWAP_8(x) << 8) | BSWAP_8((x) >> 8)) 209#define BSWAP_32(x) ((BSWAP_16(x) << 16) | \ 210 BSWAP_16((x) >> 16)) 211#define BSWAP_64(x) ((BSWAP_32(x) << 32) | \ 212 BSWAP_32((x) >> 32)) 213 214#define for_all_wq_queues(sc, wq, i) \ 215 for (i = 0, wq = sc->wq[0]; i < sc->nwqs; i++, wq = sc->wq[i]) 216#define for_all_rq_queues(sc, rq, i) \ 217 for (i = 0, rq = sc->rq[0]; i < sc->nrqs; i++, rq = sc->rq[i]) 218#define for_all_rss_queues(sc, rq, i) \ 219 for (i = 0, rq = sc->rq[i + 1]; i < (sc->nrqs - 1); \ 220 i++, rq = sc->rq[i + 1]) 221#define for_all_evnt_queues(sc, eq, i) \ 222 for (i = 0, eq = sc->eq[0]; i < sc->neqs; i++, eq = sc->eq[i]) 223#define for_all_cq_queues(sc, cq, i) \ 224 for (i = 0, cq = sc->cq[0]; i < sc->ncqs; i++, cq = sc->cq[i]) 225 226 227/* Flash specific */ 228#define IOCTL_COOKIE "SERVERENGINES CORP" 229#define MAX_FLASH_COMP 32 230 231#define IMG_ISCSI 160 232#define IMG_REDBOOT 224 233#define IMG_BIOS 34 234#define IMG_PXEBIOS 32 235#define IMG_FCOEBIOS 33 236#define IMG_ISCSI_BAK 176 237#define IMG_FCOE 162 238#define IMG_FCOE_BAK 178 239#define IMG_NCSI 16 240#define IMG_PHY 192 241#define FLASHROM_OPER_FLASH 1 242#define FLASHROM_OPER_SAVE 2 243#define FLASHROM_OPER_REPORT 4 244#define FLASHROM_OPER_FLASH_PHY 9 245#define FLASHROM_OPER_SAVE_PHY 10 246#define TN_8022 13 247 248enum { 249 PHY_TYPE_CX4_10GB = 0, 250 PHY_TYPE_XFP_10GB, 251 PHY_TYPE_SFP_1GB, 252 PHY_TYPE_SFP_PLUS_10GB, 253 PHY_TYPE_KR_10GB, 254 PHY_TYPE_KX4_10GB, 255 PHY_TYPE_BASET_10GB, 256 PHY_TYPE_BASET_1GB, 257 PHY_TYPE_BASEX_1GB, 258 PHY_TYPE_SGMII, 259 PHY_TYPE_DISABLED = 255 260}; 261 262/** 263 * @brief Define and hold all necessary info for a single interrupt 264 */ 265#define OCE_MAX_MSI 32 /* Message Signaled Interrupts */ 266#define OCE_MAX_MSIX 2048 /* PCI Express MSI Interrrupts */ 267 268typedef struct oce_intr_info { 269 void *tag; /* cookie returned by bus_setup_intr */ 270 struct resource *intr_res; /* PCI resource container */ 271 int irq_rr; /* resource id for the interrupt */ 272 struct oce_softc *sc; /* pointer to the parent soft c */ 273 struct oce_eq *eq; /* pointer to the connected EQ */ 274 struct taskqueue *tq; /* Associated task queue */ 275 struct task task; /* task queue task */ 276 char task_name[32]; /* task name */ 277 int vector; /* interrupt vector number */ 278} OCE_INTR_INFO, *POCE_INTR_INFO; 279 280 281/* Ring related */ 282#define GET_Q_NEXT(_START, _STEP, _END) \ 283 (((_START) + (_STEP)) < (_END) ? ((_START) + (_STEP)) \ 284 : (((_START) + (_STEP)) - (_END))) 285 286#define DBUF_PA(obj) ((obj)->addr) 287#define DBUF_VA(obj) ((obj)->ptr) 288#define DBUF_TAG(obj) ((obj)->tag) 289#define DBUF_MAP(obj) ((obj)->map) 290#define DBUF_SYNC(obj, flags) \ 291 (void) bus_dmamap_sync(DBUF_TAG(obj), DBUF_MAP(obj), (flags)) 292 293#define RING_NUM_PENDING(ring) ring->num_used 294#define RING_FULL(ring) (ring->num_used == ring->num_items) 295#define RING_EMPTY(ring) (ring->num_used == 0) 296#define RING_NUM_FREE(ring) \ 297 (uint32_t)(ring->num_items - ring->num_used) 298#define RING_GET(ring, n) \ 299 ring->cidx = GET_Q_NEXT(ring->cidx, n, ring->num_items) 300#define RING_PUT(ring, n) \ 301 ring->pidx = GET_Q_NEXT(ring->pidx, n, ring->num_items) 302 303#define RING_GET_CONSUMER_ITEM_VA(ring, type) \ 304 (void*)((type *)DBUF_VA(&ring->dma) + ring->cidx) 305#define RING_GET_CONSUMER_ITEM_PA(ring, type) \ 306 (uint64_t)(((type *)DBUF_PA(ring->dbuf)) + ring->cidx) 307#define RING_GET_PRODUCER_ITEM_VA(ring, type) \ 308 (void *)(((type *)DBUF_VA(&ring->dma)) + ring->pidx) 309#define RING_GET_PRODUCER_ITEM_PA(ring, type) \ 310 (uint64_t)(((type *)DBUF_PA(ring->dbuf)) + ring->pidx) 311 312#define OCE_DMAPTR(o, c) ((c *)(o)->ptr) 313 314struct oce_packet_desc { 315 struct mbuf *mbuf; 316 bus_dmamap_t map; 317 int nsegs; 318 uint32_t wqe_idx; 319}; 320 321typedef struct oce_dma_mem { 322 bus_dma_tag_t tag; 323 bus_dmamap_t map; 324 void *ptr; 325 bus_addr_t paddr; 326} OCE_DMA_MEM, *POCE_DMA_MEM; 327 328typedef struct oce_ring_buffer_s { 329 uint16_t cidx; /* Get ptr */ 330 uint16_t pidx; /* Put Ptr */ 331 size_t item_size; 332 size_t num_items; 333 uint32_t num_used; 334 OCE_DMA_MEM dma; 335} oce_ring_buffer_t; 336 337/* Stats */ 338#define OCE_UNICAST_PACKET 0 339#define OCE_MULTICAST_PACKET 1 340#define OCE_BROADCAST_PACKET 2 341#define OCE_RSVD_PACKET 3 342 343struct oce_rx_stats { 344 /* Total Receive Stats*/ 345 uint64_t t_rx_pkts; 346 uint64_t t_rx_bytes; 347 uint32_t t_rx_frags; 348 uint32_t t_rx_mcast_pkts; 349 uint32_t t_rx_ucast_pkts; 350 uint32_t t_rxcp_errs; 351}; 352struct oce_tx_stats { 353 /*Total Transmit Stats */ 354 uint64_t t_tx_pkts; 355 uint64_t t_tx_bytes; 356 uint32_t t_tx_reqs; 357 uint32_t t_tx_stops; 358 uint32_t t_tx_wrbs; 359 uint32_t t_tx_compl; 360 uint32_t t_ipv6_ext_hdr_tx_drop; 361}; 362 363struct oce_be_stats { 364 uint8_t be_on_die_temperature; 365 uint32_t be_tx_events; 366 uint32_t eth_red_drops; 367 uint32_t rx_drops_no_pbuf; 368 uint32_t rx_drops_no_txpb; 369 uint32_t rx_drops_no_erx_descr; 370 uint32_t rx_drops_no_tpre_descr; 371 uint32_t rx_drops_too_many_frags; 372 uint32_t rx_drops_invalid_ring; 373 uint32_t forwarded_packets; 374 uint32_t rx_drops_mtu; 375 uint32_t rx_crc_errors; 376 uint32_t rx_alignment_symbol_errors; 377 uint32_t rx_pause_frames; 378 uint32_t rx_priority_pause_frames; 379 uint32_t rx_control_frames; 380 uint32_t rx_in_range_errors; 381 uint32_t rx_out_range_errors; 382 uint32_t rx_frame_too_long; 383 uint32_t rx_address_match_errors; 384 uint32_t rx_dropped_too_small; 385 uint32_t rx_dropped_too_short; 386 uint32_t rx_dropped_header_too_small; 387 uint32_t rx_dropped_tcp_length; 388 uint32_t rx_dropped_runt; 389 uint32_t rx_ip_checksum_errs; 390 uint32_t rx_tcp_checksum_errs; 391 uint32_t rx_udp_checksum_errs; 392 uint32_t rx_switched_unicast_packets; 393 uint32_t rx_switched_multicast_packets; 394 uint32_t rx_switched_broadcast_packets; 395 uint32_t tx_pauseframes; 396 uint32_t tx_priority_pauseframes; 397 uint32_t tx_controlframes; 398 uint32_t rxpp_fifo_overflow_drop; 399 uint32_t rx_input_fifo_overflow_drop; 400 uint32_t pmem_fifo_overflow_drop; 401 uint32_t jabber_events; 402}; 403 404struct oce_xe201_stats { 405 uint64_t tx_pkts; 406 uint64_t tx_unicast_pkts; 407 uint64_t tx_multicast_pkts; 408 uint64_t tx_broadcast_pkts; 409 uint64_t tx_bytes; 410 uint64_t tx_unicast_bytes; 411 uint64_t tx_multicast_bytes; 412 uint64_t tx_broadcast_bytes; 413 uint64_t tx_discards; 414 uint64_t tx_errors; 415 uint64_t tx_pause_frames; 416 uint64_t tx_pause_on_frames; 417 uint64_t tx_pause_off_frames; 418 uint64_t tx_internal_mac_errors; 419 uint64_t tx_control_frames; 420 uint64_t tx_pkts_64_bytes; 421 uint64_t tx_pkts_65_to_127_bytes; 422 uint64_t tx_pkts_128_to_255_bytes; 423 uint64_t tx_pkts_256_to_511_bytes; 424 uint64_t tx_pkts_512_to_1023_bytes; 425 uint64_t tx_pkts_1024_to_1518_bytes; 426 uint64_t tx_pkts_1519_to_2047_bytes; 427 uint64_t tx_pkts_2048_to_4095_bytes; 428 uint64_t tx_pkts_4096_to_8191_bytes; 429 uint64_t tx_pkts_8192_to_9216_bytes; 430 uint64_t tx_lso_pkts; 431 uint64_t rx_pkts; 432 uint64_t rx_unicast_pkts; 433 uint64_t rx_multicast_pkts; 434 uint64_t rx_broadcast_pkts; 435 uint64_t rx_bytes; 436 uint64_t rx_unicast_bytes; 437 uint64_t rx_multicast_bytes; 438 uint64_t rx_broadcast_bytes; 439 uint32_t rx_unknown_protos; 440 uint64_t rx_discards; 441 uint64_t rx_errors; 442 uint64_t rx_crc_errors; 443 uint64_t rx_alignment_errors; 444 uint64_t rx_symbol_errors; 445 uint64_t rx_pause_frames; 446 uint64_t rx_pause_on_frames; 447 uint64_t rx_pause_off_frames; 448 uint64_t rx_frames_too_long; 449 uint64_t rx_internal_mac_errors; 450 uint32_t rx_undersize_pkts; 451 uint32_t rx_oversize_pkts; 452 uint32_t rx_fragment_pkts; 453 uint32_t rx_jabbers; 454 uint64_t rx_control_frames; 455 uint64_t rx_control_frames_unknown_opcode; 456 uint32_t rx_in_range_errors; 457 uint32_t rx_out_of_range_errors; 458 uint32_t rx_address_match_errors; 459 uint32_t rx_vlan_mismatch_errors; 460 uint32_t rx_dropped_too_small; 461 uint32_t rx_dropped_too_short; 462 uint32_t rx_dropped_header_too_small; 463 uint32_t rx_dropped_invalid_tcp_length; 464 uint32_t rx_dropped_runt; 465 uint32_t rx_ip_checksum_errors; 466 uint32_t rx_tcp_checksum_errors; 467 uint32_t rx_udp_checksum_errors; 468 uint32_t rx_non_rss_pkts; 469 uint64_t rx_ipv4_pkts; 470 uint64_t rx_ipv6_pkts; 471 uint64_t rx_ipv4_bytes; 472 uint64_t rx_ipv6_bytes; 473 uint64_t rx_nic_pkts; 474 uint64_t rx_tcp_pkts; 475 uint64_t rx_iscsi_pkts; 476 uint64_t rx_management_pkts; 477 uint64_t rx_switched_unicast_pkts; 478 uint64_t rx_switched_multicast_pkts; 479 uint64_t rx_switched_broadcast_pkts; 480 uint64_t num_forwards; 481 uint32_t rx_fifo_overflow; 482 uint32_t rx_input_fifo_overflow; 483 uint64_t rx_drops_too_many_frags; 484 uint32_t rx_drops_invalid_queue; 485 uint64_t rx_drops_mtu; 486 uint64_t rx_pkts_64_bytes; 487 uint64_t rx_pkts_65_to_127_bytes; 488 uint64_t rx_pkts_128_to_255_bytes; 489 uint64_t rx_pkts_256_to_511_bytes; 490 uint64_t rx_pkts_512_to_1023_bytes; 491 uint64_t rx_pkts_1024_to_1518_bytes; 492 uint64_t rx_pkts_1519_to_2047_bytes; 493 uint64_t rx_pkts_2048_to_4095_bytes; 494 uint64_t rx_pkts_4096_to_8191_bytes; 495 uint64_t rx_pkts_8192_to_9216_bytes; 496}; 497 498struct oce_drv_stats { 499 struct oce_rx_stats rx; 500 struct oce_tx_stats tx; 501 union { 502 struct oce_be_stats be; 503 struct oce_xe201_stats xe201; 504 } u0; 505}; 506 507#define INTR_RATE_HWM 15000 508#define INTR_RATE_LWM 10000 509 510#define OCE_MAX_EQD 128u 511#define OCE_MIN_EQD 0u 512 513struct oce_set_eqd { 514 uint32_t eq_id; 515 uint32_t phase; 516 uint32_t delay_multiplier; 517}; 518 519struct oce_aic_obj { /* Adaptive interrupt coalescing (AIC) info */ 520 boolean_t enable; 521 uint32_t min_eqd; /* in usecs */ 522 uint32_t max_eqd; /* in usecs */ 523 uint32_t cur_eqd; /* in usecs */ 524 uint32_t et_eqd; /* configured value when aic is off */ 525 uint64_t ticks; 526 uint64_t prev_rxpkts; 527 uint64_t prev_txreqs; 528}; 529 530#define MAX_LOCK_DESC_LEN 32 531struct oce_lock { 532 struct mtx mutex; 533 char name[MAX_LOCK_DESC_LEN+1]; 534}; 535#define OCE_LOCK struct oce_lock 536 537#define LOCK_CREATE(lock, desc) { \ 538 strncpy((lock)->name, (desc), MAX_LOCK_DESC_LEN); \ 539 (lock)->name[MAX_LOCK_DESC_LEN] = '\0'; \ 540 mtx_init(&(lock)->mutex, (lock)->name, NULL, MTX_DEF); \ 541} 542#define LOCK_DESTROY(lock) \ 543 if (mtx_initialized(&(lock)->mutex))\ 544 mtx_destroy(&(lock)->mutex) 545#define TRY_LOCK(lock) mtx_trylock(&(lock)->mutex) 546#define LOCK(lock) mtx_lock(&(lock)->mutex) 547#define LOCKED(lock) mtx_owned(&(lock)->mutex) 548#define UNLOCK(lock) mtx_unlock(&(lock)->mutex) 549 550#define DEFAULT_MQ_MBOX_TIMEOUT (5 * 1000 * 1000) 551#define MBX_READY_TIMEOUT (1 * 1000 * 1000) 552#define DEFAULT_DRAIN_TIME 200 553#define MBX_TIMEOUT_SEC 5 554#define STAT_TIMEOUT 2000000 555 556/* size of the packet descriptor array in a transmit queue */ 557#define OCE_TX_RING_SIZE 2048 558#define OCE_RX_RING_SIZE 1024 559#define OCE_WQ_PACKET_ARRAY_SIZE (OCE_TX_RING_SIZE/2) 560#define OCE_RQ_PACKET_ARRAY_SIZE (OCE_RX_RING_SIZE) 561 562struct oce_dev; 563 564enum eq_len { 565 EQ_LEN_256 = 256, 566 EQ_LEN_512 = 512, 567 EQ_LEN_1024 = 1024, 568 EQ_LEN_2048 = 2048, 569 EQ_LEN_4096 = 4096 570}; 571 572enum eqe_size { 573 EQE_SIZE_4 = 4, 574 EQE_SIZE_16 = 16 575}; 576 577enum qtype { 578 QTYPE_EQ, 579 QTYPE_MQ, 580 QTYPE_WQ, 581 QTYPE_RQ, 582 QTYPE_CQ, 583 QTYPE_RSS 584}; 585 586typedef enum qstate_e { 587 QDELETED = 0x0, 588 QCREATED = 0x1 589} qstate_t; 590 591struct eq_config { 592 enum eq_len q_len; 593 enum eqe_size item_size; 594 uint32_t q_vector_num; 595 uint8_t min_eqd; 596 uint8_t max_eqd; 597 uint8_t cur_eqd; 598 uint8_t pad; 599}; 600 601struct oce_eq { 602 uint32_t eq_id; 603 void *parent; 604 void *cb_context; 605 oce_ring_buffer_t *ring; 606 uint32_t ref_count; 607 qstate_t qstate; 608 struct oce_cq *cq[OCE_MAX_CQ_EQ]; 609 int cq_valid; 610 struct eq_config eq_cfg; 611 int vector; 612 uint64_t intr; 613}; 614 615enum cq_len { 616 CQ_LEN_256 = 256, 617 CQ_LEN_512 = 512, 618 CQ_LEN_1024 = 1024, 619 CQ_LEN_2048 = 2048 620}; 621 622struct cq_config { 623 enum cq_len q_len; 624 uint32_t item_size; 625 boolean_t is_eventable; 626 boolean_t sol_eventable; 627 boolean_t nodelay; 628 uint16_t dma_coalescing; 629}; 630 631typedef uint16_t(*cq_handler_t) (void *arg1); 632 633struct oce_cq { 634 uint32_t cq_id; 635 void *parent; 636 struct oce_eq *eq; 637 cq_handler_t cq_handler; 638 void *cb_arg; 639 oce_ring_buffer_t *ring; 640 qstate_t qstate; 641 struct cq_config cq_cfg; 642 uint32_t ref_count; 643}; 644 645 646struct mq_config { 647 uint32_t eqd; 648 uint8_t q_len; 649 uint8_t pad[3]; 650}; 651 652 653struct oce_mq { 654 void *parent; 655 oce_ring_buffer_t *ring; 656 uint32_t mq_id; 657 struct oce_cq *cq; 658 struct oce_cq *async_cq; 659 uint32_t mq_free; 660 qstate_t qstate; 661 struct mq_config cfg; 662}; 663 664struct oce_mbx_ctx { 665 struct oce_mbx *mbx; 666 void (*cb) (void *ctx); 667 void *cb_ctx; 668}; 669 670struct wq_config { 671 uint8_t wq_type; 672 uint16_t buf_size; 673 uint8_t pad[1]; 674 uint32_t q_len; 675 uint16_t pd_id; 676 uint16_t pci_fn_num; 677 uint32_t eqd; /* interrupt delay */ 678 uint32_t nbufs; 679 uint32_t nhdl; 680}; 681 682struct oce_tx_queue_stats { 683 uint64_t tx_pkts; 684 uint64_t tx_bytes; 685 uint32_t tx_reqs; 686 uint32_t tx_stops; /* number of times TX Q was stopped */ 687 uint32_t tx_wrbs; 688 uint32_t tx_compl; 689 uint32_t tx_rate; 690 uint32_t ipv6_ext_hdr_tx_drop; 691}; 692 693struct oce_wq { 694 OCE_LOCK tx_lock; 695 OCE_LOCK tx_compl_lock; 696 void *parent; 697 oce_ring_buffer_t *ring; 698 struct oce_cq *cq; 699 bus_dma_tag_t tag; 700 struct oce_packet_desc pckts[OCE_WQ_PACKET_ARRAY_SIZE]; 701 uint32_t pkt_desc_tail; 702 uint32_t pkt_desc_head; 703 uint32_t wqm_used; 704 boolean_t resched; 705 uint32_t wq_free; 706 uint32_t tx_deferd; 707 uint32_t pkt_drops; 708 qstate_t qstate; 709 uint16_t wq_id; 710 struct wq_config cfg; 711 int queue_index; 712 struct oce_tx_queue_stats tx_stats; 713 struct buf_ring *br; 714 struct task txtask; 715 uint32_t db_offset; 716}; 717 718struct rq_config { 719 uint32_t q_len; 720 uint32_t frag_size; 721 uint32_t mtu; 722 uint32_t if_id; 723 uint32_t is_rss_queue; 724 uint32_t eqd; 725 uint32_t nbufs; 726}; 727 728struct oce_rx_queue_stats { 729 uint32_t rx_post_fail; 730 uint32_t rx_ucast_pkts; 731 uint32_t rx_compl; 732 uint64_t rx_bytes; 733 uint64_t rx_bytes_prev; 734 uint64_t rx_pkts; 735 uint32_t rx_rate; 736 uint32_t rx_mcast_pkts; 737 uint32_t rxcp_err; 738 uint32_t rx_frags; 739 uint32_t prev_rx_frags; 740 uint32_t rx_fps; 741 uint32_t rx_drops_no_frags; /* HW has no fetched frags */ 742}; 743 744 745struct oce_rq { 746 struct rq_config cfg; 747 uint32_t rq_id; 748 int queue_index; 749 uint32_t rss_cpuid; 750 void *parent; 751 oce_ring_buffer_t *ring; 752 struct oce_cq *cq; 753 void *pad1; 754 bus_dma_tag_t tag; 755 struct oce_packet_desc pckts[OCE_RQ_PACKET_ARRAY_SIZE]; 756 uint32_t pending; 757#ifdef notdef 758 struct mbuf *head; 759 struct mbuf *tail; 760 int fragsleft; 761#endif 762 qstate_t qstate; 763 OCE_LOCK rx_lock; 764 struct oce_rx_queue_stats rx_stats; 765 struct lro_ctrl lro; 766 int lro_pkts_queued; 767 int islro; 768 struct nic_hwlro_cqe_part1 *cqe_firstpart; 769 770}; 771 772struct link_status { 773 uint8_t phys_port_speed; 774 uint8_t logical_link_status; 775 uint16_t qos_link_speed; 776}; 777 778 779 780#define OCE_FLAGS_PCIX 0x00000001 781#define OCE_FLAGS_PCIE 0x00000002 782#define OCE_FLAGS_MSI_CAPABLE 0x00000004 783#define OCE_FLAGS_MSIX_CAPABLE 0x00000008 784#define OCE_FLAGS_USING_MSI 0x00000010 785#define OCE_FLAGS_USING_MSIX 0x00000020 786#define OCE_FLAGS_FUNCRESET_RQD 0x00000040 787#define OCE_FLAGS_VIRTUAL_PORT 0x00000080 788#define OCE_FLAGS_MBOX_ENDIAN_RQD 0x00000100 789#define OCE_FLAGS_BE3 0x00000200 790#define OCE_FLAGS_XE201 0x00000400 791#define OCE_FLAGS_BE2 0x00000800 792#define OCE_FLAGS_SH 0x00001000 793#define OCE_FLAGS_OS2BMC 0x00002000 794 795#define OCE_DEV_BE2_CFG_BAR 1 796#define OCE_DEV_CFG_BAR 0 797#define OCE_PCI_CSR_BAR 2 798#define OCE_PCI_DB_BAR 4 799 800typedef struct oce_softc { 801 device_t dev; 802 OCE_LOCK dev_lock; 803 804 uint32_t flags; 805 806 uint32_t pcie_link_speed; 807 uint32_t pcie_link_width; 808 809 uint8_t fn; /* PCI function number */ 810 811 struct resource *devcfg_res; 812 bus_space_tag_t devcfg_btag; 813 bus_space_handle_t devcfg_bhandle; 814 void *devcfg_vhandle; 815 816 struct resource *csr_res; 817 bus_space_tag_t csr_btag; 818 bus_space_handle_t csr_bhandle; 819 void *csr_vhandle; 820 821 struct resource *db_res; 822 bus_space_tag_t db_btag; 823 bus_space_handle_t db_bhandle; 824 void *db_vhandle; 825 826 OCE_INTR_INFO intrs[OCE_MAX_EQ]; 827 int intr_count; 828 int roce_intr_count; 829 830 struct ifnet *ifp; 831 832 struct ifmedia media; 833 uint8_t link_status; 834 uint8_t link_speed; 835 uint8_t duplex; 836 uint32_t qos_link_speed; 837 uint32_t speed; 838 uint32_t enable_hwlro; 839 840 char fw_version[32]; 841 struct mac_address_format macaddr; 842 843 OCE_DMA_MEM bsmbx; 844 OCE_LOCK bmbx_lock; 845 846 uint32_t config_number; 847 uint32_t asic_revision; 848 uint32_t port_id; 849 uint32_t function_mode; 850 uint32_t function_caps; 851 uint32_t max_tx_rings; 852 uint32_t max_rx_rings; 853 854 struct oce_wq *wq[OCE_MAX_WQ]; /* TX work queues */ 855 struct oce_rq *rq[OCE_MAX_RQ]; /* RX work queues */ 856 struct oce_cq *cq[OCE_MAX_CQ]; /* Completion queues */ 857 struct oce_eq *eq[OCE_MAX_EQ]; /* Event queues */ 858 struct oce_mq *mq; /* Mailbox queue */ 859 860 uint32_t neqs; 861 uint32_t ncqs; 862 uint32_t nrqs; 863 uint32_t nwqs; 864 uint32_t nrssqs; 865 866 uint32_t tx_ring_size; 867 uint32_t rx_ring_size; 868 uint32_t rq_frag_size; 869 870 uint32_t if_id; /* interface ID */ 871 uint32_t nifs; /* number of adapter interfaces, 0 or 1 */ 872 uint32_t pmac_id; /* PMAC id */ 873 874 uint32_t if_cap_flags; 875 876 uint32_t flow_control; 877 uint8_t promisc; 878 879 struct oce_aic_obj aic_obj[OCE_MAX_EQ]; 880 881 /*Vlan Filtering related */ 882 eventhandler_tag vlan_attach; 883 eventhandler_tag vlan_detach; 884 uint16_t vlans_added; 885 uint8_t vlan_tag[MAX_VLANS]; 886 /*stats */ 887 OCE_DMA_MEM stats_mem; 888 struct oce_drv_stats oce_stats_info; 889 struct callout timer; 890 int8_t be3_native; 891 uint8_t hw_error; 892 uint16_t qnq_debug_event; 893 uint16_t qnqid; 894 uint32_t pvid; 895 uint32_t max_vlans; 896 uint32_t bmc_filt_mask; 897 898 void *rdma_context; 899 uint32_t rdma_flags; 900 struct oce_softc *next; 901 902} OCE_SOFTC, *POCE_SOFTC; 903 904#define OCE_RDMA_FLAG_SUPPORTED 0x00000001 905 906 907/************************************************** 908 * BUS memory read/write macros 909 * BE3: accesses three BAR spaces (CFG, CSR, DB) 910 * Lancer: accesses one BAR space (CFG) 911 **************************************************/ 912#define OCE_READ_CSR_MPU(sc, space, o) \ 913 ((IS_BE(sc)) ? (bus_space_read_4((sc)->space##_btag, \ 914 (sc)->space##_bhandle,o)) \ 915 : (bus_space_read_4((sc)->devcfg_btag, \ 916 (sc)->devcfg_bhandle,o))) 917#define OCE_READ_REG32(sc, space, o) \ 918 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_read_4((sc)->space##_btag, \ 919 (sc)->space##_bhandle,o)) \ 920 : (bus_space_read_4((sc)->devcfg_btag, \ 921 (sc)->devcfg_bhandle,o))) 922#define OCE_READ_REG16(sc, space, o) \ 923 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_read_2((sc)->space##_btag, \ 924 (sc)->space##_bhandle,o)) \ 925 : (bus_space_read_2((sc)->devcfg_btag, \ 926 (sc)->devcfg_bhandle,o))) 927#define OCE_READ_REG8(sc, space, o) \ 928 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_read_1((sc)->space##_btag, \ 929 (sc)->space##_bhandle,o)) \ 930 : (bus_space_read_1((sc)->devcfg_btag, \ 931 (sc)->devcfg_bhandle,o))) 932 933#define OCE_WRITE_CSR_MPU(sc, space, o, v) \ 934 ((IS_BE(sc)) ? (bus_space_write_4((sc)->space##_btag, \ 935 (sc)->space##_bhandle,o,v)) \ 936 : (bus_space_write_4((sc)->devcfg_btag, \ 937 (sc)->devcfg_bhandle,o,v))) 938#define OCE_WRITE_REG32(sc, space, o, v) \ 939 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_write_4((sc)->space##_btag, \ 940 (sc)->space##_bhandle,o,v)) \ 941 : (bus_space_write_4((sc)->devcfg_btag, \ 942 (sc)->devcfg_bhandle,o,v))) 943#define OCE_WRITE_REG16(sc, space, o, v) \ 944 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_write_2((sc)->space##_btag, \ 945 (sc)->space##_bhandle,o,v)) \ 946 : (bus_space_write_2((sc)->devcfg_btag, \ 947 (sc)->devcfg_bhandle,o,v))) 948#define OCE_WRITE_REG8(sc, space, o, v) \ 949 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_write_1((sc)->space##_btag, \ 950 (sc)->space##_bhandle,o,v)) \ 951 : (bus_space_write_1((sc)->devcfg_btag, \ 952 (sc)->devcfg_bhandle,o,v))) 953 954void oce_rx_flush_lro(struct oce_rq *rq); 955/*********************************************************** 956 * DMA memory functions 957 ***********************************************************/ 958#define oce_dma_sync(d, f) bus_dmamap_sync((d)->tag, (d)->map, f) 959int oce_dma_alloc(POCE_SOFTC sc, bus_size_t size, POCE_DMA_MEM dma, int flags); 960void oce_dma_free(POCE_SOFTC sc, POCE_DMA_MEM dma); 961void oce_dma_map_addr(void *arg, bus_dma_segment_t * segs, int nseg, int error); 962void oce_destroy_ring_buffer(POCE_SOFTC sc, oce_ring_buffer_t *ring); 963oce_ring_buffer_t *oce_create_ring_buffer(POCE_SOFTC sc, 964 uint32_t q_len, uint32_t num_entries); 965/************************************************************ 966 * oce_hw_xxx functions 967 ************************************************************/ 968int oce_clear_rx_buf(struct oce_rq *rq); 969int oce_hw_pci_alloc(POCE_SOFTC sc); 970int oce_hw_init(POCE_SOFTC sc); 971int oce_hw_start(POCE_SOFTC sc); 972int oce_create_nw_interface(POCE_SOFTC sc); 973int oce_pci_soft_reset(POCE_SOFTC sc); 974int oce_hw_update_multicast(POCE_SOFTC sc); 975void oce_delete_nw_interface(POCE_SOFTC sc); 976void oce_hw_shutdown(POCE_SOFTC sc); 977void oce_hw_intr_enable(POCE_SOFTC sc); 978void oce_hw_intr_disable(POCE_SOFTC sc); 979void oce_hw_pci_free(POCE_SOFTC sc); 980 981/*********************************************************** 982 * oce_queue_xxx functions 983 ***********************************************************/ 984int oce_queue_init_all(POCE_SOFTC sc); 985int oce_start_rq(struct oce_rq *rq); 986int oce_start_wq(struct oce_wq *wq); 987int oce_start_mq(struct oce_mq *mq); 988int oce_start_rx(POCE_SOFTC sc); 989void oce_arm_eq(POCE_SOFTC sc, 990 int16_t qid, int npopped, uint32_t rearm, uint32_t clearint); 991void oce_queue_release_all(POCE_SOFTC sc); 992void oce_arm_cq(POCE_SOFTC sc, int16_t qid, int npopped, uint32_t rearm); 993void oce_drain_eq(struct oce_eq *eq); 994void oce_drain_mq_cq(void *arg); 995void oce_drain_rq_cq(struct oce_rq *rq); 996void oce_drain_wq_cq(struct oce_wq *wq); 997 998uint32_t oce_page_list(oce_ring_buffer_t *ring, struct phys_addr *pa_list); 999 1000/*********************************************************** 1001 * cleanup functions 1002 ***********************************************************/ 1003void oce_stop_rx(POCE_SOFTC sc); 1004void oce_discard_rx_comp(struct oce_rq *rq, int num_frags); 1005void oce_rx_cq_clean(struct oce_rq *rq); 1006void oce_rx_cq_clean_hwlro(struct oce_rq *rq); 1007void oce_intr_free(POCE_SOFTC sc); 1008void oce_free_posted_rxbuf(struct oce_rq *rq); 1009#if defined(INET6) || defined(INET) 1010void oce_free_lro(POCE_SOFTC sc); 1011#endif 1012 1013 1014/************************************************************ 1015 * Mailbox functions 1016 ************************************************************/ 1017int oce_fw_clean(POCE_SOFTC sc); 1018int oce_wait_ready(POCE_SOFTC sc); 1019int oce_reset_fun(POCE_SOFTC sc); 1020int oce_mbox_init(POCE_SOFTC sc); 1021int oce_mbox_dispatch(POCE_SOFTC sc, uint32_t tmo_sec); 1022int oce_get_fw_version(POCE_SOFTC sc); 1023int oce_first_mcc_cmd(POCE_SOFTC sc); 1024 1025int oce_read_mac_addr(POCE_SOFTC sc, uint32_t if_id, uint8_t perm, 1026 uint8_t type, struct mac_address_format *mac); 1027int oce_get_fw_config(POCE_SOFTC sc); 1028int oce_if_create(POCE_SOFTC sc, uint32_t cap_flags, uint32_t en_flags, 1029 uint16_t vlan_tag, uint8_t *mac_addr, uint32_t *if_id); 1030int oce_if_del(POCE_SOFTC sc, uint32_t if_id); 1031int oce_config_vlan(POCE_SOFTC sc, uint32_t if_id, 1032 struct normal_vlan *vtag_arr, uint8_t vtag_cnt, 1033 uint32_t untagged, uint32_t enable_promisc); 1034int oce_set_flow_control(POCE_SOFTC sc, uint32_t flow_control); 1035int oce_config_nic_rss(POCE_SOFTC sc, uint32_t if_id, uint16_t enable_rss); 1036int oce_rxf_set_promiscuous(POCE_SOFTC sc, uint8_t enable); 1037int oce_set_common_iface_rx_filter(POCE_SOFTC sc, POCE_DMA_MEM sgl); 1038int oce_get_link_status(POCE_SOFTC sc, struct link_status *link); 1039int oce_mbox_get_nic_stats_v0(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem); 1040int oce_mbox_get_nic_stats_v1(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem); 1041int oce_mbox_get_nic_stats_v2(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem); 1042int oce_mbox_get_pport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem, 1043 uint32_t reset_stats); 1044int oce_mbox_get_vport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem, 1045 uint32_t req_size, uint32_t reset_stats); 1046int oce_update_multicast(POCE_SOFTC sc, POCE_DMA_MEM pdma_mem); 1047int oce_pass_through_mbox(POCE_SOFTC sc, POCE_DMA_MEM dma_mem, uint32_t req_size); 1048int oce_mbox_macaddr_del(POCE_SOFTC sc, uint32_t if_id, uint32_t pmac_id); 1049int oce_mbox_macaddr_add(POCE_SOFTC sc, uint8_t *mac_addr, 1050 uint32_t if_id, uint32_t *pmac_id); 1051int oce_mbox_cmd_test_loopback(POCE_SOFTC sc, uint32_t port_num, 1052 uint32_t loopback_type, uint32_t pkt_size, uint32_t num_pkts, 1053 uint64_t pattern); 1054 1055int oce_mbox_cmd_set_loopback(POCE_SOFTC sc, uint8_t port_num, 1056 uint8_t loopback_type, uint8_t enable); 1057 1058int oce_mbox_check_native_mode(POCE_SOFTC sc); 1059int oce_mbox_post(POCE_SOFTC sc, 1060 struct oce_mbx *mbx, struct oce_mbx_ctx *mbxctx); 1061int oce_mbox_write_flashrom(POCE_SOFTC sc, uint32_t optype,uint32_t opcode, 1062 POCE_DMA_MEM pdma_mem, uint32_t num_bytes); 1063int oce_mbox_lancer_write_flashrom(POCE_SOFTC sc, uint32_t data_size, 1064 uint32_t data_offset,POCE_DMA_MEM pdma_mem, 1065 uint32_t *written_data, uint32_t *additional_status); 1066 1067int oce_mbox_get_flashrom_crc(POCE_SOFTC sc, uint8_t *flash_crc, 1068 uint32_t offset, uint32_t optype); 1069int oce_mbox_get_phy_info(POCE_SOFTC sc, struct oce_phy_info *phy_info); 1070int oce_mbox_create_rq(struct oce_rq *rq); 1071int oce_mbox_create_wq(struct oce_wq *wq); 1072int oce_mbox_create_eq(struct oce_eq *eq); 1073int oce_mbox_cq_create(struct oce_cq *cq, uint32_t ncoalesce, 1074 uint32_t is_eventable); 1075int oce_mbox_read_transrecv_data(POCE_SOFTC sc, uint32_t page_num); 1076void oce_mbox_eqd_modify_periodic(POCE_SOFTC sc, struct oce_set_eqd *set_eqd, 1077 int num); 1078int oce_get_profile_config(POCE_SOFTC sc, uint32_t max_rss); 1079int oce_get_func_config(POCE_SOFTC sc); 1080void mbx_common_req_hdr_init(struct mbx_hdr *hdr, 1081 uint8_t dom, 1082 uint8_t port, 1083 uint8_t subsys, 1084 uint8_t opcode, 1085 uint32_t timeout, uint32_t pyld_len, 1086 uint8_t version); 1087 1088 1089uint16_t oce_mq_handler(void *arg); 1090 1091/************************************************************ 1092 * Transmit functions 1093 ************************************************************/ 1094uint16_t oce_wq_handler(void *arg); 1095void oce_start(struct ifnet *ifp); 1096void oce_tx_task(void *arg, int npending); 1097 1098/************************************************************ 1099 * Receive functions 1100 ************************************************************/ 1101int oce_alloc_rx_bufs(struct oce_rq *rq, int count); 1102uint16_t oce_rq_handler(void *arg); 1103 1104 1105/* Sysctl functions */ 1106void oce_add_sysctls(POCE_SOFTC sc); 1107void oce_refresh_queue_stats(POCE_SOFTC sc); 1108int oce_refresh_nic_stats(POCE_SOFTC sc); 1109int oce_stats_init(POCE_SOFTC sc); 1110void oce_stats_free(POCE_SOFTC sc); 1111 1112/* hw lro functions */ 1113int oce_mbox_nic_query_lro_capabilities(POCE_SOFTC sc, uint32_t *lro_rq_cnt, uint32_t *lro_flags); 1114int oce_mbox_nic_set_iface_lro_config(POCE_SOFTC sc, int enable); 1115int oce_mbox_create_rq_v2(struct oce_rq *rq); 1116 1117/* Capabilities */ 1118#define OCE_MODCAP_RSS 1 1119#define OCE_MAX_RSP_HANDLED 64 1120extern uint32_t oce_max_rsp_handled; /* max responses */ 1121extern uint32_t oce_rq_buf_size; 1122 1123#define OCE_MAC_LOOPBACK 0x0 1124#define OCE_PHY_LOOPBACK 0x1 1125#define OCE_ONE_PORT_EXT_LOOPBACK 0x2 1126#define OCE_NO_LOOPBACK 0xff 1127 1128#undef IFM_40G_SR4 1129#define IFM_40G_SR4 28 1130 1131#define atomic_inc_32(x) atomic_add_32(x, 1) 1132#define atomic_dec_32(x) atomic_subtract_32(x, 1) 1133 1134#define LE_64(x) htole64(x) 1135#define LE_32(x) htole32(x) 1136#define LE_16(x) htole16(x) 1137#define HOST_64(x) le64toh(x) 1138#define HOST_32(x) le32toh(x) 1139#define HOST_16(x) le16toh(x) 1140#define DW_SWAP(x, l) 1141#define IS_ALIGNED(x,a) ((x % a) == 0) 1142#define ADDR_HI(x) ((uint32_t)((uint64_t)(x) >> 32)) 1143#define ADDR_LO(x) ((uint32_t)((uint64_t)(x) & 0xffffffff)); 1144 1145#define IF_LRO_ENABLED(sc) (((sc)->ifp->if_capenable & IFCAP_LRO) ? 1:0) 1146#define IF_LSO_ENABLED(sc) (((sc)->ifp->if_capenable & IFCAP_TSO4) ? 1:0) 1147#define IF_CSUM_ENABLED(sc) (((sc)->ifp->if_capenable & IFCAP_HWCSUM) ? 1:0) 1148 1149#define OCE_LOG2(x) (oce_highbit(x)) 1150static inline uint32_t oce_highbit(uint32_t x) 1151{ 1152 int i; 1153 int c; 1154 int b; 1155 1156 c = 0; 1157 b = 0; 1158 1159 for (i = 0; i < 32; i++) { 1160 if ((1 << i) & x) { 1161 c++; 1162 b = i; 1163 } 1164 } 1165 1166 if (c == 1) 1167 return b; 1168 1169 return 0; 1170} 1171 1172static inline int MPU_EP_SEMAPHORE(POCE_SOFTC sc) 1173{ 1174 if (IS_BE(sc)) 1175 return MPU_EP_SEMAPHORE_BE3; 1176 else if (IS_SH(sc)) 1177 return MPU_EP_SEMAPHORE_SH; 1178 else 1179 return MPU_EP_SEMAPHORE_XE201; 1180} 1181 1182#define TRANSCEIVER_DATA_NUM_ELE 64 1183#define TRANSCEIVER_DATA_SIZE 256 1184#define TRANSCEIVER_A0_SIZE 128 1185#define TRANSCEIVER_A2_SIZE 128 1186#define PAGE_NUM_A0 0xa0 1187#define PAGE_NUM_A2 0xa2 1188#define IS_QNQ_OR_UMC(sc) ((sc->pvid && (sc->function_mode & FNM_UMC_MODE ))\ 1189 || (sc->qnqid && (sc->function_mode & FNM_FLEX10_MODE))) 1190extern uint8_t sfp_vpd_dump_buffer[TRANSCEIVER_DATA_SIZE]; 1191 1192struct oce_rdma_info; 1193extern struct oce_rdma_if *oce_rdma_if; 1194 1195 1196 1197/* OS2BMC related */ 1198 1199#define DHCP_CLIENT_PORT 68 1200#define DHCP_SERVER_PORT 67 1201#define NET_BIOS_PORT1 137 1202#define NET_BIOS_PORT2 138 1203#define DHCPV6_RAS_PORT 547 1204 1205#define BMC_FILT_BROADCAST_ARP ((uint32_t)(1)) 1206#define BMC_FILT_BROADCAST_DHCP_CLIENT ((uint32_t)(1 << 1)) 1207#define BMC_FILT_BROADCAST_DHCP_SERVER ((uint32_t)(1 << 2)) 1208#define BMC_FILT_BROADCAST_NET_BIOS ((uint32_t)(1 << 3)) 1209#define BMC_FILT_BROADCAST ((uint32_t)(1 << 4)) 1210#define BMC_FILT_MULTICAST_IPV6_NEIGH_ADVER ((uint32_t)(1 << 5)) 1211#define BMC_FILT_MULTICAST_IPV6_RA ((uint32_t)(1 << 6)) 1212#define BMC_FILT_MULTICAST_IPV6_RAS ((uint32_t)(1 << 7)) 1213#define BMC_FILT_MULTICAST ((uint32_t)(1 << 8)) 1214 1215#define ND_ROUTER_ADVERT 134 1216#define ND_NEIGHBOR_ADVERT 136 1217 1218#define is_mc_allowed_on_bmc(sc, eh) \ 1219 (!is_multicast_filt_enabled(sc) && \ 1220 ETHER_IS_MULTICAST(eh->ether_dhost) && \ 1221 !ETHER_IS_BROADCAST(eh->ether_dhost)) 1222 1223#define is_bc_allowed_on_bmc(sc, eh) \ 1224 (!is_broadcast_filt_enabled(sc) && \ 1225 ETHER_IS_BROADCAST(eh->ether_dhost)) 1226 1227#define is_arp_allowed_on_bmc(sc, et) \ 1228 (is_arp(et) && is_arp_filt_enabled(sc)) 1229 1230#define is_arp(et) (et == ETHERTYPE_ARP) 1231 1232#define is_arp_filt_enabled(sc) \ 1233 (sc->bmc_filt_mask & (BMC_FILT_BROADCAST_ARP)) 1234 1235#define is_dhcp_client_filt_enabled(sc) \ 1236 (sc->bmc_filt_mask & BMC_FILT_BROADCAST_DHCP_CLIENT) 1237 1238#define is_dhcp_srvr_filt_enabled(sc) \ 1239 (sc->bmc_filt_mask & BMC_FILT_BROADCAST_DHCP_SERVER) 1240 1241#define is_nbios_filt_enabled(sc) \ 1242 (sc->bmc_filt_mask & BMC_FILT_BROADCAST_NET_BIOS) 1243 1244#define is_ipv6_na_filt_enabled(sc) \ 1245 (sc->bmc_filt_mask & \ 1246 BMC_FILT_MULTICAST_IPV6_NEIGH_ADVER) 1247 1248#define is_ipv6_ra_filt_enabled(sc) \ 1249 (sc->bmc_filt_mask & BMC_FILT_MULTICAST_IPV6_RA) 1250 1251#define is_ipv6_ras_filt_enabled(sc) \ 1252 (sc->bmc_filt_mask & BMC_FILT_MULTICAST_IPV6_RAS) 1253 1254#define is_broadcast_filt_enabled(sc) \ 1255 (sc->bmc_filt_mask & BMC_FILT_BROADCAST) 1256 1257#define is_multicast_filt_enabled(sc) \ 1258 (sc->bmc_filt_mask & BMC_FILT_MULTICAST) 1259 1260#define is_os2bmc_enabled(sc) (sc->flags & OCE_FLAGS_OS2BMC) 1261 1262#define LRO_FLAGS_HASH_MODE 0x00000001 1263#define LRO_FLAGS_RSS_MODE 0x00000004 1264#define LRO_FLAGS_CLSC_IPV4 0x00000010 1265#define LRO_FLAGS_CLSC_IPV6 0x00000020 1266#define NIC_RQ_FLAGS_RSS 0x0001 1267#define NIC_RQ_FLAGS_LRO 0x0020 1268 1269