1/*	$FreeBSD$	*/
2/*	$NecBSD: nspreg.h,v 1.4.14.3 2001/06/29 06:27:53 honda Exp $	*/
3/*	$NetBSD$	*/
4
5/*-
6 * [NetBSD for NEC PC-98 series]
7 *  Copyright (c) 1998
8 *	NetBSD/pc98 porting staff. All rights reserved.
9 *
10 *  Redistribution and use in source and binary forms, with or without
11 *  modification, are permitted provided that the following conditions
12 *  are met:
13 *  1. Redistributions of source code must retain the above copyright
14 *     notice, this list of conditions and the following disclaimer.
15 *  2. Redistributions in binary form must reproduce the above copyright
16 *     notice, this list of conditions and the following disclaimer in the
17 *     documentation and/or other materials provided with the distribution.
18 *  3. The name of the author may not be used to endorse or promote products
19 *     derived from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
24 * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
29 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
30 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34#ifndef	_NSPREG_H_
35#define	_NSPREG_H_
36
37/* base registers */
38#define	nsp_irqcr	0
39#define	IRQCR_RESCL	0x01
40#define	IRQCR_PHCL	0x02
41#define	IRQCR_TIMERCL	0x04
42#define	IRQCR_FIFOCL	0x08
43#define	IRQCR_SCSIIDIS	0x10
44#define	IRQCR_EXTIDIS	0x20
45#define	IRQCR_TIMERIDIS	0x40
46#define	IRQCR_FIFOIDIS	0x80
47#define	IRQCR_ALLMASK	0xff
48#define	IRQCR_IRQDIS	0xf0
49
50#define	nsp_irqsr	0
51#define	IRQSR_SCSI	0x01
52#define	IRQSR_EXT	0x02
53#define	IRQSR_TIMER	0x04
54#define	IRQSR_FIFO	0x08
55#define	IRQSR_MASK	0x0f
56
57#define	nsp_ifselr	1
58#define	IFSELR_IFSEL	0x01
59#define	IFSELR_REGSEL	0x04
60
61#define	nsp_fifosr	1
62#define	FIFOSR_CHIPREVM	0x0f
63#define	FIFOSR_CHIPIDM	0x70
64#define	FIFOSR_FULLEMP	0x80
65
66#define	nsp_idxr	2
67#define	nsp_datar	3
68#define	nsp_fifodr	4
69
70/* indexed registers */
71#define	NSPR_EXTBUSC	0x10
72
73#define	NSPR_CLKDIVR	0x11
74#define	CLKDIVR_40M	0x02
75#define	CLKDIVR_20M	0x01
76
77#define	NSPR_TERMPWRC	0x13
78#define	TERMPWRC_POWON	0x01
79
80#define	NSPR_SCIENR	0x15
81#define	SCIENR_SCCHG	0x01
82#define	SCIENR_RESEL	0x10
83#define	SCIENR_FIFO	0x20
84#define	SCIENR_RST	0x40
85
86#define	NSPR_IRQPHS	0x16
87#define	IRQPHS_LMSG	0x01
88#define	IRQPHS_LIO	0x02
89#define	IRQPHS_LCD	0x04
90#define	IRQPHS_LBF	0x08
91#define	IRQPHS_PCHG	0x10
92#define	IRQPHS_RSEL	0x20
93#define	IRQPHS_FIFO	0x40
94#define	IRQPHS_RST	0x80
95#define	IRQPHS_PHMASK   (IRQPHS_LCD | IRQPHS_LMSG | IRQPHS_LIO)
96
97#define	NSPR_TIMERCNT	0x17
98
99#define NSPR_SCBUSCR	0x18
100#define	SCBUSCR_SEL	0x01
101#define	SCBUSCR_RST	0x02
102#define	SCBUSCR_DOUT	0x04
103#define	SCBUSCR_ATN	0x08
104#define	SCBUSCR_ACK	0x10
105#define	SCBUSCR_BSY	0x20
106#define	SCBUSCR_ADIR	0x40
107#define	SCBUSCR_ACKEN	0x80
108
109#define	NSPR_SCBUSMON	0x19
110#define	SCBUSMON_MSG	0x01
111#define	SCBUSMON_IO	0x02
112#define	SCBUSMON_CD	0x04
113#define	SCBUSMON_BSY	0x08
114#define	SCBUSMON_ACK	0x10
115#define	SCBUSMON_REQ	0x20
116#define	SCBUSMON_SEL	0x40
117#define SCBUSMON_ATN	0x80
118
119#define	NSPR_SETARBIT	0x1A
120
121#define	NSPR_ARBITS	0x1A
122#define	ARBITS_EXEC	0x01
123#define	ARBITS_CLR	0x02
124#define	ARBITS_WIN	0x02
125#define	ARBITS_FAIL	0x04
126#define	ARBITS_RESEL	0x08
127
128#define	NSPR_PARITYR	0x1B	/* (W/R) */
129#define	PARITYR_ENABLE	0x01
130#define	PARITYR_CLEAR	0x02
131#define	PARITYR_PE	0x02
132
133#define	NSPR_CMDCR	0x1C	/* (W) */
134#define	CMDCR_PTCLR	0x01
135#define	CMDCR_EXEC	0x02
136
137#define	NSPR_RESELR	0x1C	/* (R) */
138#define	NSPR_CMDDR	0x1D	/* (W/R) */
139
140#define	NSPR_PTCLRR	0x1E	/* (W) */
141#define	PTCLRR_PT	0x01
142#define	PTCLRR_ACK	0x02
143#define	PTCLRR_REQ	0x04
144#define	PTCLRR_HOST	0x08
145#define	PTCLRR_RSS	0x30
146#define	PTCLRR_RSS_ACK	0x00
147#define	PTCLRR_RSS_REQ	0x10
148#define	PTCLRR_RSS_HOST	0x20
149
150#define	NSPR_XFERCR	0x1E	/* (R) */
151
152#define	NSPR_XFERMR	0x20
153#define	XFERMR_MEM8	0x01
154#define	XFERMR_MEM32	0x02
155#define	XFERMR_ADR24	0x04
156#define	XFERMR_ADR32	0x08
157#define	XFERMR_IO8	0x10
158#define	XFERMR_IO32	0x20
159#define	XFERMR_XEN	0x40
160#define	XFERMR_FIFOEN	0x80
161
162#define	NSPR_SYNCR	0x21
163#define	SYNCR_OFFM	0x0f
164#define	SYNCR_PERM	0xf0
165#define	SYNCR_PERS	4
166
167#define	NSPR_DATA	0x22
168#define	NSPR_DATAACK	0x23
169#define	NSPR_OCR	0x26
170#define	OCR_ROMEN	0x01
171#define	OCR_TERMPWROUT	0x02
172#define	OCR_TERMPWRS	0x04
173
174#define NSPR_ACKWIDTH	0x27
175
176/* SCBUSMON phase defs */
177#define	SCBUSMON_FREE	0
178#define	SCBUSMON_CMD \
179	(SCBUSMON_BSY | SCBUSMON_CD | SCBUSMON_REQ)
180#define	SCBUSMON_MSGIN \
181	(SCBUSMON_BSY | SCBUSMON_MSG | SCBUSMON_IO | SCBUSMON_CD | SCBUSMON_REQ)
182#define	SCBUSMON_MSGOUT \
183	(SCBUSMON_BSY | SCBUSMON_MSG | SCBUSMON_CD | SCBUSMON_REQ)
184#define	SCBUSMON_DATAIN \
185	(SCBUSMON_BSY | SCBUSMON_IO | SCBUSMON_REQ)
186#define	SCBUSMON_DATAOUT \
187	(SCBUSMON_BSY | SCBUSMON_REQ)
188#define	SCBUSMON_STATUS \
189	(SCBUSMON_BSY | SCBUSMON_IO | SCBUSMON_CD | SCBUSMON_REQ)
190#define	SCBUSMON_RESELECT \
191	(SCBUSMON_SEL | SCBUSMON_IO)
192#define	SCBUSMON_PHMASK \
193	(SCBUSMON_SEL | SCBUSMON_CD | SCBUSMON_MSG | SCBUSMON_IO)
194
195/* Data phase */
196#define	NSP_IS_PHASE_DATA(ph) \
197	((((ph) & SCBUSMON_PHMASK) & ~SCBUSMON_IO) == 0)
198#define	NSP_IS_IRQPHS_DATA(ph) \
199	((((ph) & IRQPHS_PHMASK) & ~SCBUSMON_IO) == 0)
200
201/* SCSI phase */
202#define	PHASE_CMD	(SCBUSMON_CMD & SCBUSMON_PHMASK)
203#define	PHASE_DATAIN	(SCBUSMON_DATAIN & SCBUSMON_PHMASK)
204#define	PHASE_DATAOUT	(SCBUSMON_DATAOUT & SCBUSMON_PHMASK)
205#define	PHASE_STATUS	(SCBUSMON_STATUS & SCBUSMON_PHMASK)
206#define	PHASE_MSGIN	(SCBUSMON_MSGIN & SCBUSMON_PHMASK)
207#define	PHASE_MSGOUT	(SCBUSMON_MSGOUT & SCBUSMON_PHMASK)
208#define	PHASE_SEL	(SCBUSMON_SEL | SCBUSMON_IO)
209
210#define	IRQPHS_CMD	(IRQPHS_LCD)
211#define	IRQPHS_DATAIN	(IRQPHS_LIO)
212#define	IRQPHS_DATAOUT	(0)
213#define	IRQPHS_STATUS	(IRQPHS_LCD | IRQPHS_LIO)
214#define	IRQPHS_MSGIN	(IRQPHS_LCD | IRQPHS_LMSG | IRQPHS_LIO)
215#define	IRQPHS_MSGOUT	(IRQPHS_LCD | IRQPHS_LMSG)
216
217/* Size */
218#define	NSP_MEMSIZE	NBPG
219#define	NSP_IOSIZE	16
220#define	NSP_BUFFER_SIZE	512
221#endif	/* !_NSPREG_H_ */
222