if_nge.c revision 92739
1/* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2000, 2001 4 * Bill Paul <wpaul@bsdi.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: head/sys/dev/nge/if_nge.c 92739 2002-03-20 02:08:01Z alfred $ 34 */ 35 36/* 37 * National Semiconductor DP83820/DP83821 gigabit ethernet driver 38 * for FreeBSD. Datasheets are available from: 39 * 40 * http://www.national.com/ds/DP/DP83820.pdf 41 * http://www.national.com/ds/DP/DP83821.pdf 42 * 43 * These chips are used on several low cost gigabit ethernet NICs 44 * sold by D-Link, Addtron, SMC and Asante. Both parts are 45 * virtually the same, except the 83820 is a 64-bit/32-bit part, 46 * while the 83821 is 32-bit only. 47 * 48 * Many cards also use National gigE transceivers, such as the 49 * DP83891, DP83861 and DP83862 gigPHYTER parts. The DP83861 datasheet 50 * contains a full register description that applies to all of these 51 * components: 52 * 53 * http://www.national.com/ds/DP/DP83861.pdf 54 * 55 * Written by Bill Paul <wpaul@bsdi.com> 56 * BSDi Open Source Solutions 57 */ 58 59/* 60 * The NatSemi DP83820 and 83821 controllers are enhanced versions 61 * of the NatSemi MacPHYTER 10/100 devices. They support 10, 100 62 * and 1000Mbps speeds with 1000baseX (ten bit interface), MII and GMII 63 * ports. Other features include 8K TX FIFO and 32K RX FIFO, TCP/IP 64 * hardware checksum offload (IPv4 only), VLAN tagging and filtering, 65 * priority TX and RX queues, a 2048 bit multicast hash filter, 4 RX pattern 66 * matching buffers, one perfect address filter buffer and interrupt 67 * moderation. The 83820 supports both 64-bit and 32-bit addressing 68 * and data transfers: the 64-bit support can be toggled on or off 69 * via software. This affects the size of certain fields in the DMA 70 * descriptors. 71 * 72 * There are two bugs/misfeatures in the 83820/83821 that I have 73 * discovered so far: 74 * 75 * - Receive buffers must be aligned on 64-bit boundaries, which means 76 * you must resort to copying data in order to fix up the payload 77 * alignment. 78 * 79 * - In order to transmit jumbo frames larger than 8170 bytes, you have 80 * to turn off transmit checksum offloading, because the chip can't 81 * compute the checksum on an outgoing frame unless it fits entirely 82 * within the TX FIFO, which is only 8192 bytes in size. If you have 83 * TX checksum offload enabled and you transmit attempt to transmit a 84 * frame larger than 8170 bytes, the transmitter will wedge. 85 * 86 * To work around the latter problem, TX checksum offload is disabled 87 * if the user selects an MTU larger than 8152 (8170 - 18). 88 */ 89 90#include <sys/param.h> 91#include <sys/systm.h> 92#include <sys/sockio.h> 93#include <sys/mbuf.h> 94#include <sys/malloc.h> 95#include <sys/kernel.h> 96#include <sys/socket.h> 97 98#include <net/if.h> 99#include <net/if_arp.h> 100#include <net/ethernet.h> 101#include <net/if_dl.h> 102#include <net/if_media.h> 103#include <net/if_types.h> 104#include <net/if_vlan_var.h> 105 106#include <net/bpf.h> 107 108#include <vm/vm.h> /* for vtophys */ 109#include <vm/pmap.h> /* for vtophys */ 110#include <machine/clock.h> /* for DELAY */ 111#include <machine/bus_pio.h> 112#include <machine/bus_memio.h> 113#include <machine/bus.h> 114#include <machine/resource.h> 115#include <sys/bus.h> 116#include <sys/rman.h> 117 118#include <dev/mii/mii.h> 119#include <dev/mii/miivar.h> 120 121#include <pci/pcireg.h> 122#include <pci/pcivar.h> 123 124#define NGE_USEIOSPACE 125 126#include <dev/nge/if_ngereg.h> 127 128MODULE_DEPEND(nge, miibus, 1, 1, 1); 129 130/* "controller miibus0" required. See GENERIC if you get errors here. */ 131#include "miibus_if.h" 132 133#ifndef lint 134static const char rcsid[] = 135 "$FreeBSD: head/sys/dev/nge/if_nge.c 92739 2002-03-20 02:08:01Z alfred $"; 136#endif 137 138#define NGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 139 140/* 141 * Various supported device vendors/types and their names. 142 */ 143static struct nge_type nge_devs[] = { 144 { NGE_VENDORID, NGE_DEVICEID, 145 "National Semiconductor Gigabit Ethernet" }, 146 { 0, 0, NULL } 147}; 148 149static int nge_probe (device_t); 150static int nge_attach (device_t); 151static int nge_detach (device_t); 152 153static int nge_alloc_jumbo_mem (struct nge_softc *); 154static void nge_free_jumbo_mem (struct nge_softc *); 155static void *nge_jalloc (struct nge_softc *); 156static void nge_jfree (caddr_t, void *); 157 158static int nge_newbuf (struct nge_softc *, 159 struct nge_desc *, struct mbuf *); 160static int nge_encap (struct nge_softc *, 161 struct mbuf *, u_int32_t *); 162static void nge_rxeof (struct nge_softc *); 163#ifdef notdef 164static void nge_rxeoc (struct nge_softc *); 165#endif 166static void nge_txeof (struct nge_softc *); 167static void nge_intr (void *); 168static void nge_tick (void *); 169static void nge_start (struct ifnet *); 170static int nge_ioctl (struct ifnet *, u_long, caddr_t); 171static void nge_init (void *); 172static void nge_stop (struct nge_softc *); 173static void nge_watchdog (struct ifnet *); 174static void nge_shutdown (device_t); 175static int nge_ifmedia_upd (struct ifnet *); 176static void nge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 177 178static void nge_delay (struct nge_softc *); 179static void nge_eeprom_idle (struct nge_softc *); 180static void nge_eeprom_putbyte (struct nge_softc *, int); 181static void nge_eeprom_getword (struct nge_softc *, int, u_int16_t *); 182static void nge_read_eeprom (struct nge_softc *, caddr_t, int, int, int); 183 184static void nge_mii_sync (struct nge_softc *); 185static void nge_mii_send (struct nge_softc *, u_int32_t, int); 186static int nge_mii_readreg (struct nge_softc *, struct nge_mii_frame *); 187static int nge_mii_writereg (struct nge_softc *, struct nge_mii_frame *); 188 189static int nge_miibus_readreg (device_t, int, int); 190static int nge_miibus_writereg (device_t, int, int, int); 191static void nge_miibus_statchg (device_t); 192 193static void nge_setmulti (struct nge_softc *); 194static u_int32_t nge_crc (struct nge_softc *, caddr_t); 195static void nge_reset (struct nge_softc *); 196static int nge_list_rx_init (struct nge_softc *); 197static int nge_list_tx_init (struct nge_softc *); 198 199#ifdef NGE_USEIOSPACE 200#define NGE_RES SYS_RES_IOPORT 201#define NGE_RID NGE_PCI_LOIO 202#else 203#define NGE_RES SYS_RES_MEMORY 204#define NGE_RID NGE_PCI_LOMEM 205#endif 206 207static device_method_t nge_methods[] = { 208 /* Device interface */ 209 DEVMETHOD(device_probe, nge_probe), 210 DEVMETHOD(device_attach, nge_attach), 211 DEVMETHOD(device_detach, nge_detach), 212 DEVMETHOD(device_shutdown, nge_shutdown), 213 214 /* bus interface */ 215 DEVMETHOD(bus_print_child, bus_generic_print_child), 216 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 217 218 /* MII interface */ 219 DEVMETHOD(miibus_readreg, nge_miibus_readreg), 220 DEVMETHOD(miibus_writereg, nge_miibus_writereg), 221 DEVMETHOD(miibus_statchg, nge_miibus_statchg), 222 223 { 0, 0 } 224}; 225 226static driver_t nge_driver = { 227 "nge", 228 nge_methods, 229 sizeof(struct nge_softc) 230}; 231 232static devclass_t nge_devclass; 233 234DRIVER_MODULE(if_nge, pci, nge_driver, nge_devclass, 0, 0); 235DRIVER_MODULE(miibus, nge, miibus_driver, miibus_devclass, 0, 0); 236 237#define NGE_SETBIT(sc, reg, x) \ 238 CSR_WRITE_4(sc, reg, \ 239 CSR_READ_4(sc, reg) | (x)) 240 241#define NGE_CLRBIT(sc, reg, x) \ 242 CSR_WRITE_4(sc, reg, \ 243 CSR_READ_4(sc, reg) & ~(x)) 244 245#define SIO_SET(x) \ 246 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | x) 247 248#define SIO_CLR(x) \ 249 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~x) 250 251static void nge_delay(sc) 252 struct nge_softc *sc; 253{ 254 int idx; 255 256 for (idx = (300 / 33) + 1; idx > 0; idx--) 257 CSR_READ_4(sc, NGE_CSR); 258 259 return; 260} 261 262static void nge_eeprom_idle(sc) 263 struct nge_softc *sc; 264{ 265 register int i; 266 267 SIO_SET(NGE_MEAR_EE_CSEL); 268 nge_delay(sc); 269 SIO_SET(NGE_MEAR_EE_CLK); 270 nge_delay(sc); 271 272 for (i = 0; i < 25; i++) { 273 SIO_CLR(NGE_MEAR_EE_CLK); 274 nge_delay(sc); 275 SIO_SET(NGE_MEAR_EE_CLK); 276 nge_delay(sc); 277 } 278 279 SIO_CLR(NGE_MEAR_EE_CLK); 280 nge_delay(sc); 281 SIO_CLR(NGE_MEAR_EE_CSEL); 282 nge_delay(sc); 283 CSR_WRITE_4(sc, NGE_MEAR, 0x00000000); 284 285 return; 286} 287 288/* 289 * Send a read command and address to the EEPROM, check for ACK. 290 */ 291static void nge_eeprom_putbyte(sc, addr) 292 struct nge_softc *sc; 293 int addr; 294{ 295 register int d, i; 296 297 d = addr | NGE_EECMD_READ; 298 299 /* 300 * Feed in each bit and stobe the clock. 301 */ 302 for (i = 0x400; i; i >>= 1) { 303 if (d & i) { 304 SIO_SET(NGE_MEAR_EE_DIN); 305 } else { 306 SIO_CLR(NGE_MEAR_EE_DIN); 307 } 308 nge_delay(sc); 309 SIO_SET(NGE_MEAR_EE_CLK); 310 nge_delay(sc); 311 SIO_CLR(NGE_MEAR_EE_CLK); 312 nge_delay(sc); 313 } 314 315 return; 316} 317 318/* 319 * Read a word of data stored in the EEPROM at address 'addr.' 320 */ 321static void nge_eeprom_getword(sc, addr, dest) 322 struct nge_softc *sc; 323 int addr; 324 u_int16_t *dest; 325{ 326 register int i; 327 u_int16_t word = 0; 328 329 /* Force EEPROM to idle state. */ 330 nge_eeprom_idle(sc); 331 332 /* Enter EEPROM access mode. */ 333 nge_delay(sc); 334 SIO_CLR(NGE_MEAR_EE_CLK); 335 nge_delay(sc); 336 SIO_SET(NGE_MEAR_EE_CSEL); 337 nge_delay(sc); 338 339 /* 340 * Send address of word we want to read. 341 */ 342 nge_eeprom_putbyte(sc, addr); 343 344 /* 345 * Start reading bits from EEPROM. 346 */ 347 for (i = 0x8000; i; i >>= 1) { 348 SIO_SET(NGE_MEAR_EE_CLK); 349 nge_delay(sc); 350 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT) 351 word |= i; 352 nge_delay(sc); 353 SIO_CLR(NGE_MEAR_EE_CLK); 354 nge_delay(sc); 355 } 356 357 /* Turn off EEPROM access mode. */ 358 nge_eeprom_idle(sc); 359 360 *dest = word; 361 362 return; 363} 364 365/* 366 * Read a sequence of words from the EEPROM. 367 */ 368static void nge_read_eeprom(sc, dest, off, cnt, swap) 369 struct nge_softc *sc; 370 caddr_t dest; 371 int off; 372 int cnt; 373 int swap; 374{ 375 int i; 376 u_int16_t word = 0, *ptr; 377 378 for (i = 0; i < cnt; i++) { 379 nge_eeprom_getword(sc, off + i, &word); 380 ptr = (u_int16_t *)(dest + (i * 2)); 381 if (swap) 382 *ptr = ntohs(word); 383 else 384 *ptr = word; 385 } 386 387 return; 388} 389 390/* 391 * Sync the PHYs by setting data bit and strobing the clock 32 times. 392 */ 393static void nge_mii_sync(sc) 394 struct nge_softc *sc; 395{ 396 register int i; 397 398 SIO_SET(NGE_MEAR_MII_DIR|NGE_MEAR_MII_DATA); 399 400 for (i = 0; i < 32; i++) { 401 SIO_SET(NGE_MEAR_MII_CLK); 402 DELAY(1); 403 SIO_CLR(NGE_MEAR_MII_CLK); 404 DELAY(1); 405 } 406 407 return; 408} 409 410/* 411 * Clock a series of bits through the MII. 412 */ 413static void nge_mii_send(sc, bits, cnt) 414 struct nge_softc *sc; 415 u_int32_t bits; 416 int cnt; 417{ 418 int i; 419 420 SIO_CLR(NGE_MEAR_MII_CLK); 421 422 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 423 if (bits & i) { 424 SIO_SET(NGE_MEAR_MII_DATA); 425 } else { 426 SIO_CLR(NGE_MEAR_MII_DATA); 427 } 428 DELAY(1); 429 SIO_CLR(NGE_MEAR_MII_CLK); 430 DELAY(1); 431 SIO_SET(NGE_MEAR_MII_CLK); 432 } 433} 434 435/* 436 * Read an PHY register through the MII. 437 */ 438static int nge_mii_readreg(sc, frame) 439 struct nge_softc *sc; 440 struct nge_mii_frame *frame; 441 442{ 443 int i, ack, s; 444 445 s = splimp(); 446 447 /* 448 * Set up frame for RX. 449 */ 450 frame->mii_stdelim = NGE_MII_STARTDELIM; 451 frame->mii_opcode = NGE_MII_READOP; 452 frame->mii_turnaround = 0; 453 frame->mii_data = 0; 454 455 CSR_WRITE_4(sc, NGE_MEAR, 0); 456 457 /* 458 * Turn on data xmit. 459 */ 460 SIO_SET(NGE_MEAR_MII_DIR); 461 462 nge_mii_sync(sc); 463 464 /* 465 * Send command/address info. 466 */ 467 nge_mii_send(sc, frame->mii_stdelim, 2); 468 nge_mii_send(sc, frame->mii_opcode, 2); 469 nge_mii_send(sc, frame->mii_phyaddr, 5); 470 nge_mii_send(sc, frame->mii_regaddr, 5); 471 472 /* Idle bit */ 473 SIO_CLR((NGE_MEAR_MII_CLK|NGE_MEAR_MII_DATA)); 474 DELAY(1); 475 SIO_SET(NGE_MEAR_MII_CLK); 476 DELAY(1); 477 478 /* Turn off xmit. */ 479 SIO_CLR(NGE_MEAR_MII_DIR); 480 /* Check for ack */ 481 SIO_CLR(NGE_MEAR_MII_CLK); 482 DELAY(1); 483 SIO_SET(NGE_MEAR_MII_CLK); 484 DELAY(1); 485 ack = CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA; 486 487 /* 488 * Now try reading data bits. If the ack failed, we still 489 * need to clock through 16 cycles to keep the PHY(s) in sync. 490 */ 491 if (ack) { 492 for(i = 0; i < 16; i++) { 493 SIO_CLR(NGE_MEAR_MII_CLK); 494 DELAY(1); 495 SIO_SET(NGE_MEAR_MII_CLK); 496 DELAY(1); 497 } 498 goto fail; 499 } 500 501 for (i = 0x8000; i; i >>= 1) { 502 SIO_CLR(NGE_MEAR_MII_CLK); 503 DELAY(1); 504 if (!ack) { 505 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA) 506 frame->mii_data |= i; 507 DELAY(1); 508 } 509 SIO_SET(NGE_MEAR_MII_CLK); 510 DELAY(1); 511 } 512 513fail: 514 515 SIO_CLR(NGE_MEAR_MII_CLK); 516 DELAY(1); 517 SIO_SET(NGE_MEAR_MII_CLK); 518 DELAY(1); 519 520 splx(s); 521 522 if (ack) 523 return(1); 524 return(0); 525} 526 527/* 528 * Write to a PHY register through the MII. 529 */ 530static int nge_mii_writereg(sc, frame) 531 struct nge_softc *sc; 532 struct nge_mii_frame *frame; 533 534{ 535 int s; 536 537 s = splimp(); 538 /* 539 * Set up frame for TX. 540 */ 541 542 frame->mii_stdelim = NGE_MII_STARTDELIM; 543 frame->mii_opcode = NGE_MII_WRITEOP; 544 frame->mii_turnaround = NGE_MII_TURNAROUND; 545 546 /* 547 * Turn on data output. 548 */ 549 SIO_SET(NGE_MEAR_MII_DIR); 550 551 nge_mii_sync(sc); 552 553 nge_mii_send(sc, frame->mii_stdelim, 2); 554 nge_mii_send(sc, frame->mii_opcode, 2); 555 nge_mii_send(sc, frame->mii_phyaddr, 5); 556 nge_mii_send(sc, frame->mii_regaddr, 5); 557 nge_mii_send(sc, frame->mii_turnaround, 2); 558 nge_mii_send(sc, frame->mii_data, 16); 559 560 /* Idle bit. */ 561 SIO_SET(NGE_MEAR_MII_CLK); 562 DELAY(1); 563 SIO_CLR(NGE_MEAR_MII_CLK); 564 DELAY(1); 565 566 /* 567 * Turn off xmit. 568 */ 569 SIO_CLR(NGE_MEAR_MII_DIR); 570 571 splx(s); 572 573 return(0); 574} 575 576static int nge_miibus_readreg(dev, phy, reg) 577 device_t dev; 578 int phy, reg; 579{ 580 struct nge_softc *sc; 581 struct nge_mii_frame frame; 582 583 sc = device_get_softc(dev); 584 585 bzero((char *)&frame, sizeof(frame)); 586 587 frame.mii_phyaddr = phy; 588 frame.mii_regaddr = reg; 589 nge_mii_readreg(sc, &frame); 590 591 return(frame.mii_data); 592} 593 594static int nge_miibus_writereg(dev, phy, reg, data) 595 device_t dev; 596 int phy, reg, data; 597{ 598 struct nge_softc *sc; 599 struct nge_mii_frame frame; 600 601 sc = device_get_softc(dev); 602 603 bzero((char *)&frame, sizeof(frame)); 604 605 frame.mii_phyaddr = phy; 606 frame.mii_regaddr = reg; 607 frame.mii_data = data; 608 nge_mii_writereg(sc, &frame); 609 610 return(0); 611} 612 613static void nge_miibus_statchg(dev) 614 device_t dev; 615{ 616 struct nge_softc *sc; 617 struct mii_data *mii; 618 619 sc = device_get_softc(dev); 620 mii = device_get_softc(sc->nge_miibus); 621 622 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 623 NGE_SETBIT(sc, NGE_TX_CFG, 624 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 625 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 626 } else { 627 NGE_CLRBIT(sc, NGE_TX_CFG, 628 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 629 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 630 } 631 632 /* If we have a 1000Mbps link, set the mode_1000 bit. */ 633 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX || 634 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) { 635 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_MODE_1000); 636 } else { 637 NGE_CLRBIT(sc, NGE_CFG, NGE_CFG_MODE_1000); 638 } 639 640 return; 641} 642 643static u_int32_t nge_crc(sc, addr) 644 struct nge_softc *sc; 645 caddr_t addr; 646{ 647 u_int32_t crc, carry; 648 int i, j; 649 u_int8_t c; 650 651 /* Compute CRC for the address value. */ 652 crc = 0xFFFFFFFF; /* initial value */ 653 654 for (i = 0; i < 6; i++) { 655 c = *(addr + i); 656 for (j = 0; j < 8; j++) { 657 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 658 crc <<= 1; 659 c >>= 1; 660 if (carry) 661 crc = (crc ^ 0x04c11db6) | carry; 662 } 663 } 664 665 /* 666 * return the filter bit position 667 */ 668 669 return((crc >> 21) & 0x00000FFF); 670} 671 672static void nge_setmulti(sc) 673 struct nge_softc *sc; 674{ 675 struct ifnet *ifp; 676 struct ifmultiaddr *ifma; 677 u_int32_t h = 0, i, filtsave; 678 int bit, index; 679 680 ifp = &sc->arpcom.ac_if; 681 682 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 683 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 684 NGE_RXFILTCTL_MCHASH|NGE_RXFILTCTL_UCHASH); 685 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLMULTI); 686 return; 687 } 688 689 /* 690 * We have to explicitly enable the multicast hash table 691 * on the NatSemi chip if we want to use it, which we do. 692 * We also have to tell it that we don't want to use the 693 * hash table for matching unicast addresses. 694 */ 695 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_MCHASH); 696 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 697 NGE_RXFILTCTL_ALLMULTI|NGE_RXFILTCTL_UCHASH); 698 699 filtsave = CSR_READ_4(sc, NGE_RXFILT_CTL); 700 701 /* first, zot all the existing hash bits */ 702 for (i = 0; i < NGE_MCAST_FILTER_LEN; i += 2) { 703 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + i); 704 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 0); 705 } 706 707 /* 708 * From the 11 bits returned by the crc routine, the top 7 709 * bits represent the 16-bit word in the mcast hash table 710 * that needs to be updated, and the lower 4 bits represent 711 * which bit within that byte needs to be set. 712 */ 713 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 714 if (ifma->ifma_addr->sa_family != AF_LINK) 715 continue; 716 h = nge_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 717 index = (h >> 4) & 0x7F; 718 bit = h & 0xF; 719 CSR_WRITE_4(sc, NGE_RXFILT_CTL, 720 NGE_FILTADDR_MCAST_LO + (index * 2)); 721 NGE_SETBIT(sc, NGE_RXFILT_DATA, (1 << bit)); 722 } 723 724 CSR_WRITE_4(sc, NGE_RXFILT_CTL, filtsave); 725 726 return; 727} 728 729static void nge_reset(sc) 730 struct nge_softc *sc; 731{ 732 register int i; 733 734 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RESET); 735 736 for (i = 0; i < NGE_TIMEOUT; i++) { 737 if (!(CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET)) 738 break; 739 } 740 741 if (i == NGE_TIMEOUT) 742 printf("nge%d: reset never completed\n", sc->nge_unit); 743 744 /* Wait a little while for the chip to get its brains in order. */ 745 DELAY(1000); 746 747 /* 748 * If this is a NetSemi chip, make sure to clear 749 * PME mode. 750 */ 751 CSR_WRITE_4(sc, NGE_CLKRUN, NGE_CLKRUN_PMESTS); 752 CSR_WRITE_4(sc, NGE_CLKRUN, 0); 753 754 return; 755} 756 757/* 758 * Probe for an NatSemi chip. Check the PCI vendor and device 759 * IDs against our list and return a device name if we find a match. 760 */ 761static int nge_probe(dev) 762 device_t dev; 763{ 764 struct nge_type *t; 765 766 t = nge_devs; 767 768 while(t->nge_name != NULL) { 769 if ((pci_get_vendor(dev) == t->nge_vid) && 770 (pci_get_device(dev) == t->nge_did)) { 771 device_set_desc(dev, t->nge_name); 772 return(0); 773 } 774 t++; 775 } 776 777 return(ENXIO); 778} 779 780/* 781 * Attach the interface. Allocate softc structures, do ifmedia 782 * setup and ethernet/BPF attach. 783 */ 784static int nge_attach(dev) 785 device_t dev; 786{ 787 int s; 788 u_char eaddr[ETHER_ADDR_LEN]; 789 u_int32_t command; 790 struct nge_softc *sc; 791 struct ifnet *ifp; 792 int unit, error = 0, rid; 793 794 s = splimp(); 795 796 sc = device_get_softc(dev); 797 unit = device_get_unit(dev); 798 bzero(sc, sizeof(struct nge_softc)); 799 800 mtx_init(&sc->nge_mtx, device_get_nameunit(dev), MTX_DEF|MTX_RECURSE); 801 802 /* 803 * Handle power management nonsense. 804 */ 805 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 806 u_int32_t iobase, membase, irq; 807 808 /* Save important PCI config data. */ 809 iobase = pci_read_config(dev, NGE_PCI_LOIO, 4); 810 membase = pci_read_config(dev, NGE_PCI_LOMEM, 4); 811 irq = pci_read_config(dev, NGE_PCI_INTLINE, 4); 812 813 /* Reset the power state. */ 814 printf("nge%d: chip is in D%d power mode " 815 "-- setting to D0\n", unit, 816 pci_get_powerstate(dev)); 817 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 818 819 /* Restore PCI config data. */ 820 pci_write_config(dev, NGE_PCI_LOIO, iobase, 4); 821 pci_write_config(dev, NGE_PCI_LOMEM, membase, 4); 822 pci_write_config(dev, NGE_PCI_INTLINE, irq, 4); 823 } 824 825 /* 826 * Map control/status registers. 827 */ 828 pci_enable_busmaster(dev); 829 pci_enable_io(dev, SYS_RES_IOPORT); 830 pci_enable_io(dev, SYS_RES_MEMORY); 831 command = pci_read_config(dev, PCIR_COMMAND, 4); 832 833#ifdef NGE_USEIOSPACE 834 if (!(command & PCIM_CMD_PORTEN)) { 835 printf("nge%d: failed to enable I/O ports!\n", unit); 836 error = ENXIO;; 837 goto fail; 838 } 839#else 840 if (!(command & PCIM_CMD_MEMEN)) { 841 printf("nge%d: failed to enable memory mapping!\n", unit); 842 error = ENXIO;; 843 goto fail; 844 } 845#endif 846 847 rid = NGE_RID; 848 sc->nge_res = bus_alloc_resource(dev, NGE_RES, &rid, 849 0, ~0, 1, RF_ACTIVE); 850 851 if (sc->nge_res == NULL) { 852 printf("nge%d: couldn't map ports/memory\n", unit); 853 error = ENXIO; 854 goto fail; 855 } 856 857 sc->nge_btag = rman_get_bustag(sc->nge_res); 858 sc->nge_bhandle = rman_get_bushandle(sc->nge_res); 859 860 /* Allocate interrupt */ 861 rid = 0; 862 sc->nge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 863 RF_SHAREABLE | RF_ACTIVE); 864 865 if (sc->nge_irq == NULL) { 866 printf("nge%d: couldn't map interrupt\n", unit); 867 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 868 error = ENXIO; 869 goto fail; 870 } 871 872 error = bus_setup_intr(dev, sc->nge_irq, INTR_TYPE_NET, 873 nge_intr, sc, &sc->nge_intrhand); 874 875 if (error) { 876 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 877 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 878 printf("nge%d: couldn't set up irq\n", unit); 879 goto fail; 880 } 881 882 /* Reset the adapter. */ 883 nge_reset(sc); 884 885 /* 886 * Get station address from the EEPROM. 887 */ 888 nge_read_eeprom(sc, (caddr_t)&eaddr[4], NGE_EE_NODEADDR, 1, 0); 889 nge_read_eeprom(sc, (caddr_t)&eaddr[2], NGE_EE_NODEADDR + 1, 1, 0); 890 nge_read_eeprom(sc, (caddr_t)&eaddr[0], NGE_EE_NODEADDR + 2, 1, 0); 891 892 /* 893 * A NatSemi chip was detected. Inform the world. 894 */ 895 printf("nge%d: Ethernet address: %6D\n", unit, eaddr, ":"); 896 897 sc->nge_unit = unit; 898 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 899 900 sc->nge_ldata = contigmalloc(sizeof(struct nge_list_data), M_DEVBUF, 901 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 902 903 if (sc->nge_ldata == NULL) { 904 printf("nge%d: no memory for list buffers!\n", unit); 905 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 906 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 907 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 908 error = ENXIO; 909 goto fail; 910 } 911 bzero(sc->nge_ldata, sizeof(struct nge_list_data)); 912 913 /* Try to allocate memory for jumbo buffers. */ 914 if (nge_alloc_jumbo_mem(sc)) { 915 printf("nge%d: jumbo buffer allocation failed\n", 916 sc->nge_unit); 917 contigfree(sc->nge_ldata, 918 sizeof(struct nge_list_data), M_DEVBUF); 919 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 920 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 921 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 922 error = ENXIO; 923 goto fail; 924 } 925 926 ifp = &sc->arpcom.ac_if; 927 ifp->if_softc = sc; 928 ifp->if_unit = unit; 929 ifp->if_name = "nge"; 930 ifp->if_mtu = ETHERMTU; 931 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 932 ifp->if_ioctl = nge_ioctl; 933 ifp->if_output = ether_output; 934 ifp->if_start = nge_start; 935 ifp->if_watchdog = nge_watchdog; 936 ifp->if_init = nge_init; 937 ifp->if_baudrate = 1000000000; 938 ifp->if_snd.ifq_maxlen = NGE_TX_LIST_CNT - 1; 939 ifp->if_hwassist = NGE_CSUM_FEATURES; 940 ifp->if_capabilities = IFCAP_HWCSUM; 941 ifp->if_capenable = ifp->if_capabilities; 942 943 /* 944 * Do MII setup. 945 */ 946 if (mii_phy_probe(dev, &sc->nge_miibus, 947 nge_ifmedia_upd, nge_ifmedia_sts)) { 948 printf("nge%d: MII without any PHY!\n", sc->nge_unit); 949 nge_free_jumbo_mem(sc); 950 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 951 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 952 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 953 error = ENXIO; 954 goto fail; 955 } 956 957 /* 958 * Call MI attach routine. 959 */ 960 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 961 callout_handle_init(&sc->nge_stat_ch); 962 963fail: 964 splx(s); 965 mtx_destroy(&sc->nge_mtx); 966 return(error); 967} 968 969static int nge_detach(dev) 970 device_t dev; 971{ 972 struct nge_softc *sc; 973 struct ifnet *ifp; 974 int s; 975 976 s = splimp(); 977 978 sc = device_get_softc(dev); 979 ifp = &sc->arpcom.ac_if; 980 981 nge_reset(sc); 982 nge_stop(sc); 983 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 984 985 bus_generic_detach(dev); 986 device_delete_child(dev, sc->nge_miibus); 987 988 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 989 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 990 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 991 992 contigfree(sc->nge_ldata, sizeof(struct nge_list_data), M_DEVBUF); 993 nge_free_jumbo_mem(sc); 994 995 splx(s); 996 mtx_destroy(&sc->nge_mtx); 997 998 return(0); 999} 1000 1001/* 1002 * Initialize the transmit descriptors. 1003 */ 1004static int nge_list_tx_init(sc) 1005 struct nge_softc *sc; 1006{ 1007 struct nge_list_data *ld; 1008 struct nge_ring_data *cd; 1009 int i; 1010 1011 cd = &sc->nge_cdata; 1012 ld = sc->nge_ldata; 1013 1014 for (i = 0; i < NGE_TX_LIST_CNT; i++) { 1015 if (i == (NGE_TX_LIST_CNT - 1)) { 1016 ld->nge_tx_list[i].nge_nextdesc = 1017 &ld->nge_tx_list[0]; 1018 ld->nge_tx_list[i].nge_next = 1019 vtophys(&ld->nge_tx_list[0]); 1020 } else { 1021 ld->nge_tx_list[i].nge_nextdesc = 1022 &ld->nge_tx_list[i + 1]; 1023 ld->nge_tx_list[i].nge_next = 1024 vtophys(&ld->nge_tx_list[i + 1]); 1025 } 1026 ld->nge_tx_list[i].nge_mbuf = NULL; 1027 ld->nge_tx_list[i].nge_ptr = 0; 1028 ld->nge_tx_list[i].nge_ctl = 0; 1029 } 1030 1031 cd->nge_tx_prod = cd->nge_tx_cons = cd->nge_tx_cnt = 0; 1032 1033 return(0); 1034} 1035 1036 1037/* 1038 * Initialize the RX descriptors and allocate mbufs for them. Note that 1039 * we arrange the descriptors in a closed ring, so that the last descriptor 1040 * points back to the first. 1041 */ 1042static int nge_list_rx_init(sc) 1043 struct nge_softc *sc; 1044{ 1045 struct nge_list_data *ld; 1046 struct nge_ring_data *cd; 1047 int i; 1048 1049 ld = sc->nge_ldata; 1050 cd = &sc->nge_cdata; 1051 1052 for (i = 0; i < NGE_RX_LIST_CNT; i++) { 1053 if (nge_newbuf(sc, &ld->nge_rx_list[i], NULL) == ENOBUFS) 1054 return(ENOBUFS); 1055 if (i == (NGE_RX_LIST_CNT - 1)) { 1056 ld->nge_rx_list[i].nge_nextdesc = 1057 &ld->nge_rx_list[0]; 1058 ld->nge_rx_list[i].nge_next = 1059 vtophys(&ld->nge_rx_list[0]); 1060 } else { 1061 ld->nge_rx_list[i].nge_nextdesc = 1062 &ld->nge_rx_list[i + 1]; 1063 ld->nge_rx_list[i].nge_next = 1064 vtophys(&ld->nge_rx_list[i + 1]); 1065 } 1066 } 1067 1068 cd->nge_rx_prod = 0; 1069 1070 return(0); 1071} 1072 1073/* 1074 * Initialize an RX descriptor and attach an MBUF cluster. 1075 */ 1076static int nge_newbuf(sc, c, m) 1077 struct nge_softc *sc; 1078 struct nge_desc *c; 1079 struct mbuf *m; 1080{ 1081 struct mbuf *m_new = NULL; 1082 caddr_t *buf = NULL; 1083 1084 if (m == NULL) { 1085 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1086 if (m_new == NULL) { 1087 printf("nge%d: no memory for rx list " 1088 "-- packet dropped!\n", sc->nge_unit); 1089 return(ENOBUFS); 1090 } 1091 1092 /* Allocate the jumbo buffer */ 1093 buf = nge_jalloc(sc); 1094 if (buf == NULL) { 1095#ifdef NGE_VERBOSE 1096 printf("nge%d: jumbo allocation failed " 1097 "-- packet dropped!\n", sc->nge_unit); 1098#endif 1099 m_freem(m_new); 1100 return(ENOBUFS); 1101 } 1102 /* Attach the buffer to the mbuf */ 1103 m_new->m_data = (void *)buf; 1104 m_new->m_len = m_new->m_pkthdr.len = NGE_JUMBO_FRAMELEN; 1105 MEXTADD(m_new, buf, NGE_JUMBO_FRAMELEN, nge_jfree, 1106 (struct nge_softc *)sc, 0, EXT_NET_DRV); 1107 } else { 1108 m_new = m; 1109 m_new->m_len = m_new->m_pkthdr.len = NGE_JUMBO_FRAMELEN; 1110 m_new->m_data = m_new->m_ext.ext_buf; 1111 } 1112 1113 m_adj(m_new, sizeof(u_int64_t)); 1114 1115 c->nge_mbuf = m_new; 1116 c->nge_ptr = vtophys(mtod(m_new, caddr_t)); 1117 c->nge_ctl = m_new->m_len; 1118 c->nge_extsts = 0; 1119 1120 return(0); 1121} 1122 1123static int nge_alloc_jumbo_mem(sc) 1124 struct nge_softc *sc; 1125{ 1126 caddr_t ptr; 1127 register int i; 1128 struct nge_jpool_entry *entry; 1129 1130 /* Grab a big chunk o' storage. */ 1131 sc->nge_cdata.nge_jumbo_buf = contigmalloc(NGE_JMEM, M_DEVBUF, 1132 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1133 1134 if (sc->nge_cdata.nge_jumbo_buf == NULL) { 1135 printf("nge%d: no memory for jumbo buffers!\n", sc->nge_unit); 1136 return(ENOBUFS); 1137 } 1138 1139 SLIST_INIT(&sc->nge_jfree_listhead); 1140 SLIST_INIT(&sc->nge_jinuse_listhead); 1141 1142 /* 1143 * Now divide it up into 9K pieces and save the addresses 1144 * in an array. 1145 */ 1146 ptr = sc->nge_cdata.nge_jumbo_buf; 1147 for (i = 0; i < NGE_JSLOTS; i++) { 1148 sc->nge_cdata.nge_jslots[i] = ptr; 1149 ptr += NGE_JLEN; 1150 entry = malloc(sizeof(struct nge_jpool_entry), 1151 M_DEVBUF, M_NOWAIT); 1152 if (entry == NULL) { 1153 printf("nge%d: no memory for jumbo " 1154 "buffer queue!\n", sc->nge_unit); 1155 return(ENOBUFS); 1156 } 1157 entry->slot = i; 1158 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead, 1159 entry, jpool_entries); 1160 } 1161 1162 return(0); 1163} 1164 1165static void nge_free_jumbo_mem(sc) 1166 struct nge_softc *sc; 1167{ 1168 register int i; 1169 struct nge_jpool_entry *entry; 1170 1171 for (i = 0; i < NGE_JSLOTS; i++) { 1172 entry = SLIST_FIRST(&sc->nge_jfree_listhead); 1173 SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jpool_entries); 1174 free(entry, M_DEVBUF); 1175 } 1176 1177 contigfree(sc->nge_cdata.nge_jumbo_buf, NGE_JMEM, M_DEVBUF); 1178 1179 return; 1180} 1181 1182/* 1183 * Allocate a jumbo buffer. 1184 */ 1185static void *nge_jalloc(sc) 1186 struct nge_softc *sc; 1187{ 1188 struct nge_jpool_entry *entry; 1189 1190 entry = SLIST_FIRST(&sc->nge_jfree_listhead); 1191 1192 if (entry == NULL) { 1193#ifdef NGE_VERBOSE 1194 printf("nge%d: no free jumbo buffers\n", sc->nge_unit); 1195#endif 1196 return(NULL); 1197 } 1198 1199 SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jpool_entries); 1200 SLIST_INSERT_HEAD(&sc->nge_jinuse_listhead, entry, jpool_entries); 1201 return(sc->nge_cdata.nge_jslots[entry->slot]); 1202} 1203 1204/* 1205 * Release a jumbo buffer. 1206 */ 1207static void nge_jfree(buf, args) 1208 caddr_t buf; 1209 void *args; 1210{ 1211 struct nge_softc *sc; 1212 int i; 1213 struct nge_jpool_entry *entry; 1214 1215 /* Extract the softc struct pointer. */ 1216 sc = args; 1217 1218 if (sc == NULL) 1219 panic("nge_jfree: can't find softc pointer!"); 1220 1221 /* calculate the slot this buffer belongs to */ 1222 i = ((vm_offset_t)buf 1223 - (vm_offset_t)sc->nge_cdata.nge_jumbo_buf) / NGE_JLEN; 1224 1225 if ((i < 0) || (i >= NGE_JSLOTS)) 1226 panic("nge_jfree: asked to free buffer that we don't manage!"); 1227 1228 entry = SLIST_FIRST(&sc->nge_jinuse_listhead); 1229 if (entry == NULL) 1230 panic("nge_jfree: buffer not in use!"); 1231 entry->slot = i; 1232 SLIST_REMOVE_HEAD(&sc->nge_jinuse_listhead, jpool_entries); 1233 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead, entry, jpool_entries); 1234 1235 return; 1236} 1237/* 1238 * A frame has been uploaded: pass the resulting mbuf chain up to 1239 * the higher level protocols. 1240 */ 1241static void nge_rxeof(sc) 1242 struct nge_softc *sc; 1243{ 1244 struct ether_header *eh; 1245 struct mbuf *m; 1246 struct ifnet *ifp; 1247 struct nge_desc *cur_rx; 1248 int i, total_len = 0; 1249 u_int32_t rxstat; 1250 1251 ifp = &sc->arpcom.ac_if; 1252 i = sc->nge_cdata.nge_rx_prod; 1253 1254 while(NGE_OWNDESC(&sc->nge_ldata->nge_rx_list[i])) { 1255 struct mbuf *m0 = NULL; 1256 u_int32_t extsts; 1257 1258 cur_rx = &sc->nge_ldata->nge_rx_list[i]; 1259 rxstat = cur_rx->nge_rxstat; 1260 extsts = cur_rx->nge_extsts; 1261 m = cur_rx->nge_mbuf; 1262 cur_rx->nge_mbuf = NULL; 1263 total_len = NGE_RXBYTES(cur_rx); 1264 NGE_INC(i, NGE_RX_LIST_CNT); 1265 1266 /* 1267 * If an error occurs, update stats, clear the 1268 * status word and leave the mbuf cluster in place: 1269 * it should simply get re-used next time this descriptor 1270 * comes up in the ring. 1271 */ 1272 if (!(rxstat & NGE_CMDSTS_PKT_OK)) { 1273 ifp->if_ierrors++; 1274 nge_newbuf(sc, cur_rx, m); 1275 continue; 1276 } 1277 1278 1279 /* 1280 * Ok. NatSemi really screwed up here. This is the 1281 * only gigE chip I know of with alignment constraints 1282 * on receive buffers. RX buffers must be 64-bit aligned. 1283 */ 1284#ifdef __i386__ 1285 /* 1286 * By popular demand, ignore the alignment problems 1287 * on the Intel x86 platform. The performance hit 1288 * incurred due to unaligned accesses is much smaller 1289 * than the hit produced by forcing buffer copies all 1290 * the time, especially with jumbo frames. We still 1291 * need to fix up the alignment everywhere else though. 1292 */ 1293 if (nge_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 1294#endif 1295 m0 = m_devget(mtod(m, char *), total_len, 1296 ETHER_ALIGN, ifp, NULL); 1297 nge_newbuf(sc, cur_rx, m); 1298 if (m0 == NULL) { 1299 printf("nge%d: no receive buffers " 1300 "available -- packet dropped!\n", 1301 sc->nge_unit); 1302 ifp->if_ierrors++; 1303 continue; 1304 } 1305 m = m0; 1306#ifdef __i386__ 1307 } else { 1308 m->m_pkthdr.rcvif = ifp; 1309 m->m_pkthdr.len = m->m_len = total_len; 1310 } 1311#endif 1312 1313 ifp->if_ipackets++; 1314 eh = mtod(m, struct ether_header *); 1315 1316 /* Remove header from mbuf and pass it on. */ 1317 m_adj(m, sizeof(struct ether_header)); 1318 1319 /* Do IP checksum checking. */ 1320 if (extsts & NGE_RXEXTSTS_IPPKT) 1321 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1322 if (!(extsts & NGE_RXEXTSTS_IPCSUMERR)) 1323 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1324 if ((extsts & NGE_RXEXTSTS_TCPPKT && 1325 !(extsts & NGE_RXEXTSTS_TCPCSUMERR)) || 1326 (extsts & NGE_RXEXTSTS_UDPPKT && 1327 !(extsts & NGE_RXEXTSTS_UDPCSUMERR))) { 1328 m->m_pkthdr.csum_flags |= 1329 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1330 m->m_pkthdr.csum_data = 0xffff; 1331 } 1332 1333 /* 1334 * If we received a packet with a vlan tag, pass it 1335 * to vlan_input() instead of ether_input(). 1336 */ 1337 if (extsts & NGE_RXEXTSTS_VLANPKT) { 1338 VLAN_INPUT_TAG(eh, m, extsts & NGE_RXEXTSTS_VTCI); 1339 continue; 1340 } 1341 1342 ether_input(ifp, eh, m); 1343 } 1344 1345 sc->nge_cdata.nge_rx_prod = i; 1346 1347 return; 1348} 1349 1350#ifdef notdef 1351void nge_rxeoc(sc) 1352 struct nge_softc *sc; 1353{ 1354 struct ifnet *ifp; 1355 1356 ifp = &sc->arpcom.ac_if; 1357 nge_rxeof(sc); 1358 ifp->if_flags &= ~IFF_RUNNING; 1359 nge_init(sc); 1360 return; 1361} 1362#endif 1363 1364/* 1365 * A frame was downloaded to the chip. It's safe for us to clean up 1366 * the list buffers. 1367 */ 1368 1369static void nge_txeof(sc) 1370 struct nge_softc *sc; 1371{ 1372 struct nge_desc *cur_tx = NULL; 1373 struct ifnet *ifp; 1374 u_int32_t idx; 1375 1376 ifp = &sc->arpcom.ac_if; 1377 1378 /* Clear the timeout timer. */ 1379 ifp->if_timer = 0; 1380 1381 /* 1382 * Go through our tx list and free mbufs for those 1383 * frames that have been transmitted. 1384 */ 1385 idx = sc->nge_cdata.nge_tx_cons; 1386 while (idx != sc->nge_cdata.nge_tx_prod) { 1387 cur_tx = &sc->nge_ldata->nge_tx_list[idx]; 1388 1389 if (NGE_OWNDESC(cur_tx)) 1390 break; 1391 1392 if (cur_tx->nge_ctl & NGE_CMDSTS_MORE) { 1393 sc->nge_cdata.nge_tx_cnt--; 1394 NGE_INC(idx, NGE_TX_LIST_CNT); 1395 continue; 1396 } 1397 1398 if (!(cur_tx->nge_ctl & NGE_CMDSTS_PKT_OK)) { 1399 ifp->if_oerrors++; 1400 if (cur_tx->nge_txstat & NGE_TXSTAT_EXCESSCOLLS) 1401 ifp->if_collisions++; 1402 if (cur_tx->nge_txstat & NGE_TXSTAT_OUTOFWINCOLL) 1403 ifp->if_collisions++; 1404 } 1405 1406 ifp->if_collisions += 1407 (cur_tx->nge_txstat & NGE_TXSTAT_COLLCNT) >> 16; 1408 1409 ifp->if_opackets++; 1410 if (cur_tx->nge_mbuf != NULL) { 1411 m_freem(cur_tx->nge_mbuf); 1412 cur_tx->nge_mbuf = NULL; 1413 } 1414 1415 sc->nge_cdata.nge_tx_cnt--; 1416 NGE_INC(idx, NGE_TX_LIST_CNT); 1417 ifp->if_timer = 0; 1418 } 1419 1420 sc->nge_cdata.nge_tx_cons = idx; 1421 1422 if (cur_tx != NULL) 1423 ifp->if_flags &= ~IFF_OACTIVE; 1424 1425 return; 1426} 1427 1428static void nge_tick(xsc) 1429 void *xsc; 1430{ 1431 struct nge_softc *sc; 1432 struct mii_data *mii; 1433 struct ifnet *ifp; 1434 int s; 1435 1436 s = splimp(); 1437 1438 sc = xsc; 1439 ifp = &sc->arpcom.ac_if; 1440 1441 mii = device_get_softc(sc->nge_miibus); 1442 mii_tick(mii); 1443 1444 if (!sc->nge_link) { 1445 if (mii->mii_media_status & IFM_ACTIVE && 1446 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1447 sc->nge_link++; 1448 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX) 1449 printf("nge%d: gigabit link up\n", 1450 sc->nge_unit); 1451 if (ifp->if_snd.ifq_head != NULL) 1452 nge_start(ifp); 1453 } else 1454 sc->nge_stat_ch = timeout(nge_tick, sc, hz); 1455 } 1456 1457 1458 splx(s); 1459 1460 return; 1461} 1462 1463static void nge_intr(arg) 1464 void *arg; 1465{ 1466 struct nge_softc *sc; 1467 struct ifnet *ifp; 1468 u_int32_t status; 1469 1470 sc = arg; 1471 ifp = &sc->arpcom.ac_if; 1472 1473 /* Supress unwanted interrupts */ 1474 if (!(ifp->if_flags & IFF_UP)) { 1475 nge_stop(sc); 1476 return; 1477 } 1478 1479 /* Disable interrupts. */ 1480 CSR_WRITE_4(sc, NGE_IER, 0); 1481 1482 for (;;) { 1483 /* Reading the ISR register clears all interrupts. */ 1484 status = CSR_READ_4(sc, NGE_ISR); 1485 1486 if ((status & NGE_INTRS) == 0) 1487 break; 1488 1489 if ((status & NGE_ISR_TX_DESC_OK) || 1490 (status & NGE_ISR_TX_ERR) || 1491 (status & NGE_ISR_TX_OK) || 1492 (status & NGE_ISR_TX_IDLE)) 1493 nge_txeof(sc); 1494 1495 if ((status & NGE_ISR_RX_DESC_OK) || 1496 (status & NGE_ISR_RX_ERR) || 1497 (status & NGE_ISR_RX_OFLOW) || 1498 (status & NGE_ISR_RX_OK)) 1499 nge_rxeof(sc); 1500#ifdef notdef 1501 if ((status & NGE_ISR_RX_OFLOW)) 1502 nge_rxeoc(sc); 1503#endif 1504 if (status & NGE_ISR_SYSERR) { 1505 nge_reset(sc); 1506 ifp->if_flags &= ~IFF_RUNNING; 1507 nge_init(sc); 1508 } 1509 1510 if (status & NGE_IMR_PHY_INTR) { 1511 sc->nge_link = 0; 1512 nge_tick(sc); 1513 } 1514 } 1515 1516 /* Re-enable interrupts. */ 1517 CSR_WRITE_4(sc, NGE_IER, 1); 1518 1519 if (ifp->if_snd.ifq_head != NULL) 1520 nge_start(ifp); 1521 1522 return; 1523} 1524 1525/* 1526 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1527 * pointers to the fragment pointers. 1528 */ 1529static int nge_encap(sc, m_head, txidx) 1530 struct nge_softc *sc; 1531 struct mbuf *m_head; 1532 u_int32_t *txidx; 1533{ 1534 struct nge_desc *f = NULL; 1535 struct mbuf *m; 1536 int frag, cur, cnt = 0; 1537 struct ifvlan *ifv = NULL; 1538 1539 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 1540 m_head->m_pkthdr.rcvif != NULL && 1541 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN) 1542 ifv = m_head->m_pkthdr.rcvif->if_softc; 1543 1544 /* 1545 * Start packing the mbufs in this chain into 1546 * the fragment pointers. Stop when we run out 1547 * of fragments or hit the end of the mbuf chain. 1548 */ 1549 m = m_head; 1550 cur = frag = *txidx; 1551 1552 for (m = m_head; m != NULL; m = m->m_next) { 1553 if (m->m_len != 0) { 1554 if ((NGE_TX_LIST_CNT - 1555 (sc->nge_cdata.nge_tx_cnt + cnt)) < 2) 1556 return(ENOBUFS); 1557 f = &sc->nge_ldata->nge_tx_list[frag]; 1558 f->nge_ctl = NGE_CMDSTS_MORE | m->m_len; 1559 f->nge_ptr = vtophys(mtod(m, vm_offset_t)); 1560 if (cnt != 0) 1561 f->nge_ctl |= NGE_CMDSTS_OWN; 1562 cur = frag; 1563 NGE_INC(frag, NGE_TX_LIST_CNT); 1564 cnt++; 1565 } 1566 } 1567 1568 if (m != NULL) 1569 return(ENOBUFS); 1570 1571 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts = 0; 1572 if (m_head->m_pkthdr.csum_flags) { 1573 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1574 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1575 NGE_TXEXTSTS_IPCSUM; 1576 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1577 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1578 NGE_TXEXTSTS_TCPCSUM; 1579 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 1580 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1581 NGE_TXEXTSTS_UDPCSUM; 1582 } 1583 1584 if (ifv != NULL) { 1585 sc->nge_ldata->nge_tx_list[cur].nge_extsts |= 1586 (NGE_TXEXTSTS_VLANPKT|ifv->ifv_tag); 1587 } 1588 1589 sc->nge_ldata->nge_tx_list[cur].nge_mbuf = m_head; 1590 sc->nge_ldata->nge_tx_list[cur].nge_ctl &= ~NGE_CMDSTS_MORE; 1591 sc->nge_ldata->nge_tx_list[*txidx].nge_ctl |= NGE_CMDSTS_OWN; 1592 sc->nge_cdata.nge_tx_cnt += cnt; 1593 *txidx = frag; 1594 1595 return(0); 1596} 1597 1598/* 1599 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1600 * to the mbuf data regions directly in the transmit lists. We also save a 1601 * copy of the pointers since the transmit list fragment pointers are 1602 * physical addresses. 1603 */ 1604 1605static void nge_start(ifp) 1606 struct ifnet *ifp; 1607{ 1608 struct nge_softc *sc; 1609 struct mbuf *m_head = NULL; 1610 u_int32_t idx; 1611 1612 sc = ifp->if_softc; 1613 1614 if (!sc->nge_link) 1615 return; 1616 1617 idx = sc->nge_cdata.nge_tx_prod; 1618 1619 if (ifp->if_flags & IFF_OACTIVE) 1620 return; 1621 1622 while(sc->nge_ldata->nge_tx_list[idx].nge_mbuf == NULL) { 1623 IF_DEQUEUE(&ifp->if_snd, m_head); 1624 if (m_head == NULL) 1625 break; 1626 1627 if (nge_encap(sc, m_head, &idx)) { 1628 IF_PREPEND(&ifp->if_snd, m_head); 1629 ifp->if_flags |= IFF_OACTIVE; 1630 break; 1631 } 1632 1633 /* 1634 * If there's a BPF listener, bounce a copy of this frame 1635 * to him. 1636 */ 1637 if (ifp->if_bpf) 1638 bpf_mtap(ifp, m_head); 1639 1640 } 1641 1642 /* Transmit */ 1643 sc->nge_cdata.nge_tx_prod = idx; 1644 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_ENABLE); 1645 1646 /* 1647 * Set a timeout in case the chip goes out to lunch. 1648 */ 1649 ifp->if_timer = 5; 1650 1651 return; 1652} 1653 1654static void nge_init(xsc) 1655 void *xsc; 1656{ 1657 struct nge_softc *sc = xsc; 1658 struct ifnet *ifp = &sc->arpcom.ac_if; 1659 struct mii_data *mii; 1660 int s; 1661 1662 if (ifp->if_flags & IFF_RUNNING) 1663 return; 1664 1665 s = splimp(); 1666 1667 /* 1668 * Cancel pending I/O and free all RX/TX buffers. 1669 */ 1670 nge_stop(sc); 1671 1672 mii = device_get_softc(sc->nge_miibus); 1673 1674 /* Set MAC address */ 1675 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0); 1676 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1677 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1678 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR1); 1679 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1680 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1681 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR2); 1682 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1683 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1684 1685 /* Init circular RX list. */ 1686 if (nge_list_rx_init(sc) == ENOBUFS) { 1687 printf("nge%d: initialization failed: no " 1688 "memory for rx buffers\n", sc->nge_unit); 1689 nge_stop(sc); 1690 (void)splx(s); 1691 return; 1692 } 1693 1694 /* 1695 * Init tx descriptors. 1696 */ 1697 nge_list_tx_init(sc); 1698 1699 /* 1700 * For the NatSemi chip, we have to explicitly enable the 1701 * reception of ARP frames, as well as turn on the 'perfect 1702 * match' filter where we store the station address, otherwise 1703 * we won't receive unicasts meant for this host. 1704 */ 1705 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ARP); 1706 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_PERFECT); 1707 1708 /* If we want promiscuous mode, set the allframes bit. */ 1709 if (ifp->if_flags & IFF_PROMISC) { 1710 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS); 1711 } else { 1712 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS); 1713 } 1714 1715 /* 1716 * Set the capture broadcast bit to capture broadcast frames. 1717 */ 1718 if (ifp->if_flags & IFF_BROADCAST) { 1719 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD); 1720 } else { 1721 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD); 1722 } 1723 1724 /* 1725 * Load the multicast filter. 1726 */ 1727 nge_setmulti(sc); 1728 1729 /* Turn the receive filter on */ 1730 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ENABLE); 1731 1732 /* 1733 * Load the address of the RX and TX lists. 1734 */ 1735 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 1736 vtophys(&sc->nge_ldata->nge_rx_list[0])); 1737 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 1738 vtophys(&sc->nge_ldata->nge_tx_list[0])); 1739 1740 /* Set RX configuration */ 1741 CSR_WRITE_4(sc, NGE_RX_CFG, NGE_RXCFG); 1742 /* 1743 * Enable hardware checksum validation for all IPv4 1744 * packets, do not reject packets with bad checksums. 1745 */ 1746 CSR_WRITE_4(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_IPCSUM_ENB); 1747 1748 /* 1749 * Tell the chip to detect and strip VLAN tag info from 1750 * received frames. The tag will be provided in the extsts 1751 * field in the RX descriptors. 1752 */ 1753 NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL, 1754 NGE_VIPRXCTL_TAG_DETECT_ENB|NGE_VIPRXCTL_TAG_STRIP_ENB); 1755 1756 /* Set TX configuration */ 1757 CSR_WRITE_4(sc, NGE_TX_CFG, NGE_TXCFG); 1758 1759 /* 1760 * Enable TX IPv4 checksumming on a per-packet basis. 1761 */ 1762 CSR_WRITE_4(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_CSUM_PER_PKT); 1763 1764 /* 1765 * Tell the chip to insert VLAN tags on a per-packet basis as 1766 * dictated by the code in the frame encapsulation routine. 1767 */ 1768 NGE_SETBIT(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_TAG_PER_PKT); 1769 1770 /* Set full/half duplex mode. */ 1771 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1772 NGE_SETBIT(sc, NGE_TX_CFG, 1773 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1774 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1775 } else { 1776 NGE_CLRBIT(sc, NGE_TX_CFG, 1777 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1778 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1779 } 1780 1781 /* 1782 * Enable the delivery of PHY interrupts based on 1783 * link/speed/duplex status changes. Also enable the 1784 * extsts field in the DMA descriptors (needed for 1785 * TCP/IP checksum offload on transmit). 1786 */ 1787 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_PHYINTR_SPD| 1788 NGE_CFG_PHYINTR_LNK|NGE_CFG_PHYINTR_DUP|NGE_CFG_EXTSTS_ENB); 1789 1790 /* 1791 * Configure interrupt holdoff (moderation). We can 1792 * have the chip delay interrupt delivery for a certain 1793 * period. Units are in 100us, and the max setting 1794 * is 25500us (0xFF x 100us). Default is a 100us holdoff. 1795 */ 1796 CSR_WRITE_4(sc, NGE_IHR, 0x01); 1797 1798 /* 1799 * Enable interrupts. 1800 */ 1801 CSR_WRITE_4(sc, NGE_IMR, NGE_INTRS); 1802 CSR_WRITE_4(sc, NGE_IER, 1); 1803 1804 /* Enable receiver and transmitter. */ 1805 NGE_CLRBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE); 1806 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1807 1808 nge_ifmedia_upd(ifp); 1809 1810 ifp->if_flags |= IFF_RUNNING; 1811 ifp->if_flags &= ~IFF_OACTIVE; 1812 1813 (void)splx(s); 1814 1815 return; 1816} 1817 1818/* 1819 * Set media options. 1820 */ 1821static int nge_ifmedia_upd(ifp) 1822 struct ifnet *ifp; 1823{ 1824 struct nge_softc *sc; 1825 struct mii_data *mii; 1826 1827 sc = ifp->if_softc; 1828 1829 mii = device_get_softc(sc->nge_miibus); 1830 sc->nge_link = 0; 1831 if (mii->mii_instance) { 1832 struct mii_softc *miisc; 1833 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1834 miisc = LIST_NEXT(miisc, mii_list)) 1835 mii_phy_reset(miisc); 1836 } 1837 mii_mediachg(mii); 1838 1839 return(0); 1840} 1841 1842/* 1843 * Report current media status. 1844 */ 1845static void nge_ifmedia_sts(ifp, ifmr) 1846 struct ifnet *ifp; 1847 struct ifmediareq *ifmr; 1848{ 1849 struct nge_softc *sc; 1850 struct mii_data *mii; 1851 1852 sc = ifp->if_softc; 1853 1854 mii = device_get_softc(sc->nge_miibus); 1855 mii_pollstat(mii); 1856 ifmr->ifm_active = mii->mii_media_active; 1857 ifmr->ifm_status = mii->mii_media_status; 1858 1859 return; 1860} 1861 1862static int nge_ioctl(ifp, command, data) 1863 struct ifnet *ifp; 1864 u_long command; 1865 caddr_t data; 1866{ 1867 struct nge_softc *sc = ifp->if_softc; 1868 struct ifreq *ifr = (struct ifreq *) data; 1869 struct mii_data *mii; 1870 int s, error = 0; 1871 1872 s = splimp(); 1873 1874 switch(command) { 1875 case SIOCSIFADDR: 1876 case SIOCGIFADDR: 1877 error = ether_ioctl(ifp, command, data); 1878 break; 1879 case SIOCSIFMTU: 1880 if (ifr->ifr_mtu > NGE_JUMBO_MTU) 1881 error = EINVAL; 1882 else { 1883 ifp->if_mtu = ifr->ifr_mtu; 1884 /* 1885 * Workaround: if the MTU is larger than 1886 * 8152 (TX FIFO size minus 64 minus 18), turn off 1887 * TX checksum offloading. 1888 */ 1889 if (ifr->ifr_mtu >= 8152) 1890 ifp->if_hwassist = 0; 1891 else 1892 ifp->if_hwassist = NGE_CSUM_FEATURES; 1893 } 1894 break; 1895 case SIOCSIFFLAGS: 1896 if (ifp->if_flags & IFF_UP) { 1897 if (ifp->if_flags & IFF_RUNNING && 1898 ifp->if_flags & IFF_PROMISC && 1899 !(sc->nge_if_flags & IFF_PROMISC)) { 1900 NGE_SETBIT(sc, NGE_RXFILT_CTL, 1901 NGE_RXFILTCTL_ALLPHYS| 1902 NGE_RXFILTCTL_ALLMULTI); 1903 } else if (ifp->if_flags & IFF_RUNNING && 1904 !(ifp->if_flags & IFF_PROMISC) && 1905 sc->nge_if_flags & IFF_PROMISC) { 1906 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 1907 NGE_RXFILTCTL_ALLPHYS); 1908 if (!(ifp->if_flags & IFF_ALLMULTI)) 1909 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 1910 NGE_RXFILTCTL_ALLMULTI); 1911 } else { 1912 ifp->if_flags &= ~IFF_RUNNING; 1913 nge_init(sc); 1914 } 1915 } else { 1916 if (ifp->if_flags & IFF_RUNNING) 1917 nge_stop(sc); 1918 } 1919 sc->nge_if_flags = ifp->if_flags; 1920 error = 0; 1921 break; 1922 case SIOCADDMULTI: 1923 case SIOCDELMULTI: 1924 nge_setmulti(sc); 1925 error = 0; 1926 break; 1927 case SIOCGIFMEDIA: 1928 case SIOCSIFMEDIA: 1929 mii = device_get_softc(sc->nge_miibus); 1930 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1931 break; 1932 default: 1933 error = EINVAL; 1934 break; 1935 } 1936 1937 (void)splx(s); 1938 1939 return(error); 1940} 1941 1942static void nge_watchdog(ifp) 1943 struct ifnet *ifp; 1944{ 1945 struct nge_softc *sc; 1946 1947 sc = ifp->if_softc; 1948 1949 ifp->if_oerrors++; 1950 printf("nge%d: watchdog timeout\n", sc->nge_unit); 1951 1952 nge_stop(sc); 1953 nge_reset(sc); 1954 ifp->if_flags &= ~IFF_RUNNING; 1955 nge_init(sc); 1956 1957 if (ifp->if_snd.ifq_head != NULL) 1958 nge_start(ifp); 1959 1960 return; 1961} 1962 1963/* 1964 * Stop the adapter and free any mbufs allocated to the 1965 * RX and TX lists. 1966 */ 1967static void nge_stop(sc) 1968 struct nge_softc *sc; 1969{ 1970 register int i; 1971 struct ifnet *ifp; 1972 struct ifmedia_entry *ifm; 1973 struct mii_data *mii; 1974 int mtmp, itmp; 1975 1976 ifp = &sc->arpcom.ac_if; 1977 ifp->if_timer = 0; 1978 mii = device_get_softc(sc->nge_miibus); 1979 1980 untimeout(nge_tick, sc, sc->nge_stat_ch); 1981 CSR_WRITE_4(sc, NGE_IER, 0); 1982 CSR_WRITE_4(sc, NGE_IMR, 0); 1983 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE); 1984 DELAY(1000); 1985 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 0); 1986 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 0); 1987 1988 /* 1989 * Isolate/power down the PHY, but leave the media selection 1990 * unchanged so that things will be put back to normal when 1991 * we bring the interface back up. 1992 */ 1993 itmp = ifp->if_flags; 1994 ifp->if_flags |= IFF_UP; 1995 ifm = mii->mii_media.ifm_cur; 1996 mtmp = ifm->ifm_media; 1997 ifm->ifm_media = IFM_ETHER|IFM_NONE; 1998 mii_mediachg(mii); 1999 ifm->ifm_media = mtmp; 2000 ifp->if_flags = itmp; 2001 2002 sc->nge_link = 0; 2003 2004 /* 2005 * Free data in the RX lists. 2006 */ 2007 for (i = 0; i < NGE_RX_LIST_CNT; i++) { 2008 if (sc->nge_ldata->nge_rx_list[i].nge_mbuf != NULL) { 2009 m_freem(sc->nge_ldata->nge_rx_list[i].nge_mbuf); 2010 sc->nge_ldata->nge_rx_list[i].nge_mbuf = NULL; 2011 } 2012 } 2013 bzero((char *)&sc->nge_ldata->nge_rx_list, 2014 sizeof(sc->nge_ldata->nge_rx_list)); 2015 2016 /* 2017 * Free the TX list buffers. 2018 */ 2019 for (i = 0; i < NGE_TX_LIST_CNT; i++) { 2020 if (sc->nge_ldata->nge_tx_list[i].nge_mbuf != NULL) { 2021 m_freem(sc->nge_ldata->nge_tx_list[i].nge_mbuf); 2022 sc->nge_ldata->nge_tx_list[i].nge_mbuf = NULL; 2023 } 2024 } 2025 2026 bzero((char *)&sc->nge_ldata->nge_tx_list, 2027 sizeof(sc->nge_ldata->nge_tx_list)); 2028 2029 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2030 2031 return; 2032} 2033 2034/* 2035 * Stop all chip I/O so that the kernel's probe routines don't 2036 * get confused by errant DMAs when rebooting. 2037 */ 2038static void nge_shutdown(dev) 2039 device_t dev; 2040{ 2041 struct nge_softc *sc; 2042 2043 sc = device_get_softc(dev); 2044 2045 nge_reset(sc); 2046 nge_stop(sc); 2047 2048 return; 2049} 2050