if_nge.c revision 87276
1/* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2000, 2001 4 * Bill Paul <wpaul@bsdi.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: head/sys/dev/nge/if_nge.c 87276 2001-12-03 17:28:27Z brooks $ 34 */ 35 36/* 37 * National Semiconductor DP83820/DP83821 gigabit ethernet driver 38 * for FreeBSD. Datasheets are available from: 39 * 40 * http://www.national.com/ds/DP/DP83820.pdf 41 * http://www.national.com/ds/DP/DP83821.pdf 42 * 43 * These chips are used on several low cost gigabit ethernet NICs 44 * sold by D-Link, Addtron, SMC and Asante. Both parts are 45 * virtually the same, except the 83820 is a 64-bit/32-bit part, 46 * while the 83821 is 32-bit only. 47 * 48 * Many cards also use National gigE transceivers, such as the 49 * DP83891, DP83861 and DP83862 gigPHYTER parts. The DP83861 datasheet 50 * contains a full register description that applies to all of these 51 * components: 52 * 53 * http://www.national.com/ds/DP/DP83861.pdf 54 * 55 * Written by Bill Paul <wpaul@bsdi.com> 56 * BSDi Open Source Solutions 57 */ 58 59/* 60 * The NatSemi DP83820 and 83821 controllers are enhanced versions 61 * of the NatSemi MacPHYTER 10/100 devices. They support 10, 100 62 * and 1000Mbps speeds with 1000baseX (ten bit interface), MII and GMII 63 * ports. Other features include 8K TX FIFO and 32K RX FIFO, TCP/IP 64 * hardware checksum offload (IPv4 only), VLAN tagging and filtering, 65 * priority TX and RX queues, a 2048 bit multicast hash filter, 4 RX pattern 66 * matching buffers, one perfect address filter buffer and interrupt 67 * moderation. The 83820 supports both 64-bit and 32-bit addressing 68 * and data transfers: the 64-bit support can be toggled on or off 69 * via software. This affects the size of certain fields in the DMA 70 * descriptors. 71 * 72 * There are two bugs/misfeatures in the 83820/83821 that I have 73 * discovered so far: 74 * 75 * - Receive buffers must be aligned on 64-bit boundaries, which means 76 * you must resort to copying data in order to fix up the payload 77 * alignment. 78 * 79 * - In order to transmit jumbo frames larger than 8170 bytes, you have 80 * to turn off transmit checksum offloading, because the chip can't 81 * compute the checksum on an outgoing frame unless it fits entirely 82 * within the TX FIFO, which is only 8192 bytes in size. If you have 83 * TX checksum offload enabled and you transmit attempt to transmit a 84 * frame larger than 8170 bytes, the transmitter will wedge. 85 * 86 * To work around the latter problem, TX checksum offload is disabled 87 * if the user selects an MTU larger than 8152 (8170 - 18). 88 */ 89 90#include <sys/param.h> 91#include <sys/systm.h> 92#include <sys/sockio.h> 93#include <sys/mbuf.h> 94#include <sys/malloc.h> 95#include <sys/kernel.h> 96#include <sys/socket.h> 97 98#include <net/if.h> 99#include <net/if_arp.h> 100#include <net/ethernet.h> 101#include <net/if_dl.h> 102#include <net/if_media.h> 103#include <net/if_types.h> 104#include <net/if_vlan_var.h> 105 106#include <net/bpf.h> 107 108#include <vm/vm.h> /* for vtophys */ 109#include <vm/pmap.h> /* for vtophys */ 110#include <machine/clock.h> /* for DELAY */ 111#include <machine/bus_pio.h> 112#include <machine/bus_memio.h> 113#include <machine/bus.h> 114#include <machine/resource.h> 115#include <sys/bus.h> 116#include <sys/rman.h> 117 118#include <dev/mii/mii.h> 119#include <dev/mii/miivar.h> 120 121#include <pci/pcireg.h> 122#include <pci/pcivar.h> 123 124#define NGE_USEIOSPACE 125 126#include <dev/nge/if_ngereg.h> 127 128MODULE_DEPEND(nge, miibus, 1, 1, 1); 129 130/* "controller miibus0" required. See GENERIC if you get errors here. */ 131#include "miibus_if.h" 132 133#ifndef lint 134static const char rcsid[] = 135 "$FreeBSD: head/sys/dev/nge/if_nge.c 87276 2001-12-03 17:28:27Z brooks $"; 136#endif 137 138#define NGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 139 140/* 141 * Various supported device vendors/types and their names. 142 */ 143static struct nge_type nge_devs[] = { 144 { NGE_VENDORID, NGE_DEVICEID, 145 "National Semiconductor Gigabit Ethernet" }, 146 { 0, 0, NULL } 147}; 148 149static int nge_probe __P((device_t)); 150static int nge_attach __P((device_t)); 151static int nge_detach __P((device_t)); 152 153static int nge_alloc_jumbo_mem __P((struct nge_softc *)); 154static void nge_free_jumbo_mem __P((struct nge_softc *)); 155static void *nge_jalloc __P((struct nge_softc *)); 156static void nge_jfree __P((caddr_t, void *)); 157 158static int nge_newbuf __P((struct nge_softc *, 159 struct nge_desc *, 160 struct mbuf *)); 161static int nge_encap __P((struct nge_softc *, 162 struct mbuf *, u_int32_t *)); 163static void nge_rxeof __P((struct nge_softc *)); 164static void nge_rxeoc __P((struct nge_softc *)); 165static void nge_txeof __P((struct nge_softc *)); 166static void nge_intr __P((void *)); 167static void nge_tick __P((void *)); 168static void nge_start __P((struct ifnet *)); 169static int nge_ioctl __P((struct ifnet *, u_long, caddr_t)); 170static void nge_init __P((void *)); 171static void nge_stop __P((struct nge_softc *)); 172static void nge_watchdog __P((struct ifnet *)); 173static void nge_shutdown __P((device_t)); 174static int nge_ifmedia_upd __P((struct ifnet *)); 175static void nge_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 176 177static void nge_delay __P((struct nge_softc *)); 178static void nge_eeprom_idle __P((struct nge_softc *)); 179static void nge_eeprom_putbyte __P((struct nge_softc *, int)); 180static void nge_eeprom_getword __P((struct nge_softc *, int, u_int16_t *)); 181static void nge_read_eeprom __P((struct nge_softc *, caddr_t, int, 182 int, int)); 183 184static void nge_mii_sync __P((struct nge_softc *)); 185static void nge_mii_send __P((struct nge_softc *, u_int32_t, int)); 186static int nge_mii_readreg __P((struct nge_softc *, 187 struct nge_mii_frame *)); 188static int nge_mii_writereg __P((struct nge_softc *, 189 struct nge_mii_frame *)); 190 191static int nge_miibus_readreg __P((device_t, int, int)); 192static int nge_miibus_writereg __P((device_t, int, int, int)); 193static void nge_miibus_statchg __P((device_t)); 194 195static void nge_setmulti __P((struct nge_softc *)); 196static u_int32_t nge_crc __P((struct nge_softc *, caddr_t)); 197static void nge_reset __P((struct nge_softc *)); 198static int nge_list_rx_init __P((struct nge_softc *)); 199static int nge_list_tx_init __P((struct nge_softc *)); 200 201#ifdef NGE_USEIOSPACE 202#define NGE_RES SYS_RES_IOPORT 203#define NGE_RID NGE_PCI_LOIO 204#else 205#define NGE_RES SYS_RES_MEMORY 206#define NGE_RID NGE_PCI_LOMEM 207#endif 208 209static device_method_t nge_methods[] = { 210 /* Device interface */ 211 DEVMETHOD(device_probe, nge_probe), 212 DEVMETHOD(device_attach, nge_attach), 213 DEVMETHOD(device_detach, nge_detach), 214 DEVMETHOD(device_shutdown, nge_shutdown), 215 216 /* bus interface */ 217 DEVMETHOD(bus_print_child, bus_generic_print_child), 218 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 219 220 /* MII interface */ 221 DEVMETHOD(miibus_readreg, nge_miibus_readreg), 222 DEVMETHOD(miibus_writereg, nge_miibus_writereg), 223 DEVMETHOD(miibus_statchg, nge_miibus_statchg), 224 225 { 0, 0 } 226}; 227 228static driver_t nge_driver = { 229 "nge", 230 nge_methods, 231 sizeof(struct nge_softc) 232}; 233 234static devclass_t nge_devclass; 235 236DRIVER_MODULE(if_nge, pci, nge_driver, nge_devclass, 0, 0); 237DRIVER_MODULE(miibus, nge, miibus_driver, miibus_devclass, 0, 0); 238 239#define NGE_SETBIT(sc, reg, x) \ 240 CSR_WRITE_4(sc, reg, \ 241 CSR_READ_4(sc, reg) | (x)) 242 243#define NGE_CLRBIT(sc, reg, x) \ 244 CSR_WRITE_4(sc, reg, \ 245 CSR_READ_4(sc, reg) & ~(x)) 246 247#define SIO_SET(x) \ 248 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | x) 249 250#define SIO_CLR(x) \ 251 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~x) 252 253static void nge_delay(sc) 254 struct nge_softc *sc; 255{ 256 int idx; 257 258 for (idx = (300 / 33) + 1; idx > 0; idx--) 259 CSR_READ_4(sc, NGE_CSR); 260 261 return; 262} 263 264static void nge_eeprom_idle(sc) 265 struct nge_softc *sc; 266{ 267 register int i; 268 269 SIO_SET(NGE_MEAR_EE_CSEL); 270 nge_delay(sc); 271 SIO_SET(NGE_MEAR_EE_CLK); 272 nge_delay(sc); 273 274 for (i = 0; i < 25; i++) { 275 SIO_CLR(NGE_MEAR_EE_CLK); 276 nge_delay(sc); 277 SIO_SET(NGE_MEAR_EE_CLK); 278 nge_delay(sc); 279 } 280 281 SIO_CLR(NGE_MEAR_EE_CLK); 282 nge_delay(sc); 283 SIO_CLR(NGE_MEAR_EE_CSEL); 284 nge_delay(sc); 285 CSR_WRITE_4(sc, NGE_MEAR, 0x00000000); 286 287 return; 288} 289 290/* 291 * Send a read command and address to the EEPROM, check for ACK. 292 */ 293static void nge_eeprom_putbyte(sc, addr) 294 struct nge_softc *sc; 295 int addr; 296{ 297 register int d, i; 298 299 d = addr | NGE_EECMD_READ; 300 301 /* 302 * Feed in each bit and stobe the clock. 303 */ 304 for (i = 0x400; i; i >>= 1) { 305 if (d & i) { 306 SIO_SET(NGE_MEAR_EE_DIN); 307 } else { 308 SIO_CLR(NGE_MEAR_EE_DIN); 309 } 310 nge_delay(sc); 311 SIO_SET(NGE_MEAR_EE_CLK); 312 nge_delay(sc); 313 SIO_CLR(NGE_MEAR_EE_CLK); 314 nge_delay(sc); 315 } 316 317 return; 318} 319 320/* 321 * Read a word of data stored in the EEPROM at address 'addr.' 322 */ 323static void nge_eeprom_getword(sc, addr, dest) 324 struct nge_softc *sc; 325 int addr; 326 u_int16_t *dest; 327{ 328 register int i; 329 u_int16_t word = 0; 330 331 /* Force EEPROM to idle state. */ 332 nge_eeprom_idle(sc); 333 334 /* Enter EEPROM access mode. */ 335 nge_delay(sc); 336 SIO_CLR(NGE_MEAR_EE_CLK); 337 nge_delay(sc); 338 SIO_SET(NGE_MEAR_EE_CSEL); 339 nge_delay(sc); 340 341 /* 342 * Send address of word we want to read. 343 */ 344 nge_eeprom_putbyte(sc, addr); 345 346 /* 347 * Start reading bits from EEPROM. 348 */ 349 for (i = 0x8000; i; i >>= 1) { 350 SIO_SET(NGE_MEAR_EE_CLK); 351 nge_delay(sc); 352 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT) 353 word |= i; 354 nge_delay(sc); 355 SIO_CLR(NGE_MEAR_EE_CLK); 356 nge_delay(sc); 357 } 358 359 /* Turn off EEPROM access mode. */ 360 nge_eeprom_idle(sc); 361 362 *dest = word; 363 364 return; 365} 366 367/* 368 * Read a sequence of words from the EEPROM. 369 */ 370static void nge_read_eeprom(sc, dest, off, cnt, swap) 371 struct nge_softc *sc; 372 caddr_t dest; 373 int off; 374 int cnt; 375 int swap; 376{ 377 int i; 378 u_int16_t word = 0, *ptr; 379 380 for (i = 0; i < cnt; i++) { 381 nge_eeprom_getword(sc, off + i, &word); 382 ptr = (u_int16_t *)(dest + (i * 2)); 383 if (swap) 384 *ptr = ntohs(word); 385 else 386 *ptr = word; 387 } 388 389 return; 390} 391 392/* 393 * Sync the PHYs by setting data bit and strobing the clock 32 times. 394 */ 395static void nge_mii_sync(sc) 396 struct nge_softc *sc; 397{ 398 register int i; 399 400 SIO_SET(NGE_MEAR_MII_DIR|NGE_MEAR_MII_DATA); 401 402 for (i = 0; i < 32; i++) { 403 SIO_SET(NGE_MEAR_MII_CLK); 404 DELAY(1); 405 SIO_CLR(NGE_MEAR_MII_CLK); 406 DELAY(1); 407 } 408 409 return; 410} 411 412/* 413 * Clock a series of bits through the MII. 414 */ 415static void nge_mii_send(sc, bits, cnt) 416 struct nge_softc *sc; 417 u_int32_t bits; 418 int cnt; 419{ 420 int i; 421 422 SIO_CLR(NGE_MEAR_MII_CLK); 423 424 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 425 if (bits & i) { 426 SIO_SET(NGE_MEAR_MII_DATA); 427 } else { 428 SIO_CLR(NGE_MEAR_MII_DATA); 429 } 430 DELAY(1); 431 SIO_CLR(NGE_MEAR_MII_CLK); 432 DELAY(1); 433 SIO_SET(NGE_MEAR_MII_CLK); 434 } 435} 436 437/* 438 * Read an PHY register through the MII. 439 */ 440static int nge_mii_readreg(sc, frame) 441 struct nge_softc *sc; 442 struct nge_mii_frame *frame; 443 444{ 445 int i, ack, s; 446 447 s = splimp(); 448 449 /* 450 * Set up frame for RX. 451 */ 452 frame->mii_stdelim = NGE_MII_STARTDELIM; 453 frame->mii_opcode = NGE_MII_READOP; 454 frame->mii_turnaround = 0; 455 frame->mii_data = 0; 456 457 CSR_WRITE_4(sc, NGE_MEAR, 0); 458 459 /* 460 * Turn on data xmit. 461 */ 462 SIO_SET(NGE_MEAR_MII_DIR); 463 464 nge_mii_sync(sc); 465 466 /* 467 * Send command/address info. 468 */ 469 nge_mii_send(sc, frame->mii_stdelim, 2); 470 nge_mii_send(sc, frame->mii_opcode, 2); 471 nge_mii_send(sc, frame->mii_phyaddr, 5); 472 nge_mii_send(sc, frame->mii_regaddr, 5); 473 474 /* Idle bit */ 475 SIO_CLR((NGE_MEAR_MII_CLK|NGE_MEAR_MII_DATA)); 476 DELAY(1); 477 SIO_SET(NGE_MEAR_MII_CLK); 478 DELAY(1); 479 480 /* Turn off xmit. */ 481 SIO_CLR(NGE_MEAR_MII_DIR); 482 /* Check for ack */ 483 SIO_CLR(NGE_MEAR_MII_CLK); 484 DELAY(1); 485 SIO_SET(NGE_MEAR_MII_CLK); 486 DELAY(1); 487 ack = CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA; 488 489 /* 490 * Now try reading data bits. If the ack failed, we still 491 * need to clock through 16 cycles to keep the PHY(s) in sync. 492 */ 493 if (ack) { 494 for(i = 0; i < 16; i++) { 495 SIO_CLR(NGE_MEAR_MII_CLK); 496 DELAY(1); 497 SIO_SET(NGE_MEAR_MII_CLK); 498 DELAY(1); 499 } 500 goto fail; 501 } 502 503 for (i = 0x8000; i; i >>= 1) { 504 SIO_CLR(NGE_MEAR_MII_CLK); 505 DELAY(1); 506 if (!ack) { 507 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA) 508 frame->mii_data |= i; 509 DELAY(1); 510 } 511 SIO_SET(NGE_MEAR_MII_CLK); 512 DELAY(1); 513 } 514 515fail: 516 517 SIO_CLR(NGE_MEAR_MII_CLK); 518 DELAY(1); 519 SIO_SET(NGE_MEAR_MII_CLK); 520 DELAY(1); 521 522 splx(s); 523 524 if (ack) 525 return(1); 526 return(0); 527} 528 529/* 530 * Write to a PHY register through the MII. 531 */ 532static int nge_mii_writereg(sc, frame) 533 struct nge_softc *sc; 534 struct nge_mii_frame *frame; 535 536{ 537 int s; 538 539 s = splimp(); 540 /* 541 * Set up frame for TX. 542 */ 543 544 frame->mii_stdelim = NGE_MII_STARTDELIM; 545 frame->mii_opcode = NGE_MII_WRITEOP; 546 frame->mii_turnaround = NGE_MII_TURNAROUND; 547 548 /* 549 * Turn on data output. 550 */ 551 SIO_SET(NGE_MEAR_MII_DIR); 552 553 nge_mii_sync(sc); 554 555 nge_mii_send(sc, frame->mii_stdelim, 2); 556 nge_mii_send(sc, frame->mii_opcode, 2); 557 nge_mii_send(sc, frame->mii_phyaddr, 5); 558 nge_mii_send(sc, frame->mii_regaddr, 5); 559 nge_mii_send(sc, frame->mii_turnaround, 2); 560 nge_mii_send(sc, frame->mii_data, 16); 561 562 /* Idle bit. */ 563 SIO_SET(NGE_MEAR_MII_CLK); 564 DELAY(1); 565 SIO_CLR(NGE_MEAR_MII_CLK); 566 DELAY(1); 567 568 /* 569 * Turn off xmit. 570 */ 571 SIO_CLR(NGE_MEAR_MII_DIR); 572 573 splx(s); 574 575 return(0); 576} 577 578static int nge_miibus_readreg(dev, phy, reg) 579 device_t dev; 580 int phy, reg; 581{ 582 struct nge_softc *sc; 583 struct nge_mii_frame frame; 584 585 sc = device_get_softc(dev); 586 587 bzero((char *)&frame, sizeof(frame)); 588 589 frame.mii_phyaddr = phy; 590 frame.mii_regaddr = reg; 591 nge_mii_readreg(sc, &frame); 592 593 return(frame.mii_data); 594} 595 596static int nge_miibus_writereg(dev, phy, reg, data) 597 device_t dev; 598 int phy, reg, data; 599{ 600 struct nge_softc *sc; 601 struct nge_mii_frame frame; 602 603 sc = device_get_softc(dev); 604 605 bzero((char *)&frame, sizeof(frame)); 606 607 frame.mii_phyaddr = phy; 608 frame.mii_regaddr = reg; 609 frame.mii_data = data; 610 nge_mii_writereg(sc, &frame); 611 612 return(0); 613} 614 615static void nge_miibus_statchg(dev) 616 device_t dev; 617{ 618 struct nge_softc *sc; 619 struct mii_data *mii; 620 621 sc = device_get_softc(dev); 622 mii = device_get_softc(sc->nge_miibus); 623 624 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 625 NGE_SETBIT(sc, NGE_TX_CFG, 626 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 627 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 628 } else { 629 NGE_CLRBIT(sc, NGE_TX_CFG, 630 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 631 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 632 } 633 634 /* If we have a 1000Mbps link, set the mode_1000 bit. */ 635 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX || 636 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) { 637 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_MODE_1000); 638 } else { 639 NGE_CLRBIT(sc, NGE_CFG, NGE_CFG_MODE_1000); 640 } 641 642 return; 643} 644 645static u_int32_t nge_crc(sc, addr) 646 struct nge_softc *sc; 647 caddr_t addr; 648{ 649 u_int32_t crc, carry; 650 int i, j; 651 u_int8_t c; 652 653 /* Compute CRC for the address value. */ 654 crc = 0xFFFFFFFF; /* initial value */ 655 656 for (i = 0; i < 6; i++) { 657 c = *(addr + i); 658 for (j = 0; j < 8; j++) { 659 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 660 crc <<= 1; 661 c >>= 1; 662 if (carry) 663 crc = (crc ^ 0x04c11db6) | carry; 664 } 665 } 666 667 /* 668 * return the filter bit position 669 */ 670 671 return((crc >> 21) & 0x00000FFF); 672} 673 674static void nge_setmulti(sc) 675 struct nge_softc *sc; 676{ 677 struct ifnet *ifp; 678 struct ifmultiaddr *ifma; 679 u_int32_t h = 0, i, filtsave; 680 int bit, index; 681 682 ifp = &sc->arpcom.ac_if; 683 684 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 685 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 686 NGE_RXFILTCTL_MCHASH|NGE_RXFILTCTL_UCHASH); 687 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLMULTI); 688 return; 689 } 690 691 /* 692 * We have to explicitly enable the multicast hash table 693 * on the NatSemi chip if we want to use it, which we do. 694 * We also have to tell it that we don't want to use the 695 * hash table for matching unicast addresses. 696 */ 697 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_MCHASH); 698 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 699 NGE_RXFILTCTL_ALLMULTI|NGE_RXFILTCTL_UCHASH); 700 701 filtsave = CSR_READ_4(sc, NGE_RXFILT_CTL); 702 703 /* first, zot all the existing hash bits */ 704 for (i = 0; i < NGE_MCAST_FILTER_LEN; i += 2) { 705 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + i); 706 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 0); 707 } 708 709 /* 710 * From the 11 bits returned by the crc routine, the top 7 711 * bits represent the 16-bit word in the mcast hash table 712 * that needs to be updated, and the lower 4 bits represent 713 * which bit within that byte needs to be set. 714 */ 715 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 716 if (ifma->ifma_addr->sa_family != AF_LINK) 717 continue; 718 h = nge_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 719 index = (h >> 4) & 0x7F; 720 bit = h & 0xF; 721 CSR_WRITE_4(sc, NGE_RXFILT_CTL, 722 NGE_FILTADDR_MCAST_LO + (index * 2)); 723 NGE_SETBIT(sc, NGE_RXFILT_DATA, (1 << bit)); 724 } 725 726 CSR_WRITE_4(sc, NGE_RXFILT_CTL, filtsave); 727 728 return; 729} 730 731static void nge_reset(sc) 732 struct nge_softc *sc; 733{ 734 register int i; 735 736 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RESET); 737 738 for (i = 0; i < NGE_TIMEOUT; i++) { 739 if (!(CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET)) 740 break; 741 } 742 743 if (i == NGE_TIMEOUT) 744 printf("nge%d: reset never completed\n", sc->nge_unit); 745 746 /* Wait a little while for the chip to get its brains in order. */ 747 DELAY(1000); 748 749 /* 750 * If this is a NetSemi chip, make sure to clear 751 * PME mode. 752 */ 753 CSR_WRITE_4(sc, NGE_CLKRUN, NGE_CLKRUN_PMESTS); 754 CSR_WRITE_4(sc, NGE_CLKRUN, 0); 755 756 return; 757} 758 759/* 760 * Probe for an NatSemi chip. Check the PCI vendor and device 761 * IDs against our list and return a device name if we find a match. 762 */ 763static int nge_probe(dev) 764 device_t dev; 765{ 766 struct nge_type *t; 767 768 t = nge_devs; 769 770 while(t->nge_name != NULL) { 771 if ((pci_get_vendor(dev) == t->nge_vid) && 772 (pci_get_device(dev) == t->nge_did)) { 773 device_set_desc(dev, t->nge_name); 774 return(0); 775 } 776 t++; 777 } 778 779 return(ENXIO); 780} 781 782/* 783 * Attach the interface. Allocate softc structures, do ifmedia 784 * setup and ethernet/BPF attach. 785 */ 786static int nge_attach(dev) 787 device_t dev; 788{ 789 int s; 790 u_char eaddr[ETHER_ADDR_LEN]; 791 u_int32_t command; 792 struct nge_softc *sc; 793 struct ifnet *ifp; 794 int unit, error = 0, rid; 795 796 s = splimp(); 797 798 sc = device_get_softc(dev); 799 unit = device_get_unit(dev); 800 bzero(sc, sizeof(struct nge_softc)); 801 802 mtx_init(&sc->nge_mtx, device_get_nameunit(dev), MTX_DEF|MTX_RECURSE); 803 804 /* 805 * Handle power management nonsense. 806 */ 807 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 808 u_int32_t iobase, membase, irq; 809 810 /* Save important PCI config data. */ 811 iobase = pci_read_config(dev, NGE_PCI_LOIO, 4); 812 membase = pci_read_config(dev, NGE_PCI_LOMEM, 4); 813 irq = pci_read_config(dev, NGE_PCI_INTLINE, 4); 814 815 /* Reset the power state. */ 816 printf("nge%d: chip is in D%d power mode " 817 "-- setting to D0\n", unit, 818 pci_get_powerstate(dev)); 819 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 820 821 /* Restore PCI config data. */ 822 pci_write_config(dev, NGE_PCI_LOIO, iobase, 4); 823 pci_write_config(dev, NGE_PCI_LOMEM, membase, 4); 824 pci_write_config(dev, NGE_PCI_INTLINE, irq, 4); 825 } 826 827 /* 828 * Map control/status registers. 829 */ 830 pci_enable_busmaster(dev); 831 pci_enable_io(dev, SYS_RES_IOPORT); 832 pci_enable_io(dev, SYS_RES_MEMORY); 833 command = pci_read_config(dev, PCIR_COMMAND, 4); 834 835#ifdef NGE_USEIOSPACE 836 if (!(command & PCIM_CMD_PORTEN)) { 837 printf("nge%d: failed to enable I/O ports!\n", unit); 838 error = ENXIO;; 839 goto fail; 840 } 841#else 842 if (!(command & PCIM_CMD_MEMEN)) { 843 printf("nge%d: failed to enable memory mapping!\n", unit); 844 error = ENXIO;; 845 goto fail; 846 } 847#endif 848 849 rid = NGE_RID; 850 sc->nge_res = bus_alloc_resource(dev, NGE_RES, &rid, 851 0, ~0, 1, RF_ACTIVE); 852 853 if (sc->nge_res == NULL) { 854 printf("nge%d: couldn't map ports/memory\n", unit); 855 error = ENXIO; 856 goto fail; 857 } 858 859 sc->nge_btag = rman_get_bustag(sc->nge_res); 860 sc->nge_bhandle = rman_get_bushandle(sc->nge_res); 861 862 /* Allocate interrupt */ 863 rid = 0; 864 sc->nge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 865 RF_SHAREABLE | RF_ACTIVE); 866 867 if (sc->nge_irq == NULL) { 868 printf("nge%d: couldn't map interrupt\n", unit); 869 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 870 error = ENXIO; 871 goto fail; 872 } 873 874 error = bus_setup_intr(dev, sc->nge_irq, INTR_TYPE_NET, 875 nge_intr, sc, &sc->nge_intrhand); 876 877 if (error) { 878 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 879 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 880 printf("nge%d: couldn't set up irq\n", unit); 881 goto fail; 882 } 883 884 /* Reset the adapter. */ 885 nge_reset(sc); 886 887 /* 888 * Get station address from the EEPROM. 889 */ 890 nge_read_eeprom(sc, (caddr_t)&eaddr[4], NGE_EE_NODEADDR, 1, 0); 891 nge_read_eeprom(sc, (caddr_t)&eaddr[2], NGE_EE_NODEADDR + 1, 1, 0); 892 nge_read_eeprom(sc, (caddr_t)&eaddr[0], NGE_EE_NODEADDR + 2, 1, 0); 893 894 /* 895 * A NatSemi chip was detected. Inform the world. 896 */ 897 printf("nge%d: Ethernet address: %6D\n", unit, eaddr, ":"); 898 899 sc->nge_unit = unit; 900 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 901 902 sc->nge_ldata = contigmalloc(sizeof(struct nge_list_data), M_DEVBUF, 903 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 904 905 if (sc->nge_ldata == NULL) { 906 printf("nge%d: no memory for list buffers!\n", unit); 907 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 908 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 909 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 910 error = ENXIO; 911 goto fail; 912 } 913 bzero(sc->nge_ldata, sizeof(struct nge_list_data)); 914 915 /* Try to allocate memory for jumbo buffers. */ 916 if (nge_alloc_jumbo_mem(sc)) { 917 printf("nge%d: jumbo buffer allocation failed\n", 918 sc->nge_unit); 919 contigfree(sc->nge_ldata, 920 sizeof(struct nge_list_data), M_DEVBUF); 921 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 922 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 923 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 924 error = ENXIO; 925 goto fail; 926 } 927 928 ifp = &sc->arpcom.ac_if; 929 ifp->if_softc = sc; 930 ifp->if_unit = unit; 931 ifp->if_name = "nge"; 932 ifp->if_mtu = ETHERMTU; 933 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 934 ifp->if_ioctl = nge_ioctl; 935 ifp->if_output = ether_output; 936 ifp->if_start = nge_start; 937 ifp->if_watchdog = nge_watchdog; 938 ifp->if_init = nge_init; 939 ifp->if_baudrate = 1000000000; 940 ifp->if_snd.ifq_maxlen = NGE_TX_LIST_CNT - 1; 941 ifp->if_hwassist = NGE_CSUM_FEATURES; 942 ifp->if_capabilities = IFCAP_HWCSUM; 943 ifp->if_capenable = ifp->if_capabilities; 944 945 /* 946 * Do MII setup. 947 */ 948 if (mii_phy_probe(dev, &sc->nge_miibus, 949 nge_ifmedia_upd, nge_ifmedia_sts)) { 950 printf("nge%d: MII without any PHY!\n", sc->nge_unit); 951 nge_free_jumbo_mem(sc); 952 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 953 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 954 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 955 error = ENXIO; 956 goto fail; 957 } 958 959 /* 960 * Call MI attach routine. 961 */ 962 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 963 callout_handle_init(&sc->nge_stat_ch); 964 965fail: 966 splx(s); 967 mtx_destroy(&sc->nge_mtx); 968 return(error); 969} 970 971static int nge_detach(dev) 972 device_t dev; 973{ 974 struct nge_softc *sc; 975 struct ifnet *ifp; 976 int s; 977 978 s = splimp(); 979 980 sc = device_get_softc(dev); 981 ifp = &sc->arpcom.ac_if; 982 983 nge_reset(sc); 984 nge_stop(sc); 985 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 986 987 bus_generic_detach(dev); 988 device_delete_child(dev, sc->nge_miibus); 989 990 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 991 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 992 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 993 994 contigfree(sc->nge_ldata, sizeof(struct nge_list_data), M_DEVBUF); 995 nge_free_jumbo_mem(sc); 996 997 splx(s); 998 mtx_destroy(&sc->nge_mtx); 999 1000 return(0); 1001} 1002 1003/* 1004 * Initialize the transmit descriptors. 1005 */ 1006static int nge_list_tx_init(sc) 1007 struct nge_softc *sc; 1008{ 1009 struct nge_list_data *ld; 1010 struct nge_ring_data *cd; 1011 int i; 1012 1013 cd = &sc->nge_cdata; 1014 ld = sc->nge_ldata; 1015 1016 for (i = 0; i < NGE_TX_LIST_CNT; i++) { 1017 if (i == (NGE_TX_LIST_CNT - 1)) { 1018 ld->nge_tx_list[i].nge_nextdesc = 1019 &ld->nge_tx_list[0]; 1020 ld->nge_tx_list[i].nge_next = 1021 vtophys(&ld->nge_tx_list[0]); 1022 } else { 1023 ld->nge_tx_list[i].nge_nextdesc = 1024 &ld->nge_tx_list[i + 1]; 1025 ld->nge_tx_list[i].nge_next = 1026 vtophys(&ld->nge_tx_list[i + 1]); 1027 } 1028 ld->nge_tx_list[i].nge_mbuf = NULL; 1029 ld->nge_tx_list[i].nge_ptr = 0; 1030 ld->nge_tx_list[i].nge_ctl = 0; 1031 } 1032 1033 cd->nge_tx_prod = cd->nge_tx_cons = cd->nge_tx_cnt = 0; 1034 1035 return(0); 1036} 1037 1038 1039/* 1040 * Initialize the RX descriptors and allocate mbufs for them. Note that 1041 * we arrange the descriptors in a closed ring, so that the last descriptor 1042 * points back to the first. 1043 */ 1044static int nge_list_rx_init(sc) 1045 struct nge_softc *sc; 1046{ 1047 struct nge_list_data *ld; 1048 struct nge_ring_data *cd; 1049 int i; 1050 1051 ld = sc->nge_ldata; 1052 cd = &sc->nge_cdata; 1053 1054 for (i = 0; i < NGE_RX_LIST_CNT; i++) { 1055 if (nge_newbuf(sc, &ld->nge_rx_list[i], NULL) == ENOBUFS) 1056 return(ENOBUFS); 1057 if (i == (NGE_RX_LIST_CNT - 1)) { 1058 ld->nge_rx_list[i].nge_nextdesc = 1059 &ld->nge_rx_list[0]; 1060 ld->nge_rx_list[i].nge_next = 1061 vtophys(&ld->nge_rx_list[0]); 1062 } else { 1063 ld->nge_rx_list[i].nge_nextdesc = 1064 &ld->nge_rx_list[i + 1]; 1065 ld->nge_rx_list[i].nge_next = 1066 vtophys(&ld->nge_rx_list[i + 1]); 1067 } 1068 } 1069 1070 cd->nge_rx_prod = 0; 1071 1072 return(0); 1073} 1074 1075/* 1076 * Initialize an RX descriptor and attach an MBUF cluster. 1077 */ 1078static int nge_newbuf(sc, c, m) 1079 struct nge_softc *sc; 1080 struct nge_desc *c; 1081 struct mbuf *m; 1082{ 1083 struct mbuf *m_new = NULL; 1084 caddr_t *buf = NULL; 1085 1086 if (m == NULL) { 1087 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1088 if (m_new == NULL) { 1089 printf("nge%d: no memory for rx list " 1090 "-- packet dropped!\n", sc->nge_unit); 1091 return(ENOBUFS); 1092 } 1093 1094 /* Allocate the jumbo buffer */ 1095 buf = nge_jalloc(sc); 1096 if (buf == NULL) { 1097#ifdef NGE_VERBOSE 1098 printf("nge%d: jumbo allocation failed " 1099 "-- packet dropped!\n", sc->nge_unit); 1100#endif 1101 m_freem(m_new); 1102 return(ENOBUFS); 1103 } 1104 /* Attach the buffer to the mbuf */ 1105 m_new->m_data = (void *)buf; 1106 m_new->m_len = m_new->m_pkthdr.len = NGE_JUMBO_FRAMELEN; 1107 MEXTADD(m_new, buf, NGE_JUMBO_FRAMELEN, nge_jfree, 1108 (struct nge_softc *)sc, 0, EXT_NET_DRV); 1109 } else { 1110 m_new = m; 1111 m_new->m_len = m_new->m_pkthdr.len = NGE_JUMBO_FRAMELEN; 1112 m_new->m_data = m_new->m_ext.ext_buf; 1113 } 1114 1115 m_adj(m_new, sizeof(u_int64_t)); 1116 1117 c->nge_mbuf = m_new; 1118 c->nge_ptr = vtophys(mtod(m_new, caddr_t)); 1119 c->nge_ctl = m_new->m_len; 1120 c->nge_extsts = 0; 1121 1122 return(0); 1123} 1124 1125static int nge_alloc_jumbo_mem(sc) 1126 struct nge_softc *sc; 1127{ 1128 caddr_t ptr; 1129 register int i; 1130 struct nge_jpool_entry *entry; 1131 1132 /* Grab a big chunk o' storage. */ 1133 sc->nge_cdata.nge_jumbo_buf = contigmalloc(NGE_JMEM, M_DEVBUF, 1134 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1135 1136 if (sc->nge_cdata.nge_jumbo_buf == NULL) { 1137 printf("nge%d: no memory for jumbo buffers!\n", sc->nge_unit); 1138 return(ENOBUFS); 1139 } 1140 1141 SLIST_INIT(&sc->nge_jfree_listhead); 1142 SLIST_INIT(&sc->nge_jinuse_listhead); 1143 1144 /* 1145 * Now divide it up into 9K pieces and save the addresses 1146 * in an array. 1147 */ 1148 ptr = sc->nge_cdata.nge_jumbo_buf; 1149 for (i = 0; i < NGE_JSLOTS; i++) { 1150 sc->nge_cdata.nge_jslots[i] = ptr; 1151 ptr += NGE_JLEN; 1152 entry = malloc(sizeof(struct nge_jpool_entry), 1153 M_DEVBUF, M_NOWAIT); 1154 if (entry == NULL) { 1155 printf("nge%d: no memory for jumbo " 1156 "buffer queue!\n", sc->nge_unit); 1157 return(ENOBUFS); 1158 } 1159 entry->slot = i; 1160 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead, 1161 entry, jpool_entries); 1162 } 1163 1164 return(0); 1165} 1166 1167static void nge_free_jumbo_mem(sc) 1168 struct nge_softc *sc; 1169{ 1170 register int i; 1171 struct nge_jpool_entry *entry; 1172 1173 for (i = 0; i < NGE_JSLOTS; i++) { 1174 entry = SLIST_FIRST(&sc->nge_jfree_listhead); 1175 SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jpool_entries); 1176 free(entry, M_DEVBUF); 1177 } 1178 1179 contigfree(sc->nge_cdata.nge_jumbo_buf, NGE_JMEM, M_DEVBUF); 1180 1181 return; 1182} 1183 1184/* 1185 * Allocate a jumbo buffer. 1186 */ 1187static void *nge_jalloc(sc) 1188 struct nge_softc *sc; 1189{ 1190 struct nge_jpool_entry *entry; 1191 1192 entry = SLIST_FIRST(&sc->nge_jfree_listhead); 1193 1194 if (entry == NULL) { 1195#ifdef NGE_VERBOSE 1196 printf("nge%d: no free jumbo buffers\n", sc->nge_unit); 1197#endif 1198 return(NULL); 1199 } 1200 1201 SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jpool_entries); 1202 SLIST_INSERT_HEAD(&sc->nge_jinuse_listhead, entry, jpool_entries); 1203 return(sc->nge_cdata.nge_jslots[entry->slot]); 1204} 1205 1206/* 1207 * Release a jumbo buffer. 1208 */ 1209static void nge_jfree(buf, args) 1210 caddr_t buf; 1211 void *args; 1212{ 1213 struct nge_softc *sc; 1214 int i; 1215 struct nge_jpool_entry *entry; 1216 1217 /* Extract the softc struct pointer. */ 1218 sc = args; 1219 1220 if (sc == NULL) 1221 panic("nge_jfree: can't find softc pointer!"); 1222 1223 /* calculate the slot this buffer belongs to */ 1224 i = ((vm_offset_t)buf 1225 - (vm_offset_t)sc->nge_cdata.nge_jumbo_buf) / NGE_JLEN; 1226 1227 if ((i < 0) || (i >= NGE_JSLOTS)) 1228 panic("nge_jfree: asked to free buffer that we don't manage!"); 1229 1230 entry = SLIST_FIRST(&sc->nge_jinuse_listhead); 1231 if (entry == NULL) 1232 panic("nge_jfree: buffer not in use!"); 1233 entry->slot = i; 1234 SLIST_REMOVE_HEAD(&sc->nge_jinuse_listhead, jpool_entries); 1235 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead, entry, jpool_entries); 1236 1237 return; 1238} 1239/* 1240 * A frame has been uploaded: pass the resulting mbuf chain up to 1241 * the higher level protocols. 1242 */ 1243static void nge_rxeof(sc) 1244 struct nge_softc *sc; 1245{ 1246 struct ether_header *eh; 1247 struct mbuf *m; 1248 struct ifnet *ifp; 1249 struct nge_desc *cur_rx; 1250 int i, total_len = 0; 1251 u_int32_t rxstat; 1252 1253 ifp = &sc->arpcom.ac_if; 1254 i = sc->nge_cdata.nge_rx_prod; 1255 1256 while(NGE_OWNDESC(&sc->nge_ldata->nge_rx_list[i])) { 1257 struct mbuf *m0 = NULL; 1258 u_int32_t extsts; 1259 1260 cur_rx = &sc->nge_ldata->nge_rx_list[i]; 1261 rxstat = cur_rx->nge_rxstat; 1262 extsts = cur_rx->nge_extsts; 1263 m = cur_rx->nge_mbuf; 1264 cur_rx->nge_mbuf = NULL; 1265 total_len = NGE_RXBYTES(cur_rx); 1266 NGE_INC(i, NGE_RX_LIST_CNT); 1267 1268 /* 1269 * If an error occurs, update stats, clear the 1270 * status word and leave the mbuf cluster in place: 1271 * it should simply get re-used next time this descriptor 1272 * comes up in the ring. 1273 */ 1274 if (!(rxstat & NGE_CMDSTS_PKT_OK)) { 1275 ifp->if_ierrors++; 1276 nge_newbuf(sc, cur_rx, m); 1277 continue; 1278 } 1279 1280 1281 /* 1282 * Ok. NatSemi really screwed up here. This is the 1283 * only gigE chip I know of with alignment constraints 1284 * on receive buffers. RX buffers must be 64-bit aligned. 1285 */ 1286#ifdef __i386__ 1287 /* 1288 * By popular demand, ignore the alignment problems 1289 * on the Intel x86 platform. The performance hit 1290 * incurred due to unaligned accesses is much smaller 1291 * than the hit produced by forcing buffer copies all 1292 * the time, especially with jumbo frames. We still 1293 * need to fix up the alignment everywhere else though. 1294 */ 1295 if (nge_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 1296#endif 1297 m0 = m_devget(mtod(m, char *), total_len, 1298 ETHER_ALIGN, ifp, NULL); 1299 nge_newbuf(sc, cur_rx, m); 1300 if (m0 == NULL) { 1301 printf("nge%d: no receive buffers " 1302 "available -- packet dropped!\n", 1303 sc->nge_unit); 1304 ifp->if_ierrors++; 1305 continue; 1306 } 1307 m = m0; 1308#ifdef __i386__ 1309 } else { 1310 m->m_pkthdr.rcvif = ifp; 1311 m->m_pkthdr.len = m->m_len = total_len; 1312 } 1313#endif 1314 1315 ifp->if_ipackets++; 1316 eh = mtod(m, struct ether_header *); 1317 1318 /* Remove header from mbuf and pass it on. */ 1319 m_adj(m, sizeof(struct ether_header)); 1320 1321 /* Do IP checksum checking. */ 1322 if (extsts & NGE_RXEXTSTS_IPPKT) 1323 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1324 if (!(extsts & NGE_RXEXTSTS_IPCSUMERR)) 1325 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1326 if ((extsts & NGE_RXEXTSTS_TCPPKT && 1327 !(extsts & NGE_RXEXTSTS_TCPCSUMERR)) || 1328 (extsts & NGE_RXEXTSTS_UDPPKT && 1329 !(extsts & NGE_RXEXTSTS_UDPCSUMERR))) { 1330 m->m_pkthdr.csum_flags |= 1331 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1332 m->m_pkthdr.csum_data = 0xffff; 1333 } 1334 1335 /* 1336 * If we received a packet with a vlan tag, pass it 1337 * to vlan_input() instead of ether_input(). 1338 */ 1339 if (extsts & NGE_RXEXTSTS_VLANPKT) { 1340 VLAN_INPUT_TAG(eh, m, extsts & NGE_RXEXTSTS_VTCI); 1341 continue; 1342 } 1343 1344 ether_input(ifp, eh, m); 1345 } 1346 1347 sc->nge_cdata.nge_rx_prod = i; 1348 1349 return; 1350} 1351 1352void nge_rxeoc(sc) 1353 struct nge_softc *sc; 1354{ 1355 struct ifnet *ifp; 1356 1357 ifp = &sc->arpcom.ac_if; 1358 nge_rxeof(sc); 1359 ifp->if_flags &= ~IFF_RUNNING; 1360 nge_init(sc); 1361 return; 1362} 1363 1364/* 1365 * A frame was downloaded to the chip. It's safe for us to clean up 1366 * the list buffers. 1367 */ 1368 1369static void nge_txeof(sc) 1370 struct nge_softc *sc; 1371{ 1372 struct nge_desc *cur_tx = NULL; 1373 struct ifnet *ifp; 1374 u_int32_t idx; 1375 1376 ifp = &sc->arpcom.ac_if; 1377 1378 /* Clear the timeout timer. */ 1379 ifp->if_timer = 0; 1380 1381 /* 1382 * Go through our tx list and free mbufs for those 1383 * frames that have been transmitted. 1384 */ 1385 idx = sc->nge_cdata.nge_tx_cons; 1386 while (idx != sc->nge_cdata.nge_tx_prod) { 1387 cur_tx = &sc->nge_ldata->nge_tx_list[idx]; 1388 1389 if (NGE_OWNDESC(cur_tx)) 1390 break; 1391 1392 if (cur_tx->nge_ctl & NGE_CMDSTS_MORE) { 1393 sc->nge_cdata.nge_tx_cnt--; 1394 NGE_INC(idx, NGE_TX_LIST_CNT); 1395 continue; 1396 } 1397 1398 if (!(cur_tx->nge_ctl & NGE_CMDSTS_PKT_OK)) { 1399 ifp->if_oerrors++; 1400 if (cur_tx->nge_txstat & NGE_TXSTAT_EXCESSCOLLS) 1401 ifp->if_collisions++; 1402 if (cur_tx->nge_txstat & NGE_TXSTAT_OUTOFWINCOLL) 1403 ifp->if_collisions++; 1404 } 1405 1406 ifp->if_collisions += 1407 (cur_tx->nge_txstat & NGE_TXSTAT_COLLCNT) >> 16; 1408 1409 ifp->if_opackets++; 1410 if (cur_tx->nge_mbuf != NULL) { 1411 m_freem(cur_tx->nge_mbuf); 1412 cur_tx->nge_mbuf = NULL; 1413 } 1414 1415 sc->nge_cdata.nge_tx_cnt--; 1416 NGE_INC(idx, NGE_TX_LIST_CNT); 1417 ifp->if_timer = 0; 1418 } 1419 1420 sc->nge_cdata.nge_tx_cons = idx; 1421 1422 if (cur_tx != NULL) 1423 ifp->if_flags &= ~IFF_OACTIVE; 1424 1425 return; 1426} 1427 1428static void nge_tick(xsc) 1429 void *xsc; 1430{ 1431 struct nge_softc *sc; 1432 struct mii_data *mii; 1433 struct ifnet *ifp; 1434 int s; 1435 1436 s = splimp(); 1437 1438 sc = xsc; 1439 ifp = &sc->arpcom.ac_if; 1440 1441 mii = device_get_softc(sc->nge_miibus); 1442 mii_tick(mii); 1443 1444 if (!sc->nge_link) { 1445 if (mii->mii_media_status & IFM_ACTIVE && 1446 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1447 sc->nge_link++; 1448 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX) 1449 printf("nge%d: gigabit link up\n", 1450 sc->nge_unit); 1451 if (ifp->if_snd.ifq_head != NULL) 1452 nge_start(ifp); 1453 } else 1454 sc->nge_stat_ch = timeout(nge_tick, sc, hz); 1455 } 1456 1457 1458 splx(s); 1459 1460 return; 1461} 1462 1463static void nge_intr(arg) 1464 void *arg; 1465{ 1466 struct nge_softc *sc; 1467 struct ifnet *ifp; 1468 u_int32_t status; 1469 1470 sc = arg; 1471 ifp = &sc->arpcom.ac_if; 1472 1473 /* Supress unwanted interrupts */ 1474 if (!(ifp->if_flags & IFF_UP)) { 1475 nge_stop(sc); 1476 return; 1477 } 1478 1479 /* Disable interrupts. */ 1480 CSR_WRITE_4(sc, NGE_IER, 0); 1481 1482 for (;;) { 1483 /* Reading the ISR register clears all interrupts. */ 1484 status = CSR_READ_4(sc, NGE_ISR); 1485 1486 if ((status & NGE_INTRS) == 0) 1487 break; 1488 1489 if ((status & NGE_ISR_TX_DESC_OK) || 1490 (status & NGE_ISR_TX_ERR) || 1491 (status & NGE_ISR_TX_OK) || 1492 (status & NGE_ISR_TX_IDLE)) 1493 nge_txeof(sc); 1494 1495 if ((status & NGE_ISR_RX_DESC_OK) || 1496 (status & NGE_ISR_RX_ERR) || 1497 (status & NGE_ISR_RX_OFLOW) || 1498 (status & NGE_ISR_RX_OK)) 1499 nge_rxeof(sc); 1500#ifdef notdef 1501 if ((status & NGE_ISR_RX_OFLOW)) 1502 nge_rxeoc(sc); 1503#endif 1504 if (status & NGE_ISR_SYSERR) { 1505 nge_reset(sc); 1506 ifp->if_flags &= ~IFF_RUNNING; 1507 nge_init(sc); 1508 } 1509 1510 if (status & NGE_IMR_PHY_INTR) { 1511 sc->nge_link = 0; 1512 nge_tick(sc); 1513 } 1514 } 1515 1516 /* Re-enable interrupts. */ 1517 CSR_WRITE_4(sc, NGE_IER, 1); 1518 1519 if (ifp->if_snd.ifq_head != NULL) 1520 nge_start(ifp); 1521 1522 return; 1523} 1524 1525/* 1526 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1527 * pointers to the fragment pointers. 1528 */ 1529static int nge_encap(sc, m_head, txidx) 1530 struct nge_softc *sc; 1531 struct mbuf *m_head; 1532 u_int32_t *txidx; 1533{ 1534 struct nge_desc *f = NULL; 1535 struct mbuf *m; 1536 int frag, cur, cnt = 0; 1537 struct ifvlan *ifv = NULL; 1538 1539 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 1540 m_head->m_pkthdr.rcvif != NULL && 1541 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN) 1542 ifv = m_head->m_pkthdr.rcvif->if_softc; 1543 1544 /* 1545 * Start packing the mbufs in this chain into 1546 * the fragment pointers. Stop when we run out 1547 * of fragments or hit the end of the mbuf chain. 1548 */ 1549 m = m_head; 1550 cur = frag = *txidx; 1551 1552 for (m = m_head; m != NULL; m = m->m_next) { 1553 if (m->m_len != 0) { 1554 if ((NGE_TX_LIST_CNT - 1555 (sc->nge_cdata.nge_tx_cnt + cnt)) < 2) 1556 return(ENOBUFS); 1557 f = &sc->nge_ldata->nge_tx_list[frag]; 1558 f->nge_ctl = NGE_CMDSTS_MORE | m->m_len; 1559 f->nge_ptr = vtophys(mtod(m, vm_offset_t)); 1560 if (cnt != 0) 1561 f->nge_ctl |= NGE_CMDSTS_OWN; 1562 cur = frag; 1563 NGE_INC(frag, NGE_TX_LIST_CNT); 1564 cnt++; 1565 } 1566 } 1567 1568 if (m != NULL) 1569 return(ENOBUFS); 1570 1571 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts = 0; 1572 if (m_head->m_pkthdr.csum_flags) { 1573 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1574 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1575 NGE_TXEXTSTS_IPCSUM; 1576 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1577 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1578 NGE_TXEXTSTS_TCPCSUM; 1579 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 1580 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1581 NGE_TXEXTSTS_UDPCSUM; 1582 } 1583 1584 if (ifv != NULL) { 1585 sc->nge_ldata->nge_tx_list[cur].nge_extsts |= 1586 (NGE_TXEXTSTS_VLANPKT|ifv->ifv_tag); 1587 } 1588 1589 sc->nge_ldata->nge_tx_list[cur].nge_mbuf = m_head; 1590 sc->nge_ldata->nge_tx_list[cur].nge_ctl &= ~NGE_CMDSTS_MORE; 1591 sc->nge_ldata->nge_tx_list[*txidx].nge_ctl |= NGE_CMDSTS_OWN; 1592 sc->nge_cdata.nge_tx_cnt += cnt; 1593 *txidx = frag; 1594 1595 return(0); 1596} 1597 1598/* 1599 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1600 * to the mbuf data regions directly in the transmit lists. We also save a 1601 * copy of the pointers since the transmit list fragment pointers are 1602 * physical addresses. 1603 */ 1604 1605static void nge_start(ifp) 1606 struct ifnet *ifp; 1607{ 1608 struct nge_softc *sc; 1609 struct mbuf *m_head = NULL; 1610 u_int32_t idx; 1611 1612 sc = ifp->if_softc; 1613 1614 if (!sc->nge_link) 1615 return; 1616 1617 idx = sc->nge_cdata.nge_tx_prod; 1618 1619 if (ifp->if_flags & IFF_OACTIVE) 1620 return; 1621 1622 while(sc->nge_ldata->nge_tx_list[idx].nge_mbuf == NULL) { 1623 IF_DEQUEUE(&ifp->if_snd, m_head); 1624 if (m_head == NULL) 1625 break; 1626 1627 if (nge_encap(sc, m_head, &idx)) { 1628 IF_PREPEND(&ifp->if_snd, m_head); 1629 ifp->if_flags |= IFF_OACTIVE; 1630 break; 1631 } 1632 1633 /* 1634 * If there's a BPF listener, bounce a copy of this frame 1635 * to him. 1636 */ 1637 if (ifp->if_bpf) 1638 bpf_mtap(ifp, m_head); 1639 1640 } 1641 1642 /* Transmit */ 1643 sc->nge_cdata.nge_tx_prod = idx; 1644 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_ENABLE); 1645 1646 /* 1647 * Set a timeout in case the chip goes out to lunch. 1648 */ 1649 ifp->if_timer = 5; 1650 1651 return; 1652} 1653 1654static void nge_init(xsc) 1655 void *xsc; 1656{ 1657 struct nge_softc *sc = xsc; 1658 struct ifnet *ifp = &sc->arpcom.ac_if; 1659 struct mii_data *mii; 1660 int s; 1661 1662 if (ifp->if_flags & IFF_RUNNING) 1663 return; 1664 1665 s = splimp(); 1666 1667 /* 1668 * Cancel pending I/O and free all RX/TX buffers. 1669 */ 1670 nge_stop(sc); 1671 1672 mii = device_get_softc(sc->nge_miibus); 1673 1674 /* Set MAC address */ 1675 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0); 1676 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1677 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1678 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR1); 1679 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1680 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1681 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR2); 1682 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1683 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1684 1685 /* Init circular RX list. */ 1686 if (nge_list_rx_init(sc) == ENOBUFS) { 1687 printf("nge%d: initialization failed: no " 1688 "memory for rx buffers\n", sc->nge_unit); 1689 nge_stop(sc); 1690 (void)splx(s); 1691 return; 1692 } 1693 1694 /* 1695 * Init tx descriptors. 1696 */ 1697 nge_list_tx_init(sc); 1698 1699 /* 1700 * For the NatSemi chip, we have to explicitly enable the 1701 * reception of ARP frames, as well as turn on the 'perfect 1702 * match' filter where we store the station address, otherwise 1703 * we won't receive unicasts meant for this host. 1704 */ 1705 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ARP); 1706 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_PERFECT); 1707 1708 /* If we want promiscuous mode, set the allframes bit. */ 1709 if (ifp->if_flags & IFF_PROMISC) { 1710 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS); 1711 } else { 1712 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS); 1713 } 1714 1715 /* 1716 * Set the capture broadcast bit to capture broadcast frames. 1717 */ 1718 if (ifp->if_flags & IFF_BROADCAST) { 1719 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD); 1720 } else { 1721 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD); 1722 } 1723 1724 /* 1725 * Load the multicast filter. 1726 */ 1727 nge_setmulti(sc); 1728 1729 /* Turn the receive filter on */ 1730 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ENABLE); 1731 1732 /* 1733 * Load the address of the RX and TX lists. 1734 */ 1735 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 1736 vtophys(&sc->nge_ldata->nge_rx_list[0])); 1737 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 1738 vtophys(&sc->nge_ldata->nge_tx_list[0])); 1739 1740 /* Set RX configuration */ 1741 CSR_WRITE_4(sc, NGE_RX_CFG, NGE_RXCFG); 1742 /* 1743 * Enable hardware checksum validation for all IPv4 1744 * packets, do not reject packets with bad checksums. 1745 */ 1746 CSR_WRITE_4(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_IPCSUM_ENB); 1747 1748 /* 1749 * Tell the chip to detect and strip VLAN tag info from 1750 * received frames. The tag will be provided in the extsts 1751 * field in the RX descriptors. 1752 */ 1753 NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL, 1754 NGE_VIPRXCTL_TAG_DETECT_ENB|NGE_VIPRXCTL_TAG_STRIP_ENB); 1755 1756 /* Set TX configuration */ 1757 CSR_WRITE_4(sc, NGE_TX_CFG, NGE_TXCFG); 1758 1759 /* 1760 * Enable TX IPv4 checksumming on a per-packet basis. 1761 */ 1762 CSR_WRITE_4(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_CSUM_PER_PKT); 1763 1764 /* 1765 * Tell the chip to insert VLAN tags on a per-packet basis as 1766 * dictated by the code in the frame encapsulation routine. 1767 */ 1768 NGE_SETBIT(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_TAG_PER_PKT); 1769 1770 /* Set full/half duplex mode. */ 1771 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1772 NGE_SETBIT(sc, NGE_TX_CFG, 1773 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1774 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1775 } else { 1776 NGE_CLRBIT(sc, NGE_TX_CFG, 1777 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1778 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1779 } 1780 1781 /* 1782 * Enable the delivery of PHY interrupts based on 1783 * link/speed/duplex status changes. Also enable the 1784 * extsts field in the DMA descriptors (needed for 1785 * TCP/IP checksum offload on transmit). 1786 */ 1787 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_PHYINTR_SPD| 1788 NGE_CFG_PHYINTR_LNK|NGE_CFG_PHYINTR_DUP|NGE_CFG_EXTSTS_ENB); 1789 1790 /* 1791 * Configure interrupt holdoff (moderation). We can 1792 * have the chip delay interrupt delivery for a certain 1793 * period. Units are in 100us, and the max setting 1794 * is 25500us (0xFF x 100us). Default is a 100us holdoff. 1795 */ 1796 CSR_WRITE_4(sc, NGE_IHR, 0x01); 1797 1798 /* 1799 * Enable interrupts. 1800 */ 1801 CSR_WRITE_4(sc, NGE_IMR, NGE_INTRS); 1802 CSR_WRITE_4(sc, NGE_IER, 1); 1803 1804 /* Enable receiver and transmitter. */ 1805 NGE_CLRBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE); 1806 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1807 1808 nge_ifmedia_upd(ifp); 1809 1810 ifp->if_flags |= IFF_RUNNING; 1811 ifp->if_flags &= ~IFF_OACTIVE; 1812 1813 (void)splx(s); 1814 1815 return; 1816} 1817 1818/* 1819 * Set media options. 1820 */ 1821static int nge_ifmedia_upd(ifp) 1822 struct ifnet *ifp; 1823{ 1824 struct nge_softc *sc; 1825 struct mii_data *mii; 1826 1827 sc = ifp->if_softc; 1828 1829 mii = device_get_softc(sc->nge_miibus); 1830 sc->nge_link = 0; 1831 if (mii->mii_instance) { 1832 struct mii_softc *miisc; 1833 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1834 miisc = LIST_NEXT(miisc, mii_list)) 1835 mii_phy_reset(miisc); 1836 } 1837 mii_mediachg(mii); 1838 1839 return(0); 1840} 1841 1842/* 1843 * Report current media status. 1844 */ 1845static void nge_ifmedia_sts(ifp, ifmr) 1846 struct ifnet *ifp; 1847 struct ifmediareq *ifmr; 1848{ 1849 struct nge_softc *sc; 1850 struct mii_data *mii; 1851 1852 sc = ifp->if_softc; 1853 1854 mii = device_get_softc(sc->nge_miibus); 1855 mii_pollstat(mii); 1856 ifmr->ifm_active = mii->mii_media_active; 1857 ifmr->ifm_status = mii->mii_media_status; 1858 1859 return; 1860} 1861 1862static int nge_ioctl(ifp, command, data) 1863 struct ifnet *ifp; 1864 u_long command; 1865 caddr_t data; 1866{ 1867 struct nge_softc *sc = ifp->if_softc; 1868 struct ifreq *ifr = (struct ifreq *) data; 1869 struct mii_data *mii; 1870 int s, error = 0; 1871 1872 s = splimp(); 1873 1874 switch(command) { 1875 case SIOCSIFADDR: 1876 case SIOCGIFADDR: 1877 error = ether_ioctl(ifp, command, data); 1878 break; 1879 case SIOCSIFMTU: 1880 if (ifr->ifr_mtu > NGE_JUMBO_MTU) 1881 error = EINVAL; 1882 else { 1883 ifp->if_mtu = ifr->ifr_mtu; 1884 /* 1885 * Workaround: if the MTU is larger than 1886 * 8152 (TX FIFO size minus 64 minus 18), turn off 1887 * TX checksum offloading. 1888 */ 1889 if (ifr->ifr_mtu >= 8152) 1890 ifp->if_hwassist = 0; 1891 else 1892 ifp->if_hwassist = NGE_CSUM_FEATURES; 1893 } 1894 break; 1895 case SIOCSIFFLAGS: 1896 if (ifp->if_flags & IFF_UP) { 1897 if (ifp->if_flags & IFF_RUNNING && 1898 ifp->if_flags & IFF_PROMISC && 1899 !(sc->nge_if_flags & IFF_PROMISC)) { 1900 NGE_SETBIT(sc, NGE_RXFILT_CTL, 1901 NGE_RXFILTCTL_ALLPHYS| 1902 NGE_RXFILTCTL_ALLMULTI); 1903 } else if (ifp->if_flags & IFF_RUNNING && 1904 !(ifp->if_flags & IFF_PROMISC) && 1905 sc->nge_if_flags & IFF_PROMISC) { 1906 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 1907 NGE_RXFILTCTL_ALLPHYS); 1908 if (!(ifp->if_flags & IFF_ALLMULTI)) 1909 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 1910 NGE_RXFILTCTL_ALLMULTI); 1911 } else { 1912 ifp->if_flags &= ~IFF_RUNNING; 1913 nge_init(sc); 1914 } 1915 } else { 1916 if (ifp->if_flags & IFF_RUNNING) 1917 nge_stop(sc); 1918 } 1919 sc->nge_if_flags = ifp->if_flags; 1920 error = 0; 1921 break; 1922 case SIOCADDMULTI: 1923 case SIOCDELMULTI: 1924 nge_setmulti(sc); 1925 error = 0; 1926 break; 1927 case SIOCGIFMEDIA: 1928 case SIOCSIFMEDIA: 1929 mii = device_get_softc(sc->nge_miibus); 1930 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1931 break; 1932 default: 1933 error = EINVAL; 1934 break; 1935 } 1936 1937 (void)splx(s); 1938 1939 return(error); 1940} 1941 1942static void nge_watchdog(ifp) 1943 struct ifnet *ifp; 1944{ 1945 struct nge_softc *sc; 1946 1947 sc = ifp->if_softc; 1948 1949 ifp->if_oerrors++; 1950 printf("nge%d: watchdog timeout\n", sc->nge_unit); 1951 1952 nge_stop(sc); 1953 nge_reset(sc); 1954 ifp->if_flags &= ~IFF_RUNNING; 1955 nge_init(sc); 1956 1957 if (ifp->if_snd.ifq_head != NULL) 1958 nge_start(ifp); 1959 1960 return; 1961} 1962 1963/* 1964 * Stop the adapter and free any mbufs allocated to the 1965 * RX and TX lists. 1966 */ 1967static void nge_stop(sc) 1968 struct nge_softc *sc; 1969{ 1970 register int i; 1971 struct ifnet *ifp; 1972 struct ifmedia_entry *ifm; 1973 struct mii_data *mii; 1974 int mtmp, itmp; 1975 1976 ifp = &sc->arpcom.ac_if; 1977 ifp->if_timer = 0; 1978 mii = device_get_softc(sc->nge_miibus); 1979 1980 untimeout(nge_tick, sc, sc->nge_stat_ch); 1981 CSR_WRITE_4(sc, NGE_IER, 0); 1982 CSR_WRITE_4(sc, NGE_IMR, 0); 1983 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE); 1984 DELAY(1000); 1985 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 0); 1986 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 0); 1987 1988 /* 1989 * Isolate/power down the PHY, but leave the media selection 1990 * unchanged so that things will be put back to normal when 1991 * we bring the interface back up. 1992 */ 1993 itmp = ifp->if_flags; 1994 ifp->if_flags |= IFF_UP; 1995 ifm = mii->mii_media.ifm_cur; 1996 mtmp = ifm->ifm_media; 1997 ifm->ifm_media = IFM_ETHER|IFM_NONE; 1998 mii_mediachg(mii); 1999 ifm->ifm_media = mtmp; 2000 ifp->if_flags = itmp; 2001 2002 sc->nge_link = 0; 2003 2004 /* 2005 * Free data in the RX lists. 2006 */ 2007 for (i = 0; i < NGE_RX_LIST_CNT; i++) { 2008 if (sc->nge_ldata->nge_rx_list[i].nge_mbuf != NULL) { 2009 m_freem(sc->nge_ldata->nge_rx_list[i].nge_mbuf); 2010 sc->nge_ldata->nge_rx_list[i].nge_mbuf = NULL; 2011 } 2012 } 2013 bzero((char *)&sc->nge_ldata->nge_rx_list, 2014 sizeof(sc->nge_ldata->nge_rx_list)); 2015 2016 /* 2017 * Free the TX list buffers. 2018 */ 2019 for (i = 0; i < NGE_TX_LIST_CNT; i++) { 2020 if (sc->nge_ldata->nge_tx_list[i].nge_mbuf != NULL) { 2021 m_freem(sc->nge_ldata->nge_tx_list[i].nge_mbuf); 2022 sc->nge_ldata->nge_tx_list[i].nge_mbuf = NULL; 2023 } 2024 } 2025 2026 bzero((char *)&sc->nge_ldata->nge_tx_list, 2027 sizeof(sc->nge_ldata->nge_tx_list)); 2028 2029 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2030 2031 return; 2032} 2033 2034/* 2035 * Stop all chip I/O so that the kernel's probe routines don't 2036 * get confused by errant DMAs when rebooting. 2037 */ 2038static void nge_shutdown(dev) 2039 device_t dev; 2040{ 2041 struct nge_softc *sc; 2042 2043 sc = device_get_softc(dev); 2044 2045 nge_reset(sc); 2046 nge_stop(sc); 2047 2048 return; 2049} 2050