if_nge.c revision 79798
1/* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2000, 2001 4 * Bill Paul <wpaul@bsdi.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: head/sys/dev/nge/if_nge.c 79798 2001-07-16 16:35:09Z wpaul $ 34 */ 35 36/* 37 * National Semiconductor DP83820/DP83821 gigabit ethernet driver 38 * for FreeBSD. Datasheets are available from: 39 * 40 * http://www.national.com/ds/DP/DP83820.pdf 41 * http://www.national.com/ds/DP/DP83821.pdf 42 * 43 * These chips are used on several low cost gigabit ethernet NICs 44 * sold by D-Link, Addtron, SMC and Asante. Both parts are 45 * virtually the same, except the 83820 is a 64-bit/32-bit part, 46 * while the 83821 is 32-bit only. 47 * 48 * Many cards also use National gigE transceivers, such as the 49 * DP83891, DP83861 and DP83862 gigPHYTER parts. The DP83861 datasheet 50 * contains a full register description that applies to all of these 51 * components: 52 * 53 * http://www.national.com/ds/DP/DP83861.pdf 54 * 55 * Written by Bill Paul <wpaul@bsdi.com> 56 * BSDi Open Source Solutions 57 */ 58 59/* 60 * The NatSemi DP83820 and 83821 controllers are enhanced versions 61 * of the NatSemi MacPHYTER 10/100 devices. They support 10, 100 62 * and 1000Mbps speeds with 1000baseX (ten bit interface), MII and GMII 63 * ports. Other features include 8K TX FIFO and 32K RX FIFO, TCP/IP 64 * hardware checksum offload (IPv4 only), VLAN tagging and filtering, 65 * priority TX and RX queues, a 2048 bit multicast hash filter, 4 RX pattern 66 * matching buffers, one perfect address filter buffer and interrupt 67 * moderation. The 83820 supports both 64-bit and 32-bit addressing 68 * and data transfers: the 64-bit support can be toggled on or off 69 * via software. This affects the size of certain fields in the DMA 70 * descriptors. 71 * 72 * There are two bugs/misfeatures in the 83820/83821 that I have 73 * discovered so far: 74 * 75 * - Receive buffers must be aligned on 64-bit boundaries, which means 76 * you must resort to copying data in order to fix up the payload 77 * alignment. 78 * 79 * - In order to transmit jumbo frames larger than 8170 bytes, you have 80 * to turn off transmit checksum offloading, because the chip can't 81 * compute the checksum on an outgoing frame unless it fits entirely 82 * within the TX FIFO, which is only 8192 bytes in size. If you have 83 * TX checksum offload enabled and you transmit attempt to transmit a 84 * frame larger than 8170 bytes, the transmitter will wedge. 85 * 86 * To work around the latter problem, TX checksum offload is disabled 87 * if the user selects an MTU larger than 8152 (8170 - 18). 88 */ 89 90#include "vlan.h" 91 92#include <sys/param.h> 93#include <sys/systm.h> 94#include <sys/sockio.h> 95#include <sys/mbuf.h> 96#include <sys/malloc.h> 97#include <sys/kernel.h> 98#include <sys/socket.h> 99 100#include <net/if.h> 101#include <net/if_arp.h> 102#include <net/ethernet.h> 103#include <net/if_dl.h> 104#include <net/if_media.h> 105 106#if NVLAN > 0 107#include <net/if_types.h> 108#include <net/if_vlan_var.h> 109#endif 110 111#include <net/bpf.h> 112 113#include <vm/vm.h> /* for vtophys */ 114#include <vm/pmap.h> /* for vtophys */ 115#include <machine/clock.h> /* for DELAY */ 116#include <machine/bus_pio.h> 117#include <machine/bus_memio.h> 118#include <machine/bus.h> 119#include <machine/resource.h> 120#include <sys/bus.h> 121#include <sys/rman.h> 122 123#include <dev/mii/mii.h> 124#include <dev/mii/miivar.h> 125 126#include <pci/pcireg.h> 127#include <pci/pcivar.h> 128 129#define NGE_USEIOSPACE 130 131#include <dev/nge/if_ngereg.h> 132 133MODULE_DEPEND(nge, miibus, 1, 1, 1); 134 135/* "controller miibus0" required. See GENERIC if you get errors here. */ 136#include "miibus_if.h" 137 138#ifndef lint 139static const char rcsid[] = 140 "$FreeBSD: head/sys/dev/nge/if_nge.c 79798 2001-07-16 16:35:09Z wpaul $"; 141#endif 142 143#define NGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 144 145/* 146 * Various supported device vendors/types and their names. 147 */ 148static struct nge_type nge_devs[] = { 149 { NGE_VENDORID, NGE_DEVICEID, 150 "National Semiconductor Gigabit Ethernet" }, 151 { 0, 0, NULL } 152}; 153 154static int nge_probe __P((device_t)); 155static int nge_attach __P((device_t)); 156static int nge_detach __P((device_t)); 157 158static int nge_alloc_jumbo_mem __P((struct nge_softc *)); 159static void nge_free_jumbo_mem __P((struct nge_softc *)); 160static void *nge_jalloc __P((struct nge_softc *)); 161static void nge_jfree __P((caddr_t, void *)); 162 163static int nge_newbuf __P((struct nge_softc *, 164 struct nge_desc *, 165 struct mbuf *)); 166static int nge_encap __P((struct nge_softc *, 167 struct mbuf *, u_int32_t *)); 168static void nge_rxeof __P((struct nge_softc *)); 169static void nge_rxeoc __P((struct nge_softc *)); 170static void nge_txeof __P((struct nge_softc *)); 171static void nge_intr __P((void *)); 172static void nge_tick __P((void *)); 173static void nge_start __P((struct ifnet *)); 174static int nge_ioctl __P((struct ifnet *, u_long, caddr_t)); 175static void nge_init __P((void *)); 176static void nge_stop __P((struct nge_softc *)); 177static void nge_watchdog __P((struct ifnet *)); 178static void nge_shutdown __P((device_t)); 179static int nge_ifmedia_upd __P((struct ifnet *)); 180static void nge_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 181 182static void nge_delay __P((struct nge_softc *)); 183static void nge_eeprom_idle __P((struct nge_softc *)); 184static void nge_eeprom_putbyte __P((struct nge_softc *, int)); 185static void nge_eeprom_getword __P((struct nge_softc *, int, u_int16_t *)); 186static void nge_read_eeprom __P((struct nge_softc *, caddr_t, int, 187 int, int)); 188 189static void nge_mii_sync __P((struct nge_softc *)); 190static void nge_mii_send __P((struct nge_softc *, u_int32_t, int)); 191static int nge_mii_readreg __P((struct nge_softc *, 192 struct nge_mii_frame *)); 193static int nge_mii_writereg __P((struct nge_softc *, 194 struct nge_mii_frame *)); 195 196static int nge_miibus_readreg __P((device_t, int, int)); 197static int nge_miibus_writereg __P((device_t, int, int, int)); 198static void nge_miibus_statchg __P((device_t)); 199 200static void nge_setmulti __P((struct nge_softc *)); 201static u_int32_t nge_crc __P((struct nge_softc *, caddr_t)); 202static void nge_reset __P((struct nge_softc *)); 203static int nge_list_rx_init __P((struct nge_softc *)); 204static int nge_list_tx_init __P((struct nge_softc *)); 205 206#ifdef NGE_USEIOSPACE 207#define NGE_RES SYS_RES_IOPORT 208#define NGE_RID NGE_PCI_LOIO 209#else 210#define NGE_RES SYS_RES_MEMORY 211#define NGE_RID NGE_PCI_LOMEM 212#endif 213 214static device_method_t nge_methods[] = { 215 /* Device interface */ 216 DEVMETHOD(device_probe, nge_probe), 217 DEVMETHOD(device_attach, nge_attach), 218 DEVMETHOD(device_detach, nge_detach), 219 DEVMETHOD(device_shutdown, nge_shutdown), 220 221 /* bus interface */ 222 DEVMETHOD(bus_print_child, bus_generic_print_child), 223 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 224 225 /* MII interface */ 226 DEVMETHOD(miibus_readreg, nge_miibus_readreg), 227 DEVMETHOD(miibus_writereg, nge_miibus_writereg), 228 DEVMETHOD(miibus_statchg, nge_miibus_statchg), 229 230 { 0, 0 } 231}; 232 233static driver_t nge_driver = { 234 "nge", 235 nge_methods, 236 sizeof(struct nge_softc) 237}; 238 239static devclass_t nge_devclass; 240 241DRIVER_MODULE(if_nge, pci, nge_driver, nge_devclass, 0, 0); 242DRIVER_MODULE(miibus, nge, miibus_driver, miibus_devclass, 0, 0); 243 244#define NGE_SETBIT(sc, reg, x) \ 245 CSR_WRITE_4(sc, reg, \ 246 CSR_READ_4(sc, reg) | (x)) 247 248#define NGE_CLRBIT(sc, reg, x) \ 249 CSR_WRITE_4(sc, reg, \ 250 CSR_READ_4(sc, reg) & ~(x)) 251 252#define SIO_SET(x) \ 253 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | x) 254 255#define SIO_CLR(x) \ 256 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~x) 257 258static void nge_delay(sc) 259 struct nge_softc *sc; 260{ 261 int idx; 262 263 for (idx = (300 / 33) + 1; idx > 0; idx--) 264 CSR_READ_4(sc, NGE_CSR); 265 266 return; 267} 268 269static void nge_eeprom_idle(sc) 270 struct nge_softc *sc; 271{ 272 register int i; 273 274 SIO_SET(NGE_MEAR_EE_CSEL); 275 nge_delay(sc); 276 SIO_SET(NGE_MEAR_EE_CLK); 277 nge_delay(sc); 278 279 for (i = 0; i < 25; i++) { 280 SIO_CLR(NGE_MEAR_EE_CLK); 281 nge_delay(sc); 282 SIO_SET(NGE_MEAR_EE_CLK); 283 nge_delay(sc); 284 } 285 286 SIO_CLR(NGE_MEAR_EE_CLK); 287 nge_delay(sc); 288 SIO_CLR(NGE_MEAR_EE_CSEL); 289 nge_delay(sc); 290 CSR_WRITE_4(sc, NGE_MEAR, 0x00000000); 291 292 return; 293} 294 295/* 296 * Send a read command and address to the EEPROM, check for ACK. 297 */ 298static void nge_eeprom_putbyte(sc, addr) 299 struct nge_softc *sc; 300 int addr; 301{ 302 register int d, i; 303 304 d = addr | NGE_EECMD_READ; 305 306 /* 307 * Feed in each bit and stobe the clock. 308 */ 309 for (i = 0x400; i; i >>= 1) { 310 if (d & i) { 311 SIO_SET(NGE_MEAR_EE_DIN); 312 } else { 313 SIO_CLR(NGE_MEAR_EE_DIN); 314 } 315 nge_delay(sc); 316 SIO_SET(NGE_MEAR_EE_CLK); 317 nge_delay(sc); 318 SIO_CLR(NGE_MEAR_EE_CLK); 319 nge_delay(sc); 320 } 321 322 return; 323} 324 325/* 326 * Read a word of data stored in the EEPROM at address 'addr.' 327 */ 328static void nge_eeprom_getword(sc, addr, dest) 329 struct nge_softc *sc; 330 int addr; 331 u_int16_t *dest; 332{ 333 register int i; 334 u_int16_t word = 0; 335 336 /* Force EEPROM to idle state. */ 337 nge_eeprom_idle(sc); 338 339 /* Enter EEPROM access mode. */ 340 nge_delay(sc); 341 SIO_CLR(NGE_MEAR_EE_CLK); 342 nge_delay(sc); 343 SIO_SET(NGE_MEAR_EE_CSEL); 344 nge_delay(sc); 345 346 /* 347 * Send address of word we want to read. 348 */ 349 nge_eeprom_putbyte(sc, addr); 350 351 /* 352 * Start reading bits from EEPROM. 353 */ 354 for (i = 0x8000; i; i >>= 1) { 355 SIO_SET(NGE_MEAR_EE_CLK); 356 nge_delay(sc); 357 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT) 358 word |= i; 359 nge_delay(sc); 360 SIO_CLR(NGE_MEAR_EE_CLK); 361 nge_delay(sc); 362 } 363 364 /* Turn off EEPROM access mode. */ 365 nge_eeprom_idle(sc); 366 367 *dest = word; 368 369 return; 370} 371 372/* 373 * Read a sequence of words from the EEPROM. 374 */ 375static void nge_read_eeprom(sc, dest, off, cnt, swap) 376 struct nge_softc *sc; 377 caddr_t dest; 378 int off; 379 int cnt; 380 int swap; 381{ 382 int i; 383 u_int16_t word = 0, *ptr; 384 385 for (i = 0; i < cnt; i++) { 386 nge_eeprom_getword(sc, off + i, &word); 387 ptr = (u_int16_t *)(dest + (i * 2)); 388 if (swap) 389 *ptr = ntohs(word); 390 else 391 *ptr = word; 392 } 393 394 return; 395} 396 397/* 398 * Sync the PHYs by setting data bit and strobing the clock 32 times. 399 */ 400static void nge_mii_sync(sc) 401 struct nge_softc *sc; 402{ 403 register int i; 404 405 SIO_SET(NGE_MEAR_MII_DIR|NGE_MEAR_MII_DATA); 406 407 for (i = 0; i < 32; i++) { 408 SIO_SET(NGE_MEAR_MII_CLK); 409 DELAY(1); 410 SIO_CLR(NGE_MEAR_MII_CLK); 411 DELAY(1); 412 } 413 414 return; 415} 416 417/* 418 * Clock a series of bits through the MII. 419 */ 420static void nge_mii_send(sc, bits, cnt) 421 struct nge_softc *sc; 422 u_int32_t bits; 423 int cnt; 424{ 425 int i; 426 427 SIO_CLR(NGE_MEAR_MII_CLK); 428 429 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 430 if (bits & i) { 431 SIO_SET(NGE_MEAR_MII_DATA); 432 } else { 433 SIO_CLR(NGE_MEAR_MII_DATA); 434 } 435 DELAY(1); 436 SIO_CLR(NGE_MEAR_MII_CLK); 437 DELAY(1); 438 SIO_SET(NGE_MEAR_MII_CLK); 439 } 440} 441 442/* 443 * Read an PHY register through the MII. 444 */ 445static int nge_mii_readreg(sc, frame) 446 struct nge_softc *sc; 447 struct nge_mii_frame *frame; 448 449{ 450 int i, ack, s; 451 452 s = splimp(); 453 454 /* 455 * Set up frame for RX. 456 */ 457 frame->mii_stdelim = NGE_MII_STARTDELIM; 458 frame->mii_opcode = NGE_MII_READOP; 459 frame->mii_turnaround = 0; 460 frame->mii_data = 0; 461 462 CSR_WRITE_4(sc, NGE_MEAR, 0); 463 464 /* 465 * Turn on data xmit. 466 */ 467 SIO_SET(NGE_MEAR_MII_DIR); 468 469 nge_mii_sync(sc); 470 471 /* 472 * Send command/address info. 473 */ 474 nge_mii_send(sc, frame->mii_stdelim, 2); 475 nge_mii_send(sc, frame->mii_opcode, 2); 476 nge_mii_send(sc, frame->mii_phyaddr, 5); 477 nge_mii_send(sc, frame->mii_regaddr, 5); 478 479 /* Idle bit */ 480 SIO_CLR((NGE_MEAR_MII_CLK|NGE_MEAR_MII_DATA)); 481 DELAY(1); 482 SIO_SET(NGE_MEAR_MII_CLK); 483 DELAY(1); 484 485 /* Turn off xmit. */ 486 SIO_CLR(NGE_MEAR_MII_DIR); 487 /* Check for ack */ 488 SIO_CLR(NGE_MEAR_MII_CLK); 489 DELAY(1); 490 SIO_SET(NGE_MEAR_MII_CLK); 491 DELAY(1); 492 ack = CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA; 493 494 /* 495 * Now try reading data bits. If the ack failed, we still 496 * need to clock through 16 cycles to keep the PHY(s) in sync. 497 */ 498 if (ack) { 499 for(i = 0; i < 16; i++) { 500 SIO_CLR(NGE_MEAR_MII_CLK); 501 DELAY(1); 502 SIO_SET(NGE_MEAR_MII_CLK); 503 DELAY(1); 504 } 505 goto fail; 506 } 507 508 for (i = 0x8000; i; i >>= 1) { 509 SIO_CLR(NGE_MEAR_MII_CLK); 510 DELAY(1); 511 if (!ack) { 512 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA) 513 frame->mii_data |= i; 514 DELAY(1); 515 } 516 SIO_SET(NGE_MEAR_MII_CLK); 517 DELAY(1); 518 } 519 520fail: 521 522 SIO_CLR(NGE_MEAR_MII_CLK); 523 DELAY(1); 524 SIO_SET(NGE_MEAR_MII_CLK); 525 DELAY(1); 526 527 splx(s); 528 529 if (ack) 530 return(1); 531 return(0); 532} 533 534/* 535 * Write to a PHY register through the MII. 536 */ 537static int nge_mii_writereg(sc, frame) 538 struct nge_softc *sc; 539 struct nge_mii_frame *frame; 540 541{ 542 int s; 543 544 s = splimp(); 545 /* 546 * Set up frame for TX. 547 */ 548 549 frame->mii_stdelim = NGE_MII_STARTDELIM; 550 frame->mii_opcode = NGE_MII_WRITEOP; 551 frame->mii_turnaround = NGE_MII_TURNAROUND; 552 553 /* 554 * Turn on data output. 555 */ 556 SIO_SET(NGE_MEAR_MII_DIR); 557 558 nge_mii_sync(sc); 559 560 nge_mii_send(sc, frame->mii_stdelim, 2); 561 nge_mii_send(sc, frame->mii_opcode, 2); 562 nge_mii_send(sc, frame->mii_phyaddr, 5); 563 nge_mii_send(sc, frame->mii_regaddr, 5); 564 nge_mii_send(sc, frame->mii_turnaround, 2); 565 nge_mii_send(sc, frame->mii_data, 16); 566 567 /* Idle bit. */ 568 SIO_SET(NGE_MEAR_MII_CLK); 569 DELAY(1); 570 SIO_CLR(NGE_MEAR_MII_CLK); 571 DELAY(1); 572 573 /* 574 * Turn off xmit. 575 */ 576 SIO_CLR(NGE_MEAR_MII_DIR); 577 578 splx(s); 579 580 return(0); 581} 582 583static int nge_miibus_readreg(dev, phy, reg) 584 device_t dev; 585 int phy, reg; 586{ 587 struct nge_softc *sc; 588 struct nge_mii_frame frame; 589 590 sc = device_get_softc(dev); 591 592 bzero((char *)&frame, sizeof(frame)); 593 594 frame.mii_phyaddr = phy; 595 frame.mii_regaddr = reg; 596 nge_mii_readreg(sc, &frame); 597 598 return(frame.mii_data); 599} 600 601static int nge_miibus_writereg(dev, phy, reg, data) 602 device_t dev; 603 int phy, reg, data; 604{ 605 struct nge_softc *sc; 606 struct nge_mii_frame frame; 607 608 sc = device_get_softc(dev); 609 610 bzero((char *)&frame, sizeof(frame)); 611 612 frame.mii_phyaddr = phy; 613 frame.mii_regaddr = reg; 614 frame.mii_data = data; 615 nge_mii_writereg(sc, &frame); 616 617 return(0); 618} 619 620static void nge_miibus_statchg(dev) 621 device_t dev; 622{ 623 struct nge_softc *sc; 624 struct mii_data *mii; 625 626 sc = device_get_softc(dev); 627 mii = device_get_softc(sc->nge_miibus); 628 629 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 630 NGE_SETBIT(sc, NGE_TX_CFG, 631 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 632 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 633 } else { 634 NGE_CLRBIT(sc, NGE_TX_CFG, 635 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 636 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 637 } 638 639 /* If we have a 1000Mbps link, set the mode_1000 bit. */ 640 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX || 641 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) { 642 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_MODE_1000); 643 } else { 644 NGE_CLRBIT(sc, NGE_CFG, NGE_CFG_MODE_1000); 645 } 646 647 return; 648} 649 650static u_int32_t nge_crc(sc, addr) 651 struct nge_softc *sc; 652 caddr_t addr; 653{ 654 u_int32_t crc, carry; 655 int i, j; 656 u_int8_t c; 657 658 /* Compute CRC for the address value. */ 659 crc = 0xFFFFFFFF; /* initial value */ 660 661 for (i = 0; i < 6; i++) { 662 c = *(addr + i); 663 for (j = 0; j < 8; j++) { 664 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 665 crc <<= 1; 666 c >>= 1; 667 if (carry) 668 crc = (crc ^ 0x04c11db6) | carry; 669 } 670 } 671 672 /* 673 * return the filter bit position 674 */ 675 676 return((crc >> 21) & 0x00000FFF); 677} 678 679static void nge_setmulti(sc) 680 struct nge_softc *sc; 681{ 682 struct ifnet *ifp; 683 struct ifmultiaddr *ifma; 684 u_int32_t h = 0, i, filtsave; 685 int bit, index; 686 687 ifp = &sc->arpcom.ac_if; 688 689 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 690 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 691 NGE_RXFILTCTL_MCHASH|NGE_RXFILTCTL_UCHASH); 692 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLMULTI); 693 return; 694 } 695 696 /* 697 * We have to explicitly enable the multicast hash table 698 * on the NatSemi chip if we want to use it, which we do. 699 * We also have to tell it that we don't want to use the 700 * hash table for matching unicast addresses. 701 */ 702 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_MCHASH); 703 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 704 NGE_RXFILTCTL_ALLMULTI|NGE_RXFILTCTL_UCHASH); 705 706 filtsave = CSR_READ_4(sc, NGE_RXFILT_CTL); 707 708 /* first, zot all the existing hash bits */ 709 for (i = 0; i < NGE_MCAST_FILTER_LEN; i += 2) { 710 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + i); 711 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 0); 712 } 713 714 /* 715 * From the 11 bits returned by the crc routine, the top 7 716 * bits represent the 16-bit word in the mcast hash table 717 * that needs to be updated, and the lower 4 bits represent 718 * which bit within that byte needs to be set. 719 */ 720 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 721 if (ifma->ifma_addr->sa_family != AF_LINK) 722 continue; 723 h = nge_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 724 index = (h >> 4) & 0x7F; 725 bit = h & 0xF; 726 CSR_WRITE_4(sc, NGE_RXFILT_CTL, 727 NGE_FILTADDR_MCAST_LO + (index * 2)); 728 NGE_SETBIT(sc, NGE_RXFILT_DATA, (1 << bit)); 729 } 730 731 CSR_WRITE_4(sc, NGE_RXFILT_CTL, filtsave); 732 733 return; 734} 735 736static void nge_reset(sc) 737 struct nge_softc *sc; 738{ 739 register int i; 740 741 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RESET); 742 743 for (i = 0; i < NGE_TIMEOUT; i++) { 744 if (!(CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET)) 745 break; 746 } 747 748 if (i == NGE_TIMEOUT) 749 printf("nge%d: reset never completed\n", sc->nge_unit); 750 751 /* Wait a little while for the chip to get its brains in order. */ 752 DELAY(1000); 753 754 /* 755 * If this is a NetSemi chip, make sure to clear 756 * PME mode. 757 */ 758 CSR_WRITE_4(sc, NGE_CLKRUN, NGE_CLKRUN_PMESTS); 759 CSR_WRITE_4(sc, NGE_CLKRUN, 0); 760 761 return; 762} 763 764/* 765 * Probe for an NatSemi chip. Check the PCI vendor and device 766 * IDs against our list and return a device name if we find a match. 767 */ 768static int nge_probe(dev) 769 device_t dev; 770{ 771 struct nge_type *t; 772 773 t = nge_devs; 774 775 while(t->nge_name != NULL) { 776 if ((pci_get_vendor(dev) == t->nge_vid) && 777 (pci_get_device(dev) == t->nge_did)) { 778 device_set_desc(dev, t->nge_name); 779 return(0); 780 } 781 t++; 782 } 783 784 return(ENXIO); 785} 786 787/* 788 * Attach the interface. Allocate softc structures, do ifmedia 789 * setup and ethernet/BPF attach. 790 */ 791static int nge_attach(dev) 792 device_t dev; 793{ 794 int s; 795 u_char eaddr[ETHER_ADDR_LEN]; 796 u_int32_t command; 797 struct nge_softc *sc; 798 struct ifnet *ifp; 799 int unit, error = 0, rid; 800 801 s = splimp(); 802 803 sc = device_get_softc(dev); 804 unit = device_get_unit(dev); 805 bzero(sc, sizeof(struct nge_softc)); 806 807 mtx_init(&sc->nge_mtx, device_get_nameunit(dev), MTX_DEF|MTX_RECURSE); 808 809 /* 810 * Handle power management nonsense. 811 */ 812 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 813 u_int32_t iobase, membase, irq; 814 815 /* Save important PCI config data. */ 816 iobase = pci_read_config(dev, NGE_PCI_LOIO, 4); 817 membase = pci_read_config(dev, NGE_PCI_LOMEM, 4); 818 irq = pci_read_config(dev, NGE_PCI_INTLINE, 4); 819 820 /* Reset the power state. */ 821 printf("nge%d: chip is in D%d power mode " 822 "-- setting to D0\n", unit, 823 pci_get_powerstate(dev)); 824 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 825 826 /* Restore PCI config data. */ 827 pci_write_config(dev, NGE_PCI_LOIO, iobase, 4); 828 pci_write_config(dev, NGE_PCI_LOMEM, membase, 4); 829 pci_write_config(dev, NGE_PCI_INTLINE, irq, 4); 830 } 831 832 /* 833 * Map control/status registers. 834 */ 835 pci_enable_busmaster(dev); 836 pci_enable_io(dev, SYS_RES_IOPORT); 837 pci_enable_io(dev, SYS_RES_MEMORY); 838 command = pci_read_config(dev, PCIR_COMMAND, 4); 839 840#ifdef NGE_USEIOSPACE 841 if (!(command & PCIM_CMD_PORTEN)) { 842 printf("nge%d: failed to enable I/O ports!\n", unit); 843 error = ENXIO;; 844 goto fail; 845 } 846#else 847 if (!(command & PCIM_CMD_MEMEN)) { 848 printf("nge%d: failed to enable memory mapping!\n", unit); 849 error = ENXIO;; 850 goto fail; 851 } 852#endif 853 854 rid = NGE_RID; 855 sc->nge_res = bus_alloc_resource(dev, NGE_RES, &rid, 856 0, ~0, 1, RF_ACTIVE); 857 858 if (sc->nge_res == NULL) { 859 printf("nge%d: couldn't map ports/memory\n", unit); 860 error = ENXIO; 861 goto fail; 862 } 863 864 sc->nge_btag = rman_get_bustag(sc->nge_res); 865 sc->nge_bhandle = rman_get_bushandle(sc->nge_res); 866 867 /* Allocate interrupt */ 868 rid = 0; 869 sc->nge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 870 RF_SHAREABLE | RF_ACTIVE); 871 872 if (sc->nge_irq == NULL) { 873 printf("nge%d: couldn't map interrupt\n", unit); 874 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 875 error = ENXIO; 876 goto fail; 877 } 878 879 error = bus_setup_intr(dev, sc->nge_irq, INTR_TYPE_NET, 880 nge_intr, sc, &sc->nge_intrhand); 881 882 if (error) { 883 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 884 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 885 printf("nge%d: couldn't set up irq\n", unit); 886 goto fail; 887 } 888 889 /* Reset the adapter. */ 890 nge_reset(sc); 891 892 /* 893 * Get station address from the EEPROM. 894 */ 895 nge_read_eeprom(sc, (caddr_t)&eaddr[4], NGE_EE_NODEADDR, 1, 0); 896 nge_read_eeprom(sc, (caddr_t)&eaddr[2], NGE_EE_NODEADDR + 1, 1, 0); 897 nge_read_eeprom(sc, (caddr_t)&eaddr[0], NGE_EE_NODEADDR + 2, 1, 0); 898 899 /* 900 * A NatSemi chip was detected. Inform the world. 901 */ 902 printf("nge%d: Ethernet address: %6D\n", unit, eaddr, ":"); 903 904 sc->nge_unit = unit; 905 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 906 907 sc->nge_ldata = contigmalloc(sizeof(struct nge_list_data), M_DEVBUF, 908 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 909 910 if (sc->nge_ldata == NULL) { 911 printf("nge%d: no memory for list buffers!\n", unit); 912 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 913 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 914 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 915 error = ENXIO; 916 goto fail; 917 } 918 bzero(sc->nge_ldata, sizeof(struct nge_list_data)); 919 920 /* Try to allocate memory for jumbo buffers. */ 921 if (nge_alloc_jumbo_mem(sc)) { 922 printf("nge%d: jumbo buffer allocation failed\n", 923 sc->nge_unit); 924 contigfree(sc->nge_ldata, 925 sizeof(struct nge_list_data), M_DEVBUF); 926 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 927 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 928 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 929 error = ENXIO; 930 goto fail; 931 } 932 933 ifp = &sc->arpcom.ac_if; 934 ifp->if_softc = sc; 935 ifp->if_unit = unit; 936 ifp->if_name = "nge"; 937 ifp->if_mtu = ETHERMTU; 938 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 939 ifp->if_ioctl = nge_ioctl; 940 ifp->if_output = ether_output; 941 ifp->if_start = nge_start; 942 ifp->if_watchdog = nge_watchdog; 943 ifp->if_init = nge_init; 944 ifp->if_baudrate = 1000000000; 945 ifp->if_snd.ifq_maxlen = NGE_TX_LIST_CNT - 1; 946 ifp->if_hwassist = NGE_CSUM_FEATURES; 947 948 /* 949 * Do MII setup. 950 */ 951 if (mii_phy_probe(dev, &sc->nge_miibus, 952 nge_ifmedia_upd, nge_ifmedia_sts)) { 953 printf("nge%d: MII without any PHY!\n", sc->nge_unit); 954 nge_free_jumbo_mem(sc); 955 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 956 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 957 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 958 error = ENXIO; 959 goto fail; 960 } 961 962 /* 963 * Call MI attach routine. 964 */ 965 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 966 callout_handle_init(&sc->nge_stat_ch); 967 968fail: 969 splx(s); 970 mtx_destroy(&sc->nge_mtx); 971 return(error); 972} 973 974static int nge_detach(dev) 975 device_t dev; 976{ 977 struct nge_softc *sc; 978 struct ifnet *ifp; 979 int s; 980 981 s = splimp(); 982 983 sc = device_get_softc(dev); 984 ifp = &sc->arpcom.ac_if; 985 986 nge_reset(sc); 987 nge_stop(sc); 988 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 989 990 bus_generic_detach(dev); 991 device_delete_child(dev, sc->nge_miibus); 992 993 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 994 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 995 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 996 997 contigfree(sc->nge_ldata, sizeof(struct nge_list_data), M_DEVBUF); 998 nge_free_jumbo_mem(sc); 999 1000 splx(s); 1001 mtx_destroy(&sc->nge_mtx); 1002 1003 return(0); 1004} 1005 1006/* 1007 * Initialize the transmit descriptors. 1008 */ 1009static int nge_list_tx_init(sc) 1010 struct nge_softc *sc; 1011{ 1012 struct nge_list_data *ld; 1013 struct nge_ring_data *cd; 1014 int i; 1015 1016 cd = &sc->nge_cdata; 1017 ld = sc->nge_ldata; 1018 1019 for (i = 0; i < NGE_TX_LIST_CNT; i++) { 1020 if (i == (NGE_TX_LIST_CNT - 1)) { 1021 ld->nge_tx_list[i].nge_nextdesc = 1022 &ld->nge_tx_list[0]; 1023 ld->nge_tx_list[i].nge_next = 1024 vtophys(&ld->nge_tx_list[0]); 1025 } else { 1026 ld->nge_tx_list[i].nge_nextdesc = 1027 &ld->nge_tx_list[i + 1]; 1028 ld->nge_tx_list[i].nge_next = 1029 vtophys(&ld->nge_tx_list[i + 1]); 1030 } 1031 ld->nge_tx_list[i].nge_mbuf = NULL; 1032 ld->nge_tx_list[i].nge_ptr = 0; 1033 ld->nge_tx_list[i].nge_ctl = 0; 1034 } 1035 1036 cd->nge_tx_prod = cd->nge_tx_cons = cd->nge_tx_cnt = 0; 1037 1038 return(0); 1039} 1040 1041 1042/* 1043 * Initialize the RX descriptors and allocate mbufs for them. Note that 1044 * we arrange the descriptors in a closed ring, so that the last descriptor 1045 * points back to the first. 1046 */ 1047static int nge_list_rx_init(sc) 1048 struct nge_softc *sc; 1049{ 1050 struct nge_list_data *ld; 1051 struct nge_ring_data *cd; 1052 int i; 1053 1054 ld = sc->nge_ldata; 1055 cd = &sc->nge_cdata; 1056 1057 for (i = 0; i < NGE_RX_LIST_CNT; i++) { 1058 if (nge_newbuf(sc, &ld->nge_rx_list[i], NULL) == ENOBUFS) 1059 return(ENOBUFS); 1060 if (i == (NGE_RX_LIST_CNT - 1)) { 1061 ld->nge_rx_list[i].nge_nextdesc = 1062 &ld->nge_rx_list[0]; 1063 ld->nge_rx_list[i].nge_next = 1064 vtophys(&ld->nge_rx_list[0]); 1065 } else { 1066 ld->nge_rx_list[i].nge_nextdesc = 1067 &ld->nge_rx_list[i + 1]; 1068 ld->nge_rx_list[i].nge_next = 1069 vtophys(&ld->nge_rx_list[i + 1]); 1070 } 1071 } 1072 1073 cd->nge_rx_prod = 0; 1074 1075 return(0); 1076} 1077 1078/* 1079 * Initialize an RX descriptor and attach an MBUF cluster. 1080 */ 1081static int nge_newbuf(sc, c, m) 1082 struct nge_softc *sc; 1083 struct nge_desc *c; 1084 struct mbuf *m; 1085{ 1086 struct mbuf *m_new = NULL; 1087 caddr_t *buf = NULL; 1088 1089 if (m == NULL) { 1090 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1091 if (m_new == NULL) { 1092 printf("nge%d: no memory for rx list " 1093 "-- packet dropped!\n", sc->nge_unit); 1094 return(ENOBUFS); 1095 } 1096 1097 /* Allocate the jumbo buffer */ 1098 buf = nge_jalloc(sc); 1099 if (buf == NULL) { 1100#ifdef NGE_VERBOSE 1101 printf("nge%d: jumbo allocation failed " 1102 "-- packet dropped!\n", sc->nge_unit); 1103#endif 1104 m_freem(m_new); 1105 return(ENOBUFS); 1106 } 1107 /* Attach the buffer to the mbuf */ 1108 m_new->m_data = (void *)buf; 1109 m_new->m_len = m_new->m_pkthdr.len = NGE_JUMBO_FRAMELEN; 1110 MEXTADD(m_new, buf, NGE_JUMBO_FRAMELEN, nge_jfree, 1111 (struct nge_softc *)sc, 0, EXT_NET_DRV); 1112 } else { 1113 m_new = m; 1114 m_new->m_len = m_new->m_pkthdr.len = NGE_JUMBO_FRAMELEN; 1115 m_new->m_data = m_new->m_ext.ext_buf; 1116 } 1117 1118 m_adj(m_new, sizeof(u_int64_t)); 1119 1120 c->nge_mbuf = m_new; 1121 c->nge_ptr = vtophys(mtod(m_new, caddr_t)); 1122 c->nge_ctl = m_new->m_len; 1123 c->nge_extsts = 0; 1124 1125 return(0); 1126} 1127 1128static int nge_alloc_jumbo_mem(sc) 1129 struct nge_softc *sc; 1130{ 1131 caddr_t ptr; 1132 register int i; 1133 struct nge_jpool_entry *entry; 1134 1135 /* Grab a big chunk o' storage. */ 1136 sc->nge_cdata.nge_jumbo_buf = contigmalloc(NGE_JMEM, M_DEVBUF, 1137 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1138 1139 if (sc->nge_cdata.nge_jumbo_buf == NULL) { 1140 printf("nge%d: no memory for jumbo buffers!\n", sc->nge_unit); 1141 return(ENOBUFS); 1142 } 1143 1144 SLIST_INIT(&sc->nge_jfree_listhead); 1145 SLIST_INIT(&sc->nge_jinuse_listhead); 1146 1147 /* 1148 * Now divide it up into 9K pieces and save the addresses 1149 * in an array. 1150 */ 1151 ptr = sc->nge_cdata.nge_jumbo_buf; 1152 for (i = 0; i < NGE_JSLOTS; i++) { 1153 sc->nge_cdata.nge_jslots[i] = ptr; 1154 ptr += NGE_JLEN; 1155 entry = malloc(sizeof(struct nge_jpool_entry), 1156 M_DEVBUF, M_NOWAIT); 1157 if (entry == NULL) { 1158 printf("nge%d: no memory for jumbo " 1159 "buffer queue!\n", sc->nge_unit); 1160 return(ENOBUFS); 1161 } 1162 entry->slot = i; 1163 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead, 1164 entry, jpool_entries); 1165 } 1166 1167 return(0); 1168} 1169 1170static void nge_free_jumbo_mem(sc) 1171 struct nge_softc *sc; 1172{ 1173 register int i; 1174 struct nge_jpool_entry *entry; 1175 1176 for (i = 0; i < NGE_JSLOTS; i++) { 1177 entry = SLIST_FIRST(&sc->nge_jfree_listhead); 1178 SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jpool_entries); 1179 free(entry, M_DEVBUF); 1180 } 1181 1182 contigfree(sc->nge_cdata.nge_jumbo_buf, NGE_JMEM, M_DEVBUF); 1183 1184 return; 1185} 1186 1187/* 1188 * Allocate a jumbo buffer. 1189 */ 1190static void *nge_jalloc(sc) 1191 struct nge_softc *sc; 1192{ 1193 struct nge_jpool_entry *entry; 1194 1195 entry = SLIST_FIRST(&sc->nge_jfree_listhead); 1196 1197 if (entry == NULL) { 1198#ifdef NGE_VERBOSE 1199 printf("nge%d: no free jumbo buffers\n", sc->nge_unit); 1200#endif 1201 return(NULL); 1202 } 1203 1204 SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jpool_entries); 1205 SLIST_INSERT_HEAD(&sc->nge_jinuse_listhead, entry, jpool_entries); 1206 return(sc->nge_cdata.nge_jslots[entry->slot]); 1207} 1208 1209/* 1210 * Release a jumbo buffer. 1211 */ 1212static void nge_jfree(buf, args) 1213 caddr_t buf; 1214 void *args; 1215{ 1216 struct nge_softc *sc; 1217 int i; 1218 struct nge_jpool_entry *entry; 1219 1220 /* Extract the softc struct pointer. */ 1221 sc = args; 1222 1223 if (sc == NULL) 1224 panic("nge_jfree: can't find softc pointer!"); 1225 1226 /* calculate the slot this buffer belongs to */ 1227 i = ((vm_offset_t)buf 1228 - (vm_offset_t)sc->nge_cdata.nge_jumbo_buf) / NGE_JLEN; 1229 1230 if ((i < 0) || (i >= NGE_JSLOTS)) 1231 panic("nge_jfree: asked to free buffer that we don't manage!"); 1232 1233 entry = SLIST_FIRST(&sc->nge_jinuse_listhead); 1234 if (entry == NULL) 1235 panic("nge_jfree: buffer not in use!"); 1236 entry->slot = i; 1237 SLIST_REMOVE_HEAD(&sc->nge_jinuse_listhead, jpool_entries); 1238 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead, entry, jpool_entries); 1239 1240 return; 1241} 1242/* 1243 * A frame has been uploaded: pass the resulting mbuf chain up to 1244 * the higher level protocols. 1245 */ 1246static void nge_rxeof(sc) 1247 struct nge_softc *sc; 1248{ 1249 struct ether_header *eh; 1250 struct mbuf *m; 1251 struct ifnet *ifp; 1252 struct nge_desc *cur_rx; 1253 int i, total_len = 0; 1254 u_int32_t rxstat; 1255 1256 ifp = &sc->arpcom.ac_if; 1257 i = sc->nge_cdata.nge_rx_prod; 1258 1259 while(NGE_OWNDESC(&sc->nge_ldata->nge_rx_list[i])) { 1260 struct mbuf *m0 = NULL; 1261 u_int32_t extsts; 1262 1263 cur_rx = &sc->nge_ldata->nge_rx_list[i]; 1264 rxstat = cur_rx->nge_rxstat; 1265 extsts = cur_rx->nge_extsts; 1266 m = cur_rx->nge_mbuf; 1267 cur_rx->nge_mbuf = NULL; 1268 total_len = NGE_RXBYTES(cur_rx); 1269 NGE_INC(i, NGE_RX_LIST_CNT); 1270 1271 /* 1272 * If an error occurs, update stats, clear the 1273 * status word and leave the mbuf cluster in place: 1274 * it should simply get re-used next time this descriptor 1275 * comes up in the ring. 1276 */ 1277 if (!(rxstat & NGE_CMDSTS_PKT_OK)) { 1278 ifp->if_ierrors++; 1279 nge_newbuf(sc, cur_rx, m); 1280 continue; 1281 } 1282 1283 1284 /* 1285 * Ok. NatSemi really screwed up here. This is the 1286 * only gigE chip I know of with alignment constraints 1287 * on receive buffers. RX buffers must be 64-bit aligned. 1288 */ 1289#ifdef __i386__ 1290 /* 1291 * By popular demand, ignore the alignment problems 1292 * on the Intel x86 platform. The performance hit 1293 * incurred due to unaligned accesses is much smaller 1294 * than the hit produced by forcing buffer copies all 1295 * the time, especially with jumbo frames. We still 1296 * need to fix up the alignment everywhere else though. 1297 */ 1298 if (nge_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 1299#endif 1300 m0 = m_devget(mtod(m, char *), total_len, 1301 ETHER_ALIGN, ifp, NULL); 1302 nge_newbuf(sc, cur_rx, m); 1303 if (m0 == NULL) { 1304 printf("nge%d: no receive buffers " 1305 "available -- packet dropped!\n", 1306 sc->nge_unit); 1307 ifp->if_ierrors++; 1308 continue; 1309 } 1310 m = m0; 1311#ifdef __i386__ 1312 } else { 1313 m->m_pkthdr.rcvif = ifp; 1314 m->m_pkthdr.len = m->m_len = total_len; 1315 } 1316#endif 1317 1318 ifp->if_ipackets++; 1319 eh = mtod(m, struct ether_header *); 1320 1321 /* Remove header from mbuf and pass it on. */ 1322 m_adj(m, sizeof(struct ether_header)); 1323 1324 /* Do IP checksum checking. */ 1325 if (extsts & NGE_RXEXTSTS_IPPKT) 1326 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1327 if (!(extsts & NGE_RXEXTSTS_IPCSUMERR)) 1328 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1329 if ((extsts & NGE_RXEXTSTS_TCPPKT && 1330 !(extsts & NGE_RXEXTSTS_TCPCSUMERR)) || 1331 (extsts & NGE_RXEXTSTS_UDPPKT && 1332 !(extsts & NGE_RXEXTSTS_UDPCSUMERR))) { 1333 m->m_pkthdr.csum_flags |= 1334 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1335 m->m_pkthdr.csum_data = 0xffff; 1336 } 1337 1338#if NVLAN > 0 1339 /* 1340 * If we received a packet with a vlan tag, pass it 1341 * to vlan_input() instead of ether_input(). 1342 */ 1343 if (extsts & NGE_RXEXTSTS_VLANPKT) { 1344 vlan_input_tag(eh, m, extsts & NGE_RXEXTSTS_VTCI); 1345 continue; 1346 } 1347#endif 1348 1349 ether_input(ifp, eh, m); 1350 } 1351 1352 sc->nge_cdata.nge_rx_prod = i; 1353 1354 return; 1355} 1356 1357void nge_rxeoc(sc) 1358 struct nge_softc *sc; 1359{ 1360 struct ifnet *ifp; 1361 1362 ifp = &sc->arpcom.ac_if; 1363 nge_rxeof(sc); 1364 ifp->if_flags &= ~IFF_RUNNING; 1365 nge_init(sc); 1366 return; 1367} 1368 1369/* 1370 * A frame was downloaded to the chip. It's safe for us to clean up 1371 * the list buffers. 1372 */ 1373 1374static void nge_txeof(sc) 1375 struct nge_softc *sc; 1376{ 1377 struct nge_desc *cur_tx = NULL; 1378 struct ifnet *ifp; 1379 u_int32_t idx; 1380 1381 ifp = &sc->arpcom.ac_if; 1382 1383 /* Clear the timeout timer. */ 1384 ifp->if_timer = 0; 1385 1386 /* 1387 * Go through our tx list and free mbufs for those 1388 * frames that have been transmitted. 1389 */ 1390 idx = sc->nge_cdata.nge_tx_cons; 1391 while (idx != sc->nge_cdata.nge_tx_prod) { 1392 cur_tx = &sc->nge_ldata->nge_tx_list[idx]; 1393 1394 if (NGE_OWNDESC(cur_tx)) 1395 break; 1396 1397 if (cur_tx->nge_ctl & NGE_CMDSTS_MORE) { 1398 sc->nge_cdata.nge_tx_cnt--; 1399 NGE_INC(idx, NGE_TX_LIST_CNT); 1400 continue; 1401 } 1402 1403 if (!(cur_tx->nge_ctl & NGE_CMDSTS_PKT_OK)) { 1404 ifp->if_oerrors++; 1405 if (cur_tx->nge_txstat & NGE_TXSTAT_EXCESSCOLLS) 1406 ifp->if_collisions++; 1407 if (cur_tx->nge_txstat & NGE_TXSTAT_OUTOFWINCOLL) 1408 ifp->if_collisions++; 1409 } 1410 1411 ifp->if_collisions += 1412 (cur_tx->nge_txstat & NGE_TXSTAT_COLLCNT) >> 16; 1413 1414 ifp->if_opackets++; 1415 if (cur_tx->nge_mbuf != NULL) { 1416 m_freem(cur_tx->nge_mbuf); 1417 cur_tx->nge_mbuf = NULL; 1418 } 1419 1420 sc->nge_cdata.nge_tx_cnt--; 1421 NGE_INC(idx, NGE_TX_LIST_CNT); 1422 ifp->if_timer = 0; 1423 } 1424 1425 sc->nge_cdata.nge_tx_cons = idx; 1426 1427 if (cur_tx != NULL) 1428 ifp->if_flags &= ~IFF_OACTIVE; 1429 1430 return; 1431} 1432 1433static void nge_tick(xsc) 1434 void *xsc; 1435{ 1436 struct nge_softc *sc; 1437 struct mii_data *mii; 1438 struct ifnet *ifp; 1439 int s; 1440 1441 s = splimp(); 1442 1443 sc = xsc; 1444 ifp = &sc->arpcom.ac_if; 1445 1446 mii = device_get_softc(sc->nge_miibus); 1447 mii_tick(mii); 1448 1449 if (!sc->nge_link) { 1450 mii_pollstat(mii); 1451 if (mii->mii_media_status & IFM_ACTIVE && 1452 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1453 sc->nge_link++; 1454 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX) 1455 printf("nge%d: gigabit link up\n", 1456 sc->nge_unit); 1457 if (ifp->if_snd.ifq_head != NULL) 1458 nge_start(ifp); 1459 } else 1460 sc->nge_stat_ch = timeout(nge_tick, sc, hz); 1461 } 1462 1463 1464 splx(s); 1465 1466 return; 1467} 1468 1469static void nge_intr(arg) 1470 void *arg; 1471{ 1472 struct nge_softc *sc; 1473 struct ifnet *ifp; 1474 u_int32_t status; 1475 1476 sc = arg; 1477 ifp = &sc->arpcom.ac_if; 1478 1479 /* Supress unwanted interrupts */ 1480 if (!(ifp->if_flags & IFF_UP)) { 1481 nge_stop(sc); 1482 return; 1483 } 1484 1485 /* Disable interrupts. */ 1486 CSR_WRITE_4(sc, NGE_IER, 0); 1487 1488 for (;;) { 1489 /* Reading the ISR register clears all interrupts. */ 1490 status = CSR_READ_4(sc, NGE_ISR); 1491 1492 if ((status & NGE_INTRS) == 0) 1493 break; 1494 1495 if ((status & NGE_ISR_TX_DESC_OK) || 1496 (status & NGE_ISR_TX_ERR) || 1497 (status & NGE_ISR_TX_OK) || 1498 (status & NGE_ISR_TX_IDLE)) 1499 nge_txeof(sc); 1500 1501 if ((status & NGE_ISR_RX_DESC_OK) || 1502 (status & NGE_ISR_RX_ERR) || 1503 (status & NGE_ISR_RX_OK)) 1504 nge_rxeof(sc); 1505 1506 if ((status & NGE_ISR_RX_OFLOW)) 1507 nge_rxeoc(sc); 1508 1509 if (status & NGE_ISR_SYSERR) { 1510 nge_reset(sc); 1511 ifp->if_flags &= ~IFF_RUNNING; 1512 nge_init(sc); 1513 } 1514 1515 if (status & NGE_IMR_PHY_INTR) { 1516 sc->nge_link = 0; 1517 nge_tick(sc); 1518 } 1519 } 1520 1521 /* Re-enable interrupts. */ 1522 CSR_WRITE_4(sc, NGE_IER, 1); 1523 1524 if (ifp->if_snd.ifq_head != NULL) 1525 nge_start(ifp); 1526 1527 return; 1528} 1529 1530/* 1531 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1532 * pointers to the fragment pointers. 1533 */ 1534static int nge_encap(sc, m_head, txidx) 1535 struct nge_softc *sc; 1536 struct mbuf *m_head; 1537 u_int32_t *txidx; 1538{ 1539 struct nge_desc *f = NULL; 1540 struct mbuf *m; 1541 int frag, cur, cnt = 0; 1542#if NVLAN > 0 1543 struct ifvlan *ifv = NULL; 1544 1545 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 1546 m_head->m_pkthdr.rcvif != NULL && 1547 m_head->m_pkthdr.rcvif->if_type == IFT_8021_VLAN) 1548 ifv = m_head->m_pkthdr.rcvif->if_softc; 1549#endif 1550 1551 /* 1552 * Start packing the mbufs in this chain into 1553 * the fragment pointers. Stop when we run out 1554 * of fragments or hit the end of the mbuf chain. 1555 */ 1556 m = m_head; 1557 cur = frag = *txidx; 1558 1559 for (m = m_head; m != NULL; m = m->m_next) { 1560 if (m->m_len != 0) { 1561 if ((NGE_TX_LIST_CNT - 1562 (sc->nge_cdata.nge_tx_cnt + cnt)) < 2) 1563 return(ENOBUFS); 1564 f = &sc->nge_ldata->nge_tx_list[frag]; 1565 f->nge_ctl = NGE_CMDSTS_MORE | m->m_len; 1566 f->nge_ptr = vtophys(mtod(m, vm_offset_t)); 1567 if (cnt != 0) 1568 f->nge_ctl |= NGE_CMDSTS_OWN; 1569 cur = frag; 1570 NGE_INC(frag, NGE_TX_LIST_CNT); 1571 cnt++; 1572 } 1573 } 1574 1575 if (m != NULL) 1576 return(ENOBUFS); 1577 1578 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts = 0; 1579 if (m_head->m_pkthdr.csum_flags) { 1580 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1581 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1582 NGE_TXEXTSTS_IPCSUM; 1583 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1584 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1585 NGE_TXEXTSTS_TCPCSUM; 1586 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 1587 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1588 NGE_TXEXTSTS_UDPCSUM; 1589 } 1590 1591#if NVLAN > 0 1592 if (ifv != NULL) { 1593 sc->nge_ldata->nge_tx_list[cur].nge_extsts |= 1594 (NGE_TXEXTSTS_VLANPKT|ifv->ifv_tag); 1595 } 1596#endif 1597 1598 sc->nge_ldata->nge_tx_list[cur].nge_mbuf = m_head; 1599 sc->nge_ldata->nge_tx_list[cur].nge_ctl &= ~NGE_CMDSTS_MORE; 1600 sc->nge_ldata->nge_tx_list[*txidx].nge_ctl |= NGE_CMDSTS_OWN; 1601 sc->nge_cdata.nge_tx_cnt += cnt; 1602 *txidx = frag; 1603 1604 return(0); 1605} 1606 1607/* 1608 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1609 * to the mbuf data regions directly in the transmit lists. We also save a 1610 * copy of the pointers since the transmit list fragment pointers are 1611 * physical addresses. 1612 */ 1613 1614static void nge_start(ifp) 1615 struct ifnet *ifp; 1616{ 1617 struct nge_softc *sc; 1618 struct mbuf *m_head = NULL; 1619 u_int32_t idx; 1620 1621 sc = ifp->if_softc; 1622 1623 if (!sc->nge_link) 1624 return; 1625 1626 idx = sc->nge_cdata.nge_tx_prod; 1627 1628 if (ifp->if_flags & IFF_OACTIVE) 1629 return; 1630 1631 while(sc->nge_ldata->nge_tx_list[idx].nge_mbuf == NULL) { 1632 IF_DEQUEUE(&ifp->if_snd, m_head); 1633 if (m_head == NULL) 1634 break; 1635 1636 if (nge_encap(sc, m_head, &idx)) { 1637 IF_PREPEND(&ifp->if_snd, m_head); 1638 ifp->if_flags |= IFF_OACTIVE; 1639 break; 1640 } 1641 1642 /* 1643 * If there's a BPF listener, bounce a copy of this frame 1644 * to him. 1645 */ 1646 if (ifp->if_bpf) 1647 bpf_mtap(ifp, m_head); 1648 1649 } 1650 1651 /* Transmit */ 1652 sc->nge_cdata.nge_tx_prod = idx; 1653 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_ENABLE); 1654 1655 /* 1656 * Set a timeout in case the chip goes out to lunch. 1657 */ 1658 ifp->if_timer = 5; 1659 1660 return; 1661} 1662 1663static void nge_init(xsc) 1664 void *xsc; 1665{ 1666 struct nge_softc *sc = xsc; 1667 struct ifnet *ifp = &sc->arpcom.ac_if; 1668 struct mii_data *mii; 1669 int s; 1670 1671 if (ifp->if_flags & IFF_RUNNING) 1672 return; 1673 1674 s = splimp(); 1675 1676 /* 1677 * Cancel pending I/O and free all RX/TX buffers. 1678 */ 1679 nge_stop(sc); 1680 1681 mii = device_get_softc(sc->nge_miibus); 1682 1683 /* Set MAC address */ 1684 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0); 1685 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1686 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1687 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR1); 1688 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1689 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1690 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR2); 1691 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1692 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1693 1694 /* Init circular RX list. */ 1695 if (nge_list_rx_init(sc) == ENOBUFS) { 1696 printf("nge%d: initialization failed: no " 1697 "memory for rx buffers\n", sc->nge_unit); 1698 nge_stop(sc); 1699 (void)splx(s); 1700 return; 1701 } 1702 1703 /* 1704 * Init tx descriptors. 1705 */ 1706 nge_list_tx_init(sc); 1707 1708 /* 1709 * For the NatSemi chip, we have to explicitly enable the 1710 * reception of ARP frames, as well as turn on the 'perfect 1711 * match' filter where we store the station address, otherwise 1712 * we won't receive unicasts meant for this host. 1713 */ 1714 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ARP); 1715 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_PERFECT); 1716 1717 /* If we want promiscuous mode, set the allframes bit. */ 1718 if (ifp->if_flags & IFF_PROMISC) { 1719 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS); 1720 } else { 1721 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS); 1722 } 1723 1724 /* 1725 * Set the capture broadcast bit to capture broadcast frames. 1726 */ 1727 if (ifp->if_flags & IFF_BROADCAST) { 1728 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD); 1729 } else { 1730 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD); 1731 } 1732 1733 /* 1734 * Load the multicast filter. 1735 */ 1736 nge_setmulti(sc); 1737 1738 /* Turn the receive filter on */ 1739 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ENABLE); 1740 1741 /* 1742 * Load the address of the RX and TX lists. 1743 */ 1744 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 1745 vtophys(&sc->nge_ldata->nge_rx_list[0])); 1746 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 1747 vtophys(&sc->nge_ldata->nge_tx_list[0])); 1748 1749 /* Set RX configuration */ 1750 CSR_WRITE_4(sc, NGE_RX_CFG, NGE_RXCFG); 1751 /* 1752 * Enable hardware checksum validation for all IPv4 1753 * packets, do not reject packets with bad checksums. 1754 */ 1755 CSR_WRITE_4(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_IPCSUM_ENB); 1756 1757#if NVLAN > 0 1758 /* 1759 * If VLAN support is enabled, tell the chip to detect 1760 * and strip VLAN tag info from received frames. The tag 1761 * will be provided in the extsts field in the RX descriptors. 1762 */ 1763 NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL, 1764 NGE_VIPRXCTL_TAG_DETECT_ENB|NGE_VIPRXCTL_TAG_STRIP_ENB); 1765#endif 1766 1767 /* Set TX configuration */ 1768 CSR_WRITE_4(sc, NGE_TX_CFG, NGE_TXCFG); 1769 1770 /* 1771 * Enable TX IPv4 checksumming on a per-packet basis. 1772 */ 1773 CSR_WRITE_4(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_CSUM_PER_PKT); 1774 1775#if NVLAN > 0 1776 /* 1777 * If VLAN support is enabled, tell the chip to insert 1778 * VLAN tags on a per-packet basis as dictated by the 1779 * code in the frame encapsulation routine. 1780 */ 1781 NGE_SETBIT(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_TAG_PER_PKT); 1782#endif 1783 1784 /* Set full/half duplex mode. */ 1785 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1786 NGE_SETBIT(sc, NGE_TX_CFG, 1787 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1788 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1789 } else { 1790 NGE_CLRBIT(sc, NGE_TX_CFG, 1791 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1792 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1793 } 1794 1795 /* 1796 * Enable the delivery of PHY interrupts based on 1797 * link/speed/duplex status changes. Also enable the 1798 * extsts field in the DMA descriptors (needed for 1799 * TCP/IP checksum offload on transmit). 1800 */ 1801 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_PHYINTR_SPD| 1802 NGE_CFG_PHYINTR_LNK|NGE_CFG_PHYINTR_DUP|NGE_CFG_EXTSTS_ENB); 1803 1804 /* 1805 * Configure interrupt holdoff (moderation). We can 1806 * have the chip delay interrupt delivery for a certain 1807 * period. Units are in 100us, and the max setting 1808 * is 25500us (0xFF x 100us). Default is a 100us holdoff. 1809 */ 1810 CSR_WRITE_4(sc, NGE_IHR, 0x01); 1811 1812 /* 1813 * Enable interrupts. 1814 */ 1815 CSR_WRITE_4(sc, NGE_IMR, NGE_INTRS); 1816 CSR_WRITE_4(sc, NGE_IER, 1); 1817 1818 /* Enable receiver and transmitter. */ 1819 NGE_CLRBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE); 1820 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1821 1822 nge_ifmedia_upd(ifp); 1823 1824 ifp->if_flags |= IFF_RUNNING; 1825 ifp->if_flags &= ~IFF_OACTIVE; 1826 1827 (void)splx(s); 1828 1829 return; 1830} 1831 1832/* 1833 * Set media options. 1834 */ 1835static int nge_ifmedia_upd(ifp) 1836 struct ifnet *ifp; 1837{ 1838 struct nge_softc *sc; 1839 struct mii_data *mii; 1840 1841 sc = ifp->if_softc; 1842 1843 mii = device_get_softc(sc->nge_miibus); 1844 sc->nge_link = 0; 1845 if (mii->mii_instance) { 1846 struct mii_softc *miisc; 1847 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1848 miisc = LIST_NEXT(miisc, mii_list)) 1849 mii_phy_reset(miisc); 1850 } 1851 mii_mediachg(mii); 1852 1853 return(0); 1854} 1855 1856/* 1857 * Report current media status. 1858 */ 1859static void nge_ifmedia_sts(ifp, ifmr) 1860 struct ifnet *ifp; 1861 struct ifmediareq *ifmr; 1862{ 1863 struct nge_softc *sc; 1864 struct mii_data *mii; 1865 1866 sc = ifp->if_softc; 1867 1868 mii = device_get_softc(sc->nge_miibus); 1869 mii_pollstat(mii); 1870 ifmr->ifm_active = mii->mii_media_active; 1871 ifmr->ifm_status = mii->mii_media_status; 1872 1873 return; 1874} 1875 1876static int nge_ioctl(ifp, command, data) 1877 struct ifnet *ifp; 1878 u_long command; 1879 caddr_t data; 1880{ 1881 struct nge_softc *sc = ifp->if_softc; 1882 struct ifreq *ifr = (struct ifreq *) data; 1883 struct mii_data *mii; 1884 int s, error = 0; 1885 1886 s = splimp(); 1887 1888 switch(command) { 1889 case SIOCSIFADDR: 1890 case SIOCGIFADDR: 1891 error = ether_ioctl(ifp, command, data); 1892 break; 1893 case SIOCSIFMTU: 1894 if (ifr->ifr_mtu > NGE_JUMBO_MTU) 1895 error = EINVAL; 1896 else { 1897 ifp->if_mtu = ifr->ifr_mtu; 1898 /* 1899 * Workaround: if the MTU is larger than 1900 * 8152 (TX FIFO size minus 64 minus 18), turn off 1901 * TX checksum offloading. 1902 */ 1903 if (ifr->ifr_mtu >= 8152) 1904 ifp->if_hwassist = 0; 1905 else 1906 ifp->if_hwassist = NGE_CSUM_FEATURES; 1907 } 1908 break; 1909 case SIOCSIFFLAGS: 1910 if (ifp->if_flags & IFF_UP) { 1911 if (ifp->if_flags & IFF_RUNNING && 1912 ifp->if_flags & IFF_PROMISC && 1913 !(sc->nge_if_flags & IFF_PROMISC)) { 1914 NGE_SETBIT(sc, NGE_RXFILT_CTL, 1915 NGE_RXFILTCTL_ALLPHYS| 1916 NGE_RXFILTCTL_ALLMULTI); 1917 } else if (ifp->if_flags & IFF_RUNNING && 1918 !(ifp->if_flags & IFF_PROMISC) && 1919 sc->nge_if_flags & IFF_PROMISC) { 1920 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 1921 NGE_RXFILTCTL_ALLPHYS); 1922 if (!(ifp->if_flags & IFF_ALLMULTI)) 1923 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 1924 NGE_RXFILTCTL_ALLMULTI); 1925 } else { 1926 ifp->if_flags &= ~IFF_RUNNING; 1927 nge_init(sc); 1928 } 1929 } else { 1930 if (ifp->if_flags & IFF_RUNNING) 1931 nge_stop(sc); 1932 } 1933 sc->nge_if_flags = ifp->if_flags; 1934 error = 0; 1935 break; 1936 case SIOCADDMULTI: 1937 case SIOCDELMULTI: 1938 nge_setmulti(sc); 1939 error = 0; 1940 break; 1941 case SIOCGIFMEDIA: 1942 case SIOCSIFMEDIA: 1943 mii = device_get_softc(sc->nge_miibus); 1944 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1945 break; 1946 default: 1947 error = EINVAL; 1948 break; 1949 } 1950 1951 (void)splx(s); 1952 1953 return(error); 1954} 1955 1956static void nge_watchdog(ifp) 1957 struct ifnet *ifp; 1958{ 1959 struct nge_softc *sc; 1960 1961 sc = ifp->if_softc; 1962 1963 ifp->if_oerrors++; 1964 printf("nge%d: watchdog timeout\n", sc->nge_unit); 1965 1966 nge_stop(sc); 1967 nge_reset(sc); 1968 ifp->if_flags &= ~IFF_RUNNING; 1969 nge_init(sc); 1970 1971 if (ifp->if_snd.ifq_head != NULL) 1972 nge_start(ifp); 1973 1974 return; 1975} 1976 1977/* 1978 * Stop the adapter and free any mbufs allocated to the 1979 * RX and TX lists. 1980 */ 1981static void nge_stop(sc) 1982 struct nge_softc *sc; 1983{ 1984 register int i; 1985 struct ifnet *ifp; 1986 struct ifmedia_entry *ifm; 1987 struct mii_data *mii; 1988 int mtmp, itmp; 1989 1990 ifp = &sc->arpcom.ac_if; 1991 ifp->if_timer = 0; 1992 mii = device_get_softc(sc->nge_miibus); 1993 1994 untimeout(nge_tick, sc, sc->nge_stat_ch); 1995 CSR_WRITE_4(sc, NGE_IER, 0); 1996 CSR_WRITE_4(sc, NGE_IMR, 0); 1997 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE); 1998 DELAY(1000); 1999 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 0); 2000 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 0); 2001 2002 /* 2003 * Isolate/power down the PHY, but leave the media selection 2004 * unchanged so that things will be put back to normal when 2005 * we bring the interface back up. 2006 */ 2007 itmp = ifp->if_flags; 2008 ifp->if_flags |= IFF_UP; 2009 ifm = mii->mii_media.ifm_cur; 2010 mtmp = ifm->ifm_media; 2011 ifm->ifm_media = IFM_ETHER|IFM_NONE; 2012 mii_mediachg(mii); 2013 ifm->ifm_media = mtmp; 2014 ifp->if_flags = itmp; 2015 2016 sc->nge_link = 0; 2017 2018 /* 2019 * Free data in the RX lists. 2020 */ 2021 for (i = 0; i < NGE_RX_LIST_CNT; i++) { 2022 if (sc->nge_ldata->nge_rx_list[i].nge_mbuf != NULL) { 2023 m_freem(sc->nge_ldata->nge_rx_list[i].nge_mbuf); 2024 sc->nge_ldata->nge_rx_list[i].nge_mbuf = NULL; 2025 } 2026 } 2027 bzero((char *)&sc->nge_ldata->nge_rx_list, 2028 sizeof(sc->nge_ldata->nge_rx_list)); 2029 2030 /* 2031 * Free the TX list buffers. 2032 */ 2033 for (i = 0; i < NGE_TX_LIST_CNT; i++) { 2034 if (sc->nge_ldata->nge_tx_list[i].nge_mbuf != NULL) { 2035 m_freem(sc->nge_ldata->nge_tx_list[i].nge_mbuf); 2036 sc->nge_ldata->nge_tx_list[i].nge_mbuf = NULL; 2037 } 2038 } 2039 2040 bzero((char *)&sc->nge_ldata->nge_tx_list, 2041 sizeof(sc->nge_ldata->nge_tx_list)); 2042 2043 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2044 2045 return; 2046} 2047 2048/* 2049 * Stop all chip I/O so that the kernel's probe routines don't 2050 * get confused by errant DMAs when rebooting. 2051 */ 2052static void nge_shutdown(dev) 2053 device_t dev; 2054{ 2055 struct nge_softc *sc; 2056 2057 sc = device_get_softc(dev); 2058 2059 nge_reset(sc); 2060 nge_stop(sc); 2061 2062 return; 2063} 2064