if_nge.c revision 79424
1139823Simp/* 21541Srgrimes * Copyright (c) 2001 Wind River Systems 31541Srgrimes * Copyright (c) 1997, 1998, 1999, 2000, 2001 41541Srgrimes * Bill Paul <wpaul@bsdi.com>. All rights reserved. 51541Srgrimes * 61541Srgrimes * Redistribution and use in source and binary forms, with or without 71541Srgrimes * modification, are permitted provided that the following conditions 81541Srgrimes * are met: 91541Srgrimes * 1. Redistributions of source code must retain the above copyright 101541Srgrimes * notice, this list of conditions and the following disclaimer. 111541Srgrimes * 2. Redistributions in binary form must reproduce the above copyright 121541Srgrimes * notice, this list of conditions and the following disclaimer in the 131541Srgrimes * documentation and/or other materials provided with the distribution. 141541Srgrimes * 3. All advertising materials mentioning features or use of this software 151541Srgrimes * must display the following acknowledgement: 161541Srgrimes * This product includes software developed by Bill Paul. 171541Srgrimes * 4. Neither the name of the author nor the names of any co-contributors 181541Srgrimes * may be used to endorse or promote products derived from this software 191541Srgrimes * without specific prior written permission. 201541Srgrimes * 211541Srgrimes * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 221541Srgrimes * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 231541Srgrimes * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 241541Srgrimes * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 251541Srgrimes * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 261541Srgrimes * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 271541Srgrimes * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 281541Srgrimes * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 291541Srgrimes * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3050477Speter * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 311541Srgrimes * THE POSSIBILITY OF SUCH DAMAGE. 321541Srgrimes * 332168Spaul * $FreeBSD: head/sys/dev/nge/if_nge.c 79424 2001-07-08 16:24:01Z wpaul $ 344507Sbde */ 352168Spaul 36104355Smike/* 37104355Smike * National Semiconductor DP83820/DP83821 gigabit ethernet driver 38104355Smike * for FreeBSD. Datasheets are available from: 391541Srgrimes * 4034750Speter * http://www.national.com/ds/DP/DP83820.pdf 4172093Sasmodai * http://www.national.com/ds/DP/DP83821.pdf 42226610Sed * 4334750Speter * These chips are used on several low cost gigabit ethernet NICs 4455205Speter * sold by D-Link, Addtron, SMC and Asante. Both parts are 4534750Speter * virtually the same, except the 83820 is a 64-bit/32-bit part, 46226610Sed * while the 83821 is 32-bit only. 4734750Speter * 48104355Smike * Many cards also use National gigE transceivers, such as the 4979103Sbrooks * DP83891, DP83861 and DP83862 gigPHYTER parts. The DP83861 datasheet 5034750Speter * contains a full register description that applies to all of these 5179103Sbrooks * components: 5279103Sbrooks * 5379103Sbrooks * http://www.national.com/ds/DP/DP83861.pdf 54104355Smike * 55104355Smike * Written by Bill Paul <wpaul@bsdi.com> 56104355Smike * BSDi Open Source Solutions 57121816Sbrooks */ 58104355Smike 59104355Smike/* 60104355Smike * The NatSemi DP83820 and 83821 controllers are enhanced versions 6179103Sbrooks * of the NatSemi MacPHYTER 10/100 devices. They support 10, 100 6279103Sbrooks * and 1000Mbps speeds with 1000baseX (ten bit interface), MII and GMII 6379103Sbrooks * ports. Other features include 8K TX FIFO and 32K RX FIFO, TCP/IP 6479103Sbrooks * hardware checksum offload (IPv4 only), VLAN tagging and filtering, 6579103Sbrooks * priority TX and RX queues, a 2048 bit multicast hash filter, 4 RX pattern 6679103Sbrooks * matching buffers, one perfect address filter buffer and interrupt 6779103Sbrooks * moderation. The 83820 supports both 64-bit and 32-bit addressing 6879103Sbrooks * and data transfers: the 64-bit support can be toggled on or off 6979103Sbrooks * via software. This affects the size of certain fields in the DMA 7079103Sbrooks * descriptors. 7179103Sbrooks * 7219079Sfenner * There are two bugs/misfeatures in the 83820/83821 that I have 7319079Sfenner * discovered so far: 7419079Sfenner * 759457Sjoerg * - Receive buffers must be aligned on 64-bit boundaries, which means 769457Sjoerg * you must resort to copying data in order to fix up the payload 77263102Sglebius * alignment. 78263102Sglebius * 79263102Sglebius * - In order to transmit jumbo frames larger than 8170 bytes, you have 80263102Sglebius * to turn off transmit checksum offloading, because the chip can't 81263102Sglebius * compute the checksum on an outgoing frame unless it fits entirely 82263102Sglebius * within the TX FIFO, which is only 8192 bytes in size. If you have 83263102Sglebius * TX checksum offload enabled and you transmit attempt to transmit a 84263102Sglebius * frame larger than 8170 bytes, the transmitter will wedge. 85263102Sglebius * 86263102Sglebius * To work around the latter problem, TX checksum offload is disabled 879457Sjoerg * if the user selects an MTU larger than 8152 (8170 - 18). 88263102Sglebius */ 89263102Sglebius 90263102Sglebius#include "vlan.h" 91263102Sglebius 92263102Sglebius#include <sys/param.h> 93263102Sglebius#include <sys/systm.h> 94263102Sglebius#include <sys/sockio.h> 95263102Sglebius#include <sys/mbuf.h> 96263102Sglebius#include <sys/malloc.h> 97263102Sglebius#include <sys/kernel.h> 98263102Sglebius#include <sys/socket.h> 99263102Sglebius 100263102Sglebius#include <net/if.h> 101263102Sglebius#include <net/if_arp.h> 102263102Sglebius#include <net/ethernet.h> 103263102Sglebius#include <net/if_dl.h> 104263102Sglebius#include <net/if_media.h> 105263102Sglebius 106263102Sglebius#if NVLAN > 0 107263102Sglebius#include <net/if_types.h> 108263102Sglebius#include <net/if_vlan_var.h> 109263102Sglebius#endif 110263102Sglebius 111263102Sglebius#include <net/bpf.h> 112263102Sglebius 113263102Sglebius#include <vm/vm.h> /* for vtophys */ 114263102Sglebius#include <vm/pmap.h> /* for vtophys */ 115263102Sglebius#include <machine/clock.h> /* for DELAY */ 1169457Sjoerg#include <machine/bus_pio.h> 1179457Sjoerg#include <machine/bus_memio.h> 118148894Srwatson#include <machine/bus.h> 119148886Srwatson#include <machine/resource.h> 120148886Srwatson#include <sys/bus.h> 121148886Srwatson#include <sys/rman.h> 122148886Srwatson 123148886Srwatson#include <dev/mii/mii.h> 124148886Srwatson#include <dev/mii/miivar.h> 125148886Srwatson 126148886Srwatson#include <pci/pcireg.h> 127148886Srwatson#include <pci/pcivar.h> 128148886Srwatson 129148886Srwatson#define NGE_USEIOSPACE 130148886Srwatson 131148894Srwatson#include <dev/nge/if_ngereg.h> 132148894Srwatson 133148894SrwatsonMODULE_DEPEND(nge, miibus, 1, 1, 1); 134148894Srwatson 135148894Srwatson/* "controller miibus0" required. See GENERIC if you get errors here. */ 136148894Srwatson#include "miibus_if.h" 137148894Srwatson 138148894Srwatson#ifndef lint 139148886Srwatsonstatic const char rcsid[] = 140148894Srwatson "$FreeBSD: head/sys/dev/nge/if_nge.c 79424 2001-07-08 16:24:01Z wpaul $"; 141148894Srwatson#endif 142148894Srwatson 143148894Srwatson#define NGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 144148894Srwatson 145257699Sglebius/* 146148894Srwatson * Various supported device vendors/types and their names. 147148894Srwatson */ 148148894Srwatsonstatic struct nge_type nge_devs[] = { 149148894Srwatson { NGE_VENDORID, NGE_DEVICEID, 150148894Srwatson "National Semiconductor Gigabit Ethernet" }, 151148894Srwatson { 0, 0, NULL } 1521541Srgrimes}; 1531541Srgrimes 1541541Srgrimesstatic int nge_probe __P((device_t)); 1553274Swollmanstatic int nge_attach __P((device_t)); 156148894Srwatsonstatic int nge_detach __P((device_t)); 157216267Sweongyo 158148894Srwatsonstatic int nge_alloc_jumbo_mem __P((struct nge_softc *)); 159148894Srwatsonstatic void nge_free_jumbo_mem __P((struct nge_softc *)); 160148894Srwatsonstatic void *nge_jalloc __P((struct nge_softc *)); 161191416Srwatsonstatic void nge_jfree __P((caddr_t, void *)); 162201196Sjhb 163148886Srwatsonstatic int nge_newbuf __P((struct nge_softc *, 164148886Srwatson struct nge_desc *, 165148894Srwatson struct mbuf *)); 166148886Srwatsonstatic int nge_encap __P((struct nge_softc *, 167148886Srwatson struct mbuf *, u_int32_t *)); 168148886Srwatsonstatic void nge_rxeof __P((struct nge_softc *)); 169148886Srwatsonstatic void nge_rxeoc __P((struct nge_softc *)); 170148886Srwatsonstatic void nge_txeof __P((struct nge_softc *)); 171148886Srwatsonstatic void nge_intr __P((void *)); 1721541Srgrimesstatic void nge_tick __P((void *)); 1731541Srgrimesstatic void nge_start __P((struct ifnet *)); 174148886Srwatsonstatic int nge_ioctl __P((struct ifnet *, u_long, caddr_t)); 175257699Sglebiusstatic void nge_init __P((void *)); 176216268Sweongyostatic void nge_stop __P((struct nge_softc *)); 1771541Srgrimesstatic void nge_watchdog __P((struct ifnet *)); 178106925Ssamstatic void nge_shutdown __P((device_t)); 179128871Sandrestatic int nge_ifmedia_upd __P((struct ifnet *)); 180128871Sandrestatic void nge_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 181128871Sandre 182128871Sandrestatic void nge_delay __P((struct nge_softc *)); 183128871Sandrestatic void nge_eeprom_idle __P((struct nge_softc *)); 184128871Sandrestatic void nge_eeprom_putbyte __P((struct nge_softc *, int)); 185128871Sandrestatic void nge_eeprom_getword __P((struct nge_softc *, int, u_int16_t *)); 186106925Ssamstatic void nge_read_eeprom __P((struct nge_softc *, caddr_t, int, 187106925Ssam int, int)); 188106925Ssam 189241646Semaxstatic void nge_mii_sync __P((struct nge_softc *)); 190106925Ssamstatic void nge_mii_send __P((struct nge_softc *, u_int32_t, int)); 191106925Ssamstatic int nge_mii_readreg __P((struct nge_softc *, 192106925Ssam struct nge_mii_frame *)); 193162070Sandrestatic int nge_mii_writereg __P((struct nge_softc *, 194162070Sandre struct nge_mii_frame *)); 195162070Sandre 196162070Sandrestatic int nge_miibus_readreg __P((device_t, int, int)); 197162070Sandrestatic int nge_miibus_writereg __P((device_t, int, int, int)); 198162070Sandrestatic void nge_miibus_statchg __P((device_t)); 199162070Sandre 200169207Syarstatic void nge_setmulti __P((struct nge_softc *)); 201162070Sandrestatic u_int32_t nge_crc __P((struct nge_softc *, caddr_t)); 202162070Sandrestatic void nge_reset __P((struct nge_softc *)); 203162070Sandrestatic int nge_list_rx_init __P((struct nge_softc *)); 204162070Sandrestatic int nge_list_tx_init __P((struct nge_softc *)); 205162070Sandre 206162070Sandre#ifdef NGE_USEIOSPACE 207162070Sandre#define NGE_RES SYS_RES_IOPORT 208169207Syar#define NGE_RID NGE_PCI_LOIO 209162070Sandre#else 210223078Sluigi#define NGE_RES SYS_RES_MEMORY 211223078Sluigi#define NGE_RID NGE_PCI_LOMEM 212223078Sluigi#endif 213223078Sluigi 214223078Sluigistatic device_method_t nge_methods[] = { 215223078Sluigi /* Device interface */ 216223078Sluigi DEVMETHOD(device_probe, nge_probe), 217162070Sandre DEVMETHOD(device_attach, nge_attach), 218182413Sjfv DEVMETHOD(device_detach, nge_detach), 219182413Sjfv DEVMETHOD(device_shutdown, nge_shutdown), 220182413Sjfv 221182413Sjfv /* bus interface */ 222182413Sjfv DEVMETHOD(bus_print_child, bus_generic_print_child), 223182413Sjfv DEVMETHOD(bus_driver_added, bus_generic_driver_added), 224182413Sjfv 225182413Sjfv /* MII interface */ 226182413Sjfv DEVMETHOD(miibus_readreg, nge_miibus_readreg), 227182413Sjfv DEVMETHOD(miibus_writereg, nge_miibus_writereg), 228182413Sjfv DEVMETHOD(miibus_statchg, nge_miibus_statchg), 229182413Sjfv 230182413Sjfv { 0, 0 } 231182413Sjfv}; 232182413Sjfv 233182413Sjfvstatic driver_t nge_driver = { 234182413Sjfv "nge", 235193096Sattilio nge_methods, 236204149Syongari sizeof(struct nge_softc) 237205222Sqingli}; 238223078Sluigi 239236170Sbzstatic devclass_t nge_devclass; 240236170Sbz 241256218SglebiusDRIVER_MODULE(if_nge, pci, nge_driver, nge_devclass, 0, 0); 24283624SjlemonDRIVER_MODULE(miibus, nge, miibus_driver, miibus_devclass, 0, 0); 243236170Sbz 244236170Sbz#define NGE_SETBIT(sc, reg, x) \ 245174505Ssam CSR_WRITE_4(sc, reg, \ 246174505Ssam CSR_READ_4(sc, reg) | (x)) 247174505Ssam 248174628Skmacy#define NGE_CLRBIT(sc, reg, x) \ 24983636Sjlemon CSR_WRITE_4(sc, reg, \ 250223078Sluigi CSR_READ_4(sc, reg) & ~(x)) 251223078Sluigi 2521541Srgrimes#define SIO_SET(x) \ 2531541Srgrimes CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | x) 2541541Srgrimes 2551541Srgrimes#define SIO_CLR(x) \ 2561541Srgrimes CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~x) 2571541Srgrimes 258231505Sbzstatic void nge_delay(sc) 2591541Srgrimes struct nge_softc *sc; 2601541Srgrimes{ 2611541Srgrimes int idx; 26272093Sasmodai 2631541Srgrimes for (idx = (300 / 33) + 1; idx > 0; idx--) 2641541Srgrimes CSR_READ_4(sc, NGE_CSR); 2651541Srgrimes 2661541Srgrimes return; 2671541Srgrimes} 2681541Srgrimes 2691541Srgrimesstatic void nge_eeprom_idle(sc) 2701541Srgrimes struct nge_softc *sc; 271231505Sbz{ 272231505Sbz register int i; 273231505Sbz 274231505Sbz SIO_SET(NGE_MEAR_EE_CSEL); 275231505Sbz nge_delay(sc); 276231505Sbz SIO_SET(NGE_MEAR_EE_CLK); 277231505Sbz nge_delay(sc); 278231505Sbz 279231505Sbz for (i = 0; i < 25; i++) { 280231505Sbz SIO_CLR(NGE_MEAR_EE_CLK); 281231505Sbz nge_delay(sc); 282231505Sbz SIO_SET(NGE_MEAR_EE_CLK); 283231505Sbz nge_delay(sc); 284231505Sbz } 285231505Sbz 286231505Sbz SIO_CLR(NGE_MEAR_EE_CLK); 287231505Sbz nge_delay(sc); 288231505Sbz SIO_CLR(NGE_MEAR_EE_CSEL); 289231505Sbz nge_delay(sc); 290231505Sbz CSR_WRITE_4(sc, NGE_MEAR, 0x00000000); 291231505Sbz 292231505Sbz return; 293231505Sbz} 294231505Sbz 295231505Sbz/* 2961541Srgrimes * Send a read command and address to the EEPROM, check for ACK. 2971541Srgrimes */ 298231505Sbzstatic void nge_eeprom_putbyte(sc, addr) 2991541Srgrimes struct nge_softc *sc; 3001541Srgrimes int addr; 3011541Srgrimes{ 30272093Sasmodai register int d, i; 3031541Srgrimes 3041541Srgrimes d = addr | NGE_EECMD_READ; 3051541Srgrimes 3061541Srgrimes /* 307269243Sglebius * Feed in each bit and stobe the clock. 3081541Srgrimes */ 3091541Srgrimes for (i = 0x400; i; i >>= 1) { 3101541Srgrimes if (d & i) { 311231505Sbz SIO_SET(NGE_MEAR_EE_DIN); 312231505Sbz } else { 313231505Sbz SIO_CLR(NGE_MEAR_EE_DIN); 314231505Sbz } 315231505Sbz nge_delay(sc); 316231505Sbz SIO_SET(NGE_MEAR_EE_CLK); 317231505Sbz nge_delay(sc); 318231505Sbz SIO_CLR(NGE_MEAR_EE_CLK); 319231505Sbz nge_delay(sc); 320231505Sbz } 321231505Sbz 322231505Sbz return; 323231505Sbz} 324231505Sbz 325231505Sbz/* 326231505Sbz * Read a word of data stored in the EEPROM at address 'addr.' 327231505Sbz */ 328231505Sbzstatic void nge_eeprom_getword(sc, addr, dest) 329231505Sbz struct nge_softc *sc; 330231505Sbz int addr; 331231505Sbz u_int16_t *dest; 332269243Sglebius{ 333231505Sbz register int i; 334231505Sbz u_int16_t word = 0; 335231505Sbz 336231505Sbz /* Force EEPROM to idle state. */ 337231505Sbz nge_eeprom_idle(sc); 33821666Swollman 33921666Swollman /* Enter EEPROM access mode. */ 34021666Swollman nge_delay(sc); 34121666Swollman SIO_CLR(NGE_MEAR_EE_CLK); 34221666Swollman nge_delay(sc); 34372093Sasmodai SIO_SET(NGE_MEAR_EE_CSEL); 34421666Swollman nge_delay(sc); 34521666Swollman 34621666Swollman /* 34721666Swollman * Send address of word we want to read. 34821666Swollman */ 34921666Swollman nge_eeprom_putbyte(sc, addr); 35021666Swollman 35189498Sru /* 35289498Sru * Start reading bits from EEPROM. 35389498Sru */ 35489498Sru for (i = 0x8000; i; i >>= 1) { 35589498Sru SIO_SET(NGE_MEAR_EE_CLK); 35689498Sru nge_delay(sc); 35789498Sru if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT) 35889498Sru word |= i; 35989498Sru nge_delay(sc); 36089498Sru SIO_CLR(NGE_MEAR_EE_CLK); 36189498Sru nge_delay(sc); 36289498Sru } 36389498Sru 36489498Sru /* Turn off EEPROM access mode. */ 36589498Sru nge_eeprom_idle(sc); 366203052Sdelphij 367203052Sdelphij *dest = word; 368203052Sdelphij 369203052Sdelphij return; 370203052Sdelphij} 371203052Sdelphij 372203052Sdelphij/* 373203052Sdelphij * Read a sequence of words from the EEPROM. 3741541Srgrimes */ 3751541Srgrimesstatic void nge_read_eeprom(sc, dest, off, cnt, swap) 3761541Srgrimes struct nge_softc *sc; 3771541Srgrimes caddr_t dest; 3781541Srgrimes int off; 3791541Srgrimes int cnt; 3801541Srgrimes int swap; 3811541Srgrimes{ 3821541Srgrimes int i; 3831541Srgrimes u_int16_t word = 0, *ptr; 3841541Srgrimes 385203052Sdelphij for (i = 0; i < cnt; i++) { 38644144Sphk nge_eeprom_getword(sc, off + i, &word); 38785079Sjlemon ptr = (u_int16_t *)(dest + (i * 2)); 388194251Sjamie if (swap) 3891541Srgrimes *ptr = ntohs(word); 3901941Sdg else 3915184Swollman *ptr = word; 39225434Speter } 3931541Srgrimes 39483624Sjlemon return; 395223735Sbz} 396301496Saraujo 3971541Srgrimes/* 3981541Srgrimes * Sync the PHYs by setting data bit and strobing the clock 32 times. 3991541Srgrimes */ 4001541Srgrimesstatic void nge_mii_sync(sc) 401332281Sbrooks struct nge_softc *sc; 402203052Sdelphij{ 403332281Sbrooks register int i; 404102052Ssobomax 405102052Ssobomax SIO_SET(NGE_MEAR_MII_DIR|NGE_MEAR_MII_DATA); 406194251Sjamie 4071541Srgrimes for (i = 0; i < 32; i++) { 4081941Sdg SIO_SET(NGE_MEAR_MII_CLK); 4095187Sdg DELAY(1); 41025434Speter SIO_CLR(NGE_MEAR_MII_CLK); 411332288Sbrooks DELAY(1); 4121541Srgrimes } 413332288Sbrooks 41483624Sjlemon return; 41583624Sjlemon} 41685079Sjlemon 417223735Sbz/* 418301496Saraujo * Clock a series of bits through the MII. 419332991Skib */ 4201541Srgrimesstatic void nge_mii_send(sc, bits, cnt) 4211541Srgrimes struct nge_softc *sc; 42232491Swollman u_int32_t bits; 42332491Swollman int cnt; 42432491Swollman{ 42532491Swollman int i; 42632491Swollman 4271541Srgrimes SIO_CLR(NGE_MEAR_MII_CLK); 4281541Srgrimes 4291541Srgrimes for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 4301541Srgrimes if (bits & i) { 4311541Srgrimes SIO_SET(NGE_MEAR_MII_DATA); 432228571Sglebius } else { 4331541Srgrimes SIO_CLR(NGE_MEAR_MII_DATA); 4341541Srgrimes } 435257761Sglebius DELAY(1); 436257761Sglebius SIO_CLR(NGE_MEAR_MII_CLK); 437257761Sglebius DELAY(1); 438257761Sglebius SIO_SET(NGE_MEAR_MII_CLK); 439257761Sglebius } 440257761Sglebius} 441257761Sglebius 442257761Sglebius/* 44325434Speter * Read an PHY register through the MII. 44425434Speter */ 44525434Speterstatic int nge_mii_readreg(sc, frame) 44625434Speter struct nge_softc *sc; 44725434Speter struct nge_mii_frame *frame; 44825434Speter 44925434Speter{ 45025434Speter int i, ack, s; 45125434Speter 45248021Sphk s = splimp(); 453146986Sthompsa 454146986Sthompsa /* 455146986Sthompsa * Set up frame for RX. 456146986Sthompsa */ 457146986Sthompsa frame->mii_stdelim = NGE_MII_STARTDELIM; 458146986Sthompsa frame->mii_opcode = NGE_MII_READOP; 459146986Sthompsa frame->mii_turnaround = 0; 46048021Sphk frame->mii_data = 0; 46148021Sphk 46248589Sbde CSR_WRITE_4(sc, NGE_MEAR, 0); 46348021Sphk 46448589Sbde /* 46548021Sphk * Turn on data xmit. 46648021Sphk */ 46748589Sbde SIO_SET(NGE_MEAR_MII_DIR); 46848021Sphk 46948589Sbde nge_mii_sync(sc); 47048589Sbde 47148021Sphk /* 47248021Sphk * Send command/address info. 4731541Srgrimes */ 4741541Srgrimes nge_mii_send(sc, frame->mii_stdelim, 2); 4751541Srgrimes nge_mii_send(sc, frame->mii_opcode, 2); 4761541Srgrimes nge_mii_send(sc, frame->mii_phyaddr, 5); 4771541Srgrimes nge_mii_send(sc, frame->mii_regaddr, 5); 4781541Srgrimes 4791541Srgrimes /* Idle bit */ 4801541Srgrimes SIO_CLR((NGE_MEAR_MII_CLK|NGE_MEAR_MII_DATA)); 4811541Srgrimes DELAY(1); 4821541Srgrimes SIO_SET(NGE_MEAR_MII_CLK); 4831541Srgrimes DELAY(1); 4841541Srgrimes 4851541Srgrimes /* Turn off xmit. */ 4861541Srgrimes SIO_CLR(NGE_MEAR_MII_DIR); 4871541Srgrimes /* Check for ack */ 4881541Srgrimes SIO_CLR(NGE_MEAR_MII_CLK); 48952904Sshin DELAY(1); 490159781Smlaier SIO_SET(NGE_MEAR_MII_CLK); 491159781Smlaier DELAY(1); 492159781Smlaier ack = CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA; 493159781Smlaier 494159781Smlaier /* 495159781Smlaier * Now try reading data bits. If the ack failed, we still 496159781Smlaier * need to clock through 16 cycles to keep the PHY(s) in sync. 497159781Smlaier */ 498159781Smlaier if (ack) { 499159781Smlaier for(i = 0; i < 16; i++) { 500159781Smlaier SIO_CLR(NGE_MEAR_MII_CLK); 501159781Smlaier DELAY(1); 502159781Smlaier SIO_SET(NGE_MEAR_MII_CLK); 503159781Smlaier DELAY(1); 504159781Smlaier } 505159781Smlaier goto fail; 506159781Smlaier } 507159781Smlaier 508159781Smlaier for (i = 0x8000; i; i >>= 1) { 509159781Smlaier SIO_CLR(NGE_MEAR_MII_CLK); 510159781Smlaier DELAY(1); 511159781Smlaier if (!ack) { 512159781Smlaier if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA) 513159781Smlaier frame->mii_data |= i; 514159781Smlaier DELAY(1); 515159781Smlaier } 516332493Sbrooks SIO_SET(NGE_MEAR_MII_CLK); 517159781Smlaier DELAY(1); 518159781Smlaier } 519332493Sbrooks 520159781Smlaierfail: 521159781Smlaier 522270822Smelifaro SIO_CLR(NGE_MEAR_MII_CLK); 523270822Smelifaro DELAY(1); 524270822Smelifaro SIO_SET(NGE_MEAR_MII_CLK); 525270822Smelifaro DELAY(1); 526270822Smelifaro 527270822Smelifaro splx(s); 528270822Smelifaro 529270822Smelifaro if (ack) 530270822Smelifaro return(1); 531270822Smelifaro return(0); 532270822Smelifaro} 533270822Smelifaro 534270822Smelifaro/* 535324472Ssephe * Write to a PHY register through the MII. 536324472Ssephe */ 537324472Ssephestatic int nge_mii_writereg(sc, frame) 538324472Ssephe struct nge_softc *sc; 539324472Ssephe struct nge_mii_frame *frame; 540324472Ssephe 541324472Ssephe{ 542324472Ssephe int s; 543324472Ssephe 544324472Ssephe s = splimp(); 545324472Ssephe /* 546324472Ssephe * Set up frame for TX. 547324472Ssephe */ 548324472Ssephe 549324472Ssephe frame->mii_stdelim = NGE_MII_STARTDELIM; 550324472Ssephe frame->mii_opcode = NGE_MII_WRITEOP; 551324472Ssephe frame->mii_turnaround = NGE_MII_TURNAROUND; 552324472Ssephe 553324472Ssephe /* 554324472Ssephe * Turn on data output. 555324472Ssephe */ 556324472Ssephe SIO_SET(NGE_MEAR_MII_DIR); 557324472Ssephe 558324472Ssephe nge_mii_sync(sc); 559324472Ssephe 560324472Ssephe nge_mii_send(sc, frame->mii_stdelim, 2); 561324472Ssephe nge_mii_send(sc, frame->mii_opcode, 2); 562324472Ssephe nge_mii_send(sc, frame->mii_phyaddr, 5); 563324472Ssephe nge_mii_send(sc, frame->mii_regaddr, 5); 564324472Ssephe nge_mii_send(sc, frame->mii_turnaround, 2); 565324472Ssephe nge_mii_send(sc, frame->mii_data, 16); 566324472Ssephe 567324472Ssephe /* Idle bit. */ 568324472Ssephe SIO_SET(NGE_MEAR_MII_CLK); 569324472Ssephe DELAY(1); 570324472Ssephe SIO_CLR(NGE_MEAR_MII_CLK); 571332991Skib DELAY(1); 572332991Skib 573104355Smike /* 574104355Smike * Turn off xmit. 57555205Speter */ 57630354Sphk SIO_CLR(NGE_MEAR_MII_DIR); 57730354Sphk 57830354Sphk splx(s); 57930354Sphk 58030354Sphk return(0); 58130354Sphk} 58255205Speter 58352904Sshinstatic int nge_miibus_readreg(dev, phy, reg) 584104355Smike device_t dev; 585104360Smike int phy, reg; 58652904Sshin{ 58752904Sshin struct nge_softc *sc; 58852904Sshin struct nge_mii_frame frame; 589104360Smike 590104360Smike sc = device_get_softc(dev); 591104360Smike 592104360Smike bzero((char *)&frame, sizeof(frame)); 59352904Sshin 59452904Sshin frame.mii_phyaddr = phy; 5954507Sbde frame.mii_regaddr = reg; 596 nge_mii_readreg(sc, &frame); 597 598 return(frame.mii_data); 599} 600 601static int nge_miibus_writereg(dev, phy, reg, data) 602 device_t dev; 603 int phy, reg, data; 604{ 605 struct nge_softc *sc; 606 struct nge_mii_frame frame; 607 608 sc = device_get_softc(dev); 609 610 bzero((char *)&frame, sizeof(frame)); 611 612 frame.mii_phyaddr = phy; 613 frame.mii_regaddr = reg; 614 frame.mii_data = data; 615 nge_mii_writereg(sc, &frame); 616 617 return(0); 618} 619 620static void nge_miibus_statchg(dev) 621 device_t dev; 622{ 623 struct nge_softc *sc; 624 struct mii_data *mii; 625 626 sc = device_get_softc(dev); 627 mii = device_get_softc(sc->nge_miibus); 628 629 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 630 NGE_SETBIT(sc, NGE_TX_CFG, 631 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 632 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 633 } else { 634 NGE_CLRBIT(sc, NGE_TX_CFG, 635 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 636 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 637 } 638 639 /* If we have a 1000Mbps link, set the mode_1000 bit. */ 640 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX || 641 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) { 642 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_MODE_1000); 643 } else { 644 NGE_CLRBIT(sc, NGE_CFG, NGE_CFG_MODE_1000); 645 } 646 647 return; 648} 649 650static u_int32_t nge_crc(sc, addr) 651 struct nge_softc *sc; 652 caddr_t addr; 653{ 654 u_int32_t crc, carry; 655 int i, j; 656 u_int8_t c; 657 658 /* Compute CRC for the address value. */ 659 crc = 0xFFFFFFFF; /* initial value */ 660 661 for (i = 0; i < 6; i++) { 662 c = *(addr + i); 663 for (j = 0; j < 8; j++) { 664 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 665 crc <<= 1; 666 c >>= 1; 667 if (carry) 668 crc = (crc ^ 0x04c11db6) | carry; 669 } 670 } 671 672 /* 673 * return the filter bit position 674 */ 675 676 return((crc >> 21) & 0x00000FFF); 677} 678 679static void nge_setmulti(sc) 680 struct nge_softc *sc; 681{ 682 struct ifnet *ifp; 683 struct ifmultiaddr *ifma; 684 u_int32_t h = 0, i, filtsave; 685 int bit, index; 686 687 ifp = &sc->arpcom.ac_if; 688 689 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 690 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 691 NGE_RXFILTCTL_MCHASH|NGE_RXFILTCTL_UCHASH); 692 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLMULTI); 693 return; 694 } 695 696 /* 697 * We have to explicitly enable the multicast hash table 698 * on the NatSemi chip if we want to use it, which we do. 699 * We also have to tell it that we don't want to use the 700 * hash table for matching unicast addresses. 701 */ 702 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_MCHASH); 703 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 704 NGE_RXFILTCTL_ALLMULTI|NGE_RXFILTCTL_UCHASH); 705 706 filtsave = CSR_READ_4(sc, NGE_RXFILT_CTL); 707 708 /* first, zot all the existing hash bits */ 709 for (i = 0; i < NGE_MCAST_FILTER_LEN; i += 2) { 710 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + i); 711 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 0); 712 } 713 714 /* 715 * From the 11 bits returned by the crc routine, the top 7 716 * bits represent the 16-bit word in the mcast hash table 717 * that needs to be updated, and the lower 4 bits represent 718 * which bit within that byte needs to be set. 719 */ 720 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 721 if (ifma->ifma_addr->sa_family != AF_LINK) 722 continue; 723 h = nge_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 724 index = (h >> 4) & 0x7F; 725 bit = h & 0xF; 726 CSR_WRITE_4(sc, NGE_RXFILT_CTL, 727 NGE_FILTADDR_MCAST_LO + (index * 2)); 728 NGE_SETBIT(sc, NGE_RXFILT_DATA, (1 << bit)); 729 } 730 731 CSR_WRITE_4(sc, NGE_RXFILT_CTL, filtsave); 732 733 return; 734} 735 736static void nge_reset(sc) 737 struct nge_softc *sc; 738{ 739 register int i; 740 741 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RESET); 742 743 for (i = 0; i < NGE_TIMEOUT; i++) { 744 if (!(CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET)) 745 break; 746 } 747 748 if (i == NGE_TIMEOUT) 749 printf("nge%d: reset never completed\n", sc->nge_unit); 750 751 /* Wait a little while for the chip to get its brains in order. */ 752 DELAY(1000); 753 754 /* 755 * If this is a NetSemi chip, make sure to clear 756 * PME mode. 757 */ 758 CSR_WRITE_4(sc, NGE_CLKRUN, NGE_CLKRUN_PMESTS); 759 CSR_WRITE_4(sc, NGE_CLKRUN, 0); 760 761 return; 762} 763 764/* 765 * Probe for an NatSemi chip. Check the PCI vendor and device 766 * IDs against our list and return a device name if we find a match. 767 */ 768static int nge_probe(dev) 769 device_t dev; 770{ 771 struct nge_type *t; 772 773 t = nge_devs; 774 775 while(t->nge_name != NULL) { 776 if ((pci_get_vendor(dev) == t->nge_vid) && 777 (pci_get_device(dev) == t->nge_did)) { 778 device_set_desc(dev, t->nge_name); 779 return(0); 780 } 781 t++; 782 } 783 784 return(ENXIO); 785} 786 787/* 788 * Attach the interface. Allocate softc structures, do ifmedia 789 * setup and ethernet/BPF attach. 790 */ 791static int nge_attach(dev) 792 device_t dev; 793{ 794 int s; 795 u_char eaddr[ETHER_ADDR_LEN]; 796 u_int32_t command; 797 struct nge_softc *sc; 798 struct ifnet *ifp; 799 int unit, error = 0, rid; 800 801 s = splimp(); 802 803 sc = device_get_softc(dev); 804 unit = device_get_unit(dev); 805 bzero(sc, sizeof(struct nge_softc)); 806 807 mtx_init(&sc->nge_mtx, device_get_nameunit(dev), MTX_DEF|MTX_RECURSE); 808 809 /* 810 * Handle power management nonsense. 811 */ 812 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 813 u_int32_t iobase, membase, irq; 814 815 /* Save important PCI config data. */ 816 iobase = pci_read_config(dev, NGE_PCI_LOIO, 4); 817 membase = pci_read_config(dev, NGE_PCI_LOMEM, 4); 818 irq = pci_read_config(dev, NGE_PCI_INTLINE, 4); 819 820 /* Reset the power state. */ 821 printf("nge%d: chip is in D%d power mode " 822 "-- setting to D0\n", unit, 823 pci_get_powerstate(dev)); 824 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 825 826 /* Restore PCI config data. */ 827 pci_write_config(dev, NGE_PCI_LOIO, iobase, 4); 828 pci_write_config(dev, NGE_PCI_LOMEM, membase, 4); 829 pci_write_config(dev, NGE_PCI_INTLINE, irq, 4); 830 } 831 832 /* 833 * Map control/status registers. 834 */ 835 pci_enable_busmaster(dev); 836 pci_enable_io(dev, PCIM_CMD_PORTEN); 837 pci_enable_io(dev, PCIM_CMD_MEMEN); 838 command = pci_read_config(dev, PCIR_COMMAND, 4); 839 840#ifdef NGE_USEIOSPACE 841 if (!(command & PCIM_CMD_PORTEN)) { 842 printf("nge%d: failed to enable I/O ports!\n", unit); 843 error = ENXIO;; 844 goto fail; 845 } 846#else 847 if (!(command & PCIM_CMD_MEMEN)) { 848 printf("nge%d: failed to enable memory mapping!\n", unit); 849 error = ENXIO;; 850 goto fail; 851 } 852#endif 853 854 rid = NGE_RID; 855 sc->nge_res = bus_alloc_resource(dev, NGE_RES, &rid, 856 0, ~0, 1, RF_ACTIVE); 857 858 if (sc->nge_res == NULL) { 859 printf("nge%d: couldn't map ports/memory\n", unit); 860 error = ENXIO; 861 goto fail; 862 } 863 864 sc->nge_btag = rman_get_bustag(sc->nge_res); 865 sc->nge_bhandle = rman_get_bushandle(sc->nge_res); 866 867 /* Allocate interrupt */ 868 rid = 0; 869 sc->nge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 870 RF_SHAREABLE | RF_ACTIVE); 871 872 if (sc->nge_irq == NULL) { 873 printf("nge%d: couldn't map interrupt\n", unit); 874 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 875 error = ENXIO; 876 goto fail; 877 } 878 879 error = bus_setup_intr(dev, sc->nge_irq, INTR_TYPE_NET, 880 nge_intr, sc, &sc->nge_intrhand); 881 882 if (error) { 883 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 884 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 885 printf("nge%d: couldn't set up irq\n", unit); 886 goto fail; 887 } 888 889 /* Reset the adapter. */ 890 nge_reset(sc); 891 892 /* 893 * Get station address from the EEPROM. 894 */ 895 nge_read_eeprom(sc, (caddr_t)&eaddr[4], NGE_EE_NODEADDR, 1, 0); 896 nge_read_eeprom(sc, (caddr_t)&eaddr[2], NGE_EE_NODEADDR + 1, 1, 0); 897 nge_read_eeprom(sc, (caddr_t)&eaddr[0], NGE_EE_NODEADDR + 2, 1, 0); 898 899 /* 900 * A NatSemi chip was detected. Inform the world. 901 */ 902 printf("nge%d: Ethernet address: %6D\n", unit, eaddr, ":"); 903 904 sc->nge_unit = unit; 905 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 906 907 sc->nge_ldata = contigmalloc(sizeof(struct nge_list_data), M_DEVBUF, 908 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 909 910 if (sc->nge_ldata == NULL) { 911 printf("nge%d: no memory for list buffers!\n", unit); 912 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 913 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 914 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 915 error = ENXIO; 916 goto fail; 917 } 918 bzero(sc->nge_ldata, sizeof(struct nge_list_data)); 919 920 /* Try to allocate memory for jumbo buffers. */ 921 if (nge_alloc_jumbo_mem(sc)) { 922 printf("nge%d: jumbo buffer allocation failed\n", 923 sc->nge_unit); 924 contigfree(sc->nge_ldata, 925 sizeof(struct nge_list_data), M_DEVBUF); 926 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 927 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 928 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 929 error = ENXIO; 930 goto fail; 931 } 932 933 ifp = &sc->arpcom.ac_if; 934 ifp->if_softc = sc; 935 ifp->if_unit = unit; 936 ifp->if_name = "nge"; 937 ifp->if_mtu = ETHERMTU; 938 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 939 ifp->if_ioctl = nge_ioctl; 940 ifp->if_output = ether_output; 941 ifp->if_start = nge_start; 942 ifp->if_watchdog = nge_watchdog; 943 ifp->if_init = nge_init; 944 ifp->if_baudrate = 1000000000; 945 ifp->if_snd.ifq_maxlen = NGE_TX_LIST_CNT - 1; 946 ifp->if_hwassist = NGE_CSUM_FEATURES; 947 948 /* 949 * Do MII setup. 950 */ 951 if (mii_phy_probe(dev, &sc->nge_miibus, 952 nge_ifmedia_upd, nge_ifmedia_sts)) { 953 printf("nge%d: MII without any PHY!\n", sc->nge_unit); 954 nge_free_jumbo_mem(sc); 955 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 956 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 957 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 958 error = ENXIO; 959 goto fail; 960 } 961 962 /* 963 * Call MI attach routine. 964 */ 965 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 966 callout_handle_init(&sc->nge_stat_ch); 967 968fail: 969 splx(s); 970 mtx_destroy(&sc->nge_mtx); 971 return(error); 972} 973 974static int nge_detach(dev) 975 device_t dev; 976{ 977 struct nge_softc *sc; 978 struct ifnet *ifp; 979 int s; 980 981 s = splimp(); 982 983 sc = device_get_softc(dev); 984 ifp = &sc->arpcom.ac_if; 985 986 nge_reset(sc); 987 nge_stop(sc); 988 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 989 990 bus_generic_detach(dev); 991 device_delete_child(dev, sc->nge_miibus); 992 993 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 994 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 995 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 996 997 contigfree(sc->nge_ldata, sizeof(struct nge_list_data), M_DEVBUF); 998 nge_free_jumbo_mem(sc); 999 1000 splx(s); 1001 mtx_destroy(&sc->nge_mtx); 1002 1003 return(0); 1004} 1005 1006/* 1007 * Initialize the transmit descriptors. 1008 */ 1009static int nge_list_tx_init(sc) 1010 struct nge_softc *sc; 1011{ 1012 struct nge_list_data *ld; 1013 struct nge_ring_data *cd; 1014 int i; 1015 1016 cd = &sc->nge_cdata; 1017 ld = sc->nge_ldata; 1018 1019 for (i = 0; i < NGE_TX_LIST_CNT; i++) { 1020 if (i == (NGE_TX_LIST_CNT - 1)) { 1021 ld->nge_tx_list[i].nge_nextdesc = 1022 &ld->nge_tx_list[0]; 1023 ld->nge_tx_list[i].nge_next = 1024 vtophys(&ld->nge_tx_list[0]); 1025 } else { 1026 ld->nge_tx_list[i].nge_nextdesc = 1027 &ld->nge_tx_list[i + 1]; 1028 ld->nge_tx_list[i].nge_next = 1029 vtophys(&ld->nge_tx_list[i + 1]); 1030 } 1031 ld->nge_tx_list[i].nge_mbuf = NULL; 1032 ld->nge_tx_list[i].nge_ptr = 0; 1033 ld->nge_tx_list[i].nge_ctl = 0; 1034 } 1035 1036 cd->nge_tx_prod = cd->nge_tx_cons = cd->nge_tx_cnt = 0; 1037 1038 return(0); 1039} 1040 1041 1042/* 1043 * Initialize the RX descriptors and allocate mbufs for them. Note that 1044 * we arrange the descriptors in a closed ring, so that the last descriptor 1045 * points back to the first. 1046 */ 1047static int nge_list_rx_init(sc) 1048 struct nge_softc *sc; 1049{ 1050 struct nge_list_data *ld; 1051 struct nge_ring_data *cd; 1052 int i; 1053 1054 ld = sc->nge_ldata; 1055 cd = &sc->nge_cdata; 1056 1057 for (i = 0; i < NGE_RX_LIST_CNT; i++) { 1058 if (nge_newbuf(sc, &ld->nge_rx_list[i], NULL) == ENOBUFS) 1059 return(ENOBUFS); 1060 if (i == (NGE_RX_LIST_CNT - 1)) { 1061 ld->nge_rx_list[i].nge_nextdesc = 1062 &ld->nge_rx_list[0]; 1063 ld->nge_rx_list[i].nge_next = 1064 vtophys(&ld->nge_rx_list[0]); 1065 } else { 1066 ld->nge_rx_list[i].nge_nextdesc = 1067 &ld->nge_rx_list[i + 1]; 1068 ld->nge_rx_list[i].nge_next = 1069 vtophys(&ld->nge_rx_list[i + 1]); 1070 } 1071 } 1072 1073 cd->nge_rx_prod = 0; 1074 1075 return(0); 1076} 1077 1078/* 1079 * Initialize an RX descriptor and attach an MBUF cluster. 1080 */ 1081static int nge_newbuf(sc, c, m) 1082 struct nge_softc *sc; 1083 struct nge_desc *c; 1084 struct mbuf *m; 1085{ 1086 struct mbuf *m_new = NULL; 1087 caddr_t *buf = NULL; 1088 1089 if (m == NULL) { 1090 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1091 if (m_new == NULL) { 1092 printf("nge%d: no memory for rx list " 1093 "-- packet dropped!\n", sc->nge_unit); 1094 return(ENOBUFS); 1095 } 1096 1097 /* Allocate the jumbo buffer */ 1098 buf = nge_jalloc(sc); 1099 if (buf == NULL) { 1100#ifdef NGE_VERBOSE 1101 printf("nge%d: jumbo allocation failed " 1102 "-- packet dropped!\n", sc->nge_unit); 1103#endif 1104 m_freem(m_new); 1105 return(ENOBUFS); 1106 } 1107 /* Attach the buffer to the mbuf */ 1108 m_new->m_data = (void *)buf; 1109 m_new->m_len = m_new->m_pkthdr.len = NGE_JUMBO_FRAMELEN; 1110 MEXTADD(m_new, buf, NGE_JUMBO_FRAMELEN, nge_jfree, 1111 (struct nge_softc *)sc, 0, EXT_NET_DRV); 1112 } else { 1113 m_new = m; 1114 m_new->m_len = m_new->m_pkthdr.len = NGE_JUMBO_FRAMELEN; 1115 m_new->m_data = m_new->m_ext.ext_buf; 1116 } 1117 1118 m_adj(m_new, sizeof(u_int64_t)); 1119 1120 c->nge_mbuf = m_new; 1121 c->nge_ptr = vtophys(mtod(m_new, caddr_t)); 1122 c->nge_ctl = m_new->m_len; 1123 c->nge_extsts = 0; 1124 1125 return(0); 1126} 1127 1128static int nge_alloc_jumbo_mem(sc) 1129 struct nge_softc *sc; 1130{ 1131 caddr_t ptr; 1132 register int i; 1133 struct nge_jpool_entry *entry; 1134 1135 /* Grab a big chunk o' storage. */ 1136 sc->nge_cdata.nge_jumbo_buf = contigmalloc(NGE_JMEM, M_DEVBUF, 1137 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1138 1139 if (sc->nge_cdata.nge_jumbo_buf == NULL) { 1140 printf("nge%d: no memory for jumbo buffers!\n", sc->nge_unit); 1141 return(ENOBUFS); 1142 } 1143 1144 SLIST_INIT(&sc->nge_jfree_listhead); 1145 SLIST_INIT(&sc->nge_jinuse_listhead); 1146 1147 /* 1148 * Now divide it up into 9K pieces and save the addresses 1149 * in an array. 1150 */ 1151 ptr = sc->nge_cdata.nge_jumbo_buf; 1152 for (i = 0; i < NGE_JSLOTS; i++) { 1153 sc->nge_cdata.nge_jslots[i] = ptr; 1154 ptr += NGE_JLEN; 1155 entry = malloc(sizeof(struct nge_jpool_entry), 1156 M_DEVBUF, M_NOWAIT); 1157 if (entry == NULL) { 1158 printf("nge%d: no memory for jumbo " 1159 "buffer queue!\n", sc->nge_unit); 1160 return(ENOBUFS); 1161 } 1162 entry->slot = i; 1163 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead, 1164 entry, jpool_entries); 1165 } 1166 1167 return(0); 1168} 1169 1170static void nge_free_jumbo_mem(sc) 1171 struct nge_softc *sc; 1172{ 1173 register int i; 1174 struct nge_jpool_entry *entry; 1175 1176 for (i = 0; i < NGE_JSLOTS; i++) { 1177 entry = SLIST_FIRST(&sc->nge_jfree_listhead); 1178 SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jpool_entries); 1179 free(entry, M_DEVBUF); 1180 } 1181 1182 contigfree(sc->nge_cdata.nge_jumbo_buf, NGE_JMEM, M_DEVBUF); 1183 1184 return; 1185} 1186 1187/* 1188 * Allocate a jumbo buffer. 1189 */ 1190static void *nge_jalloc(sc) 1191 struct nge_softc *sc; 1192{ 1193 struct nge_jpool_entry *entry; 1194 1195 entry = SLIST_FIRST(&sc->nge_jfree_listhead); 1196 1197 if (entry == NULL) { 1198#ifdef NGE_VERBOSE 1199 printf("nge%d: no free jumbo buffers\n", sc->nge_unit); 1200#endif 1201 return(NULL); 1202 } 1203 1204 SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jpool_entries); 1205 SLIST_INSERT_HEAD(&sc->nge_jinuse_listhead, entry, jpool_entries); 1206 return(sc->nge_cdata.nge_jslots[entry->slot]); 1207} 1208 1209/* 1210 * Release a jumbo buffer. 1211 */ 1212static void nge_jfree(buf, args) 1213 caddr_t buf; 1214 void *args; 1215{ 1216 struct nge_softc *sc; 1217 int i; 1218 struct nge_jpool_entry *entry; 1219 1220 /* Extract the softc struct pointer. */ 1221 sc = args; 1222 1223 if (sc == NULL) 1224 panic("nge_jfree: can't find softc pointer!"); 1225 1226 /* calculate the slot this buffer belongs to */ 1227 i = ((vm_offset_t)buf 1228 - (vm_offset_t)sc->nge_cdata.nge_jumbo_buf) / NGE_JLEN; 1229 1230 if ((i < 0) || (i >= NGE_JSLOTS)) 1231 panic("nge_jfree: asked to free buffer that we don't manage!"); 1232 1233 entry = SLIST_FIRST(&sc->nge_jinuse_listhead); 1234 if (entry == NULL) 1235 panic("nge_jfree: buffer not in use!"); 1236 entry->slot = i; 1237 SLIST_REMOVE_HEAD(&sc->nge_jinuse_listhead, jpool_entries); 1238 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead, entry, jpool_entries); 1239 1240 return; 1241} 1242/* 1243 * A frame has been uploaded: pass the resulting mbuf chain up to 1244 * the higher level protocols. 1245 */ 1246static void nge_rxeof(sc) 1247 struct nge_softc *sc; 1248{ 1249 struct ether_header *eh; 1250 struct mbuf *m; 1251 struct ifnet *ifp; 1252 struct nge_desc *cur_rx; 1253 int i, total_len = 0; 1254 u_int32_t rxstat; 1255 1256 ifp = &sc->arpcom.ac_if; 1257 i = sc->nge_cdata.nge_rx_prod; 1258 1259 while(NGE_OWNDESC(&sc->nge_ldata->nge_rx_list[i])) { 1260 struct mbuf *m0 = NULL; 1261 u_int32_t extsts; 1262 1263 cur_rx = &sc->nge_ldata->nge_rx_list[i]; 1264 rxstat = cur_rx->nge_rxstat; 1265 extsts = cur_rx->nge_extsts; 1266 m = cur_rx->nge_mbuf; 1267 cur_rx->nge_mbuf = NULL; 1268 total_len = NGE_RXBYTES(cur_rx); 1269 NGE_INC(i, NGE_RX_LIST_CNT); 1270 1271 /* 1272 * If an error occurs, update stats, clear the 1273 * status word and leave the mbuf cluster in place: 1274 * it should simply get re-used next time this descriptor 1275 * comes up in the ring. 1276 */ 1277 if (!(rxstat & NGE_CMDSTS_PKT_OK)) { 1278 ifp->if_ierrors++; 1279 nge_newbuf(sc, cur_rx, m); 1280 continue; 1281 } 1282 1283 1284 /* 1285 * Ok. NatSemi really screwed up here. This is the 1286 * only gigE chip I know of with alignment constraints 1287 * on receive buffers. RX buffers must be 64-bit aligned. 1288 */ 1289 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 1290 NULL); 1291 nge_newbuf(sc, cur_rx, m); 1292 if (m0 == NULL) { 1293 printf("nge%d: no receive buffers " 1294 "available -- packet dropped!\n", 1295 sc->nge_unit); 1296 ifp->if_ierrors++; 1297 continue; 1298 } 1299 m = m0; 1300 1301 ifp->if_ipackets++; 1302 eh = mtod(m, struct ether_header *); 1303 1304 /* Remove header from mbuf and pass it on. */ 1305 m_adj(m, sizeof(struct ether_header)); 1306 1307 /* Do IP checksum checking. */ 1308 if (extsts & NGE_RXEXTSTS_IPPKT) 1309 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1310 if (!(extsts & NGE_RXEXTSTS_IPCSUMERR)) 1311 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1312 if ((extsts & NGE_RXEXTSTS_TCPPKT && 1313 !(extsts & NGE_RXEXTSTS_TCPCSUMERR)) || 1314 (extsts & NGE_RXEXTSTS_UDPPKT && 1315 !(extsts & NGE_RXEXTSTS_UDPCSUMERR))) { 1316 m->m_pkthdr.csum_flags |= 1317 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1318 m->m_pkthdr.csum_data = 0xffff; 1319 } 1320 1321#if NVLAN > 0 1322 /* 1323 * If we received a packet with a vlan tag, pass it 1324 * to vlan_input() instead of ether_input(). 1325 */ 1326 if (extsts & NGE_RXEXTSTS_VLANPKT) { 1327 vlan_input_tag(eh, m, extsts & NGE_RXEXTSTS_VTCI); 1328 continue; 1329 } 1330#endif 1331 1332 ether_input(ifp, eh, m); 1333 } 1334 1335 sc->nge_cdata.nge_rx_prod = i; 1336 1337 return; 1338} 1339 1340void nge_rxeoc(sc) 1341 struct nge_softc *sc; 1342{ 1343 struct ifnet *ifp; 1344 1345 ifp = &sc->arpcom.ac_if; 1346 nge_rxeof(sc); 1347 ifp->if_flags &= ~IFF_RUNNING; 1348 nge_init(sc); 1349 return; 1350} 1351 1352/* 1353 * A frame was downloaded to the chip. It's safe for us to clean up 1354 * the list buffers. 1355 */ 1356 1357static void nge_txeof(sc) 1358 struct nge_softc *sc; 1359{ 1360 struct nge_desc *cur_tx = NULL; 1361 struct ifnet *ifp; 1362 u_int32_t idx; 1363 1364 ifp = &sc->arpcom.ac_if; 1365 1366 /* Clear the timeout timer. */ 1367 ifp->if_timer = 0; 1368 1369 /* 1370 * Go through our tx list and free mbufs for those 1371 * frames that have been transmitted. 1372 */ 1373 idx = sc->nge_cdata.nge_tx_cons; 1374 while (idx != sc->nge_cdata.nge_tx_prod) { 1375 cur_tx = &sc->nge_ldata->nge_tx_list[idx]; 1376 1377 if (NGE_OWNDESC(cur_tx)) 1378 break; 1379 1380 if (cur_tx->nge_ctl & NGE_CMDSTS_MORE) { 1381 sc->nge_cdata.nge_tx_cnt--; 1382 NGE_INC(idx, NGE_TX_LIST_CNT); 1383 continue; 1384 } 1385 1386 if (!(cur_tx->nge_ctl & NGE_CMDSTS_PKT_OK)) { 1387 ifp->if_oerrors++; 1388 if (cur_tx->nge_txstat & NGE_TXSTAT_EXCESSCOLLS) 1389 ifp->if_collisions++; 1390 if (cur_tx->nge_txstat & NGE_TXSTAT_OUTOFWINCOLL) 1391 ifp->if_collisions++; 1392 } 1393 1394 ifp->if_collisions += 1395 (cur_tx->nge_txstat & NGE_TXSTAT_COLLCNT) >> 16; 1396 1397 ifp->if_opackets++; 1398 if (cur_tx->nge_mbuf != NULL) { 1399 m_freem(cur_tx->nge_mbuf); 1400 cur_tx->nge_mbuf = NULL; 1401 } 1402 1403 sc->nge_cdata.nge_tx_cnt--; 1404 NGE_INC(idx, NGE_TX_LIST_CNT); 1405 ifp->if_timer = 0; 1406 } 1407 1408 sc->nge_cdata.nge_tx_cons = idx; 1409 1410 if (cur_tx != NULL) 1411 ifp->if_flags &= ~IFF_OACTIVE; 1412 1413 return; 1414} 1415 1416static void nge_tick(xsc) 1417 void *xsc; 1418{ 1419 struct nge_softc *sc; 1420 struct mii_data *mii; 1421 struct ifnet *ifp; 1422 int s; 1423 1424 s = splimp(); 1425 1426 sc = xsc; 1427 ifp = &sc->arpcom.ac_if; 1428 1429 mii = device_get_softc(sc->nge_miibus); 1430 mii_tick(mii); 1431 1432 if (!sc->nge_link) { 1433 mii_pollstat(mii); 1434 if (mii->mii_media_status & IFM_ACTIVE && 1435 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1436 sc->nge_link++; 1437 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX) 1438 printf("nge%d: gigabit link up\n", 1439 sc->nge_unit); 1440 if (ifp->if_snd.ifq_head != NULL) 1441 nge_start(ifp); 1442 } else 1443 sc->nge_stat_ch = timeout(nge_tick, sc, hz); 1444 } 1445 1446 1447 splx(s); 1448 1449 return; 1450} 1451 1452static void nge_intr(arg) 1453 void *arg; 1454{ 1455 struct nge_softc *sc; 1456 struct ifnet *ifp; 1457 u_int32_t status; 1458 1459 sc = arg; 1460 ifp = &sc->arpcom.ac_if; 1461 1462 /* Supress unwanted interrupts */ 1463 if (!(ifp->if_flags & IFF_UP)) { 1464 nge_stop(sc); 1465 return; 1466 } 1467 1468 /* Disable interrupts. */ 1469 CSR_WRITE_4(sc, NGE_IER, 0); 1470 1471 for (;;) { 1472 /* Reading the ISR register clears all interrupts. */ 1473 status = CSR_READ_4(sc, NGE_ISR); 1474 1475 if ((status & NGE_INTRS) == 0) 1476 break; 1477 1478 if ((status & NGE_ISR_TX_DESC_OK) || 1479 (status & NGE_ISR_TX_ERR) || 1480 (status & NGE_ISR_TX_OK) || 1481 (status & NGE_ISR_TX_IDLE)) 1482 nge_txeof(sc); 1483 1484 if ((status & NGE_ISR_RX_DESC_OK) || 1485 (status & NGE_ISR_RX_OK)) 1486 nge_rxeof(sc); 1487 1488 if ((status & NGE_ISR_RX_ERR) || 1489 (status & NGE_ISR_RX_OFLOW)) { 1490 nge_rxeoc(sc); 1491 } 1492 1493 if (status & NGE_ISR_SYSERR) { 1494 nge_reset(sc); 1495 ifp->if_flags &= ~IFF_RUNNING; 1496 nge_init(sc); 1497 } 1498 1499 if (status & NGE_IMR_PHY_INTR) { 1500 sc->nge_link = 0; 1501 nge_tick(sc); 1502 } 1503 } 1504 1505 /* Re-enable interrupts. */ 1506 CSR_WRITE_4(sc, NGE_IER, 1); 1507 1508 if (ifp->if_snd.ifq_head != NULL) 1509 nge_start(ifp); 1510 1511 return; 1512} 1513 1514/* 1515 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1516 * pointers to the fragment pointers. 1517 */ 1518static int nge_encap(sc, m_head, txidx) 1519 struct nge_softc *sc; 1520 struct mbuf *m_head; 1521 u_int32_t *txidx; 1522{ 1523 struct nge_desc *f = NULL; 1524 struct mbuf *m; 1525 int frag, cur, cnt = 0; 1526#if NVLAN > 0 1527 struct ifvlan *ifv = NULL; 1528 1529 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 1530 m_head->m_pkthdr.rcvif != NULL && 1531 m_head->m_pkthdr.rcvif->if_type == IFT_8021_VLAN) 1532 ifv = m_head->m_pkthdr.rcvif->if_softc; 1533#endif 1534 1535 /* 1536 * Start packing the mbufs in this chain into 1537 * the fragment pointers. Stop when we run out 1538 * of fragments or hit the end of the mbuf chain. 1539 */ 1540 m = m_head; 1541 cur = frag = *txidx; 1542 1543 for (m = m_head; m != NULL; m = m->m_next) { 1544 if (m->m_len != 0) { 1545 if ((NGE_TX_LIST_CNT - 1546 (sc->nge_cdata.nge_tx_cnt + cnt)) < 2) 1547 return(ENOBUFS); 1548 f = &sc->nge_ldata->nge_tx_list[frag]; 1549 f->nge_ctl = NGE_CMDSTS_MORE | m->m_len; 1550 f->nge_ptr = vtophys(mtod(m, vm_offset_t)); 1551 if (cnt != 0) 1552 f->nge_ctl |= NGE_CMDSTS_OWN; 1553 cur = frag; 1554 NGE_INC(frag, NGE_TX_LIST_CNT); 1555 cnt++; 1556 } 1557 } 1558 1559 if (m != NULL) 1560 return(ENOBUFS); 1561 1562 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts = 0; 1563 if (m_head->m_pkthdr.csum_flags) { 1564 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1565 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1566 NGE_TXEXTSTS_IPCSUM; 1567 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1568 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1569 NGE_TXEXTSTS_TCPCSUM; 1570 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 1571 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1572 NGE_TXEXTSTS_UDPCSUM; 1573 } 1574 1575#if NVLAN > 0 1576 if (ifv != NULL) { 1577 sc->nge_ldata->nge_tx_list[cur].nge_extsts |= 1578 (NGE_TXEXTSTS_VLANPKT|ifv->ifv_tag); 1579 } 1580#endif 1581 1582 sc->nge_ldata->nge_tx_list[cur].nge_mbuf = m_head; 1583 sc->nge_ldata->nge_tx_list[cur].nge_ctl &= ~NGE_CMDSTS_MORE; 1584 sc->nge_ldata->nge_tx_list[*txidx].nge_ctl |= NGE_CMDSTS_OWN; 1585 sc->nge_cdata.nge_tx_cnt += cnt; 1586 *txidx = frag; 1587 1588 return(0); 1589} 1590 1591/* 1592 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1593 * to the mbuf data regions directly in the transmit lists. We also save a 1594 * copy of the pointers since the transmit list fragment pointers are 1595 * physical addresses. 1596 */ 1597 1598static void nge_start(ifp) 1599 struct ifnet *ifp; 1600{ 1601 struct nge_softc *sc; 1602 struct mbuf *m_head = NULL; 1603 u_int32_t idx; 1604 1605 sc = ifp->if_softc; 1606 1607 if (!sc->nge_link) 1608 return; 1609 1610 idx = sc->nge_cdata.nge_tx_prod; 1611 1612 if (ifp->if_flags & IFF_OACTIVE) 1613 return; 1614 1615 while(sc->nge_ldata->nge_tx_list[idx].nge_mbuf == NULL) { 1616 IF_DEQUEUE(&ifp->if_snd, m_head); 1617 if (m_head == NULL) 1618 break; 1619 1620 if (nge_encap(sc, m_head, &idx)) { 1621 IF_PREPEND(&ifp->if_snd, m_head); 1622 ifp->if_flags |= IFF_OACTIVE; 1623 break; 1624 } 1625 1626 /* 1627 * If there's a BPF listener, bounce a copy of this frame 1628 * to him. 1629 */ 1630 if (ifp->if_bpf) 1631 bpf_mtap(ifp, m_head); 1632 1633 } 1634 1635 /* Transmit */ 1636 sc->nge_cdata.nge_tx_prod = idx; 1637 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_ENABLE); 1638 1639 /* 1640 * Set a timeout in case the chip goes out to lunch. 1641 */ 1642 ifp->if_timer = 5; 1643 1644 return; 1645} 1646 1647static void nge_init(xsc) 1648 void *xsc; 1649{ 1650 struct nge_softc *sc = xsc; 1651 struct ifnet *ifp = &sc->arpcom.ac_if; 1652 struct mii_data *mii; 1653 int s; 1654 1655 if (ifp->if_flags & IFF_RUNNING) 1656 return; 1657 1658 s = splimp(); 1659 1660 /* 1661 * Cancel pending I/O and free all RX/TX buffers. 1662 */ 1663 nge_stop(sc); 1664 1665 mii = device_get_softc(sc->nge_miibus); 1666 1667 /* Set MAC address */ 1668 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0); 1669 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1670 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1671 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR1); 1672 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1673 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1674 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR2); 1675 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1676 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1677 1678 /* Init circular RX list. */ 1679 if (nge_list_rx_init(sc) == ENOBUFS) { 1680 printf("nge%d: initialization failed: no " 1681 "memory for rx buffers\n", sc->nge_unit); 1682 nge_stop(sc); 1683 (void)splx(s); 1684 return; 1685 } 1686 1687 /* 1688 * Init tx descriptors. 1689 */ 1690 nge_list_tx_init(sc); 1691 1692 /* 1693 * For the NatSemi chip, we have to explicitly enable the 1694 * reception of ARP frames, as well as turn on the 'perfect 1695 * match' filter where we store the station address, otherwise 1696 * we won't receive unicasts meant for this host. 1697 */ 1698 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ARP); 1699 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_PERFECT); 1700 1701 /* If we want promiscuous mode, set the allframes bit. */ 1702 if (ifp->if_flags & IFF_PROMISC) { 1703 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS); 1704 } else { 1705 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS); 1706 } 1707 1708 /* 1709 * Set the capture broadcast bit to capture broadcast frames. 1710 */ 1711 if (ifp->if_flags & IFF_BROADCAST) { 1712 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD); 1713 } else { 1714 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD); 1715 } 1716 1717 /* 1718 * Load the multicast filter. 1719 */ 1720 nge_setmulti(sc); 1721 1722 /* Turn the receive filter on */ 1723 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ENABLE); 1724 1725 /* 1726 * Load the address of the RX and TX lists. 1727 */ 1728 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 1729 vtophys(&sc->nge_ldata->nge_rx_list[0])); 1730 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 1731 vtophys(&sc->nge_ldata->nge_tx_list[0])); 1732 1733 /* Set RX configuration */ 1734 CSR_WRITE_4(sc, NGE_RX_CFG, NGE_RXCFG); 1735 /* 1736 * Enable hardware checksum validation for all IPv4 1737 * packets, do not reject packets with bad checksums. 1738 */ 1739 CSR_WRITE_4(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_IPCSUM_ENB); 1740 1741#if NVLAN > 0 1742 /* 1743 * If VLAN support is enabled, tell the chip to detect 1744 * and strip VLAN tag info from received frames. The tag 1745 * will be provided in the extsts field in the RX descriptors. 1746 */ 1747 NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL, 1748 NGE_VIPRXCTL_TAG_DETECT_ENB|NGE_VIPRXCTL_TAG_STRIP_ENB); 1749#endif 1750 1751 /* Set TX configuration */ 1752 CSR_WRITE_4(sc, NGE_TX_CFG, NGE_TXCFG); 1753 1754 /* 1755 * Enable TX IPv4 checksumming on a per-packet basis. 1756 */ 1757 CSR_WRITE_4(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_CSUM_PER_PKT); 1758 1759#if NVLAN > 0 1760 /* 1761 * If VLAN support is enabled, tell the chip to insert 1762 * VLAN tags on a per-packet basis as dictated by the 1763 * code in the frame encapsulation routine. 1764 */ 1765 NGE_SETBIT(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_TAG_PER_PKT); 1766#endif 1767 1768 /* Set full/half duplex mode. */ 1769 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1770 NGE_SETBIT(sc, NGE_TX_CFG, 1771 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1772 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1773 } else { 1774 NGE_CLRBIT(sc, NGE_TX_CFG, 1775 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1776 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1777 } 1778 1779 /* 1780 * Enable the delivery of PHY interrupts based on 1781 * link/speed/duplex status changes. Also enable the 1782 * extsts field in the DMA descriptors (needed for 1783 * TCP/IP checksum offload on transmit). 1784 */ 1785 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_PHYINTR_SPD| 1786 NGE_CFG_PHYINTR_LNK|NGE_CFG_PHYINTR_DUP|NGE_CFG_EXTSTS_ENB); 1787 1788 /* 1789 * Enable interrupts. 1790 */ 1791 CSR_WRITE_4(sc, NGE_IMR, NGE_INTRS); 1792 CSR_WRITE_4(sc, NGE_IER, 1); 1793 1794 /* Enable receiver and transmitter. */ 1795 NGE_CLRBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE); 1796 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1797 1798 nge_ifmedia_upd(ifp); 1799 1800 ifp->if_flags |= IFF_RUNNING; 1801 ifp->if_flags &= ~IFF_OACTIVE; 1802 1803 (void)splx(s); 1804 1805 return; 1806} 1807 1808/* 1809 * Set media options. 1810 */ 1811static int nge_ifmedia_upd(ifp) 1812 struct ifnet *ifp; 1813{ 1814 struct nge_softc *sc; 1815 struct mii_data *mii; 1816 1817 sc = ifp->if_softc; 1818 1819 mii = device_get_softc(sc->nge_miibus); 1820 sc->nge_link = 0; 1821 if (mii->mii_instance) { 1822 struct mii_softc *miisc; 1823 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1824 miisc = LIST_NEXT(miisc, mii_list)) 1825 mii_phy_reset(miisc); 1826 } 1827 mii_mediachg(mii); 1828 1829 return(0); 1830} 1831 1832/* 1833 * Report current media status. 1834 */ 1835static void nge_ifmedia_sts(ifp, ifmr) 1836 struct ifnet *ifp; 1837 struct ifmediareq *ifmr; 1838{ 1839 struct nge_softc *sc; 1840 struct mii_data *mii; 1841 1842 sc = ifp->if_softc; 1843 1844 mii = device_get_softc(sc->nge_miibus); 1845 mii_pollstat(mii); 1846 ifmr->ifm_active = mii->mii_media_active; 1847 ifmr->ifm_status = mii->mii_media_status; 1848 1849 return; 1850} 1851 1852static int nge_ioctl(ifp, command, data) 1853 struct ifnet *ifp; 1854 u_long command; 1855 caddr_t data; 1856{ 1857 struct nge_softc *sc = ifp->if_softc; 1858 struct ifreq *ifr = (struct ifreq *) data; 1859 struct mii_data *mii; 1860 int s, error = 0; 1861 1862 s = splimp(); 1863 1864 switch(command) { 1865 case SIOCSIFADDR: 1866 case SIOCGIFADDR: 1867 error = ether_ioctl(ifp, command, data); 1868 break; 1869 case SIOCSIFMTU: 1870 if (ifr->ifr_mtu > NGE_JUMBO_MTU) 1871 error = EINVAL; 1872 else { 1873 ifp->if_mtu = ifr->ifr_mtu; 1874 /* 1875 * Workaround: if the MTU is larger than 1876 * 8152 (TX FIFO size minus 64 minus 18), turn off 1877 * TX checksum offloading. 1878 */ 1879 if (ifr->ifr_mtu >= 8152) 1880 ifp->if_hwassist = 0; 1881 else 1882 ifp->if_hwassist = NGE_CSUM_FEATURES; 1883 } 1884 break; 1885 case SIOCSIFFLAGS: 1886 if (ifp->if_flags & IFF_UP) { 1887 if (ifp->if_flags & IFF_RUNNING && 1888 ifp->if_flags & IFF_PROMISC && 1889 !(sc->nge_if_flags & IFF_PROMISC)) { 1890 NGE_SETBIT(sc, NGE_RXFILT_CTL, 1891 NGE_RXFILTCTL_ALLPHYS| 1892 NGE_RXFILTCTL_ALLMULTI); 1893 } else if (ifp->if_flags & IFF_RUNNING && 1894 !(ifp->if_flags & IFF_PROMISC) && 1895 sc->nge_if_flags & IFF_PROMISC) { 1896 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 1897 NGE_RXFILTCTL_ALLPHYS); 1898 if (!(ifp->if_flags & IFF_ALLMULTI)) 1899 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 1900 NGE_RXFILTCTL_ALLMULTI); 1901 } else { 1902 ifp->if_flags &= ~IFF_RUNNING; 1903 nge_init(sc); 1904 } 1905 } else { 1906 if (ifp->if_flags & IFF_RUNNING) 1907 nge_stop(sc); 1908 } 1909 sc->nge_if_flags = ifp->if_flags; 1910 error = 0; 1911 break; 1912 case SIOCADDMULTI: 1913 case SIOCDELMULTI: 1914 nge_setmulti(sc); 1915 error = 0; 1916 break; 1917 case SIOCGIFMEDIA: 1918 case SIOCSIFMEDIA: 1919 mii = device_get_softc(sc->nge_miibus); 1920 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1921 break; 1922 default: 1923 error = EINVAL; 1924 break; 1925 } 1926 1927 (void)splx(s); 1928 1929 return(error); 1930} 1931 1932static void nge_watchdog(ifp) 1933 struct ifnet *ifp; 1934{ 1935 struct nge_softc *sc; 1936 1937 sc = ifp->if_softc; 1938 1939 ifp->if_oerrors++; 1940 printf("nge%d: watchdog timeout\n", sc->nge_unit); 1941 1942 nge_stop(sc); 1943 nge_reset(sc); 1944 ifp->if_flags &= ~IFF_RUNNING; 1945 nge_init(sc); 1946 1947 if (ifp->if_snd.ifq_head != NULL) 1948 nge_start(ifp); 1949 1950 return; 1951} 1952 1953/* 1954 * Stop the adapter and free any mbufs allocated to the 1955 * RX and TX lists. 1956 */ 1957static void nge_stop(sc) 1958 struct nge_softc *sc; 1959{ 1960 register int i; 1961 struct ifnet *ifp; 1962 struct ifmedia_entry *ifm; 1963 struct mii_data *mii; 1964 int mtmp, itmp; 1965 1966 ifp = &sc->arpcom.ac_if; 1967 ifp->if_timer = 0; 1968 mii = device_get_softc(sc->nge_miibus); 1969 1970 untimeout(nge_tick, sc, sc->nge_stat_ch); 1971 CSR_WRITE_4(sc, NGE_IER, 0); 1972 CSR_WRITE_4(sc, NGE_IMR, 0); 1973 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE); 1974 DELAY(1000); 1975 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 0); 1976 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 0); 1977 1978 /* 1979 * Isolate/power down the PHY, but leave the media selection 1980 * unchanged so that things will be put back to normal when 1981 * we bring the interface back up. 1982 */ 1983 itmp = ifp->if_flags; 1984 ifp->if_flags |= IFF_UP; 1985 ifm = mii->mii_media.ifm_cur; 1986 mtmp = ifm->ifm_media; 1987 ifm->ifm_media = IFM_ETHER|IFM_NONE; 1988 mii_mediachg(mii); 1989 ifm->ifm_media = mtmp; 1990 ifp->if_flags = itmp; 1991 1992 sc->nge_link = 0; 1993 1994 /* 1995 * Free data in the RX lists. 1996 */ 1997 for (i = 0; i < NGE_RX_LIST_CNT; i++) { 1998 if (sc->nge_ldata->nge_rx_list[i].nge_mbuf != NULL) { 1999 m_freem(sc->nge_ldata->nge_rx_list[i].nge_mbuf); 2000 sc->nge_ldata->nge_rx_list[i].nge_mbuf = NULL; 2001 } 2002 } 2003 bzero((char *)&sc->nge_ldata->nge_rx_list, 2004 sizeof(sc->nge_ldata->nge_rx_list)); 2005 2006 /* 2007 * Free the TX list buffers. 2008 */ 2009 for (i = 0; i < NGE_TX_LIST_CNT; i++) { 2010 if (sc->nge_ldata->nge_tx_list[i].nge_mbuf != NULL) { 2011 m_freem(sc->nge_ldata->nge_tx_list[i].nge_mbuf); 2012 sc->nge_ldata->nge_tx_list[i].nge_mbuf = NULL; 2013 } 2014 } 2015 2016 bzero((char *)&sc->nge_ldata->nge_tx_list, 2017 sizeof(sc->nge_ldata->nge_tx_list)); 2018 2019 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2020 2021 return; 2022} 2023 2024/* 2025 * Stop all chip I/O so that the kernel's probe routines don't 2026 * get confused by errant DMAs when rebooting. 2027 */ 2028static void nge_shutdown(dev) 2029 device_t dev; 2030{ 2031 struct nge_softc *sc; 2032 2033 sc = device_get_softc(dev); 2034 2035 nge_reset(sc); 2036 nge_stop(sc); 2037 2038 return; 2039} 2040