if_nge.c revision 78323
1/* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2000, 2001 4 * Bill Paul <wpaul@bsdi.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: head/sys/dev/nge/if_nge.c 78323 2001-06-16 03:38:44Z wpaul $ 34 */ 35 36/* 37 * National Semiconductor DP83820/DP83821 gigabit ethernet driver 38 * for FreeBSD. Datasheets are available from: 39 * 40 * http://www.national.com/ds/DP/DP83820.pdf 41 * http://www.national.com/ds/DP/DP83821.pdf 42 * 43 * These chips are used on several low cost gigabit ethernet NICs 44 * sold by D-Link, Addtron, SMC and Asante. Both parts are 45 * virtually the same, except the 83820 is a 64-bit/32-bit part, 46 * while the 83821 is 32-bit only. 47 * 48 * Many cards also use National gigE transceivers, such as the 49 * DP83891, DP83861 and DP83862 gigPHYTER parts. The DP83861 datasheet 50 * contains a full register description that applies to all of these 51 * components: 52 * 53 * http://www.national.com/ds/DP/DP83861.pdf 54 * 55 * Written by Bill Paul <wpaul@bsdi.com> 56 * BSDi Open Source Solutions 57 */ 58 59/* 60 * The NatSemi DP83820 and 83821 controllers are enhanced versions 61 * of the NatSemi MacPHYTER 10/100 devices. They support 10, 100 62 * and 1000Mbps speeds with 1000baseX (ten bit interface), MII and GMII 63 * ports. Other features include 8K TX FIFO and 32K RX FIFO, TCP/IP 64 * hardware checksum offload (IPv4 only), VLAN tagging and filtering, 65 * priority TX and RX queues, a 2048 bit multicast hash filter, 4 RX pattern 66 * matching buffers, one perfect address filter buffer and interrupt 67 * moderation. The 83820 supports both 64-bit and 32-bit addressing 68 * and data transfers: the 64-bit support can be toggled on or off 69 * via software. This affects the size of certain fields in the DMA 70 * descriptors. 71 * 72 * There are two bugs/misfeatures in the 83820/83821 that I have 73 * discovered so far: 74 * 75 * - Receive buffers must be aligned on 64-bit boundaries, which means 76 * you must resort to copying data in order to fix up the payload 77 * alignment. 78 * 79 * - In order to transmit jumbo frames larger than 8170 bytes, you have 80 * to turn off transmit checksum offloading, because the chip can't 81 * compute the checksum on an outgoing frame unless it fits entirely 82 * within the TX FIFO, which is only 8192 bytes in size. If you have 83 * TX checksum offload enabled and you transmit attempt to transmit a 84 * frame larger than 8170 bytes, the transmitter will wedge. 85 * 86 * To work around the latter problem, TX checksum offload is disabled 87 * if the user selects an MTU larger than 8152 (8170 - 18). 88 */ 89 90#include "vlan.h" 91 92#include <sys/param.h> 93#include <sys/systm.h> 94#include <sys/sockio.h> 95#include <sys/mbuf.h> 96#include <sys/malloc.h> 97#include <sys/kernel.h> 98#include <sys/socket.h> 99 100#include <net/if.h> 101#include <net/if_arp.h> 102#include <net/ethernet.h> 103#include <net/if_dl.h> 104#include <net/if_media.h> 105 106#if NVLAN > 0 107#include <net/if_types.h> 108#include <net/if_vlan_var.h> 109#endif 110 111#include <net/bpf.h> 112 113#include <vm/vm.h> /* for vtophys */ 114#include <vm/pmap.h> /* for vtophys */ 115#include <machine/clock.h> /* for DELAY */ 116#include <machine/bus_pio.h> 117#include <machine/bus_memio.h> 118#include <machine/bus.h> 119#include <machine/resource.h> 120#include <sys/bus.h> 121#include <sys/rman.h> 122 123#include <dev/mii/mii.h> 124#include <dev/mii/miivar.h> 125 126#include <pci/pcireg.h> 127#include <pci/pcivar.h> 128 129#define NGE_USEIOSPACE 130 131#include <dev/nge/if_ngereg.h> 132 133MODULE_DEPEND(nge, miibus, 1, 1, 1); 134 135/* "controller miibus0" required. See GENERIC if you get errors here. */ 136#include "miibus_if.h" 137 138#ifndef lint 139static const char rcsid[] = 140 "$FreeBSD: head/sys/dev/nge/if_nge.c 78323 2001-06-16 03:38:44Z wpaul $"; 141#endif 142 143#define NGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 144 145/* 146 * Various supported device vendors/types and their names. 147 */ 148static struct nge_type nge_devs[] = { 149 { NGE_VENDORID, NGE_DEVICEID, 150 "National Semiconductor Gigabit Ethernet" }, 151 { 0, 0, NULL } 152}; 153 154static int nge_probe __P((device_t)); 155static int nge_attach __P((device_t)); 156static int nge_detach __P((device_t)); 157 158static int nge_alloc_jumbo_mem __P((struct nge_softc *)); 159static void nge_free_jumbo_mem __P((struct nge_softc *)); 160static void *nge_jalloc __P((struct nge_softc *)); 161static void nge_jfree __P((caddr_t, void *)); 162 163static int nge_newbuf __P((struct nge_softc *, 164 struct nge_desc *, 165 struct mbuf *)); 166static int nge_encap __P((struct nge_softc *, 167 struct mbuf *, u_int32_t *)); 168static void nge_rxeof __P((struct nge_softc *)); 169static void nge_rxeoc __P((struct nge_softc *)); 170static void nge_txeof __P((struct nge_softc *)); 171static void nge_intr __P((void *)); 172static void nge_tick __P((void *)); 173static void nge_start __P((struct ifnet *)); 174static int nge_ioctl __P((struct ifnet *, u_long, caddr_t)); 175static void nge_init __P((void *)); 176static void nge_stop __P((struct nge_softc *)); 177static void nge_watchdog __P((struct ifnet *)); 178static void nge_shutdown __P((device_t)); 179static int nge_ifmedia_upd __P((struct ifnet *)); 180static void nge_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 181 182static void nge_delay __P((struct nge_softc *)); 183static void nge_eeprom_idle __P((struct nge_softc *)); 184static void nge_eeprom_putbyte __P((struct nge_softc *, int)); 185static void nge_eeprom_getword __P((struct nge_softc *, int, u_int16_t *)); 186static void nge_read_eeprom __P((struct nge_softc *, caddr_t, int, 187 int, int)); 188 189static void nge_mii_sync __P((struct nge_softc *)); 190static void nge_mii_send __P((struct nge_softc *, u_int32_t, int)); 191static int nge_mii_readreg __P((struct nge_softc *, 192 struct nge_mii_frame *)); 193static int nge_mii_writereg __P((struct nge_softc *, 194 struct nge_mii_frame *)); 195 196static int nge_miibus_readreg __P((device_t, int, int)); 197static int nge_miibus_writereg __P((device_t, int, int, int)); 198static void nge_miibus_statchg __P((device_t)); 199 200static void nge_setmulti __P((struct nge_softc *)); 201static u_int32_t nge_crc __P((struct nge_softc *, caddr_t)); 202static void nge_reset __P((struct nge_softc *)); 203static int nge_list_rx_init __P((struct nge_softc *)); 204static int nge_list_tx_init __P((struct nge_softc *)); 205 206#ifdef NGE_USEIOSPACE 207#define NGE_RES SYS_RES_IOPORT 208#define NGE_RID NGE_PCI_LOIO 209#else 210#define NGE_RES SYS_RES_MEMORY 211#define NGE_RID NGE_PCI_LOMEM 212#endif 213 214static device_method_t nge_methods[] = { 215 /* Device interface */ 216 DEVMETHOD(device_probe, nge_probe), 217 DEVMETHOD(device_attach, nge_attach), 218 DEVMETHOD(device_detach, nge_detach), 219 DEVMETHOD(device_shutdown, nge_shutdown), 220 221 /* bus interface */ 222 DEVMETHOD(bus_print_child, bus_generic_print_child), 223 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 224 225 /* MII interface */ 226 DEVMETHOD(miibus_readreg, nge_miibus_readreg), 227 DEVMETHOD(miibus_writereg, nge_miibus_writereg), 228 DEVMETHOD(miibus_statchg, nge_miibus_statchg), 229 230 { 0, 0 } 231}; 232 233static driver_t nge_driver = { 234 "nge", 235 nge_methods, 236 sizeof(struct nge_softc) 237}; 238 239static devclass_t nge_devclass; 240 241DRIVER_MODULE(if_nge, pci, nge_driver, nge_devclass, 0, 0); 242DRIVER_MODULE(miibus, nge, miibus_driver, miibus_devclass, 0, 0); 243 244#define NGE_SETBIT(sc, reg, x) \ 245 CSR_WRITE_4(sc, reg, \ 246 CSR_READ_4(sc, reg) | (x)) 247 248#define NGE_CLRBIT(sc, reg, x) \ 249 CSR_WRITE_4(sc, reg, \ 250 CSR_READ_4(sc, reg) & ~(x)) 251 252#define SIO_SET(x) \ 253 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | x) 254 255#define SIO_CLR(x) \ 256 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~x) 257 258static void nge_delay(sc) 259 struct nge_softc *sc; 260{ 261 int idx; 262 263 for (idx = (300 / 33) + 1; idx > 0; idx--) 264 CSR_READ_4(sc, NGE_CSR); 265 266 return; 267} 268 269static void nge_eeprom_idle(sc) 270 struct nge_softc *sc; 271{ 272 register int i; 273 274 SIO_SET(NGE_MEAR_EE_CSEL); 275 nge_delay(sc); 276 SIO_SET(NGE_MEAR_EE_CLK); 277 nge_delay(sc); 278 279 for (i = 0; i < 25; i++) { 280 SIO_CLR(NGE_MEAR_EE_CLK); 281 nge_delay(sc); 282 SIO_SET(NGE_MEAR_EE_CLK); 283 nge_delay(sc); 284 } 285 286 SIO_CLR(NGE_MEAR_EE_CLK); 287 nge_delay(sc); 288 SIO_CLR(NGE_MEAR_EE_CSEL); 289 nge_delay(sc); 290 CSR_WRITE_4(sc, NGE_MEAR, 0x00000000); 291 292 return; 293} 294 295/* 296 * Send a read command and address to the EEPROM, check for ACK. 297 */ 298static void nge_eeprom_putbyte(sc, addr) 299 struct nge_softc *sc; 300 int addr; 301{ 302 register int d, i; 303 304 d = addr | NGE_EECMD_READ; 305 306 /* 307 * Feed in each bit and stobe the clock. 308 */ 309 for (i = 0x400; i; i >>= 1) { 310 if (d & i) { 311 SIO_SET(NGE_MEAR_EE_DIN); 312 } else { 313 SIO_CLR(NGE_MEAR_EE_DIN); 314 } 315 nge_delay(sc); 316 SIO_SET(NGE_MEAR_EE_CLK); 317 nge_delay(sc); 318 SIO_CLR(NGE_MEAR_EE_CLK); 319 nge_delay(sc); 320 } 321 322 return; 323} 324 325/* 326 * Read a word of data stored in the EEPROM at address 'addr.' 327 */ 328static void nge_eeprom_getword(sc, addr, dest) 329 struct nge_softc *sc; 330 int addr; 331 u_int16_t *dest; 332{ 333 register int i; 334 u_int16_t word = 0; 335 336 /* Force EEPROM to idle state. */ 337 nge_eeprom_idle(sc); 338 339 /* Enter EEPROM access mode. */ 340 nge_delay(sc); 341 SIO_CLR(NGE_MEAR_EE_CLK); 342 nge_delay(sc); 343 SIO_SET(NGE_MEAR_EE_CSEL); 344 nge_delay(sc); 345 346 /* 347 * Send address of word we want to read. 348 */ 349 nge_eeprom_putbyte(sc, addr); 350 351 /* 352 * Start reading bits from EEPROM. 353 */ 354 for (i = 0x8000; i; i >>= 1) { 355 SIO_SET(NGE_MEAR_EE_CLK); 356 nge_delay(sc); 357 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT) 358 word |= i; 359 nge_delay(sc); 360 SIO_CLR(NGE_MEAR_EE_CLK); 361 nge_delay(sc); 362 } 363 364 /* Turn off EEPROM access mode. */ 365 nge_eeprom_idle(sc); 366 367 *dest = word; 368 369 return; 370} 371 372/* 373 * Read a sequence of words from the EEPROM. 374 */ 375static void nge_read_eeprom(sc, dest, off, cnt, swap) 376 struct nge_softc *sc; 377 caddr_t dest; 378 int off; 379 int cnt; 380 int swap; 381{ 382 int i; 383 u_int16_t word = 0, *ptr; 384 385 for (i = 0; i < cnt; i++) { 386 nge_eeprom_getword(sc, off + i, &word); 387 ptr = (u_int16_t *)(dest + (i * 2)); 388 if (swap) 389 *ptr = ntohs(word); 390 else 391 *ptr = word; 392 } 393 394 return; 395} 396 397/* 398 * Sync the PHYs by setting data bit and strobing the clock 32 times. 399 */ 400static void nge_mii_sync(sc) 401 struct nge_softc *sc; 402{ 403 register int i; 404 405 SIO_SET(NGE_MEAR_MII_DIR|NGE_MEAR_MII_DATA); 406 407 for (i = 0; i < 32; i++) { 408 SIO_SET(NGE_MEAR_MII_CLK); 409 DELAY(1); 410 SIO_CLR(NGE_MEAR_MII_CLK); 411 DELAY(1); 412 } 413 414 return; 415} 416 417/* 418 * Clock a series of bits through the MII. 419 */ 420static void nge_mii_send(sc, bits, cnt) 421 struct nge_softc *sc; 422 u_int32_t bits; 423 int cnt; 424{ 425 int i; 426 427 SIO_CLR(NGE_MEAR_MII_CLK); 428 429 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 430 if (bits & i) { 431 SIO_SET(NGE_MEAR_MII_DATA); 432 } else { 433 SIO_CLR(NGE_MEAR_MII_DATA); 434 } 435 DELAY(1); 436 SIO_CLR(NGE_MEAR_MII_CLK); 437 DELAY(1); 438 SIO_SET(NGE_MEAR_MII_CLK); 439 } 440} 441 442/* 443 * Read an PHY register through the MII. 444 */ 445static int nge_mii_readreg(sc, frame) 446 struct nge_softc *sc; 447 struct nge_mii_frame *frame; 448 449{ 450 int i, ack, s; 451 452 s = splimp(); 453 454 /* 455 * Set up frame for RX. 456 */ 457 frame->mii_stdelim = NGE_MII_STARTDELIM; 458 frame->mii_opcode = NGE_MII_READOP; 459 frame->mii_turnaround = 0; 460 frame->mii_data = 0; 461 462 CSR_WRITE_4(sc, NGE_MEAR, 0); 463 464 /* 465 * Turn on data xmit. 466 */ 467 SIO_SET(NGE_MEAR_MII_DIR); 468 469 nge_mii_sync(sc); 470 471 /* 472 * Send command/address info. 473 */ 474 nge_mii_send(sc, frame->mii_stdelim, 2); 475 nge_mii_send(sc, frame->mii_opcode, 2); 476 nge_mii_send(sc, frame->mii_phyaddr, 5); 477 nge_mii_send(sc, frame->mii_regaddr, 5); 478 479 /* Idle bit */ 480 SIO_CLR((NGE_MEAR_MII_CLK|NGE_MEAR_MII_DATA)); 481 DELAY(1); 482 SIO_SET(NGE_MEAR_MII_CLK); 483 DELAY(1); 484 485 /* Turn off xmit. */ 486 SIO_CLR(NGE_MEAR_MII_DIR); 487 /* Check for ack */ 488 SIO_CLR(NGE_MEAR_MII_CLK); 489 DELAY(1); 490 SIO_SET(NGE_MEAR_MII_CLK); 491 DELAY(1); 492 ack = CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA; 493 494 /* 495 * Now try reading data bits. If the ack failed, we still 496 * need to clock through 16 cycles to keep the PHY(s) in sync. 497 */ 498 if (ack) { 499 for(i = 0; i < 16; i++) { 500 SIO_CLR(NGE_MEAR_MII_CLK); 501 DELAY(1); 502 SIO_SET(NGE_MEAR_MII_CLK); 503 DELAY(1); 504 } 505 goto fail; 506 } 507 508 for (i = 0x8000; i; i >>= 1) { 509 SIO_CLR(NGE_MEAR_MII_CLK); 510 DELAY(1); 511 if (!ack) { 512 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA) 513 frame->mii_data |= i; 514 DELAY(1); 515 } 516 SIO_SET(NGE_MEAR_MII_CLK); 517 DELAY(1); 518 } 519 520fail: 521 522 SIO_CLR(NGE_MEAR_MII_CLK); 523 DELAY(1); 524 SIO_SET(NGE_MEAR_MII_CLK); 525 DELAY(1); 526 527 splx(s); 528 529 if (ack) 530 return(1); 531 return(0); 532} 533 534/* 535 * Write to a PHY register through the MII. 536 */ 537static int nge_mii_writereg(sc, frame) 538 struct nge_softc *sc; 539 struct nge_mii_frame *frame; 540 541{ 542 int s; 543 544 s = splimp(); 545 /* 546 * Set up frame for TX. 547 */ 548 549 frame->mii_stdelim = NGE_MII_STARTDELIM; 550 frame->mii_opcode = NGE_MII_WRITEOP; 551 frame->mii_turnaround = NGE_MII_TURNAROUND; 552 553 /* 554 * Turn on data output. 555 */ 556 SIO_SET(NGE_MEAR_MII_DIR); 557 558 nge_mii_sync(sc); 559 560 nge_mii_send(sc, frame->mii_stdelim, 2); 561 nge_mii_send(sc, frame->mii_opcode, 2); 562 nge_mii_send(sc, frame->mii_phyaddr, 5); 563 nge_mii_send(sc, frame->mii_regaddr, 5); 564 nge_mii_send(sc, frame->mii_turnaround, 2); 565 nge_mii_send(sc, frame->mii_data, 16); 566 567 /* Idle bit. */ 568 SIO_SET(NGE_MEAR_MII_CLK); 569 DELAY(1); 570 SIO_CLR(NGE_MEAR_MII_CLK); 571 DELAY(1); 572 573 /* 574 * Turn off xmit. 575 */ 576 SIO_CLR(NGE_MEAR_MII_DIR); 577 578 splx(s); 579 580 return(0); 581} 582 583static int nge_miibus_readreg(dev, phy, reg) 584 device_t dev; 585 int phy, reg; 586{ 587 struct nge_softc *sc; 588 struct nge_mii_frame frame; 589 590 sc = device_get_softc(dev); 591 592 bzero((char *)&frame, sizeof(frame)); 593 594 frame.mii_phyaddr = phy; 595 frame.mii_regaddr = reg; 596 nge_mii_readreg(sc, &frame); 597 598 return(frame.mii_data); 599} 600 601static int nge_miibus_writereg(dev, phy, reg, data) 602 device_t dev; 603 int phy, reg, data; 604{ 605 struct nge_softc *sc; 606 struct nge_mii_frame frame; 607 608 sc = device_get_softc(dev); 609 610 bzero((char *)&frame, sizeof(frame)); 611 612 frame.mii_phyaddr = phy; 613 frame.mii_regaddr = reg; 614 frame.mii_data = data; 615 nge_mii_writereg(sc, &frame); 616 617 return(0); 618} 619 620static void nge_miibus_statchg(dev) 621 device_t dev; 622{ 623 struct nge_softc *sc; 624 struct mii_data *mii; 625 626 sc = device_get_softc(dev); 627 mii = device_get_softc(sc->nge_miibus); 628 629 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 630 NGE_SETBIT(sc, NGE_TX_CFG, 631 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 632 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 633 } else { 634 NGE_CLRBIT(sc, NGE_TX_CFG, 635 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 636 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 637 } 638 639 return; 640} 641 642static u_int32_t nge_crc(sc, addr) 643 struct nge_softc *sc; 644 caddr_t addr; 645{ 646 u_int32_t crc, carry; 647 int i, j; 648 u_int8_t c; 649 650 /* Compute CRC for the address value. */ 651 crc = 0xFFFFFFFF; /* initial value */ 652 653 for (i = 0; i < 6; i++) { 654 c = *(addr + i); 655 for (j = 0; j < 8; j++) { 656 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 657 crc <<= 1; 658 c >>= 1; 659 if (carry) 660 crc = (crc ^ 0x04c11db6) | carry; 661 } 662 } 663 664 /* 665 * return the filter bit position 666 */ 667 668 return((crc >> 21) & 0x00000FFF); 669} 670 671static void nge_setmulti(sc) 672 struct nge_softc *sc; 673{ 674 struct ifnet *ifp; 675 struct ifmultiaddr *ifma; 676 u_int32_t h = 0, i, filtsave; 677 int bit, index; 678 679 ifp = &sc->arpcom.ac_if; 680 681 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 682 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 683 NGE_RXFILTCTL_MCHASH|NGE_RXFILTCTL_UCHASH); 684 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLMULTI); 685 return; 686 } 687 688 /* 689 * We have to explicitly enable the multicast hash table 690 * on the NatSemi chip if we want to use it, which we do. 691 * We also have to tell it that we don't want to use the 692 * hash table for matching unicast addresses. 693 */ 694 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_MCHASH); 695 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 696 NGE_RXFILTCTL_ALLMULTI|NGE_RXFILTCTL_UCHASH); 697 698 filtsave = CSR_READ_4(sc, NGE_RXFILT_CTL); 699 700 /* first, zot all the existing hash bits */ 701 for (i = 0; i < NGE_MCAST_FILTER_LEN; i += 2) { 702 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + i); 703 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 0); 704 } 705 706 /* 707 * From the 11 bits returned by the crc routine, the top 7 708 * bits represent the 16-bit word in the mcast hash table 709 * that needs to be updated, and the lower 4 bits represent 710 * which bit within that byte needs to be set. 711 */ 712 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 713 if (ifma->ifma_addr->sa_family != AF_LINK) 714 continue; 715 h = nge_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 716 index = (h >> 4) & 0x7F; 717 bit = h & 0xF; 718 CSR_WRITE_4(sc, NGE_RXFILT_CTL, 719 NGE_FILTADDR_MCAST_LO + (index * 2)); 720 NGE_SETBIT(sc, NGE_RXFILT_DATA, (1 << bit)); 721 } 722 723 CSR_WRITE_4(sc, NGE_RXFILT_CTL, filtsave); 724 725 return; 726} 727 728static void nge_reset(sc) 729 struct nge_softc *sc; 730{ 731 register int i; 732 733 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RESET); 734 735 for (i = 0; i < NGE_TIMEOUT; i++) { 736 if (!(CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET)) 737 break; 738 } 739 740 if (i == NGE_TIMEOUT) 741 printf("nge%d: reset never completed\n", sc->nge_unit); 742 743 /* Wait a little while for the chip to get its brains in order. */ 744 DELAY(1000); 745 746 /* 747 * If this is a NetSemi chip, make sure to clear 748 * PME mode. 749 */ 750 CSR_WRITE_4(sc, NGE_CLKRUN, NGE_CLKRUN_PMESTS); 751 CSR_WRITE_4(sc, NGE_CLKRUN, 0); 752 753 return; 754} 755 756/* 757 * Probe for an NatSemi chip. Check the PCI vendor and device 758 * IDs against our list and return a device name if we find a match. 759 */ 760static int nge_probe(dev) 761 device_t dev; 762{ 763 struct nge_type *t; 764 765 t = nge_devs; 766 767 while(t->nge_name != NULL) { 768 if ((pci_get_vendor(dev) == t->nge_vid) && 769 (pci_get_device(dev) == t->nge_did)) { 770 device_set_desc(dev, t->nge_name); 771 return(0); 772 } 773 t++; 774 } 775 776 return(ENXIO); 777} 778 779/* 780 * Attach the interface. Allocate softc structures, do ifmedia 781 * setup and ethernet/BPF attach. 782 */ 783static int nge_attach(dev) 784 device_t dev; 785{ 786 int s; 787 u_char eaddr[ETHER_ADDR_LEN]; 788 u_int32_t command; 789 struct nge_softc *sc; 790 struct ifnet *ifp; 791 int unit, error = 0, rid; 792 793 s = splimp(); 794 795 sc = device_get_softc(dev); 796 unit = device_get_unit(dev); 797 bzero(sc, sizeof(struct nge_softc)); 798 799 mtx_init(&sc->nge_mtx, device_get_nameunit(dev), MTX_DEF|MTX_RECURSE); 800 801 /* 802 * Handle power management nonsense. 803 */ 804 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 805 u_int32_t iobase, membase, irq; 806 807 /* Save important PCI config data. */ 808 iobase = pci_read_config(dev, NGE_PCI_LOIO, 4); 809 membase = pci_read_config(dev, NGE_PCI_LOMEM, 4); 810 irq = pci_read_config(dev, NGE_PCI_INTLINE, 4); 811 812 /* Reset the power state. */ 813 printf("nge%d: chip is in D%d power mode " 814 "-- setting to D0\n", unit, 815 pci_get_powerstate(dev)); 816 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 817 818 /* Restore PCI config data. */ 819 pci_write_config(dev, NGE_PCI_LOIO, iobase, 4); 820 pci_write_config(dev, NGE_PCI_LOMEM, membase, 4); 821 pci_write_config(dev, NGE_PCI_INTLINE, irq, 4); 822 } 823 824 /* 825 * Map control/status registers. 826 */ 827 pci_enable_busmaster(dev); 828 pci_enable_io(dev, PCIM_CMD_PORTEN); 829 pci_enable_io(dev, PCIM_CMD_MEMEN); 830 command = pci_read_config(dev, PCIR_COMMAND, 4); 831 832#ifdef NGE_USEIOSPACE 833 if (!(command & PCIM_CMD_PORTEN)) { 834 printf("nge%d: failed to enable I/O ports!\n", unit); 835 error = ENXIO;; 836 goto fail; 837 } 838#else 839 if (!(command & PCIM_CMD_MEMEN)) { 840 printf("nge%d: failed to enable memory mapping!\n", unit); 841 error = ENXIO;; 842 goto fail; 843 } 844#endif 845 846 rid = NGE_RID; 847 sc->nge_res = bus_alloc_resource(dev, NGE_RES, &rid, 848 0, ~0, 1, RF_ACTIVE); 849 850 if (sc->nge_res == NULL) { 851 printf("nge%d: couldn't map ports/memory\n", unit); 852 error = ENXIO; 853 goto fail; 854 } 855 856 sc->nge_btag = rman_get_bustag(sc->nge_res); 857 sc->nge_bhandle = rman_get_bushandle(sc->nge_res); 858 859 /* Allocate interrupt */ 860 rid = 0; 861 sc->nge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 862 RF_SHAREABLE | RF_ACTIVE); 863 864 if (sc->nge_irq == NULL) { 865 printf("nge%d: couldn't map interrupt\n", unit); 866 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 867 error = ENXIO; 868 goto fail; 869 } 870 871 error = bus_setup_intr(dev, sc->nge_irq, INTR_TYPE_NET, 872 nge_intr, sc, &sc->nge_intrhand); 873 874 if (error) { 875 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 876 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 877 printf("nge%d: couldn't set up irq\n", unit); 878 goto fail; 879 } 880 881 /* Reset the adapter. */ 882 nge_reset(sc); 883 884 /* 885 * Get station address from the EEPROM. 886 */ 887 nge_read_eeprom(sc, (caddr_t)&eaddr[4], NGE_EE_NODEADDR, 1, 0); 888 nge_read_eeprom(sc, (caddr_t)&eaddr[2], NGE_EE_NODEADDR + 1, 1, 0); 889 nge_read_eeprom(sc, (caddr_t)&eaddr[0], NGE_EE_NODEADDR + 2, 1, 0); 890 891 /* 892 * A NatSemi chip was detected. Inform the world. 893 */ 894 printf("nge%d: Ethernet address: %6D\n", unit, eaddr, ":"); 895 896 sc->nge_unit = unit; 897 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 898 899 sc->nge_ldata = contigmalloc(sizeof(struct nge_list_data), M_DEVBUF, 900 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 901 902 if (sc->nge_ldata == NULL) { 903 printf("nge%d: no memory for list buffers!\n", unit); 904 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 905 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 906 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 907 error = ENXIO; 908 goto fail; 909 } 910 bzero(sc->nge_ldata, sizeof(struct nge_list_data)); 911 912 /* Try to allocate memory for jumbo buffers. */ 913 if (nge_alloc_jumbo_mem(sc)) { 914 printf("nge%d: jumbo buffer allocation failed\n", 915 sc->nge_unit); 916 contigfree(sc->nge_ldata, 917 sizeof(struct nge_list_data), M_DEVBUF); 918 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 919 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 920 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 921 error = ENXIO; 922 goto fail; 923 } 924 925 ifp = &sc->arpcom.ac_if; 926 ifp->if_softc = sc; 927 ifp->if_unit = unit; 928 ifp->if_name = "nge"; 929 ifp->if_mtu = ETHERMTU; 930 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 931 ifp->if_ioctl = nge_ioctl; 932 ifp->if_output = ether_output; 933 ifp->if_start = nge_start; 934 ifp->if_watchdog = nge_watchdog; 935 ifp->if_init = nge_init; 936 ifp->if_baudrate = 1000000000; 937 ifp->if_snd.ifq_maxlen = NGE_TX_LIST_CNT - 1; 938 ifp->if_hwassist = NGE_CSUM_FEATURES; 939 940 /* 941 * Do MII setup. 942 */ 943 if (mii_phy_probe(dev, &sc->nge_miibus, 944 nge_ifmedia_upd, nge_ifmedia_sts)) { 945 printf("nge%d: MII without any PHY!\n", sc->nge_unit); 946 nge_free_jumbo_mem(sc); 947 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 948 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 949 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 950 error = ENXIO; 951 goto fail; 952 } 953 954 /* 955 * Call MI attach routine. 956 */ 957 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 958 callout_handle_init(&sc->nge_stat_ch); 959 960fail: 961 splx(s); 962 mtx_destroy(&sc->nge_mtx); 963 return(error); 964} 965 966static int nge_detach(dev) 967 device_t dev; 968{ 969 struct nge_softc *sc; 970 struct ifnet *ifp; 971 int s; 972 973 s = splimp(); 974 975 sc = device_get_softc(dev); 976 ifp = &sc->arpcom.ac_if; 977 978 nge_reset(sc); 979 nge_stop(sc); 980 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 981 982 bus_generic_detach(dev); 983 device_delete_child(dev, sc->nge_miibus); 984 985 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 986 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 987 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 988 989 contigfree(sc->nge_ldata, sizeof(struct nge_list_data), M_DEVBUF); 990 nge_free_jumbo_mem(sc); 991 992 splx(s); 993 mtx_destroy(&sc->nge_mtx); 994 995 return(0); 996} 997 998/* 999 * Initialize the transmit descriptors. 1000 */ 1001static int nge_list_tx_init(sc) 1002 struct nge_softc *sc; 1003{ 1004 struct nge_list_data *ld; 1005 struct nge_ring_data *cd; 1006 int i; 1007 1008 cd = &sc->nge_cdata; 1009 ld = sc->nge_ldata; 1010 1011 for (i = 0; i < NGE_TX_LIST_CNT; i++) { 1012 if (i == (NGE_TX_LIST_CNT - 1)) { 1013 ld->nge_tx_list[i].nge_nextdesc = 1014 &ld->nge_tx_list[0]; 1015 ld->nge_tx_list[i].nge_next = 1016 vtophys(&ld->nge_tx_list[0]); 1017 } else { 1018 ld->nge_tx_list[i].nge_nextdesc = 1019 &ld->nge_tx_list[i + 1]; 1020 ld->nge_tx_list[i].nge_next = 1021 vtophys(&ld->nge_tx_list[i + 1]); 1022 } 1023 ld->nge_tx_list[i].nge_mbuf = NULL; 1024 ld->nge_tx_list[i].nge_ptr = 0; 1025 ld->nge_tx_list[i].nge_ctl = 0; 1026 } 1027 1028 cd->nge_tx_prod = cd->nge_tx_cons = cd->nge_tx_cnt = 0; 1029 1030 return(0); 1031} 1032 1033 1034/* 1035 * Initialize the RX descriptors and allocate mbufs for them. Note that 1036 * we arrange the descriptors in a closed ring, so that the last descriptor 1037 * points back to the first. 1038 */ 1039static int nge_list_rx_init(sc) 1040 struct nge_softc *sc; 1041{ 1042 struct nge_list_data *ld; 1043 struct nge_ring_data *cd; 1044 int i; 1045 1046 ld = sc->nge_ldata; 1047 cd = &sc->nge_cdata; 1048 1049 for (i = 0; i < NGE_RX_LIST_CNT; i++) { 1050 if (nge_newbuf(sc, &ld->nge_rx_list[i], NULL) == ENOBUFS) 1051 return(ENOBUFS); 1052 if (i == (NGE_RX_LIST_CNT - 1)) { 1053 ld->nge_rx_list[i].nge_nextdesc = 1054 &ld->nge_rx_list[0]; 1055 ld->nge_rx_list[i].nge_next = 1056 vtophys(&ld->nge_rx_list[0]); 1057 } else { 1058 ld->nge_rx_list[i].nge_nextdesc = 1059 &ld->nge_rx_list[i + 1]; 1060 ld->nge_rx_list[i].nge_next = 1061 vtophys(&ld->nge_rx_list[i + 1]); 1062 } 1063 } 1064 1065 cd->nge_rx_prod = 0; 1066 1067 return(0); 1068} 1069 1070/* 1071 * Initialize an RX descriptor and attach an MBUF cluster. 1072 */ 1073static int nge_newbuf(sc, c, m) 1074 struct nge_softc *sc; 1075 struct nge_desc *c; 1076 struct mbuf *m; 1077{ 1078 struct mbuf *m_new = NULL; 1079 caddr_t *buf = NULL; 1080 1081 if (m == NULL) { 1082 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1083 if (m_new == NULL) { 1084 printf("nge%d: no memory for rx list " 1085 "-- packet dropped!\n", sc->nge_unit); 1086 return(ENOBUFS); 1087 } 1088 1089 /* Allocate the jumbo buffer */ 1090 buf = nge_jalloc(sc); 1091 if (buf == NULL) { 1092#ifdef NGE_VERBOSE 1093 printf("nge%d: jumbo allocation failed " 1094 "-- packet dropped!\n", sc->nge_unit); 1095#endif 1096 m_freem(m_new); 1097 return(ENOBUFS); 1098 } 1099 /* Attach the buffer to the mbuf */ 1100 m_new->m_data = (void *)buf; 1101 m_new->m_len = m_new->m_pkthdr.len = NGE_MCLBYTES; 1102 MEXTADD(m_new, buf, NGE_MCLBYTES, nge_jfree, 1103 (struct nge_softc *)sc, 0, EXT_NET_DRV); 1104 } else { 1105 m_new = m; 1106 m_new->m_len = m_new->m_pkthdr.len = NGE_MCLBYTES; 1107 m_new->m_data = m_new->m_ext.ext_buf; 1108 } 1109 1110 m_adj(m_new, sizeof(u_int64_t)); 1111 1112 c->nge_mbuf = m_new; 1113 c->nge_ptr = vtophys(mtod(m_new, caddr_t)); 1114 c->nge_ctl = m_new->m_len; 1115 c->nge_extsts = 0; 1116 1117 return(0); 1118} 1119 1120static int nge_alloc_jumbo_mem(sc) 1121 struct nge_softc *sc; 1122{ 1123 caddr_t ptr; 1124 register int i; 1125 struct nge_jpool_entry *entry; 1126 1127 /* Grab a big chunk o' storage. */ 1128 sc->nge_cdata.nge_jumbo_buf = contigmalloc(NGE_JMEM, M_DEVBUF, 1129 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1130 1131 if (sc->nge_cdata.nge_jumbo_buf == NULL) { 1132 printf("nge%d: no memory for jumbo buffers!\n", sc->nge_unit); 1133 return(ENOBUFS); 1134 } 1135 1136 SLIST_INIT(&sc->nge_jfree_listhead); 1137 SLIST_INIT(&sc->nge_jinuse_listhead); 1138 1139 /* 1140 * Now divide it up into 9K pieces and save the addresses 1141 * in an array. 1142 */ 1143 ptr = sc->nge_cdata.nge_jumbo_buf; 1144 for (i = 0; i < NGE_JSLOTS; i++) { 1145 sc->nge_cdata.nge_jslots[i] = ptr; 1146 ptr += NGE_MCLBYTES; 1147 entry = malloc(sizeof(struct nge_jpool_entry), 1148 M_DEVBUF, M_NOWAIT); 1149 if (entry == NULL) { 1150 free(sc->nge_cdata.nge_jumbo_buf, M_DEVBUF); 1151 sc->nge_cdata.nge_jumbo_buf = NULL; 1152 printf("nge%d: no memory for jumbo " 1153 "buffer queue!\n", sc->nge_unit); 1154 return(ENOBUFS); 1155 } 1156 entry->slot = i; 1157 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead, 1158 entry, jpool_entries); 1159 } 1160 1161 return(0); 1162} 1163 1164static void nge_free_jumbo_mem(sc) 1165 struct nge_softc *sc; 1166{ 1167 register int i; 1168 struct nge_jpool_entry *entry; 1169 1170 for (i = 0; i < NGE_JSLOTS; i++) { 1171 entry = SLIST_FIRST(&sc->nge_jfree_listhead); 1172 free(entry, M_DEVBUF); 1173 SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jpool_entries); 1174 } 1175 1176 contigfree(sc->nge_cdata.nge_jumbo_buf, NGE_JMEM, M_DEVBUF); 1177 1178 return; 1179} 1180 1181/* 1182 * Allocate a jumbo buffer. 1183 */ 1184static void *nge_jalloc(sc) 1185 struct nge_softc *sc; 1186{ 1187 struct nge_jpool_entry *entry; 1188 1189 entry = SLIST_FIRST(&sc->nge_jfree_listhead); 1190 1191 if (entry == NULL) { 1192#ifdef NGE_VERBOSE 1193 printf("nge%d: no free jumbo buffers\n", sc->nge_unit); 1194#endif 1195 return(NULL); 1196 } 1197 1198 SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jpool_entries); 1199 SLIST_INSERT_HEAD(&sc->nge_jinuse_listhead, entry, jpool_entries); 1200 return(sc->nge_cdata.nge_jslots[entry->slot]); 1201} 1202 1203/* 1204 * Release a jumbo buffer. 1205 */ 1206static void nge_jfree(buf, args) 1207 caddr_t buf; 1208 void *args; 1209{ 1210 struct nge_softc *sc; 1211 int i; 1212 struct nge_jpool_entry *entry; 1213 1214 /* Extract the softc struct pointer. */ 1215 sc = args; 1216 1217 if (sc == NULL) 1218 panic("nge_jfree: can't find softc pointer!"); 1219 1220 /* calculate the slot this buffer belongs to */ 1221 i = ((vm_offset_t)buf 1222 - (vm_offset_t)sc->nge_cdata.nge_jumbo_buf) / NGE_JLEN; 1223 1224 if ((i < 0) || (i >= NGE_JSLOTS)) 1225 panic("nge_jfree: asked to free buffer that we don't manage!"); 1226 1227 entry = SLIST_FIRST(&sc->nge_jinuse_listhead); 1228 if (entry == NULL) 1229 panic("nge_jfree: buffer not in use!"); 1230 entry->slot = i; 1231 SLIST_REMOVE_HEAD(&sc->nge_jinuse_listhead, jpool_entries); 1232 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead, entry, jpool_entries); 1233 1234 return; 1235} 1236/* 1237 * A frame has been uploaded: pass the resulting mbuf chain up to 1238 * the higher level protocols. 1239 */ 1240static void nge_rxeof(sc) 1241 struct nge_softc *sc; 1242{ 1243 struct ether_header *eh; 1244 struct mbuf *m; 1245 struct ifnet *ifp; 1246 struct nge_desc *cur_rx; 1247 int i, total_len = 0; 1248 u_int32_t rxstat; 1249 1250 ifp = &sc->arpcom.ac_if; 1251 i = sc->nge_cdata.nge_rx_prod; 1252 1253 while(NGE_OWNDESC(&sc->nge_ldata->nge_rx_list[i])) { 1254 struct mbuf *m0 = NULL; 1255 u_int32_t extsts; 1256 1257 cur_rx = &sc->nge_ldata->nge_rx_list[i]; 1258 rxstat = cur_rx->nge_rxstat; 1259 extsts = cur_rx->nge_extsts; 1260 m = cur_rx->nge_mbuf; 1261 cur_rx->nge_mbuf = NULL; 1262 total_len = NGE_RXBYTES(cur_rx); 1263 NGE_INC(i, NGE_RX_LIST_CNT); 1264 1265 /* 1266 * If an error occurs, update stats, clear the 1267 * status word and leave the mbuf cluster in place: 1268 * it should simply get re-used next time this descriptor 1269 * comes up in the ring. 1270 */ 1271 if (!(rxstat & NGE_CMDSTS_PKT_OK)) { 1272 ifp->if_ierrors++; 1273 nge_newbuf(sc, cur_rx, m); 1274 continue; 1275 } 1276 1277 1278 /* 1279 * Ok. NatSemi really screwed up here. This is the 1280 * only gigE chip I know of with alignment constraints 1281 * on receive buffers. RX buffers must be 64-bit aligned. 1282 */ 1283 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1284 total_len + ETHER_ALIGN, 0, ifp, NULL); 1285 nge_newbuf(sc, cur_rx, m); 1286 if (m0 == NULL) { 1287 printf("nge%d: no receive buffers " 1288 "available -- packet dropped!\n", 1289 sc->nge_unit); 1290 ifp->if_ierrors++; 1291 continue; 1292 } 1293 m_adj(m0, ETHER_ALIGN); 1294 m = m0; 1295 1296 ifp->if_ipackets++; 1297 eh = mtod(m, struct ether_header *); 1298 1299 /* Remove header from mbuf and pass it on. */ 1300 m_adj(m, sizeof(struct ether_header)); 1301 1302 /* Do IP checksum checking. */ 1303 if (extsts & NGE_RXEXTSTS_IPPKT) 1304 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1305 if (!(extsts & NGE_RXEXTSTS_IPCSUMERR)) 1306 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1307 if ((extsts & NGE_RXEXTSTS_TCPPKT && 1308 !(extsts & NGE_RXEXTSTS_TCPCSUMERR)) || 1309 (extsts & NGE_RXEXTSTS_UDPPKT && 1310 !(extsts & NGE_RXEXTSTS_UDPCSUMERR))) { 1311 m->m_pkthdr.csum_flags |= 1312 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1313 m->m_pkthdr.csum_data = 0xffff; 1314 } 1315 1316#if NVLAN > 0 1317 /* 1318 * If we received a packet with a vlan tag, pass it 1319 * to vlan_input() instead of ether_input(). 1320 */ 1321 if (extsts & NGE_RXEXTSTS_VLANPKT) { 1322 vlan_input_tag(eh, m, extsts & NGE_RXEXTSTS_VTCI); 1323 continue; 1324 } 1325#endif 1326 1327 ether_input(ifp, eh, m); 1328 } 1329 1330 sc->nge_cdata.nge_rx_prod = i; 1331 1332 return; 1333} 1334 1335void nge_rxeoc(sc) 1336 struct nge_softc *sc; 1337{ 1338 struct ifnet *ifp; 1339 1340 ifp = &sc->arpcom.ac_if; 1341 nge_rxeof(sc); 1342 ifp->if_flags &= ~IFF_RUNNING; 1343 nge_init(sc); 1344 return; 1345} 1346 1347/* 1348 * A frame was downloaded to the chip. It's safe for us to clean up 1349 * the list buffers. 1350 */ 1351 1352static void nge_txeof(sc) 1353 struct nge_softc *sc; 1354{ 1355 struct nge_desc *cur_tx = NULL; 1356 struct ifnet *ifp; 1357 u_int32_t idx; 1358 1359 ifp = &sc->arpcom.ac_if; 1360 1361 /* Clear the timeout timer. */ 1362 ifp->if_timer = 0; 1363 1364 /* 1365 * Go through our tx list and free mbufs for those 1366 * frames that have been transmitted. 1367 */ 1368 idx = sc->nge_cdata.nge_tx_cons; 1369 while (idx != sc->nge_cdata.nge_tx_prod) { 1370 cur_tx = &sc->nge_ldata->nge_tx_list[idx]; 1371 1372 if (NGE_OWNDESC(cur_tx)) 1373 break; 1374 1375 if (cur_tx->nge_ctl & NGE_CMDSTS_MORE) { 1376 sc->nge_cdata.nge_tx_cnt--; 1377 NGE_INC(idx, NGE_TX_LIST_CNT); 1378 continue; 1379 } 1380 1381 if (!(cur_tx->nge_ctl & NGE_CMDSTS_PKT_OK)) { 1382 ifp->if_oerrors++; 1383 if (cur_tx->nge_txstat & NGE_TXSTAT_EXCESSCOLLS) 1384 ifp->if_collisions++; 1385 if (cur_tx->nge_txstat & NGE_TXSTAT_OUTOFWINCOLL) 1386 ifp->if_collisions++; 1387 } 1388 1389 ifp->if_collisions += 1390 (cur_tx->nge_txstat & NGE_TXSTAT_COLLCNT) >> 16; 1391 1392 ifp->if_opackets++; 1393 if (cur_tx->nge_mbuf != NULL) { 1394 m_freem(cur_tx->nge_mbuf); 1395 cur_tx->nge_mbuf = NULL; 1396 } 1397 1398 sc->nge_cdata.nge_tx_cnt--; 1399 NGE_INC(idx, NGE_TX_LIST_CNT); 1400 ifp->if_timer = 0; 1401 } 1402 1403 sc->nge_cdata.nge_tx_cons = idx; 1404 1405 if (cur_tx != NULL) 1406 ifp->if_flags &= ~IFF_OACTIVE; 1407 1408 return; 1409} 1410 1411static void nge_tick(xsc) 1412 void *xsc; 1413{ 1414 struct nge_softc *sc; 1415 struct mii_data *mii; 1416 struct ifnet *ifp; 1417 int s; 1418 1419 s = splimp(); 1420 1421 sc = xsc; 1422 ifp = &sc->arpcom.ac_if; 1423 1424 mii = device_get_softc(sc->nge_miibus); 1425 mii_tick(mii); 1426 1427 if (!sc->nge_link) { 1428 mii_pollstat(mii); 1429 if (mii->mii_media_status & IFM_ACTIVE && 1430 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1431 sc->nge_link++; 1432 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX) 1433 printf("nge%d: gigabit link up\n", 1434 sc->nge_unit); 1435 if (ifp->if_snd.ifq_head != NULL) 1436 nge_start(ifp); 1437 } else 1438 sc->nge_stat_ch = timeout(nge_tick, sc, hz); 1439 } 1440 1441 1442 splx(s); 1443 1444 return; 1445} 1446 1447static void nge_intr(arg) 1448 void *arg; 1449{ 1450 struct nge_softc *sc; 1451 struct ifnet *ifp; 1452 u_int32_t status; 1453 1454 sc = arg; 1455 ifp = &sc->arpcom.ac_if; 1456 1457 /* Supress unwanted interrupts */ 1458 if (!(ifp->if_flags & IFF_UP)) { 1459 nge_stop(sc); 1460 return; 1461 } 1462 1463 /* Disable interrupts. */ 1464 CSR_WRITE_4(sc, NGE_IER, 0); 1465 1466 for (;;) { 1467 /* Reading the ISR register clears all interrupts. */ 1468 status = CSR_READ_4(sc, NGE_ISR); 1469 1470 if ((status & NGE_INTRS) == 0) 1471 break; 1472 1473 if ((status & NGE_ISR_TX_DESC_OK) || 1474 (status & NGE_ISR_TX_ERR) || 1475 (status & NGE_ISR_TX_OK) || 1476 (status & NGE_ISR_TX_IDLE)) 1477 nge_txeof(sc); 1478 1479 if ((status & NGE_ISR_RX_DESC_OK) || 1480 (status & NGE_ISR_RX_OK)) 1481 nge_rxeof(sc); 1482 1483 if ((status & NGE_ISR_RX_ERR) || 1484 (status & NGE_ISR_RX_OFLOW)) { 1485 nge_rxeoc(sc); 1486 } 1487 1488 if (status & NGE_ISR_SYSERR) { 1489 nge_reset(sc); 1490 ifp->if_flags &= ~IFF_RUNNING; 1491 nge_init(sc); 1492 } 1493 1494 if (status & NGE_IMR_PHY_INTR) { 1495 sc->nge_link = 0; 1496 nge_tick(sc); 1497 } 1498 } 1499 1500 /* Re-enable interrupts. */ 1501 CSR_WRITE_4(sc, NGE_IER, 1); 1502 1503 if (ifp->if_snd.ifq_head != NULL) 1504 nge_start(ifp); 1505 1506 return; 1507} 1508 1509/* 1510 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1511 * pointers to the fragment pointers. 1512 */ 1513static int nge_encap(sc, m_head, txidx) 1514 struct nge_softc *sc; 1515 struct mbuf *m_head; 1516 u_int32_t *txidx; 1517{ 1518 struct nge_desc *f = NULL; 1519 struct mbuf *m; 1520 int frag, cur, cnt = 0; 1521#if NVLAN > 0 1522 struct ifvlan *ifv = NULL; 1523 1524 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 1525 m_head->m_pkthdr.rcvif != NULL && 1526 m_head->m_pkthdr.rcvif->if_type == IFT_8021_VLAN) 1527 ifv = m_head->m_pkthdr.rcvif->if_softc; 1528#endif 1529 1530 /* 1531 * Start packing the mbufs in this chain into 1532 * the fragment pointers. Stop when we run out 1533 * of fragments or hit the end of the mbuf chain. 1534 */ 1535 m = m_head; 1536 cur = frag = *txidx; 1537 1538 for (m = m_head; m != NULL; m = m->m_next) { 1539 if (m->m_len != 0) { 1540 if ((NGE_TX_LIST_CNT - 1541 (sc->nge_cdata.nge_tx_cnt + cnt)) < 2) 1542 return(ENOBUFS); 1543 f = &sc->nge_ldata->nge_tx_list[frag]; 1544 f->nge_ctl = NGE_CMDSTS_MORE | m->m_len; 1545 f->nge_ptr = vtophys(mtod(m, vm_offset_t)); 1546 if (cnt != 0) 1547 f->nge_ctl |= NGE_CMDSTS_OWN; 1548 cur = frag; 1549 NGE_INC(frag, NGE_TX_LIST_CNT); 1550 cnt++; 1551 } 1552 } 1553 1554 if (m != NULL) 1555 return(ENOBUFS); 1556 1557 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts = 0; 1558 if (m_head->m_pkthdr.csum_flags) { 1559 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1560 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1561 NGE_TXEXTSTS_IPCSUM; 1562 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1563 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1564 NGE_TXEXTSTS_TCPCSUM; 1565 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 1566 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1567 NGE_TXEXTSTS_UDPCSUM; 1568 } 1569 1570#if NVLAN > 0 1571 if (ifv != NULL) { 1572 sc->nge_ldata->nge_tx_list[cur].nge_extsts |= 1573 (NGE_TXEXTSTS_VLANPKT|ifv->ifv_tag); 1574 } 1575#endif 1576 1577 sc->nge_ldata->nge_tx_list[cur].nge_mbuf = m_head; 1578 sc->nge_ldata->nge_tx_list[cur].nge_ctl &= ~NGE_CMDSTS_MORE; 1579 sc->nge_ldata->nge_tx_list[*txidx].nge_ctl |= NGE_CMDSTS_OWN; 1580 sc->nge_cdata.nge_tx_cnt += cnt; 1581 *txidx = frag; 1582 1583 return(0); 1584} 1585 1586/* 1587 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1588 * to the mbuf data regions directly in the transmit lists. We also save a 1589 * copy of the pointers since the transmit list fragment pointers are 1590 * physical addresses. 1591 */ 1592 1593static void nge_start(ifp) 1594 struct ifnet *ifp; 1595{ 1596 struct nge_softc *sc; 1597 struct mbuf *m_head = NULL; 1598 u_int32_t idx; 1599 1600 sc = ifp->if_softc; 1601 1602 if (!sc->nge_link) 1603 return; 1604 1605 idx = sc->nge_cdata.nge_tx_prod; 1606 1607 if (ifp->if_flags & IFF_OACTIVE) 1608 return; 1609 1610 while(sc->nge_ldata->nge_tx_list[idx].nge_mbuf == NULL) { 1611 IF_DEQUEUE(&ifp->if_snd, m_head); 1612 if (m_head == NULL) 1613 break; 1614 1615 if (nge_encap(sc, m_head, &idx)) { 1616 IF_PREPEND(&ifp->if_snd, m_head); 1617 ifp->if_flags |= IFF_OACTIVE; 1618 break; 1619 } 1620 1621 /* 1622 * If there's a BPF listener, bounce a copy of this frame 1623 * to him. 1624 */ 1625 if (ifp->if_bpf) 1626 bpf_mtap(ifp, m_head); 1627 1628 } 1629 1630 /* Transmit */ 1631 sc->nge_cdata.nge_tx_prod = idx; 1632 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_ENABLE); 1633 1634 /* 1635 * Set a timeout in case the chip goes out to lunch. 1636 */ 1637 ifp->if_timer = 5; 1638 1639 return; 1640} 1641 1642static void nge_init(xsc) 1643 void *xsc; 1644{ 1645 struct nge_softc *sc = xsc; 1646 struct ifnet *ifp = &sc->arpcom.ac_if; 1647 struct mii_data *mii; 1648 int s; 1649 1650 if (ifp->if_flags & IFF_RUNNING) 1651 return; 1652 1653 s = splimp(); 1654 1655 /* 1656 * Cancel pending I/O and free all RX/TX buffers. 1657 */ 1658 nge_stop(sc); 1659 1660 mii = device_get_softc(sc->nge_miibus); 1661 1662 /* Set MAC address */ 1663 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0); 1664 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1665 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1666 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR1); 1667 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1668 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1669 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR2); 1670 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1671 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1672 1673 /* Init circular RX list. */ 1674 if (nge_list_rx_init(sc) == ENOBUFS) { 1675 printf("nge%d: initialization failed: no " 1676 "memory for rx buffers\n", sc->nge_unit); 1677 nge_stop(sc); 1678 (void)splx(s); 1679 return; 1680 } 1681 1682 /* 1683 * Init tx descriptors. 1684 */ 1685 nge_list_tx_init(sc); 1686 1687 /* 1688 * For the NatSemi chip, we have to explicitly enable the 1689 * reception of ARP frames, as well as turn on the 'perfect 1690 * match' filter where we store the station address, otherwise 1691 * we won't receive unicasts meant for this host. 1692 */ 1693 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ARP); 1694 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_PERFECT); 1695 1696 /* If we want promiscuous mode, set the allframes bit. */ 1697 if (ifp->if_flags & IFF_PROMISC) { 1698 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS); 1699 } else { 1700 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS); 1701 } 1702 1703 /* 1704 * Set the capture broadcast bit to capture broadcast frames. 1705 */ 1706 if (ifp->if_flags & IFF_BROADCAST) { 1707 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD); 1708 } else { 1709 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD); 1710 } 1711 1712 /* 1713 * Load the multicast filter. 1714 */ 1715 nge_setmulti(sc); 1716 1717 /* Turn the receive filter on */ 1718 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ENABLE); 1719 1720 /* 1721 * Load the address of the RX and TX lists. 1722 */ 1723 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 1724 vtophys(&sc->nge_ldata->nge_rx_list[0])); 1725 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 1726 vtophys(&sc->nge_ldata->nge_tx_list[0])); 1727 1728 /* Set RX configuration */ 1729 CSR_WRITE_4(sc, NGE_RX_CFG, NGE_RXCFG); 1730 /* 1731 * Enable hardware checksum validation for all IPv4 1732 * packets, do not reject packets with bad checksums. 1733 */ 1734 CSR_WRITE_4(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_IPCSUM_ENB); 1735 1736#if NVLAN > 0 1737 /* 1738 * If VLAN support is enabled, tell the chip to detect 1739 * and strip VLAN tag info from received frames. The tag 1740 * will be provided in the extsts field in the RX descriptors. 1741 */ 1742 NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL, 1743 NGE_VIPRXCTL_TAG_DETECT_ENB|NGE_VIPRXCTL_TAG_STRIP_ENB); 1744#endif 1745 1746 /* Set TX configuration */ 1747 CSR_WRITE_4(sc, NGE_TX_CFG, NGE_TXCFG); 1748 1749 /* 1750 * Enable TX IPv4 checksumming on a per-packet basis. 1751 */ 1752 CSR_WRITE_4(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_CSUM_PER_PKT); 1753 1754#if NVLAN > 0 1755 /* 1756 * If VLAN support is enabled, tell the chip to insert 1757 * VLAN tags on a per-packet basis as dictated by the 1758 * code in the frame encapsulation routine. 1759 */ 1760 NGE_SETBIT(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_TAG_PER_PKT); 1761#endif 1762 1763 /* Set full/half duplex mode. */ 1764 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1765 NGE_SETBIT(sc, NGE_TX_CFG, 1766 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1767 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1768 } else { 1769 NGE_CLRBIT(sc, NGE_TX_CFG, 1770 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1771 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1772 } 1773 1774 /* 1775 * Enable the delivery of PHY interrupts based on 1776 * link/speed/duplex status changes. Also enable the 1777 * extsts field in the DMA descriptors (needed for 1778 * TCP/IP checksum offload on transmit). 1779 */ 1780 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_PHYINTR_SPD|NGE_CFG_MODE_1000| 1781 NGE_CFG_PHYINTR_LNK|NGE_CFG_PHYINTR_DUP|NGE_CFG_EXTSTS_ENB); 1782 1783 /* 1784 * Enable interrupts. 1785 */ 1786 CSR_WRITE_4(sc, NGE_IMR, NGE_INTRS); 1787 CSR_WRITE_4(sc, NGE_IER, 1); 1788 1789 /* Enable receiver and transmitter. */ 1790 NGE_CLRBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE); 1791 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1792 1793 nge_ifmedia_upd(ifp); 1794 1795 ifp->if_flags |= IFF_RUNNING; 1796 ifp->if_flags &= ~IFF_OACTIVE; 1797 1798 (void)splx(s); 1799 1800 return; 1801} 1802 1803/* 1804 * Set media options. 1805 */ 1806static int nge_ifmedia_upd(ifp) 1807 struct ifnet *ifp; 1808{ 1809 struct nge_softc *sc; 1810 struct mii_data *mii; 1811 1812 sc = ifp->if_softc; 1813 1814 mii = device_get_softc(sc->nge_miibus); 1815 sc->nge_link = 0; 1816 if (mii->mii_instance) { 1817 struct mii_softc *miisc; 1818 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1819 miisc = LIST_NEXT(miisc, mii_list)) 1820 mii_phy_reset(miisc); 1821 } 1822 mii_mediachg(mii); 1823 1824 return(0); 1825} 1826 1827/* 1828 * Report current media status. 1829 */ 1830static void nge_ifmedia_sts(ifp, ifmr) 1831 struct ifnet *ifp; 1832 struct ifmediareq *ifmr; 1833{ 1834 struct nge_softc *sc; 1835 struct mii_data *mii; 1836 1837 sc = ifp->if_softc; 1838 1839 mii = device_get_softc(sc->nge_miibus); 1840 mii_pollstat(mii); 1841 ifmr->ifm_active = mii->mii_media_active; 1842 ifmr->ifm_status = mii->mii_media_status; 1843 1844 return; 1845} 1846 1847static int nge_ioctl(ifp, command, data) 1848 struct ifnet *ifp; 1849 u_long command; 1850 caddr_t data; 1851{ 1852 struct nge_softc *sc = ifp->if_softc; 1853 struct ifreq *ifr = (struct ifreq *) data; 1854 struct mii_data *mii; 1855 int s, error = 0; 1856 1857 s = splimp(); 1858 1859 switch(command) { 1860 case SIOCSIFADDR: 1861 case SIOCGIFADDR: 1862 error = ether_ioctl(ifp, command, data); 1863 break; 1864 case SIOCSIFMTU: 1865 if (ifr->ifr_mtu > NGE_JUMBO_MTU) 1866 error = EINVAL; 1867 else { 1868 ifp->if_mtu = ifr->ifr_mtu; 1869 /* 1870 * Workaround: if the MTU is larger than 1871 * 8152 (TX FIFO size minus 64 minus 18), turn off 1872 * TX checksum offloading. 1873 */ 1874 if (ifr->ifr_mtu == 8152) 1875 ifp->if_hwassist = 0; 1876 else 1877 ifp->if_hwassist = NGE_CSUM_FEATURES; 1878 } 1879 break; 1880 case SIOCSIFFLAGS: 1881 if (ifp->if_flags & IFF_UP) { 1882 if (ifp->if_flags & IFF_RUNNING && 1883 ifp->if_flags & IFF_PROMISC && 1884 !(sc->nge_if_flags & IFF_PROMISC)) { 1885 NGE_SETBIT(sc, NGE_RXFILT_CTL, 1886 NGE_RXFILTCTL_ALLPHYS| 1887 NGE_RXFILTCTL_ALLMULTI); 1888 } else if (ifp->if_flags & IFF_RUNNING && 1889 !(ifp->if_flags & IFF_PROMISC) && 1890 sc->nge_if_flags & IFF_PROMISC) { 1891 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 1892 NGE_RXFILTCTL_ALLPHYS); 1893 if (!(ifp->if_flags & IFF_ALLMULTI)) 1894 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 1895 NGE_RXFILTCTL_ALLMULTI); 1896 } else { 1897 ifp->if_flags &= ~IFF_RUNNING; 1898 nge_init(sc); 1899 } 1900 } else { 1901 if (ifp->if_flags & IFF_RUNNING) 1902 nge_stop(sc); 1903 } 1904 sc->nge_if_flags = ifp->if_flags; 1905 error = 0; 1906 break; 1907 case SIOCADDMULTI: 1908 case SIOCDELMULTI: 1909 nge_setmulti(sc); 1910 error = 0; 1911 break; 1912 case SIOCGIFMEDIA: 1913 case SIOCSIFMEDIA: 1914 mii = device_get_softc(sc->nge_miibus); 1915 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1916 break; 1917 default: 1918 error = EINVAL; 1919 break; 1920 } 1921 1922 (void)splx(s); 1923 1924 return(error); 1925} 1926 1927static void nge_watchdog(ifp) 1928 struct ifnet *ifp; 1929{ 1930 struct nge_softc *sc; 1931 1932 sc = ifp->if_softc; 1933 1934 ifp->if_oerrors++; 1935 printf("nge%d: watchdog timeout\n", sc->nge_unit); 1936 1937 nge_stop(sc); 1938 nge_reset(sc); 1939 ifp->if_flags &= ~IFF_RUNNING; 1940 nge_init(sc); 1941 1942 if (ifp->if_snd.ifq_head != NULL) 1943 nge_start(ifp); 1944 1945 return; 1946} 1947 1948/* 1949 * Stop the adapter and free any mbufs allocated to the 1950 * RX and TX lists. 1951 */ 1952static void nge_stop(sc) 1953 struct nge_softc *sc; 1954{ 1955 register int i; 1956 struct ifnet *ifp; 1957 struct ifmedia_entry *ifm; 1958 struct mii_data *mii; 1959 int mtmp, itmp; 1960 1961 ifp = &sc->arpcom.ac_if; 1962 ifp->if_timer = 0; 1963 mii = device_get_softc(sc->nge_miibus); 1964 1965 untimeout(nge_tick, sc, sc->nge_stat_ch); 1966 CSR_WRITE_4(sc, NGE_IER, 0); 1967 CSR_WRITE_4(sc, NGE_IMR, 0); 1968 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE); 1969 DELAY(1000); 1970 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 0); 1971 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 0); 1972 1973 /* 1974 * Isolate/power down the PHY, but leave the media selection 1975 * unchanged so that things will be put back to normal when 1976 * we bring the interface back up. 1977 */ 1978 itmp = ifp->if_flags; 1979 ifp->if_flags |= IFF_UP; 1980 ifm = mii->mii_media.ifm_cur; 1981 mtmp = ifm->ifm_media; 1982 ifm->ifm_media = IFM_ETHER|IFM_NONE; 1983 mii_mediachg(mii); 1984 ifm->ifm_media = mtmp; 1985 ifp->if_flags = itmp; 1986 1987 sc->nge_link = 0; 1988 1989 /* 1990 * Free data in the RX lists. 1991 */ 1992 for (i = 0; i < NGE_RX_LIST_CNT; i++) { 1993 if (sc->nge_ldata->nge_rx_list[i].nge_mbuf != NULL) { 1994 m_freem(sc->nge_ldata->nge_rx_list[i].nge_mbuf); 1995 sc->nge_ldata->nge_rx_list[i].nge_mbuf = NULL; 1996 } 1997 } 1998 bzero((char *)&sc->nge_ldata->nge_rx_list, 1999 sizeof(sc->nge_ldata->nge_rx_list)); 2000 2001 /* 2002 * Free the TX list buffers. 2003 */ 2004 for (i = 0; i < NGE_TX_LIST_CNT; i++) { 2005 if (sc->nge_ldata->nge_tx_list[i].nge_mbuf != NULL) { 2006 m_freem(sc->nge_ldata->nge_tx_list[i].nge_mbuf); 2007 sc->nge_ldata->nge_tx_list[i].nge_mbuf = NULL; 2008 } 2009 } 2010 2011 bzero((char *)&sc->nge_ldata->nge_tx_list, 2012 sizeof(sc->nge_ldata->nge_tx_list)); 2013 2014 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2015 2016 return; 2017} 2018 2019/* 2020 * Stop all chip I/O so that the kernel's probe routines don't 2021 * get confused by errant DMAs when rebooting. 2022 */ 2023static void nge_shutdown(dev) 2024 device_t dev; 2025{ 2026 struct nge_softc *sc; 2027 2028 sc = device_get_softc(dev); 2029 2030 nge_reset(sc); 2031 nge_stop(sc); 2032 2033 return; 2034} 2035