if_nge.c revision 150185
1/*-
2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2000, 2001
4 *	Bill Paul <wpaul@bsdi.com>.  All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 *    must display the following acknowledgement:
16 *	This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 *    may be used to endorse or promote products derived from this software
19 *    without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34#include <sys/cdefs.h>
35__FBSDID("$FreeBSD: head/sys/dev/nge/if_nge.c 150185 2005-09-15 20:06:44Z ru $");
36
37/*
38 * National Semiconductor DP83820/DP83821 gigabit ethernet driver
39 * for FreeBSD. Datasheets are available from:
40 *
41 * http://www.national.com/ds/DP/DP83820.pdf
42 * http://www.national.com/ds/DP/DP83821.pdf
43 *
44 * These chips are used on several low cost gigabit ethernet NICs
45 * sold by D-Link, Addtron, SMC and Asante. Both parts are
46 * virtually the same, except the 83820 is a 64-bit/32-bit part,
47 * while the 83821 is 32-bit only.
48 *
49 * Many cards also use National gigE transceivers, such as the
50 * DP83891, DP83861 and DP83862 gigPHYTER parts. The DP83861 datasheet
51 * contains a full register description that applies to all of these
52 * components:
53 *
54 * http://www.national.com/ds/DP/DP83861.pdf
55 *
56 * Written by Bill Paul <wpaul@bsdi.com>
57 * BSDi Open Source Solutions
58 */
59
60/*
61 * The NatSemi DP83820 and 83821 controllers are enhanced versions
62 * of the NatSemi MacPHYTER 10/100 devices. They support 10, 100
63 * and 1000Mbps speeds with 1000baseX (ten bit interface), MII and GMII
64 * ports. Other features include 8K TX FIFO and 32K RX FIFO, TCP/IP
65 * hardware checksum offload (IPv4 only), VLAN tagging and filtering,
66 * priority TX and RX queues, a 2048 bit multicast hash filter, 4 RX pattern
67 * matching buffers, one perfect address filter buffer and interrupt
68 * moderation. The 83820 supports both 64-bit and 32-bit addressing
69 * and data transfers: the 64-bit support can be toggled on or off
70 * via software. This affects the size of certain fields in the DMA
71 * descriptors.
72 *
73 * There are two bugs/misfeatures in the 83820/83821 that I have
74 * discovered so far:
75 *
76 * - Receive buffers must be aligned on 64-bit boundaries, which means
77 *   you must resort to copying data in order to fix up the payload
78 *   alignment.
79 *
80 * - In order to transmit jumbo frames larger than 8170 bytes, you have
81 *   to turn off transmit checksum offloading, because the chip can't
82 *   compute the checksum on an outgoing frame unless it fits entirely
83 *   within the TX FIFO, which is only 8192 bytes in size. If you have
84 *   TX checksum offload enabled and you transmit attempt to transmit a
85 *   frame larger than 8170 bytes, the transmitter will wedge.
86 *
87 * To work around the latter problem, TX checksum offload is disabled
88 * if the user selects an MTU larger than 8152 (8170 - 18).
89 */
90
91#include <sys/param.h>
92#include <sys/systm.h>
93#include <sys/sockio.h>
94#include <sys/mbuf.h>
95#include <sys/malloc.h>
96#include <sys/module.h>
97#include <sys/kernel.h>
98#include <sys/socket.h>
99
100#include <net/if.h>
101#include <net/if_arp.h>
102#include <net/ethernet.h>
103#include <net/if_dl.h>
104#include <net/if_media.h>
105#include <net/if_types.h>
106#include <net/if_vlan_var.h>
107
108#include <net/bpf.h>
109
110#include <vm/vm.h>              /* for vtophys */
111#include <vm/pmap.h>            /* for vtophys */
112#include <machine/clock.h>      /* for DELAY */
113#include <machine/bus.h>
114#include <machine/resource.h>
115#include <sys/bus.h>
116#include <sys/rman.h>
117
118#include <dev/mii/mii.h>
119#include <dev/mii/miivar.h>
120
121#include <dev/pci/pcireg.h>
122#include <dev/pci/pcivar.h>
123
124#define NGE_USEIOSPACE
125
126#include <dev/nge/if_ngereg.h>
127
128MODULE_DEPEND(nge, pci, 1, 1, 1);
129MODULE_DEPEND(nge, ether, 1, 1, 1);
130MODULE_DEPEND(nge, miibus, 1, 1, 1);
131
132/* "controller miibus0" required.  See GENERIC if you get errors here. */
133#include "miibus_if.h"
134
135#define NGE_CSUM_FEATURES	(CSUM_IP | CSUM_TCP | CSUM_UDP)
136
137/*
138 * Various supported device vendors/types and their names.
139 */
140static struct nge_type nge_devs[] = {
141	{ NGE_VENDORID, NGE_DEVICEID,
142	    "National Semiconductor Gigabit Ethernet" },
143	{ 0, 0, NULL }
144};
145
146static int nge_probe(device_t);
147static int nge_attach(device_t);
148static int nge_detach(device_t);
149
150static int nge_newbuf(struct nge_softc *, struct nge_desc *, struct mbuf *);
151static int nge_encap(struct nge_softc *, struct mbuf *, u_int32_t *);
152#ifdef NGE_FIXUP_RX
153static __inline void nge_fixup_rx (struct mbuf *);
154#endif
155static void nge_rxeof(struct nge_softc *);
156static void nge_txeof(struct nge_softc *);
157static void nge_intr(void *);
158static void nge_tick(void *);
159static void nge_tick_locked(struct nge_softc *);
160static void nge_start(struct ifnet *);
161static void nge_start_locked(struct ifnet *);
162static int nge_ioctl(struct ifnet *, u_long, caddr_t);
163static void nge_init(void *);
164static void nge_init_locked(struct nge_softc *);
165static void nge_stop(struct nge_softc *);
166static void nge_watchdog(struct ifnet *);
167static void nge_shutdown(device_t);
168static int nge_ifmedia_upd(struct ifnet *);
169static void nge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
170
171static void nge_delay(struct nge_softc *);
172static void nge_eeprom_idle(struct nge_softc *);
173static void nge_eeprom_putbyte(struct nge_softc *, int);
174static void nge_eeprom_getword(struct nge_softc *, int, u_int16_t *);
175static void nge_read_eeprom(struct nge_softc *, caddr_t, int, int, int);
176
177static void nge_mii_sync(struct nge_softc *);
178static void nge_mii_send(struct nge_softc *, u_int32_t, int);
179static int nge_mii_readreg(struct nge_softc *, struct nge_mii_frame *);
180static int nge_mii_writereg(struct nge_softc *, struct nge_mii_frame *);
181
182static int nge_miibus_readreg(device_t, int, int);
183static int nge_miibus_writereg(device_t, int, int, int);
184static void nge_miibus_statchg(device_t);
185
186static void nge_setmulti(struct nge_softc *);
187static void nge_reset(struct nge_softc *);
188static int nge_list_rx_init(struct nge_softc *);
189static int nge_list_tx_init(struct nge_softc *);
190
191#ifdef NGE_USEIOSPACE
192#define NGE_RES			SYS_RES_IOPORT
193#define NGE_RID			NGE_PCI_LOIO
194#else
195#define NGE_RES			SYS_RES_MEMORY
196#define NGE_RID			NGE_PCI_LOMEM
197#endif
198
199static device_method_t nge_methods[] = {
200	/* Device interface */
201	DEVMETHOD(device_probe,		nge_probe),
202	DEVMETHOD(device_attach,	nge_attach),
203	DEVMETHOD(device_detach,	nge_detach),
204	DEVMETHOD(device_shutdown,	nge_shutdown),
205
206	/* bus interface */
207	DEVMETHOD(bus_print_child,	bus_generic_print_child),
208	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
209
210	/* MII interface */
211	DEVMETHOD(miibus_readreg,	nge_miibus_readreg),
212	DEVMETHOD(miibus_writereg,	nge_miibus_writereg),
213	DEVMETHOD(miibus_statchg,	nge_miibus_statchg),
214
215	{ 0, 0 }
216};
217
218static driver_t nge_driver = {
219	"nge",
220	nge_methods,
221	sizeof(struct nge_softc)
222};
223
224static devclass_t nge_devclass;
225
226DRIVER_MODULE(nge, pci, nge_driver, nge_devclass, 0, 0);
227DRIVER_MODULE(miibus, nge, miibus_driver, miibus_devclass, 0, 0);
228
229#define NGE_SETBIT(sc, reg, x)				\
230	CSR_WRITE_4(sc, reg,				\
231		CSR_READ_4(sc, reg) | (x))
232
233#define NGE_CLRBIT(sc, reg, x)				\
234	CSR_WRITE_4(sc, reg,				\
235		CSR_READ_4(sc, reg) & ~(x))
236
237#define SIO_SET(x)					\
238	CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x))
239
240#define SIO_CLR(x)					\
241	CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x))
242
243static void
244nge_delay(sc)
245	struct nge_softc	*sc;
246{
247	int			idx;
248
249	for (idx = (300 / 33) + 1; idx > 0; idx--)
250		CSR_READ_4(sc, NGE_CSR);
251
252	return;
253}
254
255static void
256nge_eeprom_idle(sc)
257	struct nge_softc	*sc;
258{
259	register int		i;
260
261	SIO_SET(NGE_MEAR_EE_CSEL);
262	nge_delay(sc);
263	SIO_SET(NGE_MEAR_EE_CLK);
264	nge_delay(sc);
265
266	for (i = 0; i < 25; i++) {
267		SIO_CLR(NGE_MEAR_EE_CLK);
268		nge_delay(sc);
269		SIO_SET(NGE_MEAR_EE_CLK);
270		nge_delay(sc);
271	}
272
273	SIO_CLR(NGE_MEAR_EE_CLK);
274	nge_delay(sc);
275	SIO_CLR(NGE_MEAR_EE_CSEL);
276	nge_delay(sc);
277	CSR_WRITE_4(sc, NGE_MEAR, 0x00000000);
278
279	return;
280}
281
282/*
283 * Send a read command and address to the EEPROM, check for ACK.
284 */
285static void
286nge_eeprom_putbyte(sc, addr)
287	struct nge_softc	*sc;
288	int			addr;
289{
290	register int		d, i;
291
292	d = addr | NGE_EECMD_READ;
293
294	/*
295	 * Feed in each bit and stobe the clock.
296	 */
297	for (i = 0x400; i; i >>= 1) {
298		if (d & i) {
299			SIO_SET(NGE_MEAR_EE_DIN);
300		} else {
301			SIO_CLR(NGE_MEAR_EE_DIN);
302		}
303		nge_delay(sc);
304		SIO_SET(NGE_MEAR_EE_CLK);
305		nge_delay(sc);
306		SIO_CLR(NGE_MEAR_EE_CLK);
307		nge_delay(sc);
308	}
309
310	return;
311}
312
313/*
314 * Read a word of data stored in the EEPROM at address 'addr.'
315 */
316static void
317nge_eeprom_getword(sc, addr, dest)
318	struct nge_softc	*sc;
319	int			addr;
320	u_int16_t		*dest;
321{
322	register int		i;
323	u_int16_t		word = 0;
324
325	/* Force EEPROM to idle state. */
326	nge_eeprom_idle(sc);
327
328	/* Enter EEPROM access mode. */
329	nge_delay(sc);
330	SIO_CLR(NGE_MEAR_EE_CLK);
331	nge_delay(sc);
332	SIO_SET(NGE_MEAR_EE_CSEL);
333	nge_delay(sc);
334
335	/*
336	 * Send address of word we want to read.
337	 */
338	nge_eeprom_putbyte(sc, addr);
339
340	/*
341	 * Start reading bits from EEPROM.
342	 */
343	for (i = 0x8000; i; i >>= 1) {
344		SIO_SET(NGE_MEAR_EE_CLK);
345		nge_delay(sc);
346		if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT)
347			word |= i;
348		nge_delay(sc);
349		SIO_CLR(NGE_MEAR_EE_CLK);
350		nge_delay(sc);
351	}
352
353	/* Turn off EEPROM access mode. */
354	nge_eeprom_idle(sc);
355
356	*dest = word;
357
358	return;
359}
360
361/*
362 * Read a sequence of words from the EEPROM.
363 */
364static void
365nge_read_eeprom(sc, dest, off, cnt, swap)
366	struct nge_softc	*sc;
367	caddr_t			dest;
368	int			off;
369	int			cnt;
370	int			swap;
371{
372	int			i;
373	u_int16_t		word = 0, *ptr;
374
375	for (i = 0; i < cnt; i++) {
376		nge_eeprom_getword(sc, off + i, &word);
377		ptr = (u_int16_t *)(dest + (i * 2));
378		if (swap)
379			*ptr = ntohs(word);
380		else
381			*ptr = word;
382	}
383
384	return;
385}
386
387/*
388 * Sync the PHYs by setting data bit and strobing the clock 32 times.
389 */
390static void
391nge_mii_sync(sc)
392	struct nge_softc		*sc;
393{
394	register int		i;
395
396	SIO_SET(NGE_MEAR_MII_DIR|NGE_MEAR_MII_DATA);
397
398	for (i = 0; i < 32; i++) {
399		SIO_SET(NGE_MEAR_MII_CLK);
400		DELAY(1);
401		SIO_CLR(NGE_MEAR_MII_CLK);
402		DELAY(1);
403	}
404
405	return;
406}
407
408/*
409 * Clock a series of bits through the MII.
410 */
411static void
412nge_mii_send(sc, bits, cnt)
413	struct nge_softc		*sc;
414	u_int32_t		bits;
415	int			cnt;
416{
417	int			i;
418
419	SIO_CLR(NGE_MEAR_MII_CLK);
420
421	for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
422                if (bits & i) {
423			SIO_SET(NGE_MEAR_MII_DATA);
424                } else {
425			SIO_CLR(NGE_MEAR_MII_DATA);
426                }
427		DELAY(1);
428		SIO_CLR(NGE_MEAR_MII_CLK);
429		DELAY(1);
430		SIO_SET(NGE_MEAR_MII_CLK);
431	}
432}
433
434/*
435 * Read an PHY register through the MII.
436 */
437static int
438nge_mii_readreg(sc, frame)
439	struct nge_softc		*sc;
440	struct nge_mii_frame	*frame;
441
442{
443	int			i, ack;
444
445	/*
446	 * Set up frame for RX.
447	 */
448	frame->mii_stdelim = NGE_MII_STARTDELIM;
449	frame->mii_opcode = NGE_MII_READOP;
450	frame->mii_turnaround = 0;
451	frame->mii_data = 0;
452
453	CSR_WRITE_4(sc, NGE_MEAR, 0);
454
455	/*
456 	 * Turn on data xmit.
457	 */
458	SIO_SET(NGE_MEAR_MII_DIR);
459
460	nge_mii_sync(sc);
461
462	/*
463	 * Send command/address info.
464	 */
465	nge_mii_send(sc, frame->mii_stdelim, 2);
466	nge_mii_send(sc, frame->mii_opcode, 2);
467	nge_mii_send(sc, frame->mii_phyaddr, 5);
468	nge_mii_send(sc, frame->mii_regaddr, 5);
469
470	/* Idle bit */
471	SIO_CLR((NGE_MEAR_MII_CLK|NGE_MEAR_MII_DATA));
472	DELAY(1);
473	SIO_SET(NGE_MEAR_MII_CLK);
474	DELAY(1);
475
476	/* Turn off xmit. */
477	SIO_CLR(NGE_MEAR_MII_DIR);
478	/* Check for ack */
479	SIO_CLR(NGE_MEAR_MII_CLK);
480	DELAY(1);
481	ack = CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA;
482	SIO_SET(NGE_MEAR_MII_CLK);
483	DELAY(1);
484
485	/*
486	 * Now try reading data bits. If the ack failed, we still
487	 * need to clock through 16 cycles to keep the PHY(s) in sync.
488	 */
489	if (ack) {
490		for(i = 0; i < 16; i++) {
491			SIO_CLR(NGE_MEAR_MII_CLK);
492			DELAY(1);
493			SIO_SET(NGE_MEAR_MII_CLK);
494			DELAY(1);
495		}
496		goto fail;
497	}
498
499	for (i = 0x8000; i; i >>= 1) {
500		SIO_CLR(NGE_MEAR_MII_CLK);
501		DELAY(1);
502		if (!ack) {
503			if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA)
504				frame->mii_data |= i;
505			DELAY(1);
506		}
507		SIO_SET(NGE_MEAR_MII_CLK);
508		DELAY(1);
509	}
510
511fail:
512
513	SIO_CLR(NGE_MEAR_MII_CLK);
514	DELAY(1);
515	SIO_SET(NGE_MEAR_MII_CLK);
516	DELAY(1);
517
518	if (ack)
519		return(1);
520	return(0);
521}
522
523/*
524 * Write to a PHY register through the MII.
525 */
526static int
527nge_mii_writereg(sc, frame)
528	struct nge_softc		*sc;
529	struct nge_mii_frame	*frame;
530
531{
532
533	/*
534	 * Set up frame for TX.
535	 */
536
537	frame->mii_stdelim = NGE_MII_STARTDELIM;
538	frame->mii_opcode = NGE_MII_WRITEOP;
539	frame->mii_turnaround = NGE_MII_TURNAROUND;
540
541	/*
542 	 * Turn on data output.
543	 */
544	SIO_SET(NGE_MEAR_MII_DIR);
545
546	nge_mii_sync(sc);
547
548	nge_mii_send(sc, frame->mii_stdelim, 2);
549	nge_mii_send(sc, frame->mii_opcode, 2);
550	nge_mii_send(sc, frame->mii_phyaddr, 5);
551	nge_mii_send(sc, frame->mii_regaddr, 5);
552	nge_mii_send(sc, frame->mii_turnaround, 2);
553	nge_mii_send(sc, frame->mii_data, 16);
554
555	/* Idle bit. */
556	SIO_SET(NGE_MEAR_MII_CLK);
557	DELAY(1);
558	SIO_CLR(NGE_MEAR_MII_CLK);
559	DELAY(1);
560
561	/*
562	 * Turn off xmit.
563	 */
564	SIO_CLR(NGE_MEAR_MII_DIR);
565
566	return(0);
567}
568
569static int
570nge_miibus_readreg(dev, phy, reg)
571	device_t		dev;
572	int			phy, reg;
573{
574	struct nge_softc	*sc;
575	struct nge_mii_frame	frame;
576
577	sc = device_get_softc(dev);
578
579	bzero((char *)&frame, sizeof(frame));
580
581	frame.mii_phyaddr = phy;
582	frame.mii_regaddr = reg;
583	nge_mii_readreg(sc, &frame);
584
585	return(frame.mii_data);
586}
587
588static int
589nge_miibus_writereg(dev, phy, reg, data)
590	device_t		dev;
591	int			phy, reg, data;
592{
593	struct nge_softc	*sc;
594	struct nge_mii_frame	frame;
595
596	sc = device_get_softc(dev);
597
598	bzero((char *)&frame, sizeof(frame));
599
600	frame.mii_phyaddr = phy;
601	frame.mii_regaddr = reg;
602	frame.mii_data = data;
603	nge_mii_writereg(sc, &frame);
604
605	return(0);
606}
607
608static void
609nge_miibus_statchg(dev)
610	device_t		dev;
611{
612	int			status;
613	struct nge_softc	*sc;
614	struct mii_data		*mii;
615
616	sc = device_get_softc(dev);
617	if (sc->nge_tbi) {
618		if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media)
619		    == IFM_AUTO) {
620			status = CSR_READ_4(sc, NGE_TBI_ANLPAR);
621			if (status == 0 || status & NGE_TBIANAR_FDX) {
622				NGE_SETBIT(sc, NGE_TX_CFG,
623				    (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
624				NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
625			} else {
626				NGE_CLRBIT(sc, NGE_TX_CFG,
627				    (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
628				NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
629			}
630
631		} else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
632			!= IFM_FDX) {
633			NGE_CLRBIT(sc, NGE_TX_CFG,
634			    (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
635			NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
636		} else {
637			NGE_SETBIT(sc, NGE_TX_CFG,
638			    (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
639			NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
640		}
641	} else {
642		mii = device_get_softc(sc->nge_miibus);
643
644		if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
645		        NGE_SETBIT(sc, NGE_TX_CFG,
646			    (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
647			NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
648		} else {
649			NGE_CLRBIT(sc, NGE_TX_CFG,
650			    (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
651			NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
652		}
653
654		/* If we have a 1000Mbps link, set the mode_1000 bit. */
655		if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
656		    IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
657			NGE_SETBIT(sc, NGE_CFG, NGE_CFG_MODE_1000);
658		} else {
659			NGE_CLRBIT(sc, NGE_CFG, NGE_CFG_MODE_1000);
660		}
661	}
662	return;
663}
664
665static void
666nge_setmulti(sc)
667	struct nge_softc	*sc;
668{
669	struct ifnet		*ifp;
670	struct ifmultiaddr	*ifma;
671	u_int32_t		h = 0, i, filtsave;
672	int			bit, index;
673
674	NGE_LOCK_ASSERT(sc);
675	ifp = sc->nge_ifp;
676
677	if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
678		NGE_CLRBIT(sc, NGE_RXFILT_CTL,
679		    NGE_RXFILTCTL_MCHASH|NGE_RXFILTCTL_UCHASH);
680		NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLMULTI);
681		return;
682	}
683
684	/*
685	 * We have to explicitly enable the multicast hash table
686	 * on the NatSemi chip if we want to use it, which we do.
687	 * We also have to tell it that we don't want to use the
688	 * hash table for matching unicast addresses.
689	 */
690	NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_MCHASH);
691	NGE_CLRBIT(sc, NGE_RXFILT_CTL,
692	    NGE_RXFILTCTL_ALLMULTI|NGE_RXFILTCTL_UCHASH);
693
694	filtsave = CSR_READ_4(sc, NGE_RXFILT_CTL);
695
696	/* first, zot all the existing hash bits */
697	for (i = 0; i < NGE_MCAST_FILTER_LEN; i += 2) {
698		CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + i);
699		CSR_WRITE_4(sc, NGE_RXFILT_DATA, 0);
700	}
701
702	/*
703	 * From the 11 bits returned by the crc routine, the top 7
704	 * bits represent the 16-bit word in the mcast hash table
705	 * that needs to be updated, and the lower 4 bits represent
706	 * which bit within that byte needs to be set.
707	 */
708	IF_ADDR_LOCK(ifp);
709	TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
710		if (ifma->ifma_addr->sa_family != AF_LINK)
711			continue;
712		h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
713		    ifma->ifma_addr), ETHER_ADDR_LEN) >> 21;
714		index = (h >> 4) & 0x7F;
715		bit = h & 0xF;
716		CSR_WRITE_4(sc, NGE_RXFILT_CTL,
717		    NGE_FILTADDR_MCAST_LO + (index * 2));
718		NGE_SETBIT(sc, NGE_RXFILT_DATA, (1 << bit));
719	}
720	IF_ADDR_UNLOCK(ifp);
721
722	CSR_WRITE_4(sc, NGE_RXFILT_CTL, filtsave);
723
724	return;
725}
726
727static void
728nge_reset(sc)
729	struct nge_softc	*sc;
730{
731	register int		i;
732
733	NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RESET);
734
735	for (i = 0; i < NGE_TIMEOUT; i++) {
736		if (!(CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET))
737			break;
738	}
739
740	if (i == NGE_TIMEOUT)
741		printf("nge%d: reset never completed\n", sc->nge_unit);
742
743	/* Wait a little while for the chip to get its brains in order. */
744	DELAY(1000);
745
746	/*
747	 * If this is a NetSemi chip, make sure to clear
748	 * PME mode.
749	 */
750	CSR_WRITE_4(sc, NGE_CLKRUN, NGE_CLKRUN_PMESTS);
751	CSR_WRITE_4(sc, NGE_CLKRUN, 0);
752
753        return;
754}
755
756/*
757 * Probe for a NatSemi chip. Check the PCI vendor and device
758 * IDs against our list and return a device name if we find a match.
759 */
760static int
761nge_probe(dev)
762	device_t		dev;
763{
764	struct nge_type		*t;
765
766	t = nge_devs;
767
768	while(t->nge_name != NULL) {
769		if ((pci_get_vendor(dev) == t->nge_vid) &&
770		    (pci_get_device(dev) == t->nge_did)) {
771			device_set_desc(dev, t->nge_name);
772			return(BUS_PROBE_DEFAULT);
773		}
774		t++;
775	}
776
777	return(ENXIO);
778}
779
780/*
781 * Attach the interface. Allocate softc structures, do ifmedia
782 * setup and ethernet/BPF attach.
783 */
784static int
785nge_attach(dev)
786	device_t		dev;
787{
788	u_char			eaddr[ETHER_ADDR_LEN];
789	struct nge_softc	*sc;
790	struct ifnet		*ifp;
791	int			unit, error = 0, rid;
792	const char		*sep = "";
793
794	sc = device_get_softc(dev);
795	unit = device_get_unit(dev);
796	bzero(sc, sizeof(struct nge_softc));
797
798	NGE_LOCK_INIT(sc, device_get_nameunit(dev));
799	/*
800	 * Map control/status registers.
801	 */
802	pci_enable_busmaster(dev);
803
804	rid = NGE_RID;
805	sc->nge_res = bus_alloc_resource_any(dev, NGE_RES, &rid, RF_ACTIVE);
806
807	if (sc->nge_res == NULL) {
808		printf("nge%d: couldn't map ports/memory\n", unit);
809		error = ENXIO;
810		goto fail;
811	}
812
813	sc->nge_btag = rman_get_bustag(sc->nge_res);
814	sc->nge_bhandle = rman_get_bushandle(sc->nge_res);
815
816	/* Allocate interrupt */
817	rid = 0;
818	sc->nge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
819	    RF_SHAREABLE | RF_ACTIVE);
820
821	if (sc->nge_irq == NULL) {
822		printf("nge%d: couldn't map interrupt\n", unit);
823		bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
824		error = ENXIO;
825		goto fail;
826	}
827
828	/* Reset the adapter. */
829	nge_reset(sc);
830
831	/*
832	 * Get station address from the EEPROM.
833	 */
834	nge_read_eeprom(sc, (caddr_t)&eaddr[4], NGE_EE_NODEADDR, 1, 0);
835	nge_read_eeprom(sc, (caddr_t)&eaddr[2], NGE_EE_NODEADDR + 1, 1, 0);
836	nge_read_eeprom(sc, (caddr_t)&eaddr[0], NGE_EE_NODEADDR + 2, 1, 0);
837
838	sc->nge_unit = unit;
839
840	/* XXX: leaked on error */
841	sc->nge_ldata = contigmalloc(sizeof(struct nge_list_data), M_DEVBUF,
842	    M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
843
844	if (sc->nge_ldata == NULL) {
845		printf("nge%d: no memory for list buffers!\n", unit);
846		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
847		bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
848		error = ENXIO;
849		goto fail;
850	}
851
852	ifp = sc->nge_ifp = if_alloc(IFT_ETHER);
853	if (ifp == NULL) {
854		printf("nge%d: can not if_alloc()\n", unit);
855		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
856		bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
857		error = ENOSPC;
858		goto fail;
859	}
860	ifp->if_softc = sc;
861	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
862	ifp->if_mtu = ETHERMTU;
863	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
864	ifp->if_ioctl = nge_ioctl;
865	ifp->if_start = nge_start;
866	ifp->if_watchdog = nge_watchdog;
867	ifp->if_init = nge_init;
868	ifp->if_baudrate = 1000000000;
869	ifp->if_snd.ifq_maxlen = NGE_TX_LIST_CNT - 1;
870	ifp->if_hwassist = NGE_CSUM_FEATURES;
871	ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING;
872#ifdef DEVICE_POLLING
873	ifp->if_capabilities |= IFCAP_POLLING;
874#endif
875	ifp->if_capenable = ifp->if_capabilities;
876
877	/*
878	 * Do MII setup.
879	 */
880	/* XXX: leaked on error */
881	if (mii_phy_probe(dev, &sc->nge_miibus,
882			  nge_ifmedia_upd, nge_ifmedia_sts)) {
883		if (CSR_READ_4(sc, NGE_CFG) & NGE_CFG_TBI_EN) {
884			sc->nge_tbi = 1;
885			device_printf(dev, "Using TBI\n");
886
887			sc->nge_miibus = dev;
888
889			ifmedia_init(&sc->nge_ifmedia, 0, nge_ifmedia_upd,
890				nge_ifmedia_sts);
891#define	ADD(m, c)	ifmedia_add(&sc->nge_ifmedia, (m), (c), NULL)
892#define PRINT(s)	printf("%s%s", sep, s); sep = ", "
893			ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, 0), 0);
894			device_printf(dev, " ");
895			ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, 0, 0), 0);
896			PRINT("1000baseSX");
897			ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, 0),0);
898			PRINT("1000baseSX-FDX");
899			ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0), 0);
900			PRINT("auto");
901
902			printf("\n");
903#undef ADD
904#undef PRINT
905			ifmedia_set(&sc->nge_ifmedia,
906				IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0));
907
908			CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
909				| NGE_GPIO_GP4_OUT
910				| NGE_GPIO_GP1_OUTENB | NGE_GPIO_GP2_OUTENB
911				| NGE_GPIO_GP3_OUTENB
912				| NGE_GPIO_GP3_IN | NGE_GPIO_GP4_IN);
913
914		} else {
915			printf("nge%d: MII without any PHY!\n", sc->nge_unit);
916			if_free(ifp);
917			bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
918			bus_release_resource(dev, NGE_RES, NGE_RID,
919					 sc->nge_res);
920			error = ENXIO;
921			goto fail;
922		}
923	}
924
925	/*
926	 * Call MI attach routine.
927	 */
928	ether_ifattach(ifp, eaddr);
929	callout_init(&sc->nge_stat_ch, CALLOUT_MPSAFE);
930
931	/*
932	 * Hookup IRQ last.
933	 */
934	error = bus_setup_intr(dev, sc->nge_irq, INTR_TYPE_NET | INTR_MPSAFE,
935	    nge_intr, sc, &sc->nge_intrhand);
936	if (error) {
937		/* XXX: resource leaks */
938		if_free(ifp);
939		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
940		bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
941		printf("nge%d: couldn't set up irq\n", unit);
942	}
943
944fail:
945
946	if (error)
947		NGE_LOCK_DESTROY(sc);
948	return(error);
949}
950
951static int
952nge_detach(dev)
953	device_t		dev;
954{
955	struct nge_softc	*sc;
956	struct ifnet		*ifp;
957
958	sc = device_get_softc(dev);
959	ifp = sc->nge_ifp;
960
961	NGE_LOCK(sc);
962	nge_reset(sc);
963	nge_stop(sc);
964	NGE_UNLOCK(sc);
965	ether_ifdetach(ifp);
966	if_free(ifp);
967
968	bus_generic_detach(dev);
969	if (!sc->nge_tbi) {
970		device_delete_child(dev, sc->nge_miibus);
971	}
972	bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand);
973	bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
974	bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
975
976	contigfree(sc->nge_ldata, sizeof(struct nge_list_data), M_DEVBUF);
977
978	NGE_LOCK_DESTROY(sc);
979
980	return(0);
981}
982
983/*
984 * Initialize the transmit descriptors.
985 */
986static int
987nge_list_tx_init(sc)
988	struct nge_softc	*sc;
989{
990	struct nge_list_data	*ld;
991	struct nge_ring_data	*cd;
992	int			i;
993
994	cd = &sc->nge_cdata;
995	ld = sc->nge_ldata;
996
997	for (i = 0; i < NGE_TX_LIST_CNT; i++) {
998		if (i == (NGE_TX_LIST_CNT - 1)) {
999			ld->nge_tx_list[i].nge_nextdesc =
1000			    &ld->nge_tx_list[0];
1001			ld->nge_tx_list[i].nge_next =
1002			    vtophys(&ld->nge_tx_list[0]);
1003		} else {
1004			ld->nge_tx_list[i].nge_nextdesc =
1005			    &ld->nge_tx_list[i + 1];
1006			ld->nge_tx_list[i].nge_next =
1007			    vtophys(&ld->nge_tx_list[i + 1]);
1008		}
1009		ld->nge_tx_list[i].nge_mbuf = NULL;
1010		ld->nge_tx_list[i].nge_ptr = 0;
1011		ld->nge_tx_list[i].nge_ctl = 0;
1012	}
1013
1014	cd->nge_tx_prod = cd->nge_tx_cons = cd->nge_tx_cnt = 0;
1015
1016	return(0);
1017}
1018
1019
1020/*
1021 * Initialize the RX descriptors and allocate mbufs for them. Note that
1022 * we arrange the descriptors in a closed ring, so that the last descriptor
1023 * points back to the first.
1024 */
1025static int
1026nge_list_rx_init(sc)
1027	struct nge_softc	*sc;
1028{
1029	struct nge_list_data	*ld;
1030	struct nge_ring_data	*cd;
1031	int			i;
1032
1033	ld = sc->nge_ldata;
1034	cd = &sc->nge_cdata;
1035
1036	for (i = 0; i < NGE_RX_LIST_CNT; i++) {
1037		if (nge_newbuf(sc, &ld->nge_rx_list[i], NULL) == ENOBUFS)
1038			return(ENOBUFS);
1039		if (i == (NGE_RX_LIST_CNT - 1)) {
1040			ld->nge_rx_list[i].nge_nextdesc =
1041			    &ld->nge_rx_list[0];
1042			ld->nge_rx_list[i].nge_next =
1043			    vtophys(&ld->nge_rx_list[0]);
1044		} else {
1045			ld->nge_rx_list[i].nge_nextdesc =
1046			    &ld->nge_rx_list[i + 1];
1047			ld->nge_rx_list[i].nge_next =
1048			    vtophys(&ld->nge_rx_list[i + 1]);
1049		}
1050	}
1051
1052	cd->nge_rx_prod = 0;
1053	sc->nge_head = sc->nge_tail = NULL;
1054
1055	return(0);
1056}
1057
1058/*
1059 * Initialize an RX descriptor and attach an MBUF cluster.
1060 */
1061static int
1062nge_newbuf(sc, c, m)
1063	struct nge_softc	*sc;
1064	struct nge_desc		*c;
1065	struct mbuf		*m;
1066{
1067
1068	if (m == NULL) {
1069		m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1070		if (m == NULL)
1071			return (ENOBUFS);
1072	} else
1073		m->m_data = m->m_ext.ext_buf;
1074
1075	m->m_len = m->m_pkthdr.len = MCLBYTES;
1076
1077	m_adj(m, sizeof(u_int64_t));
1078
1079	c->nge_mbuf = m;
1080	c->nge_ptr = vtophys(mtod(m, caddr_t));
1081	c->nge_ctl = m->m_len;
1082	c->nge_extsts = 0;
1083
1084	return(0);
1085}
1086
1087#ifdef NGE_FIXUP_RX
1088static __inline void
1089nge_fixup_rx(m)
1090	struct mbuf		*m;
1091{
1092        int			i;
1093        uint16_t		*src, *dst;
1094
1095	src = mtod(m, uint16_t *);
1096	dst = src - 1;
1097
1098	for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
1099		*dst++ = *src++;
1100
1101	m->m_data -= ETHER_ALIGN;
1102
1103	return;
1104}
1105#endif
1106
1107/*
1108 * A frame has been uploaded: pass the resulting mbuf chain up to
1109 * the higher level protocols.
1110 */
1111static void
1112nge_rxeof(sc)
1113	struct nge_softc	*sc;
1114{
1115        struct mbuf		*m;
1116        struct ifnet		*ifp;
1117	struct nge_desc		*cur_rx;
1118	int			i, total_len = 0;
1119	u_int32_t		rxstat;
1120
1121	NGE_LOCK_ASSERT(sc);
1122	ifp = sc->nge_ifp;
1123	i = sc->nge_cdata.nge_rx_prod;
1124
1125	while(NGE_OWNDESC(&sc->nge_ldata->nge_rx_list[i])) {
1126		u_int32_t		extsts;
1127
1128#ifdef DEVICE_POLLING
1129		if (ifp->if_flags & IFF_POLLING) {
1130			if (sc->rxcycles <= 0)
1131				break;
1132			sc->rxcycles--;
1133		}
1134#endif /* DEVICE_POLLING */
1135
1136		cur_rx = &sc->nge_ldata->nge_rx_list[i];
1137		rxstat = cur_rx->nge_rxstat;
1138		extsts = cur_rx->nge_extsts;
1139		m = cur_rx->nge_mbuf;
1140		cur_rx->nge_mbuf = NULL;
1141		total_len = NGE_RXBYTES(cur_rx);
1142		NGE_INC(i, NGE_RX_LIST_CNT);
1143
1144		if (rxstat & NGE_CMDSTS_MORE) {
1145			m->m_len = total_len;
1146			if (sc->nge_head == NULL) {
1147				m->m_pkthdr.len = total_len;
1148				sc->nge_head = sc->nge_tail = m;
1149			} else {
1150				m->m_flags &= ~M_PKTHDR;
1151				sc->nge_head->m_pkthdr.len += total_len;
1152				sc->nge_tail->m_next = m;
1153				sc->nge_tail = m;
1154			}
1155			nge_newbuf(sc, cur_rx, NULL);
1156			continue;
1157		}
1158
1159		/*
1160		 * If an error occurs, update stats, clear the
1161		 * status word and leave the mbuf cluster in place:
1162		 * it should simply get re-used next time this descriptor
1163	 	 * comes up in the ring.
1164		 */
1165		if (!(rxstat & NGE_CMDSTS_PKT_OK)) {
1166			ifp->if_ierrors++;
1167			if (sc->nge_head != NULL) {
1168				m_freem(sc->nge_head);
1169				sc->nge_head = sc->nge_tail = NULL;
1170			}
1171			nge_newbuf(sc, cur_rx, m);
1172			continue;
1173		}
1174
1175		/* Try conjure up a replacement mbuf. */
1176
1177		if (nge_newbuf(sc, cur_rx, NULL)) {
1178			ifp->if_ierrors++;
1179			if (sc->nge_head != NULL) {
1180				m_freem(sc->nge_head);
1181				sc->nge_head = sc->nge_tail = NULL;
1182			}
1183			nge_newbuf(sc, cur_rx, m);
1184			continue;
1185		}
1186
1187		if (sc->nge_head != NULL) {
1188			m->m_len = total_len;
1189			m->m_flags &= ~M_PKTHDR;
1190			sc->nge_tail->m_next = m;
1191			m = sc->nge_head;
1192			m->m_pkthdr.len += total_len;
1193			sc->nge_head = sc->nge_tail = NULL;
1194		} else
1195			m->m_pkthdr.len = m->m_len = total_len;
1196
1197		/*
1198		 * Ok. NatSemi really screwed up here. This is the
1199		 * only gigE chip I know of with alignment constraints
1200		 * on receive buffers. RX buffers must be 64-bit aligned.
1201		 */
1202		/*
1203		 * By popular demand, ignore the alignment problems
1204		 * on the Intel x86 platform. The performance hit
1205		 * incurred due to unaligned accesses is much smaller
1206		 * than the hit produced by forcing buffer copies all
1207		 * the time, especially with jumbo frames. We still
1208		 * need to fix up the alignment everywhere else though.
1209		 */
1210#ifdef NGE_FIXUP_RX
1211		nge_fixup_rx(m);
1212#endif
1213
1214		ifp->if_ipackets++;
1215		m->m_pkthdr.rcvif = ifp;
1216
1217		/* Do IP checksum checking. */
1218		if (extsts & NGE_RXEXTSTS_IPPKT)
1219			m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1220		if (!(extsts & NGE_RXEXTSTS_IPCSUMERR))
1221			m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1222		if ((extsts & NGE_RXEXTSTS_TCPPKT &&
1223		    !(extsts & NGE_RXEXTSTS_TCPCSUMERR)) ||
1224		    (extsts & NGE_RXEXTSTS_UDPPKT &&
1225		    !(extsts & NGE_RXEXTSTS_UDPCSUMERR))) {
1226			m->m_pkthdr.csum_flags |=
1227			    CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1228			m->m_pkthdr.csum_data = 0xffff;
1229		}
1230
1231		/*
1232		 * If we received a packet with a vlan tag, pass it
1233		 * to vlan_input() instead of ether_input().
1234		 */
1235		if (extsts & NGE_RXEXTSTS_VLANPKT) {
1236			VLAN_INPUT_TAG(ifp, m,
1237			    ntohs(extsts & NGE_RXEXTSTS_VTCI), continue);
1238		}
1239		NGE_UNLOCK(sc);
1240		(*ifp->if_input)(ifp, m);
1241		NGE_LOCK(sc);
1242	}
1243
1244	sc->nge_cdata.nge_rx_prod = i;
1245
1246	return;
1247}
1248
1249/*
1250 * A frame was downloaded to the chip. It's safe for us to clean up
1251 * the list buffers.
1252 */
1253
1254static void
1255nge_txeof(sc)
1256	struct nge_softc	*sc;
1257{
1258	struct nge_desc		*cur_tx;
1259	struct ifnet		*ifp;
1260	u_int32_t		idx;
1261
1262	NGE_LOCK_ASSERT(sc);
1263	ifp = sc->nge_ifp;
1264
1265	/*
1266	 * Go through our tx list and free mbufs for those
1267	 * frames that have been transmitted.
1268	 */
1269	idx = sc->nge_cdata.nge_tx_cons;
1270	while (idx != sc->nge_cdata.nge_tx_prod) {
1271		cur_tx = &sc->nge_ldata->nge_tx_list[idx];
1272
1273		if (NGE_OWNDESC(cur_tx))
1274			break;
1275
1276		if (cur_tx->nge_ctl & NGE_CMDSTS_MORE) {
1277			sc->nge_cdata.nge_tx_cnt--;
1278			NGE_INC(idx, NGE_TX_LIST_CNT);
1279			continue;
1280		}
1281
1282		if (!(cur_tx->nge_ctl & NGE_CMDSTS_PKT_OK)) {
1283			ifp->if_oerrors++;
1284			if (cur_tx->nge_txstat & NGE_TXSTAT_EXCESSCOLLS)
1285				ifp->if_collisions++;
1286			if (cur_tx->nge_txstat & NGE_TXSTAT_OUTOFWINCOLL)
1287				ifp->if_collisions++;
1288		}
1289
1290		ifp->if_collisions +=
1291		    (cur_tx->nge_txstat & NGE_TXSTAT_COLLCNT) >> 16;
1292
1293		ifp->if_opackets++;
1294		if (cur_tx->nge_mbuf != NULL) {
1295			m_freem(cur_tx->nge_mbuf);
1296			cur_tx->nge_mbuf = NULL;
1297			ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1298		}
1299
1300		sc->nge_cdata.nge_tx_cnt--;
1301		NGE_INC(idx, NGE_TX_LIST_CNT);
1302	}
1303
1304	sc->nge_cdata.nge_tx_cons = idx;
1305
1306	if (idx == sc->nge_cdata.nge_tx_prod)
1307		ifp->if_timer = 0;
1308
1309	return;
1310}
1311
1312static void
1313nge_tick(xsc)
1314	void			*xsc;
1315{
1316	struct nge_softc	*sc;
1317
1318	sc = xsc;
1319
1320	NGE_LOCK(sc);
1321	nge_tick_locked(sc);
1322	NGE_UNLOCK(sc);
1323}
1324
1325static void
1326nge_tick_locked(sc)
1327	struct nge_softc	*sc;
1328{
1329	struct mii_data		*mii;
1330	struct ifnet		*ifp;
1331
1332	NGE_LOCK_ASSERT(sc);
1333	ifp = sc->nge_ifp;
1334
1335	if (sc->nge_tbi) {
1336		if (!sc->nge_link) {
1337			if (CSR_READ_4(sc, NGE_TBI_BMSR)
1338			    & NGE_TBIBMSR_ANEG_DONE) {
1339				if (bootverbose)
1340					printf("nge%d: gigabit link up\n",
1341					    sc->nge_unit);
1342				nge_miibus_statchg(sc->nge_miibus);
1343				sc->nge_link++;
1344				if (ifp->if_snd.ifq_head != NULL)
1345					nge_start_locked(ifp);
1346			}
1347		}
1348	} else {
1349		mii = device_get_softc(sc->nge_miibus);
1350		mii_tick(mii);
1351
1352		if (!sc->nge_link) {
1353			if (mii->mii_media_status & IFM_ACTIVE &&
1354			    IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1355				sc->nge_link++;
1356				if (IFM_SUBTYPE(mii->mii_media_active)
1357				    == IFM_1000_T && bootverbose)
1358					printf("nge%d: gigabit link up\n",
1359					    sc->nge_unit);
1360				if (ifp->if_snd.ifq_head != NULL)
1361					nge_start_locked(ifp);
1362			}
1363		}
1364	}
1365	callout_reset(&sc->nge_stat_ch, hz, nge_tick, sc);
1366
1367	return;
1368}
1369
1370#ifdef DEVICE_POLLING
1371static poll_handler_t nge_poll;
1372
1373static void
1374nge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1375{
1376	struct  nge_softc *sc = ifp->if_softc;
1377
1378	NGE_LOCK(sc);
1379	if (!(ifp->if_capenable & IFCAP_POLLING)) {
1380		ether_poll_deregister(ifp);
1381		cmd = POLL_DEREGISTER;
1382	}
1383	if (cmd == POLL_DEREGISTER) {	/* final call, enable interrupts */
1384		CSR_WRITE_4(sc, NGE_IER, 1);
1385		NGE_UNLOCK(sc);
1386		return;
1387	}
1388
1389	/*
1390	 * On the nge, reading the status register also clears it.
1391	 * So before returning to intr mode we must make sure that all
1392	 * possible pending sources of interrupts have been served.
1393	 * In practice this means run to completion the *eof routines,
1394	 * and then call the interrupt routine
1395	 */
1396	sc->rxcycles = count;
1397	nge_rxeof(sc);
1398	nge_txeof(sc);
1399	if (ifp->if_snd.ifq_head != NULL)
1400		nge_start_locked(ifp);
1401
1402	if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) {
1403		u_int32_t	status;
1404
1405		/* Reading the ISR register clears all interrupts. */
1406		status = CSR_READ_4(sc, NGE_ISR);
1407
1408		if (status & (NGE_ISR_RX_ERR|NGE_ISR_RX_OFLOW))
1409			nge_rxeof(sc);
1410
1411		if (status & (NGE_ISR_RX_IDLE))
1412			NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
1413
1414		if (status & NGE_ISR_SYSERR) {
1415			nge_reset(sc);
1416			nge_init_locked(sc);
1417		}
1418	}
1419	NGE_UNLOCK(sc);
1420}
1421#endif /* DEVICE_POLLING */
1422
1423static void
1424nge_intr(arg)
1425	void			*arg;
1426{
1427	struct nge_softc	*sc;
1428	struct ifnet		*ifp;
1429	u_int32_t		status;
1430
1431	sc = arg;
1432	ifp = sc->nge_ifp;
1433
1434	NGE_LOCK(sc);
1435#ifdef DEVICE_POLLING
1436	if (ifp->if_flags & IFF_POLLING) {
1437		NGE_UNLOCK(sc);
1438		return;
1439	}
1440	if ((ifp->if_capenable & IFCAP_POLLING) &&
1441	    ether_poll_register(nge_poll, ifp)) { /* ok, disable interrupts */
1442		CSR_WRITE_4(sc, NGE_IER, 0);
1443		NGE_UNLOCK(sc);
1444		nge_poll(ifp, 0, 1);
1445		return;
1446	}
1447#endif /* DEVICE_POLLING */
1448
1449	/* Supress unwanted interrupts */
1450	if (!(ifp->if_flags & IFF_UP)) {
1451		nge_stop(sc);
1452		NGE_UNLOCK(sc);
1453		return;
1454	}
1455
1456	/* Disable interrupts. */
1457	CSR_WRITE_4(sc, NGE_IER, 0);
1458
1459	/* Data LED on for TBI mode */
1460	if(sc->nge_tbi)
1461		 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
1462			     | NGE_GPIO_GP3_OUT);
1463
1464	for (;;) {
1465		/* Reading the ISR register clears all interrupts. */
1466		status = CSR_READ_4(sc, NGE_ISR);
1467
1468		if ((status & NGE_INTRS) == 0)
1469			break;
1470
1471		if ((status & NGE_ISR_TX_DESC_OK) ||
1472		    (status & NGE_ISR_TX_ERR) ||
1473		    (status & NGE_ISR_TX_OK) ||
1474		    (status & NGE_ISR_TX_IDLE))
1475			nge_txeof(sc);
1476
1477		if ((status & NGE_ISR_RX_DESC_OK) ||
1478		    (status & NGE_ISR_RX_ERR) ||
1479		    (status & NGE_ISR_RX_OFLOW) ||
1480		    (status & NGE_ISR_RX_FIFO_OFLOW) ||
1481		    (status & NGE_ISR_RX_IDLE) ||
1482		    (status & NGE_ISR_RX_OK))
1483			nge_rxeof(sc);
1484
1485		if ((status & NGE_ISR_RX_IDLE))
1486			NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
1487
1488		if (status & NGE_ISR_SYSERR) {
1489			nge_reset(sc);
1490			ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1491			nge_init_locked(sc);
1492		}
1493
1494#if 0
1495		/*
1496		 * XXX: nge_tick() is not ready to be called this way
1497		 * it screws up the aneg timeout because mii_tick() is
1498		 * only to be called once per second.
1499		 */
1500		if (status & NGE_IMR_PHY_INTR) {
1501			sc->nge_link = 0;
1502			nge_tick_locked(sc);
1503		}
1504#endif
1505	}
1506
1507	/* Re-enable interrupts. */
1508	CSR_WRITE_4(sc, NGE_IER, 1);
1509
1510	if (ifp->if_snd.ifq_head != NULL)
1511		nge_start_locked(ifp);
1512
1513	/* Data LED off for TBI mode */
1514
1515	if(sc->nge_tbi)
1516		CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
1517			    & ~NGE_GPIO_GP3_OUT);
1518
1519	NGE_UNLOCK(sc);
1520
1521	return;
1522}
1523
1524/*
1525 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1526 * pointers to the fragment pointers.
1527 */
1528static int
1529nge_encap(sc, m_head, txidx)
1530	struct nge_softc	*sc;
1531	struct mbuf		*m_head;
1532	u_int32_t		*txidx;
1533{
1534	struct nge_desc		*f = NULL;
1535	struct mbuf		*m;
1536	int			frag, cur, cnt = 0;
1537	struct m_tag		*mtag;
1538
1539	/*
1540 	 * Start packing the mbufs in this chain into
1541	 * the fragment pointers. Stop when we run out
1542 	 * of fragments or hit the end of the mbuf chain.
1543	 */
1544	m = m_head;
1545	cur = frag = *txidx;
1546
1547	for (m = m_head; m != NULL; m = m->m_next) {
1548		if (m->m_len != 0) {
1549			if ((NGE_TX_LIST_CNT -
1550			    (sc->nge_cdata.nge_tx_cnt + cnt)) < 2)
1551				return(ENOBUFS);
1552			f = &sc->nge_ldata->nge_tx_list[frag];
1553			f->nge_ctl = NGE_CMDSTS_MORE | m->m_len;
1554			f->nge_ptr = vtophys(mtod(m, vm_offset_t));
1555			if (cnt != 0)
1556				f->nge_ctl |= NGE_CMDSTS_OWN;
1557			cur = frag;
1558			NGE_INC(frag, NGE_TX_LIST_CNT);
1559			cnt++;
1560		}
1561	}
1562
1563	if (m != NULL)
1564		return(ENOBUFS);
1565
1566	sc->nge_ldata->nge_tx_list[*txidx].nge_extsts = 0;
1567	if (m_head->m_pkthdr.csum_flags) {
1568		if (m_head->m_pkthdr.csum_flags & CSUM_IP)
1569			sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |=
1570			    NGE_TXEXTSTS_IPCSUM;
1571		if (m_head->m_pkthdr.csum_flags & CSUM_TCP)
1572			sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |=
1573			    NGE_TXEXTSTS_TCPCSUM;
1574		if (m_head->m_pkthdr.csum_flags & CSUM_UDP)
1575			sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |=
1576			    NGE_TXEXTSTS_UDPCSUM;
1577	}
1578
1579	mtag = VLAN_OUTPUT_TAG(sc->nge_ifp, m_head);
1580	if (mtag != NULL) {
1581		sc->nge_ldata->nge_tx_list[cur].nge_extsts |=
1582		    (NGE_TXEXTSTS_VLANPKT|htons(VLAN_TAG_VALUE(mtag)));
1583	}
1584
1585	sc->nge_ldata->nge_tx_list[cur].nge_mbuf = m_head;
1586	sc->nge_ldata->nge_tx_list[cur].nge_ctl &= ~NGE_CMDSTS_MORE;
1587	sc->nge_ldata->nge_tx_list[*txidx].nge_ctl |= NGE_CMDSTS_OWN;
1588	sc->nge_cdata.nge_tx_cnt += cnt;
1589	*txidx = frag;
1590
1591	return(0);
1592}
1593
1594/*
1595 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1596 * to the mbuf data regions directly in the transmit lists. We also save a
1597 * copy of the pointers since the transmit list fragment pointers are
1598 * physical addresses.
1599 */
1600
1601static void
1602nge_start(ifp)
1603	struct ifnet		*ifp;
1604{
1605	struct nge_softc	*sc;
1606
1607	sc = ifp->if_softc;
1608	NGE_LOCK(sc);
1609	nge_start_locked(ifp);
1610	NGE_UNLOCK(sc);
1611}
1612
1613static void
1614nge_start_locked(ifp)
1615	struct ifnet		*ifp;
1616{
1617	struct nge_softc	*sc;
1618	struct mbuf		*m_head = NULL;
1619	u_int32_t		idx;
1620
1621	sc = ifp->if_softc;
1622
1623	if (!sc->nge_link)
1624		return;
1625
1626	idx = sc->nge_cdata.nge_tx_prod;
1627
1628	if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
1629		return;
1630
1631	while(sc->nge_ldata->nge_tx_list[idx].nge_mbuf == NULL) {
1632		IF_DEQUEUE(&ifp->if_snd, m_head);
1633		if (m_head == NULL)
1634			break;
1635
1636		if (nge_encap(sc, m_head, &idx)) {
1637			IF_PREPEND(&ifp->if_snd, m_head);
1638			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1639			break;
1640		}
1641
1642		/*
1643		 * If there's a BPF listener, bounce a copy of this frame
1644		 * to him.
1645		 */
1646		BPF_MTAP(ifp, m_head);
1647
1648	}
1649
1650	/* Transmit */
1651	sc->nge_cdata.nge_tx_prod = idx;
1652	NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_ENABLE);
1653
1654	/*
1655	 * Set a timeout in case the chip goes out to lunch.
1656	 */
1657	ifp->if_timer = 5;
1658
1659	return;
1660}
1661
1662static void
1663nge_init(xsc)
1664	void			*xsc;
1665{
1666	struct nge_softc	*sc = xsc;
1667
1668	NGE_LOCK(sc);
1669	nge_init_locked(sc);
1670	NGE_UNLOCK(sc);
1671}
1672
1673static void
1674nge_init_locked(sc)
1675	struct nge_softc	*sc;
1676{
1677	struct ifnet		*ifp = sc->nge_ifp;
1678	struct mii_data		*mii;
1679
1680	NGE_LOCK_ASSERT(sc);
1681
1682	if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1683		return;
1684
1685	/*
1686	 * Cancel pending I/O and free all RX/TX buffers.
1687	 */
1688	nge_stop(sc);
1689
1690	if (sc->nge_tbi) {
1691		mii = NULL;
1692	} else {
1693		mii = device_get_softc(sc->nge_miibus);
1694	}
1695
1696	/* Set MAC address */
1697	CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0);
1698	CSR_WRITE_4(sc, NGE_RXFILT_DATA,
1699	    ((u_int16_t *)IFP2ENADDR(sc->nge_ifp))[0]);
1700	CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR1);
1701	CSR_WRITE_4(sc, NGE_RXFILT_DATA,
1702	    ((u_int16_t *)IFP2ENADDR(sc->nge_ifp))[1]);
1703	CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR2);
1704	CSR_WRITE_4(sc, NGE_RXFILT_DATA,
1705	    ((u_int16_t *)IFP2ENADDR(sc->nge_ifp))[2]);
1706
1707	/* Init circular RX list. */
1708	if (nge_list_rx_init(sc) == ENOBUFS) {
1709		printf("nge%d: initialization failed: no "
1710			"memory for rx buffers\n", sc->nge_unit);
1711		nge_stop(sc);
1712		return;
1713	}
1714
1715	/*
1716	 * Init tx descriptors.
1717	 */
1718	nge_list_tx_init(sc);
1719
1720	/*
1721	 * For the NatSemi chip, we have to explicitly enable the
1722	 * reception of ARP frames, as well as turn on the 'perfect
1723	 * match' filter where we store the station address, otherwise
1724	 * we won't receive unicasts meant for this host.
1725	 */
1726	NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ARP);
1727	NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_PERFECT);
1728
1729	 /* If we want promiscuous mode, set the allframes bit. */
1730	if (ifp->if_flags & IFF_PROMISC) {
1731		NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS);
1732	} else {
1733		NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS);
1734	}
1735
1736	/*
1737	 * Set the capture broadcast bit to capture broadcast frames.
1738	 */
1739	if (ifp->if_flags & IFF_BROADCAST) {
1740		NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD);
1741	} else {
1742		NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD);
1743	}
1744
1745	/*
1746	 * Load the multicast filter.
1747	 */
1748	nge_setmulti(sc);
1749
1750	/* Turn the receive filter on */
1751	NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ENABLE);
1752
1753	/*
1754	 * Load the address of the RX and TX lists.
1755	 */
1756	CSR_WRITE_4(sc, NGE_RX_LISTPTR,
1757	    vtophys(&sc->nge_ldata->nge_rx_list[0]));
1758	CSR_WRITE_4(sc, NGE_TX_LISTPTR,
1759	    vtophys(&sc->nge_ldata->nge_tx_list[0]));
1760
1761	/* Set RX configuration */
1762	CSR_WRITE_4(sc, NGE_RX_CFG, NGE_RXCFG);
1763	/*
1764	 * Enable hardware checksum validation for all IPv4
1765	 * packets, do not reject packets with bad checksums.
1766	 */
1767	CSR_WRITE_4(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_IPCSUM_ENB);
1768
1769	/*
1770	 * Tell the chip to detect and strip VLAN tag info from
1771	 * received frames. The tag will be provided in the extsts
1772	 * field in the RX descriptors.
1773	 */
1774	NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL,
1775	    NGE_VIPRXCTL_TAG_DETECT_ENB|NGE_VIPRXCTL_TAG_STRIP_ENB);
1776
1777	/* Set TX configuration */
1778	CSR_WRITE_4(sc, NGE_TX_CFG, NGE_TXCFG);
1779
1780	/*
1781	 * Enable TX IPv4 checksumming on a per-packet basis.
1782	 */
1783	CSR_WRITE_4(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_CSUM_PER_PKT);
1784
1785	/*
1786	 * Tell the chip to insert VLAN tags on a per-packet basis as
1787	 * dictated by the code in the frame encapsulation routine.
1788	 */
1789	NGE_SETBIT(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_TAG_PER_PKT);
1790
1791	/* Set full/half duplex mode. */
1792	if (sc->nge_tbi) {
1793		if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
1794		    == IFM_FDX) {
1795			NGE_SETBIT(sc, NGE_TX_CFG,
1796			    (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1797			NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1798		} else {
1799			NGE_CLRBIT(sc, NGE_TX_CFG,
1800			    (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1801			NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1802		}
1803	} else {
1804		if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1805			NGE_SETBIT(sc, NGE_TX_CFG,
1806			    (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1807			NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1808		} else {
1809			NGE_CLRBIT(sc, NGE_TX_CFG,
1810			    (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1811			NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1812		}
1813	}
1814
1815	nge_tick_locked(sc);
1816
1817	/*
1818	 * Enable the delivery of PHY interrupts based on
1819	 * link/speed/duplex status changes. Also enable the
1820	 * extsts field in the DMA descriptors (needed for
1821	 * TCP/IP checksum offload on transmit).
1822	 */
1823	NGE_SETBIT(sc, NGE_CFG, NGE_CFG_PHYINTR_SPD|
1824	    NGE_CFG_PHYINTR_LNK|NGE_CFG_PHYINTR_DUP|NGE_CFG_EXTSTS_ENB);
1825
1826	/*
1827	 * Configure interrupt holdoff (moderation). We can
1828	 * have the chip delay interrupt delivery for a certain
1829	 * period. Units are in 100us, and the max setting
1830	 * is 25500us (0xFF x 100us). Default is a 100us holdoff.
1831	 */
1832	CSR_WRITE_4(sc, NGE_IHR, 0x01);
1833
1834	/*
1835	 * Enable interrupts.
1836	 */
1837	CSR_WRITE_4(sc, NGE_IMR, NGE_INTRS);
1838#ifdef DEVICE_POLLING
1839	/*
1840	 * ... only enable interrupts if we are not polling, make sure
1841	 * they are off otherwise.
1842	 */
1843	if (ifp->if_flags & IFF_POLLING)
1844		CSR_WRITE_4(sc, NGE_IER, 0);
1845	else
1846#endif /* DEVICE_POLLING */
1847	CSR_WRITE_4(sc, NGE_IER, 1);
1848
1849	/* Enable receiver and transmitter. */
1850	NGE_CLRBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE);
1851	NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
1852
1853	nge_ifmedia_upd(ifp);
1854
1855	ifp->if_drv_flags |= IFF_DRV_RUNNING;
1856	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1857
1858	return;
1859}
1860
1861/*
1862 * Set media options.
1863 */
1864static int
1865nge_ifmedia_upd(ifp)
1866	struct ifnet		*ifp;
1867{
1868	struct nge_softc	*sc;
1869	struct mii_data		*mii;
1870
1871	sc = ifp->if_softc;
1872
1873	if (sc->nge_tbi) {
1874		if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media)
1875		     == IFM_AUTO) {
1876			CSR_WRITE_4(sc, NGE_TBI_ANAR,
1877				CSR_READ_4(sc, NGE_TBI_ANAR)
1878					| NGE_TBIANAR_HDX | NGE_TBIANAR_FDX
1879					| NGE_TBIANAR_PS1 | NGE_TBIANAR_PS2);
1880			CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG
1881				| NGE_TBIBMCR_RESTART_ANEG);
1882			CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG);
1883		} else if ((sc->nge_ifmedia.ifm_cur->ifm_media
1884			    & IFM_GMASK) == IFM_FDX) {
1885			NGE_SETBIT(sc, NGE_TX_CFG,
1886			    (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1887			NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1888
1889			CSR_WRITE_4(sc, NGE_TBI_ANAR, 0);
1890			CSR_WRITE_4(sc, NGE_TBI_BMCR, 0);
1891		} else {
1892			NGE_CLRBIT(sc, NGE_TX_CFG,
1893			    (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1894			NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1895
1896			CSR_WRITE_4(sc, NGE_TBI_ANAR, 0);
1897			CSR_WRITE_4(sc, NGE_TBI_BMCR, 0);
1898		}
1899
1900		CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
1901			    & ~NGE_GPIO_GP3_OUT);
1902	} else {
1903		mii = device_get_softc(sc->nge_miibus);
1904		sc->nge_link = 0;
1905		if (mii->mii_instance) {
1906			struct mii_softc	*miisc;
1907			for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1908			    miisc = LIST_NEXT(miisc, mii_list))
1909				mii_phy_reset(miisc);
1910		}
1911		mii_mediachg(mii);
1912	}
1913
1914	return(0);
1915}
1916
1917/*
1918 * Report current media status.
1919 */
1920static void
1921nge_ifmedia_sts(ifp, ifmr)
1922	struct ifnet		*ifp;
1923	struct ifmediareq	*ifmr;
1924{
1925	struct nge_softc	*sc;
1926	struct mii_data		*mii;
1927
1928	sc = ifp->if_softc;
1929
1930	if (sc->nge_tbi) {
1931		ifmr->ifm_status = IFM_AVALID;
1932		ifmr->ifm_active = IFM_ETHER;
1933
1934		if (CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE) {
1935			ifmr->ifm_status |= IFM_ACTIVE;
1936		}
1937		if (CSR_READ_4(sc, NGE_TBI_BMCR) & NGE_TBIBMCR_LOOPBACK)
1938			ifmr->ifm_active |= IFM_LOOP;
1939		if (!CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE) {
1940			ifmr->ifm_active |= IFM_NONE;
1941			ifmr->ifm_status = 0;
1942			return;
1943		}
1944		ifmr->ifm_active |= IFM_1000_SX;
1945		if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media)
1946		    == IFM_AUTO) {
1947			ifmr->ifm_active |= IFM_AUTO;
1948			if (CSR_READ_4(sc, NGE_TBI_ANLPAR)
1949			    & NGE_TBIANAR_FDX) {
1950				ifmr->ifm_active |= IFM_FDX;
1951			}else if (CSR_READ_4(sc, NGE_TBI_ANLPAR)
1952				  & NGE_TBIANAR_HDX) {
1953				ifmr->ifm_active |= IFM_HDX;
1954			}
1955		} else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
1956			== IFM_FDX)
1957			ifmr->ifm_active |= IFM_FDX;
1958		else
1959			ifmr->ifm_active |= IFM_HDX;
1960
1961	} else {
1962		mii = device_get_softc(sc->nge_miibus);
1963		mii_pollstat(mii);
1964		ifmr->ifm_active = mii->mii_media_active;
1965		ifmr->ifm_status = mii->mii_media_status;
1966	}
1967
1968	return;
1969}
1970
1971static int
1972nge_ioctl(ifp, command, data)
1973	struct ifnet		*ifp;
1974	u_long			command;
1975	caddr_t			data;
1976{
1977	struct nge_softc	*sc = ifp->if_softc;
1978	struct ifreq		*ifr = (struct ifreq *) data;
1979	struct mii_data		*mii;
1980	int			error = 0;
1981
1982	switch(command) {
1983	case SIOCSIFMTU:
1984		if (ifr->ifr_mtu > NGE_JUMBO_MTU)
1985			error = EINVAL;
1986		else {
1987			ifp->if_mtu = ifr->ifr_mtu;
1988			/*
1989			 * Workaround: if the MTU is larger than
1990			 * 8152 (TX FIFO size minus 64 minus 18), turn off
1991			 * TX checksum offloading.
1992			 */
1993			if (ifr->ifr_mtu >= 8152) {
1994				ifp->if_capenable &= ~IFCAP_TXCSUM;
1995				ifp->if_hwassist = 0;
1996			} else {
1997				ifp->if_capenable |= IFCAP_TXCSUM;
1998				ifp->if_hwassist = NGE_CSUM_FEATURES;
1999			}
2000		}
2001		break;
2002	case SIOCSIFFLAGS:
2003		NGE_LOCK(sc);
2004		if (ifp->if_flags & IFF_UP) {
2005			if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
2006			    ifp->if_flags & IFF_PROMISC &&
2007			    !(sc->nge_if_flags & IFF_PROMISC)) {
2008				NGE_SETBIT(sc, NGE_RXFILT_CTL,
2009				    NGE_RXFILTCTL_ALLPHYS|
2010				    NGE_RXFILTCTL_ALLMULTI);
2011			} else if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
2012			    !(ifp->if_flags & IFF_PROMISC) &&
2013			    sc->nge_if_flags & IFF_PROMISC) {
2014				NGE_CLRBIT(sc, NGE_RXFILT_CTL,
2015				    NGE_RXFILTCTL_ALLPHYS);
2016				if (!(ifp->if_flags & IFF_ALLMULTI))
2017					NGE_CLRBIT(sc, NGE_RXFILT_CTL,
2018					    NGE_RXFILTCTL_ALLMULTI);
2019			} else {
2020				ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2021				nge_init_locked(sc);
2022			}
2023		} else {
2024			if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2025				nge_stop(sc);
2026		}
2027		sc->nge_if_flags = ifp->if_flags;
2028		NGE_UNLOCK(sc);
2029		error = 0;
2030		break;
2031	case SIOCADDMULTI:
2032	case SIOCDELMULTI:
2033		NGE_LOCK(sc);
2034		nge_setmulti(sc);
2035		NGE_UNLOCK(sc);
2036		error = 0;
2037		break;
2038	case SIOCGIFMEDIA:
2039	case SIOCSIFMEDIA:
2040		if (sc->nge_tbi) {
2041			error = ifmedia_ioctl(ifp, ifr, &sc->nge_ifmedia,
2042					      command);
2043		} else {
2044			mii = device_get_softc(sc->nge_miibus);
2045			error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
2046					      command);
2047		}
2048		break;
2049	case SIOCSIFCAP:
2050		ifp->if_capenable &= ~IFCAP_POLLING;
2051		ifp->if_capenable |= ifr->ifr_reqcap & IFCAP_POLLING;
2052		break;
2053	default:
2054		error = ether_ioctl(ifp, command, data);
2055		break;
2056	}
2057
2058	return(error);
2059}
2060
2061static void
2062nge_watchdog(ifp)
2063	struct ifnet		*ifp;
2064{
2065	struct nge_softc	*sc;
2066
2067	sc = ifp->if_softc;
2068
2069	ifp->if_oerrors++;
2070	printf("nge%d: watchdog timeout\n", sc->nge_unit);
2071
2072	NGE_LOCK(sc);
2073	nge_stop(sc);
2074	nge_reset(sc);
2075	ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2076	nge_init_locked(sc);
2077
2078	if (ifp->if_snd.ifq_head != NULL)
2079		nge_start_locked(ifp);
2080
2081	NGE_UNLOCK(sc);
2082
2083	return;
2084}
2085
2086/*
2087 * Stop the adapter and free any mbufs allocated to the
2088 * RX and TX lists.
2089 */
2090static void
2091nge_stop(sc)
2092	struct nge_softc	*sc;
2093{
2094	register int		i;
2095	struct ifnet		*ifp;
2096	struct mii_data		*mii;
2097
2098	NGE_LOCK_ASSERT(sc);
2099	ifp = sc->nge_ifp;
2100	ifp->if_timer = 0;
2101	if (sc->nge_tbi) {
2102		mii = NULL;
2103	} else {
2104		mii = device_get_softc(sc->nge_miibus);
2105	}
2106
2107	callout_stop(&sc->nge_stat_ch);
2108#ifdef DEVICE_POLLING
2109	ether_poll_deregister(ifp);
2110#endif
2111	CSR_WRITE_4(sc, NGE_IER, 0);
2112	CSR_WRITE_4(sc, NGE_IMR, 0);
2113	NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE);
2114	DELAY(1000);
2115	CSR_WRITE_4(sc, NGE_TX_LISTPTR, 0);
2116	CSR_WRITE_4(sc, NGE_RX_LISTPTR, 0);
2117
2118	if (!sc->nge_tbi)
2119		mii_down(mii);
2120
2121	sc->nge_link = 0;
2122
2123	/*
2124	 * Free data in the RX lists.
2125	 */
2126	for (i = 0; i < NGE_RX_LIST_CNT; i++) {
2127		if (sc->nge_ldata->nge_rx_list[i].nge_mbuf != NULL) {
2128			m_freem(sc->nge_ldata->nge_rx_list[i].nge_mbuf);
2129			sc->nge_ldata->nge_rx_list[i].nge_mbuf = NULL;
2130		}
2131	}
2132	bzero((char *)&sc->nge_ldata->nge_rx_list,
2133		sizeof(sc->nge_ldata->nge_rx_list));
2134
2135	/*
2136	 * Free the TX list buffers.
2137	 */
2138	for (i = 0; i < NGE_TX_LIST_CNT; i++) {
2139		if (sc->nge_ldata->nge_tx_list[i].nge_mbuf != NULL) {
2140			m_freem(sc->nge_ldata->nge_tx_list[i].nge_mbuf);
2141			sc->nge_ldata->nge_tx_list[i].nge_mbuf = NULL;
2142		}
2143	}
2144
2145	bzero((char *)&sc->nge_ldata->nge_tx_list,
2146		sizeof(sc->nge_ldata->nge_tx_list));
2147
2148	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2149
2150	return;
2151}
2152
2153/*
2154 * Stop all chip I/O so that the kernel's probe routines don't
2155 * get confused by errant DMAs when rebooting.
2156 */
2157static void
2158nge_shutdown(dev)
2159	device_t		dev;
2160{
2161	struct nge_softc	*sc;
2162
2163	sc = device_get_softc(dev);
2164
2165	NGE_LOCK(sc);
2166	nge_reset(sc);
2167	nge_stop(sc);
2168	NGE_UNLOCK(sc);
2169
2170	return;
2171}
2172