if_nge.c revision 108470
1/* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2000, 2001 4 * Bill Paul <wpaul@bsdi.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: head/sys/dev/nge/if_nge.c 108470 2002-12-30 21:18:15Z schweikh $ 34 */ 35 36/* 37 * National Semiconductor DP83820/DP83821 gigabit ethernet driver 38 * for FreeBSD. Datasheets are available from: 39 * 40 * http://www.national.com/ds/DP/DP83820.pdf 41 * http://www.national.com/ds/DP/DP83821.pdf 42 * 43 * These chips are used on several low cost gigabit ethernet NICs 44 * sold by D-Link, Addtron, SMC and Asante. Both parts are 45 * virtually the same, except the 83820 is a 64-bit/32-bit part, 46 * while the 83821 is 32-bit only. 47 * 48 * Many cards also use National gigE transceivers, such as the 49 * DP83891, DP83861 and DP83862 gigPHYTER parts. The DP83861 datasheet 50 * contains a full register description that applies to all of these 51 * components: 52 * 53 * http://www.national.com/ds/DP/DP83861.pdf 54 * 55 * Written by Bill Paul <wpaul@bsdi.com> 56 * BSDi Open Source Solutions 57 */ 58 59/* 60 * The NatSemi DP83820 and 83821 controllers are enhanced versions 61 * of the NatSemi MacPHYTER 10/100 devices. They support 10, 100 62 * and 1000Mbps speeds with 1000baseX (ten bit interface), MII and GMII 63 * ports. Other features include 8K TX FIFO and 32K RX FIFO, TCP/IP 64 * hardware checksum offload (IPv4 only), VLAN tagging and filtering, 65 * priority TX and RX queues, a 2048 bit multicast hash filter, 4 RX pattern 66 * matching buffers, one perfect address filter buffer and interrupt 67 * moderation. The 83820 supports both 64-bit and 32-bit addressing 68 * and data transfers: the 64-bit support can be toggled on or off 69 * via software. This affects the size of certain fields in the DMA 70 * descriptors. 71 * 72 * There are two bugs/misfeatures in the 83820/83821 that I have 73 * discovered so far: 74 * 75 * - Receive buffers must be aligned on 64-bit boundaries, which means 76 * you must resort to copying data in order to fix up the payload 77 * alignment. 78 * 79 * - In order to transmit jumbo frames larger than 8170 bytes, you have 80 * to turn off transmit checksum offloading, because the chip can't 81 * compute the checksum on an outgoing frame unless it fits entirely 82 * within the TX FIFO, which is only 8192 bytes in size. If you have 83 * TX checksum offload enabled and you transmit attempt to transmit a 84 * frame larger than 8170 bytes, the transmitter will wedge. 85 * 86 * To work around the latter problem, TX checksum offload is disabled 87 * if the user selects an MTU larger than 8152 (8170 - 18). 88 */ 89 90#include <sys/param.h> 91#include <sys/systm.h> 92#include <sys/sockio.h> 93#include <sys/mbuf.h> 94#include <sys/malloc.h> 95#include <sys/kernel.h> 96#include <sys/socket.h> 97 98#include <net/if.h> 99#include <net/if_arp.h> 100#include <net/ethernet.h> 101#include <net/if_dl.h> 102#include <net/if_media.h> 103#include <net/if_types.h> 104#include <net/if_vlan_var.h> 105 106#include <net/bpf.h> 107 108#include <vm/vm.h> /* for vtophys */ 109#include <vm/pmap.h> /* for vtophys */ 110#include <machine/clock.h> /* for DELAY */ 111#include <machine/bus_pio.h> 112#include <machine/bus_memio.h> 113#include <machine/bus.h> 114#include <machine/resource.h> 115#include <sys/bus.h> 116#include <sys/rman.h> 117 118#include <dev/mii/mii.h> 119#include <dev/mii/miivar.h> 120 121#include <pci/pcireg.h> 122#include <pci/pcivar.h> 123 124#define NGE_USEIOSPACE 125 126#include <dev/nge/if_ngereg.h> 127 128MODULE_DEPEND(nge, miibus, 1, 1, 1); 129 130/* "controller miibus0" required. See GENERIC if you get errors here. */ 131#include "miibus_if.h" 132 133#ifndef lint 134static const char rcsid[] = 135 "$FreeBSD: head/sys/dev/nge/if_nge.c 108470 2002-12-30 21:18:15Z schweikh $"; 136#endif 137 138#define NGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 139 140/* 141 * Various supported device vendors/types and their names. 142 */ 143static struct nge_type nge_devs[] = { 144 { NGE_VENDORID, NGE_DEVICEID, 145 "National Semiconductor Gigabit Ethernet" }, 146 { 0, 0, NULL } 147}; 148 149static int nge_probe(device_t); 150static int nge_attach(device_t); 151static int nge_detach(device_t); 152 153static int nge_alloc_jumbo_mem(struct nge_softc *); 154static void nge_free_jumbo_mem(struct nge_softc *); 155static void *nge_jalloc(struct nge_softc *); 156static void nge_jfree(void *, void *); 157 158static int nge_newbuf(struct nge_softc *, struct nge_desc *, struct mbuf *); 159static int nge_encap(struct nge_softc *, struct mbuf *, u_int32_t *); 160static void nge_rxeof(struct nge_softc *); 161static void nge_txeof(struct nge_softc *); 162static void nge_intr(void *); 163static void nge_tick(void *); 164static void nge_start(struct ifnet *); 165static int nge_ioctl(struct ifnet *, u_long, caddr_t); 166static void nge_init(void *); 167static void nge_stop(struct nge_softc *); 168static void nge_watchdog(struct ifnet *); 169static void nge_shutdown(device_t); 170static int nge_ifmedia_upd(struct ifnet *); 171static void nge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 172 173static void nge_delay(struct nge_softc *); 174static void nge_eeprom_idle(struct nge_softc *); 175static void nge_eeprom_putbyte(struct nge_softc *, int); 176static void nge_eeprom_getword(struct nge_softc *, int, u_int16_t *); 177static void nge_read_eeprom(struct nge_softc *, caddr_t, int, int, int); 178 179static void nge_mii_sync(struct nge_softc *); 180static void nge_mii_send(struct nge_softc *, u_int32_t, int); 181static int nge_mii_readreg(struct nge_softc *, struct nge_mii_frame *); 182static int nge_mii_writereg(struct nge_softc *, struct nge_mii_frame *); 183 184static int nge_miibus_readreg(device_t, int, int); 185static int nge_miibus_writereg(device_t, int, int, int); 186static void nge_miibus_statchg(device_t); 187 188static void nge_setmulti(struct nge_softc *); 189static u_int32_t nge_crc(struct nge_softc *, caddr_t); 190static void nge_reset(struct nge_softc *); 191static int nge_list_rx_init(struct nge_softc *); 192static int nge_list_tx_init(struct nge_softc *); 193 194#ifdef NGE_USEIOSPACE 195#define NGE_RES SYS_RES_IOPORT 196#define NGE_RID NGE_PCI_LOIO 197#else 198#define NGE_RES SYS_RES_MEMORY 199#define NGE_RID NGE_PCI_LOMEM 200#endif 201 202static device_method_t nge_methods[] = { 203 /* Device interface */ 204 DEVMETHOD(device_probe, nge_probe), 205 DEVMETHOD(device_attach, nge_attach), 206 DEVMETHOD(device_detach, nge_detach), 207 DEVMETHOD(device_shutdown, nge_shutdown), 208 209 /* bus interface */ 210 DEVMETHOD(bus_print_child, bus_generic_print_child), 211 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 212 213 /* MII interface */ 214 DEVMETHOD(miibus_readreg, nge_miibus_readreg), 215 DEVMETHOD(miibus_writereg, nge_miibus_writereg), 216 DEVMETHOD(miibus_statchg, nge_miibus_statchg), 217 218 { 0, 0 } 219}; 220 221static driver_t nge_driver = { 222 "nge", 223 nge_methods, 224 sizeof(struct nge_softc) 225}; 226 227static devclass_t nge_devclass; 228 229DRIVER_MODULE(if_nge, pci, nge_driver, nge_devclass, 0, 0); 230DRIVER_MODULE(miibus, nge, miibus_driver, miibus_devclass, 0, 0); 231 232#define NGE_SETBIT(sc, reg, x) \ 233 CSR_WRITE_4(sc, reg, \ 234 CSR_READ_4(sc, reg) | (x)) 235 236#define NGE_CLRBIT(sc, reg, x) \ 237 CSR_WRITE_4(sc, reg, \ 238 CSR_READ_4(sc, reg) & ~(x)) 239 240#define SIO_SET(x) \ 241 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x)) 242 243#define SIO_CLR(x) \ 244 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x)) 245 246static void 247nge_delay(sc) 248 struct nge_softc *sc; 249{ 250 int idx; 251 252 for (idx = (300 / 33) + 1; idx > 0; idx--) 253 CSR_READ_4(sc, NGE_CSR); 254 255 return; 256} 257 258static void 259nge_eeprom_idle(sc) 260 struct nge_softc *sc; 261{ 262 register int i; 263 264 SIO_SET(NGE_MEAR_EE_CSEL); 265 nge_delay(sc); 266 SIO_SET(NGE_MEAR_EE_CLK); 267 nge_delay(sc); 268 269 for (i = 0; i < 25; i++) { 270 SIO_CLR(NGE_MEAR_EE_CLK); 271 nge_delay(sc); 272 SIO_SET(NGE_MEAR_EE_CLK); 273 nge_delay(sc); 274 } 275 276 SIO_CLR(NGE_MEAR_EE_CLK); 277 nge_delay(sc); 278 SIO_CLR(NGE_MEAR_EE_CSEL); 279 nge_delay(sc); 280 CSR_WRITE_4(sc, NGE_MEAR, 0x00000000); 281 282 return; 283} 284 285/* 286 * Send a read command and address to the EEPROM, check for ACK. 287 */ 288static void 289nge_eeprom_putbyte(sc, addr) 290 struct nge_softc *sc; 291 int addr; 292{ 293 register int d, i; 294 295 d = addr | NGE_EECMD_READ; 296 297 /* 298 * Feed in each bit and stobe the clock. 299 */ 300 for (i = 0x400; i; i >>= 1) { 301 if (d & i) { 302 SIO_SET(NGE_MEAR_EE_DIN); 303 } else { 304 SIO_CLR(NGE_MEAR_EE_DIN); 305 } 306 nge_delay(sc); 307 SIO_SET(NGE_MEAR_EE_CLK); 308 nge_delay(sc); 309 SIO_CLR(NGE_MEAR_EE_CLK); 310 nge_delay(sc); 311 } 312 313 return; 314} 315 316/* 317 * Read a word of data stored in the EEPROM at address 'addr.' 318 */ 319static void 320nge_eeprom_getword(sc, addr, dest) 321 struct nge_softc *sc; 322 int addr; 323 u_int16_t *dest; 324{ 325 register int i; 326 u_int16_t word = 0; 327 328 /* Force EEPROM to idle state. */ 329 nge_eeprom_idle(sc); 330 331 /* Enter EEPROM access mode. */ 332 nge_delay(sc); 333 SIO_CLR(NGE_MEAR_EE_CLK); 334 nge_delay(sc); 335 SIO_SET(NGE_MEAR_EE_CSEL); 336 nge_delay(sc); 337 338 /* 339 * Send address of word we want to read. 340 */ 341 nge_eeprom_putbyte(sc, addr); 342 343 /* 344 * Start reading bits from EEPROM. 345 */ 346 for (i = 0x8000; i; i >>= 1) { 347 SIO_SET(NGE_MEAR_EE_CLK); 348 nge_delay(sc); 349 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT) 350 word |= i; 351 nge_delay(sc); 352 SIO_CLR(NGE_MEAR_EE_CLK); 353 nge_delay(sc); 354 } 355 356 /* Turn off EEPROM access mode. */ 357 nge_eeprom_idle(sc); 358 359 *dest = word; 360 361 return; 362} 363 364/* 365 * Read a sequence of words from the EEPROM. 366 */ 367static void 368nge_read_eeprom(sc, dest, off, cnt, swap) 369 struct nge_softc *sc; 370 caddr_t dest; 371 int off; 372 int cnt; 373 int swap; 374{ 375 int i; 376 u_int16_t word = 0, *ptr; 377 378 for (i = 0; i < cnt; i++) { 379 nge_eeprom_getword(sc, off + i, &word); 380 ptr = (u_int16_t *)(dest + (i * 2)); 381 if (swap) 382 *ptr = ntohs(word); 383 else 384 *ptr = word; 385 } 386 387 return; 388} 389 390/* 391 * Sync the PHYs by setting data bit and strobing the clock 32 times. 392 */ 393static void 394nge_mii_sync(sc) 395 struct nge_softc *sc; 396{ 397 register int i; 398 399 SIO_SET(NGE_MEAR_MII_DIR|NGE_MEAR_MII_DATA); 400 401 for (i = 0; i < 32; i++) { 402 SIO_SET(NGE_MEAR_MII_CLK); 403 DELAY(1); 404 SIO_CLR(NGE_MEAR_MII_CLK); 405 DELAY(1); 406 } 407 408 return; 409} 410 411/* 412 * Clock a series of bits through the MII. 413 */ 414static void 415nge_mii_send(sc, bits, cnt) 416 struct nge_softc *sc; 417 u_int32_t bits; 418 int cnt; 419{ 420 int i; 421 422 SIO_CLR(NGE_MEAR_MII_CLK); 423 424 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 425 if (bits & i) { 426 SIO_SET(NGE_MEAR_MII_DATA); 427 } else { 428 SIO_CLR(NGE_MEAR_MII_DATA); 429 } 430 DELAY(1); 431 SIO_CLR(NGE_MEAR_MII_CLK); 432 DELAY(1); 433 SIO_SET(NGE_MEAR_MII_CLK); 434 } 435} 436 437/* 438 * Read an PHY register through the MII. 439 */ 440static int 441nge_mii_readreg(sc, frame) 442 struct nge_softc *sc; 443 struct nge_mii_frame *frame; 444 445{ 446 int i, ack, s; 447 448 s = splimp(); 449 450 /* 451 * Set up frame for RX. 452 */ 453 frame->mii_stdelim = NGE_MII_STARTDELIM; 454 frame->mii_opcode = NGE_MII_READOP; 455 frame->mii_turnaround = 0; 456 frame->mii_data = 0; 457 458 CSR_WRITE_4(sc, NGE_MEAR, 0); 459 460 /* 461 * Turn on data xmit. 462 */ 463 SIO_SET(NGE_MEAR_MII_DIR); 464 465 nge_mii_sync(sc); 466 467 /* 468 * Send command/address info. 469 */ 470 nge_mii_send(sc, frame->mii_stdelim, 2); 471 nge_mii_send(sc, frame->mii_opcode, 2); 472 nge_mii_send(sc, frame->mii_phyaddr, 5); 473 nge_mii_send(sc, frame->mii_regaddr, 5); 474 475 /* Idle bit */ 476 SIO_CLR((NGE_MEAR_MII_CLK|NGE_MEAR_MII_DATA)); 477 DELAY(1); 478 SIO_SET(NGE_MEAR_MII_CLK); 479 DELAY(1); 480 481 /* Turn off xmit. */ 482 SIO_CLR(NGE_MEAR_MII_DIR); 483 /* Check for ack */ 484 SIO_CLR(NGE_MEAR_MII_CLK); 485 DELAY(1); 486 SIO_SET(NGE_MEAR_MII_CLK); 487 DELAY(1); 488 ack = CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA; 489 490 /* 491 * Now try reading data bits. If the ack failed, we still 492 * need to clock through 16 cycles to keep the PHY(s) in sync. 493 */ 494 if (ack) { 495 for(i = 0; i < 16; i++) { 496 SIO_CLR(NGE_MEAR_MII_CLK); 497 DELAY(1); 498 SIO_SET(NGE_MEAR_MII_CLK); 499 DELAY(1); 500 } 501 goto fail; 502 } 503 504 for (i = 0x8000; i; i >>= 1) { 505 SIO_CLR(NGE_MEAR_MII_CLK); 506 DELAY(1); 507 if (!ack) { 508 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA) 509 frame->mii_data |= i; 510 DELAY(1); 511 } 512 SIO_SET(NGE_MEAR_MII_CLK); 513 DELAY(1); 514 } 515 516fail: 517 518 SIO_CLR(NGE_MEAR_MII_CLK); 519 DELAY(1); 520 SIO_SET(NGE_MEAR_MII_CLK); 521 DELAY(1); 522 523 splx(s); 524 525 if (ack) 526 return(1); 527 return(0); 528} 529 530/* 531 * Write to a PHY register through the MII. 532 */ 533static int 534nge_mii_writereg(sc, frame) 535 struct nge_softc *sc; 536 struct nge_mii_frame *frame; 537 538{ 539 int s; 540 541 s = splimp(); 542 /* 543 * Set up frame for TX. 544 */ 545 546 frame->mii_stdelim = NGE_MII_STARTDELIM; 547 frame->mii_opcode = NGE_MII_WRITEOP; 548 frame->mii_turnaround = NGE_MII_TURNAROUND; 549 550 /* 551 * Turn on data output. 552 */ 553 SIO_SET(NGE_MEAR_MII_DIR); 554 555 nge_mii_sync(sc); 556 557 nge_mii_send(sc, frame->mii_stdelim, 2); 558 nge_mii_send(sc, frame->mii_opcode, 2); 559 nge_mii_send(sc, frame->mii_phyaddr, 5); 560 nge_mii_send(sc, frame->mii_regaddr, 5); 561 nge_mii_send(sc, frame->mii_turnaround, 2); 562 nge_mii_send(sc, frame->mii_data, 16); 563 564 /* Idle bit. */ 565 SIO_SET(NGE_MEAR_MII_CLK); 566 DELAY(1); 567 SIO_CLR(NGE_MEAR_MII_CLK); 568 DELAY(1); 569 570 /* 571 * Turn off xmit. 572 */ 573 SIO_CLR(NGE_MEAR_MII_DIR); 574 575 splx(s); 576 577 return(0); 578} 579 580static int 581nge_miibus_readreg(dev, phy, reg) 582 device_t dev; 583 int phy, reg; 584{ 585 struct nge_softc *sc; 586 struct nge_mii_frame frame; 587 588 sc = device_get_softc(dev); 589 590 bzero((char *)&frame, sizeof(frame)); 591 592 frame.mii_phyaddr = phy; 593 frame.mii_regaddr = reg; 594 nge_mii_readreg(sc, &frame); 595 596 return(frame.mii_data); 597} 598 599static int 600nge_miibus_writereg(dev, phy, reg, data) 601 device_t dev; 602 int phy, reg, data; 603{ 604 struct nge_softc *sc; 605 struct nge_mii_frame frame; 606 607 sc = device_get_softc(dev); 608 609 bzero((char *)&frame, sizeof(frame)); 610 611 frame.mii_phyaddr = phy; 612 frame.mii_regaddr = reg; 613 frame.mii_data = data; 614 nge_mii_writereg(sc, &frame); 615 616 return(0); 617} 618 619static void 620nge_miibus_statchg(dev) 621 device_t dev; 622{ 623 int status; 624 struct nge_softc *sc; 625 struct mii_data *mii; 626 627 sc = device_get_softc(dev); 628 if (sc->nge_tbi) { 629 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) 630 == IFM_AUTO) { 631 status = CSR_READ_4(sc, NGE_TBI_ANLPAR); 632 if (status == 0 || status & NGE_TBIANAR_FDX) { 633 NGE_SETBIT(sc, NGE_TX_CFG, 634 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 635 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 636 } else { 637 NGE_CLRBIT(sc, NGE_TX_CFG, 638 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 639 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 640 } 641 642 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) 643 != IFM_FDX) { 644 NGE_CLRBIT(sc, NGE_TX_CFG, 645 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 646 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 647 } else { 648 NGE_SETBIT(sc, NGE_TX_CFG, 649 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 650 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 651 } 652 } else { 653 mii = device_get_softc(sc->nge_miibus); 654 655 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 656 NGE_SETBIT(sc, NGE_TX_CFG, 657 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 658 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 659 } else { 660 NGE_CLRBIT(sc, NGE_TX_CFG, 661 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 662 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 663 } 664 665 /* If we have a 1000Mbps link, set the mode_1000 bit. */ 666 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 667 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) { 668 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_MODE_1000); 669 } else { 670 NGE_CLRBIT(sc, NGE_CFG, NGE_CFG_MODE_1000); 671 } 672 } 673 return; 674} 675 676static u_int32_t 677nge_crc(sc, addr) 678 struct nge_softc *sc; 679 caddr_t addr; 680{ 681 u_int32_t crc, carry; 682 int i, j; 683 u_int8_t c; 684 685 /* Compute CRC for the address value. */ 686 crc = 0xFFFFFFFF; /* initial value */ 687 688 for (i = 0; i < 6; i++) { 689 c = *(addr + i); 690 for (j = 0; j < 8; j++) { 691 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 692 crc <<= 1; 693 c >>= 1; 694 if (carry) 695 crc = (crc ^ 0x04c11db6) | carry; 696 } 697 } 698 699 /* 700 * return the filter bit position 701 */ 702 703 return((crc >> 21) & 0x00000FFF); 704} 705 706static void 707nge_setmulti(sc) 708 struct nge_softc *sc; 709{ 710 struct ifnet *ifp; 711 struct ifmultiaddr *ifma; 712 u_int32_t h = 0, i, filtsave; 713 int bit, index; 714 715 ifp = &sc->arpcom.ac_if; 716 717 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 718 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 719 NGE_RXFILTCTL_MCHASH|NGE_RXFILTCTL_UCHASH); 720 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLMULTI); 721 return; 722 } 723 724 /* 725 * We have to explicitly enable the multicast hash table 726 * on the NatSemi chip if we want to use it, which we do. 727 * We also have to tell it that we don't want to use the 728 * hash table for matching unicast addresses. 729 */ 730 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_MCHASH); 731 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 732 NGE_RXFILTCTL_ALLMULTI|NGE_RXFILTCTL_UCHASH); 733 734 filtsave = CSR_READ_4(sc, NGE_RXFILT_CTL); 735 736 /* first, zot all the existing hash bits */ 737 for (i = 0; i < NGE_MCAST_FILTER_LEN; i += 2) { 738 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + i); 739 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 0); 740 } 741 742 /* 743 * From the 11 bits returned by the crc routine, the top 7 744 * bits represent the 16-bit word in the mcast hash table 745 * that needs to be updated, and the lower 4 bits represent 746 * which bit within that byte needs to be set. 747 */ 748 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 749 if (ifma->ifma_addr->sa_family != AF_LINK) 750 continue; 751 h = nge_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 752 index = (h >> 4) & 0x7F; 753 bit = h & 0xF; 754 CSR_WRITE_4(sc, NGE_RXFILT_CTL, 755 NGE_FILTADDR_MCAST_LO + (index * 2)); 756 NGE_SETBIT(sc, NGE_RXFILT_DATA, (1 << bit)); 757 } 758 759 CSR_WRITE_4(sc, NGE_RXFILT_CTL, filtsave); 760 761 return; 762} 763 764static void 765nge_reset(sc) 766 struct nge_softc *sc; 767{ 768 register int i; 769 770 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RESET); 771 772 for (i = 0; i < NGE_TIMEOUT; i++) { 773 if (!(CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET)) 774 break; 775 } 776 777 if (i == NGE_TIMEOUT) 778 printf("nge%d: reset never completed\n", sc->nge_unit); 779 780 /* Wait a little while for the chip to get its brains in order. */ 781 DELAY(1000); 782 783 /* 784 * If this is a NetSemi chip, make sure to clear 785 * PME mode. 786 */ 787 CSR_WRITE_4(sc, NGE_CLKRUN, NGE_CLKRUN_PMESTS); 788 CSR_WRITE_4(sc, NGE_CLKRUN, 0); 789 790 return; 791} 792 793/* 794 * Probe for a NatSemi chip. Check the PCI vendor and device 795 * IDs against our list and return a device name if we find a match. 796 */ 797static int 798nge_probe(dev) 799 device_t dev; 800{ 801 struct nge_type *t; 802 803 t = nge_devs; 804 805 while(t->nge_name != NULL) { 806 if ((pci_get_vendor(dev) == t->nge_vid) && 807 (pci_get_device(dev) == t->nge_did)) { 808 device_set_desc(dev, t->nge_name); 809 return(0); 810 } 811 t++; 812 } 813 814 return(ENXIO); 815} 816 817/* 818 * Attach the interface. Allocate softc structures, do ifmedia 819 * setup and ethernet/BPF attach. 820 */ 821static int 822nge_attach(dev) 823 device_t dev; 824{ 825 int s; 826 u_char eaddr[ETHER_ADDR_LEN]; 827 u_int32_t command; 828 struct nge_softc *sc; 829 struct ifnet *ifp; 830 int unit, error = 0, rid; 831 const char *sep = ""; 832 833 s = splimp(); 834 835 sc = device_get_softc(dev); 836 unit = device_get_unit(dev); 837 bzero(sc, sizeof(struct nge_softc)); 838 839 mtx_init(&sc->nge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 840 MTX_DEF | MTX_RECURSE); 841 842 /* 843 * Handle power management nonsense. 844 */ 845 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 846 u_int32_t iobase, membase, irq; 847 848 /* Save important PCI config data. */ 849 iobase = pci_read_config(dev, NGE_PCI_LOIO, 4); 850 membase = pci_read_config(dev, NGE_PCI_LOMEM, 4); 851 irq = pci_read_config(dev, NGE_PCI_INTLINE, 4); 852 853 /* Reset the power state. */ 854 printf("nge%d: chip is in D%d power mode " 855 "-- setting to D0\n", unit, 856 pci_get_powerstate(dev)); 857 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 858 859 /* Restore PCI config data. */ 860 pci_write_config(dev, NGE_PCI_LOIO, iobase, 4); 861 pci_write_config(dev, NGE_PCI_LOMEM, membase, 4); 862 pci_write_config(dev, NGE_PCI_INTLINE, irq, 4); 863 } 864 865 /* 866 * Map control/status registers. 867 */ 868 pci_enable_busmaster(dev); 869 pci_enable_io(dev, SYS_RES_IOPORT); 870 pci_enable_io(dev, SYS_RES_MEMORY); 871 command = pci_read_config(dev, PCIR_COMMAND, 4); 872 873#ifdef NGE_USEIOSPACE 874 if (!(command & PCIM_CMD_PORTEN)) { 875 printf("nge%d: failed to enable I/O ports!\n", unit); 876 error = ENXIO;; 877 goto fail; 878 } 879#else 880 if (!(command & PCIM_CMD_MEMEN)) { 881 printf("nge%d: failed to enable memory mapping!\n", unit); 882 error = ENXIO;; 883 goto fail; 884 } 885#endif 886 887 rid = NGE_RID; 888 sc->nge_res = bus_alloc_resource(dev, NGE_RES, &rid, 889 0, ~0, 1, RF_ACTIVE); 890 891 if (sc->nge_res == NULL) { 892 printf("nge%d: couldn't map ports/memory\n", unit); 893 error = ENXIO; 894 goto fail; 895 } 896 897 sc->nge_btag = rman_get_bustag(sc->nge_res); 898 sc->nge_bhandle = rman_get_bushandle(sc->nge_res); 899 900 /* Allocate interrupt */ 901 rid = 0; 902 sc->nge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 903 RF_SHAREABLE | RF_ACTIVE); 904 905 if (sc->nge_irq == NULL) { 906 printf("nge%d: couldn't map interrupt\n", unit); 907 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 908 error = ENXIO; 909 goto fail; 910 } 911 912 error = bus_setup_intr(dev, sc->nge_irq, INTR_TYPE_NET, 913 nge_intr, sc, &sc->nge_intrhand); 914 915 if (error) { 916 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 917 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 918 printf("nge%d: couldn't set up irq\n", unit); 919 goto fail; 920 } 921 922 /* Reset the adapter. */ 923 nge_reset(sc); 924 925 /* 926 * Get station address from the EEPROM. 927 */ 928 nge_read_eeprom(sc, (caddr_t)&eaddr[4], NGE_EE_NODEADDR, 1, 0); 929 nge_read_eeprom(sc, (caddr_t)&eaddr[2], NGE_EE_NODEADDR + 1, 1, 0); 930 nge_read_eeprom(sc, (caddr_t)&eaddr[0], NGE_EE_NODEADDR + 2, 1, 0); 931 932 /* 933 * A NatSemi chip was detected. Inform the world. 934 */ 935 printf("nge%d: Ethernet address: %6D\n", unit, eaddr, ":"); 936 937 sc->nge_unit = unit; 938 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 939 940 sc->nge_ldata = contigmalloc(sizeof(struct nge_list_data), M_DEVBUF, 941 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 942 943 if (sc->nge_ldata == NULL) { 944 printf("nge%d: no memory for list buffers!\n", unit); 945 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 946 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 947 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 948 error = ENXIO; 949 goto fail; 950 } 951 bzero(sc->nge_ldata, sizeof(struct nge_list_data)); 952 953 /* Try to allocate memory for jumbo buffers. */ 954 if (nge_alloc_jumbo_mem(sc)) { 955 printf("nge%d: jumbo buffer allocation failed\n", 956 sc->nge_unit); 957 contigfree(sc->nge_ldata, 958 sizeof(struct nge_list_data), M_DEVBUF); 959 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 960 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 961 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 962 error = ENXIO; 963 goto fail; 964 } 965 966 ifp = &sc->arpcom.ac_if; 967 ifp->if_softc = sc; 968 ifp->if_unit = unit; 969 ifp->if_name = "nge"; 970 ifp->if_mtu = ETHERMTU; 971 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 972 ifp->if_ioctl = nge_ioctl; 973 ifp->if_output = ether_output; 974 ifp->if_start = nge_start; 975 ifp->if_watchdog = nge_watchdog; 976 ifp->if_init = nge_init; 977 ifp->if_baudrate = 1000000000; 978 ifp->if_snd.ifq_maxlen = NGE_TX_LIST_CNT - 1; 979 ifp->if_hwassist = NGE_CSUM_FEATURES; 980 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING; 981 ifp->if_capenable = ifp->if_capabilities; 982 983 /* 984 * Do MII setup. 985 */ 986 if (mii_phy_probe(dev, &sc->nge_miibus, 987 nge_ifmedia_upd, nge_ifmedia_sts)) { 988 if (CSR_READ_4(sc, NGE_CFG) & NGE_CFG_TBI_EN) { 989 sc->nge_tbi = 1; 990 device_printf(dev, "Using TBI\n"); 991 992 sc->nge_miibus = dev; 993 994 ifmedia_init(&sc->nge_ifmedia, 0, nge_ifmedia_upd, 995 nge_ifmedia_sts); 996#define ADD(m, c) ifmedia_add(&sc->nge_ifmedia, (m), (c), NULL) 997#define PRINT(s) printf("%s%s", sep, s); sep = ", " 998 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, 0), 0); 999 device_printf(dev, " "); 1000 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, 0, 0), 0); 1001 PRINT("1000baseSX"); 1002 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, 0),0); 1003 PRINT("1000baseSX-FDX"); 1004 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0), 0); 1005 PRINT("auto"); 1006 1007 printf("\n"); 1008#undef ADD 1009#undef PRINT 1010 ifmedia_set(&sc->nge_ifmedia, 1011 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0)); 1012 1013 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 1014 | NGE_GPIO_GP4_OUT 1015 | NGE_GPIO_GP1_OUTENB | NGE_GPIO_GP2_OUTENB 1016 | NGE_GPIO_GP3_OUTENB 1017 | NGE_GPIO_GP3_IN | NGE_GPIO_GP4_IN); 1018 1019 } else { 1020 printf("nge%d: MII without any PHY!\n", sc->nge_unit); 1021 nge_free_jumbo_mem(sc); 1022 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 1023 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 1024 bus_release_resource(dev, NGE_RES, NGE_RID, 1025 sc->nge_res); 1026 error = ENXIO; 1027 goto fail; 1028 } 1029 } 1030 1031 /* 1032 * Call MI attach routine. 1033 */ 1034 ether_ifattach(ifp, eaddr); 1035 callout_handle_init(&sc->nge_stat_ch); 1036 1037fail: 1038 1039 splx(s); 1040 mtx_destroy(&sc->nge_mtx); 1041 return(error); 1042} 1043 1044static int 1045nge_detach(dev) 1046 device_t dev; 1047{ 1048 struct nge_softc *sc; 1049 struct ifnet *ifp; 1050 int s; 1051 1052 s = splimp(); 1053 1054 sc = device_get_softc(dev); 1055 ifp = &sc->arpcom.ac_if; 1056 1057 nge_reset(sc); 1058 nge_stop(sc); 1059 ether_ifdetach(ifp); 1060 1061 bus_generic_detach(dev); 1062 if (!sc->nge_tbi) { 1063 device_delete_child(dev, sc->nge_miibus); 1064 } 1065 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 1066 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 1067 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 1068 1069 contigfree(sc->nge_ldata, sizeof(struct nge_list_data), M_DEVBUF); 1070 nge_free_jumbo_mem(sc); 1071 1072 splx(s); 1073 mtx_destroy(&sc->nge_mtx); 1074 1075 return(0); 1076} 1077 1078/* 1079 * Initialize the transmit descriptors. 1080 */ 1081static int 1082nge_list_tx_init(sc) 1083 struct nge_softc *sc; 1084{ 1085 struct nge_list_data *ld; 1086 struct nge_ring_data *cd; 1087 int i; 1088 1089 cd = &sc->nge_cdata; 1090 ld = sc->nge_ldata; 1091 1092 for (i = 0; i < NGE_TX_LIST_CNT; i++) { 1093 if (i == (NGE_TX_LIST_CNT - 1)) { 1094 ld->nge_tx_list[i].nge_nextdesc = 1095 &ld->nge_tx_list[0]; 1096 ld->nge_tx_list[i].nge_next = 1097 vtophys(&ld->nge_tx_list[0]); 1098 } else { 1099 ld->nge_tx_list[i].nge_nextdesc = 1100 &ld->nge_tx_list[i + 1]; 1101 ld->nge_tx_list[i].nge_next = 1102 vtophys(&ld->nge_tx_list[i + 1]); 1103 } 1104 ld->nge_tx_list[i].nge_mbuf = NULL; 1105 ld->nge_tx_list[i].nge_ptr = 0; 1106 ld->nge_tx_list[i].nge_ctl = 0; 1107 } 1108 1109 cd->nge_tx_prod = cd->nge_tx_cons = cd->nge_tx_cnt = 0; 1110 1111 return(0); 1112} 1113 1114 1115/* 1116 * Initialize the RX descriptors and allocate mbufs for them. Note that 1117 * we arrange the descriptors in a closed ring, so that the last descriptor 1118 * points back to the first. 1119 */ 1120static int 1121nge_list_rx_init(sc) 1122 struct nge_softc *sc; 1123{ 1124 struct nge_list_data *ld; 1125 struct nge_ring_data *cd; 1126 int i; 1127 1128 ld = sc->nge_ldata; 1129 cd = &sc->nge_cdata; 1130 1131 for (i = 0; i < NGE_RX_LIST_CNT; i++) { 1132 if (nge_newbuf(sc, &ld->nge_rx_list[i], NULL) == ENOBUFS) 1133 return(ENOBUFS); 1134 if (i == (NGE_RX_LIST_CNT - 1)) { 1135 ld->nge_rx_list[i].nge_nextdesc = 1136 &ld->nge_rx_list[0]; 1137 ld->nge_rx_list[i].nge_next = 1138 vtophys(&ld->nge_rx_list[0]); 1139 } else { 1140 ld->nge_rx_list[i].nge_nextdesc = 1141 &ld->nge_rx_list[i + 1]; 1142 ld->nge_rx_list[i].nge_next = 1143 vtophys(&ld->nge_rx_list[i + 1]); 1144 } 1145 } 1146 1147 cd->nge_rx_prod = 0; 1148 1149 return(0); 1150} 1151 1152/* 1153 * Initialize an RX descriptor and attach an MBUF cluster. 1154 */ 1155static int 1156nge_newbuf(sc, c, m) 1157 struct nge_softc *sc; 1158 struct nge_desc *c; 1159 struct mbuf *m; 1160{ 1161 struct mbuf *m_new = NULL; 1162 caddr_t *buf = NULL; 1163 1164 if (m == NULL) { 1165 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1166 if (m_new == NULL) { 1167 printf("nge%d: no memory for rx list " 1168 "-- packet dropped!\n", sc->nge_unit); 1169 return(ENOBUFS); 1170 } 1171 1172 /* Allocate the jumbo buffer */ 1173 buf = nge_jalloc(sc); 1174 if (buf == NULL) { 1175#ifdef NGE_VERBOSE 1176 printf("nge%d: jumbo allocation failed " 1177 "-- packet dropped!\n", sc->nge_unit); 1178#endif 1179 m_freem(m_new); 1180 return(ENOBUFS); 1181 } 1182 /* Attach the buffer to the mbuf */ 1183 m_new->m_data = (void *)buf; 1184 m_new->m_len = m_new->m_pkthdr.len = NGE_JUMBO_FRAMELEN; 1185 MEXTADD(m_new, buf, NGE_JUMBO_FRAMELEN, nge_jfree, 1186 (struct nge_softc *)sc, 0, EXT_NET_DRV); 1187 } else { 1188 m_new = m; 1189 m_new->m_len = m_new->m_pkthdr.len = NGE_JUMBO_FRAMELEN; 1190 m_new->m_data = m_new->m_ext.ext_buf; 1191 } 1192 1193 m_adj(m_new, sizeof(u_int64_t)); 1194 1195 c->nge_mbuf = m_new; 1196 c->nge_ptr = vtophys(mtod(m_new, caddr_t)); 1197 c->nge_ctl = m_new->m_len; 1198 c->nge_extsts = 0; 1199 1200 return(0); 1201} 1202 1203static int 1204nge_alloc_jumbo_mem(sc) 1205 struct nge_softc *sc; 1206{ 1207 caddr_t ptr; 1208 register int i; 1209 struct nge_jpool_entry *entry; 1210 1211 /* Grab a big chunk o' storage. */ 1212 sc->nge_cdata.nge_jumbo_buf = contigmalloc(NGE_JMEM, M_DEVBUF, 1213 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1214 1215 if (sc->nge_cdata.nge_jumbo_buf == NULL) { 1216 printf("nge%d: no memory for jumbo buffers!\n", sc->nge_unit); 1217 return(ENOBUFS); 1218 } 1219 1220 SLIST_INIT(&sc->nge_jfree_listhead); 1221 SLIST_INIT(&sc->nge_jinuse_listhead); 1222 1223 /* 1224 * Now divide it up into 9K pieces and save the addresses 1225 * in an array. 1226 */ 1227 ptr = sc->nge_cdata.nge_jumbo_buf; 1228 for (i = 0; i < NGE_JSLOTS; i++) { 1229 sc->nge_cdata.nge_jslots[i] = ptr; 1230 ptr += NGE_JLEN; 1231 entry = malloc(sizeof(struct nge_jpool_entry), 1232 M_DEVBUF, M_NOWAIT); 1233 if (entry == NULL) { 1234 printf("nge%d: no memory for jumbo " 1235 "buffer queue!\n", sc->nge_unit); 1236 return(ENOBUFS); 1237 } 1238 entry->slot = i; 1239 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead, 1240 entry, jpool_entries); 1241 } 1242 1243 return(0); 1244} 1245 1246static void 1247nge_free_jumbo_mem(sc) 1248 struct nge_softc *sc; 1249{ 1250 register int i; 1251 struct nge_jpool_entry *entry; 1252 1253 for (i = 0; i < NGE_JSLOTS; i++) { 1254 entry = SLIST_FIRST(&sc->nge_jfree_listhead); 1255 SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jpool_entries); 1256 free(entry, M_DEVBUF); 1257 } 1258 1259 contigfree(sc->nge_cdata.nge_jumbo_buf, NGE_JMEM, M_DEVBUF); 1260 1261 return; 1262} 1263 1264/* 1265 * Allocate a jumbo buffer. 1266 */ 1267static void * 1268nge_jalloc(sc) 1269 struct nge_softc *sc; 1270{ 1271 struct nge_jpool_entry *entry; 1272 1273 entry = SLIST_FIRST(&sc->nge_jfree_listhead); 1274 1275 if (entry == NULL) { 1276#ifdef NGE_VERBOSE 1277 printf("nge%d: no free jumbo buffers\n", sc->nge_unit); 1278#endif 1279 return(NULL); 1280 } 1281 1282 SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jpool_entries); 1283 SLIST_INSERT_HEAD(&sc->nge_jinuse_listhead, entry, jpool_entries); 1284 return(sc->nge_cdata.nge_jslots[entry->slot]); 1285} 1286 1287/* 1288 * Release a jumbo buffer. 1289 */ 1290static void 1291nge_jfree(buf, args) 1292 void *buf; 1293 void *args; 1294{ 1295 struct nge_softc *sc; 1296 int i; 1297 struct nge_jpool_entry *entry; 1298 1299 /* Extract the softc struct pointer. */ 1300 sc = args; 1301 1302 if (sc == NULL) 1303 panic("nge_jfree: can't find softc pointer!"); 1304 1305 /* calculate the slot this buffer belongs to */ 1306 i = ((vm_offset_t)buf 1307 - (vm_offset_t)sc->nge_cdata.nge_jumbo_buf) / NGE_JLEN; 1308 1309 if ((i < 0) || (i >= NGE_JSLOTS)) 1310 panic("nge_jfree: asked to free buffer that we don't manage!"); 1311 1312 entry = SLIST_FIRST(&sc->nge_jinuse_listhead); 1313 if (entry == NULL) 1314 panic("nge_jfree: buffer not in use!"); 1315 entry->slot = i; 1316 SLIST_REMOVE_HEAD(&sc->nge_jinuse_listhead, jpool_entries); 1317 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead, entry, jpool_entries); 1318 1319 return; 1320} 1321/* 1322 * A frame has been uploaded: pass the resulting mbuf chain up to 1323 * the higher level protocols. 1324 */ 1325static void 1326nge_rxeof(sc) 1327 struct nge_softc *sc; 1328{ 1329 struct mbuf *m; 1330 struct ifnet *ifp; 1331 struct nge_desc *cur_rx; 1332 int i, total_len = 0; 1333 u_int32_t rxstat; 1334 1335 ifp = &sc->arpcom.ac_if; 1336 i = sc->nge_cdata.nge_rx_prod; 1337 1338 while(NGE_OWNDESC(&sc->nge_ldata->nge_rx_list[i])) { 1339 struct mbuf *m0 = NULL; 1340 u_int32_t extsts; 1341 1342#ifdef DEVICE_POLLING 1343 if (ifp->if_ipending & IFF_POLLING) { 1344 if (sc->rxcycles <= 0) 1345 break; 1346 sc->rxcycles--; 1347 } 1348#endif /* DEVICE_POLLING */ 1349 1350 cur_rx = &sc->nge_ldata->nge_rx_list[i]; 1351 rxstat = cur_rx->nge_rxstat; 1352 extsts = cur_rx->nge_extsts; 1353 m = cur_rx->nge_mbuf; 1354 cur_rx->nge_mbuf = NULL; 1355 total_len = NGE_RXBYTES(cur_rx); 1356 NGE_INC(i, NGE_RX_LIST_CNT); 1357 /* 1358 * If an error occurs, update stats, clear the 1359 * status word and leave the mbuf cluster in place: 1360 * it should simply get re-used next time this descriptor 1361 * comes up in the ring. 1362 */ 1363 if (!(rxstat & NGE_CMDSTS_PKT_OK)) { 1364 ifp->if_ierrors++; 1365 nge_newbuf(sc, cur_rx, m); 1366 continue; 1367 } 1368 1369 /* 1370 * Ok. NatSemi really screwed up here. This is the 1371 * only gigE chip I know of with alignment constraints 1372 * on receive buffers. RX buffers must be 64-bit aligned. 1373 */ 1374#ifdef __i386__ 1375 /* 1376 * By popular demand, ignore the alignment problems 1377 * on the Intel x86 platform. The performance hit 1378 * incurred due to unaligned accesses is much smaller 1379 * than the hit produced by forcing buffer copies all 1380 * the time, especially with jumbo frames. We still 1381 * need to fix up the alignment everywhere else though. 1382 */ 1383 if (nge_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 1384#endif 1385 m0 = m_devget(mtod(m, char *), total_len, 1386 ETHER_ALIGN, ifp, NULL); 1387 nge_newbuf(sc, cur_rx, m); 1388 if (m0 == NULL) { 1389 printf("nge%d: no receive buffers " 1390 "available -- packet dropped!\n", 1391 sc->nge_unit); 1392 ifp->if_ierrors++; 1393 continue; 1394 } 1395 m = m0; 1396#ifdef __i386__ 1397 } else { 1398 m->m_pkthdr.rcvif = ifp; 1399 m->m_pkthdr.len = m->m_len = total_len; 1400 } 1401#endif 1402 1403 ifp->if_ipackets++; 1404 1405 /* Do IP checksum checking. */ 1406 if (extsts & NGE_RXEXTSTS_IPPKT) 1407 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1408 if (!(extsts & NGE_RXEXTSTS_IPCSUMERR)) 1409 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1410 if ((extsts & NGE_RXEXTSTS_TCPPKT && 1411 !(extsts & NGE_RXEXTSTS_TCPCSUMERR)) || 1412 (extsts & NGE_RXEXTSTS_UDPPKT && 1413 !(extsts & NGE_RXEXTSTS_UDPCSUMERR))) { 1414 m->m_pkthdr.csum_flags |= 1415 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1416 m->m_pkthdr.csum_data = 0xffff; 1417 } 1418 1419 /* 1420 * If we received a packet with a vlan tag, pass it 1421 * to vlan_input() instead of ether_input(). 1422 */ 1423 if (extsts & NGE_RXEXTSTS_VLANPKT) { 1424 VLAN_INPUT_TAG(ifp, m, 1425 extsts & NGE_RXEXTSTS_VTCI, continue); 1426 } 1427 1428 (*ifp->if_input)(ifp, m); 1429 } 1430 1431 sc->nge_cdata.nge_rx_prod = i; 1432 1433 return; 1434} 1435 1436/* 1437 * A frame was downloaded to the chip. It's safe for us to clean up 1438 * the list buffers. 1439 */ 1440 1441static void 1442nge_txeof(sc) 1443 struct nge_softc *sc; 1444{ 1445 struct nge_desc *cur_tx = NULL; 1446 struct ifnet *ifp; 1447 u_int32_t idx; 1448 1449 ifp = &sc->arpcom.ac_if; 1450 1451 /* Clear the timeout timer. */ 1452 ifp->if_timer = 0; 1453 1454 /* 1455 * Go through our tx list and free mbufs for those 1456 * frames that have been transmitted. 1457 */ 1458 idx = sc->nge_cdata.nge_tx_cons; 1459 while (idx != sc->nge_cdata.nge_tx_prod) { 1460 cur_tx = &sc->nge_ldata->nge_tx_list[idx]; 1461 1462 if (NGE_OWNDESC(cur_tx)) 1463 break; 1464 1465 if (cur_tx->nge_ctl & NGE_CMDSTS_MORE) { 1466 sc->nge_cdata.nge_tx_cnt--; 1467 NGE_INC(idx, NGE_TX_LIST_CNT); 1468 continue; 1469 } 1470 1471 if (!(cur_tx->nge_ctl & NGE_CMDSTS_PKT_OK)) { 1472 ifp->if_oerrors++; 1473 if (cur_tx->nge_txstat & NGE_TXSTAT_EXCESSCOLLS) 1474 ifp->if_collisions++; 1475 if (cur_tx->nge_txstat & NGE_TXSTAT_OUTOFWINCOLL) 1476 ifp->if_collisions++; 1477 } 1478 1479 ifp->if_collisions += 1480 (cur_tx->nge_txstat & NGE_TXSTAT_COLLCNT) >> 16; 1481 1482 ifp->if_opackets++; 1483 if (cur_tx->nge_mbuf != NULL) { 1484 m_freem(cur_tx->nge_mbuf); 1485 cur_tx->nge_mbuf = NULL; 1486 } 1487 1488 sc->nge_cdata.nge_tx_cnt--; 1489 NGE_INC(idx, NGE_TX_LIST_CNT); 1490 ifp->if_timer = 0; 1491 } 1492 1493 sc->nge_cdata.nge_tx_cons = idx; 1494 1495 if (cur_tx != NULL) 1496 ifp->if_flags &= ~IFF_OACTIVE; 1497 1498 return; 1499} 1500 1501static void 1502nge_tick(xsc) 1503 void *xsc; 1504{ 1505 struct nge_softc *sc; 1506 struct mii_data *mii; 1507 struct ifnet *ifp; 1508 int s; 1509 1510 s = splimp(); 1511 1512 sc = xsc; 1513 ifp = &sc->arpcom.ac_if; 1514 1515 if (sc->nge_tbi) { 1516 if (!sc->nge_link) { 1517 if (CSR_READ_4(sc, NGE_TBI_BMSR) 1518 & NGE_TBIBMSR_ANEG_DONE) { 1519 printf("nge%d: gigabit link up\n", 1520 sc->nge_unit); 1521 nge_miibus_statchg(sc->nge_miibus); 1522 sc->nge_link++; 1523 if (ifp->if_snd.ifq_head != NULL) 1524 nge_start(ifp); 1525 } 1526 } 1527 } else { 1528 mii = device_get_softc(sc->nge_miibus); 1529 mii_tick(mii); 1530 1531 if (!sc->nge_link) { 1532 if (mii->mii_media_status & IFM_ACTIVE && 1533 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1534 sc->nge_link++; 1535 if (IFM_SUBTYPE(mii->mii_media_active) 1536 == IFM_1000_T) 1537 printf("nge%d: gigabit link up\n", 1538 sc->nge_unit); 1539 if (ifp->if_snd.ifq_head != NULL) 1540 nge_start(ifp); 1541 } 1542 } 1543 } 1544 sc->nge_stat_ch = timeout(nge_tick, sc, hz); 1545 1546 splx(s); 1547 1548 return; 1549} 1550 1551#ifdef DEVICE_POLLING 1552static poll_handler_t nge_poll; 1553 1554static void 1555nge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1556{ 1557 struct nge_softc *sc = ifp->if_softc; 1558 1559 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1560 CSR_WRITE_4(sc, NGE_IER, 1); 1561 return; 1562 } 1563 1564 /* 1565 * On the nge, reading the status register also clears it. 1566 * So before returning to intr mode we must make sure that all 1567 * possible pending sources of interrupts have been served. 1568 * In practice this means run to completion the *eof routines, 1569 * and then call the interrupt routine 1570 */ 1571 sc->rxcycles = count; 1572 nge_rxeof(sc); 1573 nge_txeof(sc); 1574 if (ifp->if_snd.ifq_head != NULL) 1575 nge_start(ifp); 1576 1577 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1578 u_int32_t status; 1579 1580 /* Reading the ISR register clears all interrupts. */ 1581 status = CSR_READ_4(sc, NGE_ISR); 1582 1583 if (status & (NGE_ISR_RX_ERR|NGE_ISR_RX_OFLOW)) 1584 nge_rxeof(sc); 1585 1586 if (status & (NGE_ISR_RX_IDLE)) 1587 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1588 1589 if (status & NGE_ISR_SYSERR) { 1590 nge_reset(sc); 1591 nge_init(sc); 1592 } 1593 } 1594} 1595#endif /* DEVICE_POLLING */ 1596 1597static void 1598nge_intr(arg) 1599 void *arg; 1600{ 1601 struct nge_softc *sc; 1602 struct ifnet *ifp; 1603 u_int32_t status; 1604 1605 sc = arg; 1606 ifp = &sc->arpcom.ac_if; 1607 1608#ifdef DEVICE_POLLING 1609 if (ifp->if_ipending & IFF_POLLING) 1610 return; 1611 if (ether_poll_register(nge_poll, ifp)) { /* ok, disable interrupts */ 1612 CSR_WRITE_4(sc, NGE_IER, 0); 1613 nge_poll(ifp, 0, 1); 1614 return; 1615 } 1616#endif /* DEVICE_POLLING */ 1617 1618 /* Supress unwanted interrupts */ 1619 if (!(ifp->if_flags & IFF_UP)) { 1620 nge_stop(sc); 1621 return; 1622 } 1623 1624 /* Disable interrupts. */ 1625 CSR_WRITE_4(sc, NGE_IER, 0); 1626 1627 /* Data LED on for TBI mode */ 1628 if(sc->nge_tbi) 1629 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 1630 | NGE_GPIO_GP3_OUT); 1631 1632 for (;;) { 1633 /* Reading the ISR register clears all interrupts. */ 1634 status = CSR_READ_4(sc, NGE_ISR); 1635 1636 if ((status & NGE_INTRS) == 0) 1637 break; 1638 1639 if ((status & NGE_ISR_TX_DESC_OK) || 1640 (status & NGE_ISR_TX_ERR) || 1641 (status & NGE_ISR_TX_OK) || 1642 (status & NGE_ISR_TX_IDLE)) 1643 nge_txeof(sc); 1644 1645 if ((status & NGE_ISR_RX_DESC_OK) || 1646 (status & NGE_ISR_RX_ERR) || 1647 (status & NGE_ISR_RX_OFLOW) || 1648 (status & NGE_ISR_RX_FIFO_OFLOW) || 1649 (status & NGE_ISR_RX_IDLE) || 1650 (status & NGE_ISR_RX_OK)) 1651 nge_rxeof(sc); 1652 1653 if ((status & NGE_ISR_RX_IDLE)) 1654 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1655 1656 if (status & NGE_ISR_SYSERR) { 1657 nge_reset(sc); 1658 ifp->if_flags &= ~IFF_RUNNING; 1659 nge_init(sc); 1660 } 1661 1662#if 0 1663 /* 1664 * XXX: nge_tick() is not ready to be called this way 1665 * it screws up the aneg timeout because mii_tick() is 1666 * only to be called once per second. 1667 */ 1668 if (status & NGE_IMR_PHY_INTR) { 1669 sc->nge_link = 0; 1670 nge_tick(sc); 1671 } 1672#endif 1673 } 1674 1675 /* Re-enable interrupts. */ 1676 CSR_WRITE_4(sc, NGE_IER, 1); 1677 1678 if (ifp->if_snd.ifq_head != NULL) 1679 nge_start(ifp); 1680 1681 /* Data LED off for TBI mode */ 1682 1683 if(sc->nge_tbi) 1684 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 1685 & ~NGE_GPIO_GP3_OUT); 1686 1687 return; 1688} 1689 1690/* 1691 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1692 * pointers to the fragment pointers. 1693 */ 1694static int 1695nge_encap(sc, m_head, txidx) 1696 struct nge_softc *sc; 1697 struct mbuf *m_head; 1698 u_int32_t *txidx; 1699{ 1700 struct nge_desc *f = NULL; 1701 struct mbuf *m; 1702 int frag, cur, cnt = 0; 1703 struct m_tag *mtag; 1704 1705 /* 1706 * Start packing the mbufs in this chain into 1707 * the fragment pointers. Stop when we run out 1708 * of fragments or hit the end of the mbuf chain. 1709 */ 1710 m = m_head; 1711 cur = frag = *txidx; 1712 1713 for (m = m_head; m != NULL; m = m->m_next) { 1714 if (m->m_len != 0) { 1715 if ((NGE_TX_LIST_CNT - 1716 (sc->nge_cdata.nge_tx_cnt + cnt)) < 2) 1717 return(ENOBUFS); 1718 f = &sc->nge_ldata->nge_tx_list[frag]; 1719 f->nge_ctl = NGE_CMDSTS_MORE | m->m_len; 1720 f->nge_ptr = vtophys(mtod(m, vm_offset_t)); 1721 if (cnt != 0) 1722 f->nge_ctl |= NGE_CMDSTS_OWN; 1723 cur = frag; 1724 NGE_INC(frag, NGE_TX_LIST_CNT); 1725 cnt++; 1726 } 1727 } 1728 1729 if (m != NULL) 1730 return(ENOBUFS); 1731 1732 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts = 0; 1733 if (m_head->m_pkthdr.csum_flags) { 1734 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1735 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1736 NGE_TXEXTSTS_IPCSUM; 1737 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1738 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1739 NGE_TXEXTSTS_TCPCSUM; 1740 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 1741 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1742 NGE_TXEXTSTS_UDPCSUM; 1743 } 1744 1745 mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m); 1746 if (mtag != NULL) { 1747 sc->nge_ldata->nge_tx_list[cur].nge_extsts |= 1748 (NGE_TXEXTSTS_VLANPKT|VLAN_TAG_VALUE(mtag)); 1749 } 1750 1751 sc->nge_ldata->nge_tx_list[cur].nge_mbuf = m_head; 1752 sc->nge_ldata->nge_tx_list[cur].nge_ctl &= ~NGE_CMDSTS_MORE; 1753 sc->nge_ldata->nge_tx_list[*txidx].nge_ctl |= NGE_CMDSTS_OWN; 1754 sc->nge_cdata.nge_tx_cnt += cnt; 1755 *txidx = frag; 1756 1757 return(0); 1758} 1759 1760/* 1761 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1762 * to the mbuf data regions directly in the transmit lists. We also save a 1763 * copy of the pointers since the transmit list fragment pointers are 1764 * physical addresses. 1765 */ 1766 1767static void 1768nge_start(ifp) 1769 struct ifnet *ifp; 1770{ 1771 struct nge_softc *sc; 1772 struct mbuf *m_head = NULL; 1773 u_int32_t idx; 1774 1775 sc = ifp->if_softc; 1776 1777 if (!sc->nge_link) 1778 return; 1779 1780 idx = sc->nge_cdata.nge_tx_prod; 1781 1782 if (ifp->if_flags & IFF_OACTIVE) 1783 return; 1784 1785 while(sc->nge_ldata->nge_tx_list[idx].nge_mbuf == NULL) { 1786 IF_DEQUEUE(&ifp->if_snd, m_head); 1787 if (m_head == NULL) 1788 break; 1789 1790 if (nge_encap(sc, m_head, &idx)) { 1791 IF_PREPEND(&ifp->if_snd, m_head); 1792 ifp->if_flags |= IFF_OACTIVE; 1793 break; 1794 } 1795 1796 /* 1797 * If there's a BPF listener, bounce a copy of this frame 1798 * to him. 1799 */ 1800 BPF_MTAP(ifp, m_head); 1801 1802 } 1803 1804 /* Transmit */ 1805 sc->nge_cdata.nge_tx_prod = idx; 1806 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_ENABLE); 1807 1808 /* 1809 * Set a timeout in case the chip goes out to lunch. 1810 */ 1811 ifp->if_timer = 5; 1812 1813 return; 1814} 1815 1816static void 1817nge_init(xsc) 1818 void *xsc; 1819{ 1820 struct nge_softc *sc = xsc; 1821 struct ifnet *ifp = &sc->arpcom.ac_if; 1822 struct mii_data *mii; 1823 int s; 1824 1825 if (ifp->if_flags & IFF_RUNNING) 1826 return; 1827 1828 s = splimp(); 1829 1830 /* 1831 * Cancel pending I/O and free all RX/TX buffers. 1832 */ 1833 nge_stop(sc); 1834 1835 if (sc->nge_tbi) { 1836 mii = NULL; 1837 } else { 1838 mii = device_get_softc(sc->nge_miibus); 1839 } 1840 1841 /* Set MAC address */ 1842 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0); 1843 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1844 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1845 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR1); 1846 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1847 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1848 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR2); 1849 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1850 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1851 1852 /* Init circular RX list. */ 1853 if (nge_list_rx_init(sc) == ENOBUFS) { 1854 printf("nge%d: initialization failed: no " 1855 "memory for rx buffers\n", sc->nge_unit); 1856 nge_stop(sc); 1857 (void)splx(s); 1858 return; 1859 } 1860 1861 /* 1862 * Init tx descriptors. 1863 */ 1864 nge_list_tx_init(sc); 1865 1866 /* 1867 * For the NatSemi chip, we have to explicitly enable the 1868 * reception of ARP frames, as well as turn on the 'perfect 1869 * match' filter where we store the station address, otherwise 1870 * we won't receive unicasts meant for this host. 1871 */ 1872 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ARP); 1873 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_PERFECT); 1874 1875 /* If we want promiscuous mode, set the allframes bit. */ 1876 if (ifp->if_flags & IFF_PROMISC) { 1877 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS); 1878 } else { 1879 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS); 1880 } 1881 1882 /* 1883 * Set the capture broadcast bit to capture broadcast frames. 1884 */ 1885 if (ifp->if_flags & IFF_BROADCAST) { 1886 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD); 1887 } else { 1888 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD); 1889 } 1890 1891 /* 1892 * Load the multicast filter. 1893 */ 1894 nge_setmulti(sc); 1895 1896 /* Turn the receive filter on */ 1897 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ENABLE); 1898 1899 /* 1900 * Load the address of the RX and TX lists. 1901 */ 1902 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 1903 vtophys(&sc->nge_ldata->nge_rx_list[0])); 1904 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 1905 vtophys(&sc->nge_ldata->nge_tx_list[0])); 1906 1907 /* Set RX configuration */ 1908 CSR_WRITE_4(sc, NGE_RX_CFG, NGE_RXCFG); 1909 /* 1910 * Enable hardware checksum validation for all IPv4 1911 * packets, do not reject packets with bad checksums. 1912 */ 1913 CSR_WRITE_4(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_IPCSUM_ENB); 1914 1915 /* 1916 * Tell the chip to detect and strip VLAN tag info from 1917 * received frames. The tag will be provided in the extsts 1918 * field in the RX descriptors. 1919 */ 1920 NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL, 1921 NGE_VIPRXCTL_TAG_DETECT_ENB|NGE_VIPRXCTL_TAG_STRIP_ENB); 1922 1923 /* Set TX configuration */ 1924 CSR_WRITE_4(sc, NGE_TX_CFG, NGE_TXCFG); 1925 1926 /* 1927 * Enable TX IPv4 checksumming on a per-packet basis. 1928 */ 1929 CSR_WRITE_4(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_CSUM_PER_PKT); 1930 1931 /* 1932 * Tell the chip to insert VLAN tags on a per-packet basis as 1933 * dictated by the code in the frame encapsulation routine. 1934 */ 1935 NGE_SETBIT(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_TAG_PER_PKT); 1936 1937 /* Set full/half duplex mode. */ 1938 if (sc->nge_tbi) { 1939 if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) 1940 == IFM_FDX) { 1941 NGE_SETBIT(sc, NGE_TX_CFG, 1942 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1943 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1944 } else { 1945 NGE_CLRBIT(sc, NGE_TX_CFG, 1946 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1947 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1948 } 1949 } else { 1950 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1951 NGE_SETBIT(sc, NGE_TX_CFG, 1952 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1953 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1954 } else { 1955 NGE_CLRBIT(sc, NGE_TX_CFG, 1956 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1957 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1958 } 1959 } 1960 1961 nge_tick(sc); 1962 1963 /* 1964 * Enable the delivery of PHY interrupts based on 1965 * link/speed/duplex status changes. Also enable the 1966 * extsts field in the DMA descriptors (needed for 1967 * TCP/IP checksum offload on transmit). 1968 */ 1969 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_PHYINTR_SPD| 1970 NGE_CFG_PHYINTR_LNK|NGE_CFG_PHYINTR_DUP|NGE_CFG_EXTSTS_ENB); 1971 1972 /* 1973 * Configure interrupt holdoff (moderation). We can 1974 * have the chip delay interrupt delivery for a certain 1975 * period. Units are in 100us, and the max setting 1976 * is 25500us (0xFF x 100us). Default is a 100us holdoff. 1977 */ 1978 CSR_WRITE_4(sc, NGE_IHR, 0x01); 1979 1980 /* 1981 * Enable interrupts. 1982 */ 1983 CSR_WRITE_4(sc, NGE_IMR, NGE_INTRS); 1984#ifdef DEVICE_POLLING 1985 /* 1986 * ... only enable interrupts if we are not polling, make sure 1987 * they are off otherwise. 1988 */ 1989 if (ifp->if_ipending & IFF_POLLING) 1990 CSR_WRITE_4(sc, NGE_IER, 0); 1991 else 1992#endif /* DEVICE_POLLING */ 1993 CSR_WRITE_4(sc, NGE_IER, 1); 1994 1995 /* Enable receiver and transmitter. */ 1996 NGE_CLRBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE); 1997 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1998 1999 nge_ifmedia_upd(ifp); 2000 2001 ifp->if_flags |= IFF_RUNNING; 2002 ifp->if_flags &= ~IFF_OACTIVE; 2003 2004 (void)splx(s); 2005 2006 return; 2007} 2008 2009/* 2010 * Set media options. 2011 */ 2012static int 2013nge_ifmedia_upd(ifp) 2014 struct ifnet *ifp; 2015{ 2016 struct nge_softc *sc; 2017 struct mii_data *mii; 2018 2019 sc = ifp->if_softc; 2020 2021 if (sc->nge_tbi) { 2022 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) 2023 == IFM_AUTO) { 2024 CSR_WRITE_4(sc, NGE_TBI_ANAR, 2025 CSR_READ_4(sc, NGE_TBI_ANAR) 2026 | NGE_TBIANAR_HDX | NGE_TBIANAR_FDX 2027 | NGE_TBIANAR_PS1 | NGE_TBIANAR_PS2); 2028 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG 2029 | NGE_TBIBMCR_RESTART_ANEG); 2030 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG); 2031 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media 2032 & IFM_GMASK) == IFM_FDX) { 2033 NGE_SETBIT(sc, NGE_TX_CFG, 2034 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 2035 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 2036 2037 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0); 2038 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0); 2039 } else { 2040 NGE_CLRBIT(sc, NGE_TX_CFG, 2041 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 2042 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 2043 2044 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0); 2045 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0); 2046 } 2047 2048 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 2049 & ~NGE_GPIO_GP3_OUT); 2050 } else { 2051 mii = device_get_softc(sc->nge_miibus); 2052 sc->nge_link = 0; 2053 if (mii->mii_instance) { 2054 struct mii_softc *miisc; 2055 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 2056 miisc = LIST_NEXT(miisc, mii_list)) 2057 mii_phy_reset(miisc); 2058 } 2059 mii_mediachg(mii); 2060 } 2061 2062 return(0); 2063} 2064 2065/* 2066 * Report current media status. 2067 */ 2068static void 2069nge_ifmedia_sts(ifp, ifmr) 2070 struct ifnet *ifp; 2071 struct ifmediareq *ifmr; 2072{ 2073 struct nge_softc *sc; 2074 struct mii_data *mii; 2075 2076 sc = ifp->if_softc; 2077 2078 if (sc->nge_tbi) { 2079 ifmr->ifm_status = IFM_AVALID; 2080 ifmr->ifm_active = IFM_ETHER; 2081 2082 if (CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE) { 2083 ifmr->ifm_status |= IFM_ACTIVE; 2084 } 2085 if (CSR_READ_4(sc, NGE_TBI_BMCR) & NGE_TBIBMCR_LOOPBACK) 2086 ifmr->ifm_active |= IFM_LOOP; 2087 if (!CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE) { 2088 ifmr->ifm_active |= IFM_NONE; 2089 ifmr->ifm_status = 0; 2090 return; 2091 } 2092 ifmr->ifm_active |= IFM_1000_SX; 2093 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) 2094 == IFM_AUTO) { 2095 ifmr->ifm_active |= IFM_AUTO; 2096 if (CSR_READ_4(sc, NGE_TBI_ANLPAR) 2097 & NGE_TBIANAR_FDX) { 2098 ifmr->ifm_active |= IFM_FDX; 2099 }else if (CSR_READ_4(sc, NGE_TBI_ANLPAR) 2100 & NGE_TBIANAR_HDX) { 2101 ifmr->ifm_active |= IFM_HDX; 2102 } 2103 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) 2104 == IFM_FDX) 2105 ifmr->ifm_active |= IFM_FDX; 2106 else 2107 ifmr->ifm_active |= IFM_HDX; 2108 2109 } else { 2110 mii = device_get_softc(sc->nge_miibus); 2111 mii_pollstat(mii); 2112 ifmr->ifm_active = mii->mii_media_active; 2113 ifmr->ifm_status = mii->mii_media_status; 2114 } 2115 2116 return; 2117} 2118 2119static int 2120nge_ioctl(ifp, command, data) 2121 struct ifnet *ifp; 2122 u_long command; 2123 caddr_t data; 2124{ 2125 struct nge_softc *sc = ifp->if_softc; 2126 struct ifreq *ifr = (struct ifreq *) data; 2127 struct mii_data *mii; 2128 int s, error = 0; 2129 2130 s = splimp(); 2131 2132 switch(command) { 2133 case SIOCSIFMTU: 2134 if (ifr->ifr_mtu > NGE_JUMBO_MTU) 2135 error = EINVAL; 2136 else { 2137 ifp->if_mtu = ifr->ifr_mtu; 2138 /* 2139 * Workaround: if the MTU is larger than 2140 * 8152 (TX FIFO size minus 64 minus 18), turn off 2141 * TX checksum offloading. 2142 */ 2143 if (ifr->ifr_mtu >= 8152) 2144 ifp->if_hwassist = 0; 2145 else 2146 ifp->if_hwassist = NGE_CSUM_FEATURES; 2147 } 2148 break; 2149 case SIOCSIFFLAGS: 2150 if (ifp->if_flags & IFF_UP) { 2151 if (ifp->if_flags & IFF_RUNNING && 2152 ifp->if_flags & IFF_PROMISC && 2153 !(sc->nge_if_flags & IFF_PROMISC)) { 2154 NGE_SETBIT(sc, NGE_RXFILT_CTL, 2155 NGE_RXFILTCTL_ALLPHYS| 2156 NGE_RXFILTCTL_ALLMULTI); 2157 } else if (ifp->if_flags & IFF_RUNNING && 2158 !(ifp->if_flags & IFF_PROMISC) && 2159 sc->nge_if_flags & IFF_PROMISC) { 2160 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 2161 NGE_RXFILTCTL_ALLPHYS); 2162 if (!(ifp->if_flags & IFF_ALLMULTI)) 2163 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 2164 NGE_RXFILTCTL_ALLMULTI); 2165 } else { 2166 ifp->if_flags &= ~IFF_RUNNING; 2167 nge_init(sc); 2168 } 2169 } else { 2170 if (ifp->if_flags & IFF_RUNNING) 2171 nge_stop(sc); 2172 } 2173 sc->nge_if_flags = ifp->if_flags; 2174 error = 0; 2175 break; 2176 case SIOCADDMULTI: 2177 case SIOCDELMULTI: 2178 nge_setmulti(sc); 2179 error = 0; 2180 break; 2181 case SIOCGIFMEDIA: 2182 case SIOCSIFMEDIA: 2183 if (sc->nge_tbi) { 2184 error = ifmedia_ioctl(ifp, ifr, &sc->nge_ifmedia, 2185 command); 2186 } else { 2187 mii = device_get_softc(sc->nge_miibus); 2188 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 2189 command); 2190 } 2191 break; 2192 default: 2193 error = ether_ioctl(ifp, command, data); 2194 break; 2195 } 2196 2197 (void)splx(s); 2198 2199 return(error); 2200} 2201 2202static void 2203nge_watchdog(ifp) 2204 struct ifnet *ifp; 2205{ 2206 struct nge_softc *sc; 2207 2208 sc = ifp->if_softc; 2209 2210 ifp->if_oerrors++; 2211 printf("nge%d: watchdog timeout\n", sc->nge_unit); 2212 2213 nge_stop(sc); 2214 nge_reset(sc); 2215 ifp->if_flags &= ~IFF_RUNNING; 2216 nge_init(sc); 2217 2218 if (ifp->if_snd.ifq_head != NULL) 2219 nge_start(ifp); 2220 2221 return; 2222} 2223 2224/* 2225 * Stop the adapter and free any mbufs allocated to the 2226 * RX and TX lists. 2227 */ 2228static void 2229nge_stop(sc) 2230 struct nge_softc *sc; 2231{ 2232 register int i; 2233 struct ifnet *ifp; 2234 struct mii_data *mii; 2235 2236 ifp = &sc->arpcom.ac_if; 2237 ifp->if_timer = 0; 2238 if (sc->nge_tbi) { 2239 mii = NULL; 2240 } else { 2241 mii = device_get_softc(sc->nge_miibus); 2242 } 2243 2244 untimeout(nge_tick, sc, sc->nge_stat_ch); 2245#ifdef DEVICE_POLLING 2246 ether_poll_deregister(ifp); 2247#endif 2248 CSR_WRITE_4(sc, NGE_IER, 0); 2249 CSR_WRITE_4(sc, NGE_IMR, 0); 2250 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE); 2251 DELAY(1000); 2252 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 0); 2253 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 0); 2254 2255 if (!sc->nge_tbi) 2256 mii_down(mii); 2257 2258 sc->nge_link = 0; 2259 2260 /* 2261 * Free data in the RX lists. 2262 */ 2263 for (i = 0; i < NGE_RX_LIST_CNT; i++) { 2264 if (sc->nge_ldata->nge_rx_list[i].nge_mbuf != NULL) { 2265 m_freem(sc->nge_ldata->nge_rx_list[i].nge_mbuf); 2266 sc->nge_ldata->nge_rx_list[i].nge_mbuf = NULL; 2267 } 2268 } 2269 bzero((char *)&sc->nge_ldata->nge_rx_list, 2270 sizeof(sc->nge_ldata->nge_rx_list)); 2271 2272 /* 2273 * Free the TX list buffers. 2274 */ 2275 for (i = 0; i < NGE_TX_LIST_CNT; i++) { 2276 if (sc->nge_ldata->nge_tx_list[i].nge_mbuf != NULL) { 2277 m_freem(sc->nge_ldata->nge_tx_list[i].nge_mbuf); 2278 sc->nge_ldata->nge_tx_list[i].nge_mbuf = NULL; 2279 } 2280 } 2281 2282 bzero((char *)&sc->nge_ldata->nge_tx_list, 2283 sizeof(sc->nge_ldata->nge_tx_list)); 2284 2285 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2286 2287 return; 2288} 2289 2290/* 2291 * Stop all chip I/O so that the kernel's probe routines don't 2292 * get confused by errant DMAs when rebooting. 2293 */ 2294static void 2295nge_shutdown(dev) 2296 device_t dev; 2297{ 2298 struct nge_softc *sc; 2299 2300 sc = device_get_softc(dev); 2301 2302 nge_reset(sc); 2303 nge_stop(sc); 2304 2305 return; 2306} 2307