if_nge.c revision 213894
1139749Simp/*- 276479Swpaul * Copyright (c) 2001 Wind River Systems 376479Swpaul * Copyright (c) 1997, 1998, 1999, 2000, 2001 476479Swpaul * Bill Paul <wpaul@bsdi.com>. All rights reserved. 576479Swpaul * 676479Swpaul * Redistribution and use in source and binary forms, with or without 776479Swpaul * modification, are permitted provided that the following conditions 876479Swpaul * are met: 976479Swpaul * 1. Redistributions of source code must retain the above copyright 1076479Swpaul * notice, this list of conditions and the following disclaimer. 1176479Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1276479Swpaul * notice, this list of conditions and the following disclaimer in the 1376479Swpaul * documentation and/or other materials provided with the distribution. 1476479Swpaul * 3. All advertising materials mentioning features or use of this software 1576479Swpaul * must display the following acknowledgement: 1676479Swpaul * This product includes software developed by Bill Paul. 1776479Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1876479Swpaul * may be used to endorse or promote products derived from this software 1976479Swpaul * without specific prior written permission. 2076479Swpaul * 2176479Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2276479Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2376479Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2476479Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2576479Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2676479Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2776479Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2876479Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2976479Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3076479Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3176479Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3276479Swpaul */ 3376479Swpaul 34119418Sobrien#include <sys/cdefs.h> 35119418Sobrien__FBSDID("$FreeBSD: head/sys/dev/nge/if_nge.c 213894 2010-10-15 15:00:30Z marius $"); 36119418Sobrien 3776479Swpaul/* 3876479Swpaul * National Semiconductor DP83820/DP83821 gigabit ethernet driver 3976479Swpaul * for FreeBSD. Datasheets are available from: 4076479Swpaul * 4176479Swpaul * http://www.national.com/ds/DP/DP83820.pdf 4276479Swpaul * http://www.national.com/ds/DP/DP83821.pdf 4376479Swpaul * 4476479Swpaul * These chips are used on several low cost gigabit ethernet NICs 4576479Swpaul * sold by D-Link, Addtron, SMC and Asante. Both parts are 4676479Swpaul * virtually the same, except the 83820 is a 64-bit/32-bit part, 4776479Swpaul * while the 83821 is 32-bit only. 4876479Swpaul * 4976479Swpaul * Many cards also use National gigE transceivers, such as the 5076479Swpaul * DP83891, DP83861 and DP83862 gigPHYTER parts. The DP83861 datasheet 5176479Swpaul * contains a full register description that applies to all of these 5276479Swpaul * components: 5376479Swpaul * 5476479Swpaul * http://www.national.com/ds/DP/DP83861.pdf 5576479Swpaul * 5676479Swpaul * Written by Bill Paul <wpaul@bsdi.com> 5776479Swpaul * BSDi Open Source Solutions 5876479Swpaul */ 5976479Swpaul 6076479Swpaul/* 6176479Swpaul * The NatSemi DP83820 and 83821 controllers are enhanced versions 6276479Swpaul * of the NatSemi MacPHYTER 10/100 devices. They support 10, 100 6376479Swpaul * and 1000Mbps speeds with 1000baseX (ten bit interface), MII and GMII 6476479Swpaul * ports. Other features include 8K TX FIFO and 32K RX FIFO, TCP/IP 6576479Swpaul * hardware checksum offload (IPv4 only), VLAN tagging and filtering, 6676479Swpaul * priority TX and RX queues, a 2048 bit multicast hash filter, 4 RX pattern 6776479Swpaul * matching buffers, one perfect address filter buffer and interrupt 6876479Swpaul * moderation. The 83820 supports both 64-bit and 32-bit addressing 6976479Swpaul * and data transfers: the 64-bit support can be toggled on or off 7076479Swpaul * via software. This affects the size of certain fields in the DMA 7176479Swpaul * descriptors. 7276479Swpaul * 7378323Swpaul * There are two bugs/misfeatures in the 83820/83821 that I have 7478323Swpaul * discovered so far: 7578323Swpaul * 7678323Swpaul * - Receive buffers must be aligned on 64-bit boundaries, which means 7778323Swpaul * you must resort to copying data in order to fix up the payload 7878323Swpaul * alignment. 7978323Swpaul * 8078323Swpaul * - In order to transmit jumbo frames larger than 8170 bytes, you have 8178323Swpaul * to turn off transmit checksum offloading, because the chip can't 8278323Swpaul * compute the checksum on an outgoing frame unless it fits entirely 8378323Swpaul * within the TX FIFO, which is only 8192 bytes in size. If you have 8478323Swpaul * TX checksum offload enabled and you transmit attempt to transmit a 8578323Swpaul * frame larger than 8170 bytes, the transmitter will wedge. 8678323Swpaul * 8778323Swpaul * To work around the latter problem, TX checksum offload is disabled 8878323Swpaul * if the user selects an MTU larger than 8152 (8170 - 18). 8976479Swpaul */ 9076479Swpaul 91150968Sglebius#ifdef HAVE_KERNEL_OPTION_HEADERS 92150968Sglebius#include "opt_device_polling.h" 93150968Sglebius#endif 94150968Sglebius 9576479Swpaul#include <sys/param.h> 9676479Swpaul#include <sys/systm.h> 97192506Syongari#include <sys/bus.h> 98192506Syongari#include <sys/endian.h> 99192506Syongari#include <sys/kernel.h> 100192506Syongari#include <sys/lock.h> 101192506Syongari#include <sys/malloc.h> 10276479Swpaul#include <sys/mbuf.h> 103129879Sphk#include <sys/module.h> 104192506Syongari#include <sys/mutex.h> 105192506Syongari#include <sys/rman.h> 10676479Swpaul#include <sys/socket.h> 107192506Syongari#include <sys/sockio.h> 108192506Syongari#include <sys/sysctl.h> 10976479Swpaul 110192506Syongari#include <net/bpf.h> 11176479Swpaul#include <net/if.h> 11276479Swpaul#include <net/if_arp.h> 11376479Swpaul#include <net/ethernet.h> 11476479Swpaul#include <net/if_dl.h> 11576479Swpaul#include <net/if_media.h> 11676479Swpaul#include <net/if_types.h> 11776479Swpaul#include <net/if_vlan_var.h> 11876479Swpaul 11976479Swpaul#include <dev/mii/mii.h> 12076479Swpaul#include <dev/mii/miivar.h> 12176479Swpaul 122119285Simp#include <dev/pci/pcireg.h> 123119285Simp#include <dev/pci/pcivar.h> 12476479Swpaul 125192506Syongari#include <machine/bus.h> 12676479Swpaul 12776522Swpaul#include <dev/nge/if_ngereg.h> 12876479Swpaul 129192506Syongari/* "device miibus" required. See GENERIC if you get errors here. */ 130192506Syongari#include "miibus_if.h" 131192506Syongari 132113506SmdoddMODULE_DEPEND(nge, pci, 1, 1, 1); 133113506SmdoddMODULE_DEPEND(nge, ether, 1, 1, 1); 13476479SwpaulMODULE_DEPEND(nge, miibus, 1, 1, 1); 13576479Swpaul 13676479Swpaul#define NGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 13776479Swpaul 13876479Swpaul/* 13976479Swpaul * Various supported device vendors/types and their names. 14076479Swpaul */ 14176479Swpaulstatic struct nge_type nge_devs[] = { 14276479Swpaul { NGE_VENDORID, NGE_DEVICEID, 14376479Swpaul "National Semiconductor Gigabit Ethernet" }, 14476479Swpaul { 0, 0, NULL } 14576479Swpaul}; 14676479Swpaul 14799497Salfredstatic int nge_probe(device_t); 14899497Salfredstatic int nge_attach(device_t); 14999497Salfredstatic int nge_detach(device_t); 150192506Syongaristatic int nge_shutdown(device_t); 151192506Syongaristatic int nge_suspend(device_t); 152192506Syongaristatic int nge_resume(device_t); 15376479Swpaul 154192506Syongaristatic __inline void nge_discard_rxbuf(struct nge_softc *, int); 155192506Syongaristatic int nge_newbuf(struct nge_softc *, int); 156192506Syongaristatic int nge_encap(struct nge_softc *, struct mbuf **); 157192506Syongari#ifndef __NO_STRICT_ALIGNMENT 158192506Syongaristatic __inline void nge_fixup_rx(struct mbuf *); 159135250Swpaul#endif 160193105Sattiliostatic int nge_rxeof(struct nge_softc *); 16199497Salfredstatic void nge_txeof(struct nge_softc *); 16299497Salfredstatic void nge_intr(void *); 16399497Salfredstatic void nge_tick(void *); 164192506Syongaristatic void nge_stats_update(struct nge_softc *); 16599497Salfredstatic void nge_start(struct ifnet *); 166135250Swpaulstatic void nge_start_locked(struct ifnet *); 16799497Salfredstatic int nge_ioctl(struct ifnet *, u_long, caddr_t); 16899497Salfredstatic void nge_init(void *); 169135250Swpaulstatic void nge_init_locked(struct nge_softc *); 170192506Syongaristatic int nge_stop_mac(struct nge_softc *); 17199497Salfredstatic void nge_stop(struct nge_softc *); 172192506Syongaristatic void nge_wol(struct nge_softc *); 173192506Syongaristatic void nge_watchdog(struct nge_softc *); 174192506Syongaristatic int nge_mediachange(struct ifnet *); 175192506Syongaristatic void nge_mediastatus(struct ifnet *, struct ifmediareq *); 17676479Swpaul 17799497Salfredstatic void nge_delay(struct nge_softc *); 17899497Salfredstatic void nge_eeprom_idle(struct nge_softc *); 17999497Salfredstatic void nge_eeprom_putbyte(struct nge_softc *, int); 180192294Syongaristatic void nge_eeprom_getword(struct nge_softc *, int, uint16_t *); 181192506Syongaristatic void nge_read_eeprom(struct nge_softc *, caddr_t, int, int); 18276479Swpaul 18399497Salfredstatic void nge_mii_sync(struct nge_softc *); 184192294Syongaristatic void nge_mii_send(struct nge_softc *, uint32_t, int); 18599497Salfredstatic int nge_mii_readreg(struct nge_softc *, struct nge_mii_frame *); 18699497Salfredstatic int nge_mii_writereg(struct nge_softc *, struct nge_mii_frame *); 18776479Swpaul 18899497Salfredstatic int nge_miibus_readreg(device_t, int, int); 18999497Salfredstatic int nge_miibus_writereg(device_t, int, int, int); 19099497Salfredstatic void nge_miibus_statchg(device_t); 19176479Swpaul 192192506Syongaristatic void nge_rxfilter(struct nge_softc *); 19399497Salfredstatic void nge_reset(struct nge_softc *); 194192506Syongaristatic void nge_dmamap_cb(void *, bus_dma_segment_t *, int, int); 195192506Syongaristatic int nge_dma_alloc(struct nge_softc *); 196192506Syongaristatic void nge_dma_free(struct nge_softc *); 19799497Salfredstatic int nge_list_rx_init(struct nge_softc *); 19899497Salfredstatic int nge_list_tx_init(struct nge_softc *); 199192506Syongaristatic void nge_sysctl_node(struct nge_softc *); 200192506Syongaristatic int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 201192506Syongaristatic int sysctl_hw_nge_int_holdoff(SYSCTL_HANDLER_ARGS); 20276479Swpaul 20376479Swpaulstatic device_method_t nge_methods[] = { 20476479Swpaul /* Device interface */ 20576479Swpaul DEVMETHOD(device_probe, nge_probe), 20676479Swpaul DEVMETHOD(device_attach, nge_attach), 20776479Swpaul DEVMETHOD(device_detach, nge_detach), 20876479Swpaul DEVMETHOD(device_shutdown, nge_shutdown), 209192506Syongari DEVMETHOD(device_suspend, nge_suspend), 210192506Syongari DEVMETHOD(device_resume, nge_resume), 21176479Swpaul 21276479Swpaul /* bus interface */ 21376479Swpaul DEVMETHOD(bus_print_child, bus_generic_print_child), 21476479Swpaul DEVMETHOD(bus_driver_added, bus_generic_driver_added), 21576479Swpaul 21676479Swpaul /* MII interface */ 21776479Swpaul DEVMETHOD(miibus_readreg, nge_miibus_readreg), 21876479Swpaul DEVMETHOD(miibus_writereg, nge_miibus_writereg), 21976479Swpaul DEVMETHOD(miibus_statchg, nge_miibus_statchg), 22076479Swpaul 221192506Syongari { NULL, NULL } 22276479Swpaul}; 22376479Swpaul 22476479Swpaulstatic driver_t nge_driver = { 22576479Swpaul "nge", 22676479Swpaul nge_methods, 22776479Swpaul sizeof(struct nge_softc) 22876479Swpaul}; 22976479Swpaul 23076479Swpaulstatic devclass_t nge_devclass; 23176479Swpaul 232113506SmdoddDRIVER_MODULE(nge, pci, nge_driver, nge_devclass, 0, 0); 23376479SwpaulDRIVER_MODULE(miibus, nge, miibus_driver, miibus_devclass, 0, 0); 23476479Swpaul 23576479Swpaul#define NGE_SETBIT(sc, reg, x) \ 23676479Swpaul CSR_WRITE_4(sc, reg, \ 23776479Swpaul CSR_READ_4(sc, reg) | (x)) 23876479Swpaul 23976479Swpaul#define NGE_CLRBIT(sc, reg, x) \ 24076479Swpaul CSR_WRITE_4(sc, reg, \ 24176479Swpaul CSR_READ_4(sc, reg) & ~(x)) 24276479Swpaul 24376479Swpaul#define SIO_SET(x) \ 244106696Salfred CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x)) 24576479Swpaul 24676479Swpaul#define SIO_CLR(x) \ 247106696Salfred CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x)) 24876479Swpaul 24999497Salfredstatic void 250192288Syongaringe_delay(struct nge_softc *sc) 25176479Swpaul{ 252192297Syongari int idx; 25376479Swpaul 25476479Swpaul for (idx = (300 / 33) + 1; idx > 0; idx--) 25576479Swpaul CSR_READ_4(sc, NGE_CSR); 25676479Swpaul} 25776479Swpaul 25899497Salfredstatic void 259192288Syongaringe_eeprom_idle(struct nge_softc *sc) 26076479Swpaul{ 261192297Syongari int i; 26276479Swpaul 26376479Swpaul SIO_SET(NGE_MEAR_EE_CSEL); 26476479Swpaul nge_delay(sc); 26576479Swpaul SIO_SET(NGE_MEAR_EE_CLK); 26676479Swpaul nge_delay(sc); 26776479Swpaul 26876479Swpaul for (i = 0; i < 25; i++) { 26976479Swpaul SIO_CLR(NGE_MEAR_EE_CLK); 27076479Swpaul nge_delay(sc); 27176479Swpaul SIO_SET(NGE_MEAR_EE_CLK); 27276479Swpaul nge_delay(sc); 27376479Swpaul } 27476479Swpaul 27576479Swpaul SIO_CLR(NGE_MEAR_EE_CLK); 27676479Swpaul nge_delay(sc); 27776479Swpaul SIO_CLR(NGE_MEAR_EE_CSEL); 27876479Swpaul nge_delay(sc); 27976479Swpaul CSR_WRITE_4(sc, NGE_MEAR, 0x00000000); 28076479Swpaul} 28176479Swpaul 28276479Swpaul/* 28376479Swpaul * Send a read command and address to the EEPROM, check for ACK. 28476479Swpaul */ 28599497Salfredstatic void 286192288Syongaringe_eeprom_putbyte(struct nge_softc *sc, int addr) 28776479Swpaul{ 288192297Syongari int d, i; 28976479Swpaul 29076479Swpaul d = addr | NGE_EECMD_READ; 29176479Swpaul 29276479Swpaul /* 29376479Swpaul * Feed in each bit and stobe the clock. 29476479Swpaul */ 29576479Swpaul for (i = 0x400; i; i >>= 1) { 29676479Swpaul if (d & i) { 29776479Swpaul SIO_SET(NGE_MEAR_EE_DIN); 29876479Swpaul } else { 29976479Swpaul SIO_CLR(NGE_MEAR_EE_DIN); 30076479Swpaul } 30176479Swpaul nge_delay(sc); 30276479Swpaul SIO_SET(NGE_MEAR_EE_CLK); 30376479Swpaul nge_delay(sc); 30476479Swpaul SIO_CLR(NGE_MEAR_EE_CLK); 30576479Swpaul nge_delay(sc); 30676479Swpaul } 30776479Swpaul} 30876479Swpaul 30976479Swpaul/* 31076479Swpaul * Read a word of data stored in the EEPROM at address 'addr.' 31176479Swpaul */ 31299497Salfredstatic void 313192294Syongaringe_eeprom_getword(struct nge_softc *sc, int addr, uint16_t *dest) 31476479Swpaul{ 315192297Syongari int i; 316192297Syongari uint16_t word = 0; 31776479Swpaul 31876479Swpaul /* Force EEPROM to idle state. */ 31976479Swpaul nge_eeprom_idle(sc); 32076479Swpaul 32176479Swpaul /* Enter EEPROM access mode. */ 32276479Swpaul nge_delay(sc); 32376479Swpaul SIO_CLR(NGE_MEAR_EE_CLK); 32476479Swpaul nge_delay(sc); 32576479Swpaul SIO_SET(NGE_MEAR_EE_CSEL); 32676479Swpaul nge_delay(sc); 32776479Swpaul 32876479Swpaul /* 32976479Swpaul * Send address of word we want to read. 33076479Swpaul */ 33176479Swpaul nge_eeprom_putbyte(sc, addr); 33276479Swpaul 33376479Swpaul /* 33476479Swpaul * Start reading bits from EEPROM. 33576479Swpaul */ 33676479Swpaul for (i = 0x8000; i; i >>= 1) { 33776479Swpaul SIO_SET(NGE_MEAR_EE_CLK); 33876479Swpaul nge_delay(sc); 33976479Swpaul if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT) 34076479Swpaul word |= i; 34176479Swpaul nge_delay(sc); 34276479Swpaul SIO_CLR(NGE_MEAR_EE_CLK); 34376479Swpaul nge_delay(sc); 34476479Swpaul } 34576479Swpaul 34676479Swpaul /* Turn off EEPROM access mode. */ 34776479Swpaul nge_eeprom_idle(sc); 34876479Swpaul 34976479Swpaul *dest = word; 35076479Swpaul} 35176479Swpaul 35276479Swpaul/* 35376479Swpaul * Read a sequence of words from the EEPROM. 35476479Swpaul */ 35599497Salfredstatic void 356192506Syongaringe_read_eeprom(struct nge_softc *sc, caddr_t dest, int off, int cnt) 35776479Swpaul{ 358192297Syongari int i; 359192297Syongari uint16_t word = 0, *ptr; 36076479Swpaul 36176479Swpaul for (i = 0; i < cnt; i++) { 36276479Swpaul nge_eeprom_getword(sc, off + i, &word); 363192294Syongari ptr = (uint16_t *)(dest + (i * 2)); 364192506Syongari *ptr = word; 36576479Swpaul } 36676479Swpaul} 36776479Swpaul 36876479Swpaul/* 36976479Swpaul * Sync the PHYs by setting data bit and strobing the clock 32 times. 37076479Swpaul */ 37199497Salfredstatic void 372192288Syongaringe_mii_sync(struct nge_softc *sc) 37376479Swpaul{ 374192297Syongari int i; 37576479Swpaul 37676479Swpaul SIO_SET(NGE_MEAR_MII_DIR|NGE_MEAR_MII_DATA); 37776479Swpaul 37876479Swpaul for (i = 0; i < 32; i++) { 37976479Swpaul SIO_SET(NGE_MEAR_MII_CLK); 38076479Swpaul DELAY(1); 38176479Swpaul SIO_CLR(NGE_MEAR_MII_CLK); 38276479Swpaul DELAY(1); 38376479Swpaul } 38476479Swpaul} 38576479Swpaul 38676479Swpaul/* 38776479Swpaul * Clock a series of bits through the MII. 38876479Swpaul */ 38999497Salfredstatic void 390192294Syongaringe_mii_send(struct nge_softc *sc, uint32_t bits, int cnt) 39176479Swpaul{ 392192297Syongari int i; 39376479Swpaul 39476479Swpaul SIO_CLR(NGE_MEAR_MII_CLK); 39576479Swpaul 39676479Swpaul for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 397192298Syongari if (bits & i) { 39876479Swpaul SIO_SET(NGE_MEAR_MII_DATA); 399192298Syongari } else { 40076479Swpaul SIO_CLR(NGE_MEAR_MII_DATA); 401192298Syongari } 40276479Swpaul DELAY(1); 40376479Swpaul SIO_CLR(NGE_MEAR_MII_CLK); 40476479Swpaul DELAY(1); 40576479Swpaul SIO_SET(NGE_MEAR_MII_CLK); 40676479Swpaul } 40776479Swpaul} 40876479Swpaul 40976479Swpaul/* 41076479Swpaul * Read an PHY register through the MII. 41176479Swpaul */ 41299497Salfredstatic int 413192288Syongaringe_mii_readreg(struct nge_softc *sc, struct nge_mii_frame *frame) 41476479Swpaul{ 415192297Syongari int i, ack; 41676479Swpaul 41776479Swpaul /* 41876479Swpaul * Set up frame for RX. 41976479Swpaul */ 42076479Swpaul frame->mii_stdelim = NGE_MII_STARTDELIM; 42176479Swpaul frame->mii_opcode = NGE_MII_READOP; 42276479Swpaul frame->mii_turnaround = 0; 42376479Swpaul frame->mii_data = 0; 424192290Syongari 42576479Swpaul CSR_WRITE_4(sc, NGE_MEAR, 0); 42676479Swpaul 42776479Swpaul /* 42876479Swpaul * Turn on data xmit. 42976479Swpaul */ 43076479Swpaul SIO_SET(NGE_MEAR_MII_DIR); 43176479Swpaul 43276479Swpaul nge_mii_sync(sc); 43376479Swpaul 43476479Swpaul /* 43576479Swpaul * Send command/address info. 43676479Swpaul */ 43776479Swpaul nge_mii_send(sc, frame->mii_stdelim, 2); 43876479Swpaul nge_mii_send(sc, frame->mii_opcode, 2); 43976479Swpaul nge_mii_send(sc, frame->mii_phyaddr, 5); 44076479Swpaul nge_mii_send(sc, frame->mii_regaddr, 5); 44176479Swpaul 44276479Swpaul /* Idle bit */ 44376479Swpaul SIO_CLR((NGE_MEAR_MII_CLK|NGE_MEAR_MII_DATA)); 44476479Swpaul DELAY(1); 44576479Swpaul SIO_SET(NGE_MEAR_MII_CLK); 44676479Swpaul DELAY(1); 44776479Swpaul 44876479Swpaul /* Turn off xmit. */ 44976479Swpaul SIO_CLR(NGE_MEAR_MII_DIR); 45076479Swpaul /* Check for ack */ 45176479Swpaul SIO_CLR(NGE_MEAR_MII_CLK); 45276479Swpaul DELAY(1); 453109058Smbr ack = CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA; 45476479Swpaul SIO_SET(NGE_MEAR_MII_CLK); 45576479Swpaul DELAY(1); 45676479Swpaul 45776479Swpaul /* 45876479Swpaul * Now try reading data bits. If the ack failed, we still 45976479Swpaul * need to clock through 16 cycles to keep the PHY(s) in sync. 46076479Swpaul */ 46176479Swpaul if (ack) { 462192292Syongari for (i = 0; i < 16; i++) { 46376479Swpaul SIO_CLR(NGE_MEAR_MII_CLK); 46476479Swpaul DELAY(1); 46576479Swpaul SIO_SET(NGE_MEAR_MII_CLK); 46676479Swpaul DELAY(1); 46776479Swpaul } 46876479Swpaul goto fail; 46976479Swpaul } 47076479Swpaul 47176479Swpaul for (i = 0x8000; i; i >>= 1) { 47276479Swpaul SIO_CLR(NGE_MEAR_MII_CLK); 47376479Swpaul DELAY(1); 47476479Swpaul if (!ack) { 47576479Swpaul if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA) 47676479Swpaul frame->mii_data |= i; 47776479Swpaul DELAY(1); 47876479Swpaul } 47976479Swpaul SIO_SET(NGE_MEAR_MII_CLK); 48076479Swpaul DELAY(1); 48176479Swpaul } 48276479Swpaul 48376479Swpaulfail: 48476479Swpaul 48576479Swpaul SIO_CLR(NGE_MEAR_MII_CLK); 48676479Swpaul DELAY(1); 48776479Swpaul SIO_SET(NGE_MEAR_MII_CLK); 48876479Swpaul DELAY(1); 48976479Swpaul 49076479Swpaul if (ack) 491192292Syongari return (1); 492192292Syongari return (0); 49376479Swpaul} 49476479Swpaul 49576479Swpaul/* 49676479Swpaul * Write to a PHY register through the MII. 49776479Swpaul */ 49899497Salfredstatic int 499192288Syongaringe_mii_writereg(struct nge_softc *sc, struct nge_mii_frame *frame) 50076479Swpaul{ 50176479Swpaul 50276479Swpaul /* 50376479Swpaul * Set up frame for TX. 50476479Swpaul */ 50576479Swpaul 50676479Swpaul frame->mii_stdelim = NGE_MII_STARTDELIM; 50776479Swpaul frame->mii_opcode = NGE_MII_WRITEOP; 50876479Swpaul frame->mii_turnaround = NGE_MII_TURNAROUND; 509192290Syongari 51076479Swpaul /* 51176479Swpaul * Turn on data output. 51276479Swpaul */ 51376479Swpaul SIO_SET(NGE_MEAR_MII_DIR); 51476479Swpaul 51576479Swpaul nge_mii_sync(sc); 51676479Swpaul 51776479Swpaul nge_mii_send(sc, frame->mii_stdelim, 2); 51876479Swpaul nge_mii_send(sc, frame->mii_opcode, 2); 51976479Swpaul nge_mii_send(sc, frame->mii_phyaddr, 5); 52076479Swpaul nge_mii_send(sc, frame->mii_regaddr, 5); 52176479Swpaul nge_mii_send(sc, frame->mii_turnaround, 2); 52276479Swpaul nge_mii_send(sc, frame->mii_data, 16); 52376479Swpaul 52476479Swpaul /* Idle bit. */ 52576479Swpaul SIO_SET(NGE_MEAR_MII_CLK); 52676479Swpaul DELAY(1); 52776479Swpaul SIO_CLR(NGE_MEAR_MII_CLK); 52876479Swpaul DELAY(1); 52976479Swpaul 53076479Swpaul /* 53176479Swpaul * Turn off xmit. 53276479Swpaul */ 53376479Swpaul SIO_CLR(NGE_MEAR_MII_DIR); 53476479Swpaul 535192292Syongari return (0); 53676479Swpaul} 53776479Swpaul 53899497Salfredstatic int 539192288Syongaringe_miibus_readreg(device_t dev, int phy, int reg) 54076479Swpaul{ 541192297Syongari struct nge_softc *sc; 542192297Syongari struct nge_mii_frame frame; 543192506Syongari int rv; 54476479Swpaul 54576479Swpaul sc = device_get_softc(dev); 546192506Syongari if ((sc->nge_flags & NGE_FLAG_TBI) != 0) { 547192506Syongari /* Pretend PHY is at address 0. */ 548192506Syongari if (phy != 0) 549192506Syongari return (0); 550192506Syongari switch (reg) { 551192506Syongari case MII_BMCR: 552192506Syongari reg = NGE_TBI_BMCR; 553192506Syongari break; 554192506Syongari case MII_BMSR: 555192506Syongari /* 83820/83821 has different bit layout for BMSR. */ 556192506Syongari rv = BMSR_ANEG | BMSR_EXTCAP | BMSR_EXTSTAT; 557192506Syongari reg = CSR_READ_4(sc, NGE_TBI_BMSR); 558192506Syongari if ((reg & NGE_TBIBMSR_ANEG_DONE) != 0) 559192506Syongari rv |= BMSR_ACOMP; 560192506Syongari if ((reg & NGE_TBIBMSR_LINKSTAT) != 0) 561192506Syongari rv |= BMSR_LINK; 562192506Syongari return (rv); 563192506Syongari case MII_ANAR: 564192506Syongari reg = NGE_TBI_ANAR; 565192506Syongari break; 566192506Syongari case MII_ANLPAR: 567192506Syongari reg = NGE_TBI_ANLPAR; 568192506Syongari break; 569192506Syongari case MII_ANER: 570192506Syongari reg = NGE_TBI_ANER; 571192506Syongari break; 572192506Syongari case MII_EXTSR: 573192506Syongari reg = NGE_TBI_ESR; 574192506Syongari break; 575192506Syongari case MII_PHYIDR1: 576192506Syongari case MII_PHYIDR2: 577192506Syongari return (0); 578192506Syongari default: 579192506Syongari device_printf(sc->nge_dev, 580192506Syongari "bad phy register read : %d\n", reg); 581192506Syongari return (0); 582192506Syongari } 583192506Syongari return (CSR_READ_4(sc, reg)); 584192506Syongari } 58576479Swpaul 58676479Swpaul bzero((char *)&frame, sizeof(frame)); 58776479Swpaul 58876479Swpaul frame.mii_phyaddr = phy; 58976479Swpaul frame.mii_regaddr = reg; 59076479Swpaul nge_mii_readreg(sc, &frame); 59176479Swpaul 592192292Syongari return (frame.mii_data); 59376479Swpaul} 59476479Swpaul 59599497Salfredstatic int 596192288Syongaringe_miibus_writereg(device_t dev, int phy, int reg, int data) 59776479Swpaul{ 598192297Syongari struct nge_softc *sc; 599192297Syongari struct nge_mii_frame frame; 60076479Swpaul 60176479Swpaul sc = device_get_softc(dev); 602192506Syongari if ((sc->nge_flags & NGE_FLAG_TBI) != 0) { 603192506Syongari /* Pretend PHY is at address 0. */ 604192506Syongari if (phy != 0) 605192506Syongari return (0); 606192506Syongari switch (reg) { 607192506Syongari case MII_BMCR: 608192506Syongari reg = NGE_TBI_BMCR; 609192506Syongari break; 610192506Syongari case MII_BMSR: 611192506Syongari return (0); 612192506Syongari case MII_ANAR: 613192506Syongari reg = NGE_TBI_ANAR; 614192506Syongari break; 615192506Syongari case MII_ANLPAR: 616192506Syongari reg = NGE_TBI_ANLPAR; 617192506Syongari break; 618192506Syongari case MII_ANER: 619192506Syongari reg = NGE_TBI_ANER; 620192506Syongari break; 621192506Syongari case MII_EXTSR: 622192506Syongari reg = NGE_TBI_ESR; 623192506Syongari break; 624192506Syongari case MII_PHYIDR1: 625192506Syongari case MII_PHYIDR2: 626192506Syongari return (0); 627192506Syongari default: 628192506Syongari device_printf(sc->nge_dev, 629192506Syongari "bad phy register write : %d\n", reg); 630192506Syongari return (0); 631192506Syongari } 632192506Syongari CSR_WRITE_4(sc, reg, data); 633192506Syongari return (0); 634192506Syongari } 63576479Swpaul 63676479Swpaul bzero((char *)&frame, sizeof(frame)); 63776479Swpaul 63876479Swpaul frame.mii_phyaddr = phy; 63976479Swpaul frame.mii_regaddr = reg; 64076479Swpaul frame.mii_data = data; 64176479Swpaul nge_mii_writereg(sc, &frame); 64276479Swpaul 643192292Syongari return (0); 64476479Swpaul} 64576479Swpaul 646192506Syongari/* 647192506Syongari * media status/link state change handler. 648192506Syongari */ 64999497Salfredstatic void 650192288Syongaringe_miibus_statchg(device_t dev) 65176479Swpaul{ 652192297Syongari struct nge_softc *sc; 653192297Syongari struct mii_data *mii; 654192506Syongari struct ifnet *ifp; 655192506Syongari struct nge_txdesc *txd; 656192506Syongari uint32_t done, reg, status; 657192506Syongari int i; 65876479Swpaul 65976479Swpaul sc = device_get_softc(dev); 660192506Syongari NGE_LOCK_ASSERT(sc); 66176479Swpaul 662192506Syongari mii = device_get_softc(sc->nge_miibus); 663192506Syongari ifp = sc->nge_ifp; 664192506Syongari if (mii == NULL || ifp == NULL || 665192506Syongari (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 666192506Syongari return; 667192506Syongari 668192506Syongari sc->nge_flags &= ~NGE_FLAG_LINK; 669192506Syongari if ((mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) == 670192506Syongari (IFM_AVALID | IFM_ACTIVE)) { 671192506Syongari switch (IFM_SUBTYPE(mii->mii_media_active)) { 672192506Syongari case IFM_10_T: 673192506Syongari case IFM_100_TX: 674192506Syongari case IFM_1000_T: 675192506Syongari case IFM_1000_SX: 676192506Syongari case IFM_1000_LX: 677192506Syongari case IFM_1000_CX: 678192506Syongari sc->nge_flags |= NGE_FLAG_LINK; 679192506Syongari break; 680192506Syongari default: 681192506Syongari break; 682101540Sambrisko } 683192506Syongari } 68476479Swpaul 685192506Syongari /* Stop Tx/Rx MACs. */ 686192506Syongari if (nge_stop_mac(sc) == ETIMEDOUT) 687192506Syongari device_printf(sc->nge_dev, 688192506Syongari "%s: unable to stop Tx/Rx MAC\n", __func__); 689192506Syongari nge_txeof(sc); 690192506Syongari nge_rxeof(sc); 691192506Syongari if (sc->nge_head != NULL) { 692192506Syongari m_freem(sc->nge_head); 693192506Syongari sc->nge_head = sc->nge_tail = NULL; 694192506Syongari } 695192506Syongari 696192506Syongari /* Release queued frames. */ 697192506Syongari for (i = 0; i < NGE_TX_RING_CNT; i++) { 698192506Syongari txd = &sc->nge_cdata.nge_txdesc[i]; 699192506Syongari if (txd->tx_m != NULL) { 700192506Syongari bus_dmamap_sync(sc->nge_cdata.nge_tx_tag, 701192506Syongari txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 702192506Syongari bus_dmamap_unload(sc->nge_cdata.nge_tx_tag, 703192506Syongari txd->tx_dmamap); 704192506Syongari m_freem(txd->tx_m); 705192506Syongari txd->tx_m = NULL; 706192506Syongari } 707192506Syongari } 708192506Syongari 709192506Syongari /* Program MAC with resolved speed/duplex. */ 710192506Syongari if ((sc->nge_flags & NGE_FLAG_LINK) != 0) { 711192506Syongari if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 712192506Syongari NGE_SETBIT(sc, NGE_TX_CFG, 713192506Syongari (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 714101540Sambrisko NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 715192506Syongari#ifdef notyet 716192506Syongari /* Enable flow-control. */ 717192506Syongari if ((IFM_OPTIONS(mii->mii_media_active) & 718192506Syongari (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) != 0) 719192506Syongari NGE_SETBIT(sc, NGE_PAUSECSR, 720192506Syongari NGE_PAUSECSR_PAUSE_ENB); 721192506Syongari#endif 722101540Sambrisko } else { 723101540Sambrisko NGE_CLRBIT(sc, NGE_TX_CFG, 724192506Syongari (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 725101540Sambrisko NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 726192506Syongari NGE_CLRBIT(sc, NGE_PAUSECSR, NGE_PAUSECSR_PAUSE_ENB); 727101540Sambrisko } 728101540Sambrisko /* If we have a 1000Mbps link, set the mode_1000 bit. */ 729192506Syongari reg = CSR_READ_4(sc, NGE_CFG); 730192506Syongari switch (IFM_SUBTYPE(mii->mii_media_active)) { 731192506Syongari case IFM_1000_SX: 732192506Syongari case IFM_1000_LX: 733192506Syongari case IFM_1000_CX: 734192506Syongari case IFM_1000_T: 735192506Syongari reg |= NGE_CFG_MODE_1000; 736192506Syongari break; 737192506Syongari default: 738192506Syongari reg &= ~NGE_CFG_MODE_1000; 739192506Syongari break; 740101540Sambrisko } 741192506Syongari CSR_WRITE_4(sc, NGE_CFG, reg); 742192506Syongari 743192506Syongari /* Reset Tx/Rx MAC. */ 744192506Syongari reg = CSR_READ_4(sc, NGE_CSR); 745192506Syongari reg |= NGE_CSR_TX_RESET | NGE_CSR_RX_RESET; 746192506Syongari CSR_WRITE_4(sc, NGE_CSR, reg); 747192506Syongari /* Check the completion of reset. */ 748192506Syongari done = 0; 749192506Syongari for (i = 0; i < NGE_TIMEOUT; i++) { 750192506Syongari DELAY(1); 751192506Syongari status = CSR_READ_4(sc, NGE_ISR); 752192506Syongari if ((status & NGE_ISR_RX_RESET_DONE) != 0) 753192506Syongari done |= NGE_ISR_RX_RESET_DONE; 754192506Syongari if ((status & NGE_ISR_TX_RESET_DONE) != 0) 755192506Syongari done |= NGE_ISR_TX_RESET_DONE; 756192506Syongari if (done == 757192506Syongari (NGE_ISR_TX_RESET_DONE | NGE_ISR_RX_RESET_DONE)) 758192506Syongari break; 759192506Syongari } 760192506Syongari if (i == NGE_TIMEOUT) 761192506Syongari device_printf(sc->nge_dev, 762192506Syongari "%s: unable to reset Tx/Rx MAC\n", __func__); 763192506Syongari /* Reuse Rx buffer and reset consumer pointer. */ 764192506Syongari sc->nge_cdata.nge_rx_cons = 0; 765192506Syongari /* 766192506Syongari * It seems that resetting Rx/Tx MAC results in 767192506Syongari * resetting Tx/Rx descriptor pointer registers such 768192506Syongari * that reloading Tx/Rx lists address are needed. 769192506Syongari */ 770192506Syongari CSR_WRITE_4(sc, NGE_RX_LISTPTR_HI, 771192506Syongari NGE_ADDR_HI(sc->nge_rdata.nge_rx_ring_paddr)); 772192506Syongari CSR_WRITE_4(sc, NGE_RX_LISTPTR_LO, 773192506Syongari NGE_ADDR_LO(sc->nge_rdata.nge_rx_ring_paddr)); 774192506Syongari CSR_WRITE_4(sc, NGE_TX_LISTPTR_HI, 775192506Syongari NGE_ADDR_HI(sc->nge_rdata.nge_tx_ring_paddr)); 776192506Syongari CSR_WRITE_4(sc, NGE_TX_LISTPTR_LO, 777192506Syongari NGE_ADDR_LO(sc->nge_rdata.nge_tx_ring_paddr)); 778192506Syongari /* Reinitialize Tx buffers. */ 779192506Syongari nge_list_tx_init(sc); 780192506Syongari 781192506Syongari /* Restart Rx MAC. */ 782192506Syongari reg = CSR_READ_4(sc, NGE_CSR); 783192506Syongari reg |= NGE_CSR_RX_ENABLE; 784192506Syongari CSR_WRITE_4(sc, NGE_CSR, reg); 785192506Syongari for (i = 0; i < NGE_TIMEOUT; i++) { 786192506Syongari if ((CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RX_ENABLE) != 0) 787192506Syongari break; 788192506Syongari DELAY(1); 789192506Syongari } 790192506Syongari if (i == NGE_TIMEOUT) 791192506Syongari device_printf(sc->nge_dev, 792192506Syongari "%s: unable to restart Rx MAC\n", __func__); 79379424Swpaul } 794192506Syongari 795192506Syongari /* Data LED off for TBI mode */ 796192506Syongari if ((sc->nge_flags & NGE_FLAG_TBI) != 0) 797192506Syongari CSR_WRITE_4(sc, NGE_GPIO, 798192506Syongari CSR_READ_4(sc, NGE_GPIO) & ~NGE_GPIO_GP3_OUT); 79976479Swpaul} 80076479Swpaul 80199497Salfredstatic void 802192506Syongaringe_rxfilter(struct nge_softc *sc) 80376479Swpaul{ 804192297Syongari struct ifnet *ifp; 805192297Syongari struct ifmultiaddr *ifma; 806192506Syongari uint32_t h, i, rxfilt; 807192297Syongari int bit, index; 80876479Swpaul 809135250Swpaul NGE_LOCK_ASSERT(sc); 810147256Sbrooks ifp = sc->nge_ifp; 81176479Swpaul 812192506Syongari /* Make sure to stop Rx filtering. */ 813192506Syongari rxfilt = CSR_READ_4(sc, NGE_RXFILT_CTL); 814192506Syongari rxfilt &= ~NGE_RXFILTCTL_ENABLE; 815192506Syongari CSR_WRITE_4(sc, NGE_RXFILT_CTL, rxfilt); 816192506Syongari CSR_BARRIER_WRITE_4(sc, NGE_RXFILT_CTL); 817192506Syongari 818192506Syongari rxfilt &= ~(NGE_RXFILTCTL_ALLMULTI | NGE_RXFILTCTL_ALLPHYS); 819192506Syongari rxfilt &= ~NGE_RXFILTCTL_BROAD; 820192506Syongari /* 821192506Syongari * We don't want to use the hash table for matching unicast 822192506Syongari * addresses. 823192506Syongari */ 824192506Syongari rxfilt &= ~(NGE_RXFILTCTL_MCHASH | NGE_RXFILTCTL_UCHASH); 825192506Syongari 826192506Syongari /* 827192506Syongari * For the NatSemi chip, we have to explicitly enable the 828192506Syongari * reception of ARP frames, as well as turn on the 'perfect 829192506Syongari * match' filter where we store the station address, otherwise 830192506Syongari * we won't receive unicasts meant for this host. 831192506Syongari */ 832192506Syongari rxfilt |= NGE_RXFILTCTL_ARP | NGE_RXFILTCTL_PERFECT; 833192506Syongari 834192506Syongari /* 835192506Syongari * Set the capture broadcast bit to capture broadcast frames. 836192506Syongari */ 837192506Syongari if ((ifp->if_flags & IFF_BROADCAST) != 0) 838192506Syongari rxfilt |= NGE_RXFILTCTL_BROAD; 839192506Syongari 840192506Syongari if ((ifp->if_flags & IFF_PROMISC) != 0 || 841192506Syongari (ifp->if_flags & IFF_ALLMULTI) != 0) { 842192506Syongari rxfilt |= NGE_RXFILTCTL_ALLMULTI; 843192506Syongari if ((ifp->if_flags & IFF_PROMISC) != 0) 844192506Syongari rxfilt |= NGE_RXFILTCTL_ALLPHYS; 845192506Syongari goto done; 84676479Swpaul } 84776479Swpaul 84876479Swpaul /* 84976479Swpaul * We have to explicitly enable the multicast hash table 85076479Swpaul * on the NatSemi chip if we want to use it, which we do. 85176479Swpaul */ 852192506Syongari rxfilt |= NGE_RXFILTCTL_MCHASH; 85376479Swpaul 85476479Swpaul /* first, zot all the existing hash bits */ 85576479Swpaul for (i = 0; i < NGE_MCAST_FILTER_LEN; i += 2) { 85676479Swpaul CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + i); 85776479Swpaul CSR_WRITE_4(sc, NGE_RXFILT_DATA, 0); 85876479Swpaul } 85976479Swpaul 86076479Swpaul /* 86176479Swpaul * From the 11 bits returned by the crc routine, the top 7 86276479Swpaul * bits represent the 16-bit word in the mcast hash table 86376479Swpaul * that needs to be updated, and the lower 4 bits represent 86476479Swpaul * which bit within that byte needs to be set. 86576479Swpaul */ 866195049Srwatson if_maddr_rlock(ifp); 86776479Swpaul TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 86876479Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 86976479Swpaul continue; 870130270Snaddy h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 871130270Snaddy ifma->ifma_addr), ETHER_ADDR_LEN) >> 21; 87276479Swpaul index = (h >> 4) & 0x7F; 87376479Swpaul bit = h & 0xF; 87476479Swpaul CSR_WRITE_4(sc, NGE_RXFILT_CTL, 87576479Swpaul NGE_FILTADDR_MCAST_LO + (index * 2)); 87676479Swpaul NGE_SETBIT(sc, NGE_RXFILT_DATA, (1 << bit)); 87776479Swpaul } 878195049Srwatson if_maddr_runlock(ifp); 87976479Swpaul 880192506Syongaridone: 881192506Syongari CSR_WRITE_4(sc, NGE_RXFILT_CTL, rxfilt); 882192506Syongari /* Turn the receive filter on. */ 883192506Syongari rxfilt |= NGE_RXFILTCTL_ENABLE; 884192506Syongari CSR_WRITE_4(sc, NGE_RXFILT_CTL, rxfilt); 885192506Syongari CSR_BARRIER_WRITE_4(sc, NGE_RXFILT_CTL); 88676479Swpaul} 88776479Swpaul 88899497Salfredstatic void 889192288Syongaringe_reset(struct nge_softc *sc) 89076479Swpaul{ 891192506Syongari uint32_t v; 892192297Syongari int i; 89376479Swpaul 89476479Swpaul NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RESET); 89576479Swpaul 89676479Swpaul for (i = 0; i < NGE_TIMEOUT; i++) { 89776479Swpaul if (!(CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET)) 89876479Swpaul break; 899192506Syongari DELAY(1); 90076479Swpaul } 90176479Swpaul 90276479Swpaul if (i == NGE_TIMEOUT) 903162321Sglebius device_printf(sc->nge_dev, "reset never completed\n"); 90476479Swpaul 90576479Swpaul /* Wait a little while for the chip to get its brains in order. */ 90676479Swpaul DELAY(1000); 90776479Swpaul 90876479Swpaul /* 90976479Swpaul * If this is a NetSemi chip, make sure to clear 91076479Swpaul * PME mode. 91176479Swpaul */ 91276479Swpaul CSR_WRITE_4(sc, NGE_CLKRUN, NGE_CLKRUN_PMESTS); 91376479Swpaul CSR_WRITE_4(sc, NGE_CLKRUN, 0); 914192506Syongari 915192506Syongari /* Clear WOL events which may interfere normal Rx filter opertaion. */ 916192506Syongari CSR_WRITE_4(sc, NGE_WOLCSR, 0); 917192506Syongari 918192506Syongari /* 919192506Syongari * Only DP83820 supports 64bits addressing/data transfers and 920192506Syongari * 64bit addressing requires different descriptor structures. 921192506Syongari * To make it simple, disable 64bit addressing/data transfers. 922192506Syongari */ 923192506Syongari v = CSR_READ_4(sc, NGE_CFG); 924192506Syongari v &= ~(NGE_CFG_64BIT_ADDR_ENB | NGE_CFG_64BIT_DATA_ENB); 925192506Syongari CSR_WRITE_4(sc, NGE_CFG, v); 92676479Swpaul} 92776479Swpaul 92876479Swpaul/* 929108470Sschweikh * Probe for a NatSemi chip. Check the PCI vendor and device 93076479Swpaul * IDs against our list and return a device name if we find a match. 93176479Swpaul */ 93299497Salfredstatic int 933192288Syongaringe_probe(device_t dev) 93476479Swpaul{ 935192297Syongari struct nge_type *t; 93676479Swpaul 93776479Swpaul t = nge_devs; 93876479Swpaul 939192292Syongari while (t->nge_name != NULL) { 94076479Swpaul if ((pci_get_vendor(dev) == t->nge_vid) && 94176479Swpaul (pci_get_device(dev) == t->nge_did)) { 94276479Swpaul device_set_desc(dev, t->nge_name); 943192292Syongari return (BUS_PROBE_DEFAULT); 94476479Swpaul } 94576479Swpaul t++; 94676479Swpaul } 94776479Swpaul 948192292Syongari return (ENXIO); 94976479Swpaul} 95076479Swpaul 95176479Swpaul/* 95276479Swpaul * Attach the interface. Allocate softc structures, do ifmedia 95376479Swpaul * setup and ethernet/BPF attach. 95476479Swpaul */ 95599497Salfredstatic int 956192288Syongaringe_attach(device_t dev) 95776479Swpaul{ 958192506Syongari uint8_t eaddr[ETHER_ADDR_LEN]; 959192506Syongari uint16_t ea[ETHER_ADDR_LEN/2], ea_temp, reg; 960192297Syongari struct nge_softc *sc; 961192506Syongari struct ifnet *ifp; 962192506Syongari int error, i, rid; 96376479Swpaul 964192506Syongari error = 0; 96576479Swpaul sc = device_get_softc(dev); 966162321Sglebius sc->nge_dev = dev; 96776479Swpaul 968135250Swpaul NGE_LOCK_INIT(sc, device_get_nameunit(dev)); 969151296Sjhb callout_init_mtx(&sc->nge_stat_ch, &sc->nge_mtx, 0); 970151296Sjhb 97176479Swpaul /* 97276479Swpaul * Map control/status registers. 97376479Swpaul */ 97476479Swpaul pci_enable_busmaster(dev); 97576479Swpaul 976192506Syongari#ifdef NGE_USEIOSPACE 977192506Syongari sc->nge_res_type = SYS_RES_IOPORT; 978192506Syongari sc->nge_res_id = PCIR_BAR(0); 979192506Syongari#else 980192506Syongari sc->nge_res_type = SYS_RES_MEMORY; 981192506Syongari sc->nge_res_id = PCIR_BAR(1); 982192506Syongari#endif 983192506Syongari sc->nge_res = bus_alloc_resource_any(dev, sc->nge_res_type, 984192506Syongari &sc->nge_res_id, RF_ACTIVE); 98576479Swpaul 98676479Swpaul if (sc->nge_res == NULL) { 987192506Syongari if (sc->nge_res_type == SYS_RES_MEMORY) { 988192506Syongari sc->nge_res_type = SYS_RES_IOPORT; 989192506Syongari sc->nge_res_id = PCIR_BAR(0); 990192506Syongari } else { 991192506Syongari sc->nge_res_type = SYS_RES_MEMORY; 992192506Syongari sc->nge_res_id = PCIR_BAR(1); 993192506Syongari } 994192506Syongari sc->nge_res = bus_alloc_resource_any(dev, sc->nge_res_type, 995192506Syongari &sc->nge_res_id, RF_ACTIVE); 996192506Syongari if (sc->nge_res == NULL) { 997192506Syongari device_printf(dev, "couldn't allocate %s resources\n", 998192506Syongari sc->nge_res_type == SYS_RES_MEMORY ? "memory" : 999192506Syongari "I/O"); 1000192506Syongari NGE_LOCK_DESTROY(sc); 1001192506Syongari return (ENXIO); 1002192506Syongari } 100376479Swpaul } 100476479Swpaul 100576479Swpaul /* Allocate interrupt */ 100676479Swpaul rid = 0; 1007127135Snjl sc->nge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 100876479Swpaul RF_SHAREABLE | RF_ACTIVE); 100976479Swpaul 101076479Swpaul if (sc->nge_irq == NULL) { 1011151296Sjhb device_printf(dev, "couldn't map interrupt\n"); 101276479Swpaul error = ENXIO; 101376479Swpaul goto fail; 101476479Swpaul } 101576479Swpaul 1016192506Syongari /* Enable MWI. */ 1017192506Syongari reg = pci_read_config(dev, PCIR_COMMAND, 2); 1018192506Syongari reg |= PCIM_CMD_MWRICEN; 1019192506Syongari pci_write_config(dev, PCIR_COMMAND, reg, 2); 1020192506Syongari 102176479Swpaul /* Reset the adapter. */ 102276479Swpaul nge_reset(sc); 102376479Swpaul 102476479Swpaul /* 102576479Swpaul * Get station address from the EEPROM. 102676479Swpaul */ 1027192506Syongari nge_read_eeprom(sc, (caddr_t)ea, NGE_EE_NODEADDR, 3); 1028192506Syongari for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1029192506Syongari ea[i] = le16toh(ea[i]); 1030192506Syongari ea_temp = ea[0]; 1031192506Syongari ea[0] = ea[2]; 1032192506Syongari ea[2] = ea_temp; 1033192506Syongari bcopy(ea, eaddr, sizeof(eaddr)); 103476479Swpaul 1035192506Syongari if (nge_dma_alloc(sc) != 0) { 103676479Swpaul error = ENXIO; 103776479Swpaul goto fail; 103876479Swpaul } 103976479Swpaul 1040192506Syongari nge_sysctl_node(sc); 1041192506Syongari 1042147256Sbrooks ifp = sc->nge_ifp = if_alloc(IFT_ETHER); 1043147256Sbrooks if (ifp == NULL) { 1044192506Syongari device_printf(dev, "can not allocate ifnet structure\n"); 1045147256Sbrooks error = ENOSPC; 1046147256Sbrooks goto fail; 1047147256Sbrooks } 104876479Swpaul ifp->if_softc = sc; 1049121816Sbrooks if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1050135250Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 105176479Swpaul ifp->if_ioctl = nge_ioctl; 105276479Swpaul ifp->if_start = nge_start; 105376479Swpaul ifp->if_init = nge_init; 1054192506Syongari ifp->if_snd.ifq_drv_maxlen = NGE_TX_RING_CNT - 1; 1055192506Syongari IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 1056192506Syongari IFQ_SET_READY(&ifp->if_snd); 105776479Swpaul ifp->if_hwassist = NGE_CSUM_FEATURES; 1058192506Syongari ifp->if_capabilities = IFCAP_HWCSUM; 1059192506Syongari /* 1060192506Syongari * It seems that some hardwares doesn't provide 3.3V auxiliary 1061192506Syongari * supply(3VAUX) to drive PME such that checking PCI power 1062192506Syongari * management capability is necessary. 1063192506Syongari */ 1064192506Syongari if (pci_find_extcap(sc->nge_dev, PCIY_PMG, &i) == 0) 1065192506Syongari ifp->if_capabilities |= IFCAP_WOL; 1066150789Sglebius ifp->if_capenable = ifp->if_capabilities; 106776479Swpaul 1068192506Syongari if ((CSR_READ_4(sc, NGE_CFG) & NGE_CFG_TBI_EN) != 0) { 1069192506Syongari sc->nge_flags |= NGE_FLAG_TBI; 1070192506Syongari device_printf(dev, "Using TBI\n"); 1071192506Syongari /* Configure GPIO. */ 1072192506Syongari CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 1073192506Syongari | NGE_GPIO_GP4_OUT 1074192506Syongari | NGE_GPIO_GP1_OUTENB | NGE_GPIO_GP2_OUTENB 1075192506Syongari | NGE_GPIO_GP3_OUTENB 1076192506Syongari | NGE_GPIO_GP3_IN | NGE_GPIO_GP4_IN); 1077192506Syongari } 1078192506Syongari 107976479Swpaul /* 108076479Swpaul * Do MII setup. 108176479Swpaul */ 1082213894Smarius error = mii_attach(dev, &sc->nge_miibus, ifp, nge_mediachange, 1083213894Smarius nge_mediastatus, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 1084192506Syongari if (error != 0) { 1085213894Smarius device_printf(dev, "attaching PHYs failed\n"); 1086192506Syongari goto fail; 108776479Swpaul } 108876479Swpaul 108976479Swpaul /* 109076479Swpaul * Call MI attach routine. 109176479Swpaul */ 1092106937Ssam ether_ifattach(ifp, eaddr); 109376479Swpaul 1094192506Syongari /* VLAN capability setup. */ 1095192506Syongari ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1096192506Syongari ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1097192506Syongari ifp->if_capenable = ifp->if_capabilities; 1098192506Syongari#ifdef DEVICE_POLLING 1099192506Syongari ifp->if_capabilities |= IFCAP_POLLING; 1100192506Syongari#endif 1101135250Swpaul /* 1102192506Syongari * Tell the upper layer(s) we support long frames. 1103192506Syongari * Must appear after the call to ether_ifattach() because 1104192506Syongari * ether_ifattach() sets ifi_hdrlen to the default value. 1105192506Syongari */ 1106192506Syongari ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1107192506Syongari 1108192506Syongari /* 1109135250Swpaul * Hookup IRQ last. 1110135250Swpaul */ 1111135250Swpaul error = bus_setup_intr(dev, sc->nge_irq, INTR_TYPE_NET | INTR_MPSAFE, 1112166901Spiso NULL, nge_intr, sc, &sc->nge_intrhand); 1113135250Swpaul if (error) { 1114151296Sjhb device_printf(dev, "couldn't set up irq\n"); 1115151296Sjhb goto fail; 1116151296Sjhb } 1117151296Sjhb 1118151296Sjhbfail: 1119192506Syongari if (error != 0) 1120192506Syongari nge_detach(dev); 1121192292Syongari return (error); 112276479Swpaul} 112376479Swpaul 112499497Salfredstatic int 1125192288Syongaringe_detach(device_t dev) 112676479Swpaul{ 1127192297Syongari struct nge_softc *sc; 1128192297Syongari struct ifnet *ifp; 112976479Swpaul 113076479Swpaul sc = device_get_softc(dev); 1131147256Sbrooks ifp = sc->nge_ifp; 113276479Swpaul 1133150789Sglebius#ifdef DEVICE_POLLING 1134192506Syongari if (ifp != NULL && ifp->if_capenable & IFCAP_POLLING) 1135150789Sglebius ether_poll_deregister(ifp); 1136150789Sglebius#endif 113776479Swpaul 1138192506Syongari if (device_is_attached(dev)) { 1139192506Syongari NGE_LOCK(sc); 1140192506Syongari sc->nge_flags |= NGE_FLAG_DETACH; 1141192506Syongari nge_stop(sc); 1142192506Syongari NGE_UNLOCK(sc); 1143192506Syongari callout_drain(&sc->nge_stat_ch); 1144192506Syongari if (ifp != NULL) 1145192506Syongari ether_ifdetach(ifp); 1146192506Syongari } 1147192506Syongari 1148192506Syongari if (sc->nge_miibus != NULL) { 1149101540Sambrisko device_delete_child(dev, sc->nge_miibus); 1150192506Syongari sc->nge_miibus = NULL; 1151101540Sambrisko } 1152192506Syongari bus_generic_detach(dev); 1153192506Syongari if (sc->nge_intrhand != NULL) 1154192506Syongari bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 1155192506Syongari if (sc->nge_irq != NULL) 1156192506Syongari bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 1157192506Syongari if (sc->nge_res != NULL) 1158192506Syongari bus_release_resource(dev, sc->nge_res_type, sc->nge_res_id, 1159192506Syongari sc->nge_res); 116076479Swpaul 1161192506Syongari nge_dma_free(sc); 1162192506Syongari if (ifp != NULL) 1163192506Syongari if_free(ifp); 116476479Swpaul 1165135251Swpaul NGE_LOCK_DESTROY(sc); 1166135251Swpaul 1167192292Syongari return (0); 116876479Swpaul} 116976479Swpaul 1170192506Syongaristruct nge_dmamap_arg { 1171192506Syongari bus_addr_t nge_busaddr; 1172192506Syongari}; 1173192506Syongari 1174192506Syongaristatic void 1175192506Syongaringe_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1176192506Syongari{ 1177192506Syongari struct nge_dmamap_arg *ctx; 1178192506Syongari 1179192506Syongari if (error != 0) 1180192506Syongari return; 1181192506Syongari ctx = arg; 1182192506Syongari ctx->nge_busaddr = segs[0].ds_addr; 1183192506Syongari} 1184192506Syongari 1185192506Syongaristatic int 1186192506Syongaringe_dma_alloc(struct nge_softc *sc) 1187192506Syongari{ 1188192506Syongari struct nge_dmamap_arg ctx; 1189192506Syongari struct nge_txdesc *txd; 1190192506Syongari struct nge_rxdesc *rxd; 1191192506Syongari int error, i; 1192192506Syongari 1193192506Syongari /* Create parent DMA tag. */ 1194192506Syongari error = bus_dma_tag_create( 1195192506Syongari bus_get_dma_tag(sc->nge_dev), /* parent */ 1196192506Syongari 1, 0, /* alignment, boundary */ 1197192506Syongari BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1198192506Syongari BUS_SPACE_MAXADDR, /* highaddr */ 1199192506Syongari NULL, NULL, /* filter, filterarg */ 1200192506Syongari BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1201192506Syongari 0, /* nsegments */ 1202192506Syongari BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1203192506Syongari 0, /* flags */ 1204192506Syongari NULL, NULL, /* lockfunc, lockarg */ 1205192506Syongari &sc->nge_cdata.nge_parent_tag); 1206192506Syongari if (error != 0) { 1207192506Syongari device_printf(sc->nge_dev, "failed to create parent DMA tag\n"); 1208192506Syongari goto fail; 1209192506Syongari } 1210192506Syongari /* Create tag for Tx ring. */ 1211192506Syongari error = bus_dma_tag_create(sc->nge_cdata.nge_parent_tag,/* parent */ 1212192506Syongari NGE_RING_ALIGN, 0, /* alignment, boundary */ 1213192506Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 1214192506Syongari BUS_SPACE_MAXADDR, /* highaddr */ 1215192506Syongari NULL, NULL, /* filter, filterarg */ 1216192506Syongari NGE_TX_RING_SIZE, /* maxsize */ 1217192506Syongari 1, /* nsegments */ 1218192506Syongari NGE_TX_RING_SIZE, /* maxsegsize */ 1219192506Syongari 0, /* flags */ 1220192506Syongari NULL, NULL, /* lockfunc, lockarg */ 1221192506Syongari &sc->nge_cdata.nge_tx_ring_tag); 1222192506Syongari if (error != 0) { 1223192506Syongari device_printf(sc->nge_dev, "failed to create Tx ring DMA tag\n"); 1224192506Syongari goto fail; 1225192506Syongari } 1226192506Syongari 1227192506Syongari /* Create tag for Rx ring. */ 1228192506Syongari error = bus_dma_tag_create(sc->nge_cdata.nge_parent_tag,/* parent */ 1229192506Syongari NGE_RING_ALIGN, 0, /* alignment, boundary */ 1230192506Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 1231192506Syongari BUS_SPACE_MAXADDR, /* highaddr */ 1232192506Syongari NULL, NULL, /* filter, filterarg */ 1233192506Syongari NGE_RX_RING_SIZE, /* maxsize */ 1234192506Syongari 1, /* nsegments */ 1235192506Syongari NGE_RX_RING_SIZE, /* maxsegsize */ 1236192506Syongari 0, /* flags */ 1237192506Syongari NULL, NULL, /* lockfunc, lockarg */ 1238192506Syongari &sc->nge_cdata.nge_rx_ring_tag); 1239192506Syongari if (error != 0) { 1240192506Syongari device_printf(sc->nge_dev, 1241192506Syongari "failed to create Rx ring DMA tag\n"); 1242192506Syongari goto fail; 1243192506Syongari } 1244192506Syongari 1245192506Syongari /* Create tag for Tx buffers. */ 1246192506Syongari error = bus_dma_tag_create(sc->nge_cdata.nge_parent_tag,/* parent */ 1247192506Syongari 1, 0, /* alignment, boundary */ 1248192506Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 1249192506Syongari BUS_SPACE_MAXADDR, /* highaddr */ 1250192506Syongari NULL, NULL, /* filter, filterarg */ 1251192506Syongari MCLBYTES * NGE_MAXTXSEGS, /* maxsize */ 1252192506Syongari NGE_MAXTXSEGS, /* nsegments */ 1253192506Syongari MCLBYTES, /* maxsegsize */ 1254192506Syongari 0, /* flags */ 1255192506Syongari NULL, NULL, /* lockfunc, lockarg */ 1256192506Syongari &sc->nge_cdata.nge_tx_tag); 1257192506Syongari if (error != 0) { 1258192506Syongari device_printf(sc->nge_dev, "failed to create Tx DMA tag\n"); 1259192506Syongari goto fail; 1260192506Syongari } 1261192506Syongari 1262192506Syongari /* Create tag for Rx buffers. */ 1263192506Syongari error = bus_dma_tag_create(sc->nge_cdata.nge_parent_tag,/* parent */ 1264192506Syongari NGE_RX_ALIGN, 0, /* alignment, boundary */ 1265192506Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 1266192506Syongari BUS_SPACE_MAXADDR, /* highaddr */ 1267192506Syongari NULL, NULL, /* filter, filterarg */ 1268192506Syongari MCLBYTES, /* maxsize */ 1269192506Syongari 1, /* nsegments */ 1270192506Syongari MCLBYTES, /* maxsegsize */ 1271192506Syongari 0, /* flags */ 1272192506Syongari NULL, NULL, /* lockfunc, lockarg */ 1273192506Syongari &sc->nge_cdata.nge_rx_tag); 1274192506Syongari if (error != 0) { 1275192506Syongari device_printf(sc->nge_dev, "failed to create Rx DMA tag\n"); 1276192506Syongari goto fail; 1277192506Syongari } 1278192506Syongari 1279192506Syongari /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1280192506Syongari error = bus_dmamem_alloc(sc->nge_cdata.nge_tx_ring_tag, 1281192506Syongari (void **)&sc->nge_rdata.nge_tx_ring, BUS_DMA_WAITOK | 1282192506Syongari BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->nge_cdata.nge_tx_ring_map); 1283192506Syongari if (error != 0) { 1284192506Syongari device_printf(sc->nge_dev, 1285192506Syongari "failed to allocate DMA'able memory for Tx ring\n"); 1286192506Syongari goto fail; 1287192506Syongari } 1288192506Syongari 1289192506Syongari ctx.nge_busaddr = 0; 1290192506Syongari error = bus_dmamap_load(sc->nge_cdata.nge_tx_ring_tag, 1291192506Syongari sc->nge_cdata.nge_tx_ring_map, sc->nge_rdata.nge_tx_ring, 1292192506Syongari NGE_TX_RING_SIZE, nge_dmamap_cb, &ctx, 0); 1293192506Syongari if (error != 0 || ctx.nge_busaddr == 0) { 1294192506Syongari device_printf(sc->nge_dev, 1295192506Syongari "failed to load DMA'able memory for Tx ring\n"); 1296192506Syongari goto fail; 1297192506Syongari } 1298192506Syongari sc->nge_rdata.nge_tx_ring_paddr = ctx.nge_busaddr; 1299192506Syongari 1300192506Syongari /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 1301192506Syongari error = bus_dmamem_alloc(sc->nge_cdata.nge_rx_ring_tag, 1302192506Syongari (void **)&sc->nge_rdata.nge_rx_ring, BUS_DMA_WAITOK | 1303192506Syongari BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->nge_cdata.nge_rx_ring_map); 1304192506Syongari if (error != 0) { 1305192506Syongari device_printf(sc->nge_dev, 1306192506Syongari "failed to allocate DMA'able memory for Rx ring\n"); 1307192506Syongari goto fail; 1308192506Syongari } 1309192506Syongari 1310192506Syongari ctx.nge_busaddr = 0; 1311192506Syongari error = bus_dmamap_load(sc->nge_cdata.nge_rx_ring_tag, 1312192506Syongari sc->nge_cdata.nge_rx_ring_map, sc->nge_rdata.nge_rx_ring, 1313192506Syongari NGE_RX_RING_SIZE, nge_dmamap_cb, &ctx, 0); 1314192506Syongari if (error != 0 || ctx.nge_busaddr == 0) { 1315192506Syongari device_printf(sc->nge_dev, 1316192506Syongari "failed to load DMA'able memory for Rx ring\n"); 1317192506Syongari goto fail; 1318192506Syongari } 1319192506Syongari sc->nge_rdata.nge_rx_ring_paddr = ctx.nge_busaddr; 1320192506Syongari 1321192506Syongari /* Create DMA maps for Tx buffers. */ 1322192506Syongari for (i = 0; i < NGE_TX_RING_CNT; i++) { 1323192506Syongari txd = &sc->nge_cdata.nge_txdesc[i]; 1324192506Syongari txd->tx_m = NULL; 1325192506Syongari txd->tx_dmamap = NULL; 1326192506Syongari error = bus_dmamap_create(sc->nge_cdata.nge_tx_tag, 0, 1327192506Syongari &txd->tx_dmamap); 1328192506Syongari if (error != 0) { 1329192506Syongari device_printf(sc->nge_dev, 1330192506Syongari "failed to create Tx dmamap\n"); 1331192506Syongari goto fail; 1332192506Syongari } 1333192506Syongari } 1334192506Syongari /* Create DMA maps for Rx buffers. */ 1335192506Syongari if ((error = bus_dmamap_create(sc->nge_cdata.nge_rx_tag, 0, 1336192506Syongari &sc->nge_cdata.nge_rx_sparemap)) != 0) { 1337192506Syongari device_printf(sc->nge_dev, 1338192506Syongari "failed to create spare Rx dmamap\n"); 1339192506Syongari goto fail; 1340192506Syongari } 1341192506Syongari for (i = 0; i < NGE_RX_RING_CNT; i++) { 1342192506Syongari rxd = &sc->nge_cdata.nge_rxdesc[i]; 1343192506Syongari rxd->rx_m = NULL; 1344192506Syongari rxd->rx_dmamap = NULL; 1345192506Syongari error = bus_dmamap_create(sc->nge_cdata.nge_rx_tag, 0, 1346192506Syongari &rxd->rx_dmamap); 1347192506Syongari if (error != 0) { 1348192506Syongari device_printf(sc->nge_dev, 1349192506Syongari "failed to create Rx dmamap\n"); 1350192506Syongari goto fail; 1351192506Syongari } 1352192506Syongari } 1353192506Syongari 1354192506Syongarifail: 1355192506Syongari return (error); 1356192506Syongari} 1357192506Syongari 1358192506Syongaristatic void 1359192506Syongaringe_dma_free(struct nge_softc *sc) 1360192506Syongari{ 1361192506Syongari struct nge_txdesc *txd; 1362192506Syongari struct nge_rxdesc *rxd; 1363192506Syongari int i; 1364192506Syongari 1365192506Syongari /* Tx ring. */ 1366192506Syongari if (sc->nge_cdata.nge_tx_ring_tag) { 1367192506Syongari if (sc->nge_cdata.nge_tx_ring_map) 1368192506Syongari bus_dmamap_unload(sc->nge_cdata.nge_tx_ring_tag, 1369192506Syongari sc->nge_cdata.nge_tx_ring_map); 1370192506Syongari if (sc->nge_cdata.nge_tx_ring_map && 1371192506Syongari sc->nge_rdata.nge_tx_ring) 1372192506Syongari bus_dmamem_free(sc->nge_cdata.nge_tx_ring_tag, 1373192506Syongari sc->nge_rdata.nge_tx_ring, 1374192506Syongari sc->nge_cdata.nge_tx_ring_map); 1375192506Syongari sc->nge_rdata.nge_tx_ring = NULL; 1376192506Syongari sc->nge_cdata.nge_tx_ring_map = NULL; 1377192506Syongari bus_dma_tag_destroy(sc->nge_cdata.nge_tx_ring_tag); 1378192506Syongari sc->nge_cdata.nge_tx_ring_tag = NULL; 1379192506Syongari } 1380192506Syongari /* Rx ring. */ 1381192506Syongari if (sc->nge_cdata.nge_rx_ring_tag) { 1382192506Syongari if (sc->nge_cdata.nge_rx_ring_map) 1383192506Syongari bus_dmamap_unload(sc->nge_cdata.nge_rx_ring_tag, 1384192506Syongari sc->nge_cdata.nge_rx_ring_map); 1385192506Syongari if (sc->nge_cdata.nge_rx_ring_map && 1386192506Syongari sc->nge_rdata.nge_rx_ring) 1387192506Syongari bus_dmamem_free(sc->nge_cdata.nge_rx_ring_tag, 1388192506Syongari sc->nge_rdata.nge_rx_ring, 1389192506Syongari sc->nge_cdata.nge_rx_ring_map); 1390192506Syongari sc->nge_rdata.nge_rx_ring = NULL; 1391192506Syongari sc->nge_cdata.nge_rx_ring_map = NULL; 1392192506Syongari bus_dma_tag_destroy(sc->nge_cdata.nge_rx_ring_tag); 1393192506Syongari sc->nge_cdata.nge_rx_ring_tag = NULL; 1394192506Syongari } 1395192506Syongari /* Tx buffers. */ 1396192506Syongari if (sc->nge_cdata.nge_tx_tag) { 1397192506Syongari for (i = 0; i < NGE_TX_RING_CNT; i++) { 1398192506Syongari txd = &sc->nge_cdata.nge_txdesc[i]; 1399192506Syongari if (txd->tx_dmamap) { 1400192506Syongari bus_dmamap_destroy(sc->nge_cdata.nge_tx_tag, 1401192506Syongari txd->tx_dmamap); 1402192506Syongari txd->tx_dmamap = NULL; 1403192506Syongari } 1404192506Syongari } 1405192506Syongari bus_dma_tag_destroy(sc->nge_cdata.nge_tx_tag); 1406192506Syongari sc->nge_cdata.nge_tx_tag = NULL; 1407192506Syongari } 1408192506Syongari /* Rx buffers. */ 1409192506Syongari if (sc->nge_cdata.nge_rx_tag) { 1410192506Syongari for (i = 0; i < NGE_RX_RING_CNT; i++) { 1411192506Syongari rxd = &sc->nge_cdata.nge_rxdesc[i]; 1412192506Syongari if (rxd->rx_dmamap) { 1413192506Syongari bus_dmamap_destroy(sc->nge_cdata.nge_rx_tag, 1414192506Syongari rxd->rx_dmamap); 1415192506Syongari rxd->rx_dmamap = NULL; 1416192506Syongari } 1417192506Syongari } 1418192506Syongari if (sc->nge_cdata.nge_rx_sparemap) { 1419192506Syongari bus_dmamap_destroy(sc->nge_cdata.nge_rx_tag, 1420192506Syongari sc->nge_cdata.nge_rx_sparemap); 1421192506Syongari sc->nge_cdata.nge_rx_sparemap = 0; 1422192506Syongari } 1423192506Syongari bus_dma_tag_destroy(sc->nge_cdata.nge_rx_tag); 1424192506Syongari sc->nge_cdata.nge_rx_tag = NULL; 1425192506Syongari } 1426192506Syongari 1427192506Syongari if (sc->nge_cdata.nge_parent_tag) { 1428192506Syongari bus_dma_tag_destroy(sc->nge_cdata.nge_parent_tag); 1429192506Syongari sc->nge_cdata.nge_parent_tag = NULL; 1430192506Syongari } 1431192506Syongari} 1432192506Syongari 143376479Swpaul/* 143476479Swpaul * Initialize the transmit descriptors. 143576479Swpaul */ 143699497Salfredstatic int 1437192288Syongaringe_list_tx_init(struct nge_softc *sc) 143876479Swpaul{ 1439192506Syongari struct nge_ring_data *rd; 1440192506Syongari struct nge_txdesc *txd; 1441192506Syongari bus_addr_t addr; 1442192297Syongari int i; 144376479Swpaul 1444192506Syongari sc->nge_cdata.nge_tx_prod = 0; 1445192506Syongari sc->nge_cdata.nge_tx_cons = 0; 1446192506Syongari sc->nge_cdata.nge_tx_cnt = 0; 144776479Swpaul 1448192506Syongari rd = &sc->nge_rdata; 1449192506Syongari bzero(rd->nge_tx_ring, sizeof(struct nge_desc) * NGE_TX_RING_CNT); 1450192506Syongari for (i = 0; i < NGE_TX_RING_CNT; i++) { 1451192506Syongari if (i == NGE_TX_RING_CNT - 1) 1452192506Syongari addr = NGE_TX_RING_ADDR(sc, 0); 1453192506Syongari else 1454192506Syongari addr = NGE_TX_RING_ADDR(sc, i + 1); 1455192506Syongari rd->nge_tx_ring[i].nge_next = htole32(NGE_ADDR_LO(addr)); 1456192506Syongari txd = &sc->nge_cdata.nge_txdesc[i]; 1457192506Syongari txd->tx_m = NULL; 145876479Swpaul } 145976479Swpaul 1460192506Syongari bus_dmamap_sync(sc->nge_cdata.nge_tx_ring_tag, 1461192506Syongari sc->nge_cdata.nge_tx_ring_map, 1462192506Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 146376479Swpaul 1464192292Syongari return (0); 146576479Swpaul} 146676479Swpaul 146776479Swpaul/* 146876479Swpaul * Initialize the RX descriptors and allocate mbufs for them. Note that 146976479Swpaul * we arrange the descriptors in a closed ring, so that the last descriptor 147076479Swpaul * points back to the first. 147176479Swpaul */ 147299497Salfredstatic int 1473192288Syongaringe_list_rx_init(struct nge_softc *sc) 147476479Swpaul{ 1475192506Syongari struct nge_ring_data *rd; 1476192506Syongari bus_addr_t addr; 1477192297Syongari int i; 147876479Swpaul 1479192506Syongari sc->nge_cdata.nge_rx_cons = 0; 1480192506Syongari sc->nge_head = sc->nge_tail = NULL; 148176479Swpaul 1482192506Syongari rd = &sc->nge_rdata; 1483192506Syongari bzero(rd->nge_rx_ring, sizeof(struct nge_desc) * NGE_RX_RING_CNT); 1484192506Syongari for (i = 0; i < NGE_RX_RING_CNT; i++) { 1485192506Syongari if (nge_newbuf(sc, i) != 0) 1486192292Syongari return (ENOBUFS); 1487192506Syongari if (i == NGE_RX_RING_CNT - 1) 1488192506Syongari addr = NGE_RX_RING_ADDR(sc, 0); 1489192506Syongari else 1490192506Syongari addr = NGE_RX_RING_ADDR(sc, i + 1); 1491192506Syongari rd->nge_rx_ring[i].nge_next = htole32(NGE_ADDR_LO(addr)); 149276479Swpaul } 149376479Swpaul 1494192506Syongari bus_dmamap_sync(sc->nge_cdata.nge_rx_ring_tag, 1495192506Syongari sc->nge_cdata.nge_rx_ring_map, 1496192506Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 149776479Swpaul 1498192292Syongari return (0); 149976479Swpaul} 150076479Swpaul 1501192506Syongaristatic __inline void 1502192506Syongaringe_discard_rxbuf(struct nge_softc *sc, int idx) 1503192506Syongari{ 1504192506Syongari struct nge_desc *desc; 1505192506Syongari 1506192506Syongari desc = &sc->nge_rdata.nge_rx_ring[idx]; 1507192506Syongari desc->nge_cmdsts = htole32(MCLBYTES - sizeof(uint64_t)); 1508192506Syongari desc->nge_extsts = 0; 1509192506Syongari} 1510192506Syongari 151176479Swpaul/* 151276479Swpaul * Initialize an RX descriptor and attach an MBUF cluster. 151376479Swpaul */ 151499497Salfredstatic int 1515192506Syongaringe_newbuf(struct nge_softc *sc, int idx) 151676479Swpaul{ 1517192506Syongari struct nge_desc *desc; 1518192506Syongari struct nge_rxdesc *rxd; 1519192506Syongari struct mbuf *m; 1520192506Syongari bus_dma_segment_t segs[1]; 1521192506Syongari bus_dmamap_t map; 1522192506Syongari int nsegs; 152376479Swpaul 1524192506Syongari m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1525192506Syongari if (m == NULL) 1526192506Syongari return (ENOBUFS); 1527135250Swpaul m->m_len = m->m_pkthdr.len = MCLBYTES; 1528192294Syongari m_adj(m, sizeof(uint64_t)); 152976479Swpaul 1530192506Syongari if (bus_dmamap_load_mbuf_sg(sc->nge_cdata.nge_rx_tag, 1531192506Syongari sc->nge_cdata.nge_rx_sparemap, m, segs, &nsegs, 0) != 0) { 1532192506Syongari m_freem(m); 1533192506Syongari return (ENOBUFS); 1534192506Syongari } 1535192506Syongari KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 153676479Swpaul 1537192506Syongari rxd = &sc->nge_cdata.nge_rxdesc[idx]; 1538192506Syongari if (rxd->rx_m != NULL) { 1539192506Syongari bus_dmamap_sync(sc->nge_cdata.nge_rx_tag, rxd->rx_dmamap, 1540192506Syongari BUS_DMASYNC_POSTREAD); 1541192506Syongari bus_dmamap_unload(sc->nge_cdata.nge_rx_tag, rxd->rx_dmamap); 1542192506Syongari } 1543192506Syongari map = rxd->rx_dmamap; 1544192506Syongari rxd->rx_dmamap = sc->nge_cdata.nge_rx_sparemap; 1545192506Syongari sc->nge_cdata.nge_rx_sparemap = map; 1546192506Syongari bus_dmamap_sync(sc->nge_cdata.nge_rx_tag, rxd->rx_dmamap, 1547192506Syongari BUS_DMASYNC_PREREAD); 1548192506Syongari rxd->rx_m = m; 1549192506Syongari desc = &sc->nge_rdata.nge_rx_ring[idx]; 1550192506Syongari desc->nge_ptr = htole32(NGE_ADDR_LO(segs[0].ds_addr)); 1551192506Syongari desc->nge_cmdsts = htole32(segs[0].ds_len); 1552192506Syongari desc->nge_extsts = 0; 1553192506Syongari 1554192292Syongari return (0); 155576479Swpaul} 155676479Swpaul 1557192506Syongari#ifndef __NO_STRICT_ALIGNMENT 1558135250Swpaulstatic __inline void 1559192288Syongaringe_fixup_rx(struct mbuf *m) 1560192290Syongari{ 1561192506Syongari int i; 1562192506Syongari uint16_t *src, *dst; 1563192290Syongari 1564135250Swpaul src = mtod(m, uint16_t *); 1565135250Swpaul dst = src - 1; 1566192290Syongari 1567135250Swpaul for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1568135250Swpaul *dst++ = *src++; 1569192290Syongari 1570135250Swpaul m->m_data -= ETHER_ALIGN; 1571192290Syongari} 157276479Swpaul#endif 157376479Swpaul 157476479Swpaul/* 157576479Swpaul * A frame has been uploaded: pass the resulting mbuf chain up to 157676479Swpaul * the higher level protocols. 157776479Swpaul */ 1578193105Sattiliostatic int 1579192288Syongaringe_rxeof(struct nge_softc *sc) 158076479Swpaul{ 1581192298Syongari struct mbuf *m; 1582192298Syongari struct ifnet *ifp; 1583192297Syongari struct nge_desc *cur_rx; 1584192506Syongari struct nge_rxdesc *rxd; 1585193105Sattilio int cons, prog, rx_npkts, total_len; 1586192506Syongari uint32_t cmdsts, extsts; 158776479Swpaul 1588135250Swpaul NGE_LOCK_ASSERT(sc); 1589192506Syongari 1590147256Sbrooks ifp = sc->nge_ifp; 1591192506Syongari cons = sc->nge_cdata.nge_rx_cons; 1592193105Sattilio rx_npkts = 0; 159376479Swpaul 1594192506Syongari bus_dmamap_sync(sc->nge_cdata.nge_rx_ring_tag, 1595192506Syongari sc->nge_cdata.nge_rx_ring_map, 1596192506Syongari BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 159776479Swpaul 1598192506Syongari for (prog = 0; prog < NGE_RX_RING_CNT && 1599192506Syongari (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0; 1600192506Syongari NGE_INC(cons, NGE_RX_RING_CNT)) { 1601106507Ssimokawa#ifdef DEVICE_POLLING 1602150789Sglebius if (ifp->if_capenable & IFCAP_POLLING) { 1603106507Ssimokawa if (sc->rxcycles <= 0) 1604106507Ssimokawa break; 1605106507Ssimokawa sc->rxcycles--; 1606106507Ssimokawa } 1607150789Sglebius#endif 1608192506Syongari cur_rx = &sc->nge_rdata.nge_rx_ring[cons]; 1609192506Syongari cmdsts = le32toh(cur_rx->nge_cmdsts); 1610192506Syongari extsts = le32toh(cur_rx->nge_extsts); 1611192506Syongari if ((cmdsts & NGE_CMDSTS_OWN) == 0) 1612192506Syongari break; 1613192506Syongari prog++; 1614192506Syongari rxd = &sc->nge_cdata.nge_rxdesc[cons]; 1615192506Syongari m = rxd->rx_m; 1616192506Syongari total_len = cmdsts & NGE_CMDSTS_BUFLEN; 1617106507Ssimokawa 1618192506Syongari if ((cmdsts & NGE_CMDSTS_MORE) != 0) { 1619192506Syongari if (nge_newbuf(sc, cons) != 0) { 1620192506Syongari ifp->if_iqdrops++; 1621192506Syongari if (sc->nge_head != NULL) { 1622192506Syongari m_freem(sc->nge_head); 1623192506Syongari sc->nge_head = sc->nge_tail = NULL; 1624192506Syongari } 1625192506Syongari nge_discard_rxbuf(sc, cons); 1626192506Syongari continue; 1627192506Syongari } 1628135250Swpaul m->m_len = total_len; 1629135250Swpaul if (sc->nge_head == NULL) { 1630135250Swpaul m->m_pkthdr.len = total_len; 1631135250Swpaul sc->nge_head = sc->nge_tail = m; 1632135250Swpaul } else { 1633135250Swpaul m->m_flags &= ~M_PKTHDR; 1634135250Swpaul sc->nge_head->m_pkthdr.len += total_len; 1635135250Swpaul sc->nge_tail->m_next = m; 1636135250Swpaul sc->nge_tail = m; 1637135250Swpaul } 1638135250Swpaul continue; 1639135250Swpaul } 1640135250Swpaul 164176479Swpaul /* 164276479Swpaul * If an error occurs, update stats, clear the 164376479Swpaul * status word and leave the mbuf cluster in place: 164476479Swpaul * it should simply get re-used next time this descriptor 164576479Swpaul * comes up in the ring. 164676479Swpaul */ 1647192506Syongari if ((cmdsts & NGE_CMDSTS_PKT_OK) == 0) { 1648192506Syongari if ((cmdsts & NGE_RXSTAT_RUNT) && 1649192506Syongari total_len >= (ETHER_MIN_LEN - ETHER_CRC_LEN - 4)) { 1650192506Syongari /* 1651192506Syongari * Work-around hardware bug, accept runt frames 1652192506Syongari * if its length is larger than or equal to 56. 1653192506Syongari */ 1654192506Syongari } else { 1655192506Syongari /* 1656192506Syongari * Input error counters are updated by hardware. 1657192506Syongari */ 1658192506Syongari if (sc->nge_head != NULL) { 1659192506Syongari m_freem(sc->nge_head); 1660192506Syongari sc->nge_head = sc->nge_tail = NULL; 1661192506Syongari } 1662192506Syongari nge_discard_rxbuf(sc, cons); 1663192506Syongari continue; 1664135250Swpaul } 166576479Swpaul } 166676479Swpaul 1667135250Swpaul /* Try conjure up a replacement mbuf. */ 1668135250Swpaul 1669192506Syongari if (nge_newbuf(sc, cons) != 0) { 1670192506Syongari ifp->if_iqdrops++; 1671135250Swpaul if (sc->nge_head != NULL) { 1672135250Swpaul m_freem(sc->nge_head); 1673135250Swpaul sc->nge_head = sc->nge_tail = NULL; 1674135250Swpaul } 1675192506Syongari nge_discard_rxbuf(sc, cons); 1676135250Swpaul continue; 1677135250Swpaul } 1678135250Swpaul 1679192506Syongari /* Chain received mbufs. */ 1680135250Swpaul if (sc->nge_head != NULL) { 1681135250Swpaul m->m_len = total_len; 1682135250Swpaul m->m_flags &= ~M_PKTHDR; 1683135250Swpaul sc->nge_tail->m_next = m; 1684135250Swpaul m = sc->nge_head; 1685135250Swpaul m->m_pkthdr.len += total_len; 1686135250Swpaul sc->nge_head = sc->nge_tail = NULL; 1687135250Swpaul } else 1688135250Swpaul m->m_pkthdr.len = m->m_len = total_len; 1689135250Swpaul 169076479Swpaul /* 169176479Swpaul * Ok. NatSemi really screwed up here. This is the 169276479Swpaul * only gigE chip I know of with alignment constraints 169376479Swpaul * on receive buffers. RX buffers must be 64-bit aligned. 169476479Swpaul */ 169579562Swpaul /* 169679562Swpaul * By popular demand, ignore the alignment problems 1697192506Syongari * on the non-strict alignment platform. The performance hit 169879562Swpaul * incurred due to unaligned accesses is much smaller 169979562Swpaul * than the hit produced by forcing buffer copies all 170079562Swpaul * the time, especially with jumbo frames. We still 170179562Swpaul * need to fix up the alignment everywhere else though. 170279562Swpaul */ 1703192506Syongari#ifndef __NO_STRICT_ALIGNMENT 1704135250Swpaul nge_fixup_rx(m); 170579562Swpaul#endif 1706192506Syongari m->m_pkthdr.rcvif = ifp; 170776479Swpaul ifp->if_ipackets++; 170876479Swpaul 1709192506Syongari if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) { 1710192506Syongari /* Do IP checksum checking. */ 1711192506Syongari if ((extsts & NGE_RXEXTSTS_IPPKT) != 0) 1712192506Syongari m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1713192506Syongari if ((extsts & NGE_RXEXTSTS_IPCSUMERR) == 0) 1714192506Syongari m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1715192506Syongari if ((extsts & NGE_RXEXTSTS_TCPPKT && 1716192506Syongari !(extsts & NGE_RXEXTSTS_TCPCSUMERR)) || 1717192506Syongari (extsts & NGE_RXEXTSTS_UDPPKT && 1718192506Syongari !(extsts & NGE_RXEXTSTS_UDPCSUMERR))) { 1719192506Syongari m->m_pkthdr.csum_flags |= 1720192506Syongari CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 1721192506Syongari m->m_pkthdr.csum_data = 0xffff; 1722192506Syongari } 172378323Swpaul } 172476479Swpaul 172576479Swpaul /* 172676479Swpaul * If we received a packet with a vlan tag, pass it 172776479Swpaul * to vlan_input() instead of ether_input(). 172876479Swpaul */ 1729192506Syongari if ((extsts & NGE_RXEXTSTS_VLANPKT) != 0 && 1730192506Syongari (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 1731162375Sandre m->m_pkthdr.ether_vtag = 1732192506Syongari bswap16(extsts & NGE_RXEXTSTS_VTCI); 1733162375Sandre m->m_flags |= M_VLANTAG; 1734106937Ssam } 1735135250Swpaul NGE_UNLOCK(sc); 1736106937Ssam (*ifp->if_input)(ifp, m); 1737135250Swpaul NGE_LOCK(sc); 1738193105Sattilio rx_npkts++; 173976479Swpaul } 174076479Swpaul 1741192506Syongari if (prog > 0) { 1742192506Syongari sc->nge_cdata.nge_rx_cons = cons; 1743192506Syongari bus_dmamap_sync(sc->nge_cdata.nge_rx_ring_tag, 1744192506Syongari sc->nge_cdata.nge_rx_ring_map, 1745192506Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1746192506Syongari } 1747193105Sattilio return (rx_npkts); 174876479Swpaul} 174976479Swpaul 175076479Swpaul/* 175176479Swpaul * A frame was downloaded to the chip. It's safe for us to clean up 175276479Swpaul * the list buffers. 175376479Swpaul */ 175499497Salfredstatic void 1755192288Syongaringe_txeof(struct nge_softc *sc) 175676479Swpaul{ 1757192506Syongari struct nge_desc *cur_tx; 1758192506Syongari struct nge_txdesc *txd; 1759192297Syongari struct ifnet *ifp; 1760192506Syongari uint32_t cmdsts; 1761192506Syongari int cons, prod; 176276479Swpaul 1763135250Swpaul NGE_LOCK_ASSERT(sc); 1764147256Sbrooks ifp = sc->nge_ifp; 176576479Swpaul 1766192506Syongari cons = sc->nge_cdata.nge_tx_cons; 1767192506Syongari prod = sc->nge_cdata.nge_tx_prod; 1768192506Syongari if (cons == prod) 1769192506Syongari return; 1770192506Syongari 1771192506Syongari bus_dmamap_sync(sc->nge_cdata.nge_tx_ring_tag, 1772192506Syongari sc->nge_cdata.nge_tx_ring_map, 1773192506Syongari BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1774192506Syongari 177576479Swpaul /* 177676479Swpaul * Go through our tx list and free mbufs for those 177776479Swpaul * frames that have been transmitted. 177876479Swpaul */ 1779192506Syongari for (; cons != prod; NGE_INC(cons, NGE_TX_RING_CNT)) { 1780192506Syongari cur_tx = &sc->nge_rdata.nge_tx_ring[cons]; 1781192506Syongari cmdsts = le32toh(cur_tx->nge_cmdsts); 1782192506Syongari if ((cmdsts & NGE_CMDSTS_OWN) != 0) 178376479Swpaul break; 1784192506Syongari sc->nge_cdata.nge_tx_cnt--; 1785192506Syongari ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1786192506Syongari if ((cmdsts & NGE_CMDSTS_MORE) != 0) 178776479Swpaul continue; 178876479Swpaul 1789192506Syongari txd = &sc->nge_cdata.nge_txdesc[cons]; 1790192506Syongari bus_dmamap_sync(sc->nge_cdata.nge_tx_tag, txd->tx_dmamap, 1791192506Syongari BUS_DMASYNC_POSTWRITE); 1792192506Syongari bus_dmamap_unload(sc->nge_cdata.nge_tx_tag, txd->tx_dmamap); 1793192506Syongari if ((cmdsts & NGE_CMDSTS_PKT_OK) == 0) { 179476479Swpaul ifp->if_oerrors++; 1795192506Syongari if ((cmdsts & NGE_TXSTAT_EXCESSCOLLS) != 0) 179676479Swpaul ifp->if_collisions++; 1797192506Syongari if ((cmdsts & NGE_TXSTAT_OUTOFWINCOLL) != 0) 179876479Swpaul ifp->if_collisions++; 1799192506Syongari } else 1800192506Syongari ifp->if_opackets++; 180176479Swpaul 1802192506Syongari ifp->if_collisions += (cmdsts & NGE_TXSTAT_COLLCNT) >> 16; 1803192506Syongari KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!\n", 1804192506Syongari __func__)); 1805192506Syongari m_freem(txd->tx_m); 1806192506Syongari txd->tx_m = NULL; 180776479Swpaul } 180876479Swpaul 1809192506Syongari sc->nge_cdata.nge_tx_cons = cons; 1810192506Syongari if (sc->nge_cdata.nge_tx_cnt == 0) 1811192506Syongari sc->nge_watchdog_timer = 0; 181276479Swpaul} 181376479Swpaul 181499497Salfredstatic void 1815192288Syongaringe_tick(void *xsc) 181676479Swpaul{ 1817192297Syongari struct nge_softc *sc; 1818192297Syongari struct mii_data *mii; 181976479Swpaul 1820151296Sjhb sc = xsc; 1821135250Swpaul NGE_LOCK_ASSERT(sc); 1822192506Syongari mii = device_get_softc(sc->nge_miibus); 1823192506Syongari mii_tick(mii); 1824192506Syongari /* 1825192506Syongari * For PHYs that does not reset established link, it is 1826192506Syongari * necessary to check whether driver still have a valid 1827192506Syongari * link(e.g link state change callback is not called). 1828192506Syongari * Otherwise, driver think it lost link because driver 1829192506Syongari * initialization routine clears link state flag. 1830192506Syongari */ 1831192506Syongari if ((sc->nge_flags & NGE_FLAG_LINK) == 0) 1832192506Syongari nge_miibus_statchg(sc->nge_dev); 1833192506Syongari nge_stats_update(sc); 1834192506Syongari nge_watchdog(sc); 1835192506Syongari callout_reset(&sc->nge_stat_ch, hz, nge_tick, sc); 1836192506Syongari} 1837192506Syongari 1838192506Syongaristatic void 1839192506Syongaringe_stats_update(struct nge_softc *sc) 1840192506Syongari{ 1841192506Syongari struct ifnet *ifp; 1842192506Syongari struct nge_stats now, *stats, *nstats; 1843192506Syongari 1844192506Syongari NGE_LOCK_ASSERT(sc); 1845192506Syongari 1846147256Sbrooks ifp = sc->nge_ifp; 1847192506Syongari stats = &now; 1848192506Syongari stats->rx_pkts_errs = 1849192506Syongari CSR_READ_4(sc, NGE_MIB_RXERRPKT) & 0xFFFF; 1850192506Syongari stats->rx_crc_errs = 1851192506Syongari CSR_READ_4(sc, NGE_MIB_RXERRFCS) & 0xFFFF; 1852192506Syongari stats->rx_fifo_oflows = 1853192506Syongari CSR_READ_4(sc, NGE_MIB_RXERRMISSEDPKT) & 0xFFFF; 1854192506Syongari stats->rx_align_errs = 1855192506Syongari CSR_READ_4(sc, NGE_MIB_RXERRALIGN) & 0xFFFF; 1856192506Syongari stats->rx_sym_errs = 1857192506Syongari CSR_READ_4(sc, NGE_MIB_RXERRSYM) & 0xFFFF; 1858192506Syongari stats->rx_pkts_jumbos = 1859192506Syongari CSR_READ_4(sc, NGE_MIB_RXERRGIANT) & 0xFFFF; 1860192506Syongari stats->rx_len_errs = 1861192506Syongari CSR_READ_4(sc, NGE_MIB_RXERRRANGLEN) & 0xFFFF; 1862192506Syongari stats->rx_unctl_frames = 1863192506Syongari CSR_READ_4(sc, NGE_MIB_RXBADOPCODE) & 0xFFFF; 1864192506Syongari stats->rx_pause = 1865192506Syongari CSR_READ_4(sc, NGE_MIB_RXPAUSEPKTS) & 0xFFFF; 1866192506Syongari stats->tx_pause = 1867192506Syongari CSR_READ_4(sc, NGE_MIB_TXPAUSEPKTS) & 0xFFFF; 1868192506Syongari stats->tx_seq_errs = 1869192506Syongari CSR_READ_4(sc, NGE_MIB_TXERRSQE) & 0xFF; 187076479Swpaul 1871192506Syongari /* 1872192506Syongari * Since we've accept errored frames exclude Rx length errors. 1873192506Syongari */ 1874192506Syongari ifp->if_ierrors += stats->rx_pkts_errs + stats->rx_crc_errs + 1875192506Syongari stats->rx_fifo_oflows + stats->rx_sym_errs; 1876101540Sambrisko 1877192506Syongari nstats = &sc->nge_stats; 1878192506Syongari nstats->rx_pkts_errs += stats->rx_pkts_errs; 1879192506Syongari nstats->rx_crc_errs += stats->rx_crc_errs; 1880192506Syongari nstats->rx_fifo_oflows += stats->rx_fifo_oflows; 1881192506Syongari nstats->rx_align_errs += stats->rx_align_errs; 1882192506Syongari nstats->rx_sym_errs += stats->rx_sym_errs; 1883192506Syongari nstats->rx_pkts_jumbos += stats->rx_pkts_jumbos; 1884192506Syongari nstats->rx_len_errs += stats->rx_len_errs; 1885192506Syongari nstats->rx_unctl_frames += stats->rx_unctl_frames; 1886192506Syongari nstats->rx_pause += stats->rx_pause; 1887192506Syongari nstats->tx_pause += stats->tx_pause; 1888192506Syongari nstats->tx_seq_errs += stats->tx_seq_errs; 188976479Swpaul} 189076479Swpaul 1891106507Ssimokawa#ifdef DEVICE_POLLING 1892106507Ssimokawastatic poll_handler_t nge_poll; 1893106507Ssimokawa 1894193105Sattiliostatic int 1895106507Ssimokawange_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1896106507Ssimokawa{ 1897192506Syongari struct nge_softc *sc; 1898193105Sattilio int rx_npkts = 0; 1899106507Ssimokawa 1900192506Syongari sc = ifp->if_softc; 1901192506Syongari 1902135250Swpaul NGE_LOCK(sc); 1903192506Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1904135250Swpaul NGE_UNLOCK(sc); 1905193105Sattilio return (rx_npkts); 1906106507Ssimokawa } 1907106507Ssimokawa 1908106507Ssimokawa /* 1909106507Ssimokawa * On the nge, reading the status register also clears it. 1910106507Ssimokawa * So before returning to intr mode we must make sure that all 1911106507Ssimokawa * possible pending sources of interrupts have been served. 1912106507Ssimokawa * In practice this means run to completion the *eof routines, 1913192506Syongari * and then call the interrupt routine. 1914106507Ssimokawa */ 1915106507Ssimokawa sc->rxcycles = count; 1916193105Sattilio rx_npkts = nge_rxeof(sc); 1917106507Ssimokawa nge_txeof(sc); 1918192506Syongari if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1919135250Swpaul nge_start_locked(ifp); 1920106507Ssimokawa 1921106507Ssimokawa if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1922192294Syongari uint32_t status; 1923106507Ssimokawa 1924106507Ssimokawa /* Reading the ISR register clears all interrupts. */ 1925106507Ssimokawa status = CSR_READ_4(sc, NGE_ISR); 1926106507Ssimokawa 1927192506Syongari if ((status & (NGE_ISR_RX_ERR|NGE_ISR_RX_OFLOW)) != 0) 1928193105Sattilio rx_npkts += nge_rxeof(sc); 1929106507Ssimokawa 1930192506Syongari if ((status & NGE_ISR_RX_IDLE) != 0) 1931106507Ssimokawa NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1932106507Ssimokawa 1933192506Syongari if ((status & NGE_ISR_SYSERR) != 0) { 1934192506Syongari ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1935135250Swpaul nge_init_locked(sc); 1936106507Ssimokawa } 1937106507Ssimokawa } 1938135250Swpaul NGE_UNLOCK(sc); 1939193105Sattilio return (rx_npkts); 1940106507Ssimokawa} 1941106507Ssimokawa#endif /* DEVICE_POLLING */ 1942106507Ssimokawa 1943106507Ssimokawastatic void 1944192288Syongaringe_intr(void *arg) 194576479Swpaul{ 1946192297Syongari struct nge_softc *sc; 1947192297Syongari struct ifnet *ifp; 1948192297Syongari uint32_t status; 194976479Swpaul 1950192506Syongari sc = (struct nge_softc *)arg; 1951147256Sbrooks ifp = sc->nge_ifp; 195276479Swpaul 1953135250Swpaul NGE_LOCK(sc); 1954192506Syongari 1955192506Syongari if ((sc->nge_flags & NGE_FLAG_SUSPENDED) != 0) 1956192506Syongari goto done_locked; 1957192506Syongari 1958192506Syongari /* Reading the ISR register clears all interrupts. */ 1959192506Syongari status = CSR_READ_4(sc, NGE_ISR); 1960192506Syongari if (status == 0xffffffff || (status & NGE_INTRS) == 0) 1961192506Syongari goto done_locked; 1962106507Ssimokawa#ifdef DEVICE_POLLING 1963192506Syongari if ((ifp->if_capenable & IFCAP_POLLING) != 0) 1964192506Syongari goto done_locked; 1965150789Sglebius#endif 1966192506Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1967192506Syongari goto done_locked; 1968106507Ssimokawa 196976479Swpaul /* Disable interrupts. */ 197076479Swpaul CSR_WRITE_4(sc, NGE_IER, 0); 197176479Swpaul 1972101540Sambrisko /* Data LED on for TBI mode */ 1973192506Syongari if ((sc->nge_flags & NGE_FLAG_TBI) != 0) 1974192506Syongari CSR_WRITE_4(sc, NGE_GPIO, 1975192506Syongari CSR_READ_4(sc, NGE_GPIO) | NGE_GPIO_GP3_OUT); 1976101540Sambrisko 1977192506Syongari for (; (status & NGE_INTRS) != 0;) { 1978192506Syongari if ((status & (NGE_ISR_TX_DESC_OK | NGE_ISR_TX_ERR | 1979192506Syongari NGE_ISR_TX_OK | NGE_ISR_TX_IDLE)) != 0) 198076479Swpaul nge_txeof(sc); 198176479Swpaul 1982192506Syongari if ((status & (NGE_ISR_RX_DESC_OK | NGE_ISR_RX_ERR | 1983192506Syongari NGE_ISR_RX_OFLOW | NGE_ISR_RX_FIFO_OFLOW | 1984192506Syongari NGE_ISR_RX_IDLE | NGE_ISR_RX_OK)) != 0) 198576479Swpaul nge_rxeof(sc); 198694612Sphk 1987192506Syongari if ((status & NGE_ISR_RX_IDLE) != 0) 198894612Sphk NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 198994612Sphk 1990192506Syongari if ((status & NGE_ISR_SYSERR) != 0) { 1991148887Srwatson ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1992135250Swpaul nge_init_locked(sc); 199376479Swpaul } 1994192506Syongari /* Reading the ISR register clears all interrupts. */ 1995192506Syongari status = CSR_READ_4(sc, NGE_ISR); 199676479Swpaul } 199776479Swpaul 199876479Swpaul /* Re-enable interrupts. */ 199976479Swpaul CSR_WRITE_4(sc, NGE_IER, 1); 200076479Swpaul 2001192506Syongari if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2002135250Swpaul nge_start_locked(ifp); 200376479Swpaul 2004101540Sambrisko /* Data LED off for TBI mode */ 2005192506Syongari if ((sc->nge_flags & NGE_FLAG_TBI) != 0) 2006192506Syongari CSR_WRITE_4(sc, NGE_GPIO, 2007192506Syongari CSR_READ_4(sc, NGE_GPIO) & ~NGE_GPIO_GP3_OUT); 2008101540Sambrisko 2009192506Syongaridone_locked: 2010135250Swpaul NGE_UNLOCK(sc); 201176479Swpaul} 201276479Swpaul 201376479Swpaul/* 201476479Swpaul * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 201576479Swpaul * pointers to the fragment pointers. 201676479Swpaul */ 201799497Salfredstatic int 2018192506Syongaringe_encap(struct nge_softc *sc, struct mbuf **m_head) 201976479Swpaul{ 2020192506Syongari struct nge_txdesc *txd, *txd_last; 2021192506Syongari struct nge_desc *desc; 2022192297Syongari struct mbuf *m; 2023192506Syongari bus_dmamap_t map; 2024192506Syongari bus_dma_segment_t txsegs[NGE_MAXTXSEGS]; 2025192506Syongari int error, i, nsegs, prod, si; 202676479Swpaul 2027192506Syongari NGE_LOCK_ASSERT(sc); 202876479Swpaul 2029192506Syongari m = *m_head; 2030192506Syongari prod = sc->nge_cdata.nge_tx_prod; 2031192506Syongari txd = &sc->nge_cdata.nge_txdesc[prod]; 2032192506Syongari txd_last = txd; 2033192506Syongari map = txd->tx_dmamap; 2034192506Syongari error = bus_dmamap_load_mbuf_sg(sc->nge_cdata.nge_tx_tag, map, 2035192506Syongari *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT); 2036192506Syongari if (error == EFBIG) { 2037192506Syongari m = m_collapse(*m_head, M_DONTWAIT, NGE_MAXTXSEGS); 2038192506Syongari if (m == NULL) { 2039192506Syongari m_freem(*m_head); 2040192506Syongari *m_head = NULL; 2041192506Syongari return (ENOBUFS); 204276479Swpaul } 2043192506Syongari *m_head = m; 2044192506Syongari error = bus_dmamap_load_mbuf_sg(sc->nge_cdata.nge_tx_tag, 2045192506Syongari map, *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT); 2046192506Syongari if (error != 0) { 2047192506Syongari m_freem(*m_head); 2048192506Syongari *m_head = NULL; 2049192506Syongari return (error); 2050192506Syongari } 2051192506Syongari } else if (error != 0) 2052192506Syongari return (error); 2053192506Syongari if (nsegs == 0) { 2054192506Syongari m_freem(*m_head); 2055192506Syongari *m_head = NULL; 2056192506Syongari return (EIO); 205776479Swpaul } 205876479Swpaul 2059192506Syongari /* Check number of available descriptors. */ 2060192506Syongari if (sc->nge_cdata.nge_tx_cnt + nsegs >= (NGE_TX_RING_CNT - 1)) { 2061192506Syongari bus_dmamap_unload(sc->nge_cdata.nge_tx_tag, map); 2062192292Syongari return (ENOBUFS); 2063192506Syongari } 206476479Swpaul 2065192506Syongari bus_dmamap_sync(sc->nge_cdata.nge_tx_tag, map, BUS_DMASYNC_PREWRITE); 2066192506Syongari 2067192506Syongari si = prod; 2068192506Syongari for (i = 0; i < nsegs; i++) { 2069192506Syongari desc = &sc->nge_rdata.nge_tx_ring[prod]; 2070192506Syongari desc->nge_ptr = htole32(NGE_ADDR_LO(txsegs[i].ds_addr)); 2071192506Syongari if (i == 0) 2072192506Syongari desc->nge_cmdsts = htole32(txsegs[i].ds_len | 2073192506Syongari NGE_CMDSTS_MORE); 2074192506Syongari else 2075192506Syongari desc->nge_cmdsts = htole32(txsegs[i].ds_len | 2076192506Syongari NGE_CMDSTS_MORE | NGE_CMDSTS_OWN); 2077192506Syongari desc->nge_extsts = 0; 2078192506Syongari sc->nge_cdata.nge_tx_cnt++; 2079192506Syongari NGE_INC(prod, NGE_TX_RING_CNT); 208076479Swpaul } 2081192506Syongari /* Update producer index. */ 2082192506Syongari sc->nge_cdata.nge_tx_prod = prod; 208376479Swpaul 2084192506Syongari prod = (prod + NGE_TX_RING_CNT - 1) % NGE_TX_RING_CNT; 2085192506Syongari desc = &sc->nge_rdata.nge_tx_ring[prod]; 2086192506Syongari /* Check if we have a VLAN tag to insert. */ 2087192506Syongari if ((m->m_flags & M_VLANTAG) != 0) 2088192506Syongari desc->nge_extsts |= htole32(NGE_TXEXTSTS_VLANPKT | 2089192506Syongari bswap16(m->m_pkthdr.ether_vtag)); 2090192506Syongari /* Set EOP on the last desciptor. */ 2091192506Syongari desc->nge_cmdsts &= htole32(~NGE_CMDSTS_MORE); 2092192506Syongari 2093192506Syongari /* Set checksum offload in the first descriptor. */ 2094192506Syongari desc = &sc->nge_rdata.nge_tx_ring[si]; 2095192506Syongari if ((m->m_pkthdr.csum_flags & NGE_CSUM_FEATURES) != 0) { 2096192506Syongari if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 2097192506Syongari desc->nge_extsts |= htole32(NGE_TXEXTSTS_IPCSUM); 2098192506Syongari if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 2099192506Syongari desc->nge_extsts |= htole32(NGE_TXEXTSTS_TCPCSUM); 2100192506Syongari if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2101192506Syongari desc->nge_extsts |= htole32(NGE_TXEXTSTS_UDPCSUM); 210276479Swpaul } 2103192506Syongari /* Lastly, turn the first descriptor ownership to hardware. */ 2104192506Syongari desc->nge_cmdsts |= htole32(NGE_CMDSTS_OWN); 210576479Swpaul 2106192506Syongari txd = &sc->nge_cdata.nge_txdesc[prod]; 2107192506Syongari map = txd_last->tx_dmamap; 2108192506Syongari txd_last->tx_dmamap = txd->tx_dmamap; 2109192506Syongari txd->tx_dmamap = map; 2110192506Syongari txd->tx_m = m; 211176479Swpaul 2112192292Syongari return (0); 211376479Swpaul} 211476479Swpaul 211576479Swpaul/* 211676479Swpaul * Main transmit routine. To avoid having to do mbuf copies, we put pointers 211776479Swpaul * to the mbuf data regions directly in the transmit lists. We also save a 211876479Swpaul * copy of the pointers since the transmit list fragment pointers are 211976479Swpaul * physical addresses. 212076479Swpaul */ 212176479Swpaul 212299497Salfredstatic void 2123192288Syongaringe_start(struct ifnet *ifp) 212476479Swpaul{ 2125192297Syongari struct nge_softc *sc; 2126135250Swpaul 2127135250Swpaul sc = ifp->if_softc; 2128135250Swpaul NGE_LOCK(sc); 2129135250Swpaul nge_start_locked(ifp); 2130135250Swpaul NGE_UNLOCK(sc); 2131135250Swpaul} 2132135250Swpaul 2133135250Swpaulstatic void 2134192288Syongaringe_start_locked(struct ifnet *ifp) 2135135250Swpaul{ 2136192297Syongari struct nge_softc *sc; 2137192506Syongari struct mbuf *m_head; 2138192506Syongari int enq; 213976479Swpaul 214076479Swpaul sc = ifp->if_softc; 214176479Swpaul 2142192506Syongari NGE_LOCK_ASSERT(sc); 214376479Swpaul 2144192506Syongari if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2145192506Syongari IFF_DRV_RUNNING || (sc->nge_flags & NGE_FLAG_LINK) == 0) 214676479Swpaul return; 214776479Swpaul 2148192506Syongari for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2149192506Syongari sc->nge_cdata.nge_tx_cnt < NGE_TX_RING_CNT - 2; ) { 2150192506Syongari IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 215176479Swpaul if (m_head == NULL) 215276479Swpaul break; 2153192506Syongari /* 2154192506Syongari * Pack the data into the transmit ring. If we 2155192506Syongari * don't have room, set the OACTIVE flag and wait 2156192506Syongari * for the NIC to drain the ring. 2157192506Syongari */ 2158192506Syongari if (nge_encap(sc, &m_head)) { 2159192506Syongari if (m_head == NULL) 2160192506Syongari break; 2161192506Syongari IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2162148887Srwatson ifp->if_drv_flags |= IFF_DRV_OACTIVE; 216376479Swpaul break; 216476479Swpaul } 216576479Swpaul 2166192506Syongari enq++; 216776479Swpaul /* 216876479Swpaul * If there's a BPF listener, bounce a copy of this frame 216976479Swpaul * to him. 217076479Swpaul */ 2171167190Scsjp ETHER_BPF_MTAP(ifp, m_head); 217276479Swpaul } 217376479Swpaul 2174192506Syongari if (enq > 0) { 2175192506Syongari bus_dmamap_sync(sc->nge_cdata.nge_tx_ring_tag, 2176192506Syongari sc->nge_cdata.nge_tx_ring_map, 2177192506Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2178192506Syongari /* Transmit */ 2179192506Syongari NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_ENABLE); 218076479Swpaul 2181192506Syongari /* Set a timeout in case the chip goes out to lunch. */ 2182192506Syongari sc->nge_watchdog_timer = 5; 2183192506Syongari } 218476479Swpaul} 218576479Swpaul 218699497Salfredstatic void 2187192288Syongaringe_init(void *xsc) 218876479Swpaul{ 2189192297Syongari struct nge_softc *sc = xsc; 2190135250Swpaul 2191135250Swpaul NGE_LOCK(sc); 2192135250Swpaul nge_init_locked(sc); 2193135250Swpaul NGE_UNLOCK(sc); 2194135250Swpaul} 2195135250Swpaul 2196135250Swpaulstatic void 2197192288Syongaringe_init_locked(struct nge_softc *sc) 2198135250Swpaul{ 2199192297Syongari struct ifnet *ifp = sc->nge_ifp; 2200192297Syongari struct mii_data *mii; 2201192506Syongari uint8_t *eaddr; 2202192506Syongari uint32_t reg; 220376479Swpaul 2204135250Swpaul NGE_LOCK_ASSERT(sc); 2205135250Swpaul 2206192506Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 220776479Swpaul return; 220876479Swpaul 220976479Swpaul /* 221076479Swpaul * Cancel pending I/O and free all RX/TX buffers. 221176479Swpaul */ 221276479Swpaul nge_stop(sc); 221376479Swpaul 2214192506Syongari /* Reset the adapter. */ 2215192506Syongari nge_reset(sc); 221676479Swpaul 2217192506Syongari /* Disable Rx filter prior to programming Rx filter. */ 2218192506Syongari CSR_WRITE_4(sc, NGE_RXFILT_CTL, 0); 2219192506Syongari CSR_BARRIER_WRITE_4(sc, NGE_RXFILT_CTL); 2220192506Syongari 2221192506Syongari mii = device_get_softc(sc->nge_miibus); 2222192506Syongari 2223192506Syongari /* Set MAC address. */ 2224192506Syongari eaddr = IF_LLADDR(sc->nge_ifp); 222576479Swpaul CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0); 2226192506Syongari CSR_WRITE_4(sc, NGE_RXFILT_DATA, (eaddr[1] << 8) | eaddr[0]); 222776479Swpaul CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR1); 2228192506Syongari CSR_WRITE_4(sc, NGE_RXFILT_DATA, (eaddr[3] << 8) | eaddr[2]); 222976479Swpaul CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR2); 2230192506Syongari CSR_WRITE_4(sc, NGE_RXFILT_DATA, (eaddr[5] << 8) | eaddr[4]); 223176479Swpaul 223276479Swpaul /* Init circular RX list. */ 223376479Swpaul if (nge_list_rx_init(sc) == ENOBUFS) { 2234162321Sglebius device_printf(sc->nge_dev, "initialization failed: no " 2235151296Sjhb "memory for rx buffers\n"); 223676479Swpaul nge_stop(sc); 223776479Swpaul return; 223876479Swpaul } 223976479Swpaul 224076479Swpaul /* 224176479Swpaul * Init tx descriptors. 224276479Swpaul */ 224376479Swpaul nge_list_tx_init(sc); 224476479Swpaul 224576479Swpaul /* 224676479Swpaul * For the NatSemi chip, we have to explicitly enable the 224776479Swpaul * reception of ARP frames, as well as turn on the 'perfect 224876479Swpaul * match' filter where we store the station address, otherwise 224976479Swpaul * we won't receive unicasts meant for this host. 225076479Swpaul */ 225176479Swpaul NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ARP); 225276479Swpaul NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_PERFECT); 225376479Swpaul 225476479Swpaul /* 225576479Swpaul * Set the capture broadcast bit to capture broadcast frames. 225676479Swpaul */ 225776479Swpaul if (ifp->if_flags & IFF_BROADCAST) { 225876479Swpaul NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD); 225976479Swpaul } else { 226076479Swpaul NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD); 226176479Swpaul } 226276479Swpaul 2263192506Syongari /* Turn the receive filter on. */ 2264192506Syongari NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ENABLE); 2265192506Syongari 2266192506Syongari /* Set Rx filter. */ 2267192506Syongari nge_rxfilter(sc); 2268192506Syongari 2269192506Syongari /* Disable PRIQ ctl. */ 2270192506Syongari CSR_WRITE_4(sc, NGE_PRIOQCTL, 0); 2271192506Syongari 227276479Swpaul /* 2273192506Syongari * Set pause frames paramters. 2274192506Syongari * Rx stat FIFO hi-threshold : 2 or more packets 2275192506Syongari * Rx stat FIFO lo-threshold : less than 2 packets 2276192506Syongari * Rx data FIFO hi-threshold : 2K or more bytes 2277192506Syongari * Rx data FIFO lo-threshold : less than 2K bytes 2278192506Syongari * pause time : (512ns * 0xffff) -> 33.55ms 227976479Swpaul */ 2280192506Syongari CSR_WRITE_4(sc, NGE_PAUSECSR, 2281192506Syongari NGE_PAUSECSR_PAUSE_ON_MCAST | 2282192506Syongari NGE_PAUSECSR_PAUSE_ON_DA | 2283192506Syongari ((1 << 24) & NGE_PAUSECSR_RX_STATFIFO_THR_HI) | 2284192506Syongari ((1 << 22) & NGE_PAUSECSR_RX_STATFIFO_THR_LO) | 2285192506Syongari ((1 << 20) & NGE_PAUSECSR_RX_DATAFIFO_THR_HI) | 2286192506Syongari ((1 << 18) & NGE_PAUSECSR_RX_DATAFIFO_THR_LO) | 2287192506Syongari NGE_PAUSECSR_CNT); 228876479Swpaul 228976479Swpaul /* 229076479Swpaul * Load the address of the RX and TX lists. 229176479Swpaul */ 2292192506Syongari CSR_WRITE_4(sc, NGE_RX_LISTPTR_HI, 2293192506Syongari NGE_ADDR_HI(sc->nge_rdata.nge_rx_ring_paddr)); 2294192506Syongari CSR_WRITE_4(sc, NGE_RX_LISTPTR_LO, 2295192506Syongari NGE_ADDR_LO(sc->nge_rdata.nge_rx_ring_paddr)); 2296192506Syongari CSR_WRITE_4(sc, NGE_TX_LISTPTR_HI, 2297192506Syongari NGE_ADDR_HI(sc->nge_rdata.nge_tx_ring_paddr)); 2298192506Syongari CSR_WRITE_4(sc, NGE_TX_LISTPTR_LO, 2299192506Syongari NGE_ADDR_LO(sc->nge_rdata.nge_tx_ring_paddr)); 230076479Swpaul 2301192506Syongari /* Set RX configuration. */ 230276479Swpaul CSR_WRITE_4(sc, NGE_RX_CFG, NGE_RXCFG); 2303192506Syongari 2304192506Syongari CSR_WRITE_4(sc, NGE_VLAN_IP_RXCTL, 0); 230576479Swpaul /* 230676479Swpaul * Enable hardware checksum validation for all IPv4 230776479Swpaul * packets, do not reject packets with bad checksums. 230876479Swpaul */ 2309192506Syongari if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2310192506Syongari NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_IPCSUM_ENB); 231176479Swpaul 231276479Swpaul /* 231383115Sbrooks * Tell the chip to detect and strip VLAN tag info from 231483115Sbrooks * received frames. The tag will be provided in the extsts 231583115Sbrooks * field in the RX descriptors. 231676479Swpaul */ 2317192506Syongari NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_TAG_DETECT_ENB); 2318192506Syongari if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2319192506Syongari NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_TAG_STRIP_ENB); 232076479Swpaul 2321192506Syongari /* Set TX configuration. */ 232276479Swpaul CSR_WRITE_4(sc, NGE_TX_CFG, NGE_TXCFG); 232376479Swpaul 232476479Swpaul /* 232576479Swpaul * Enable TX IPv4 checksumming on a per-packet basis. 232676479Swpaul */ 232778323Swpaul CSR_WRITE_4(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_CSUM_PER_PKT); 232876479Swpaul 232976479Swpaul /* 233083115Sbrooks * Tell the chip to insert VLAN tags on a per-packet basis as 233183115Sbrooks * dictated by the code in the frame encapsulation routine. 233276479Swpaul */ 233376479Swpaul NGE_SETBIT(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_TAG_PER_PKT); 233476479Swpaul 233576479Swpaul /* 233676479Swpaul * Enable the delivery of PHY interrupts based on 233777842Swpaul * link/speed/duplex status changes. Also enable the 233877842Swpaul * extsts field in the DMA descriptors (needed for 233977842Swpaul * TCP/IP checksum offload on transmit). 234076479Swpaul */ 2341192506Syongari NGE_SETBIT(sc, NGE_CFG, NGE_CFG_PHYINTR_SPD | 2342192506Syongari NGE_CFG_PHYINTR_LNK | NGE_CFG_PHYINTR_DUP | NGE_CFG_EXTSTS_ENB); 234376479Swpaul 234476479Swpaul /* 234579562Swpaul * Configure interrupt holdoff (moderation). We can 234679562Swpaul * have the chip delay interrupt delivery for a certain 234779562Swpaul * period. Units are in 100us, and the max setting 234879562Swpaul * is 25500us (0xFF x 100us). Default is a 100us holdoff. 234979562Swpaul */ 2350192506Syongari CSR_WRITE_4(sc, NGE_IHR, sc->nge_int_holdoff); 235179562Swpaul 235279562Swpaul /* 2353192506Syongari * Enable MAC statistics counters and clear. 2354192506Syongari */ 2355192506Syongari reg = CSR_READ_4(sc, NGE_MIBCTL); 2356192506Syongari reg &= ~NGE_MIBCTL_FREEZE_CNT; 2357192506Syongari reg |= NGE_MIBCTL_CLEAR_CNT; 2358192506Syongari CSR_WRITE_4(sc, NGE_MIBCTL, reg); 2359192506Syongari 2360192506Syongari /* 236176479Swpaul * Enable interrupts. 236276479Swpaul */ 236376479Swpaul CSR_WRITE_4(sc, NGE_IMR, NGE_INTRS); 2364106507Ssimokawa#ifdef DEVICE_POLLING 2365106507Ssimokawa /* 2366106507Ssimokawa * ... only enable interrupts if we are not polling, make sure 2367106507Ssimokawa * they are off otherwise. 2368106507Ssimokawa */ 2369192506Syongari if ((ifp->if_capenable & IFCAP_POLLING) != 0) 2370106507Ssimokawa CSR_WRITE_4(sc, NGE_IER, 0); 2371106507Ssimokawa else 2372150789Sglebius#endif 237376479Swpaul CSR_WRITE_4(sc, NGE_IER, 1); 237476479Swpaul 2375192506Syongari sc->nge_flags &= ~NGE_FLAG_LINK; 2376192506Syongari mii_mediachg(mii); 237776479Swpaul 2378192506Syongari sc->nge_watchdog_timer = 0; 2379192506Syongari callout_reset(&sc->nge_stat_ch, hz, nge_tick, sc); 238076479Swpaul 2381148887Srwatson ifp->if_drv_flags |= IFF_DRV_RUNNING; 2382148887Srwatson ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 238376479Swpaul} 238476479Swpaul 238576479Swpaul/* 238676479Swpaul * Set media options. 238776479Swpaul */ 238899497Salfredstatic int 2389192506Syongaringe_mediachange(struct ifnet *ifp) 239076479Swpaul{ 2391192297Syongari struct nge_softc *sc; 2392192506Syongari struct mii_data *mii; 2393192506Syongari struct mii_softc *miisc; 2394192506Syongari int error; 2395151296Sjhb 2396151296Sjhb sc = ifp->if_softc; 2397151296Sjhb NGE_LOCK(sc); 2398192506Syongari mii = device_get_softc(sc->nge_miibus); 2399192506Syongari if (mii->mii_instance) { 2400192506Syongari LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2401192506Syongari mii_phy_reset(miisc); 2402192506Syongari } 2403192506Syongari error = mii_mediachg(mii); 2404151296Sjhb NGE_UNLOCK(sc); 2405151296Sjhb 2406192506Syongari return (error); 240776479Swpaul} 240876479Swpaul 240976479Swpaul/* 241076479Swpaul * Report current media status. 241176479Swpaul */ 241299497Salfredstatic void 2413192506Syongaringe_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 241476479Swpaul{ 2415192297Syongari struct nge_softc *sc; 2416192297Syongari struct mii_data *mii; 241776479Swpaul 241876479Swpaul sc = ifp->if_softc; 2419151296Sjhb NGE_LOCK(sc); 2420192506Syongari mii = device_get_softc(sc->nge_miibus); 2421192506Syongari mii_pollstat(mii); 2422151296Sjhb NGE_UNLOCK(sc); 2423192506Syongari ifmr->ifm_active = mii->mii_media_active; 2424192506Syongari ifmr->ifm_status = mii->mii_media_status; 242576479Swpaul} 242676479Swpaul 242799497Salfredstatic int 2428192288Syongaringe_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 242976479Swpaul{ 2430192297Syongari struct nge_softc *sc = ifp->if_softc; 2431192297Syongari struct ifreq *ifr = (struct ifreq *) data; 2432192297Syongari struct mii_data *mii; 2433192506Syongari int error = 0, mask; 243476479Swpaul 2435192292Syongari switch (command) { 243676479Swpaul case SIOCSIFMTU: 2437192506Syongari if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > NGE_JUMBO_MTU) 243876479Swpaul error = EINVAL; 243978323Swpaul else { 2440151296Sjhb NGE_LOCK(sc); 244176479Swpaul ifp->if_mtu = ifr->ifr_mtu; 244278323Swpaul /* 244378323Swpaul * Workaround: if the MTU is larger than 244478323Swpaul * 8152 (TX FIFO size minus 64 minus 18), turn off 244578323Swpaul * TX checksum offloading. 244678323Swpaul */ 2447129632Syar if (ifr->ifr_mtu >= 8152) { 2448129632Syar ifp->if_capenable &= ~IFCAP_TXCSUM; 2449192506Syongari ifp->if_hwassist &= ~NGE_CSUM_FEATURES; 2450129632Syar } else { 2451129632Syar ifp->if_capenable |= IFCAP_TXCSUM; 2452192506Syongari ifp->if_hwassist |= NGE_CSUM_FEATURES; 2453129632Syar } 2454151296Sjhb NGE_UNLOCK(sc); 2455192506Syongari VLAN_CAPABILITIES(ifp); 245678323Swpaul } 245776479Swpaul break; 245876479Swpaul case SIOCSIFFLAGS: 2459135250Swpaul NGE_LOCK(sc); 2460192506Syongari if ((ifp->if_flags & IFF_UP) != 0) { 2461192506Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2462192506Syongari if ((ifp->if_flags ^ sc->nge_if_flags) & 2463192506Syongari (IFF_PROMISC | IFF_ALLMULTI)) 2464192506Syongari nge_rxfilter(sc); 246576479Swpaul } else { 2466192506Syongari if ((sc->nge_flags & NGE_FLAG_DETACH) == 0) 2467192506Syongari nge_init_locked(sc); 246876479Swpaul } 246976479Swpaul } else { 2470192506Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 247176479Swpaul nge_stop(sc); 247276479Swpaul } 247376479Swpaul sc->nge_if_flags = ifp->if_flags; 2474135250Swpaul NGE_UNLOCK(sc); 247576479Swpaul error = 0; 247676479Swpaul break; 247776479Swpaul case SIOCADDMULTI: 247876479Swpaul case SIOCDELMULTI: 2479135250Swpaul NGE_LOCK(sc); 2480192506Syongari nge_rxfilter(sc); 2481135250Swpaul NGE_UNLOCK(sc); 248276479Swpaul error = 0; 248376479Swpaul break; 248476479Swpaul case SIOCGIFMEDIA: 248576479Swpaul case SIOCSIFMEDIA: 2486192506Syongari mii = device_get_softc(sc->nge_miibus); 2487192506Syongari error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 248876479Swpaul break; 2489128132Sru case SIOCSIFCAP: 2490192506Syongari NGE_LOCK(sc); 2491192506Syongari mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2492150789Sglebius#ifdef DEVICE_POLLING 2493192506Syongari if ((mask & IFCAP_POLLING) != 0 && 2494192506Syongari (IFCAP_POLLING & ifp->if_capabilities) != 0) { 2495192506Syongari ifp->if_capenable ^= IFCAP_POLLING; 2496192506Syongari if ((IFCAP_POLLING & ifp->if_capenable) != 0) { 2497192506Syongari error = ether_poll_register(nge_poll, ifp); 2498192506Syongari if (error != 0) { 2499192506Syongari NGE_UNLOCK(sc); 2500192506Syongari break; 2501192506Syongari } 2502192506Syongari /* Disable interrupts. */ 2503192506Syongari CSR_WRITE_4(sc, NGE_IER, 0); 2504192506Syongari } else { 2505192506Syongari error = ether_poll_deregister(ifp); 2506192506Syongari /* Enable interrupts. */ 2507192506Syongari CSR_WRITE_4(sc, NGE_IER, 1); 2508192506Syongari } 2509192506Syongari } 2510192506Syongari#endif /* DEVICE_POLLING */ 2511192506Syongari if ((mask & IFCAP_TXCSUM) != 0 && 2512192506Syongari (IFCAP_TXCSUM & ifp->if_capabilities) != 0) { 2513192506Syongari ifp->if_capenable ^= IFCAP_TXCSUM; 2514192506Syongari if ((IFCAP_TXCSUM & ifp->if_capenable) != 0) 2515192506Syongari ifp->if_hwassist |= NGE_CSUM_FEATURES; 2516192506Syongari else 2517192506Syongari ifp->if_hwassist &= ~NGE_CSUM_FEATURES; 2518192506Syongari } 2519192506Syongari if ((mask & IFCAP_RXCSUM) != 0 && 2520192506Syongari (IFCAP_RXCSUM & ifp->if_capabilities) != 0) 2521192506Syongari ifp->if_capenable ^= IFCAP_RXCSUM; 2522192290Syongari 2523192506Syongari if ((mask & IFCAP_WOL) != 0 && 2524192506Syongari (ifp->if_capabilities & IFCAP_WOL) != 0) { 2525192506Syongari if ((mask & IFCAP_WOL_UCAST) != 0) 2526192506Syongari ifp->if_capenable ^= IFCAP_WOL_UCAST; 2527192506Syongari if ((mask & IFCAP_WOL_MCAST) != 0) 2528192506Syongari ifp->if_capenable ^= IFCAP_WOL_MCAST; 2529192506Syongari if ((mask & IFCAP_WOL_MAGIC) != 0) 2530192506Syongari ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2531150789Sglebius } 2532192506Syongari 2533192506Syongari if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2534192506Syongari (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 2535192506Syongari ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 2536192506Syongari if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2537192506Syongari (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 2538192506Syongari ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2539192506Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2540192506Syongari if ((ifp->if_capenable & 2541192506Syongari IFCAP_VLAN_HWTAGGING) != 0) 2542192506Syongari NGE_SETBIT(sc, 2543192506Syongari NGE_VLAN_IP_RXCTL, 2544192506Syongari NGE_VIPRXCTL_TAG_STRIP_ENB); 2545192506Syongari else 2546192506Syongari NGE_CLRBIT(sc, 2547192506Syongari NGE_VLAN_IP_RXCTL, 2548192506Syongari NGE_VIPRXCTL_TAG_STRIP_ENB); 2549192506Syongari } 2550150789Sglebius } 2551192506Syongari /* 2552192506Syongari * Both VLAN hardware tagging and checksum offload is 2553192506Syongari * required to do checksum offload on VLAN interface. 2554192506Syongari */ 2555192506Syongari if ((ifp->if_capenable & IFCAP_TXCSUM) == 0) 2556192506Syongari ifp->if_capenable &= ~IFCAP_VLAN_HWCSUM; 2557192506Syongari if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 2558192506Syongari ifp->if_capenable &= ~IFCAP_VLAN_HWCSUM; 2559192506Syongari NGE_UNLOCK(sc); 2560192506Syongari VLAN_CAPABILITIES(ifp); 2561128132Sru break; 256276479Swpaul default: 2563106937Ssam error = ether_ioctl(ifp, command, data); 256476479Swpaul break; 256576479Swpaul } 256676479Swpaul 2567192292Syongari return (error); 256876479Swpaul} 256976479Swpaul 257099497Salfredstatic void 2571192506Syongaringe_watchdog(struct nge_softc *sc) 257276479Swpaul{ 2573192506Syongari struct ifnet *ifp; 257476479Swpaul 2575192506Syongari NGE_LOCK_ASSERT(sc); 257676479Swpaul 2577192506Syongari if (sc->nge_watchdog_timer == 0 || --sc->nge_watchdog_timer) 2578192506Syongari return; 2579192506Syongari 2580192506Syongari ifp = sc->nge_ifp; 258176479Swpaul ifp->if_oerrors++; 2582162321Sglebius if_printf(ifp, "watchdog timeout\n"); 258376479Swpaul 2584148887Srwatson ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2585135250Swpaul nge_init_locked(sc); 258676479Swpaul 2587192506Syongari if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2588135250Swpaul nge_start_locked(ifp); 2589192506Syongari} 259076479Swpaul 2591192506Syongaristatic int 2592192506Syongaringe_stop_mac(struct nge_softc *sc) 2593192506Syongari{ 2594192506Syongari uint32_t reg; 2595192506Syongari int i; 2596192506Syongari 2597192506Syongari NGE_LOCK_ASSERT(sc); 2598192506Syongari 2599192506Syongari reg = CSR_READ_4(sc, NGE_CSR); 2600192506Syongari if ((reg & (NGE_CSR_TX_ENABLE | NGE_CSR_RX_ENABLE)) != 0) { 2601192506Syongari reg &= ~(NGE_CSR_TX_ENABLE | NGE_CSR_RX_ENABLE); 2602192506Syongari reg |= NGE_CSR_TX_DISABLE | NGE_CSR_RX_DISABLE; 2603192506Syongari CSR_WRITE_4(sc, NGE_CSR, reg); 2604192506Syongari for (i = 0; i < NGE_TIMEOUT; i++) { 2605192506Syongari DELAY(1); 2606192506Syongari if ((CSR_READ_4(sc, NGE_CSR) & 2607192506Syongari (NGE_CSR_RX_ENABLE | NGE_CSR_TX_ENABLE)) == 0) 2608192506Syongari break; 2609192506Syongari } 2610192506Syongari if (i == NGE_TIMEOUT) 2611192506Syongari return (ETIMEDOUT); 2612192506Syongari } 2613192506Syongari 2614192506Syongari return (0); 261576479Swpaul} 261676479Swpaul 261776479Swpaul/* 261876479Swpaul * Stop the adapter and free any mbufs allocated to the 261976479Swpaul * RX and TX lists. 262076479Swpaul */ 262199497Salfredstatic void 2622192288Syongaringe_stop(struct nge_softc *sc) 262376479Swpaul{ 2624192506Syongari struct nge_txdesc *txd; 2625192506Syongari struct nge_rxdesc *rxd; 2626192297Syongari int i; 2627192297Syongari struct ifnet *ifp; 262876479Swpaul 2629135250Swpaul NGE_LOCK_ASSERT(sc); 2630147256Sbrooks ifp = sc->nge_ifp; 263176479Swpaul 2632192506Syongari ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2633192506Syongari sc->nge_flags &= ~NGE_FLAG_LINK; 2634135250Swpaul callout_stop(&sc->nge_stat_ch); 2635192506Syongari sc->nge_watchdog_timer = 0; 2636192506Syongari 263776479Swpaul CSR_WRITE_4(sc, NGE_IER, 0); 263876479Swpaul CSR_WRITE_4(sc, NGE_IMR, 0); 2639192506Syongari if (nge_stop_mac(sc) == ETIMEDOUT) 2640192506Syongari device_printf(sc->nge_dev, 2641192506Syongari "%s: unable to stop Tx/Rx MAC\n", __func__); 2642192506Syongari CSR_WRITE_4(sc, NGE_TX_LISTPTR_HI, 0); 2643192506Syongari CSR_WRITE_4(sc, NGE_TX_LISTPTR_LO, 0); 2644192506Syongari CSR_WRITE_4(sc, NGE_RX_LISTPTR_HI, 0); 2645192506Syongari CSR_WRITE_4(sc, NGE_RX_LISTPTR_LO, 0); 2646192506Syongari nge_stats_update(sc); 2647192506Syongari if (sc->nge_head != NULL) { 2648192506Syongari m_freem(sc->nge_head); 2649192506Syongari sc->nge_head = sc->nge_tail = NULL; 2650192506Syongari } 265176479Swpaul 265276479Swpaul /* 2653192506Syongari * Free RX and TX mbufs still in the queues. 265476479Swpaul */ 2655192506Syongari for (i = 0; i < NGE_RX_RING_CNT; i++) { 2656192506Syongari rxd = &sc->nge_cdata.nge_rxdesc[i]; 2657192506Syongari if (rxd->rx_m != NULL) { 2658192506Syongari bus_dmamap_sync(sc->nge_cdata.nge_rx_tag, 2659192506Syongari rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2660192506Syongari bus_dmamap_unload(sc->nge_cdata.nge_rx_tag, 2661192506Syongari rxd->rx_dmamap); 2662192506Syongari m_freem(rxd->rx_m); 2663192506Syongari rxd->rx_m = NULL; 266476479Swpaul } 266576479Swpaul } 2666192506Syongari for (i = 0; i < NGE_TX_RING_CNT; i++) { 2667192506Syongari txd = &sc->nge_cdata.nge_txdesc[i]; 2668192506Syongari if (txd->tx_m != NULL) { 2669192506Syongari bus_dmamap_sync(sc->nge_cdata.nge_tx_tag, 2670192506Syongari txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2671192506Syongari bus_dmamap_unload(sc->nge_cdata.nge_tx_tag, 2672192506Syongari txd->tx_dmamap); 2673192506Syongari m_freem(txd->tx_m); 2674192506Syongari txd->tx_m = NULL; 267576479Swpaul } 267676479Swpaul } 2677192506Syongari} 267876479Swpaul 2679192506Syongari/* 2680192506Syongari * Before setting WOL bits, caller should have stopped Receiver. 2681192506Syongari */ 2682192506Syongaristatic void 2683192506Syongaringe_wol(struct nge_softc *sc) 2684192506Syongari{ 2685192506Syongari struct ifnet *ifp; 2686192506Syongari uint32_t reg; 2687192506Syongari uint16_t pmstat; 2688192506Syongari int pmc; 268976479Swpaul 2690192506Syongari NGE_LOCK_ASSERT(sc); 2691192506Syongari 2692192506Syongari if (pci_find_extcap(sc->nge_dev, PCIY_PMG, &pmc) != 0) 2693192506Syongari return; 2694192506Syongari 2695192506Syongari ifp = sc->nge_ifp; 2696192506Syongari if ((ifp->if_capenable & IFCAP_WOL) == 0) { 2697192506Syongari /* Disable WOL & disconnect CLKRUN to save power. */ 2698192506Syongari CSR_WRITE_4(sc, NGE_WOLCSR, 0); 2699192506Syongari CSR_WRITE_4(sc, NGE_CLKRUN, 0); 2700192506Syongari } else { 2701192506Syongari if (nge_stop_mac(sc) == ETIMEDOUT) 2702192506Syongari device_printf(sc->nge_dev, 2703192506Syongari "%s: unable to stop Tx/Rx MAC\n", __func__); 2704192506Syongari /* 2705192506Syongari * Make sure wake frames will be buffered in the Rx FIFO. 2706192506Syongari * (i.e. Silent Rx mode.) 2707192506Syongari */ 2708192506Syongari CSR_WRITE_4(sc, NGE_RX_LISTPTR_HI, 0); 2709192506Syongari CSR_BARRIER_WRITE_4(sc, NGE_RX_LISTPTR_HI); 2710192506Syongari CSR_WRITE_4(sc, NGE_RX_LISTPTR_LO, 0); 2711192506Syongari CSR_BARRIER_WRITE_4(sc, NGE_RX_LISTPTR_LO); 2712192506Syongari /* Enable Rx again. */ 2713192506Syongari NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 2714192506Syongari CSR_BARRIER_WRITE_4(sc, NGE_CSR); 2715192506Syongari 2716192506Syongari /* Configure WOL events. */ 2717192506Syongari reg = 0; 2718192506Syongari if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 2719192506Syongari reg |= NGE_WOLCSR_WAKE_ON_UNICAST; 2720192506Syongari if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 2721192506Syongari reg |= NGE_WOLCSR_WAKE_ON_MULTICAST; 2722192506Syongari if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2723192506Syongari reg |= NGE_WOLCSR_WAKE_ON_MAGICPKT; 2724192506Syongari CSR_WRITE_4(sc, NGE_WOLCSR, reg); 2725192506Syongari 2726192506Syongari /* Activate CLKRUN. */ 2727192506Syongari reg = CSR_READ_4(sc, NGE_CLKRUN); 2728192506Syongari reg |= NGE_CLKRUN_PMEENB | NGE_CLNRUN_CLKRUN_ENB; 2729192506Syongari CSR_WRITE_4(sc, NGE_CLKRUN, reg); 2730192506Syongari } 2731192506Syongari 2732192506Syongari /* Request PME. */ 2733192506Syongari pmstat = pci_read_config(sc->nge_dev, pmc + PCIR_POWER_STATUS, 2); 2734192506Syongari pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2735192506Syongari if ((ifp->if_capenable & IFCAP_WOL) != 0) 2736192506Syongari pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2737192506Syongari pci_write_config(sc->nge_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 273876479Swpaul} 273976479Swpaul 274076479Swpaul/* 274176479Swpaul * Stop all chip I/O so that the kernel's probe routines don't 274276479Swpaul * get confused by errant DMAs when rebooting. 274376479Swpaul */ 2744173839Syongaristatic int 2745192288Syongaringe_shutdown(device_t dev) 274676479Swpaul{ 2747192506Syongari 2748192506Syongari return (nge_suspend(dev)); 2749192506Syongari} 2750192506Syongari 2751192506Syongaristatic int 2752192506Syongaringe_suspend(device_t dev) 2753192506Syongari{ 2754192297Syongari struct nge_softc *sc; 275576479Swpaul 275676479Swpaul sc = device_get_softc(dev); 275776479Swpaul 2758135250Swpaul NGE_LOCK(sc); 275976479Swpaul nge_stop(sc); 2760192506Syongari nge_wol(sc); 2761192506Syongari sc->nge_flags |= NGE_FLAG_SUSPENDED; 2762135250Swpaul NGE_UNLOCK(sc); 276376479Swpaul 2764173839Syongari return (0); 276576479Swpaul} 2766192506Syongari 2767192506Syongaristatic int 2768192506Syongaringe_resume(device_t dev) 2769192506Syongari{ 2770192506Syongari struct nge_softc *sc; 2771192506Syongari struct ifnet *ifp; 2772192506Syongari uint16_t pmstat; 2773192506Syongari int pmc; 2774192506Syongari 2775192506Syongari sc = device_get_softc(dev); 2776192506Syongari 2777192506Syongari NGE_LOCK(sc); 2778192506Syongari ifp = sc->nge_ifp; 2779192506Syongari if (pci_find_extcap(sc->nge_dev, PCIY_PMG, &pmc) == 0) { 2780192506Syongari /* Disable PME and clear PME status. */ 2781192506Syongari pmstat = pci_read_config(sc->nge_dev, 2782192506Syongari pmc + PCIR_POWER_STATUS, 2); 2783192506Syongari if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 2784192506Syongari pmstat &= ~PCIM_PSTAT_PMEENABLE; 2785192506Syongari pci_write_config(sc->nge_dev, 2786192506Syongari pmc + PCIR_POWER_STATUS, pmstat, 2); 2787192506Syongari } 2788192506Syongari } 2789192506Syongari if (ifp->if_flags & IFF_UP) { 2790192506Syongari ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2791192506Syongari nge_init_locked(sc); 2792192506Syongari } 2793192506Syongari 2794192506Syongari sc->nge_flags &= ~NGE_FLAG_SUSPENDED; 2795192506Syongari NGE_UNLOCK(sc); 2796192506Syongari 2797192506Syongari return (0); 2798192506Syongari} 2799192506Syongari 2800192506Syongari#define NGE_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 2801192506Syongari SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 2802192506Syongari 2803192506Syongaristatic void 2804192506Syongaringe_sysctl_node(struct nge_softc *sc) 2805192506Syongari{ 2806192506Syongari struct sysctl_ctx_list *ctx; 2807192506Syongari struct sysctl_oid_list *child, *parent; 2808192506Syongari struct sysctl_oid *tree; 2809192506Syongari struct nge_stats *stats; 2810192506Syongari int error; 2811192506Syongari 2812192506Syongari ctx = device_get_sysctl_ctx(sc->nge_dev); 2813192506Syongari child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->nge_dev)); 2814192506Syongari SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_holdoff", 2815192506Syongari CTLTYPE_INT | CTLFLAG_RW, &sc->nge_int_holdoff, 0, 2816192506Syongari sysctl_hw_nge_int_holdoff, "I", "NGE interrupt moderation"); 2817192506Syongari /* Pull in device tunables. */ 2818192506Syongari sc->nge_int_holdoff = NGE_INT_HOLDOFF_DEFAULT; 2819192506Syongari error = resource_int_value(device_get_name(sc->nge_dev), 2820192506Syongari device_get_unit(sc->nge_dev), "int_holdoff", &sc->nge_int_holdoff); 2821192506Syongari if (error == 0) { 2822192506Syongari if (sc->nge_int_holdoff < NGE_INT_HOLDOFF_MIN || 2823192506Syongari sc->nge_int_holdoff > NGE_INT_HOLDOFF_MAX ) { 2824192506Syongari device_printf(sc->nge_dev, 2825192506Syongari "int_holdoff value out of range; " 2826192506Syongari "using default: %d(%d us)\n", 2827192506Syongari NGE_INT_HOLDOFF_DEFAULT, 2828192506Syongari NGE_INT_HOLDOFF_DEFAULT * 100); 2829192506Syongari sc->nge_int_holdoff = NGE_INT_HOLDOFF_DEFAULT; 2830192506Syongari } 2831192506Syongari } 2832192506Syongari 2833192506Syongari stats = &sc->nge_stats; 2834192506Syongari tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 2835192506Syongari NULL, "NGE statistics"); 2836192506Syongari parent = SYSCTL_CHILDREN(tree); 2837192506Syongari 2838192506Syongari /* Rx statistics. */ 2839192506Syongari tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 2840192506Syongari NULL, "Rx MAC statistics"); 2841192506Syongari child = SYSCTL_CHILDREN(tree); 2842192506Syongari NGE_SYSCTL_STAT_ADD32(ctx, child, "pkts_errs", 2843192506Syongari &stats->rx_pkts_errs, 2844192506Syongari "Packet errors including both wire errors and FIFO overruns"); 2845192506Syongari NGE_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 2846192506Syongari &stats->rx_crc_errs, "CRC errors"); 2847192506Syongari NGE_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 2848192506Syongari &stats->rx_fifo_oflows, "FIFO overflows"); 2849192506Syongari NGE_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 2850192506Syongari &stats->rx_align_errs, "Frame alignment errors"); 2851192506Syongari NGE_SYSCTL_STAT_ADD32(ctx, child, "sym_errs", 2852192506Syongari &stats->rx_sym_errs, "One or more symbol errors"); 2853192506Syongari NGE_SYSCTL_STAT_ADD32(ctx, child, "pkts_jumbos", 2854192506Syongari &stats->rx_pkts_jumbos, 2855192506Syongari "Packets received with length greater than 1518 bytes"); 2856192506Syongari NGE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 2857192506Syongari &stats->rx_len_errs, "In Range Length errors"); 2858192506Syongari NGE_SYSCTL_STAT_ADD32(ctx, child, "unctl_frames", 2859192506Syongari &stats->rx_unctl_frames, "Control frames with unsupported opcode"); 2860192506Syongari NGE_SYSCTL_STAT_ADD32(ctx, child, "pause", 2861192506Syongari &stats->rx_pause, "Pause frames"); 2862192506Syongari 2863192506Syongari /* Tx statistics. */ 2864192506Syongari tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 2865192506Syongari NULL, "Tx MAC statistics"); 2866192506Syongari child = SYSCTL_CHILDREN(tree); 2867192506Syongari NGE_SYSCTL_STAT_ADD32(ctx, child, "pause", 2868192506Syongari &stats->tx_pause, "Pause frames"); 2869192506Syongari NGE_SYSCTL_STAT_ADD32(ctx, child, "seq_errs", 2870192506Syongari &stats->tx_seq_errs, 2871192506Syongari "Loss of collision heartbeat during transmission"); 2872192506Syongari} 2873192506Syongari 2874192506Syongari#undef NGE_SYSCTL_STAT_ADD32 2875192506Syongari 2876192506Syongaristatic int 2877192506Syongarisysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2878192506Syongari{ 2879192506Syongari int error, value; 2880192506Syongari 2881192506Syongari if (arg1 == NULL) 2882192506Syongari return (EINVAL); 2883192506Syongari value = *(int *)arg1; 2884192506Syongari error = sysctl_handle_int(oidp, &value, 0, req); 2885192506Syongari if (error != 0 || req->newptr == NULL) 2886192506Syongari return (error); 2887192506Syongari if (value < low || value > high) 2888192506Syongari return (EINVAL); 2889192506Syongari *(int *)arg1 = value; 2890192506Syongari 2891192506Syongari return (0); 2892192506Syongari} 2893192506Syongari 2894192506Syongaristatic int 2895192506Syongarisysctl_hw_nge_int_holdoff(SYSCTL_HANDLER_ARGS) 2896192506Syongari{ 2897192506Syongari 2898192506Syongari return (sysctl_int_range(oidp, arg1, arg2, req, NGE_INT_HOLDOFF_MIN, 2899192506Syongari NGE_INT_HOLDOFF_MAX)); 2900192506Syongari} 2901