if_nfe.c revision 268131
1105965Sache/*	$OpenBSD: if_nfe.c,v 1.54 2006/04/07 12:38:12 jsg Exp $	*/
2105965Sache
3105965Sache/*-
4105965Sache * Copyright (c) 2006 Shigeaki Tagashira <shigeaki@se.hiroshima-u.ac.jp>
5105965Sache * Copyright (c) 2006 Damien Bergamini <damien.bergamini@free.fr>
6105965Sache * Copyright (c) 2005, 2006 Jonathan Gray <jsg@openbsd.org>
7105965Sache *
8105965Sache * Permission to use, copy, modify, and distribute this software for any
9105965Sache * purpose with or without fee is hereby granted, provided that the above
10105965Sache * copyright notice and this permission notice appear in all copies.
11105965Sache *
12105965Sache * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 */
20
21/* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */
22
23#include <sys/cdefs.h>
24__FBSDID("$FreeBSD: head/sys/dev/nfe/if_nfe.c 268131 2014-07-01 23:41:54Z marcel $");
25
26#ifdef HAVE_KERNEL_OPTION_HEADERS
27#include "opt_device_polling.h"
28#endif
29
30#include <sys/param.h>
31#include <sys/endian.h>
32#include <sys/systm.h>
33#include <sys/sockio.h>
34#include <sys/mbuf.h>
35#include <sys/malloc.h>
36#include <sys/module.h>
37#include <sys/kernel.h>
38#include <sys/queue.h>
39#include <sys/socket.h>
40#include <sys/sysctl.h>
41#include <sys/taskqueue.h>
42
43#include <net/if.h>
44#include <net/if_var.h>
45#include <net/if_arp.h>
46#include <net/ethernet.h>
47#include <net/if_dl.h>
48#include <net/if_media.h>
49#include <net/if_types.h>
50#include <net/if_vlan_var.h>
51
52#include <net/bpf.h>
53
54#include <machine/bus.h>
55#include <machine/resource.h>
56#include <sys/bus.h>
57#include <sys/rman.h>
58
59#include <dev/mii/mii.h>
60#include <dev/mii/miivar.h>
61
62#include <dev/pci/pcireg.h>
63#include <dev/pci/pcivar.h>
64
65#include <dev/nfe/if_nfereg.h>
66#include <dev/nfe/if_nfevar.h>
67
68MODULE_DEPEND(nfe, pci, 1, 1, 1);
69MODULE_DEPEND(nfe, ether, 1, 1, 1);
70MODULE_DEPEND(nfe, miibus, 1, 1, 1);
71
72/* "device miibus" required.  See GENERIC if you get errors here. */
73#include "miibus_if.h"
74
75static int  nfe_probe(device_t);
76static int  nfe_attach(device_t);
77static int  nfe_detach(device_t);
78static int  nfe_suspend(device_t);
79static int  nfe_resume(device_t);
80static int nfe_shutdown(device_t);
81static int  nfe_can_use_msix(struct nfe_softc *);
82static int  nfe_detect_msik9(struct nfe_softc *);
83static void nfe_power(struct nfe_softc *);
84static int  nfe_miibus_readreg(device_t, int, int);
85static int  nfe_miibus_writereg(device_t, int, int, int);
86static void nfe_miibus_statchg(device_t);
87static void nfe_mac_config(struct nfe_softc *, struct mii_data *);
88static void nfe_set_intr(struct nfe_softc *);
89static __inline void nfe_enable_intr(struct nfe_softc *);
90static __inline void nfe_disable_intr(struct nfe_softc *);
91static int  nfe_ioctl(if_t, u_long, caddr_t);
92static void nfe_alloc_msix(struct nfe_softc *, int);
93static int nfe_intr(void *);
94static void nfe_int_task(void *, int);
95static __inline void nfe_discard_rxbuf(struct nfe_softc *, int);
96static __inline void nfe_discard_jrxbuf(struct nfe_softc *, int);
97static int nfe_newbuf(struct nfe_softc *, int);
98static int nfe_jnewbuf(struct nfe_softc *, int);
99static int  nfe_rxeof(struct nfe_softc *, int, int *);
100static int  nfe_jrxeof(struct nfe_softc *, int, int *);
101static void nfe_txeof(struct nfe_softc *);
102static int  nfe_encap(struct nfe_softc *, struct mbuf **);
103static void nfe_setmulti(struct nfe_softc *);
104static void nfe_start(if_t);
105static void nfe_start_locked(if_t);
106static void nfe_watchdog(if_t);
107static void nfe_init(void *);
108static void nfe_init_locked(void *);
109static void nfe_stop(if_t);
110static int  nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
111static void nfe_alloc_jrx_ring(struct nfe_softc *, struct nfe_jrx_ring *);
112static int  nfe_init_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
113static int  nfe_init_jrx_ring(struct nfe_softc *, struct nfe_jrx_ring *);
114static void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
115static void nfe_free_jrx_ring(struct nfe_softc *, struct nfe_jrx_ring *);
116static int  nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
117static void nfe_init_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
118static void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
119static int  nfe_ifmedia_upd(if_t);
120static void nfe_ifmedia_sts(if_t, struct ifmediareq *);
121static void nfe_tick(void *);
122static void nfe_get_macaddr(struct nfe_softc *, uint8_t *);
123static void nfe_set_macaddr(struct nfe_softc *, uint8_t *);
124static void nfe_dma_map_segs(void *, bus_dma_segment_t *, int, int);
125
126static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
127static int sysctl_hw_nfe_proc_limit(SYSCTL_HANDLER_ARGS);
128static void nfe_sysctl_node(struct nfe_softc *);
129static void nfe_stats_clear(struct nfe_softc *);
130static void nfe_stats_update(struct nfe_softc *);
131static void nfe_set_linkspeed(struct nfe_softc *);
132static void nfe_set_wol(struct nfe_softc *);
133
134#ifdef NFE_DEBUG
135static int nfedebug = 0;
136#define	DPRINTF(sc, ...)	do {				\
137	if (nfedebug)						\
138		device_printf((sc)->nfe_dev, __VA_ARGS__);	\
139} while (0)
140#define	DPRINTFN(sc, n, ...)	do {				\
141	if (nfedebug >= (n))					\
142		device_printf((sc)->nfe_dev, __VA_ARGS__);	\
143} while (0)
144#else
145#define	DPRINTF(sc, ...)
146#define	DPRINTFN(sc, n, ...)
147#endif
148
149#define	NFE_LOCK(_sc)		mtx_lock(&(_sc)->nfe_mtx)
150#define	NFE_UNLOCK(_sc)		mtx_unlock(&(_sc)->nfe_mtx)
151#define	NFE_LOCK_ASSERT(_sc)	mtx_assert(&(_sc)->nfe_mtx, MA_OWNED)
152
153/* Tunables. */
154static int msi_disable = 0;
155static int msix_disable = 0;
156static int jumbo_disable = 0;
157TUNABLE_INT("hw.nfe.msi_disable", &msi_disable);
158TUNABLE_INT("hw.nfe.msix_disable", &msix_disable);
159TUNABLE_INT("hw.nfe.jumbo_disable", &jumbo_disable);
160
161static device_method_t nfe_methods[] = {
162	/* Device interface */
163	DEVMETHOD(device_probe,		nfe_probe),
164	DEVMETHOD(device_attach,	nfe_attach),
165	DEVMETHOD(device_detach,	nfe_detach),
166	DEVMETHOD(device_suspend,	nfe_suspend),
167	DEVMETHOD(device_resume,	nfe_resume),
168	DEVMETHOD(device_shutdown,	nfe_shutdown),
169
170	/* MII interface */
171	DEVMETHOD(miibus_readreg,	nfe_miibus_readreg),
172	DEVMETHOD(miibus_writereg,	nfe_miibus_writereg),
173	DEVMETHOD(miibus_statchg,	nfe_miibus_statchg),
174
175	DEVMETHOD_END
176};
177
178static driver_t nfe_driver = {
179	"nfe",
180	nfe_methods,
181	sizeof(struct nfe_softc)
182};
183
184static devclass_t nfe_devclass;
185
186DRIVER_MODULE(nfe, pci, nfe_driver, nfe_devclass, 0, 0);
187DRIVER_MODULE(miibus, nfe, miibus_driver, miibus_devclass, 0, 0);
188
189static struct nfe_type nfe_devs[] = {
190	{PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN,
191	    "NVIDIA nForce MCP Networking Adapter"},
192	{PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN,
193	    "NVIDIA nForce2 MCP2 Networking Adapter"},
194	{PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1,
195	    "NVIDIA nForce2 400 MCP4 Networking Adapter"},
196	{PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2,
197	    "NVIDIA nForce2 400 MCP5 Networking Adapter"},
198	{PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1,
199	    "NVIDIA nForce3 MCP3 Networking Adapter"},
200	{PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN,
201	    "NVIDIA nForce3 250 MCP6 Networking Adapter"},
202	{PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4,
203	    "NVIDIA nForce3 MCP7 Networking Adapter"},
204	{PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE4_LAN1,
205	    "NVIDIA nForce4 CK804 MCP8 Networking Adapter"},
206	{PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE4_LAN2,
207	    "NVIDIA nForce4 CK804 MCP9 Networking Adapter"},
208	{PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1,
209	    "NVIDIA nForce MCP04 Networking Adapter"},		/* MCP10 */
210	{PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2,
211	    "NVIDIA nForce MCP04 Networking Adapter"},		/* MCP11 */
212	{PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE430_LAN1,
213	    "NVIDIA nForce 430 MCP12 Networking Adapter"},
214	{PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE430_LAN2,
215	    "NVIDIA nForce 430 MCP13 Networking Adapter"},
216	{PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1,
217	    "NVIDIA nForce MCP55 Networking Adapter"},
218	{PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2,
219	    "NVIDIA nForce MCP55 Networking Adapter"},
220	{PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1,
221	    "NVIDIA nForce MCP61 Networking Adapter"},
222	{PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2,
223	    "NVIDIA nForce MCP61 Networking Adapter"},
224	{PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3,
225	    "NVIDIA nForce MCP61 Networking Adapter"},
226	{PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4,
227	    "NVIDIA nForce MCP61 Networking Adapter"},
228	{PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1,
229	    "NVIDIA nForce MCP65 Networking Adapter"},
230	{PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2,
231	    "NVIDIA nForce MCP65 Networking Adapter"},
232	{PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3,
233	    "NVIDIA nForce MCP65 Networking Adapter"},
234	{PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4,
235	    "NVIDIA nForce MCP65 Networking Adapter"},
236	{PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN1,
237	    "NVIDIA nForce MCP67 Networking Adapter"},
238	{PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN2,
239	    "NVIDIA nForce MCP67 Networking Adapter"},
240	{PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN3,
241	    "NVIDIA nForce MCP67 Networking Adapter"},
242	{PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN4,
243	    "NVIDIA nForce MCP67 Networking Adapter"},
244	{PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN1,
245	    "NVIDIA nForce MCP73 Networking Adapter"},
246	{PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN2,
247	    "NVIDIA nForce MCP73 Networking Adapter"},
248	{PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN3,
249	    "NVIDIA nForce MCP73 Networking Adapter"},
250	{PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN4,
251	    "NVIDIA nForce MCP73 Networking Adapter"},
252	{PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN1,
253	    "NVIDIA nForce MCP77 Networking Adapter"},
254	{PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN2,
255	    "NVIDIA nForce MCP77 Networking Adapter"},
256	{PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN3,
257	    "NVIDIA nForce MCP77 Networking Adapter"},
258	{PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN4,
259	    "NVIDIA nForce MCP77 Networking Adapter"},
260	{PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN1,
261	    "NVIDIA nForce MCP79 Networking Adapter"},
262	{PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN2,
263	    "NVIDIA nForce MCP79 Networking Adapter"},
264	{PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN3,
265	    "NVIDIA nForce MCP79 Networking Adapter"},
266	{PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN4,
267	    "NVIDIA nForce MCP79 Networking Adapter"},
268	{0, 0, NULL}
269};
270
271
272/* Probe for supported hardware ID's */
273static int
274nfe_probe(device_t dev)
275{
276	struct nfe_type *t;
277
278	t = nfe_devs;
279	/* Check for matching PCI DEVICE ID's */
280	while (t->name != NULL) {
281		if ((pci_get_vendor(dev) == t->vid_id) &&
282		    (pci_get_device(dev) == t->dev_id)) {
283			device_set_desc(dev, t->name);
284			return (BUS_PROBE_DEFAULT);
285		}
286		t++;
287	}
288
289	return (ENXIO);
290}
291
292static void
293nfe_alloc_msix(struct nfe_softc *sc, int count)
294{
295	int rid;
296
297	rid = PCIR_BAR(2);
298	sc->nfe_msix_res = bus_alloc_resource_any(sc->nfe_dev, SYS_RES_MEMORY,
299	    &rid, RF_ACTIVE);
300	if (sc->nfe_msix_res == NULL) {
301		device_printf(sc->nfe_dev,
302		    "couldn't allocate MSIX table resource\n");
303		return;
304	}
305	rid = PCIR_BAR(3);
306	sc->nfe_msix_pba_res = bus_alloc_resource_any(sc->nfe_dev,
307	    SYS_RES_MEMORY, &rid, RF_ACTIVE);
308	if (sc->nfe_msix_pba_res == NULL) {
309		device_printf(sc->nfe_dev,
310		    "couldn't allocate MSIX PBA resource\n");
311		bus_release_resource(sc->nfe_dev, SYS_RES_MEMORY, PCIR_BAR(2),
312		    sc->nfe_msix_res);
313		sc->nfe_msix_res = NULL;
314		return;
315	}
316
317	if (pci_alloc_msix(sc->nfe_dev, &count) == 0) {
318		if (count == NFE_MSI_MESSAGES) {
319			if (bootverbose)
320				device_printf(sc->nfe_dev,
321				    "Using %d MSIX messages\n", count);
322			sc->nfe_msix = 1;
323		} else {
324			if (bootverbose)
325				device_printf(sc->nfe_dev,
326				    "couldn't allocate MSIX\n");
327			pci_release_msi(sc->nfe_dev);
328			bus_release_resource(sc->nfe_dev, SYS_RES_MEMORY,
329			    PCIR_BAR(3), sc->nfe_msix_pba_res);
330			bus_release_resource(sc->nfe_dev, SYS_RES_MEMORY,
331			    PCIR_BAR(2), sc->nfe_msix_res);
332			sc->nfe_msix_pba_res = NULL;
333			sc->nfe_msix_res = NULL;
334		}
335	}
336}
337
338
339static int
340nfe_detect_msik9(struct nfe_softc *sc)
341{
342	static const char *maker = "MSI";
343	static const char *product = "K9N6PGM2-V2 (MS-7309)";
344	char *m, *p;
345	int found;
346
347	found = 0;
348	m = getenv("smbios.planar.maker");
349	p = getenv("smbios.planar.product");
350	if (m != NULL && p != NULL) {
351		if (strcmp(m, maker) == 0 && strcmp(p, product) == 0)
352			found = 1;
353	}
354	if (m != NULL)
355		freeenv(m);
356	if (p != NULL)
357		freeenv(p);
358
359	return (found);
360}
361
362
363static int
364nfe_attach(device_t dev)
365{
366	struct nfe_softc *sc;
367	if_t ifp;
368	bus_addr_t dma_addr_max;
369	int error = 0, i, msic, phyloc, reg, rid;
370
371	sc = device_get_softc(dev);
372	sc->nfe_dev = dev;
373
374	mtx_init(&sc->nfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
375	    MTX_DEF);
376	callout_init_mtx(&sc->nfe_stat_ch, &sc->nfe_mtx, 0);
377
378	pci_enable_busmaster(dev);
379
380	rid = PCIR_BAR(0);
381	sc->nfe_res[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
382	    RF_ACTIVE);
383	if (sc->nfe_res[0] == NULL) {
384		device_printf(dev, "couldn't map memory resources\n");
385		mtx_destroy(&sc->nfe_mtx);
386		return (ENXIO);
387	}
388
389	if (pci_find_cap(dev, PCIY_EXPRESS, &reg) == 0) {
390		uint16_t v, width;
391
392		v = pci_read_config(dev, reg + 0x08, 2);
393		/* Change max. read request size to 4096. */
394		v &= ~(7 << 12);
395		v |= (5 << 12);
396		pci_write_config(dev, reg + 0x08, v, 2);
397
398		v = pci_read_config(dev, reg + 0x0c, 2);
399		/* link capability */
400		v = (v >> 4) & 0x0f;
401		width = pci_read_config(dev, reg + 0x12, 2);
402		/* negotiated link width */
403		width = (width >> 4) & 0x3f;
404		if (v != width)
405			device_printf(sc->nfe_dev,
406			    "warning, negotiated width of link(x%d) != "
407			    "max. width of link(x%d)\n", width, v);
408	}
409
410	if (nfe_can_use_msix(sc) == 0) {
411		device_printf(sc->nfe_dev,
412		    "MSI/MSI-X capability black-listed, will use INTx\n");
413		msix_disable = 1;
414		msi_disable = 1;
415	}
416
417	/* Allocate interrupt */
418	if (msix_disable == 0 || msi_disable == 0) {
419		if (msix_disable == 0 &&
420		    (msic = pci_msix_count(dev)) == NFE_MSI_MESSAGES)
421			nfe_alloc_msix(sc, msic);
422		if (msi_disable == 0 && sc->nfe_msix == 0 &&
423		    (msic = pci_msi_count(dev)) == NFE_MSI_MESSAGES &&
424		    pci_alloc_msi(dev, &msic) == 0) {
425			if (msic == NFE_MSI_MESSAGES) {
426				if (bootverbose)
427					device_printf(dev,
428					    "Using %d MSI messages\n", msic);
429				sc->nfe_msi = 1;
430			} else
431				pci_release_msi(dev);
432		}
433	}
434
435	if (sc->nfe_msix == 0 && sc->nfe_msi == 0) {
436		rid = 0;
437		sc->nfe_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
438		    RF_SHAREABLE | RF_ACTIVE);
439		if (sc->nfe_irq[0] == NULL) {
440			device_printf(dev, "couldn't allocate IRQ resources\n");
441			error = ENXIO;
442			goto fail;
443		}
444	} else {
445		for (i = 0, rid = 1; i < NFE_MSI_MESSAGES; i++, rid++) {
446			sc->nfe_irq[i] = bus_alloc_resource_any(dev,
447			    SYS_RES_IRQ, &rid, RF_ACTIVE);
448			if (sc->nfe_irq[i] == NULL) {
449				device_printf(dev,
450				    "couldn't allocate IRQ resources for "
451				    "message %d\n", rid);
452				error = ENXIO;
453				goto fail;
454			}
455		}
456		/* Map interrupts to vector 0. */
457		if (sc->nfe_msix != 0) {
458			NFE_WRITE(sc, NFE_MSIX_MAP0, 0);
459			NFE_WRITE(sc, NFE_MSIX_MAP1, 0);
460		} else if (sc->nfe_msi != 0) {
461			NFE_WRITE(sc, NFE_MSI_MAP0, 0);
462			NFE_WRITE(sc, NFE_MSI_MAP1, 0);
463		}
464	}
465
466	/* Set IRQ status/mask register. */
467	sc->nfe_irq_status = NFE_IRQ_STATUS;
468	sc->nfe_irq_mask = NFE_IRQ_MASK;
469	sc->nfe_intrs = NFE_IRQ_WANTED;
470	sc->nfe_nointrs = 0;
471	if (sc->nfe_msix != 0) {
472		sc->nfe_irq_status = NFE_MSIX_IRQ_STATUS;
473		sc->nfe_nointrs = NFE_IRQ_WANTED;
474	} else if (sc->nfe_msi != 0) {
475		sc->nfe_irq_mask = NFE_MSI_IRQ_MASK;
476		sc->nfe_intrs = NFE_MSI_VECTOR_0_ENABLED;
477	}
478
479	sc->nfe_devid = pci_get_device(dev);
480	sc->nfe_revid = pci_get_revid(dev);
481	sc->nfe_flags = 0;
482
483	switch (sc->nfe_devid) {
484	case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2:
485	case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3:
486	case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4:
487	case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5:
488		sc->nfe_flags |= NFE_JUMBO_SUP | NFE_HW_CSUM;
489		break;
490	case PCI_PRODUCT_NVIDIA_MCP51_LAN1:
491	case PCI_PRODUCT_NVIDIA_MCP51_LAN2:
492		sc->nfe_flags |= NFE_40BIT_ADDR | NFE_PWR_MGMT | NFE_MIB_V1;
493		break;
494	case PCI_PRODUCT_NVIDIA_CK804_LAN1:
495	case PCI_PRODUCT_NVIDIA_CK804_LAN2:
496	case PCI_PRODUCT_NVIDIA_MCP04_LAN1:
497	case PCI_PRODUCT_NVIDIA_MCP04_LAN2:
498		sc->nfe_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM |
499		    NFE_MIB_V1;
500		break;
501	case PCI_PRODUCT_NVIDIA_MCP55_LAN1:
502	case PCI_PRODUCT_NVIDIA_MCP55_LAN2:
503		sc->nfe_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM |
504		    NFE_HW_VLAN | NFE_PWR_MGMT | NFE_TX_FLOW_CTRL | NFE_MIB_V2;
505		break;
506
507	case PCI_PRODUCT_NVIDIA_MCP61_LAN1:
508	case PCI_PRODUCT_NVIDIA_MCP61_LAN2:
509	case PCI_PRODUCT_NVIDIA_MCP61_LAN3:
510	case PCI_PRODUCT_NVIDIA_MCP61_LAN4:
511	case PCI_PRODUCT_NVIDIA_MCP67_LAN1:
512	case PCI_PRODUCT_NVIDIA_MCP67_LAN2:
513	case PCI_PRODUCT_NVIDIA_MCP67_LAN3:
514	case PCI_PRODUCT_NVIDIA_MCP67_LAN4:
515	case PCI_PRODUCT_NVIDIA_MCP73_LAN1:
516	case PCI_PRODUCT_NVIDIA_MCP73_LAN2:
517	case PCI_PRODUCT_NVIDIA_MCP73_LAN3:
518	case PCI_PRODUCT_NVIDIA_MCP73_LAN4:
519		sc->nfe_flags |= NFE_40BIT_ADDR | NFE_PWR_MGMT |
520		    NFE_CORRECT_MACADDR | NFE_TX_FLOW_CTRL | NFE_MIB_V2;
521		break;
522	case PCI_PRODUCT_NVIDIA_MCP77_LAN1:
523	case PCI_PRODUCT_NVIDIA_MCP77_LAN2:
524	case PCI_PRODUCT_NVIDIA_MCP77_LAN3:
525	case PCI_PRODUCT_NVIDIA_MCP77_LAN4:
526		/* XXX flow control */
527		sc->nfe_flags |= NFE_40BIT_ADDR | NFE_HW_CSUM | NFE_PWR_MGMT |
528		    NFE_CORRECT_MACADDR | NFE_MIB_V3;
529		break;
530	case PCI_PRODUCT_NVIDIA_MCP79_LAN1:
531	case PCI_PRODUCT_NVIDIA_MCP79_LAN2:
532	case PCI_PRODUCT_NVIDIA_MCP79_LAN3:
533	case PCI_PRODUCT_NVIDIA_MCP79_LAN4:
534		/* XXX flow control */
535		sc->nfe_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM |
536		    NFE_PWR_MGMT | NFE_CORRECT_MACADDR | NFE_MIB_V3;
537		break;
538	case PCI_PRODUCT_NVIDIA_MCP65_LAN1:
539	case PCI_PRODUCT_NVIDIA_MCP65_LAN2:
540	case PCI_PRODUCT_NVIDIA_MCP65_LAN3:
541	case PCI_PRODUCT_NVIDIA_MCP65_LAN4:
542		sc->nfe_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR |
543		    NFE_PWR_MGMT | NFE_CORRECT_MACADDR | NFE_TX_FLOW_CTRL |
544		    NFE_MIB_V2;
545		break;
546	}
547
548	nfe_power(sc);
549	/* Check for reversed ethernet address */
550	if ((NFE_READ(sc, NFE_TX_UNK) & NFE_MAC_ADDR_INORDER) != 0)
551		sc->nfe_flags |= NFE_CORRECT_MACADDR;
552	nfe_get_macaddr(sc, sc->eaddr);
553	/*
554	 * Allocate the parent bus DMA tag appropriate for PCI.
555	 */
556	dma_addr_max = BUS_SPACE_MAXADDR_32BIT;
557	if ((sc->nfe_flags & NFE_40BIT_ADDR) != 0)
558		dma_addr_max = NFE_DMA_MAXADDR;
559	error = bus_dma_tag_create(
560	    bus_get_dma_tag(sc->nfe_dev),	/* parent */
561	    1, 0,				/* alignment, boundary */
562	    dma_addr_max,			/* lowaddr */
563	    BUS_SPACE_MAXADDR,			/* highaddr */
564	    NULL, NULL,				/* filter, filterarg */
565	    BUS_SPACE_MAXSIZE_32BIT, 0,		/* maxsize, nsegments */
566	    BUS_SPACE_MAXSIZE_32BIT,		/* maxsegsize */
567	    0,					/* flags */
568	    NULL, NULL,				/* lockfunc, lockarg */
569	    &sc->nfe_parent_tag);
570	if (error)
571		goto fail;
572
573	ifp = sc->nfe_ifp = if_gethandle(IFT_ETHER);
574	if (ifp == NULL) {
575		device_printf(dev, "can not if_gethandle()\n");
576		error = ENOSPC;
577		goto fail;
578	}
579
580	/*
581	 * Allocate Tx and Rx rings.
582	 */
583	if ((error = nfe_alloc_tx_ring(sc, &sc->txq)) != 0)
584		goto fail;
585
586	if ((error = nfe_alloc_rx_ring(sc, &sc->rxq)) != 0)
587		goto fail;
588
589	nfe_alloc_jrx_ring(sc, &sc->jrxq);
590	/* Create sysctl node. */
591	nfe_sysctl_node(sc);
592
593	if_setsoftc(ifp, sc);
594	if_initname_drv(ifp, device_get_name(dev), device_get_unit(dev));
595	if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
596	if_setioctlfn(ifp, nfe_ioctl);
597	if_setstartfn(ifp, nfe_start);
598	if_sethwassist(ifp, 0);
599	if_setcapabilities(ifp, 0);
600	if_setinitfn(ifp, nfe_init);
601	if_setsendqlen(ifp, NFE_TX_RING_COUNT - 1);
602	if_setsendqready(ifp);
603
604
605	if (sc->nfe_flags & NFE_HW_CSUM) {
606		if_setcapabilitiesbit(ifp, IFCAP_HWCSUM | IFCAP_TSO4, 0);
607		if_sethwassistbits(ifp, NFE_CSUM_FEATURES | CSUM_TSO, 0);
608	}
609	if_setcapenable(ifp, if_getcapabilities(ifp));
610
611	sc->nfe_framesize = if_getmtu(ifp) + NFE_RX_HEADERS;
612	/* VLAN capability setup. */
613	if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0);
614	if ((sc->nfe_flags & NFE_HW_VLAN) != 0) {
615		if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWTAGGING, 0);
616		if ((if_getcapabilities(ifp) & IFCAP_HWCSUM) != 0)
617			if_setcapabilitiesbit(ifp,
618			    (IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO), 0);
619	}
620
621	if (pci_find_cap(dev, PCIY_PMG, &reg) == 0)
622		if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC, 0);
623	if_setcapenable(ifp, if_getcapabilities(ifp));
624
625	/*
626	 * Tell the upper layer(s) we support long frames.
627	 * Must appear after the call to ether_ifattach_drv() because
628	 * ether_ifattach_drv() sets ifi_hdrlen to the default value.
629	 */
630	if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
631
632#ifdef DEVICE_POLLING
633	if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0);
634#endif
635
636	/* Do MII setup */
637	phyloc = MII_PHY_ANY;
638	if (sc->nfe_devid == PCI_PRODUCT_NVIDIA_MCP61_LAN1 ||
639	    sc->nfe_devid == PCI_PRODUCT_NVIDIA_MCP61_LAN2 ||
640	    sc->nfe_devid == PCI_PRODUCT_NVIDIA_MCP61_LAN3 ||
641	    sc->nfe_devid == PCI_PRODUCT_NVIDIA_MCP61_LAN4) {
642		if (nfe_detect_msik9(sc) != 0)
643			phyloc = 0;
644	}
645	error = mii_attach(dev, &sc->nfe_miibus, ifp,
646	    (ifm_change_cb_t)nfe_ifmedia_upd, (ifm_stat_cb_t)nfe_ifmedia_sts,
647	    BMSR_DEFCAPMASK, phyloc, MII_OFFSET_ANY, MIIF_DOPAUSE);
648	if (error != 0) {
649		device_printf(dev, "attaching PHYs failed\n");
650		goto fail;
651	}
652	ether_ifattach_drv(ifp, sc->eaddr);
653
654	TASK_INIT(&sc->nfe_int_task, 0, nfe_int_task, sc);
655	sc->nfe_tq = taskqueue_create_fast("nfe_taskq", M_WAITOK,
656	    taskqueue_thread_enqueue, &sc->nfe_tq);
657	taskqueue_start_threads(&sc->nfe_tq, 1, PI_NET, "%s taskq",
658	    device_get_nameunit(sc->nfe_dev));
659	error = 0;
660	if (sc->nfe_msi == 0 && sc->nfe_msix == 0) {
661		error = bus_setup_intr(dev, sc->nfe_irq[0],
662		    INTR_TYPE_NET | INTR_MPSAFE, nfe_intr, NULL, sc,
663		    &sc->nfe_intrhand[0]);
664	} else {
665		for (i = 0; i < NFE_MSI_MESSAGES; i++) {
666			error = bus_setup_intr(dev, sc->nfe_irq[i],
667			    INTR_TYPE_NET | INTR_MPSAFE, nfe_intr, NULL, sc,
668			    &sc->nfe_intrhand[i]);
669			if (error != 0)
670				break;
671		}
672	}
673	if (error) {
674		device_printf(dev, "couldn't set up irq\n");
675		taskqueue_free(sc->nfe_tq);
676		sc->nfe_tq = NULL;
677		ether_ifdetach_drv(ifp);
678		goto fail;
679	}
680
681fail:
682	if (error)
683		nfe_detach(dev);
684
685	return (error);
686}
687
688
689static int
690nfe_detach(device_t dev)
691{
692	struct nfe_softc *sc;
693	if_t ifp;
694	uint8_t eaddr[ETHER_ADDR_LEN];
695	int i, rid;
696
697	sc = device_get_softc(dev);
698	KASSERT(mtx_initialized(&sc->nfe_mtx), ("nfe mutex not initialized"));
699	ifp = sc->nfe_ifp;
700
701#ifdef DEVICE_POLLING
702	if (ifp != NULL && if_getcapenable(ifp) & IFCAP_POLLING)
703		ether_poll_deregister(ifp);
704#endif
705	if (device_is_attached(dev)) {
706		NFE_LOCK(sc);
707		nfe_stop(ifp);
708		if_setflagbits(ifp, 0, IFF_UP);
709		NFE_UNLOCK(sc);
710		callout_drain(&sc->nfe_stat_ch);
711		ether_ifdetach_drv(ifp);
712	}
713
714	if (ifp) {
715		/* restore ethernet address */
716		if ((sc->nfe_flags & NFE_CORRECT_MACADDR) == 0) {
717			for (i = 0; i < ETHER_ADDR_LEN; i++) {
718				eaddr[i] = sc->eaddr[5 - i];
719			}
720		} else
721			bcopy(sc->eaddr, eaddr, ETHER_ADDR_LEN);
722		nfe_set_macaddr(sc, eaddr);
723		if_free_drv(ifp);
724	}
725	if (sc->nfe_miibus)
726		device_delete_child(dev, sc->nfe_miibus);
727	bus_generic_detach(dev);
728	if (sc->nfe_tq != NULL) {
729		taskqueue_drain(sc->nfe_tq, &sc->nfe_int_task);
730		taskqueue_free(sc->nfe_tq);
731		sc->nfe_tq = NULL;
732	}
733
734	for (i = 0; i < NFE_MSI_MESSAGES; i++) {
735		if (sc->nfe_intrhand[i] != NULL) {
736			bus_teardown_intr(dev, sc->nfe_irq[i],
737			    sc->nfe_intrhand[i]);
738			sc->nfe_intrhand[i] = NULL;
739		}
740	}
741
742	if (sc->nfe_msi == 0 && sc->nfe_msix == 0) {
743		if (sc->nfe_irq[0] != NULL)
744			bus_release_resource(dev, SYS_RES_IRQ, 0,
745			    sc->nfe_irq[0]);
746	} else {
747		for (i = 0, rid = 1; i < NFE_MSI_MESSAGES; i++, rid++) {
748			if (sc->nfe_irq[i] != NULL) {
749				bus_release_resource(dev, SYS_RES_IRQ, rid,
750				    sc->nfe_irq[i]);
751				sc->nfe_irq[i] = NULL;
752			}
753		}
754		pci_release_msi(dev);
755	}
756	if (sc->nfe_msix_pba_res != NULL) {
757		bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(3),
758		    sc->nfe_msix_pba_res);
759		sc->nfe_msix_pba_res = NULL;
760	}
761	if (sc->nfe_msix_res != NULL) {
762		bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(2),
763		    sc->nfe_msix_res);
764		sc->nfe_msix_res = NULL;
765	}
766	if (sc->nfe_res[0] != NULL) {
767		bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
768		    sc->nfe_res[0]);
769		sc->nfe_res[0] = NULL;
770	}
771
772	nfe_free_tx_ring(sc, &sc->txq);
773	nfe_free_rx_ring(sc, &sc->rxq);
774	nfe_free_jrx_ring(sc, &sc->jrxq);
775
776	if (sc->nfe_parent_tag) {
777		bus_dma_tag_destroy(sc->nfe_parent_tag);
778		sc->nfe_parent_tag = NULL;
779	}
780
781	mtx_destroy(&sc->nfe_mtx);
782
783	return (0);
784}
785
786
787static int
788nfe_suspend(device_t dev)
789{
790	struct nfe_softc *sc;
791
792	sc = device_get_softc(dev);
793
794	NFE_LOCK(sc);
795	nfe_stop(sc->nfe_ifp);
796	nfe_set_wol(sc);
797	sc->nfe_suspended = 1;
798	NFE_UNLOCK(sc);
799
800	return (0);
801}
802
803
804static int
805nfe_resume(device_t dev)
806{
807	struct nfe_softc *sc;
808	if_t ifp;
809
810	sc = device_get_softc(dev);
811
812	NFE_LOCK(sc);
813	nfe_power(sc);
814	ifp = sc->nfe_ifp;
815	if (if_getflags(ifp) & IFF_UP)
816		nfe_init_locked(sc);
817	sc->nfe_suspended = 0;
818	NFE_UNLOCK(sc);
819
820	return (0);
821}
822
823
824static int
825nfe_can_use_msix(struct nfe_softc *sc)
826{
827	static struct msix_blacklist {
828		char	*maker;
829		char	*product;
830	} msix_blacklists[] = {
831		{ "ASUSTeK Computer INC.", "P5N32-SLI PREMIUM" }
832	};
833
834	struct msix_blacklist *mblp;
835	char *maker, *product;
836	int count, n, use_msix;
837
838	/*
839	 * Search base board manufacturer and product name table
840	 * to see this system has a known MSI/MSI-X issue.
841	 */
842	maker = getenv("smbios.planar.maker");
843	product = getenv("smbios.planar.product");
844	use_msix = 1;
845	if (maker != NULL && product != NULL) {
846		count = sizeof(msix_blacklists) / sizeof(msix_blacklists[0]);
847		mblp = msix_blacklists;
848		for (n = 0; n < count; n++) {
849			if (strcmp(maker, mblp->maker) == 0 &&
850			    strcmp(product, mblp->product) == 0) {
851				use_msix = 0;
852				break;
853			}
854			mblp++;
855		}
856	}
857	if (maker != NULL)
858		freeenv(maker);
859	if (product != NULL)
860		freeenv(product);
861
862	return (use_msix);
863}
864
865
866/* Take PHY/NIC out of powerdown, from Linux */
867static void
868nfe_power(struct nfe_softc *sc)
869{
870	uint32_t pwr;
871
872	if ((sc->nfe_flags & NFE_PWR_MGMT) == 0)
873		return;
874	NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | NFE_RXTX_BIT2);
875	NFE_WRITE(sc, NFE_MAC_RESET, NFE_MAC_RESET_MAGIC);
876	DELAY(100);
877	NFE_WRITE(sc, NFE_MAC_RESET, 0);
878	DELAY(100);
879	NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT2);
880	pwr = NFE_READ(sc, NFE_PWR2_CTL);
881	pwr &= ~NFE_PWR2_WAKEUP_MASK;
882	if (sc->nfe_revid >= 0xa3 &&
883	    (sc->nfe_devid == PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 ||
884	    sc->nfe_devid == PCI_PRODUCT_NVIDIA_NFORCE430_LAN2))
885		pwr |= NFE_PWR2_REVA3;
886	NFE_WRITE(sc, NFE_PWR2_CTL, pwr);
887}
888
889
890static void
891nfe_miibus_statchg(device_t dev)
892{
893	struct nfe_softc *sc;
894	struct mii_data *mii;
895	if_t ifp;
896	uint32_t rxctl, txctl;
897
898	sc = device_get_softc(dev);
899
900	mii = device_get_softc(sc->nfe_miibus);
901	ifp = sc->nfe_ifp;
902
903	sc->nfe_link = 0;
904	if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
905	    (IFM_ACTIVE | IFM_AVALID)) {
906		switch (IFM_SUBTYPE(mii->mii_media_active)) {
907		case IFM_10_T:
908		case IFM_100_TX:
909		case IFM_1000_T:
910			sc->nfe_link = 1;
911			break;
912		default:
913			break;
914		}
915	}
916
917	nfe_mac_config(sc, mii);
918	txctl = NFE_READ(sc, NFE_TX_CTL);
919	rxctl = NFE_READ(sc, NFE_RX_CTL);
920	if (sc->nfe_link != 0 && (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
921		txctl |= NFE_TX_START;
922		rxctl |= NFE_RX_START;
923	} else {
924		txctl &= ~NFE_TX_START;
925		rxctl &= ~NFE_RX_START;
926	}
927	NFE_WRITE(sc, NFE_TX_CTL, txctl);
928	NFE_WRITE(sc, NFE_RX_CTL, rxctl);
929}
930
931
932static void
933nfe_mac_config(struct nfe_softc *sc, struct mii_data *mii)
934{
935	uint32_t link, misc, phy, seed;
936	uint32_t val;
937
938	NFE_LOCK_ASSERT(sc);
939
940	phy = NFE_READ(sc, NFE_PHY_IFACE);
941	phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T);
942
943	seed = NFE_READ(sc, NFE_RNDSEED);
944	seed &= ~NFE_SEED_MASK;
945
946	misc = NFE_MISC1_MAGIC;
947	link = NFE_MEDIA_SET;
948
949	if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0) {
950		phy  |= NFE_PHY_HDX;	/* half-duplex */
951		misc |= NFE_MISC1_HDX;
952	}
953
954	switch (IFM_SUBTYPE(mii->mii_media_active)) {
955	case IFM_1000_T:	/* full-duplex only */
956		link |= NFE_MEDIA_1000T;
957		seed |= NFE_SEED_1000T;
958		phy  |= NFE_PHY_1000T;
959		break;
960	case IFM_100_TX:
961		link |= NFE_MEDIA_100TX;
962		seed |= NFE_SEED_100TX;
963		phy  |= NFE_PHY_100TX;
964		break;
965	case IFM_10_T:
966		link |= NFE_MEDIA_10T;
967		seed |= NFE_SEED_10T;
968		break;
969	}
970
971	if ((phy & 0x10000000) != 0) {
972		if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T)
973			val = NFE_R1_MAGIC_1000;
974		else
975			val = NFE_R1_MAGIC_10_100;
976	} else
977		val = NFE_R1_MAGIC_DEFAULT;
978	NFE_WRITE(sc, NFE_SETUP_R1, val);
979
980	NFE_WRITE(sc, NFE_RNDSEED, seed);	/* XXX: gigabit NICs only? */
981
982	NFE_WRITE(sc, NFE_PHY_IFACE, phy);
983	NFE_WRITE(sc, NFE_MISC1, misc);
984	NFE_WRITE(sc, NFE_LINKSPEED, link);
985
986	if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
987		/* It seems all hardwares supports Rx pause frames. */
988		val = NFE_READ(sc, NFE_RXFILTER);
989		if ((IFM_OPTIONS(mii->mii_media_active) &
990		    IFM_ETH_RXPAUSE) != 0)
991			val |= NFE_PFF_RX_PAUSE;
992		else
993			val &= ~NFE_PFF_RX_PAUSE;
994		NFE_WRITE(sc, NFE_RXFILTER, val);
995		if ((sc->nfe_flags & NFE_TX_FLOW_CTRL) != 0) {
996			val = NFE_READ(sc, NFE_MISC1);
997			if ((IFM_OPTIONS(mii->mii_media_active) &
998			    IFM_ETH_TXPAUSE) != 0) {
999				NFE_WRITE(sc, NFE_TX_PAUSE_FRAME,
1000				    NFE_TX_PAUSE_FRAME_ENABLE);
1001				val |= NFE_MISC1_TX_PAUSE;
1002			} else {
1003				val &= ~NFE_MISC1_TX_PAUSE;
1004				NFE_WRITE(sc, NFE_TX_PAUSE_FRAME,
1005				    NFE_TX_PAUSE_FRAME_DISABLE);
1006			}
1007			NFE_WRITE(sc, NFE_MISC1, val);
1008		}
1009	} else {
1010		/* disable rx/tx pause frames */
1011		val = NFE_READ(sc, NFE_RXFILTER);
1012		val &= ~NFE_PFF_RX_PAUSE;
1013		NFE_WRITE(sc, NFE_RXFILTER, val);
1014		if ((sc->nfe_flags & NFE_TX_FLOW_CTRL) != 0) {
1015			NFE_WRITE(sc, NFE_TX_PAUSE_FRAME,
1016			    NFE_TX_PAUSE_FRAME_DISABLE);
1017			val = NFE_READ(sc, NFE_MISC1);
1018			val &= ~NFE_MISC1_TX_PAUSE;
1019			NFE_WRITE(sc, NFE_MISC1, val);
1020		}
1021	}
1022}
1023
1024
1025static int
1026nfe_miibus_readreg(device_t dev, int phy, int reg)
1027{
1028	struct nfe_softc *sc = device_get_softc(dev);
1029	uint32_t val;
1030	int ntries;
1031
1032	NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
1033
1034	if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) {
1035		NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY);
1036		DELAY(100);
1037	}
1038
1039	NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg);
1040
1041	for (ntries = 0; ntries < NFE_TIMEOUT; ntries++) {
1042		DELAY(100);
1043		if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY))
1044			break;
1045	}
1046	if (ntries == NFE_TIMEOUT) {
1047		DPRINTFN(sc, 2, "timeout waiting for PHY\n");
1048		return 0;
1049	}
1050
1051	if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) {
1052		DPRINTFN(sc, 2, "could not read PHY\n");
1053		return 0;
1054	}
1055
1056	val = NFE_READ(sc, NFE_PHY_DATA);
1057	if (val != 0xffffffff && val != 0)
1058		sc->mii_phyaddr = phy;
1059
1060	DPRINTFN(sc, 2, "mii read phy %d reg 0x%x ret 0x%x\n", phy, reg, val);
1061
1062	return (val);
1063}
1064
1065
1066static int
1067nfe_miibus_writereg(device_t dev, int phy, int reg, int val)
1068{
1069	struct nfe_softc *sc = device_get_softc(dev);
1070	uint32_t ctl;
1071	int ntries;
1072
1073	NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
1074
1075	if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) {
1076		NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY);
1077		DELAY(100);
1078	}
1079
1080	NFE_WRITE(sc, NFE_PHY_DATA, val);
1081	ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg;
1082	NFE_WRITE(sc, NFE_PHY_CTL, ctl);
1083
1084	for (ntries = 0; ntries < NFE_TIMEOUT; ntries++) {
1085		DELAY(100);
1086		if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY))
1087			break;
1088	}
1089#ifdef NFE_DEBUG
1090	if (nfedebug >= 2 && ntries == NFE_TIMEOUT)
1091		device_printf(sc->nfe_dev, "could not write to PHY\n");
1092#endif
1093	return (0);
1094}
1095
1096struct nfe_dmamap_arg {
1097	bus_addr_t nfe_busaddr;
1098};
1099
1100static int
1101nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1102{
1103	struct nfe_dmamap_arg ctx;
1104	struct nfe_rx_data *data;
1105	void *desc;
1106	int i, error, descsize;
1107
1108	if (sc->nfe_flags & NFE_40BIT_ADDR) {
1109		desc = ring->desc64;
1110		descsize = sizeof (struct nfe_desc64);
1111	} else {
1112		desc = ring->desc32;
1113		descsize = sizeof (struct nfe_desc32);
1114	}
1115
1116	ring->cur = ring->next = 0;
1117
1118	error = bus_dma_tag_create(sc->nfe_parent_tag,
1119	    NFE_RING_ALIGN, 0,			/* alignment, boundary */
1120	    BUS_SPACE_MAXADDR,			/* lowaddr */
1121	    BUS_SPACE_MAXADDR,			/* highaddr */
1122	    NULL, NULL,				/* filter, filterarg */
1123	    NFE_RX_RING_COUNT * descsize, 1,	/* maxsize, nsegments */
1124	    NFE_RX_RING_COUNT * descsize,	/* maxsegsize */
1125	    0,					/* flags */
1126	    NULL, NULL,				/* lockfunc, lockarg */
1127	    &ring->rx_desc_tag);
1128	if (error != 0) {
1129		device_printf(sc->nfe_dev, "could not create desc DMA tag\n");
1130		goto fail;
1131	}
1132
1133	/* allocate memory to desc */
1134	error = bus_dmamem_alloc(ring->rx_desc_tag, &desc, BUS_DMA_WAITOK |
1135	    BUS_DMA_COHERENT | BUS_DMA_ZERO, &ring->rx_desc_map);
1136	if (error != 0) {
1137		device_printf(sc->nfe_dev, "could not create desc DMA map\n");
1138		goto fail;
1139	}
1140	if (sc->nfe_flags & NFE_40BIT_ADDR)
1141		ring->desc64 = desc;
1142	else
1143		ring->desc32 = desc;
1144
1145	/* map desc to device visible address space */
1146	ctx.nfe_busaddr = 0;
1147	error = bus_dmamap_load(ring->rx_desc_tag, ring->rx_desc_map, desc,
1148	    NFE_RX_RING_COUNT * descsize, nfe_dma_map_segs, &ctx, 0);
1149	if (error != 0) {
1150		device_printf(sc->nfe_dev, "could not load desc DMA map\n");
1151		goto fail;
1152	}
1153	ring->physaddr = ctx.nfe_busaddr;
1154
1155	error = bus_dma_tag_create(sc->nfe_parent_tag,
1156	    1, 0,			/* alignment, boundary */
1157	    BUS_SPACE_MAXADDR,		/* lowaddr */
1158	    BUS_SPACE_MAXADDR,		/* highaddr */
1159	    NULL, NULL,			/* filter, filterarg */
1160	    MCLBYTES, 1,		/* maxsize, nsegments */
1161	    MCLBYTES,			/* maxsegsize */
1162	    0,				/* flags */
1163	    NULL, NULL,			/* lockfunc, lockarg */
1164	    &ring->rx_data_tag);
1165	if (error != 0) {
1166		device_printf(sc->nfe_dev, "could not create Rx DMA tag\n");
1167		goto fail;
1168	}
1169
1170	error = bus_dmamap_create(ring->rx_data_tag, 0, &ring->rx_spare_map);
1171	if (error != 0) {
1172		device_printf(sc->nfe_dev,
1173		    "could not create Rx DMA spare map\n");
1174		goto fail;
1175	}
1176
1177	/*
1178	 * Pre-allocate Rx buffers and populate Rx ring.
1179	 */
1180	for (i = 0; i < NFE_RX_RING_COUNT; i++) {
1181		data = &sc->rxq.data[i];
1182		data->rx_data_map = NULL;
1183		data->m = NULL;
1184		error = bus_dmamap_create(ring->rx_data_tag, 0,
1185		    &data->rx_data_map);
1186		if (error != 0) {
1187			device_printf(sc->nfe_dev,
1188			    "could not create Rx DMA map\n");
1189			goto fail;
1190		}
1191	}
1192
1193fail:
1194	return (error);
1195}
1196
1197
1198static void
1199nfe_alloc_jrx_ring(struct nfe_softc *sc, struct nfe_jrx_ring *ring)
1200{
1201	struct nfe_dmamap_arg ctx;
1202	struct nfe_rx_data *data;
1203	void *desc;
1204	int i, error, descsize;
1205
1206	if ((sc->nfe_flags & NFE_JUMBO_SUP) == 0)
1207		return;
1208	if (jumbo_disable != 0) {
1209		device_printf(sc->nfe_dev, "disabling jumbo frame support\n");
1210		sc->nfe_jumbo_disable = 1;
1211		return;
1212	}
1213
1214	if (sc->nfe_flags & NFE_40BIT_ADDR) {
1215		desc = ring->jdesc64;
1216		descsize = sizeof (struct nfe_desc64);
1217	} else {
1218		desc = ring->jdesc32;
1219		descsize = sizeof (struct nfe_desc32);
1220	}
1221
1222	ring->jcur = ring->jnext = 0;
1223
1224	/* Create DMA tag for jumbo Rx ring. */
1225	error = bus_dma_tag_create(sc->nfe_parent_tag,
1226	    NFE_RING_ALIGN, 0,			/* alignment, boundary */
1227	    BUS_SPACE_MAXADDR,			/* lowaddr */
1228	    BUS_SPACE_MAXADDR,			/* highaddr */
1229	    NULL, NULL,				/* filter, filterarg */
1230	    NFE_JUMBO_RX_RING_COUNT * descsize,	/* maxsize */
1231	    1, 					/* nsegments */
1232	    NFE_JUMBO_RX_RING_COUNT * descsize,	/* maxsegsize */
1233	    0,					/* flags */
1234	    NULL, NULL,				/* lockfunc, lockarg */
1235	    &ring->jrx_desc_tag);
1236	if (error != 0) {
1237		device_printf(sc->nfe_dev,
1238		    "could not create jumbo ring DMA tag\n");
1239		goto fail;
1240	}
1241
1242	/* Create DMA tag for jumbo Rx buffers. */
1243	error = bus_dma_tag_create(sc->nfe_parent_tag,
1244	    1, 0,				/* alignment, boundary */
1245	    BUS_SPACE_MAXADDR,			/* lowaddr */
1246	    BUS_SPACE_MAXADDR,			/* highaddr */
1247	    NULL, NULL,				/* filter, filterarg */
1248	    MJUM9BYTES,				/* maxsize */
1249	    1,					/* nsegments */
1250	    MJUM9BYTES,				/* maxsegsize */
1251	    0,					/* flags */
1252	    NULL, NULL,				/* lockfunc, lockarg */
1253	    &ring->jrx_data_tag);
1254	if (error != 0) {
1255		device_printf(sc->nfe_dev,
1256		    "could not create jumbo Rx buffer DMA tag\n");
1257		goto fail;
1258	}
1259
1260	/* Allocate DMA'able memory and load the DMA map for jumbo Rx ring. */
1261	error = bus_dmamem_alloc(ring->jrx_desc_tag, &desc, BUS_DMA_WAITOK |
1262	    BUS_DMA_COHERENT | BUS_DMA_ZERO, &ring->jrx_desc_map);
1263	if (error != 0) {
1264		device_printf(sc->nfe_dev,
1265		    "could not allocate DMA'able memory for jumbo Rx ring\n");
1266		goto fail;
1267	}
1268	if (sc->nfe_flags & NFE_40BIT_ADDR)
1269		ring->jdesc64 = desc;
1270	else
1271		ring->jdesc32 = desc;
1272
1273	ctx.nfe_busaddr = 0;
1274	error = bus_dmamap_load(ring->jrx_desc_tag, ring->jrx_desc_map, desc,
1275	    NFE_JUMBO_RX_RING_COUNT * descsize, nfe_dma_map_segs, &ctx, 0);
1276	if (error != 0) {
1277		device_printf(sc->nfe_dev,
1278		    "could not load DMA'able memory for jumbo Rx ring\n");
1279		goto fail;
1280	}
1281	ring->jphysaddr = ctx.nfe_busaddr;
1282
1283	/* Create DMA maps for jumbo Rx buffers. */
1284	error = bus_dmamap_create(ring->jrx_data_tag, 0, &ring->jrx_spare_map);
1285	if (error != 0) {
1286		device_printf(sc->nfe_dev,
1287		    "could not create jumbo Rx DMA spare map\n");
1288		goto fail;
1289	}
1290
1291	for (i = 0; i < NFE_JUMBO_RX_RING_COUNT; i++) {
1292		data = &sc->jrxq.jdata[i];
1293		data->rx_data_map = NULL;
1294		data->m = NULL;
1295		error = bus_dmamap_create(ring->jrx_data_tag, 0,
1296		    &data->rx_data_map);
1297		if (error != 0) {
1298			device_printf(sc->nfe_dev,
1299			    "could not create jumbo Rx DMA map\n");
1300			goto fail;
1301		}
1302	}
1303
1304	return;
1305
1306fail:
1307	/*
1308	 * Running without jumbo frame support is ok for most cases
1309	 * so don't fail on creating dma tag/map for jumbo frame.
1310	 */
1311	nfe_free_jrx_ring(sc, ring);
1312	device_printf(sc->nfe_dev, "disabling jumbo frame support due to "
1313	    "resource shortage\n");
1314	sc->nfe_jumbo_disable = 1;
1315}
1316
1317
1318static int
1319nfe_init_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1320{
1321	void *desc;
1322	size_t descsize;
1323	int i;
1324
1325	ring->cur = ring->next = 0;
1326	if (sc->nfe_flags & NFE_40BIT_ADDR) {
1327		desc = ring->desc64;
1328		descsize = sizeof (struct nfe_desc64);
1329	} else {
1330		desc = ring->desc32;
1331		descsize = sizeof (struct nfe_desc32);
1332	}
1333	bzero(desc, descsize * NFE_RX_RING_COUNT);
1334	for (i = 0; i < NFE_RX_RING_COUNT; i++) {
1335		if (nfe_newbuf(sc, i) != 0)
1336			return (ENOBUFS);
1337	}
1338
1339	bus_dmamap_sync(ring->rx_desc_tag, ring->rx_desc_map,
1340	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1341
1342	return (0);
1343}
1344
1345
1346static int
1347nfe_init_jrx_ring(struct nfe_softc *sc, struct nfe_jrx_ring *ring)
1348{
1349	void *desc;
1350	size_t descsize;
1351	int i;
1352
1353	ring->jcur = ring->jnext = 0;
1354	if (sc->nfe_flags & NFE_40BIT_ADDR) {
1355		desc = ring->jdesc64;
1356		descsize = sizeof (struct nfe_desc64);
1357	} else {
1358		desc = ring->jdesc32;
1359		descsize = sizeof (struct nfe_desc32);
1360	}
1361	bzero(desc, descsize * NFE_JUMBO_RX_RING_COUNT);
1362	for (i = 0; i < NFE_JUMBO_RX_RING_COUNT; i++) {
1363		if (nfe_jnewbuf(sc, i) != 0)
1364			return (ENOBUFS);
1365	}
1366
1367	bus_dmamap_sync(ring->jrx_desc_tag, ring->jrx_desc_map,
1368	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1369
1370	return (0);
1371}
1372
1373
1374static void
1375nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1376{
1377	struct nfe_rx_data *data;
1378	void *desc;
1379	int i;
1380
1381	if (sc->nfe_flags & NFE_40BIT_ADDR)
1382		desc = ring->desc64;
1383	else
1384		desc = ring->desc32;
1385
1386	for (i = 0; i < NFE_RX_RING_COUNT; i++) {
1387		data = &ring->data[i];
1388		if (data->rx_data_map != NULL) {
1389			bus_dmamap_destroy(ring->rx_data_tag,
1390			    data->rx_data_map);
1391			data->rx_data_map = NULL;
1392		}
1393		if (data->m != NULL) {
1394			m_freem(data->m);
1395			data->m = NULL;
1396		}
1397	}
1398	if (ring->rx_data_tag != NULL) {
1399		if (ring->rx_spare_map != NULL) {
1400			bus_dmamap_destroy(ring->rx_data_tag,
1401			    ring->rx_spare_map);
1402			ring->rx_spare_map = NULL;
1403		}
1404		bus_dma_tag_destroy(ring->rx_data_tag);
1405		ring->rx_data_tag = NULL;
1406	}
1407
1408	if (desc != NULL) {
1409		bus_dmamap_unload(ring->rx_desc_tag, ring->rx_desc_map);
1410		bus_dmamem_free(ring->rx_desc_tag, desc, ring->rx_desc_map);
1411		ring->desc64 = NULL;
1412		ring->desc32 = NULL;
1413	}
1414	if (ring->rx_desc_tag != NULL) {
1415		bus_dma_tag_destroy(ring->rx_desc_tag);
1416		ring->rx_desc_tag = NULL;
1417	}
1418}
1419
1420
1421static void
1422nfe_free_jrx_ring(struct nfe_softc *sc, struct nfe_jrx_ring *ring)
1423{
1424	struct nfe_rx_data *data;
1425	void *desc;
1426	int i, descsize;
1427
1428	if ((sc->nfe_flags & NFE_JUMBO_SUP) == 0)
1429		return;
1430
1431	if (sc->nfe_flags & NFE_40BIT_ADDR) {
1432		desc = ring->jdesc64;
1433		descsize = sizeof (struct nfe_desc64);
1434	} else {
1435		desc = ring->jdesc32;
1436		descsize = sizeof (struct nfe_desc32);
1437	}
1438
1439	for (i = 0; i < NFE_JUMBO_RX_RING_COUNT; i++) {
1440		data = &ring->jdata[i];
1441		if (data->rx_data_map != NULL) {
1442			bus_dmamap_destroy(ring->jrx_data_tag,
1443			    data->rx_data_map);
1444			data->rx_data_map = NULL;
1445		}
1446		if (data->m != NULL) {
1447			m_freem(data->m);
1448			data->m = NULL;
1449		}
1450	}
1451	if (ring->jrx_data_tag != NULL) {
1452		if (ring->jrx_spare_map != NULL) {
1453			bus_dmamap_destroy(ring->jrx_data_tag,
1454			    ring->jrx_spare_map);
1455			ring->jrx_spare_map = NULL;
1456		}
1457		bus_dma_tag_destroy(ring->jrx_data_tag);
1458		ring->jrx_data_tag = NULL;
1459	}
1460
1461	if (desc != NULL) {
1462		bus_dmamap_unload(ring->jrx_desc_tag, ring->jrx_desc_map);
1463		bus_dmamem_free(ring->jrx_desc_tag, desc, ring->jrx_desc_map);
1464		ring->jdesc64 = NULL;
1465		ring->jdesc32 = NULL;
1466	}
1467
1468	if (ring->jrx_desc_tag != NULL) {
1469		bus_dma_tag_destroy(ring->jrx_desc_tag);
1470		ring->jrx_desc_tag = NULL;
1471	}
1472}
1473
1474
1475static int
1476nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring)
1477{
1478	struct nfe_dmamap_arg ctx;
1479	int i, error;
1480	void *desc;
1481	int descsize;
1482
1483	if (sc->nfe_flags & NFE_40BIT_ADDR) {
1484		desc = ring->desc64;
1485		descsize = sizeof (struct nfe_desc64);
1486	} else {
1487		desc = ring->desc32;
1488		descsize = sizeof (struct nfe_desc32);
1489	}
1490
1491	ring->queued = 0;
1492	ring->cur = ring->next = 0;
1493
1494	error = bus_dma_tag_create(sc->nfe_parent_tag,
1495	    NFE_RING_ALIGN, 0,			/* alignment, boundary */
1496	    BUS_SPACE_MAXADDR,			/* lowaddr */
1497	    BUS_SPACE_MAXADDR,			/* highaddr */
1498	    NULL, NULL,				/* filter, filterarg */
1499	    NFE_TX_RING_COUNT * descsize, 1,	/* maxsize, nsegments */
1500	    NFE_TX_RING_COUNT * descsize,	/* maxsegsize */
1501	    0,					/* flags */
1502	    NULL, NULL,				/* lockfunc, lockarg */
1503	    &ring->tx_desc_tag);
1504	if (error != 0) {
1505		device_printf(sc->nfe_dev, "could not create desc DMA tag\n");
1506		goto fail;
1507	}
1508
1509	error = bus_dmamem_alloc(ring->tx_desc_tag, &desc, BUS_DMA_WAITOK |
1510	    BUS_DMA_COHERENT | BUS_DMA_ZERO, &ring->tx_desc_map);
1511	if (error != 0) {
1512		device_printf(sc->nfe_dev, "could not create desc DMA map\n");
1513		goto fail;
1514	}
1515	if (sc->nfe_flags & NFE_40BIT_ADDR)
1516		ring->desc64 = desc;
1517	else
1518		ring->desc32 = desc;
1519
1520	ctx.nfe_busaddr = 0;
1521	error = bus_dmamap_load(ring->tx_desc_tag, ring->tx_desc_map, desc,
1522	    NFE_TX_RING_COUNT * descsize, nfe_dma_map_segs, &ctx, 0);
1523	if (error != 0) {
1524		device_printf(sc->nfe_dev, "could not load desc DMA map\n");
1525		goto fail;
1526	}
1527	ring->physaddr = ctx.nfe_busaddr;
1528
1529	error = bus_dma_tag_create(sc->nfe_parent_tag,
1530	    1, 0,
1531	    BUS_SPACE_MAXADDR,
1532	    BUS_SPACE_MAXADDR,
1533	    NULL, NULL,
1534	    NFE_TSO_MAXSIZE,
1535	    NFE_MAX_SCATTER,
1536	    NFE_TSO_MAXSGSIZE,
1537	    0,
1538	    NULL, NULL,
1539	    &ring->tx_data_tag);
1540	if (error != 0) {
1541		device_printf(sc->nfe_dev, "could not create Tx DMA tag\n");
1542		goto fail;
1543	}
1544
1545	for (i = 0; i < NFE_TX_RING_COUNT; i++) {
1546		error = bus_dmamap_create(ring->tx_data_tag, 0,
1547		    &ring->data[i].tx_data_map);
1548		if (error != 0) {
1549			device_printf(sc->nfe_dev,
1550			    "could not create Tx DMA map\n");
1551			goto fail;
1552		}
1553	}
1554
1555fail:
1556	return (error);
1557}
1558
1559
1560static void
1561nfe_init_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring)
1562{
1563	void *desc;
1564	size_t descsize;
1565
1566	sc->nfe_force_tx = 0;
1567	ring->queued = 0;
1568	ring->cur = ring->next = 0;
1569	if (sc->nfe_flags & NFE_40BIT_ADDR) {
1570		desc = ring->desc64;
1571		descsize = sizeof (struct nfe_desc64);
1572	} else {
1573		desc = ring->desc32;
1574		descsize = sizeof (struct nfe_desc32);
1575	}
1576	bzero(desc, descsize * NFE_TX_RING_COUNT);
1577
1578	bus_dmamap_sync(ring->tx_desc_tag, ring->tx_desc_map,
1579	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1580}
1581
1582
1583static void
1584nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring)
1585{
1586	struct nfe_tx_data *data;
1587	void *desc;
1588	int i, descsize;
1589
1590	if (sc->nfe_flags & NFE_40BIT_ADDR) {
1591		desc = ring->desc64;
1592		descsize = sizeof (struct nfe_desc64);
1593	} else {
1594		desc = ring->desc32;
1595		descsize = sizeof (struct nfe_desc32);
1596	}
1597
1598	for (i = 0; i < NFE_TX_RING_COUNT; i++) {
1599		data = &ring->data[i];
1600
1601		if (data->m != NULL) {
1602			bus_dmamap_sync(ring->tx_data_tag, data->tx_data_map,
1603			    BUS_DMASYNC_POSTWRITE);
1604			bus_dmamap_unload(ring->tx_data_tag, data->tx_data_map);
1605			m_freem(data->m);
1606			data->m = NULL;
1607		}
1608		if (data->tx_data_map != NULL) {
1609			bus_dmamap_destroy(ring->tx_data_tag,
1610			    data->tx_data_map);
1611			data->tx_data_map = NULL;
1612		}
1613	}
1614
1615	if (ring->tx_data_tag != NULL) {
1616		bus_dma_tag_destroy(ring->tx_data_tag);
1617		ring->tx_data_tag = NULL;
1618	}
1619
1620	if (desc != NULL) {
1621		bus_dmamap_sync(ring->tx_desc_tag, ring->tx_desc_map,
1622		    BUS_DMASYNC_POSTWRITE);
1623		bus_dmamap_unload(ring->tx_desc_tag, ring->tx_desc_map);
1624		bus_dmamem_free(ring->tx_desc_tag, desc, ring->tx_desc_map);
1625		ring->desc64 = NULL;
1626		ring->desc32 = NULL;
1627		bus_dma_tag_destroy(ring->tx_desc_tag);
1628		ring->tx_desc_tag = NULL;
1629	}
1630}
1631
1632#ifdef DEVICE_POLLING
1633static poll_handler_t nfe_poll;
1634
1635
1636static int
1637nfe_poll(if_t ifp, enum poll_cmd cmd, int count)
1638{
1639	struct nfe_softc *sc = if_getsoftc(ifp);
1640	uint32_t r;
1641	int rx_npkts = 0;
1642
1643	NFE_LOCK(sc);
1644
1645	if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) {
1646		NFE_UNLOCK(sc);
1647		return (rx_npkts);
1648	}
1649
1650	if (sc->nfe_framesize > MCLBYTES - ETHER_HDR_LEN)
1651		rx_npkts = nfe_jrxeof(sc, count, &rx_npkts);
1652	else
1653		rx_npkts = nfe_rxeof(sc, count, &rx_npkts);
1654	nfe_txeof(sc);
1655	if (!if_sendq_empty(ifp))
1656		nfe_start_locked(ifp);
1657
1658	if (cmd == POLL_AND_CHECK_STATUS) {
1659		if ((r = NFE_READ(sc, sc->nfe_irq_status)) == 0) {
1660			NFE_UNLOCK(sc);
1661			return (rx_npkts);
1662		}
1663		NFE_WRITE(sc, sc->nfe_irq_status, r);
1664
1665		if (r & NFE_IRQ_LINK) {
1666			NFE_READ(sc, NFE_PHY_STATUS);
1667			NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
1668			DPRINTF(sc, "link state changed\n");
1669		}
1670	}
1671	NFE_UNLOCK(sc);
1672	return (rx_npkts);
1673}
1674#endif /* DEVICE_POLLING */
1675
1676static void
1677nfe_set_intr(struct nfe_softc *sc)
1678{
1679
1680	if (sc->nfe_msi != 0)
1681		NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED);
1682}
1683
1684
1685/* In MSIX, a write to mask reegisters behaves as XOR. */
1686static __inline void
1687nfe_enable_intr(struct nfe_softc *sc)
1688{
1689
1690	if (sc->nfe_msix != 0) {
1691		/* XXX Should have a better way to enable interrupts! */
1692		if (NFE_READ(sc, sc->nfe_irq_mask) == 0)
1693			NFE_WRITE(sc, sc->nfe_irq_mask, sc->nfe_intrs);
1694	} else
1695		NFE_WRITE(sc, sc->nfe_irq_mask, sc->nfe_intrs);
1696}
1697
1698
1699static __inline void
1700nfe_disable_intr(struct nfe_softc *sc)
1701{
1702
1703	if (sc->nfe_msix != 0) {
1704		/* XXX Should have a better way to disable interrupts! */
1705		if (NFE_READ(sc, sc->nfe_irq_mask) != 0)
1706			NFE_WRITE(sc, sc->nfe_irq_mask, sc->nfe_nointrs);
1707	} else
1708		NFE_WRITE(sc, sc->nfe_irq_mask, sc->nfe_nointrs);
1709}
1710
1711
1712static int
1713nfe_ioctl(if_t ifp, u_long cmd, caddr_t data)
1714{
1715	struct nfe_softc *sc;
1716	struct ifreq *ifr;
1717	struct mii_data *mii;
1718	int error, init, mask;
1719
1720	sc = if_getsoftc(ifp);
1721	ifr = (struct ifreq *) data;
1722	error = 0;
1723	init = 0;
1724	switch (cmd) {
1725	case SIOCSIFMTU:
1726		if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > NFE_JUMBO_MTU)
1727			error = EINVAL;
1728		else if (if_getmtu(ifp) != ifr->ifr_mtu) {
1729			if ((((sc->nfe_flags & NFE_JUMBO_SUP) == 0) ||
1730			    (sc->nfe_jumbo_disable != 0)) &&
1731			    ifr->ifr_mtu > ETHERMTU)
1732				error = EINVAL;
1733			else {
1734				NFE_LOCK(sc);
1735				if_setmtu(ifp, ifr->ifr_mtu);
1736				if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
1737					if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1738					nfe_init_locked(sc);
1739				}
1740				NFE_UNLOCK(sc);
1741			}
1742		}
1743		break;
1744	case SIOCSIFFLAGS:
1745		NFE_LOCK(sc);
1746		if (if_getflags(ifp) & IFF_UP) {
1747			/*
1748			 * If only the PROMISC or ALLMULTI flag changes, then
1749			 * don't do a full re-init of the chip, just update
1750			 * the Rx filter.
1751			 */
1752			if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) &&
1753			    ((if_getflags(ifp) ^ sc->nfe_if_flags) &
1754			     (IFF_ALLMULTI | IFF_PROMISC)) != 0)
1755				nfe_setmulti(sc);
1756			else
1757				nfe_init_locked(sc);
1758		} else {
1759			if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
1760				nfe_stop(ifp);
1761		}
1762		sc->nfe_if_flags = if_getflags(ifp);
1763		NFE_UNLOCK(sc);
1764		error = 0;
1765		break;
1766	case SIOCADDMULTI:
1767	case SIOCDELMULTI:
1768		if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
1769			NFE_LOCK(sc);
1770			nfe_setmulti(sc);
1771			NFE_UNLOCK(sc);
1772			error = 0;
1773		}
1774		break;
1775	case SIOCSIFMEDIA:
1776	case SIOCGIFMEDIA:
1777		mii = device_get_softc(sc->nfe_miibus);
1778		error = ifmedia_ioctl_drv(ifp, ifr, &mii->mii_media, cmd);
1779		break;
1780	case SIOCSIFCAP:
1781		mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
1782#ifdef DEVICE_POLLING
1783		if ((mask & IFCAP_POLLING) != 0) {
1784			if ((ifr->ifr_reqcap & IFCAP_POLLING) != 0) {
1785				error = ether_poll_register(nfe_poll, ifp);
1786				if (error)
1787					break;
1788				NFE_LOCK(sc);
1789				nfe_disable_intr(sc);
1790				if_setcapenablebit(ifp, IFCAP_POLLING, 0);
1791				NFE_UNLOCK(sc);
1792			} else {
1793				error = ether_poll_deregister(ifp);
1794				/* Enable interrupt even in error case */
1795				NFE_LOCK(sc);
1796				nfe_enable_intr(sc);
1797				if_setcapenablebit(ifp, 0, IFCAP_POLLING);
1798				NFE_UNLOCK(sc);
1799			}
1800		}
1801#endif /* DEVICE_POLLING */
1802		if ((mask & IFCAP_WOL_MAGIC) != 0 &&
1803		    (if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0)
1804			if_togglecapenable(ifp, IFCAP_WOL_MAGIC);
1805		if ((mask & IFCAP_TXCSUM) != 0 &&
1806		    (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) {
1807			if_togglecapenable(ifp, IFCAP_TXCSUM);
1808			if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0)
1809				if_sethwassistbits(ifp, NFE_CSUM_FEATURES, 0);
1810			else
1811				if_sethwassistbits(ifp, 0, NFE_CSUM_FEATURES);
1812		}
1813		if ((mask & IFCAP_RXCSUM) != 0 &&
1814		    (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) {
1815			if_togglecapenable(ifp, IFCAP_RXCSUM);
1816			init++;
1817		}
1818		if ((mask & IFCAP_TSO4) != 0 &&
1819		    (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) {
1820			if_togglecapenable(ifp, IFCAP_TSO4);
1821			if ((IFCAP_TSO4 & if_getcapenable(ifp)) != 0)
1822				if_sethwassistbits(ifp, CSUM_TSO, 0);
1823			else
1824				if_sethwassistbits(ifp, 0, CSUM_TSO);
1825		}
1826		if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
1827		    (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0)
1828			if_togglecapenable(ifp, IFCAP_VLAN_HWTSO);
1829		if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
1830		    (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) {
1831			if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING);
1832			if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0)
1833				if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO);
1834			init++;
1835		}
1836		/*
1837		 * XXX
1838		 * It seems that VLAN stripping requires Rx checksum offload.
1839		 * Unfortunately FreeBSD has no way to disable only Rx side
1840		 * VLAN stripping. So when we know Rx checksum offload is
1841		 * disabled turn entire hardware VLAN assist off.
1842		 */
1843		if ((if_getcapenable(ifp) & IFCAP_RXCSUM) == 0) {
1844			if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0)
1845				init++;
1846			if_setcapenablebit(ifp, 0,
1847			    (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWTSO));
1848		}
1849		if (init > 0 && (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
1850			if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1851			nfe_init(sc);
1852		}
1853		if_vlancap(ifp);
1854		break;
1855	default:
1856		error = ether_ioctl_drv(ifp, cmd, data);
1857		break;
1858	}
1859
1860	return (error);
1861}
1862
1863
1864static int
1865nfe_intr(void *arg)
1866{
1867	struct nfe_softc *sc;
1868	uint32_t status;
1869
1870	sc = (struct nfe_softc *)arg;
1871
1872	status = NFE_READ(sc, sc->nfe_irq_status);
1873	if (status == 0 || status == 0xffffffff)
1874		return (FILTER_STRAY);
1875	nfe_disable_intr(sc);
1876	taskqueue_enqueue_fast(sc->nfe_tq, &sc->nfe_int_task);
1877
1878	return (FILTER_HANDLED);
1879}
1880
1881
1882static void
1883nfe_int_task(void *arg, int pending)
1884{
1885	struct nfe_softc *sc = arg;
1886	if_t ifp = sc->nfe_ifp;
1887	uint32_t r;
1888	int domore;
1889
1890	NFE_LOCK(sc);
1891
1892	if ((r = NFE_READ(sc, sc->nfe_irq_status)) == 0) {
1893		nfe_enable_intr(sc);
1894		NFE_UNLOCK(sc);
1895		return;	/* not for us */
1896	}
1897	NFE_WRITE(sc, sc->nfe_irq_status, r);
1898
1899	DPRINTFN(sc, 5, "nfe_intr: interrupt register %x\n", r);
1900
1901#ifdef DEVICE_POLLING
1902	if (if_getcapenable(ifp) & IFCAP_POLLING) {
1903		NFE_UNLOCK(sc);
1904		return;
1905	}
1906#endif
1907
1908	if (r & NFE_IRQ_LINK) {
1909		NFE_READ(sc, NFE_PHY_STATUS);
1910		NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
1911		DPRINTF(sc, "link state changed\n");
1912	}
1913
1914	if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) {
1915		NFE_UNLOCK(sc);
1916		nfe_disable_intr(sc);
1917		return;
1918	}
1919
1920	domore = 0;
1921	/* check Rx ring */
1922	if (sc->nfe_framesize > MCLBYTES - ETHER_HDR_LEN)
1923		domore = nfe_jrxeof(sc, sc->nfe_process_limit, NULL);
1924	else
1925		domore = nfe_rxeof(sc, sc->nfe_process_limit, NULL);
1926	/* check Tx ring */
1927	nfe_txeof(sc);
1928
1929	if (!if_sendq_empty(ifp))
1930		nfe_start_locked(ifp);
1931
1932	NFE_UNLOCK(sc);
1933
1934	if (domore || (NFE_READ(sc, sc->nfe_irq_status) != 0)) {
1935		taskqueue_enqueue_fast(sc->nfe_tq, &sc->nfe_int_task);
1936		return;
1937	}
1938
1939	/* Reenable interrupts. */
1940	nfe_enable_intr(sc);
1941}
1942
1943
1944static __inline void
1945nfe_discard_rxbuf(struct nfe_softc *sc, int idx)
1946{
1947	struct nfe_desc32 *desc32;
1948	struct nfe_desc64 *desc64;
1949	struct nfe_rx_data *data;
1950	struct mbuf *m;
1951
1952	data = &sc->rxq.data[idx];
1953	m = data->m;
1954
1955	if (sc->nfe_flags & NFE_40BIT_ADDR) {
1956		desc64 = &sc->rxq.desc64[idx];
1957		/* VLAN packet may have overwritten it. */
1958		desc64->physaddr[0] = htole32(NFE_ADDR_HI(data->paddr));
1959		desc64->physaddr[1] = htole32(NFE_ADDR_LO(data->paddr));
1960		desc64->length = htole16(m->m_len);
1961		desc64->flags = htole16(NFE_RX_READY);
1962	} else {
1963		desc32 = &sc->rxq.desc32[idx];
1964		desc32->length = htole16(m->m_len);
1965		desc32->flags = htole16(NFE_RX_READY);
1966	}
1967}
1968
1969
1970static __inline void
1971nfe_discard_jrxbuf(struct nfe_softc *sc, int idx)
1972{
1973	struct nfe_desc32 *desc32;
1974	struct nfe_desc64 *desc64;
1975	struct nfe_rx_data *data;
1976	struct mbuf *m;
1977
1978	data = &sc->jrxq.jdata[idx];
1979	m = data->m;
1980
1981	if (sc->nfe_flags & NFE_40BIT_ADDR) {
1982		desc64 = &sc->jrxq.jdesc64[idx];
1983		/* VLAN packet may have overwritten it. */
1984		desc64->physaddr[0] = htole32(NFE_ADDR_HI(data->paddr));
1985		desc64->physaddr[1] = htole32(NFE_ADDR_LO(data->paddr));
1986		desc64->length = htole16(m->m_len);
1987		desc64->flags = htole16(NFE_RX_READY);
1988	} else {
1989		desc32 = &sc->jrxq.jdesc32[idx];
1990		desc32->length = htole16(m->m_len);
1991		desc32->flags = htole16(NFE_RX_READY);
1992	}
1993}
1994
1995
1996static int
1997nfe_newbuf(struct nfe_softc *sc, int idx)
1998{
1999	struct nfe_rx_data *data;
2000	struct nfe_desc32 *desc32;
2001	struct nfe_desc64 *desc64;
2002	struct mbuf *m;
2003	bus_dma_segment_t segs[1];
2004	bus_dmamap_t map;
2005	int nsegs;
2006
2007	m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
2008	if (m == NULL)
2009		return (ENOBUFS);
2010
2011	m->m_len = m->m_pkthdr.len = MCLBYTES;
2012	m_adj(m, ETHER_ALIGN);
2013
2014	if (bus_dmamap_load_mbuf_sg(sc->rxq.rx_data_tag, sc->rxq.rx_spare_map,
2015	    m, segs, &nsegs, BUS_DMA_NOWAIT) != 0) {
2016		m_freem(m);
2017		return (ENOBUFS);
2018	}
2019	KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
2020
2021	data = &sc->rxq.data[idx];
2022	if (data->m != NULL) {
2023		bus_dmamap_sync(sc->rxq.rx_data_tag, data->rx_data_map,
2024		    BUS_DMASYNC_POSTREAD);
2025		bus_dmamap_unload(sc->rxq.rx_data_tag, data->rx_data_map);
2026	}
2027	map = data->rx_data_map;
2028	data->rx_data_map = sc->rxq.rx_spare_map;
2029	sc->rxq.rx_spare_map = map;
2030	bus_dmamap_sync(sc->rxq.rx_data_tag, data->rx_data_map,
2031	    BUS_DMASYNC_PREREAD);
2032	data->paddr = segs[0].ds_addr;
2033	data->m = m;
2034	/* update mapping address in h/w descriptor */
2035	if (sc->nfe_flags & NFE_40BIT_ADDR) {
2036		desc64 = &sc->rxq.desc64[idx];
2037		desc64->physaddr[0] = htole32(NFE_ADDR_HI(segs[0].ds_addr));
2038		desc64->physaddr[1] = htole32(NFE_ADDR_LO(segs[0].ds_addr));
2039		desc64->length = htole16(segs[0].ds_len);
2040		desc64->flags = htole16(NFE_RX_READY);
2041	} else {
2042		desc32 = &sc->rxq.desc32[idx];
2043		desc32->physaddr = htole32(NFE_ADDR_LO(segs[0].ds_addr));
2044		desc32->length = htole16(segs[0].ds_len);
2045		desc32->flags = htole16(NFE_RX_READY);
2046	}
2047
2048	return (0);
2049}
2050
2051
2052static int
2053nfe_jnewbuf(struct nfe_softc *sc, int idx)
2054{
2055	struct nfe_rx_data *data;
2056	struct nfe_desc32 *desc32;
2057	struct nfe_desc64 *desc64;
2058	struct mbuf *m;
2059	bus_dma_segment_t segs[1];
2060	bus_dmamap_t map;
2061	int nsegs;
2062
2063	m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
2064	if (m == NULL)
2065		return (ENOBUFS);
2066	if ((m->m_flags & M_EXT) == 0) {
2067		m_freem(m);
2068		return (ENOBUFS);
2069	}
2070	m->m_pkthdr.len = m->m_len = MJUM9BYTES;
2071	m_adj(m, ETHER_ALIGN);
2072
2073	if (bus_dmamap_load_mbuf_sg(sc->jrxq.jrx_data_tag,
2074	    sc->jrxq.jrx_spare_map, m, segs, &nsegs, BUS_DMA_NOWAIT) != 0) {
2075		m_freem(m);
2076		return (ENOBUFS);
2077	}
2078	KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
2079
2080	data = &sc->jrxq.jdata[idx];
2081	if (data->m != NULL) {
2082		bus_dmamap_sync(sc->jrxq.jrx_data_tag, data->rx_data_map,
2083		    BUS_DMASYNC_POSTREAD);
2084		bus_dmamap_unload(sc->jrxq.jrx_data_tag, data->rx_data_map);
2085	}
2086	map = data->rx_data_map;
2087	data->rx_data_map = sc->jrxq.jrx_spare_map;
2088	sc->jrxq.jrx_spare_map = map;
2089	bus_dmamap_sync(sc->jrxq.jrx_data_tag, data->rx_data_map,
2090	    BUS_DMASYNC_PREREAD);
2091	data->paddr = segs[0].ds_addr;
2092	data->m = m;
2093	/* update mapping address in h/w descriptor */
2094	if (sc->nfe_flags & NFE_40BIT_ADDR) {
2095		desc64 = &sc->jrxq.jdesc64[idx];
2096		desc64->physaddr[0] = htole32(NFE_ADDR_HI(segs[0].ds_addr));
2097		desc64->physaddr[1] = htole32(NFE_ADDR_LO(segs[0].ds_addr));
2098		desc64->length = htole16(segs[0].ds_len);
2099		desc64->flags = htole16(NFE_RX_READY);
2100	} else {
2101		desc32 = &sc->jrxq.jdesc32[idx];
2102		desc32->physaddr = htole32(NFE_ADDR_LO(segs[0].ds_addr));
2103		desc32->length = htole16(segs[0].ds_len);
2104		desc32->flags = htole16(NFE_RX_READY);
2105	}
2106
2107	return (0);
2108}
2109
2110
2111static int
2112nfe_rxeof(struct nfe_softc *sc, int count, int *rx_npktsp)
2113{
2114	if_t ifp = sc->nfe_ifp;
2115	struct nfe_desc32 *desc32;
2116	struct nfe_desc64 *desc64;
2117	struct nfe_rx_data *data;
2118	struct mbuf *m;
2119	uint16_t flags;
2120	int len, prog, rx_npkts;
2121	uint32_t vtag = 0;
2122
2123	rx_npkts = 0;
2124	NFE_LOCK_ASSERT(sc);
2125
2126	bus_dmamap_sync(sc->rxq.rx_desc_tag, sc->rxq.rx_desc_map,
2127	    BUS_DMASYNC_POSTREAD);
2128
2129	for (prog = 0;;NFE_INC(sc->rxq.cur, NFE_RX_RING_COUNT), vtag = 0) {
2130		if (count <= 0)
2131			break;
2132		count--;
2133
2134		data = &sc->rxq.data[sc->rxq.cur];
2135
2136		if (sc->nfe_flags & NFE_40BIT_ADDR) {
2137			desc64 = &sc->rxq.desc64[sc->rxq.cur];
2138			vtag = le32toh(desc64->physaddr[1]);
2139			flags = le16toh(desc64->flags);
2140			len = le16toh(desc64->length) & NFE_RX_LEN_MASK;
2141		} else {
2142			desc32 = &sc->rxq.desc32[sc->rxq.cur];
2143			flags = le16toh(desc32->flags);
2144			len = le16toh(desc32->length) & NFE_RX_LEN_MASK;
2145		}
2146
2147		if (flags & NFE_RX_READY)
2148			break;
2149		prog++;
2150		if ((sc->nfe_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) {
2151			if (!(flags & NFE_RX_VALID_V1)) {
2152				if_incierrors(ifp, 1);
2153				nfe_discard_rxbuf(sc, sc->rxq.cur);
2154				continue;
2155			}
2156			if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) {
2157				flags &= ~NFE_RX_ERROR;
2158				len--;	/* fix buffer length */
2159			}
2160		} else {
2161			if (!(flags & NFE_RX_VALID_V2)) {
2162				if_incierrors(ifp, 1);
2163				nfe_discard_rxbuf(sc, sc->rxq.cur);
2164				continue;
2165			}
2166
2167			if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) {
2168				flags &= ~NFE_RX_ERROR;
2169				len--;	/* fix buffer length */
2170			}
2171		}
2172
2173		if (flags & NFE_RX_ERROR) {
2174			if_incierrors(ifp, 1);
2175			nfe_discard_rxbuf(sc, sc->rxq.cur);
2176			continue;
2177		}
2178
2179		m = data->m;
2180		if (nfe_newbuf(sc, sc->rxq.cur) != 0) {
2181			if_inciqdrops(ifp, 1);
2182			nfe_discard_rxbuf(sc, sc->rxq.cur);
2183			continue;
2184		}
2185
2186		if ((vtag & NFE_RX_VTAG) != 0 &&
2187		    (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) {
2188			m->m_pkthdr.ether_vtag = vtag & 0xffff;
2189			m->m_flags |= M_VLANTAG;
2190		}
2191
2192		m->m_pkthdr.len = m->m_len = len;
2193		m->m_pkthdr.rcvif = ifp;
2194
2195		if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) {
2196			if ((flags & NFE_RX_IP_CSUMOK) != 0) {
2197				m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2198				m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2199				if ((flags & NFE_RX_TCP_CSUMOK) != 0 ||
2200				    (flags & NFE_RX_UDP_CSUMOK) != 0) {
2201					m->m_pkthdr.csum_flags |=
2202					    CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2203					m->m_pkthdr.csum_data = 0xffff;
2204				}
2205			}
2206		}
2207
2208		if_incipackets(ifp, 1);
2209
2210		NFE_UNLOCK(sc);
2211		if_input(ifp, m);
2212		NFE_LOCK(sc);
2213		rx_npkts++;
2214	}
2215
2216	if (prog > 0)
2217		bus_dmamap_sync(sc->rxq.rx_desc_tag, sc->rxq.rx_desc_map,
2218		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2219
2220	if (rx_npktsp != NULL)
2221		*rx_npktsp = rx_npkts;
2222	return (count > 0 ? 0 : EAGAIN);
2223}
2224
2225
2226static int
2227nfe_jrxeof(struct nfe_softc *sc, int count, int *rx_npktsp)
2228{
2229	if_t ifp = sc->nfe_ifp;
2230	struct nfe_desc32 *desc32;
2231	struct nfe_desc64 *desc64;
2232	struct nfe_rx_data *data;
2233	struct mbuf *m;
2234	uint16_t flags;
2235	int len, prog, rx_npkts;
2236	uint32_t vtag = 0;
2237
2238	rx_npkts = 0;
2239	NFE_LOCK_ASSERT(sc);
2240
2241	bus_dmamap_sync(sc->jrxq.jrx_desc_tag, sc->jrxq.jrx_desc_map,
2242	    BUS_DMASYNC_POSTREAD);
2243
2244	for (prog = 0;;NFE_INC(sc->jrxq.jcur, NFE_JUMBO_RX_RING_COUNT),
2245	    vtag = 0) {
2246		if (count <= 0)
2247			break;
2248		count--;
2249
2250		data = &sc->jrxq.jdata[sc->jrxq.jcur];
2251
2252		if (sc->nfe_flags & NFE_40BIT_ADDR) {
2253			desc64 = &sc->jrxq.jdesc64[sc->jrxq.jcur];
2254			vtag = le32toh(desc64->physaddr[1]);
2255			flags = le16toh(desc64->flags);
2256			len = le16toh(desc64->length) & NFE_RX_LEN_MASK;
2257		} else {
2258			desc32 = &sc->jrxq.jdesc32[sc->jrxq.jcur];
2259			flags = le16toh(desc32->flags);
2260			len = le16toh(desc32->length) & NFE_RX_LEN_MASK;
2261		}
2262
2263		if (flags & NFE_RX_READY)
2264			break;
2265		prog++;
2266		if ((sc->nfe_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) {
2267			if (!(flags & NFE_RX_VALID_V1)) {
2268				if_incierrors(ifp, 1);
2269				nfe_discard_jrxbuf(sc, sc->jrxq.jcur);
2270				continue;
2271			}
2272			if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) {
2273				flags &= ~NFE_RX_ERROR;
2274				len--;	/* fix buffer length */
2275			}
2276		} else {
2277			if (!(flags & NFE_RX_VALID_V2)) {
2278				if_incierrors(ifp, 1);
2279				nfe_discard_jrxbuf(sc, sc->jrxq.jcur);
2280				continue;
2281			}
2282
2283			if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) {
2284				flags &= ~NFE_RX_ERROR;
2285				len--;	/* fix buffer length */
2286			}
2287		}
2288
2289		if (flags & NFE_RX_ERROR) {
2290			if_incierrors(ifp, 1);
2291			nfe_discard_jrxbuf(sc, sc->jrxq.jcur);
2292			continue;
2293		}
2294
2295		m = data->m;
2296		if (nfe_jnewbuf(sc, sc->jrxq.jcur) != 0) {
2297			if_inciqdrops(ifp, 1);
2298			nfe_discard_jrxbuf(sc, sc->jrxq.jcur);
2299			continue;
2300		}
2301
2302		if ((vtag & NFE_RX_VTAG) != 0 &&
2303		    (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) {
2304			m->m_pkthdr.ether_vtag = vtag & 0xffff;
2305			m->m_flags |= M_VLANTAG;
2306		}
2307
2308		m->m_pkthdr.len = m->m_len = len;
2309		m->m_pkthdr.rcvif = ifp;
2310
2311		if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) {
2312			if ((flags & NFE_RX_IP_CSUMOK) != 0) {
2313				m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2314				m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2315				if ((flags & NFE_RX_TCP_CSUMOK) != 0 ||
2316				    (flags & NFE_RX_UDP_CSUMOK) != 0) {
2317					m->m_pkthdr.csum_flags |=
2318					    CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2319					m->m_pkthdr.csum_data = 0xffff;
2320				}
2321			}
2322		}
2323
2324		if_incipackets(ifp, 1);
2325
2326		NFE_UNLOCK(sc);
2327		if_input(ifp, m);
2328		NFE_LOCK(sc);
2329		rx_npkts++;
2330	}
2331
2332	if (prog > 0)
2333		bus_dmamap_sync(sc->jrxq.jrx_desc_tag, sc->jrxq.jrx_desc_map,
2334		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2335
2336	if (rx_npktsp != NULL)
2337		*rx_npktsp = rx_npkts;
2338	return (count > 0 ? 0 : EAGAIN);
2339}
2340
2341
2342static void
2343nfe_txeof(struct nfe_softc *sc)
2344{
2345	if_t ifp = sc->nfe_ifp;
2346	struct nfe_desc32 *desc32;
2347	struct nfe_desc64 *desc64;
2348	struct nfe_tx_data *data = NULL;
2349	uint16_t flags;
2350	int cons, prog;
2351
2352	NFE_LOCK_ASSERT(sc);
2353
2354	bus_dmamap_sync(sc->txq.tx_desc_tag, sc->txq.tx_desc_map,
2355	    BUS_DMASYNC_POSTREAD);
2356
2357	prog = 0;
2358	for (cons = sc->txq.next; cons != sc->txq.cur;
2359	    NFE_INC(cons, NFE_TX_RING_COUNT)) {
2360		if (sc->nfe_flags & NFE_40BIT_ADDR) {
2361			desc64 = &sc->txq.desc64[cons];
2362			flags = le16toh(desc64->flags);
2363		} else {
2364			desc32 = &sc->txq.desc32[cons];
2365			flags = le16toh(desc32->flags);
2366		}
2367
2368		if (flags & NFE_TX_VALID)
2369			break;
2370
2371		prog++;
2372		sc->txq.queued--;
2373		data = &sc->txq.data[cons];
2374
2375		if ((sc->nfe_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) {
2376			if ((flags & NFE_TX_LASTFRAG_V1) == 0)
2377				continue;
2378			if ((flags & NFE_TX_ERROR_V1) != 0) {
2379				device_printf(sc->nfe_dev,
2380				    "tx v1 error 0x%4b\n", flags, NFE_V1_TXERR);
2381
2382				if_incoerrors(ifp, 1);
2383			} else
2384				if_incopackets(ifp, 1);
2385		} else {
2386			if ((flags & NFE_TX_LASTFRAG_V2) == 0)
2387				continue;
2388			if ((flags & NFE_TX_ERROR_V2) != 0) {
2389				device_printf(sc->nfe_dev,
2390				    "tx v2 error 0x%4b\n", flags, NFE_V2_TXERR);
2391				if_incoerrors(ifp, 1);
2392			} else
2393				if_incopackets(ifp, 1);
2394		}
2395
2396		/* last fragment of the mbuf chain transmitted */
2397		KASSERT(data->m != NULL, ("%s: freeing NULL mbuf!", __func__));
2398		bus_dmamap_sync(sc->txq.tx_data_tag, data->tx_data_map,
2399		    BUS_DMASYNC_POSTWRITE);
2400		bus_dmamap_unload(sc->txq.tx_data_tag, data->tx_data_map);
2401		m_freem(data->m);
2402		data->m = NULL;
2403	}
2404
2405	if (prog > 0) {
2406		sc->nfe_force_tx = 0;
2407		sc->txq.next = cons;
2408		if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
2409		if (sc->txq.queued == 0)
2410			sc->nfe_watchdog_timer = 0;
2411	}
2412}
2413
2414static int
2415nfe_encap(struct nfe_softc *sc, struct mbuf **m_head)
2416{
2417	struct nfe_desc32 *desc32 = NULL;
2418	struct nfe_desc64 *desc64 = NULL;
2419	bus_dmamap_t map;
2420	bus_dma_segment_t segs[NFE_MAX_SCATTER];
2421	int error, i, nsegs, prod, si;
2422	uint32_t tsosegsz;
2423	uint16_t cflags, flags;
2424	struct mbuf *m;
2425
2426	prod = si = sc->txq.cur;
2427	map = sc->txq.data[prod].tx_data_map;
2428
2429	error = bus_dmamap_load_mbuf_sg(sc->txq.tx_data_tag, map, *m_head, segs,
2430	    &nsegs, BUS_DMA_NOWAIT);
2431	if (error == EFBIG) {
2432		m = m_collapse(*m_head, M_NOWAIT, NFE_MAX_SCATTER);
2433		if (m == NULL) {
2434			m_freem(*m_head);
2435			*m_head = NULL;
2436			return (ENOBUFS);
2437		}
2438		*m_head = m;
2439		error = bus_dmamap_load_mbuf_sg(sc->txq.tx_data_tag, map,
2440		    *m_head, segs, &nsegs, BUS_DMA_NOWAIT);
2441		if (error != 0) {
2442			m_freem(*m_head);
2443			*m_head = NULL;
2444			return (ENOBUFS);
2445		}
2446	} else if (error != 0)
2447		return (error);
2448	if (nsegs == 0) {
2449		m_freem(*m_head);
2450		*m_head = NULL;
2451		return (EIO);
2452	}
2453
2454	if (sc->txq.queued + nsegs >= NFE_TX_RING_COUNT - 2) {
2455		bus_dmamap_unload(sc->txq.tx_data_tag, map);
2456		return (ENOBUFS);
2457	}
2458
2459	m = *m_head;
2460	cflags = flags = 0;
2461	tsosegsz = 0;
2462	if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
2463		tsosegsz = (uint32_t)m->m_pkthdr.tso_segsz <<
2464		    NFE_TX_TSO_SHIFT;
2465		cflags &= ~(NFE_TX_IP_CSUM | NFE_TX_TCP_UDP_CSUM);
2466		cflags |= NFE_TX_TSO;
2467	} else if ((m->m_pkthdr.csum_flags & NFE_CSUM_FEATURES) != 0) {
2468		if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0)
2469			cflags |= NFE_TX_IP_CSUM;
2470		if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0)
2471			cflags |= NFE_TX_TCP_UDP_CSUM;
2472		if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0)
2473			cflags |= NFE_TX_TCP_UDP_CSUM;
2474	}
2475
2476	for (i = 0; i < nsegs; i++) {
2477		if (sc->nfe_flags & NFE_40BIT_ADDR) {
2478			desc64 = &sc->txq.desc64[prod];
2479			desc64->physaddr[0] =
2480			    htole32(NFE_ADDR_HI(segs[i].ds_addr));
2481			desc64->physaddr[1] =
2482			    htole32(NFE_ADDR_LO(segs[i].ds_addr));
2483			desc64->vtag = 0;
2484			desc64->length = htole16(segs[i].ds_len - 1);
2485			desc64->flags = htole16(flags);
2486		} else {
2487			desc32 = &sc->txq.desc32[prod];
2488			desc32->physaddr =
2489			    htole32(NFE_ADDR_LO(segs[i].ds_addr));
2490			desc32->length = htole16(segs[i].ds_len - 1);
2491			desc32->flags = htole16(flags);
2492		}
2493
2494		/*
2495		 * Setting of the valid bit in the first descriptor is
2496		 * deferred until the whole chain is fully setup.
2497		 */
2498		flags |= NFE_TX_VALID;
2499
2500		sc->txq.queued++;
2501		NFE_INC(prod, NFE_TX_RING_COUNT);
2502	}
2503
2504	/*
2505	 * the whole mbuf chain has been DMA mapped, fix last/first descriptor.
2506	 * csum flags, vtag and TSO belong to the first fragment only.
2507	 */
2508	if (sc->nfe_flags & NFE_40BIT_ADDR) {
2509		desc64->flags |= htole16(NFE_TX_LASTFRAG_V2);
2510		desc64 = &sc->txq.desc64[si];
2511		if ((m->m_flags & M_VLANTAG) != 0)
2512			desc64->vtag = htole32(NFE_TX_VTAG |
2513			    m->m_pkthdr.ether_vtag);
2514		if (tsosegsz != 0) {
2515			/*
2516			 * XXX
2517			 * The following indicates the descriptor element
2518			 * is a 32bit quantity.
2519			 */
2520			desc64->length |= htole16((uint16_t)tsosegsz);
2521			desc64->flags |= htole16(tsosegsz >> 16);
2522		}
2523		/*
2524		 * finally, set the valid/checksum/TSO bit in the first
2525		 * descriptor.
2526		 */
2527		desc64->flags |= htole16(NFE_TX_VALID | cflags);
2528	} else {
2529		if (sc->nfe_flags & NFE_JUMBO_SUP)
2530			desc32->flags |= htole16(NFE_TX_LASTFRAG_V2);
2531		else
2532			desc32->flags |= htole16(NFE_TX_LASTFRAG_V1);
2533		desc32 = &sc->txq.desc32[si];
2534		if (tsosegsz != 0) {
2535			/*
2536			 * XXX
2537			 * The following indicates the descriptor element
2538			 * is a 32bit quantity.
2539			 */
2540			desc32->length |= htole16((uint16_t)tsosegsz);
2541			desc32->flags |= htole16(tsosegsz >> 16);
2542		}
2543		/*
2544		 * finally, set the valid/checksum/TSO bit in the first
2545		 * descriptor.
2546		 */
2547		desc32->flags |= htole16(NFE_TX_VALID | cflags);
2548	}
2549
2550	sc->txq.cur = prod;
2551	prod = (prod + NFE_TX_RING_COUNT - 1) % NFE_TX_RING_COUNT;
2552	sc->txq.data[si].tx_data_map = sc->txq.data[prod].tx_data_map;
2553	sc->txq.data[prod].tx_data_map = map;
2554	sc->txq.data[prod].m = m;
2555
2556	bus_dmamap_sync(sc->txq.tx_data_tag, map, BUS_DMASYNC_PREWRITE);
2557
2558	return (0);
2559}
2560
2561
2562static void
2563nfe_setmulti(struct nfe_softc *sc)
2564{
2565	if_t ifp = sc->nfe_ifp;
2566	int i, mc_count, mcnt;
2567	uint32_t filter;
2568	uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN];
2569	uint8_t etherbroadcastaddr[ETHER_ADDR_LEN] = {
2570		0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2571	};
2572	uint8_t *mta;
2573
2574	NFE_LOCK_ASSERT(sc);
2575
2576	if ((if_getflags(ifp) & (IFF_ALLMULTI | IFF_PROMISC)) != 0) {
2577		bzero(addr, ETHER_ADDR_LEN);
2578		bzero(mask, ETHER_ADDR_LEN);
2579		goto done;
2580	}
2581
2582	bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN);
2583	bcopy(etherbroadcastaddr, mask, ETHER_ADDR_LEN);
2584
2585	if_maddr_rlock(ifp);
2586	mc_count = if_multiaddr_count(ifp, -1);
2587	mta = malloc(sizeof(uint8_t) * ETHER_ADDR_LEN * mc_count, M_DEVBUF,
2588	    M_NOWAIT);
2589
2590	/* Unable to get memory - process without filtering */
2591	if (mta == NULL) {
2592		device_printf(sc->nfe_dev, "nfe_setmulti: failed to allocate"
2593		    "temp multicast buffer!\n");
2594
2595		bzero(addr, ETHER_ADDR_LEN);
2596		bzero(mask, ETHER_ADDR_LEN);
2597		free(mta, M_DEVBUF);
2598		if_maddr_runlock(ifp);
2599		goto done;
2600	};
2601
2602	if_setupmultiaddr(ifp, mta, &mcnt, mc_count);
2603
2604	for (i = 0; i < mcnt; i++) {
2605		uint8_t *addrp;
2606
2607		addrp = mta + (i * ETHER_ADDR_LEN);
2608		for (i = 0; i < ETHER_ADDR_LEN; i++) {
2609			u_int8_t mcaddr = addrp[i];
2610			addr[i] &= mcaddr;
2611			mask[i] &= ~mcaddr;
2612		}
2613	}
2614	if_maddr_runlock(ifp);
2615
2616	for (i = 0; i < ETHER_ADDR_LEN; i++) {
2617		mask[i] |= addr[i];
2618	}
2619
2620done:
2621	addr[0] |= 0x01;	/* make sure multicast bit is set */
2622
2623	NFE_WRITE(sc, NFE_MULTIADDR_HI,
2624	    addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]);
2625	NFE_WRITE(sc, NFE_MULTIADDR_LO,
2626	    addr[5] <<  8 | addr[4]);
2627	NFE_WRITE(sc, NFE_MULTIMASK_HI,
2628	    mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]);
2629	NFE_WRITE(sc, NFE_MULTIMASK_LO,
2630	    mask[5] <<  8 | mask[4]);
2631
2632	filter = NFE_READ(sc, NFE_RXFILTER);
2633	filter &= NFE_PFF_RX_PAUSE;
2634	filter |= NFE_RXFILTER_MAGIC;
2635	filter |= (if_getflags(ifp) & IFF_PROMISC) ? NFE_PFF_PROMISC : NFE_PFF_U2M;
2636	NFE_WRITE(sc, NFE_RXFILTER, filter);
2637}
2638
2639
2640static void
2641nfe_start(if_t ifp)
2642{
2643	struct nfe_softc *sc = if_getsoftc(ifp);
2644
2645	NFE_LOCK(sc);
2646	nfe_start_locked(ifp);
2647	NFE_UNLOCK(sc);
2648}
2649
2650static void
2651nfe_start_locked(if_t ifp)
2652{
2653	struct nfe_softc *sc = if_getsoftc(ifp);
2654	struct mbuf *m0;
2655	int enq = 0;
2656
2657	NFE_LOCK_ASSERT(sc);
2658
2659	if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
2660	    IFF_DRV_RUNNING || sc->nfe_link == 0)
2661		return;
2662
2663	while (!if_sendq_empty(ifp)) {
2664		m0 = if_dequeue(ifp);
2665
2666		if (m0 == NULL)
2667			break;
2668
2669		if (nfe_encap(sc, &m0) != 0) {
2670			if (m0 == NULL)
2671				break;
2672			if_sendq_prepend(ifp, m0);
2673			if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
2674			break;
2675		}
2676		enq++;
2677		if_etherbpfmtap(ifp, m0);
2678	}
2679
2680	if (enq > 0) {
2681		bus_dmamap_sync(sc->txq.tx_desc_tag, sc->txq.tx_desc_map,
2682		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2683
2684		/* kick Tx */
2685		NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl);
2686
2687		/*
2688		 * Set a timeout in case the chip goes out to lunch.
2689		 */
2690		sc->nfe_watchdog_timer = 5;
2691	}
2692}
2693
2694
2695static void
2696nfe_watchdog(if_t ifp)
2697{
2698	struct nfe_softc *sc = if_getsoftc(ifp);
2699
2700	if (sc->nfe_watchdog_timer == 0 || --sc->nfe_watchdog_timer)
2701		return;
2702
2703	/* Check if we've lost Tx completion interrupt. */
2704	nfe_txeof(sc);
2705	if (sc->txq.queued == 0) {
2706		if_printf(ifp, "watchdog timeout (missed Tx interrupts) "
2707		    "-- recovering\n");
2708		if (!if_sendq_empty(ifp))
2709			nfe_start_locked(ifp);
2710		return;
2711	}
2712	/* Check if we've lost start Tx command. */
2713	sc->nfe_force_tx++;
2714	if (sc->nfe_force_tx <= 3) {
2715		/*
2716		 * If this is the case for watchdog timeout, the following
2717		 * code should go to nfe_txeof().
2718		 */
2719		NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl);
2720		return;
2721	}
2722	sc->nfe_force_tx = 0;
2723
2724	if_printf(ifp, "watchdog timeout\n");
2725
2726	if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2727	if_incoerrors(ifp, 1);
2728	nfe_init_locked(sc);
2729}
2730
2731
2732static void
2733nfe_init(void *xsc)
2734{
2735	struct nfe_softc *sc = xsc;
2736
2737	NFE_LOCK(sc);
2738	nfe_init_locked(sc);
2739	NFE_UNLOCK(sc);
2740}
2741
2742
2743static void
2744nfe_init_locked(void *xsc)
2745{
2746	struct nfe_softc *sc = xsc;
2747	if_t ifp = sc->nfe_ifp;
2748	struct mii_data *mii;
2749	uint32_t val;
2750	int error;
2751
2752	NFE_LOCK_ASSERT(sc);
2753
2754	mii = device_get_softc(sc->nfe_miibus);
2755
2756	if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
2757		return;
2758
2759	nfe_stop(ifp);
2760
2761	sc->nfe_framesize = if_getmtu(ifp) + NFE_RX_HEADERS;
2762
2763	nfe_init_tx_ring(sc, &sc->txq);
2764	if (sc->nfe_framesize > (MCLBYTES - ETHER_HDR_LEN))
2765		error = nfe_init_jrx_ring(sc, &sc->jrxq);
2766	else
2767		error = nfe_init_rx_ring(sc, &sc->rxq);
2768	if (error != 0) {
2769		device_printf(sc->nfe_dev,
2770		    "initialization failed: no memory for rx buffers\n");
2771		nfe_stop(ifp);
2772		return;
2773	}
2774
2775	val = 0;
2776	if ((sc->nfe_flags & NFE_CORRECT_MACADDR) != 0)
2777		val |= NFE_MAC_ADDR_INORDER;
2778	NFE_WRITE(sc, NFE_TX_UNK, val);
2779	NFE_WRITE(sc, NFE_STATUS, 0);
2780
2781	if ((sc->nfe_flags & NFE_TX_FLOW_CTRL) != 0)
2782		NFE_WRITE(sc, NFE_TX_PAUSE_FRAME, NFE_TX_PAUSE_FRAME_DISABLE);
2783
2784	sc->rxtxctl = NFE_RXTX_BIT2;
2785	if (sc->nfe_flags & NFE_40BIT_ADDR)
2786		sc->rxtxctl |= NFE_RXTX_V3MAGIC;
2787	else if (sc->nfe_flags & NFE_JUMBO_SUP)
2788		sc->rxtxctl |= NFE_RXTX_V2MAGIC;
2789
2790	if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0)
2791		sc->rxtxctl |= NFE_RXTX_RXCSUM;
2792	if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0)
2793		sc->rxtxctl |= NFE_RXTX_VTAG_INSERT | NFE_RXTX_VTAG_STRIP;
2794
2795	NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl);
2796	DELAY(10);
2797	NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl);
2798
2799	if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0)
2800		NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE);
2801	else
2802		NFE_WRITE(sc, NFE_VTAG_CTL, 0);
2803
2804	NFE_WRITE(sc, NFE_SETUP_R6, 0);
2805
2806	/* set MAC address */
2807	nfe_set_macaddr(sc, if_getlladdr(ifp));
2808
2809	/* tell MAC where rings are in memory */
2810	if (sc->nfe_framesize > MCLBYTES - ETHER_HDR_LEN) {
2811		NFE_WRITE(sc, NFE_RX_RING_ADDR_HI,
2812		    NFE_ADDR_HI(sc->jrxq.jphysaddr));
2813		NFE_WRITE(sc, NFE_RX_RING_ADDR_LO,
2814		    NFE_ADDR_LO(sc->jrxq.jphysaddr));
2815	} else {
2816		NFE_WRITE(sc, NFE_RX_RING_ADDR_HI,
2817		    NFE_ADDR_HI(sc->rxq.physaddr));
2818		NFE_WRITE(sc, NFE_RX_RING_ADDR_LO,
2819		    NFE_ADDR_LO(sc->rxq.physaddr));
2820	}
2821	NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, NFE_ADDR_HI(sc->txq.physaddr));
2822	NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, NFE_ADDR_LO(sc->txq.physaddr));
2823
2824	NFE_WRITE(sc, NFE_RING_SIZE,
2825	    (NFE_RX_RING_COUNT - 1) << 16 |
2826	    (NFE_TX_RING_COUNT - 1));
2827
2828	NFE_WRITE(sc, NFE_RXBUFSZ, sc->nfe_framesize);
2829
2830	/* force MAC to wakeup */
2831	val = NFE_READ(sc, NFE_PWR_STATE);
2832	if ((val & NFE_PWR_WAKEUP) == 0)
2833		NFE_WRITE(sc, NFE_PWR_STATE, val | NFE_PWR_WAKEUP);
2834	DELAY(10);
2835	val = NFE_READ(sc, NFE_PWR_STATE);
2836	NFE_WRITE(sc, NFE_PWR_STATE, val | NFE_PWR_VALID);
2837
2838#if 1
2839	/* configure interrupts coalescing/mitigation */
2840	NFE_WRITE(sc, NFE_IMTIMER, NFE_IM_DEFAULT);
2841#else
2842	/* no interrupt mitigation: one interrupt per packet */
2843	NFE_WRITE(sc, NFE_IMTIMER, 970);
2844#endif
2845
2846	NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC_10_100);
2847	NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC);
2848	NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC);
2849
2850	/* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */
2851	NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC);
2852
2853	NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC);
2854	/* Disable WOL. */
2855	NFE_WRITE(sc, NFE_WOL_CTL, 0);
2856
2857	sc->rxtxctl &= ~NFE_RXTX_BIT2;
2858	NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl);
2859	DELAY(10);
2860	NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl);
2861
2862	/* set Rx filter */
2863	nfe_setmulti(sc);
2864
2865	/* enable Rx */
2866	NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START);
2867
2868	/* enable Tx */
2869	NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START);
2870
2871	NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
2872
2873	/* Clear hardware stats. */
2874	nfe_stats_clear(sc);
2875
2876#ifdef DEVICE_POLLING
2877	if (if_getcapenable(ifp) & IFCAP_POLLING)
2878		nfe_disable_intr(sc);
2879	else
2880#endif
2881	nfe_set_intr(sc);
2882	nfe_enable_intr(sc); /* enable interrupts */
2883
2884	if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
2885	if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
2886
2887	sc->nfe_link = 0;
2888	mii_mediachg(mii);
2889
2890	callout_reset(&sc->nfe_stat_ch, hz, nfe_tick, sc);
2891}
2892
2893
2894static void
2895nfe_stop(if_t ifp)
2896{
2897	struct nfe_softc *sc = if_getsoftc(ifp);
2898	struct nfe_rx_ring *rx_ring;
2899	struct nfe_jrx_ring *jrx_ring;
2900	struct nfe_tx_ring *tx_ring;
2901	struct nfe_rx_data *rdata;
2902	struct nfe_tx_data *tdata;
2903	int i;
2904
2905	NFE_LOCK_ASSERT(sc);
2906
2907	sc->nfe_watchdog_timer = 0;
2908	if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
2909
2910	callout_stop(&sc->nfe_stat_ch);
2911
2912	/* abort Tx */
2913	NFE_WRITE(sc, NFE_TX_CTL, 0);
2914
2915	/* disable Rx */
2916	NFE_WRITE(sc, NFE_RX_CTL, 0);
2917
2918	/* disable interrupts */
2919	nfe_disable_intr(sc);
2920
2921	sc->nfe_link = 0;
2922
2923	/* free Rx and Tx mbufs still in the queues. */
2924	rx_ring = &sc->rxq;
2925	for (i = 0; i < NFE_RX_RING_COUNT; i++) {
2926		rdata = &rx_ring->data[i];
2927		if (rdata->m != NULL) {
2928			bus_dmamap_sync(rx_ring->rx_data_tag,
2929			    rdata->rx_data_map, BUS_DMASYNC_POSTREAD);
2930			bus_dmamap_unload(rx_ring->rx_data_tag,
2931			    rdata->rx_data_map);
2932			m_freem(rdata->m);
2933			rdata->m = NULL;
2934		}
2935	}
2936
2937	if ((sc->nfe_flags & NFE_JUMBO_SUP) != 0) {
2938		jrx_ring = &sc->jrxq;
2939		for (i = 0; i < NFE_JUMBO_RX_RING_COUNT; i++) {
2940			rdata = &jrx_ring->jdata[i];
2941			if (rdata->m != NULL) {
2942				bus_dmamap_sync(jrx_ring->jrx_data_tag,
2943				    rdata->rx_data_map, BUS_DMASYNC_POSTREAD);
2944				bus_dmamap_unload(jrx_ring->jrx_data_tag,
2945				    rdata->rx_data_map);
2946				m_freem(rdata->m);
2947				rdata->m = NULL;
2948			}
2949		}
2950	}
2951
2952	tx_ring = &sc->txq;
2953	for (i = 0; i < NFE_RX_RING_COUNT; i++) {
2954		tdata = &tx_ring->data[i];
2955		if (tdata->m != NULL) {
2956			bus_dmamap_sync(tx_ring->tx_data_tag,
2957			    tdata->tx_data_map, BUS_DMASYNC_POSTWRITE);
2958			bus_dmamap_unload(tx_ring->tx_data_tag,
2959			    tdata->tx_data_map);
2960			m_freem(tdata->m);
2961			tdata->m = NULL;
2962		}
2963	}
2964	/* Update hardware stats. */
2965	nfe_stats_update(sc);
2966}
2967
2968
2969static int
2970nfe_ifmedia_upd(if_t ifp)
2971{
2972	struct nfe_softc *sc = if_getsoftc(ifp);
2973	struct mii_data *mii;
2974
2975	NFE_LOCK(sc);
2976	mii = device_get_softc(sc->nfe_miibus);
2977	mii_mediachg(mii);
2978	NFE_UNLOCK(sc);
2979
2980	return (0);
2981}
2982
2983
2984static void
2985nfe_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
2986{
2987	struct nfe_softc *sc;
2988	struct mii_data *mii;
2989
2990	sc = if_getsoftc(ifp);
2991
2992	NFE_LOCK(sc);
2993	mii = device_get_softc(sc->nfe_miibus);
2994	mii_pollstat(mii);
2995
2996	ifmr->ifm_active = mii->mii_media_active;
2997	ifmr->ifm_status = mii->mii_media_status;
2998	NFE_UNLOCK(sc);
2999}
3000
3001
3002void
3003nfe_tick(void *xsc)
3004{
3005	struct nfe_softc *sc;
3006	struct mii_data *mii;
3007	if_t ifp;
3008
3009	sc = (struct nfe_softc *)xsc;
3010
3011	NFE_LOCK_ASSERT(sc);
3012
3013	ifp = sc->nfe_ifp;
3014
3015	mii = device_get_softc(sc->nfe_miibus);
3016	mii_tick(mii);
3017	nfe_stats_update(sc);
3018	nfe_watchdog(ifp);
3019	callout_reset(&sc->nfe_stat_ch, hz, nfe_tick, sc);
3020}
3021
3022
3023static int
3024nfe_shutdown(device_t dev)
3025{
3026
3027	return (nfe_suspend(dev));
3028}
3029
3030
3031static void
3032nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr)
3033{
3034	uint32_t val;
3035
3036	if ((sc->nfe_flags & NFE_CORRECT_MACADDR) == 0) {
3037		val = NFE_READ(sc, NFE_MACADDR_LO);
3038		addr[0] = (val >> 8) & 0xff;
3039		addr[1] = (val & 0xff);
3040
3041		val = NFE_READ(sc, NFE_MACADDR_HI);
3042		addr[2] = (val >> 24) & 0xff;
3043		addr[3] = (val >> 16) & 0xff;
3044		addr[4] = (val >>  8) & 0xff;
3045		addr[5] = (val & 0xff);
3046	} else {
3047		val = NFE_READ(sc, NFE_MACADDR_LO);
3048		addr[5] = (val >> 8) & 0xff;
3049		addr[4] = (val & 0xff);
3050
3051		val = NFE_READ(sc, NFE_MACADDR_HI);
3052		addr[3] = (val >> 24) & 0xff;
3053		addr[2] = (val >> 16) & 0xff;
3054		addr[1] = (val >>  8) & 0xff;
3055		addr[0] = (val & 0xff);
3056	}
3057}
3058
3059
3060static void
3061nfe_set_macaddr(struct nfe_softc *sc, uint8_t *addr)
3062{
3063
3064	NFE_WRITE(sc, NFE_MACADDR_LO, addr[5] <<  8 | addr[4]);
3065	NFE_WRITE(sc, NFE_MACADDR_HI, addr[3] << 24 | addr[2] << 16 |
3066	    addr[1] << 8 | addr[0]);
3067}
3068
3069
3070/*
3071 * Map a single buffer address.
3072 */
3073
3074static void
3075nfe_dma_map_segs(void *arg, bus_dma_segment_t *segs, int nseg, int error)
3076{
3077	struct nfe_dmamap_arg *ctx;
3078
3079	if (error != 0)
3080		return;
3081
3082	KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
3083
3084	ctx = (struct nfe_dmamap_arg *)arg;
3085	ctx->nfe_busaddr = segs[0].ds_addr;
3086}
3087
3088
3089static int
3090sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3091{
3092	int error, value;
3093
3094	if (!arg1)
3095		return (EINVAL);
3096	value = *(int *)arg1;
3097	error = sysctl_handle_int(oidp, &value, 0, req);
3098	if (error || !req->newptr)
3099		return (error);
3100	if (value < low || value > high)
3101		return (EINVAL);
3102	*(int *)arg1 = value;
3103
3104	return (0);
3105}
3106
3107
3108static int
3109sysctl_hw_nfe_proc_limit(SYSCTL_HANDLER_ARGS)
3110{
3111
3112	return (sysctl_int_range(oidp, arg1, arg2, req, NFE_PROC_MIN,
3113	    NFE_PROC_MAX));
3114}
3115
3116
3117#define	NFE_SYSCTL_STAT_ADD32(c, h, n, p, d)	\
3118	    SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
3119#define	NFE_SYSCTL_STAT_ADD64(c, h, n, p, d)	\
3120	    SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
3121
3122static void
3123nfe_sysctl_node(struct nfe_softc *sc)
3124{
3125	struct sysctl_ctx_list *ctx;
3126	struct sysctl_oid_list *child, *parent;
3127	struct sysctl_oid *tree;
3128	struct nfe_hw_stats *stats;
3129	int error;
3130
3131	stats = &sc->nfe_stats;
3132	ctx = device_get_sysctl_ctx(sc->nfe_dev);
3133	child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->nfe_dev));
3134	SYSCTL_ADD_PROC(ctx, child,
3135	    OID_AUTO, "process_limit", CTLTYPE_INT | CTLFLAG_RW,
3136	    &sc->nfe_process_limit, 0, sysctl_hw_nfe_proc_limit, "I",
3137	    "max number of Rx events to process");
3138
3139	sc->nfe_process_limit = NFE_PROC_DEFAULT;
3140	error = resource_int_value(device_get_name(sc->nfe_dev),
3141	    device_get_unit(sc->nfe_dev), "process_limit",
3142	    &sc->nfe_process_limit);
3143	if (error == 0) {
3144		if (sc->nfe_process_limit < NFE_PROC_MIN ||
3145		    sc->nfe_process_limit > NFE_PROC_MAX) {
3146			device_printf(sc->nfe_dev,
3147			    "process_limit value out of range; "
3148			    "using default: %d\n", NFE_PROC_DEFAULT);
3149			sc->nfe_process_limit = NFE_PROC_DEFAULT;
3150		}
3151	}
3152
3153	if ((sc->nfe_flags & (NFE_MIB_V1 | NFE_MIB_V2 | NFE_MIB_V3)) == 0)
3154		return;
3155
3156	tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD,
3157	    NULL, "NFE statistics");
3158	parent = SYSCTL_CHILDREN(tree);
3159
3160	/* Rx statistics. */
3161	tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD,
3162	    NULL, "Rx MAC statistics");
3163	child = SYSCTL_CHILDREN(tree);
3164
3165	NFE_SYSCTL_STAT_ADD32(ctx, child, "frame_errors",
3166	    &stats->rx_frame_errors, "Framing Errors");
3167	NFE_SYSCTL_STAT_ADD32(ctx, child, "extra_bytes",
3168	    &stats->rx_extra_bytes, "Extra Bytes");
3169	NFE_SYSCTL_STAT_ADD32(ctx, child, "late_cols",
3170	    &stats->rx_late_cols, "Late Collisions");
3171	NFE_SYSCTL_STAT_ADD32(ctx, child, "runts",
3172	    &stats->rx_runts, "Runts");
3173	NFE_SYSCTL_STAT_ADD32(ctx, child, "jumbos",
3174	    &stats->rx_jumbos, "Jumbos");
3175	NFE_SYSCTL_STAT_ADD32(ctx, child, "fifo_overuns",
3176	    &stats->rx_fifo_overuns, "FIFO Overruns");
3177	NFE_SYSCTL_STAT_ADD32(ctx, child, "crc_errors",
3178	    &stats->rx_crc_errors, "CRC Errors");
3179	NFE_SYSCTL_STAT_ADD32(ctx, child, "fae",
3180	    &stats->rx_fae, "Frame Alignment Errors");
3181	NFE_SYSCTL_STAT_ADD32(ctx, child, "len_errors",
3182	    &stats->rx_len_errors, "Length Errors");
3183	NFE_SYSCTL_STAT_ADD32(ctx, child, "unicast",
3184	    &stats->rx_unicast, "Unicast Frames");
3185	NFE_SYSCTL_STAT_ADD32(ctx, child, "multicast",
3186	    &stats->rx_multicast, "Multicast Frames");
3187	NFE_SYSCTL_STAT_ADD32(ctx, child, "broadcast",
3188	    &stats->rx_broadcast, "Broadcast Frames");
3189	if ((sc->nfe_flags & NFE_MIB_V2) != 0) {
3190		NFE_SYSCTL_STAT_ADD64(ctx, child, "octets",
3191		    &stats->rx_octets, "Octets");
3192		NFE_SYSCTL_STAT_ADD32(ctx, child, "pause",
3193		    &stats->rx_pause, "Pause frames");
3194		NFE_SYSCTL_STAT_ADD32(ctx, child, "drops",
3195		    &stats->rx_drops, "Drop frames");
3196	}
3197
3198	/* Tx statistics. */
3199	tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD,
3200	    NULL, "Tx MAC statistics");
3201	child = SYSCTL_CHILDREN(tree);
3202	NFE_SYSCTL_STAT_ADD64(ctx, child, "octets",
3203	    &stats->tx_octets, "Octets");
3204	NFE_SYSCTL_STAT_ADD32(ctx, child, "zero_rexmits",
3205	    &stats->tx_zero_rexmits, "Zero Retransmits");
3206	NFE_SYSCTL_STAT_ADD32(ctx, child, "one_rexmits",
3207	    &stats->tx_one_rexmits, "One Retransmits");
3208	NFE_SYSCTL_STAT_ADD32(ctx, child, "multi_rexmits",
3209	    &stats->tx_multi_rexmits, "Multiple Retransmits");
3210	NFE_SYSCTL_STAT_ADD32(ctx, child, "late_cols",
3211	    &stats->tx_late_cols, "Late Collisions");
3212	NFE_SYSCTL_STAT_ADD32(ctx, child, "fifo_underuns",
3213	    &stats->tx_fifo_underuns, "FIFO Underruns");
3214	NFE_SYSCTL_STAT_ADD32(ctx, child, "carrier_losts",
3215	    &stats->tx_carrier_losts, "Carrier Losts");
3216	NFE_SYSCTL_STAT_ADD32(ctx, child, "excess_deferrals",
3217	    &stats->tx_excess_deferals, "Excess Deferrals");
3218	NFE_SYSCTL_STAT_ADD32(ctx, child, "retry_errors",
3219	    &stats->tx_retry_errors, "Retry Errors");
3220	if ((sc->nfe_flags & NFE_MIB_V2) != 0) {
3221		NFE_SYSCTL_STAT_ADD32(ctx, child, "deferrals",
3222		    &stats->tx_deferals, "Deferrals");
3223		NFE_SYSCTL_STAT_ADD32(ctx, child, "frames",
3224		    &stats->tx_frames, "Frames");
3225		NFE_SYSCTL_STAT_ADD32(ctx, child, "pause",
3226		    &stats->tx_pause, "Pause Frames");
3227	}
3228	if ((sc->nfe_flags & NFE_MIB_V3) != 0) {
3229		NFE_SYSCTL_STAT_ADD32(ctx, child, "unicast",
3230		    &stats->tx_deferals, "Unicast Frames");
3231		NFE_SYSCTL_STAT_ADD32(ctx, child, "multicast",
3232		    &stats->tx_frames, "Multicast Frames");
3233		NFE_SYSCTL_STAT_ADD32(ctx, child, "broadcast",
3234		    &stats->tx_pause, "Broadcast Frames");
3235	}
3236}
3237
3238#undef NFE_SYSCTL_STAT_ADD32
3239#undef NFE_SYSCTL_STAT_ADD64
3240
3241static void
3242nfe_stats_clear(struct nfe_softc *sc)
3243{
3244	int i, mib_cnt;
3245
3246	if ((sc->nfe_flags & NFE_MIB_V1) != 0)
3247		mib_cnt = NFE_NUM_MIB_STATV1;
3248	else if ((sc->nfe_flags & (NFE_MIB_V2 | NFE_MIB_V3)) != 0)
3249		mib_cnt = NFE_NUM_MIB_STATV2;
3250	else
3251		return;
3252
3253	for (i = 0; i < mib_cnt; i++)
3254		NFE_READ(sc, NFE_TX_OCTET + i * sizeof(uint32_t));
3255
3256	if ((sc->nfe_flags & NFE_MIB_V3) != 0) {
3257		NFE_READ(sc, NFE_TX_UNICAST);
3258		NFE_READ(sc, NFE_TX_MULTICAST);
3259		NFE_READ(sc, NFE_TX_BROADCAST);
3260	}
3261}
3262
3263static void
3264nfe_stats_update(struct nfe_softc *sc)
3265{
3266	struct nfe_hw_stats *stats;
3267
3268	NFE_LOCK_ASSERT(sc);
3269
3270	if ((sc->nfe_flags & (NFE_MIB_V1 | NFE_MIB_V2 | NFE_MIB_V3)) == 0)
3271		return;
3272
3273	stats = &sc->nfe_stats;
3274	stats->tx_octets += NFE_READ(sc, NFE_TX_OCTET);
3275	stats->tx_zero_rexmits += NFE_READ(sc, NFE_TX_ZERO_REXMIT);
3276	stats->tx_one_rexmits += NFE_READ(sc, NFE_TX_ONE_REXMIT);
3277	stats->tx_multi_rexmits += NFE_READ(sc, NFE_TX_MULTI_REXMIT);
3278	stats->tx_late_cols += NFE_READ(sc, NFE_TX_LATE_COL);
3279	stats->tx_fifo_underuns += NFE_READ(sc, NFE_TX_FIFO_UNDERUN);
3280	stats->tx_carrier_losts += NFE_READ(sc, NFE_TX_CARRIER_LOST);
3281	stats->tx_excess_deferals += NFE_READ(sc, NFE_TX_EXCESS_DEFERRAL);
3282	stats->tx_retry_errors += NFE_READ(sc, NFE_TX_RETRY_ERROR);
3283	stats->rx_frame_errors += NFE_READ(sc, NFE_RX_FRAME_ERROR);
3284	stats->rx_extra_bytes += NFE_READ(sc, NFE_RX_EXTRA_BYTES);
3285	stats->rx_late_cols += NFE_READ(sc, NFE_RX_LATE_COL);
3286	stats->rx_runts += NFE_READ(sc, NFE_RX_RUNT);
3287	stats->rx_jumbos += NFE_READ(sc, NFE_RX_JUMBO);
3288	stats->rx_fifo_overuns += NFE_READ(sc, NFE_RX_FIFO_OVERUN);
3289	stats->rx_crc_errors += NFE_READ(sc, NFE_RX_CRC_ERROR);
3290	stats->rx_fae += NFE_READ(sc, NFE_RX_FAE);
3291	stats->rx_len_errors += NFE_READ(sc, NFE_RX_LEN_ERROR);
3292	stats->rx_unicast += NFE_READ(sc, NFE_RX_UNICAST);
3293	stats->rx_multicast += NFE_READ(sc, NFE_RX_MULTICAST);
3294	stats->rx_broadcast += NFE_READ(sc, NFE_RX_BROADCAST);
3295
3296	if ((sc->nfe_flags & NFE_MIB_V2) != 0) {
3297		stats->tx_deferals += NFE_READ(sc, NFE_TX_DEFERAL);
3298		stats->tx_frames += NFE_READ(sc, NFE_TX_FRAME);
3299		stats->rx_octets += NFE_READ(sc, NFE_RX_OCTET);
3300		stats->tx_pause += NFE_READ(sc, NFE_TX_PAUSE);
3301		stats->rx_pause += NFE_READ(sc, NFE_RX_PAUSE);
3302		stats->rx_drops += NFE_READ(sc, NFE_RX_DROP);
3303	}
3304
3305	if ((sc->nfe_flags & NFE_MIB_V3) != 0) {
3306		stats->tx_unicast += NFE_READ(sc, NFE_TX_UNICAST);
3307		stats->tx_multicast += NFE_READ(sc, NFE_TX_MULTICAST);
3308		stats->tx_broadcast += NFE_READ(sc, NFE_TX_BROADCAST);
3309	}
3310}
3311
3312
3313static void
3314nfe_set_linkspeed(struct nfe_softc *sc)
3315{
3316	struct mii_softc *miisc;
3317	struct mii_data *mii;
3318	int aneg, i, phyno;
3319
3320	NFE_LOCK_ASSERT(sc);
3321
3322	mii = device_get_softc(sc->nfe_miibus);
3323	mii_pollstat(mii);
3324	aneg = 0;
3325	if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
3326	    (IFM_ACTIVE | IFM_AVALID)) {
3327		switch IFM_SUBTYPE(mii->mii_media_active) {
3328		case IFM_10_T:
3329		case IFM_100_TX:
3330			return;
3331		case IFM_1000_T:
3332			aneg++;
3333			break;
3334		default:
3335			break;
3336		}
3337	}
3338	miisc = LIST_FIRST(&mii->mii_phys);
3339	phyno = miisc->mii_phy;
3340	LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3341		PHY_RESET(miisc);
3342	nfe_miibus_writereg(sc->nfe_dev, phyno, MII_100T2CR, 0);
3343	nfe_miibus_writereg(sc->nfe_dev, phyno,
3344	    MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
3345	nfe_miibus_writereg(sc->nfe_dev, phyno,
3346	    MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
3347	DELAY(1000);
3348	if (aneg != 0) {
3349		/*
3350		 * Poll link state until nfe(4) get a 10/100Mbps link.
3351		 */
3352		for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
3353			mii_pollstat(mii);
3354			if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID))
3355			    == (IFM_ACTIVE | IFM_AVALID)) {
3356				switch (IFM_SUBTYPE(mii->mii_media_active)) {
3357				case IFM_10_T:
3358				case IFM_100_TX:
3359					nfe_mac_config(sc, mii);
3360					return;
3361				default:
3362					break;
3363				}
3364			}
3365			NFE_UNLOCK(sc);
3366			pause("nfelnk", hz);
3367			NFE_LOCK(sc);
3368		}
3369		if (i == MII_ANEGTICKS_GIGE)
3370			device_printf(sc->nfe_dev,
3371			    "establishing a link failed, WOL may not work!");
3372	}
3373	/*
3374	 * No link, force MAC to have 100Mbps, full-duplex link.
3375	 * This is the last resort and may/may not work.
3376	 */
3377	mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
3378	mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
3379	nfe_mac_config(sc, mii);
3380}
3381
3382
3383static void
3384nfe_set_wol(struct nfe_softc *sc)
3385{
3386	if_t ifp;
3387	uint32_t wolctl;
3388	int pmc;
3389	uint16_t pmstat;
3390
3391	NFE_LOCK_ASSERT(sc);
3392
3393	if (pci_find_cap(sc->nfe_dev, PCIY_PMG, &pmc) != 0)
3394		return;
3395	ifp = sc->nfe_ifp;
3396	if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0)
3397		wolctl = NFE_WOL_MAGIC;
3398	else
3399		wolctl = 0;
3400	NFE_WRITE(sc, NFE_WOL_CTL, wolctl);
3401	if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) {
3402		nfe_set_linkspeed(sc);
3403		if ((sc->nfe_flags & NFE_PWR_MGMT) != 0)
3404			NFE_WRITE(sc, NFE_PWR2_CTL,
3405			    NFE_READ(sc, NFE_PWR2_CTL) & ~NFE_PWR2_GATE_CLOCKS);
3406		/* Enable RX. */
3407		NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, 0);
3408		NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, 0);
3409		NFE_WRITE(sc, NFE_RX_CTL, NFE_READ(sc, NFE_RX_CTL) |
3410		    NFE_RX_START);
3411	}
3412	/* Request PME if WOL is requested. */
3413	pmstat = pci_read_config(sc->nfe_dev, pmc + PCIR_POWER_STATUS, 2);
3414	pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
3415	if ((if_getcapenable(ifp) & IFCAP_WOL) != 0)
3416		pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3417	pci_write_config(sc->nfe_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
3418}
3419