if_nfe.c revision 266270
1/* $OpenBSD: if_nfe.c,v 1.54 2006/04/07 12:38:12 jsg Exp $ */ 2 3/*- 4 * Copyright (c) 2006 Shigeaki Tagashira <shigeaki@se.hiroshima-u.ac.jp> 5 * Copyright (c) 2006 Damien Bergamini <damien.bergamini@free.fr> 6 * Copyright (c) 2005, 2006 Jonathan Gray <jsg@openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21/* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */ 22 23#include <sys/cdefs.h> 24__FBSDID("$FreeBSD: head/sys/dev/nfe/if_nfe.c 266270 2014-05-16 21:19:17Z brueffer $"); 25 26#ifdef HAVE_KERNEL_OPTION_HEADERS 27#include "opt_device_polling.h" 28#endif 29 30#include <sys/param.h> 31#include <sys/endian.h> 32#include <sys/systm.h> 33#include <sys/sockio.h> 34#include <sys/mbuf.h> 35#include <sys/malloc.h> 36#include <sys/module.h> 37#include <sys/kernel.h> 38#include <sys/queue.h> 39#include <sys/socket.h> 40#include <sys/sysctl.h> 41#include <sys/taskqueue.h> 42 43#include <net/if.h> 44#include <net/if_var.h> 45#include <net/if_arp.h> 46#include <net/ethernet.h> 47#include <net/if_dl.h> 48#include <net/if_media.h> 49#include <net/if_types.h> 50#include <net/if_vlan_var.h> 51 52#include <net/bpf.h> 53 54#include <machine/bus.h> 55#include <machine/resource.h> 56#include <sys/bus.h> 57#include <sys/rman.h> 58 59#include <dev/mii/mii.h> 60#include <dev/mii/miivar.h> 61 62#include <dev/pci/pcireg.h> 63#include <dev/pci/pcivar.h> 64 65#include <dev/nfe/if_nfereg.h> 66#include <dev/nfe/if_nfevar.h> 67 68MODULE_DEPEND(nfe, pci, 1, 1, 1); 69MODULE_DEPEND(nfe, ether, 1, 1, 1); 70MODULE_DEPEND(nfe, miibus, 1, 1, 1); 71 72/* "device miibus" required. See GENERIC if you get errors here. */ 73#include "miibus_if.h" 74 75static int nfe_probe(device_t); 76static int nfe_attach(device_t); 77static int nfe_detach(device_t); 78static int nfe_suspend(device_t); 79static int nfe_resume(device_t); 80static int nfe_shutdown(device_t); 81static int nfe_can_use_msix(struct nfe_softc *); 82static int nfe_detect_msik9(struct nfe_softc *); 83static void nfe_power(struct nfe_softc *); 84static int nfe_miibus_readreg(device_t, int, int); 85static int nfe_miibus_writereg(device_t, int, int, int); 86static void nfe_miibus_statchg(device_t); 87static void nfe_mac_config(struct nfe_softc *, struct mii_data *); 88static void nfe_set_intr(struct nfe_softc *); 89static __inline void nfe_enable_intr(struct nfe_softc *); 90static __inline void nfe_disable_intr(struct nfe_softc *); 91static int nfe_ioctl(struct ifnet *, u_long, caddr_t); 92static void nfe_alloc_msix(struct nfe_softc *, int); 93static int nfe_intr(void *); 94static void nfe_int_task(void *, int); 95static __inline void nfe_discard_rxbuf(struct nfe_softc *, int); 96static __inline void nfe_discard_jrxbuf(struct nfe_softc *, int); 97static int nfe_newbuf(struct nfe_softc *, int); 98static int nfe_jnewbuf(struct nfe_softc *, int); 99static int nfe_rxeof(struct nfe_softc *, int, int *); 100static int nfe_jrxeof(struct nfe_softc *, int, int *); 101static void nfe_txeof(struct nfe_softc *); 102static int nfe_encap(struct nfe_softc *, struct mbuf **); 103static void nfe_setmulti(struct nfe_softc *); 104static void nfe_start(struct ifnet *); 105static void nfe_start_locked(struct ifnet *); 106static void nfe_watchdog(struct ifnet *); 107static void nfe_init(void *); 108static void nfe_init_locked(void *); 109static void nfe_stop(struct ifnet *); 110static int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 111static void nfe_alloc_jrx_ring(struct nfe_softc *, struct nfe_jrx_ring *); 112static int nfe_init_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 113static int nfe_init_jrx_ring(struct nfe_softc *, struct nfe_jrx_ring *); 114static void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 115static void nfe_free_jrx_ring(struct nfe_softc *, struct nfe_jrx_ring *); 116static int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 117static void nfe_init_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 118static void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 119static int nfe_ifmedia_upd(struct ifnet *); 120static void nfe_ifmedia_sts(struct ifnet *, struct ifmediareq *); 121static void nfe_tick(void *); 122static void nfe_get_macaddr(struct nfe_softc *, uint8_t *); 123static void nfe_set_macaddr(struct nfe_softc *, uint8_t *); 124static void nfe_dma_map_segs(void *, bus_dma_segment_t *, int, int); 125 126static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 127static int sysctl_hw_nfe_proc_limit(SYSCTL_HANDLER_ARGS); 128static void nfe_sysctl_node(struct nfe_softc *); 129static void nfe_stats_clear(struct nfe_softc *); 130static void nfe_stats_update(struct nfe_softc *); 131static void nfe_set_linkspeed(struct nfe_softc *); 132static void nfe_set_wol(struct nfe_softc *); 133 134#ifdef NFE_DEBUG 135static int nfedebug = 0; 136#define DPRINTF(sc, ...) do { \ 137 if (nfedebug) \ 138 device_printf((sc)->nfe_dev, __VA_ARGS__); \ 139} while (0) 140#define DPRINTFN(sc, n, ...) do { \ 141 if (nfedebug >= (n)) \ 142 device_printf((sc)->nfe_dev, __VA_ARGS__); \ 143} while (0) 144#else 145#define DPRINTF(sc, ...) 146#define DPRINTFN(sc, n, ...) 147#endif 148 149#define NFE_LOCK(_sc) mtx_lock(&(_sc)->nfe_mtx) 150#define NFE_UNLOCK(_sc) mtx_unlock(&(_sc)->nfe_mtx) 151#define NFE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->nfe_mtx, MA_OWNED) 152 153/* Tunables. */ 154static int msi_disable = 0; 155static int msix_disable = 0; 156static int jumbo_disable = 0; 157TUNABLE_INT("hw.nfe.msi_disable", &msi_disable); 158TUNABLE_INT("hw.nfe.msix_disable", &msix_disable); 159TUNABLE_INT("hw.nfe.jumbo_disable", &jumbo_disable); 160 161static device_method_t nfe_methods[] = { 162 /* Device interface */ 163 DEVMETHOD(device_probe, nfe_probe), 164 DEVMETHOD(device_attach, nfe_attach), 165 DEVMETHOD(device_detach, nfe_detach), 166 DEVMETHOD(device_suspend, nfe_suspend), 167 DEVMETHOD(device_resume, nfe_resume), 168 DEVMETHOD(device_shutdown, nfe_shutdown), 169 170 /* MII interface */ 171 DEVMETHOD(miibus_readreg, nfe_miibus_readreg), 172 DEVMETHOD(miibus_writereg, nfe_miibus_writereg), 173 DEVMETHOD(miibus_statchg, nfe_miibus_statchg), 174 175 DEVMETHOD_END 176}; 177 178static driver_t nfe_driver = { 179 "nfe", 180 nfe_methods, 181 sizeof(struct nfe_softc) 182}; 183 184static devclass_t nfe_devclass; 185 186DRIVER_MODULE(nfe, pci, nfe_driver, nfe_devclass, 0, 0); 187DRIVER_MODULE(miibus, nfe, miibus_driver, miibus_devclass, 0, 0); 188 189static struct nfe_type nfe_devs[] = { 190 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN, 191 "NVIDIA nForce MCP Networking Adapter"}, 192 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN, 193 "NVIDIA nForce2 MCP2 Networking Adapter"}, 194 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1, 195 "NVIDIA nForce2 400 MCP4 Networking Adapter"}, 196 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2, 197 "NVIDIA nForce2 400 MCP5 Networking Adapter"}, 198 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1, 199 "NVIDIA nForce3 MCP3 Networking Adapter"}, 200 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN, 201 "NVIDIA nForce3 250 MCP6 Networking Adapter"}, 202 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4, 203 "NVIDIA nForce3 MCP7 Networking Adapter"}, 204 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE4_LAN1, 205 "NVIDIA nForce4 CK804 MCP8 Networking Adapter"}, 206 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE4_LAN2, 207 "NVIDIA nForce4 CK804 MCP9 Networking Adapter"}, 208 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1, 209 "NVIDIA nForce MCP04 Networking Adapter"}, /* MCP10 */ 210 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2, 211 "NVIDIA nForce MCP04 Networking Adapter"}, /* MCP11 */ 212 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE430_LAN1, 213 "NVIDIA nForce 430 MCP12 Networking Adapter"}, 214 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE430_LAN2, 215 "NVIDIA nForce 430 MCP13 Networking Adapter"}, 216 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1, 217 "NVIDIA nForce MCP55 Networking Adapter"}, 218 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2, 219 "NVIDIA nForce MCP55 Networking Adapter"}, 220 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1, 221 "NVIDIA nForce MCP61 Networking Adapter"}, 222 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2, 223 "NVIDIA nForce MCP61 Networking Adapter"}, 224 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3, 225 "NVIDIA nForce MCP61 Networking Adapter"}, 226 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4, 227 "NVIDIA nForce MCP61 Networking Adapter"}, 228 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1, 229 "NVIDIA nForce MCP65 Networking Adapter"}, 230 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2, 231 "NVIDIA nForce MCP65 Networking Adapter"}, 232 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3, 233 "NVIDIA nForce MCP65 Networking Adapter"}, 234 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4, 235 "NVIDIA nForce MCP65 Networking Adapter"}, 236 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN1, 237 "NVIDIA nForce MCP67 Networking Adapter"}, 238 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN2, 239 "NVIDIA nForce MCP67 Networking Adapter"}, 240 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN3, 241 "NVIDIA nForce MCP67 Networking Adapter"}, 242 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN4, 243 "NVIDIA nForce MCP67 Networking Adapter"}, 244 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN1, 245 "NVIDIA nForce MCP73 Networking Adapter"}, 246 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN2, 247 "NVIDIA nForce MCP73 Networking Adapter"}, 248 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN3, 249 "NVIDIA nForce MCP73 Networking Adapter"}, 250 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN4, 251 "NVIDIA nForce MCP73 Networking Adapter"}, 252 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN1, 253 "NVIDIA nForce MCP77 Networking Adapter"}, 254 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN2, 255 "NVIDIA nForce MCP77 Networking Adapter"}, 256 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN3, 257 "NVIDIA nForce MCP77 Networking Adapter"}, 258 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN4, 259 "NVIDIA nForce MCP77 Networking Adapter"}, 260 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN1, 261 "NVIDIA nForce MCP79 Networking Adapter"}, 262 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN2, 263 "NVIDIA nForce MCP79 Networking Adapter"}, 264 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN3, 265 "NVIDIA nForce MCP79 Networking Adapter"}, 266 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN4, 267 "NVIDIA nForce MCP79 Networking Adapter"}, 268 {0, 0, NULL} 269}; 270 271 272/* Probe for supported hardware ID's */ 273static int 274nfe_probe(device_t dev) 275{ 276 struct nfe_type *t; 277 278 t = nfe_devs; 279 /* Check for matching PCI DEVICE ID's */ 280 while (t->name != NULL) { 281 if ((pci_get_vendor(dev) == t->vid_id) && 282 (pci_get_device(dev) == t->dev_id)) { 283 device_set_desc(dev, t->name); 284 return (BUS_PROBE_DEFAULT); 285 } 286 t++; 287 } 288 289 return (ENXIO); 290} 291 292static void 293nfe_alloc_msix(struct nfe_softc *sc, int count) 294{ 295 int rid; 296 297 rid = PCIR_BAR(2); 298 sc->nfe_msix_res = bus_alloc_resource_any(sc->nfe_dev, SYS_RES_MEMORY, 299 &rid, RF_ACTIVE); 300 if (sc->nfe_msix_res == NULL) { 301 device_printf(sc->nfe_dev, 302 "couldn't allocate MSIX table resource\n"); 303 return; 304 } 305 rid = PCIR_BAR(3); 306 sc->nfe_msix_pba_res = bus_alloc_resource_any(sc->nfe_dev, 307 SYS_RES_MEMORY, &rid, RF_ACTIVE); 308 if (sc->nfe_msix_pba_res == NULL) { 309 device_printf(sc->nfe_dev, 310 "couldn't allocate MSIX PBA resource\n"); 311 bus_release_resource(sc->nfe_dev, SYS_RES_MEMORY, PCIR_BAR(2), 312 sc->nfe_msix_res); 313 sc->nfe_msix_res = NULL; 314 return; 315 } 316 317 if (pci_alloc_msix(sc->nfe_dev, &count) == 0) { 318 if (count == NFE_MSI_MESSAGES) { 319 if (bootverbose) 320 device_printf(sc->nfe_dev, 321 "Using %d MSIX messages\n", count); 322 sc->nfe_msix = 1; 323 } else { 324 if (bootverbose) 325 device_printf(sc->nfe_dev, 326 "couldn't allocate MSIX\n"); 327 pci_release_msi(sc->nfe_dev); 328 bus_release_resource(sc->nfe_dev, SYS_RES_MEMORY, 329 PCIR_BAR(3), sc->nfe_msix_pba_res); 330 bus_release_resource(sc->nfe_dev, SYS_RES_MEMORY, 331 PCIR_BAR(2), sc->nfe_msix_res); 332 sc->nfe_msix_pba_res = NULL; 333 sc->nfe_msix_res = NULL; 334 } 335 } 336} 337 338 339static int 340nfe_detect_msik9(struct nfe_softc *sc) 341{ 342 static const char *maker = "MSI"; 343 static const char *product = "K9N6PGM2-V2 (MS-7309)"; 344 char *m, *p; 345 int found; 346 347 found = 0; 348 m = getenv("smbios.planar.maker"); 349 p = getenv("smbios.planar.product"); 350 if (m != NULL && p != NULL) { 351 if (strcmp(m, maker) == 0 && strcmp(p, product) == 0) 352 found = 1; 353 } 354 if (m != NULL) 355 freeenv(m); 356 if (p != NULL) 357 freeenv(p); 358 359 return (found); 360} 361 362 363static int 364nfe_attach(device_t dev) 365{ 366 struct nfe_softc *sc; 367 struct ifnet *ifp; 368 bus_addr_t dma_addr_max; 369 int error = 0, i, msic, phyloc, reg, rid; 370 371 sc = device_get_softc(dev); 372 sc->nfe_dev = dev; 373 374 mtx_init(&sc->nfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 375 MTX_DEF); 376 callout_init_mtx(&sc->nfe_stat_ch, &sc->nfe_mtx, 0); 377 378 pci_enable_busmaster(dev); 379 380 rid = PCIR_BAR(0); 381 sc->nfe_res[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 382 RF_ACTIVE); 383 if (sc->nfe_res[0] == NULL) { 384 device_printf(dev, "couldn't map memory resources\n"); 385 mtx_destroy(&sc->nfe_mtx); 386 return (ENXIO); 387 } 388 389 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 390 uint16_t v, width; 391 392 v = pci_read_config(dev, reg + 0x08, 2); 393 /* Change max. read request size to 4096. */ 394 v &= ~(7 << 12); 395 v |= (5 << 12); 396 pci_write_config(dev, reg + 0x08, v, 2); 397 398 v = pci_read_config(dev, reg + 0x0c, 2); 399 /* link capability */ 400 v = (v >> 4) & 0x0f; 401 width = pci_read_config(dev, reg + 0x12, 2); 402 /* negotiated link width */ 403 width = (width >> 4) & 0x3f; 404 if (v != width) 405 device_printf(sc->nfe_dev, 406 "warning, negotiated width of link(x%d) != " 407 "max. width of link(x%d)\n", width, v); 408 } 409 410 if (nfe_can_use_msix(sc) == 0) { 411 device_printf(sc->nfe_dev, 412 "MSI/MSI-X capability black-listed, will use INTx\n"); 413 msix_disable = 1; 414 msi_disable = 1; 415 } 416 417 /* Allocate interrupt */ 418 if (msix_disable == 0 || msi_disable == 0) { 419 if (msix_disable == 0 && 420 (msic = pci_msix_count(dev)) == NFE_MSI_MESSAGES) 421 nfe_alloc_msix(sc, msic); 422 if (msi_disable == 0 && sc->nfe_msix == 0 && 423 (msic = pci_msi_count(dev)) == NFE_MSI_MESSAGES && 424 pci_alloc_msi(dev, &msic) == 0) { 425 if (msic == NFE_MSI_MESSAGES) { 426 if (bootverbose) 427 device_printf(dev, 428 "Using %d MSI messages\n", msic); 429 sc->nfe_msi = 1; 430 } else 431 pci_release_msi(dev); 432 } 433 } 434 435 if (sc->nfe_msix == 0 && sc->nfe_msi == 0) { 436 rid = 0; 437 sc->nfe_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 438 RF_SHAREABLE | RF_ACTIVE); 439 if (sc->nfe_irq[0] == NULL) { 440 device_printf(dev, "couldn't allocate IRQ resources\n"); 441 error = ENXIO; 442 goto fail; 443 } 444 } else { 445 for (i = 0, rid = 1; i < NFE_MSI_MESSAGES; i++, rid++) { 446 sc->nfe_irq[i] = bus_alloc_resource_any(dev, 447 SYS_RES_IRQ, &rid, RF_ACTIVE); 448 if (sc->nfe_irq[i] == NULL) { 449 device_printf(dev, 450 "couldn't allocate IRQ resources for " 451 "message %d\n", rid); 452 error = ENXIO; 453 goto fail; 454 } 455 } 456 /* Map interrupts to vector 0. */ 457 if (sc->nfe_msix != 0) { 458 NFE_WRITE(sc, NFE_MSIX_MAP0, 0); 459 NFE_WRITE(sc, NFE_MSIX_MAP1, 0); 460 } else if (sc->nfe_msi != 0) { 461 NFE_WRITE(sc, NFE_MSI_MAP0, 0); 462 NFE_WRITE(sc, NFE_MSI_MAP1, 0); 463 } 464 } 465 466 /* Set IRQ status/mask register. */ 467 sc->nfe_irq_status = NFE_IRQ_STATUS; 468 sc->nfe_irq_mask = NFE_IRQ_MASK; 469 sc->nfe_intrs = NFE_IRQ_WANTED; 470 sc->nfe_nointrs = 0; 471 if (sc->nfe_msix != 0) { 472 sc->nfe_irq_status = NFE_MSIX_IRQ_STATUS; 473 sc->nfe_nointrs = NFE_IRQ_WANTED; 474 } else if (sc->nfe_msi != 0) { 475 sc->nfe_irq_mask = NFE_MSI_IRQ_MASK; 476 sc->nfe_intrs = NFE_MSI_VECTOR_0_ENABLED; 477 } 478 479 sc->nfe_devid = pci_get_device(dev); 480 sc->nfe_revid = pci_get_revid(dev); 481 sc->nfe_flags = 0; 482 483 switch (sc->nfe_devid) { 484 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2: 485 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3: 486 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4: 487 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5: 488 sc->nfe_flags |= NFE_JUMBO_SUP | NFE_HW_CSUM; 489 break; 490 case PCI_PRODUCT_NVIDIA_MCP51_LAN1: 491 case PCI_PRODUCT_NVIDIA_MCP51_LAN2: 492 sc->nfe_flags |= NFE_40BIT_ADDR | NFE_PWR_MGMT | NFE_MIB_V1; 493 break; 494 case PCI_PRODUCT_NVIDIA_CK804_LAN1: 495 case PCI_PRODUCT_NVIDIA_CK804_LAN2: 496 case PCI_PRODUCT_NVIDIA_MCP04_LAN1: 497 case PCI_PRODUCT_NVIDIA_MCP04_LAN2: 498 sc->nfe_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 499 NFE_MIB_V1; 500 break; 501 case PCI_PRODUCT_NVIDIA_MCP55_LAN1: 502 case PCI_PRODUCT_NVIDIA_MCP55_LAN2: 503 sc->nfe_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 504 NFE_HW_VLAN | NFE_PWR_MGMT | NFE_TX_FLOW_CTRL | NFE_MIB_V2; 505 break; 506 507 case PCI_PRODUCT_NVIDIA_MCP61_LAN1: 508 case PCI_PRODUCT_NVIDIA_MCP61_LAN2: 509 case PCI_PRODUCT_NVIDIA_MCP61_LAN3: 510 case PCI_PRODUCT_NVIDIA_MCP61_LAN4: 511 case PCI_PRODUCT_NVIDIA_MCP67_LAN1: 512 case PCI_PRODUCT_NVIDIA_MCP67_LAN2: 513 case PCI_PRODUCT_NVIDIA_MCP67_LAN3: 514 case PCI_PRODUCT_NVIDIA_MCP67_LAN4: 515 case PCI_PRODUCT_NVIDIA_MCP73_LAN1: 516 case PCI_PRODUCT_NVIDIA_MCP73_LAN2: 517 case PCI_PRODUCT_NVIDIA_MCP73_LAN3: 518 case PCI_PRODUCT_NVIDIA_MCP73_LAN4: 519 sc->nfe_flags |= NFE_40BIT_ADDR | NFE_PWR_MGMT | 520 NFE_CORRECT_MACADDR | NFE_TX_FLOW_CTRL | NFE_MIB_V2; 521 break; 522 case PCI_PRODUCT_NVIDIA_MCP77_LAN1: 523 case PCI_PRODUCT_NVIDIA_MCP77_LAN2: 524 case PCI_PRODUCT_NVIDIA_MCP77_LAN3: 525 case PCI_PRODUCT_NVIDIA_MCP77_LAN4: 526 /* XXX flow control */ 527 sc->nfe_flags |= NFE_40BIT_ADDR | NFE_HW_CSUM | NFE_PWR_MGMT | 528 NFE_CORRECT_MACADDR | NFE_MIB_V3; 529 break; 530 case PCI_PRODUCT_NVIDIA_MCP79_LAN1: 531 case PCI_PRODUCT_NVIDIA_MCP79_LAN2: 532 case PCI_PRODUCT_NVIDIA_MCP79_LAN3: 533 case PCI_PRODUCT_NVIDIA_MCP79_LAN4: 534 /* XXX flow control */ 535 sc->nfe_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 536 NFE_PWR_MGMT | NFE_CORRECT_MACADDR | NFE_MIB_V3; 537 break; 538 case PCI_PRODUCT_NVIDIA_MCP65_LAN1: 539 case PCI_PRODUCT_NVIDIA_MCP65_LAN2: 540 case PCI_PRODUCT_NVIDIA_MCP65_LAN3: 541 case PCI_PRODUCT_NVIDIA_MCP65_LAN4: 542 sc->nfe_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | 543 NFE_PWR_MGMT | NFE_CORRECT_MACADDR | NFE_TX_FLOW_CTRL | 544 NFE_MIB_V2; 545 break; 546 } 547 548 nfe_power(sc); 549 /* Check for reversed ethernet address */ 550 if ((NFE_READ(sc, NFE_TX_UNK) & NFE_MAC_ADDR_INORDER) != 0) 551 sc->nfe_flags |= NFE_CORRECT_MACADDR; 552 nfe_get_macaddr(sc, sc->eaddr); 553 /* 554 * Allocate the parent bus DMA tag appropriate for PCI. 555 */ 556 dma_addr_max = BUS_SPACE_MAXADDR_32BIT; 557 if ((sc->nfe_flags & NFE_40BIT_ADDR) != 0) 558 dma_addr_max = NFE_DMA_MAXADDR; 559 error = bus_dma_tag_create( 560 bus_get_dma_tag(sc->nfe_dev), /* parent */ 561 1, 0, /* alignment, boundary */ 562 dma_addr_max, /* lowaddr */ 563 BUS_SPACE_MAXADDR, /* highaddr */ 564 NULL, NULL, /* filter, filterarg */ 565 BUS_SPACE_MAXSIZE_32BIT, 0, /* maxsize, nsegments */ 566 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 567 0, /* flags */ 568 NULL, NULL, /* lockfunc, lockarg */ 569 &sc->nfe_parent_tag); 570 if (error) 571 goto fail; 572 573 ifp = sc->nfe_ifp = if_alloc(IFT_ETHER); 574 if (ifp == NULL) { 575 device_printf(dev, "can not if_alloc()\n"); 576 error = ENOSPC; 577 goto fail; 578 } 579 580 /* 581 * Allocate Tx and Rx rings. 582 */ 583 if ((error = nfe_alloc_tx_ring(sc, &sc->txq)) != 0) 584 goto fail; 585 586 if ((error = nfe_alloc_rx_ring(sc, &sc->rxq)) != 0) 587 goto fail; 588 589 nfe_alloc_jrx_ring(sc, &sc->jrxq); 590 /* Create sysctl node. */ 591 nfe_sysctl_node(sc); 592 593 ifp->if_softc = sc; 594 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 595 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 596 ifp->if_ioctl = nfe_ioctl; 597 ifp->if_start = nfe_start; 598 ifp->if_hwassist = 0; 599 ifp->if_capabilities = 0; 600 ifp->if_init = nfe_init; 601 IFQ_SET_MAXLEN(&ifp->if_snd, NFE_TX_RING_COUNT - 1); 602 ifp->if_snd.ifq_drv_maxlen = NFE_TX_RING_COUNT - 1; 603 IFQ_SET_READY(&ifp->if_snd); 604 605 if (sc->nfe_flags & NFE_HW_CSUM) { 606 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_TSO4; 607 ifp->if_hwassist |= NFE_CSUM_FEATURES | CSUM_TSO; 608 } 609 ifp->if_capenable = ifp->if_capabilities; 610 611 sc->nfe_framesize = ifp->if_mtu + NFE_RX_HEADERS; 612 /* VLAN capability setup. */ 613 ifp->if_capabilities |= IFCAP_VLAN_MTU; 614 if ((sc->nfe_flags & NFE_HW_VLAN) != 0) { 615 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 616 if ((ifp->if_capabilities & IFCAP_HWCSUM) != 0) 617 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | 618 IFCAP_VLAN_HWTSO; 619 } 620 621 if (pci_find_cap(dev, PCIY_PMG, ®) == 0) 622 ifp->if_capabilities |= IFCAP_WOL_MAGIC; 623 ifp->if_capenable = ifp->if_capabilities; 624 625 /* 626 * Tell the upper layer(s) we support long frames. 627 * Must appear after the call to ether_ifattach() because 628 * ether_ifattach() sets ifi_hdrlen to the default value. 629 */ 630 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 631 632#ifdef DEVICE_POLLING 633 ifp->if_capabilities |= IFCAP_POLLING; 634#endif 635 636 /* Do MII setup */ 637 phyloc = MII_PHY_ANY; 638 if (sc->nfe_devid == PCI_PRODUCT_NVIDIA_MCP61_LAN1 || 639 sc->nfe_devid == PCI_PRODUCT_NVIDIA_MCP61_LAN2 || 640 sc->nfe_devid == PCI_PRODUCT_NVIDIA_MCP61_LAN3 || 641 sc->nfe_devid == PCI_PRODUCT_NVIDIA_MCP61_LAN4) { 642 if (nfe_detect_msik9(sc) != 0) 643 phyloc = 0; 644 } 645 error = mii_attach(dev, &sc->nfe_miibus, ifp, nfe_ifmedia_upd, 646 nfe_ifmedia_sts, BMSR_DEFCAPMASK, phyloc, MII_OFFSET_ANY, 647 MIIF_DOPAUSE); 648 if (error != 0) { 649 device_printf(dev, "attaching PHYs failed\n"); 650 goto fail; 651 } 652 ether_ifattach(ifp, sc->eaddr); 653 654 TASK_INIT(&sc->nfe_int_task, 0, nfe_int_task, sc); 655 sc->nfe_tq = taskqueue_create_fast("nfe_taskq", M_WAITOK, 656 taskqueue_thread_enqueue, &sc->nfe_tq); 657 taskqueue_start_threads(&sc->nfe_tq, 1, PI_NET, "%s taskq", 658 device_get_nameunit(sc->nfe_dev)); 659 error = 0; 660 if (sc->nfe_msi == 0 && sc->nfe_msix == 0) { 661 error = bus_setup_intr(dev, sc->nfe_irq[0], 662 INTR_TYPE_NET | INTR_MPSAFE, nfe_intr, NULL, sc, 663 &sc->nfe_intrhand[0]); 664 } else { 665 for (i = 0; i < NFE_MSI_MESSAGES; i++) { 666 error = bus_setup_intr(dev, sc->nfe_irq[i], 667 INTR_TYPE_NET | INTR_MPSAFE, nfe_intr, NULL, sc, 668 &sc->nfe_intrhand[i]); 669 if (error != 0) 670 break; 671 } 672 } 673 if (error) { 674 device_printf(dev, "couldn't set up irq\n"); 675 taskqueue_free(sc->nfe_tq); 676 sc->nfe_tq = NULL; 677 ether_ifdetach(ifp); 678 goto fail; 679 } 680 681fail: 682 if (error) 683 nfe_detach(dev); 684 685 return (error); 686} 687 688 689static int 690nfe_detach(device_t dev) 691{ 692 struct nfe_softc *sc; 693 struct ifnet *ifp; 694 uint8_t eaddr[ETHER_ADDR_LEN]; 695 int i, rid; 696 697 sc = device_get_softc(dev); 698 KASSERT(mtx_initialized(&sc->nfe_mtx), ("nfe mutex not initialized")); 699 ifp = sc->nfe_ifp; 700 701#ifdef DEVICE_POLLING 702 if (ifp != NULL && ifp->if_capenable & IFCAP_POLLING) 703 ether_poll_deregister(ifp); 704#endif 705 if (device_is_attached(dev)) { 706 NFE_LOCK(sc); 707 nfe_stop(ifp); 708 ifp->if_flags &= ~IFF_UP; 709 NFE_UNLOCK(sc); 710 callout_drain(&sc->nfe_stat_ch); 711 ether_ifdetach(ifp); 712 } 713 714 if (ifp) { 715 /* restore ethernet address */ 716 if ((sc->nfe_flags & NFE_CORRECT_MACADDR) == 0) { 717 for (i = 0; i < ETHER_ADDR_LEN; i++) { 718 eaddr[i] = sc->eaddr[5 - i]; 719 } 720 } else 721 bcopy(sc->eaddr, eaddr, ETHER_ADDR_LEN); 722 nfe_set_macaddr(sc, eaddr); 723 if_free(ifp); 724 } 725 if (sc->nfe_miibus) 726 device_delete_child(dev, sc->nfe_miibus); 727 bus_generic_detach(dev); 728 if (sc->nfe_tq != NULL) { 729 taskqueue_drain(sc->nfe_tq, &sc->nfe_int_task); 730 taskqueue_free(sc->nfe_tq); 731 sc->nfe_tq = NULL; 732 } 733 734 for (i = 0; i < NFE_MSI_MESSAGES; i++) { 735 if (sc->nfe_intrhand[i] != NULL) { 736 bus_teardown_intr(dev, sc->nfe_irq[i], 737 sc->nfe_intrhand[i]); 738 sc->nfe_intrhand[i] = NULL; 739 } 740 } 741 742 if (sc->nfe_msi == 0 && sc->nfe_msix == 0) { 743 if (sc->nfe_irq[0] != NULL) 744 bus_release_resource(dev, SYS_RES_IRQ, 0, 745 sc->nfe_irq[0]); 746 } else { 747 for (i = 0, rid = 1; i < NFE_MSI_MESSAGES; i++, rid++) { 748 if (sc->nfe_irq[i] != NULL) { 749 bus_release_resource(dev, SYS_RES_IRQ, rid, 750 sc->nfe_irq[i]); 751 sc->nfe_irq[i] = NULL; 752 } 753 } 754 pci_release_msi(dev); 755 } 756 if (sc->nfe_msix_pba_res != NULL) { 757 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(3), 758 sc->nfe_msix_pba_res); 759 sc->nfe_msix_pba_res = NULL; 760 } 761 if (sc->nfe_msix_res != NULL) { 762 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(2), 763 sc->nfe_msix_res); 764 sc->nfe_msix_res = NULL; 765 } 766 if (sc->nfe_res[0] != NULL) { 767 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), 768 sc->nfe_res[0]); 769 sc->nfe_res[0] = NULL; 770 } 771 772 nfe_free_tx_ring(sc, &sc->txq); 773 nfe_free_rx_ring(sc, &sc->rxq); 774 nfe_free_jrx_ring(sc, &sc->jrxq); 775 776 if (sc->nfe_parent_tag) { 777 bus_dma_tag_destroy(sc->nfe_parent_tag); 778 sc->nfe_parent_tag = NULL; 779 } 780 781 mtx_destroy(&sc->nfe_mtx); 782 783 return (0); 784} 785 786 787static int 788nfe_suspend(device_t dev) 789{ 790 struct nfe_softc *sc; 791 792 sc = device_get_softc(dev); 793 794 NFE_LOCK(sc); 795 nfe_stop(sc->nfe_ifp); 796 nfe_set_wol(sc); 797 sc->nfe_suspended = 1; 798 NFE_UNLOCK(sc); 799 800 return (0); 801} 802 803 804static int 805nfe_resume(device_t dev) 806{ 807 struct nfe_softc *sc; 808 struct ifnet *ifp; 809 810 sc = device_get_softc(dev); 811 812 NFE_LOCK(sc); 813 nfe_power(sc); 814 ifp = sc->nfe_ifp; 815 if (ifp->if_flags & IFF_UP) 816 nfe_init_locked(sc); 817 sc->nfe_suspended = 0; 818 NFE_UNLOCK(sc); 819 820 return (0); 821} 822 823 824static int 825nfe_can_use_msix(struct nfe_softc *sc) 826{ 827 static struct msix_blacklist { 828 char *maker; 829 char *product; 830 } msix_blacklists[] = { 831 { "ASUSTeK Computer INC.", "P5N32-SLI PREMIUM" } 832 }; 833 834 struct msix_blacklist *mblp; 835 char *maker, *product; 836 int count, n, use_msix; 837 838 /* 839 * Search base board manufacturer and product name table 840 * to see this system has a known MSI/MSI-X issue. 841 */ 842 maker = getenv("smbios.planar.maker"); 843 product = getenv("smbios.planar.product"); 844 use_msix = 1; 845 if (maker != NULL && product != NULL) { 846 count = sizeof(msix_blacklists) / sizeof(msix_blacklists[0]); 847 mblp = msix_blacklists; 848 for (n = 0; n < count; n++) { 849 if (strcmp(maker, mblp->maker) == 0 && 850 strcmp(product, mblp->product) == 0) { 851 use_msix = 0; 852 break; 853 } 854 mblp++; 855 } 856 } 857 if (maker != NULL) 858 freeenv(maker); 859 if (product != NULL) 860 freeenv(product); 861 862 return (use_msix); 863} 864 865 866/* Take PHY/NIC out of powerdown, from Linux */ 867static void 868nfe_power(struct nfe_softc *sc) 869{ 870 uint32_t pwr; 871 872 if ((sc->nfe_flags & NFE_PWR_MGMT) == 0) 873 return; 874 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | NFE_RXTX_BIT2); 875 NFE_WRITE(sc, NFE_MAC_RESET, NFE_MAC_RESET_MAGIC); 876 DELAY(100); 877 NFE_WRITE(sc, NFE_MAC_RESET, 0); 878 DELAY(100); 879 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT2); 880 pwr = NFE_READ(sc, NFE_PWR2_CTL); 881 pwr &= ~NFE_PWR2_WAKEUP_MASK; 882 if (sc->nfe_revid >= 0xa3 && 883 (sc->nfe_devid == PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 || 884 sc->nfe_devid == PCI_PRODUCT_NVIDIA_NFORCE430_LAN2)) 885 pwr |= NFE_PWR2_REVA3; 886 NFE_WRITE(sc, NFE_PWR2_CTL, pwr); 887} 888 889 890static void 891nfe_miibus_statchg(device_t dev) 892{ 893 struct nfe_softc *sc; 894 struct mii_data *mii; 895 struct ifnet *ifp; 896 uint32_t rxctl, txctl; 897 898 sc = device_get_softc(dev); 899 900 mii = device_get_softc(sc->nfe_miibus); 901 ifp = sc->nfe_ifp; 902 903 sc->nfe_link = 0; 904 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 905 (IFM_ACTIVE | IFM_AVALID)) { 906 switch (IFM_SUBTYPE(mii->mii_media_active)) { 907 case IFM_10_T: 908 case IFM_100_TX: 909 case IFM_1000_T: 910 sc->nfe_link = 1; 911 break; 912 default: 913 break; 914 } 915 } 916 917 nfe_mac_config(sc, mii); 918 txctl = NFE_READ(sc, NFE_TX_CTL); 919 rxctl = NFE_READ(sc, NFE_RX_CTL); 920 if (sc->nfe_link != 0 && (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 921 txctl |= NFE_TX_START; 922 rxctl |= NFE_RX_START; 923 } else { 924 txctl &= ~NFE_TX_START; 925 rxctl &= ~NFE_RX_START; 926 } 927 NFE_WRITE(sc, NFE_TX_CTL, txctl); 928 NFE_WRITE(sc, NFE_RX_CTL, rxctl); 929} 930 931 932static void 933nfe_mac_config(struct nfe_softc *sc, struct mii_data *mii) 934{ 935 uint32_t link, misc, phy, seed; 936 uint32_t val; 937 938 NFE_LOCK_ASSERT(sc); 939 940 phy = NFE_READ(sc, NFE_PHY_IFACE); 941 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T); 942 943 seed = NFE_READ(sc, NFE_RNDSEED); 944 seed &= ~NFE_SEED_MASK; 945 946 misc = NFE_MISC1_MAGIC; 947 link = NFE_MEDIA_SET; 948 949 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0) { 950 phy |= NFE_PHY_HDX; /* half-duplex */ 951 misc |= NFE_MISC1_HDX; 952 } 953 954 switch (IFM_SUBTYPE(mii->mii_media_active)) { 955 case IFM_1000_T: /* full-duplex only */ 956 link |= NFE_MEDIA_1000T; 957 seed |= NFE_SEED_1000T; 958 phy |= NFE_PHY_1000T; 959 break; 960 case IFM_100_TX: 961 link |= NFE_MEDIA_100TX; 962 seed |= NFE_SEED_100TX; 963 phy |= NFE_PHY_100TX; 964 break; 965 case IFM_10_T: 966 link |= NFE_MEDIA_10T; 967 seed |= NFE_SEED_10T; 968 break; 969 } 970 971 if ((phy & 0x10000000) != 0) { 972 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) 973 val = NFE_R1_MAGIC_1000; 974 else 975 val = NFE_R1_MAGIC_10_100; 976 } else 977 val = NFE_R1_MAGIC_DEFAULT; 978 NFE_WRITE(sc, NFE_SETUP_R1, val); 979 980 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */ 981 982 NFE_WRITE(sc, NFE_PHY_IFACE, phy); 983 NFE_WRITE(sc, NFE_MISC1, misc); 984 NFE_WRITE(sc, NFE_LINKSPEED, link); 985 986 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 987 /* It seems all hardwares supports Rx pause frames. */ 988 val = NFE_READ(sc, NFE_RXFILTER); 989 if ((IFM_OPTIONS(mii->mii_media_active) & 990 IFM_ETH_RXPAUSE) != 0) 991 val |= NFE_PFF_RX_PAUSE; 992 else 993 val &= ~NFE_PFF_RX_PAUSE; 994 NFE_WRITE(sc, NFE_RXFILTER, val); 995 if ((sc->nfe_flags & NFE_TX_FLOW_CTRL) != 0) { 996 val = NFE_READ(sc, NFE_MISC1); 997 if ((IFM_OPTIONS(mii->mii_media_active) & 998 IFM_ETH_TXPAUSE) != 0) { 999 NFE_WRITE(sc, NFE_TX_PAUSE_FRAME, 1000 NFE_TX_PAUSE_FRAME_ENABLE); 1001 val |= NFE_MISC1_TX_PAUSE; 1002 } else { 1003 val &= ~NFE_MISC1_TX_PAUSE; 1004 NFE_WRITE(sc, NFE_TX_PAUSE_FRAME, 1005 NFE_TX_PAUSE_FRAME_DISABLE); 1006 } 1007 NFE_WRITE(sc, NFE_MISC1, val); 1008 } 1009 } else { 1010 /* disable rx/tx pause frames */ 1011 val = NFE_READ(sc, NFE_RXFILTER); 1012 val &= ~NFE_PFF_RX_PAUSE; 1013 NFE_WRITE(sc, NFE_RXFILTER, val); 1014 if ((sc->nfe_flags & NFE_TX_FLOW_CTRL) != 0) { 1015 NFE_WRITE(sc, NFE_TX_PAUSE_FRAME, 1016 NFE_TX_PAUSE_FRAME_DISABLE); 1017 val = NFE_READ(sc, NFE_MISC1); 1018 val &= ~NFE_MISC1_TX_PAUSE; 1019 NFE_WRITE(sc, NFE_MISC1, val); 1020 } 1021 } 1022} 1023 1024 1025static int 1026nfe_miibus_readreg(device_t dev, int phy, int reg) 1027{ 1028 struct nfe_softc *sc = device_get_softc(dev); 1029 uint32_t val; 1030 int ntries; 1031 1032 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1033 1034 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 1035 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 1036 DELAY(100); 1037 } 1038 1039 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg); 1040 1041 for (ntries = 0; ntries < NFE_TIMEOUT; ntries++) { 1042 DELAY(100); 1043 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 1044 break; 1045 } 1046 if (ntries == NFE_TIMEOUT) { 1047 DPRINTFN(sc, 2, "timeout waiting for PHY\n"); 1048 return 0; 1049 } 1050 1051 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) { 1052 DPRINTFN(sc, 2, "could not read PHY\n"); 1053 return 0; 1054 } 1055 1056 val = NFE_READ(sc, NFE_PHY_DATA); 1057 if (val != 0xffffffff && val != 0) 1058 sc->mii_phyaddr = phy; 1059 1060 DPRINTFN(sc, 2, "mii read phy %d reg 0x%x ret 0x%x\n", phy, reg, val); 1061 1062 return (val); 1063} 1064 1065 1066static int 1067nfe_miibus_writereg(device_t dev, int phy, int reg, int val) 1068{ 1069 struct nfe_softc *sc = device_get_softc(dev); 1070 uint32_t ctl; 1071 int ntries; 1072 1073 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1074 1075 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 1076 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 1077 DELAY(100); 1078 } 1079 1080 NFE_WRITE(sc, NFE_PHY_DATA, val); 1081 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg; 1082 NFE_WRITE(sc, NFE_PHY_CTL, ctl); 1083 1084 for (ntries = 0; ntries < NFE_TIMEOUT; ntries++) { 1085 DELAY(100); 1086 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 1087 break; 1088 } 1089#ifdef NFE_DEBUG 1090 if (nfedebug >= 2 && ntries == NFE_TIMEOUT) 1091 device_printf(sc->nfe_dev, "could not write to PHY\n"); 1092#endif 1093 return (0); 1094} 1095 1096struct nfe_dmamap_arg { 1097 bus_addr_t nfe_busaddr; 1098}; 1099 1100static int 1101nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1102{ 1103 struct nfe_dmamap_arg ctx; 1104 struct nfe_rx_data *data; 1105 void *desc; 1106 int i, error, descsize; 1107 1108 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1109 desc = ring->desc64; 1110 descsize = sizeof (struct nfe_desc64); 1111 } else { 1112 desc = ring->desc32; 1113 descsize = sizeof (struct nfe_desc32); 1114 } 1115 1116 ring->cur = ring->next = 0; 1117 1118 error = bus_dma_tag_create(sc->nfe_parent_tag, 1119 NFE_RING_ALIGN, 0, /* alignment, boundary */ 1120 BUS_SPACE_MAXADDR, /* lowaddr */ 1121 BUS_SPACE_MAXADDR, /* highaddr */ 1122 NULL, NULL, /* filter, filterarg */ 1123 NFE_RX_RING_COUNT * descsize, 1, /* maxsize, nsegments */ 1124 NFE_RX_RING_COUNT * descsize, /* maxsegsize */ 1125 0, /* flags */ 1126 NULL, NULL, /* lockfunc, lockarg */ 1127 &ring->rx_desc_tag); 1128 if (error != 0) { 1129 device_printf(sc->nfe_dev, "could not create desc DMA tag\n"); 1130 goto fail; 1131 } 1132 1133 /* allocate memory to desc */ 1134 error = bus_dmamem_alloc(ring->rx_desc_tag, &desc, BUS_DMA_WAITOK | 1135 BUS_DMA_COHERENT | BUS_DMA_ZERO, &ring->rx_desc_map); 1136 if (error != 0) { 1137 device_printf(sc->nfe_dev, "could not create desc DMA map\n"); 1138 goto fail; 1139 } 1140 if (sc->nfe_flags & NFE_40BIT_ADDR) 1141 ring->desc64 = desc; 1142 else 1143 ring->desc32 = desc; 1144 1145 /* map desc to device visible address space */ 1146 ctx.nfe_busaddr = 0; 1147 error = bus_dmamap_load(ring->rx_desc_tag, ring->rx_desc_map, desc, 1148 NFE_RX_RING_COUNT * descsize, nfe_dma_map_segs, &ctx, 0); 1149 if (error != 0) { 1150 device_printf(sc->nfe_dev, "could not load desc DMA map\n"); 1151 goto fail; 1152 } 1153 ring->physaddr = ctx.nfe_busaddr; 1154 1155 error = bus_dma_tag_create(sc->nfe_parent_tag, 1156 1, 0, /* alignment, boundary */ 1157 BUS_SPACE_MAXADDR, /* lowaddr */ 1158 BUS_SPACE_MAXADDR, /* highaddr */ 1159 NULL, NULL, /* filter, filterarg */ 1160 MCLBYTES, 1, /* maxsize, nsegments */ 1161 MCLBYTES, /* maxsegsize */ 1162 0, /* flags */ 1163 NULL, NULL, /* lockfunc, lockarg */ 1164 &ring->rx_data_tag); 1165 if (error != 0) { 1166 device_printf(sc->nfe_dev, "could not create Rx DMA tag\n"); 1167 goto fail; 1168 } 1169 1170 error = bus_dmamap_create(ring->rx_data_tag, 0, &ring->rx_spare_map); 1171 if (error != 0) { 1172 device_printf(sc->nfe_dev, 1173 "could not create Rx DMA spare map\n"); 1174 goto fail; 1175 } 1176 1177 /* 1178 * Pre-allocate Rx buffers and populate Rx ring. 1179 */ 1180 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1181 data = &sc->rxq.data[i]; 1182 data->rx_data_map = NULL; 1183 data->m = NULL; 1184 error = bus_dmamap_create(ring->rx_data_tag, 0, 1185 &data->rx_data_map); 1186 if (error != 0) { 1187 device_printf(sc->nfe_dev, 1188 "could not create Rx DMA map\n"); 1189 goto fail; 1190 } 1191 } 1192 1193fail: 1194 return (error); 1195} 1196 1197 1198static void 1199nfe_alloc_jrx_ring(struct nfe_softc *sc, struct nfe_jrx_ring *ring) 1200{ 1201 struct nfe_dmamap_arg ctx; 1202 struct nfe_rx_data *data; 1203 void *desc; 1204 int i, error, descsize; 1205 1206 if ((sc->nfe_flags & NFE_JUMBO_SUP) == 0) 1207 return; 1208 if (jumbo_disable != 0) { 1209 device_printf(sc->nfe_dev, "disabling jumbo frame support\n"); 1210 sc->nfe_jumbo_disable = 1; 1211 return; 1212 } 1213 1214 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1215 desc = ring->jdesc64; 1216 descsize = sizeof (struct nfe_desc64); 1217 } else { 1218 desc = ring->jdesc32; 1219 descsize = sizeof (struct nfe_desc32); 1220 } 1221 1222 ring->jcur = ring->jnext = 0; 1223 1224 /* Create DMA tag for jumbo Rx ring. */ 1225 error = bus_dma_tag_create(sc->nfe_parent_tag, 1226 NFE_RING_ALIGN, 0, /* alignment, boundary */ 1227 BUS_SPACE_MAXADDR, /* lowaddr */ 1228 BUS_SPACE_MAXADDR, /* highaddr */ 1229 NULL, NULL, /* filter, filterarg */ 1230 NFE_JUMBO_RX_RING_COUNT * descsize, /* maxsize */ 1231 1, /* nsegments */ 1232 NFE_JUMBO_RX_RING_COUNT * descsize, /* maxsegsize */ 1233 0, /* flags */ 1234 NULL, NULL, /* lockfunc, lockarg */ 1235 &ring->jrx_desc_tag); 1236 if (error != 0) { 1237 device_printf(sc->nfe_dev, 1238 "could not create jumbo ring DMA tag\n"); 1239 goto fail; 1240 } 1241 1242 /* Create DMA tag for jumbo Rx buffers. */ 1243 error = bus_dma_tag_create(sc->nfe_parent_tag, 1244 1, 0, /* alignment, boundary */ 1245 BUS_SPACE_MAXADDR, /* lowaddr */ 1246 BUS_SPACE_MAXADDR, /* highaddr */ 1247 NULL, NULL, /* filter, filterarg */ 1248 MJUM9BYTES, /* maxsize */ 1249 1, /* nsegments */ 1250 MJUM9BYTES, /* maxsegsize */ 1251 0, /* flags */ 1252 NULL, NULL, /* lockfunc, lockarg */ 1253 &ring->jrx_data_tag); 1254 if (error != 0) { 1255 device_printf(sc->nfe_dev, 1256 "could not create jumbo Rx buffer DMA tag\n"); 1257 goto fail; 1258 } 1259 1260 /* Allocate DMA'able memory and load the DMA map for jumbo Rx ring. */ 1261 error = bus_dmamem_alloc(ring->jrx_desc_tag, &desc, BUS_DMA_WAITOK | 1262 BUS_DMA_COHERENT | BUS_DMA_ZERO, &ring->jrx_desc_map); 1263 if (error != 0) { 1264 device_printf(sc->nfe_dev, 1265 "could not allocate DMA'able memory for jumbo Rx ring\n"); 1266 goto fail; 1267 } 1268 if (sc->nfe_flags & NFE_40BIT_ADDR) 1269 ring->jdesc64 = desc; 1270 else 1271 ring->jdesc32 = desc; 1272 1273 ctx.nfe_busaddr = 0; 1274 error = bus_dmamap_load(ring->jrx_desc_tag, ring->jrx_desc_map, desc, 1275 NFE_JUMBO_RX_RING_COUNT * descsize, nfe_dma_map_segs, &ctx, 0); 1276 if (error != 0) { 1277 device_printf(sc->nfe_dev, 1278 "could not load DMA'able memory for jumbo Rx ring\n"); 1279 goto fail; 1280 } 1281 ring->jphysaddr = ctx.nfe_busaddr; 1282 1283 /* Create DMA maps for jumbo Rx buffers. */ 1284 error = bus_dmamap_create(ring->jrx_data_tag, 0, &ring->jrx_spare_map); 1285 if (error != 0) { 1286 device_printf(sc->nfe_dev, 1287 "could not create jumbo Rx DMA spare map\n"); 1288 goto fail; 1289 } 1290 1291 for (i = 0; i < NFE_JUMBO_RX_RING_COUNT; i++) { 1292 data = &sc->jrxq.jdata[i]; 1293 data->rx_data_map = NULL; 1294 data->m = NULL; 1295 error = bus_dmamap_create(ring->jrx_data_tag, 0, 1296 &data->rx_data_map); 1297 if (error != 0) { 1298 device_printf(sc->nfe_dev, 1299 "could not create jumbo Rx DMA map\n"); 1300 goto fail; 1301 } 1302 } 1303 1304 return; 1305 1306fail: 1307 /* 1308 * Running without jumbo frame support is ok for most cases 1309 * so don't fail on creating dma tag/map for jumbo frame. 1310 */ 1311 nfe_free_jrx_ring(sc, ring); 1312 device_printf(sc->nfe_dev, "disabling jumbo frame support due to " 1313 "resource shortage\n"); 1314 sc->nfe_jumbo_disable = 1; 1315} 1316 1317 1318static int 1319nfe_init_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1320{ 1321 void *desc; 1322 size_t descsize; 1323 int i; 1324 1325 ring->cur = ring->next = 0; 1326 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1327 desc = ring->desc64; 1328 descsize = sizeof (struct nfe_desc64); 1329 } else { 1330 desc = ring->desc32; 1331 descsize = sizeof (struct nfe_desc32); 1332 } 1333 bzero(desc, descsize * NFE_RX_RING_COUNT); 1334 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1335 if (nfe_newbuf(sc, i) != 0) 1336 return (ENOBUFS); 1337 } 1338 1339 bus_dmamap_sync(ring->rx_desc_tag, ring->rx_desc_map, 1340 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1341 1342 return (0); 1343} 1344 1345 1346static int 1347nfe_init_jrx_ring(struct nfe_softc *sc, struct nfe_jrx_ring *ring) 1348{ 1349 void *desc; 1350 size_t descsize; 1351 int i; 1352 1353 ring->jcur = ring->jnext = 0; 1354 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1355 desc = ring->jdesc64; 1356 descsize = sizeof (struct nfe_desc64); 1357 } else { 1358 desc = ring->jdesc32; 1359 descsize = sizeof (struct nfe_desc32); 1360 } 1361 bzero(desc, descsize * NFE_JUMBO_RX_RING_COUNT); 1362 for (i = 0; i < NFE_JUMBO_RX_RING_COUNT; i++) { 1363 if (nfe_jnewbuf(sc, i) != 0) 1364 return (ENOBUFS); 1365 } 1366 1367 bus_dmamap_sync(ring->jrx_desc_tag, ring->jrx_desc_map, 1368 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1369 1370 return (0); 1371} 1372 1373 1374static void 1375nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1376{ 1377 struct nfe_rx_data *data; 1378 void *desc; 1379 int i; 1380 1381 if (sc->nfe_flags & NFE_40BIT_ADDR) 1382 desc = ring->desc64; 1383 else 1384 desc = ring->desc32; 1385 1386 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1387 data = &ring->data[i]; 1388 if (data->rx_data_map != NULL) { 1389 bus_dmamap_destroy(ring->rx_data_tag, 1390 data->rx_data_map); 1391 data->rx_data_map = NULL; 1392 } 1393 if (data->m != NULL) { 1394 m_freem(data->m); 1395 data->m = NULL; 1396 } 1397 } 1398 if (ring->rx_data_tag != NULL) { 1399 if (ring->rx_spare_map != NULL) { 1400 bus_dmamap_destroy(ring->rx_data_tag, 1401 ring->rx_spare_map); 1402 ring->rx_spare_map = NULL; 1403 } 1404 bus_dma_tag_destroy(ring->rx_data_tag); 1405 ring->rx_data_tag = NULL; 1406 } 1407 1408 if (desc != NULL) { 1409 bus_dmamap_unload(ring->rx_desc_tag, ring->rx_desc_map); 1410 bus_dmamem_free(ring->rx_desc_tag, desc, ring->rx_desc_map); 1411 ring->desc64 = NULL; 1412 ring->desc32 = NULL; 1413 ring->rx_desc_map = NULL; 1414 } 1415 if (ring->rx_desc_tag != NULL) { 1416 bus_dma_tag_destroy(ring->rx_desc_tag); 1417 ring->rx_desc_tag = NULL; 1418 } 1419} 1420 1421 1422static void 1423nfe_free_jrx_ring(struct nfe_softc *sc, struct nfe_jrx_ring *ring) 1424{ 1425 struct nfe_rx_data *data; 1426 void *desc; 1427 int i, descsize; 1428 1429 if ((sc->nfe_flags & NFE_JUMBO_SUP) == 0) 1430 return; 1431 1432 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1433 desc = ring->jdesc64; 1434 descsize = sizeof (struct nfe_desc64); 1435 } else { 1436 desc = ring->jdesc32; 1437 descsize = sizeof (struct nfe_desc32); 1438 } 1439 1440 for (i = 0; i < NFE_JUMBO_RX_RING_COUNT; i++) { 1441 data = &ring->jdata[i]; 1442 if (data->rx_data_map != NULL) { 1443 bus_dmamap_destroy(ring->jrx_data_tag, 1444 data->rx_data_map); 1445 data->rx_data_map = NULL; 1446 } 1447 if (data->m != NULL) { 1448 m_freem(data->m); 1449 data->m = NULL; 1450 } 1451 } 1452 if (ring->jrx_data_tag != NULL) { 1453 if (ring->jrx_spare_map != NULL) { 1454 bus_dmamap_destroy(ring->jrx_data_tag, 1455 ring->jrx_spare_map); 1456 ring->jrx_spare_map = NULL; 1457 } 1458 bus_dma_tag_destroy(ring->jrx_data_tag); 1459 ring->jrx_data_tag = NULL; 1460 } 1461 1462 if (desc != NULL) { 1463 bus_dmamap_unload(ring->jrx_desc_tag, ring->jrx_desc_map); 1464 bus_dmamem_free(ring->jrx_desc_tag, desc, ring->jrx_desc_map); 1465 ring->jdesc64 = NULL; 1466 ring->jdesc32 = NULL; 1467 ring->jrx_desc_map = NULL; 1468 } 1469 1470 if (ring->jrx_desc_tag != NULL) { 1471 bus_dma_tag_destroy(ring->jrx_desc_tag); 1472 ring->jrx_desc_tag = NULL; 1473 } 1474} 1475 1476 1477static int 1478nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1479{ 1480 struct nfe_dmamap_arg ctx; 1481 int i, error; 1482 void *desc; 1483 int descsize; 1484 1485 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1486 desc = ring->desc64; 1487 descsize = sizeof (struct nfe_desc64); 1488 } else { 1489 desc = ring->desc32; 1490 descsize = sizeof (struct nfe_desc32); 1491 } 1492 1493 ring->queued = 0; 1494 ring->cur = ring->next = 0; 1495 1496 error = bus_dma_tag_create(sc->nfe_parent_tag, 1497 NFE_RING_ALIGN, 0, /* alignment, boundary */ 1498 BUS_SPACE_MAXADDR, /* lowaddr */ 1499 BUS_SPACE_MAXADDR, /* highaddr */ 1500 NULL, NULL, /* filter, filterarg */ 1501 NFE_TX_RING_COUNT * descsize, 1, /* maxsize, nsegments */ 1502 NFE_TX_RING_COUNT * descsize, /* maxsegsize */ 1503 0, /* flags */ 1504 NULL, NULL, /* lockfunc, lockarg */ 1505 &ring->tx_desc_tag); 1506 if (error != 0) { 1507 device_printf(sc->nfe_dev, "could not create desc DMA tag\n"); 1508 goto fail; 1509 } 1510 1511 error = bus_dmamem_alloc(ring->tx_desc_tag, &desc, BUS_DMA_WAITOK | 1512 BUS_DMA_COHERENT | BUS_DMA_ZERO, &ring->tx_desc_map); 1513 if (error != 0) { 1514 device_printf(sc->nfe_dev, "could not create desc DMA map\n"); 1515 goto fail; 1516 } 1517 if (sc->nfe_flags & NFE_40BIT_ADDR) 1518 ring->desc64 = desc; 1519 else 1520 ring->desc32 = desc; 1521 1522 ctx.nfe_busaddr = 0; 1523 error = bus_dmamap_load(ring->tx_desc_tag, ring->tx_desc_map, desc, 1524 NFE_TX_RING_COUNT * descsize, nfe_dma_map_segs, &ctx, 0); 1525 if (error != 0) { 1526 device_printf(sc->nfe_dev, "could not load desc DMA map\n"); 1527 goto fail; 1528 } 1529 ring->physaddr = ctx.nfe_busaddr; 1530 1531 error = bus_dma_tag_create(sc->nfe_parent_tag, 1532 1, 0, 1533 BUS_SPACE_MAXADDR, 1534 BUS_SPACE_MAXADDR, 1535 NULL, NULL, 1536 NFE_TSO_MAXSIZE, 1537 NFE_MAX_SCATTER, 1538 NFE_TSO_MAXSGSIZE, 1539 0, 1540 NULL, NULL, 1541 &ring->tx_data_tag); 1542 if (error != 0) { 1543 device_printf(sc->nfe_dev, "could not create Tx DMA tag\n"); 1544 goto fail; 1545 } 1546 1547 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1548 error = bus_dmamap_create(ring->tx_data_tag, 0, 1549 &ring->data[i].tx_data_map); 1550 if (error != 0) { 1551 device_printf(sc->nfe_dev, 1552 "could not create Tx DMA map\n"); 1553 goto fail; 1554 } 1555 } 1556 1557fail: 1558 return (error); 1559} 1560 1561 1562static void 1563nfe_init_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1564{ 1565 void *desc; 1566 size_t descsize; 1567 1568 sc->nfe_force_tx = 0; 1569 ring->queued = 0; 1570 ring->cur = ring->next = 0; 1571 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1572 desc = ring->desc64; 1573 descsize = sizeof (struct nfe_desc64); 1574 } else { 1575 desc = ring->desc32; 1576 descsize = sizeof (struct nfe_desc32); 1577 } 1578 bzero(desc, descsize * NFE_TX_RING_COUNT); 1579 1580 bus_dmamap_sync(ring->tx_desc_tag, ring->tx_desc_map, 1581 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1582} 1583 1584 1585static void 1586nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1587{ 1588 struct nfe_tx_data *data; 1589 void *desc; 1590 int i, descsize; 1591 1592 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1593 desc = ring->desc64; 1594 descsize = sizeof (struct nfe_desc64); 1595 } else { 1596 desc = ring->desc32; 1597 descsize = sizeof (struct nfe_desc32); 1598 } 1599 1600 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1601 data = &ring->data[i]; 1602 1603 if (data->m != NULL) { 1604 bus_dmamap_sync(ring->tx_data_tag, data->tx_data_map, 1605 BUS_DMASYNC_POSTWRITE); 1606 bus_dmamap_unload(ring->tx_data_tag, data->tx_data_map); 1607 m_freem(data->m); 1608 data->m = NULL; 1609 } 1610 if (data->tx_data_map != NULL) { 1611 bus_dmamap_destroy(ring->tx_data_tag, 1612 data->tx_data_map); 1613 data->tx_data_map = NULL; 1614 } 1615 } 1616 1617 if (ring->tx_data_tag != NULL) { 1618 bus_dma_tag_destroy(ring->tx_data_tag); 1619 ring->tx_data_tag = NULL; 1620 } 1621 1622 if (desc != NULL) { 1623 bus_dmamap_sync(ring->tx_desc_tag, ring->tx_desc_map, 1624 BUS_DMASYNC_POSTWRITE); 1625 bus_dmamap_unload(ring->tx_desc_tag, ring->tx_desc_map); 1626 bus_dmamem_free(ring->tx_desc_tag, desc, ring->tx_desc_map); 1627 ring->desc64 = NULL; 1628 ring->desc32 = NULL; 1629 ring->tx_desc_map = NULL; 1630 bus_dma_tag_destroy(ring->tx_desc_tag); 1631 ring->tx_desc_tag = NULL; 1632 } 1633} 1634 1635#ifdef DEVICE_POLLING 1636static poll_handler_t nfe_poll; 1637 1638 1639static int 1640nfe_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1641{ 1642 struct nfe_softc *sc = ifp->if_softc; 1643 uint32_t r; 1644 int rx_npkts = 0; 1645 1646 NFE_LOCK(sc); 1647 1648 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1649 NFE_UNLOCK(sc); 1650 return (rx_npkts); 1651 } 1652 1653 if (sc->nfe_framesize > MCLBYTES - ETHER_HDR_LEN) 1654 rx_npkts = nfe_jrxeof(sc, count, &rx_npkts); 1655 else 1656 rx_npkts = nfe_rxeof(sc, count, &rx_npkts); 1657 nfe_txeof(sc); 1658 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1659 nfe_start_locked(ifp); 1660 1661 if (cmd == POLL_AND_CHECK_STATUS) { 1662 if ((r = NFE_READ(sc, sc->nfe_irq_status)) == 0) { 1663 NFE_UNLOCK(sc); 1664 return (rx_npkts); 1665 } 1666 NFE_WRITE(sc, sc->nfe_irq_status, r); 1667 1668 if (r & NFE_IRQ_LINK) { 1669 NFE_READ(sc, NFE_PHY_STATUS); 1670 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1671 DPRINTF(sc, "link state changed\n"); 1672 } 1673 } 1674 NFE_UNLOCK(sc); 1675 return (rx_npkts); 1676} 1677#endif /* DEVICE_POLLING */ 1678 1679static void 1680nfe_set_intr(struct nfe_softc *sc) 1681{ 1682 1683 if (sc->nfe_msi != 0) 1684 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1685} 1686 1687 1688/* In MSIX, a write to mask reegisters behaves as XOR. */ 1689static __inline void 1690nfe_enable_intr(struct nfe_softc *sc) 1691{ 1692 1693 if (sc->nfe_msix != 0) { 1694 /* XXX Should have a better way to enable interrupts! */ 1695 if (NFE_READ(sc, sc->nfe_irq_mask) == 0) 1696 NFE_WRITE(sc, sc->nfe_irq_mask, sc->nfe_intrs); 1697 } else 1698 NFE_WRITE(sc, sc->nfe_irq_mask, sc->nfe_intrs); 1699} 1700 1701 1702static __inline void 1703nfe_disable_intr(struct nfe_softc *sc) 1704{ 1705 1706 if (sc->nfe_msix != 0) { 1707 /* XXX Should have a better way to disable interrupts! */ 1708 if (NFE_READ(sc, sc->nfe_irq_mask) != 0) 1709 NFE_WRITE(sc, sc->nfe_irq_mask, sc->nfe_nointrs); 1710 } else 1711 NFE_WRITE(sc, sc->nfe_irq_mask, sc->nfe_nointrs); 1712} 1713 1714 1715static int 1716nfe_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1717{ 1718 struct nfe_softc *sc; 1719 struct ifreq *ifr; 1720 struct mii_data *mii; 1721 int error, init, mask; 1722 1723 sc = ifp->if_softc; 1724 ifr = (struct ifreq *) data; 1725 error = 0; 1726 init = 0; 1727 switch (cmd) { 1728 case SIOCSIFMTU: 1729 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > NFE_JUMBO_MTU) 1730 error = EINVAL; 1731 else if (ifp->if_mtu != ifr->ifr_mtu) { 1732 if ((((sc->nfe_flags & NFE_JUMBO_SUP) == 0) || 1733 (sc->nfe_jumbo_disable != 0)) && 1734 ifr->ifr_mtu > ETHERMTU) 1735 error = EINVAL; 1736 else { 1737 NFE_LOCK(sc); 1738 ifp->if_mtu = ifr->ifr_mtu; 1739 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1740 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1741 nfe_init_locked(sc); 1742 } 1743 NFE_UNLOCK(sc); 1744 } 1745 } 1746 break; 1747 case SIOCSIFFLAGS: 1748 NFE_LOCK(sc); 1749 if (ifp->if_flags & IFF_UP) { 1750 /* 1751 * If only the PROMISC or ALLMULTI flag changes, then 1752 * don't do a full re-init of the chip, just update 1753 * the Rx filter. 1754 */ 1755 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) && 1756 ((ifp->if_flags ^ sc->nfe_if_flags) & 1757 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 1758 nfe_setmulti(sc); 1759 else 1760 nfe_init_locked(sc); 1761 } else { 1762 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1763 nfe_stop(ifp); 1764 } 1765 sc->nfe_if_flags = ifp->if_flags; 1766 NFE_UNLOCK(sc); 1767 error = 0; 1768 break; 1769 case SIOCADDMULTI: 1770 case SIOCDELMULTI: 1771 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1772 NFE_LOCK(sc); 1773 nfe_setmulti(sc); 1774 NFE_UNLOCK(sc); 1775 error = 0; 1776 } 1777 break; 1778 case SIOCSIFMEDIA: 1779 case SIOCGIFMEDIA: 1780 mii = device_get_softc(sc->nfe_miibus); 1781 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1782 break; 1783 case SIOCSIFCAP: 1784 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1785#ifdef DEVICE_POLLING 1786 if ((mask & IFCAP_POLLING) != 0) { 1787 if ((ifr->ifr_reqcap & IFCAP_POLLING) != 0) { 1788 error = ether_poll_register(nfe_poll, ifp); 1789 if (error) 1790 break; 1791 NFE_LOCK(sc); 1792 nfe_disable_intr(sc); 1793 ifp->if_capenable |= IFCAP_POLLING; 1794 NFE_UNLOCK(sc); 1795 } else { 1796 error = ether_poll_deregister(ifp); 1797 /* Enable interrupt even in error case */ 1798 NFE_LOCK(sc); 1799 nfe_enable_intr(sc); 1800 ifp->if_capenable &= ~IFCAP_POLLING; 1801 NFE_UNLOCK(sc); 1802 } 1803 } 1804#endif /* DEVICE_POLLING */ 1805 if ((mask & IFCAP_WOL_MAGIC) != 0 && 1806 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 1807 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 1808 if ((mask & IFCAP_TXCSUM) != 0 && 1809 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 1810 ifp->if_capenable ^= IFCAP_TXCSUM; 1811 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 1812 ifp->if_hwassist |= NFE_CSUM_FEATURES; 1813 else 1814 ifp->if_hwassist &= ~NFE_CSUM_FEATURES; 1815 } 1816 if ((mask & IFCAP_RXCSUM) != 0 && 1817 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 1818 ifp->if_capenable ^= IFCAP_RXCSUM; 1819 init++; 1820 } 1821 if ((mask & IFCAP_TSO4) != 0 && 1822 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 1823 ifp->if_capenable ^= IFCAP_TSO4; 1824 if ((IFCAP_TSO4 & ifp->if_capenable) != 0) 1825 ifp->if_hwassist |= CSUM_TSO; 1826 else 1827 ifp->if_hwassist &= ~CSUM_TSO; 1828 } 1829 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 1830 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 1831 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 1832 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 1833 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 1834 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1835 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 1836 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 1837 init++; 1838 } 1839 /* 1840 * XXX 1841 * It seems that VLAN stripping requires Rx checksum offload. 1842 * Unfortunately FreeBSD has no way to disable only Rx side 1843 * VLAN stripping. So when we know Rx checksum offload is 1844 * disabled turn entire hardware VLAN assist off. 1845 */ 1846 if ((ifp->if_capenable & IFCAP_RXCSUM) == 0) { 1847 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 1848 init++; 1849 ifp->if_capenable &= ~(IFCAP_VLAN_HWTAGGING | 1850 IFCAP_VLAN_HWTSO); 1851 } 1852 if (init > 0 && (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1853 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1854 nfe_init(sc); 1855 } 1856 VLAN_CAPABILITIES(ifp); 1857 break; 1858 default: 1859 error = ether_ioctl(ifp, cmd, data); 1860 break; 1861 } 1862 1863 return (error); 1864} 1865 1866 1867static int 1868nfe_intr(void *arg) 1869{ 1870 struct nfe_softc *sc; 1871 uint32_t status; 1872 1873 sc = (struct nfe_softc *)arg; 1874 1875 status = NFE_READ(sc, sc->nfe_irq_status); 1876 if (status == 0 || status == 0xffffffff) 1877 return (FILTER_STRAY); 1878 nfe_disable_intr(sc); 1879 taskqueue_enqueue_fast(sc->nfe_tq, &sc->nfe_int_task); 1880 1881 return (FILTER_HANDLED); 1882} 1883 1884 1885static void 1886nfe_int_task(void *arg, int pending) 1887{ 1888 struct nfe_softc *sc = arg; 1889 struct ifnet *ifp = sc->nfe_ifp; 1890 uint32_t r; 1891 int domore; 1892 1893 NFE_LOCK(sc); 1894 1895 if ((r = NFE_READ(sc, sc->nfe_irq_status)) == 0) { 1896 nfe_enable_intr(sc); 1897 NFE_UNLOCK(sc); 1898 return; /* not for us */ 1899 } 1900 NFE_WRITE(sc, sc->nfe_irq_status, r); 1901 1902 DPRINTFN(sc, 5, "nfe_intr: interrupt register %x\n", r); 1903 1904#ifdef DEVICE_POLLING 1905 if (ifp->if_capenable & IFCAP_POLLING) { 1906 NFE_UNLOCK(sc); 1907 return; 1908 } 1909#endif 1910 1911 if (r & NFE_IRQ_LINK) { 1912 NFE_READ(sc, NFE_PHY_STATUS); 1913 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1914 DPRINTF(sc, "link state changed\n"); 1915 } 1916 1917 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1918 NFE_UNLOCK(sc); 1919 nfe_disable_intr(sc); 1920 return; 1921 } 1922 1923 domore = 0; 1924 /* check Rx ring */ 1925 if (sc->nfe_framesize > MCLBYTES - ETHER_HDR_LEN) 1926 domore = nfe_jrxeof(sc, sc->nfe_process_limit, NULL); 1927 else 1928 domore = nfe_rxeof(sc, sc->nfe_process_limit, NULL); 1929 /* check Tx ring */ 1930 nfe_txeof(sc); 1931 1932 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1933 nfe_start_locked(ifp); 1934 1935 NFE_UNLOCK(sc); 1936 1937 if (domore || (NFE_READ(sc, sc->nfe_irq_status) != 0)) { 1938 taskqueue_enqueue_fast(sc->nfe_tq, &sc->nfe_int_task); 1939 return; 1940 } 1941 1942 /* Reenable interrupts. */ 1943 nfe_enable_intr(sc); 1944} 1945 1946 1947static __inline void 1948nfe_discard_rxbuf(struct nfe_softc *sc, int idx) 1949{ 1950 struct nfe_desc32 *desc32; 1951 struct nfe_desc64 *desc64; 1952 struct nfe_rx_data *data; 1953 struct mbuf *m; 1954 1955 data = &sc->rxq.data[idx]; 1956 m = data->m; 1957 1958 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1959 desc64 = &sc->rxq.desc64[idx]; 1960 /* VLAN packet may have overwritten it. */ 1961 desc64->physaddr[0] = htole32(NFE_ADDR_HI(data->paddr)); 1962 desc64->physaddr[1] = htole32(NFE_ADDR_LO(data->paddr)); 1963 desc64->length = htole16(m->m_len); 1964 desc64->flags = htole16(NFE_RX_READY); 1965 } else { 1966 desc32 = &sc->rxq.desc32[idx]; 1967 desc32->length = htole16(m->m_len); 1968 desc32->flags = htole16(NFE_RX_READY); 1969 } 1970} 1971 1972 1973static __inline void 1974nfe_discard_jrxbuf(struct nfe_softc *sc, int idx) 1975{ 1976 struct nfe_desc32 *desc32; 1977 struct nfe_desc64 *desc64; 1978 struct nfe_rx_data *data; 1979 struct mbuf *m; 1980 1981 data = &sc->jrxq.jdata[idx]; 1982 m = data->m; 1983 1984 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1985 desc64 = &sc->jrxq.jdesc64[idx]; 1986 /* VLAN packet may have overwritten it. */ 1987 desc64->physaddr[0] = htole32(NFE_ADDR_HI(data->paddr)); 1988 desc64->physaddr[1] = htole32(NFE_ADDR_LO(data->paddr)); 1989 desc64->length = htole16(m->m_len); 1990 desc64->flags = htole16(NFE_RX_READY); 1991 } else { 1992 desc32 = &sc->jrxq.jdesc32[idx]; 1993 desc32->length = htole16(m->m_len); 1994 desc32->flags = htole16(NFE_RX_READY); 1995 } 1996} 1997 1998 1999static int 2000nfe_newbuf(struct nfe_softc *sc, int idx) 2001{ 2002 struct nfe_rx_data *data; 2003 struct nfe_desc32 *desc32; 2004 struct nfe_desc64 *desc64; 2005 struct mbuf *m; 2006 bus_dma_segment_t segs[1]; 2007 bus_dmamap_t map; 2008 int nsegs; 2009 2010 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 2011 if (m == NULL) 2012 return (ENOBUFS); 2013 2014 m->m_len = m->m_pkthdr.len = MCLBYTES; 2015 m_adj(m, ETHER_ALIGN); 2016 2017 if (bus_dmamap_load_mbuf_sg(sc->rxq.rx_data_tag, sc->rxq.rx_spare_map, 2018 m, segs, &nsegs, BUS_DMA_NOWAIT) != 0) { 2019 m_freem(m); 2020 return (ENOBUFS); 2021 } 2022 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 2023 2024 data = &sc->rxq.data[idx]; 2025 if (data->m != NULL) { 2026 bus_dmamap_sync(sc->rxq.rx_data_tag, data->rx_data_map, 2027 BUS_DMASYNC_POSTREAD); 2028 bus_dmamap_unload(sc->rxq.rx_data_tag, data->rx_data_map); 2029 } 2030 map = data->rx_data_map; 2031 data->rx_data_map = sc->rxq.rx_spare_map; 2032 sc->rxq.rx_spare_map = map; 2033 bus_dmamap_sync(sc->rxq.rx_data_tag, data->rx_data_map, 2034 BUS_DMASYNC_PREREAD); 2035 data->paddr = segs[0].ds_addr; 2036 data->m = m; 2037 /* update mapping address in h/w descriptor */ 2038 if (sc->nfe_flags & NFE_40BIT_ADDR) { 2039 desc64 = &sc->rxq.desc64[idx]; 2040 desc64->physaddr[0] = htole32(NFE_ADDR_HI(segs[0].ds_addr)); 2041 desc64->physaddr[1] = htole32(NFE_ADDR_LO(segs[0].ds_addr)); 2042 desc64->length = htole16(segs[0].ds_len); 2043 desc64->flags = htole16(NFE_RX_READY); 2044 } else { 2045 desc32 = &sc->rxq.desc32[idx]; 2046 desc32->physaddr = htole32(NFE_ADDR_LO(segs[0].ds_addr)); 2047 desc32->length = htole16(segs[0].ds_len); 2048 desc32->flags = htole16(NFE_RX_READY); 2049 } 2050 2051 return (0); 2052} 2053 2054 2055static int 2056nfe_jnewbuf(struct nfe_softc *sc, int idx) 2057{ 2058 struct nfe_rx_data *data; 2059 struct nfe_desc32 *desc32; 2060 struct nfe_desc64 *desc64; 2061 struct mbuf *m; 2062 bus_dma_segment_t segs[1]; 2063 bus_dmamap_t map; 2064 int nsegs; 2065 2066 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 2067 if (m == NULL) 2068 return (ENOBUFS); 2069 if ((m->m_flags & M_EXT) == 0) { 2070 m_freem(m); 2071 return (ENOBUFS); 2072 } 2073 m->m_pkthdr.len = m->m_len = MJUM9BYTES; 2074 m_adj(m, ETHER_ALIGN); 2075 2076 if (bus_dmamap_load_mbuf_sg(sc->jrxq.jrx_data_tag, 2077 sc->jrxq.jrx_spare_map, m, segs, &nsegs, BUS_DMA_NOWAIT) != 0) { 2078 m_freem(m); 2079 return (ENOBUFS); 2080 } 2081 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 2082 2083 data = &sc->jrxq.jdata[idx]; 2084 if (data->m != NULL) { 2085 bus_dmamap_sync(sc->jrxq.jrx_data_tag, data->rx_data_map, 2086 BUS_DMASYNC_POSTREAD); 2087 bus_dmamap_unload(sc->jrxq.jrx_data_tag, data->rx_data_map); 2088 } 2089 map = data->rx_data_map; 2090 data->rx_data_map = sc->jrxq.jrx_spare_map; 2091 sc->jrxq.jrx_spare_map = map; 2092 bus_dmamap_sync(sc->jrxq.jrx_data_tag, data->rx_data_map, 2093 BUS_DMASYNC_PREREAD); 2094 data->paddr = segs[0].ds_addr; 2095 data->m = m; 2096 /* update mapping address in h/w descriptor */ 2097 if (sc->nfe_flags & NFE_40BIT_ADDR) { 2098 desc64 = &sc->jrxq.jdesc64[idx]; 2099 desc64->physaddr[0] = htole32(NFE_ADDR_HI(segs[0].ds_addr)); 2100 desc64->physaddr[1] = htole32(NFE_ADDR_LO(segs[0].ds_addr)); 2101 desc64->length = htole16(segs[0].ds_len); 2102 desc64->flags = htole16(NFE_RX_READY); 2103 } else { 2104 desc32 = &sc->jrxq.jdesc32[idx]; 2105 desc32->physaddr = htole32(NFE_ADDR_LO(segs[0].ds_addr)); 2106 desc32->length = htole16(segs[0].ds_len); 2107 desc32->flags = htole16(NFE_RX_READY); 2108 } 2109 2110 return (0); 2111} 2112 2113 2114static int 2115nfe_rxeof(struct nfe_softc *sc, int count, int *rx_npktsp) 2116{ 2117 struct ifnet *ifp = sc->nfe_ifp; 2118 struct nfe_desc32 *desc32; 2119 struct nfe_desc64 *desc64; 2120 struct nfe_rx_data *data; 2121 struct mbuf *m; 2122 uint16_t flags; 2123 int len, prog, rx_npkts; 2124 uint32_t vtag = 0; 2125 2126 rx_npkts = 0; 2127 NFE_LOCK_ASSERT(sc); 2128 2129 bus_dmamap_sync(sc->rxq.rx_desc_tag, sc->rxq.rx_desc_map, 2130 BUS_DMASYNC_POSTREAD); 2131 2132 for (prog = 0;;NFE_INC(sc->rxq.cur, NFE_RX_RING_COUNT), vtag = 0) { 2133 if (count <= 0) 2134 break; 2135 count--; 2136 2137 data = &sc->rxq.data[sc->rxq.cur]; 2138 2139 if (sc->nfe_flags & NFE_40BIT_ADDR) { 2140 desc64 = &sc->rxq.desc64[sc->rxq.cur]; 2141 vtag = le32toh(desc64->physaddr[1]); 2142 flags = le16toh(desc64->flags); 2143 len = le16toh(desc64->length) & NFE_RX_LEN_MASK; 2144 } else { 2145 desc32 = &sc->rxq.desc32[sc->rxq.cur]; 2146 flags = le16toh(desc32->flags); 2147 len = le16toh(desc32->length) & NFE_RX_LEN_MASK; 2148 } 2149 2150 if (flags & NFE_RX_READY) 2151 break; 2152 prog++; 2153 if ((sc->nfe_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 2154 if (!(flags & NFE_RX_VALID_V1)) { 2155 ifp->if_ierrors++; 2156 nfe_discard_rxbuf(sc, sc->rxq.cur); 2157 continue; 2158 } 2159 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) { 2160 flags &= ~NFE_RX_ERROR; 2161 len--; /* fix buffer length */ 2162 } 2163 } else { 2164 if (!(flags & NFE_RX_VALID_V2)) { 2165 ifp->if_ierrors++; 2166 nfe_discard_rxbuf(sc, sc->rxq.cur); 2167 continue; 2168 } 2169 2170 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) { 2171 flags &= ~NFE_RX_ERROR; 2172 len--; /* fix buffer length */ 2173 } 2174 } 2175 2176 if (flags & NFE_RX_ERROR) { 2177 ifp->if_ierrors++; 2178 nfe_discard_rxbuf(sc, sc->rxq.cur); 2179 continue; 2180 } 2181 2182 m = data->m; 2183 if (nfe_newbuf(sc, sc->rxq.cur) != 0) { 2184 ifp->if_iqdrops++; 2185 nfe_discard_rxbuf(sc, sc->rxq.cur); 2186 continue; 2187 } 2188 2189 if ((vtag & NFE_RX_VTAG) != 0 && 2190 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 2191 m->m_pkthdr.ether_vtag = vtag & 0xffff; 2192 m->m_flags |= M_VLANTAG; 2193 } 2194 2195 m->m_pkthdr.len = m->m_len = len; 2196 m->m_pkthdr.rcvif = ifp; 2197 2198 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) { 2199 if ((flags & NFE_RX_IP_CSUMOK) != 0) { 2200 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2201 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2202 if ((flags & NFE_RX_TCP_CSUMOK) != 0 || 2203 (flags & NFE_RX_UDP_CSUMOK) != 0) { 2204 m->m_pkthdr.csum_flags |= 2205 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2206 m->m_pkthdr.csum_data = 0xffff; 2207 } 2208 } 2209 } 2210 2211 ifp->if_ipackets++; 2212 2213 NFE_UNLOCK(sc); 2214 (*ifp->if_input)(ifp, m); 2215 NFE_LOCK(sc); 2216 rx_npkts++; 2217 } 2218 2219 if (prog > 0) 2220 bus_dmamap_sync(sc->rxq.rx_desc_tag, sc->rxq.rx_desc_map, 2221 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2222 2223 if (rx_npktsp != NULL) 2224 *rx_npktsp = rx_npkts; 2225 return (count > 0 ? 0 : EAGAIN); 2226} 2227 2228 2229static int 2230nfe_jrxeof(struct nfe_softc *sc, int count, int *rx_npktsp) 2231{ 2232 struct ifnet *ifp = sc->nfe_ifp; 2233 struct nfe_desc32 *desc32; 2234 struct nfe_desc64 *desc64; 2235 struct nfe_rx_data *data; 2236 struct mbuf *m; 2237 uint16_t flags; 2238 int len, prog, rx_npkts; 2239 uint32_t vtag = 0; 2240 2241 rx_npkts = 0; 2242 NFE_LOCK_ASSERT(sc); 2243 2244 bus_dmamap_sync(sc->jrxq.jrx_desc_tag, sc->jrxq.jrx_desc_map, 2245 BUS_DMASYNC_POSTREAD); 2246 2247 for (prog = 0;;NFE_INC(sc->jrxq.jcur, NFE_JUMBO_RX_RING_COUNT), 2248 vtag = 0) { 2249 if (count <= 0) 2250 break; 2251 count--; 2252 2253 data = &sc->jrxq.jdata[sc->jrxq.jcur]; 2254 2255 if (sc->nfe_flags & NFE_40BIT_ADDR) { 2256 desc64 = &sc->jrxq.jdesc64[sc->jrxq.jcur]; 2257 vtag = le32toh(desc64->physaddr[1]); 2258 flags = le16toh(desc64->flags); 2259 len = le16toh(desc64->length) & NFE_RX_LEN_MASK; 2260 } else { 2261 desc32 = &sc->jrxq.jdesc32[sc->jrxq.jcur]; 2262 flags = le16toh(desc32->flags); 2263 len = le16toh(desc32->length) & NFE_RX_LEN_MASK; 2264 } 2265 2266 if (flags & NFE_RX_READY) 2267 break; 2268 prog++; 2269 if ((sc->nfe_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 2270 if (!(flags & NFE_RX_VALID_V1)) { 2271 ifp->if_ierrors++; 2272 nfe_discard_jrxbuf(sc, sc->jrxq.jcur); 2273 continue; 2274 } 2275 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) { 2276 flags &= ~NFE_RX_ERROR; 2277 len--; /* fix buffer length */ 2278 } 2279 } else { 2280 if (!(flags & NFE_RX_VALID_V2)) { 2281 ifp->if_ierrors++; 2282 nfe_discard_jrxbuf(sc, sc->jrxq.jcur); 2283 continue; 2284 } 2285 2286 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) { 2287 flags &= ~NFE_RX_ERROR; 2288 len--; /* fix buffer length */ 2289 } 2290 } 2291 2292 if (flags & NFE_RX_ERROR) { 2293 ifp->if_ierrors++; 2294 nfe_discard_jrxbuf(sc, sc->jrxq.jcur); 2295 continue; 2296 } 2297 2298 m = data->m; 2299 if (nfe_jnewbuf(sc, sc->jrxq.jcur) != 0) { 2300 ifp->if_iqdrops++; 2301 nfe_discard_jrxbuf(sc, sc->jrxq.jcur); 2302 continue; 2303 } 2304 2305 if ((vtag & NFE_RX_VTAG) != 0 && 2306 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 2307 m->m_pkthdr.ether_vtag = vtag & 0xffff; 2308 m->m_flags |= M_VLANTAG; 2309 } 2310 2311 m->m_pkthdr.len = m->m_len = len; 2312 m->m_pkthdr.rcvif = ifp; 2313 2314 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) { 2315 if ((flags & NFE_RX_IP_CSUMOK) != 0) { 2316 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2317 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2318 if ((flags & NFE_RX_TCP_CSUMOK) != 0 || 2319 (flags & NFE_RX_UDP_CSUMOK) != 0) { 2320 m->m_pkthdr.csum_flags |= 2321 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2322 m->m_pkthdr.csum_data = 0xffff; 2323 } 2324 } 2325 } 2326 2327 ifp->if_ipackets++; 2328 2329 NFE_UNLOCK(sc); 2330 (*ifp->if_input)(ifp, m); 2331 NFE_LOCK(sc); 2332 rx_npkts++; 2333 } 2334 2335 if (prog > 0) 2336 bus_dmamap_sync(sc->jrxq.jrx_desc_tag, sc->jrxq.jrx_desc_map, 2337 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2338 2339 if (rx_npktsp != NULL) 2340 *rx_npktsp = rx_npkts; 2341 return (count > 0 ? 0 : EAGAIN); 2342} 2343 2344 2345static void 2346nfe_txeof(struct nfe_softc *sc) 2347{ 2348 struct ifnet *ifp = sc->nfe_ifp; 2349 struct nfe_desc32 *desc32; 2350 struct nfe_desc64 *desc64; 2351 struct nfe_tx_data *data = NULL; 2352 uint16_t flags; 2353 int cons, prog; 2354 2355 NFE_LOCK_ASSERT(sc); 2356 2357 bus_dmamap_sync(sc->txq.tx_desc_tag, sc->txq.tx_desc_map, 2358 BUS_DMASYNC_POSTREAD); 2359 2360 prog = 0; 2361 for (cons = sc->txq.next; cons != sc->txq.cur; 2362 NFE_INC(cons, NFE_TX_RING_COUNT)) { 2363 if (sc->nfe_flags & NFE_40BIT_ADDR) { 2364 desc64 = &sc->txq.desc64[cons]; 2365 flags = le16toh(desc64->flags); 2366 } else { 2367 desc32 = &sc->txq.desc32[cons]; 2368 flags = le16toh(desc32->flags); 2369 } 2370 2371 if (flags & NFE_TX_VALID) 2372 break; 2373 2374 prog++; 2375 sc->txq.queued--; 2376 data = &sc->txq.data[cons]; 2377 2378 if ((sc->nfe_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 2379 if ((flags & NFE_TX_LASTFRAG_V1) == 0) 2380 continue; 2381 if ((flags & NFE_TX_ERROR_V1) != 0) { 2382 device_printf(sc->nfe_dev, 2383 "tx v1 error 0x%4b\n", flags, NFE_V1_TXERR); 2384 2385 ifp->if_oerrors++; 2386 } else 2387 ifp->if_opackets++; 2388 } else { 2389 if ((flags & NFE_TX_LASTFRAG_V2) == 0) 2390 continue; 2391 if ((flags & NFE_TX_ERROR_V2) != 0) { 2392 device_printf(sc->nfe_dev, 2393 "tx v2 error 0x%4b\n", flags, NFE_V2_TXERR); 2394 ifp->if_oerrors++; 2395 } else 2396 ifp->if_opackets++; 2397 } 2398 2399 /* last fragment of the mbuf chain transmitted */ 2400 KASSERT(data->m != NULL, ("%s: freeing NULL mbuf!", __func__)); 2401 bus_dmamap_sync(sc->txq.tx_data_tag, data->tx_data_map, 2402 BUS_DMASYNC_POSTWRITE); 2403 bus_dmamap_unload(sc->txq.tx_data_tag, data->tx_data_map); 2404 m_freem(data->m); 2405 data->m = NULL; 2406 } 2407 2408 if (prog > 0) { 2409 sc->nfe_force_tx = 0; 2410 sc->txq.next = cons; 2411 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2412 if (sc->txq.queued == 0) 2413 sc->nfe_watchdog_timer = 0; 2414 } 2415} 2416 2417static int 2418nfe_encap(struct nfe_softc *sc, struct mbuf **m_head) 2419{ 2420 struct nfe_desc32 *desc32 = NULL; 2421 struct nfe_desc64 *desc64 = NULL; 2422 bus_dmamap_t map; 2423 bus_dma_segment_t segs[NFE_MAX_SCATTER]; 2424 int error, i, nsegs, prod, si; 2425 uint32_t tsosegsz; 2426 uint16_t cflags, flags; 2427 struct mbuf *m; 2428 2429 prod = si = sc->txq.cur; 2430 map = sc->txq.data[prod].tx_data_map; 2431 2432 error = bus_dmamap_load_mbuf_sg(sc->txq.tx_data_tag, map, *m_head, segs, 2433 &nsegs, BUS_DMA_NOWAIT); 2434 if (error == EFBIG) { 2435 m = m_collapse(*m_head, M_NOWAIT, NFE_MAX_SCATTER); 2436 if (m == NULL) { 2437 m_freem(*m_head); 2438 *m_head = NULL; 2439 return (ENOBUFS); 2440 } 2441 *m_head = m; 2442 error = bus_dmamap_load_mbuf_sg(sc->txq.tx_data_tag, map, 2443 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2444 if (error != 0) { 2445 m_freem(*m_head); 2446 *m_head = NULL; 2447 return (ENOBUFS); 2448 } 2449 } else if (error != 0) 2450 return (error); 2451 if (nsegs == 0) { 2452 m_freem(*m_head); 2453 *m_head = NULL; 2454 return (EIO); 2455 } 2456 2457 if (sc->txq.queued + nsegs >= NFE_TX_RING_COUNT - 2) { 2458 bus_dmamap_unload(sc->txq.tx_data_tag, map); 2459 return (ENOBUFS); 2460 } 2461 2462 m = *m_head; 2463 cflags = flags = 0; 2464 tsosegsz = 0; 2465 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2466 tsosegsz = (uint32_t)m->m_pkthdr.tso_segsz << 2467 NFE_TX_TSO_SHIFT; 2468 cflags &= ~(NFE_TX_IP_CSUM | NFE_TX_TCP_UDP_CSUM); 2469 cflags |= NFE_TX_TSO; 2470 } else if ((m->m_pkthdr.csum_flags & NFE_CSUM_FEATURES) != 0) { 2471 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 2472 cflags |= NFE_TX_IP_CSUM; 2473 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 2474 cflags |= NFE_TX_TCP_UDP_CSUM; 2475 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2476 cflags |= NFE_TX_TCP_UDP_CSUM; 2477 } 2478 2479 for (i = 0; i < nsegs; i++) { 2480 if (sc->nfe_flags & NFE_40BIT_ADDR) { 2481 desc64 = &sc->txq.desc64[prod]; 2482 desc64->physaddr[0] = 2483 htole32(NFE_ADDR_HI(segs[i].ds_addr)); 2484 desc64->physaddr[1] = 2485 htole32(NFE_ADDR_LO(segs[i].ds_addr)); 2486 desc64->vtag = 0; 2487 desc64->length = htole16(segs[i].ds_len - 1); 2488 desc64->flags = htole16(flags); 2489 } else { 2490 desc32 = &sc->txq.desc32[prod]; 2491 desc32->physaddr = 2492 htole32(NFE_ADDR_LO(segs[i].ds_addr)); 2493 desc32->length = htole16(segs[i].ds_len - 1); 2494 desc32->flags = htole16(flags); 2495 } 2496 2497 /* 2498 * Setting of the valid bit in the first descriptor is 2499 * deferred until the whole chain is fully setup. 2500 */ 2501 flags |= NFE_TX_VALID; 2502 2503 sc->txq.queued++; 2504 NFE_INC(prod, NFE_TX_RING_COUNT); 2505 } 2506 2507 /* 2508 * the whole mbuf chain has been DMA mapped, fix last/first descriptor. 2509 * csum flags, vtag and TSO belong to the first fragment only. 2510 */ 2511 if (sc->nfe_flags & NFE_40BIT_ADDR) { 2512 desc64->flags |= htole16(NFE_TX_LASTFRAG_V2); 2513 desc64 = &sc->txq.desc64[si]; 2514 if ((m->m_flags & M_VLANTAG) != 0) 2515 desc64->vtag = htole32(NFE_TX_VTAG | 2516 m->m_pkthdr.ether_vtag); 2517 if (tsosegsz != 0) { 2518 /* 2519 * XXX 2520 * The following indicates the descriptor element 2521 * is a 32bit quantity. 2522 */ 2523 desc64->length |= htole16((uint16_t)tsosegsz); 2524 desc64->flags |= htole16(tsosegsz >> 16); 2525 } 2526 /* 2527 * finally, set the valid/checksum/TSO bit in the first 2528 * descriptor. 2529 */ 2530 desc64->flags |= htole16(NFE_TX_VALID | cflags); 2531 } else { 2532 if (sc->nfe_flags & NFE_JUMBO_SUP) 2533 desc32->flags |= htole16(NFE_TX_LASTFRAG_V2); 2534 else 2535 desc32->flags |= htole16(NFE_TX_LASTFRAG_V1); 2536 desc32 = &sc->txq.desc32[si]; 2537 if (tsosegsz != 0) { 2538 /* 2539 * XXX 2540 * The following indicates the descriptor element 2541 * is a 32bit quantity. 2542 */ 2543 desc32->length |= htole16((uint16_t)tsosegsz); 2544 desc32->flags |= htole16(tsosegsz >> 16); 2545 } 2546 /* 2547 * finally, set the valid/checksum/TSO bit in the first 2548 * descriptor. 2549 */ 2550 desc32->flags |= htole16(NFE_TX_VALID | cflags); 2551 } 2552 2553 sc->txq.cur = prod; 2554 prod = (prod + NFE_TX_RING_COUNT - 1) % NFE_TX_RING_COUNT; 2555 sc->txq.data[si].tx_data_map = sc->txq.data[prod].tx_data_map; 2556 sc->txq.data[prod].tx_data_map = map; 2557 sc->txq.data[prod].m = m; 2558 2559 bus_dmamap_sync(sc->txq.tx_data_tag, map, BUS_DMASYNC_PREWRITE); 2560 2561 return (0); 2562} 2563 2564 2565static void 2566nfe_setmulti(struct nfe_softc *sc) 2567{ 2568 struct ifnet *ifp = sc->nfe_ifp; 2569 struct ifmultiaddr *ifma; 2570 int i; 2571 uint32_t filter; 2572 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN]; 2573 uint8_t etherbroadcastaddr[ETHER_ADDR_LEN] = { 2574 0xff, 0xff, 0xff, 0xff, 0xff, 0xff 2575 }; 2576 2577 NFE_LOCK_ASSERT(sc); 2578 2579 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 2580 bzero(addr, ETHER_ADDR_LEN); 2581 bzero(mask, ETHER_ADDR_LEN); 2582 goto done; 2583 } 2584 2585 bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN); 2586 bcopy(etherbroadcastaddr, mask, ETHER_ADDR_LEN); 2587 2588 if_maddr_rlock(ifp); 2589 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2590 u_char *addrp; 2591 2592 if (ifma->ifma_addr->sa_family != AF_LINK) 2593 continue; 2594 2595 addrp = LLADDR((struct sockaddr_dl *) ifma->ifma_addr); 2596 for (i = 0; i < ETHER_ADDR_LEN; i++) { 2597 u_int8_t mcaddr = addrp[i]; 2598 addr[i] &= mcaddr; 2599 mask[i] &= ~mcaddr; 2600 } 2601 } 2602 if_maddr_runlock(ifp); 2603 2604 for (i = 0; i < ETHER_ADDR_LEN; i++) { 2605 mask[i] |= addr[i]; 2606 } 2607 2608done: 2609 addr[0] |= 0x01; /* make sure multicast bit is set */ 2610 2611 NFE_WRITE(sc, NFE_MULTIADDR_HI, 2612 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 2613 NFE_WRITE(sc, NFE_MULTIADDR_LO, 2614 addr[5] << 8 | addr[4]); 2615 NFE_WRITE(sc, NFE_MULTIMASK_HI, 2616 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]); 2617 NFE_WRITE(sc, NFE_MULTIMASK_LO, 2618 mask[5] << 8 | mask[4]); 2619 2620 filter = NFE_READ(sc, NFE_RXFILTER); 2621 filter &= NFE_PFF_RX_PAUSE; 2622 filter |= NFE_RXFILTER_MAGIC; 2623 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PFF_PROMISC : NFE_PFF_U2M; 2624 NFE_WRITE(sc, NFE_RXFILTER, filter); 2625} 2626 2627 2628static void 2629nfe_start(struct ifnet *ifp) 2630{ 2631 struct nfe_softc *sc = ifp->if_softc; 2632 2633 NFE_LOCK(sc); 2634 nfe_start_locked(ifp); 2635 NFE_UNLOCK(sc); 2636} 2637 2638static void 2639nfe_start_locked(struct ifnet *ifp) 2640{ 2641 struct nfe_softc *sc = ifp->if_softc; 2642 struct mbuf *m0; 2643 int enq; 2644 2645 NFE_LOCK_ASSERT(sc); 2646 2647 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2648 IFF_DRV_RUNNING || sc->nfe_link == 0) 2649 return; 2650 2651 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) { 2652 IFQ_DRV_DEQUEUE(&ifp->if_snd, m0); 2653 if (m0 == NULL) 2654 break; 2655 2656 if (nfe_encap(sc, &m0) != 0) { 2657 if (m0 == NULL) 2658 break; 2659 IFQ_DRV_PREPEND(&ifp->if_snd, m0); 2660 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2661 break; 2662 } 2663 enq++; 2664 ETHER_BPF_MTAP(ifp, m0); 2665 } 2666 2667 if (enq > 0) { 2668 bus_dmamap_sync(sc->txq.tx_desc_tag, sc->txq.tx_desc_map, 2669 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2670 2671 /* kick Tx */ 2672 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl); 2673 2674 /* 2675 * Set a timeout in case the chip goes out to lunch. 2676 */ 2677 sc->nfe_watchdog_timer = 5; 2678 } 2679} 2680 2681 2682static void 2683nfe_watchdog(struct ifnet *ifp) 2684{ 2685 struct nfe_softc *sc = ifp->if_softc; 2686 2687 if (sc->nfe_watchdog_timer == 0 || --sc->nfe_watchdog_timer) 2688 return; 2689 2690 /* Check if we've lost Tx completion interrupt. */ 2691 nfe_txeof(sc); 2692 if (sc->txq.queued == 0) { 2693 if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 2694 "-- recovering\n"); 2695 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2696 nfe_start_locked(ifp); 2697 return; 2698 } 2699 /* Check if we've lost start Tx command. */ 2700 sc->nfe_force_tx++; 2701 if (sc->nfe_force_tx <= 3) { 2702 /* 2703 * If this is the case for watchdog timeout, the following 2704 * code should go to nfe_txeof(). 2705 */ 2706 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl); 2707 return; 2708 } 2709 sc->nfe_force_tx = 0; 2710 2711 if_printf(ifp, "watchdog timeout\n"); 2712 2713 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2714 ifp->if_oerrors++; 2715 nfe_init_locked(sc); 2716} 2717 2718 2719static void 2720nfe_init(void *xsc) 2721{ 2722 struct nfe_softc *sc = xsc; 2723 2724 NFE_LOCK(sc); 2725 nfe_init_locked(sc); 2726 NFE_UNLOCK(sc); 2727} 2728 2729 2730static void 2731nfe_init_locked(void *xsc) 2732{ 2733 struct nfe_softc *sc = xsc; 2734 struct ifnet *ifp = sc->nfe_ifp; 2735 struct mii_data *mii; 2736 uint32_t val; 2737 int error; 2738 2739 NFE_LOCK_ASSERT(sc); 2740 2741 mii = device_get_softc(sc->nfe_miibus); 2742 2743 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2744 return; 2745 2746 nfe_stop(ifp); 2747 2748 sc->nfe_framesize = ifp->if_mtu + NFE_RX_HEADERS; 2749 2750 nfe_init_tx_ring(sc, &sc->txq); 2751 if (sc->nfe_framesize > (MCLBYTES - ETHER_HDR_LEN)) 2752 error = nfe_init_jrx_ring(sc, &sc->jrxq); 2753 else 2754 error = nfe_init_rx_ring(sc, &sc->rxq); 2755 if (error != 0) { 2756 device_printf(sc->nfe_dev, 2757 "initialization failed: no memory for rx buffers\n"); 2758 nfe_stop(ifp); 2759 return; 2760 } 2761 2762 val = 0; 2763 if ((sc->nfe_flags & NFE_CORRECT_MACADDR) != 0) 2764 val |= NFE_MAC_ADDR_INORDER; 2765 NFE_WRITE(sc, NFE_TX_UNK, val); 2766 NFE_WRITE(sc, NFE_STATUS, 0); 2767 2768 if ((sc->nfe_flags & NFE_TX_FLOW_CTRL) != 0) 2769 NFE_WRITE(sc, NFE_TX_PAUSE_FRAME, NFE_TX_PAUSE_FRAME_DISABLE); 2770 2771 sc->rxtxctl = NFE_RXTX_BIT2; 2772 if (sc->nfe_flags & NFE_40BIT_ADDR) 2773 sc->rxtxctl |= NFE_RXTX_V3MAGIC; 2774 else if (sc->nfe_flags & NFE_JUMBO_SUP) 2775 sc->rxtxctl |= NFE_RXTX_V2MAGIC; 2776 2777 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2778 sc->rxtxctl |= NFE_RXTX_RXCSUM; 2779 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2780 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT | NFE_RXTX_VTAG_STRIP; 2781 2782 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl); 2783 DELAY(10); 2784 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 2785 2786 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2787 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE); 2788 else 2789 NFE_WRITE(sc, NFE_VTAG_CTL, 0); 2790 2791 NFE_WRITE(sc, NFE_SETUP_R6, 0); 2792 2793 /* set MAC address */ 2794 nfe_set_macaddr(sc, IF_LLADDR(ifp)); 2795 2796 /* tell MAC where rings are in memory */ 2797 if (sc->nfe_framesize > MCLBYTES - ETHER_HDR_LEN) { 2798 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, 2799 NFE_ADDR_HI(sc->jrxq.jphysaddr)); 2800 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, 2801 NFE_ADDR_LO(sc->jrxq.jphysaddr)); 2802 } else { 2803 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, 2804 NFE_ADDR_HI(sc->rxq.physaddr)); 2805 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, 2806 NFE_ADDR_LO(sc->rxq.physaddr)); 2807 } 2808 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, NFE_ADDR_HI(sc->txq.physaddr)); 2809 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, NFE_ADDR_LO(sc->txq.physaddr)); 2810 2811 NFE_WRITE(sc, NFE_RING_SIZE, 2812 (NFE_RX_RING_COUNT - 1) << 16 | 2813 (NFE_TX_RING_COUNT - 1)); 2814 2815 NFE_WRITE(sc, NFE_RXBUFSZ, sc->nfe_framesize); 2816 2817 /* force MAC to wakeup */ 2818 val = NFE_READ(sc, NFE_PWR_STATE); 2819 if ((val & NFE_PWR_WAKEUP) == 0) 2820 NFE_WRITE(sc, NFE_PWR_STATE, val | NFE_PWR_WAKEUP); 2821 DELAY(10); 2822 val = NFE_READ(sc, NFE_PWR_STATE); 2823 NFE_WRITE(sc, NFE_PWR_STATE, val | NFE_PWR_VALID); 2824 2825#if 1 2826 /* configure interrupts coalescing/mitigation */ 2827 NFE_WRITE(sc, NFE_IMTIMER, NFE_IM_DEFAULT); 2828#else 2829 /* no interrupt mitigation: one interrupt per packet */ 2830 NFE_WRITE(sc, NFE_IMTIMER, 970); 2831#endif 2832 2833 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC_10_100); 2834 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC); 2835 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC); 2836 2837 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */ 2838 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC); 2839 2840 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC); 2841 /* Disable WOL. */ 2842 NFE_WRITE(sc, NFE_WOL_CTL, 0); 2843 2844 sc->rxtxctl &= ~NFE_RXTX_BIT2; 2845 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 2846 DELAY(10); 2847 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl); 2848 2849 /* set Rx filter */ 2850 nfe_setmulti(sc); 2851 2852 /* enable Rx */ 2853 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START); 2854 2855 /* enable Tx */ 2856 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START); 2857 2858 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 2859 2860 /* Clear hardware stats. */ 2861 nfe_stats_clear(sc); 2862 2863#ifdef DEVICE_POLLING 2864 if (ifp->if_capenable & IFCAP_POLLING) 2865 nfe_disable_intr(sc); 2866 else 2867#endif 2868 nfe_set_intr(sc); 2869 nfe_enable_intr(sc); /* enable interrupts */ 2870 2871 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2872 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2873 2874 sc->nfe_link = 0; 2875 mii_mediachg(mii); 2876 2877 callout_reset(&sc->nfe_stat_ch, hz, nfe_tick, sc); 2878} 2879 2880 2881static void 2882nfe_stop(struct ifnet *ifp) 2883{ 2884 struct nfe_softc *sc = ifp->if_softc; 2885 struct nfe_rx_ring *rx_ring; 2886 struct nfe_jrx_ring *jrx_ring; 2887 struct nfe_tx_ring *tx_ring; 2888 struct nfe_rx_data *rdata; 2889 struct nfe_tx_data *tdata; 2890 int i; 2891 2892 NFE_LOCK_ASSERT(sc); 2893 2894 sc->nfe_watchdog_timer = 0; 2895 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2896 2897 callout_stop(&sc->nfe_stat_ch); 2898 2899 /* abort Tx */ 2900 NFE_WRITE(sc, NFE_TX_CTL, 0); 2901 2902 /* disable Rx */ 2903 NFE_WRITE(sc, NFE_RX_CTL, 0); 2904 2905 /* disable interrupts */ 2906 nfe_disable_intr(sc); 2907 2908 sc->nfe_link = 0; 2909 2910 /* free Rx and Tx mbufs still in the queues. */ 2911 rx_ring = &sc->rxq; 2912 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 2913 rdata = &rx_ring->data[i]; 2914 if (rdata->m != NULL) { 2915 bus_dmamap_sync(rx_ring->rx_data_tag, 2916 rdata->rx_data_map, BUS_DMASYNC_POSTREAD); 2917 bus_dmamap_unload(rx_ring->rx_data_tag, 2918 rdata->rx_data_map); 2919 m_freem(rdata->m); 2920 rdata->m = NULL; 2921 } 2922 } 2923 2924 if ((sc->nfe_flags & NFE_JUMBO_SUP) != 0) { 2925 jrx_ring = &sc->jrxq; 2926 for (i = 0; i < NFE_JUMBO_RX_RING_COUNT; i++) { 2927 rdata = &jrx_ring->jdata[i]; 2928 if (rdata->m != NULL) { 2929 bus_dmamap_sync(jrx_ring->jrx_data_tag, 2930 rdata->rx_data_map, BUS_DMASYNC_POSTREAD); 2931 bus_dmamap_unload(jrx_ring->jrx_data_tag, 2932 rdata->rx_data_map); 2933 m_freem(rdata->m); 2934 rdata->m = NULL; 2935 } 2936 } 2937 } 2938 2939 tx_ring = &sc->txq; 2940 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 2941 tdata = &tx_ring->data[i]; 2942 if (tdata->m != NULL) { 2943 bus_dmamap_sync(tx_ring->tx_data_tag, 2944 tdata->tx_data_map, BUS_DMASYNC_POSTWRITE); 2945 bus_dmamap_unload(tx_ring->tx_data_tag, 2946 tdata->tx_data_map); 2947 m_freem(tdata->m); 2948 tdata->m = NULL; 2949 } 2950 } 2951 /* Update hardware stats. */ 2952 nfe_stats_update(sc); 2953} 2954 2955 2956static int 2957nfe_ifmedia_upd(struct ifnet *ifp) 2958{ 2959 struct nfe_softc *sc = ifp->if_softc; 2960 struct mii_data *mii; 2961 2962 NFE_LOCK(sc); 2963 mii = device_get_softc(sc->nfe_miibus); 2964 mii_mediachg(mii); 2965 NFE_UNLOCK(sc); 2966 2967 return (0); 2968} 2969 2970 2971static void 2972nfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2973{ 2974 struct nfe_softc *sc; 2975 struct mii_data *mii; 2976 2977 sc = ifp->if_softc; 2978 2979 NFE_LOCK(sc); 2980 mii = device_get_softc(sc->nfe_miibus); 2981 mii_pollstat(mii); 2982 2983 ifmr->ifm_active = mii->mii_media_active; 2984 ifmr->ifm_status = mii->mii_media_status; 2985 NFE_UNLOCK(sc); 2986} 2987 2988 2989void 2990nfe_tick(void *xsc) 2991{ 2992 struct nfe_softc *sc; 2993 struct mii_data *mii; 2994 struct ifnet *ifp; 2995 2996 sc = (struct nfe_softc *)xsc; 2997 2998 NFE_LOCK_ASSERT(sc); 2999 3000 ifp = sc->nfe_ifp; 3001 3002 mii = device_get_softc(sc->nfe_miibus); 3003 mii_tick(mii); 3004 nfe_stats_update(sc); 3005 nfe_watchdog(ifp); 3006 callout_reset(&sc->nfe_stat_ch, hz, nfe_tick, sc); 3007} 3008 3009 3010static int 3011nfe_shutdown(device_t dev) 3012{ 3013 3014 return (nfe_suspend(dev)); 3015} 3016 3017 3018static void 3019nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr) 3020{ 3021 uint32_t val; 3022 3023 if ((sc->nfe_flags & NFE_CORRECT_MACADDR) == 0) { 3024 val = NFE_READ(sc, NFE_MACADDR_LO); 3025 addr[0] = (val >> 8) & 0xff; 3026 addr[1] = (val & 0xff); 3027 3028 val = NFE_READ(sc, NFE_MACADDR_HI); 3029 addr[2] = (val >> 24) & 0xff; 3030 addr[3] = (val >> 16) & 0xff; 3031 addr[4] = (val >> 8) & 0xff; 3032 addr[5] = (val & 0xff); 3033 } else { 3034 val = NFE_READ(sc, NFE_MACADDR_LO); 3035 addr[5] = (val >> 8) & 0xff; 3036 addr[4] = (val & 0xff); 3037 3038 val = NFE_READ(sc, NFE_MACADDR_HI); 3039 addr[3] = (val >> 24) & 0xff; 3040 addr[2] = (val >> 16) & 0xff; 3041 addr[1] = (val >> 8) & 0xff; 3042 addr[0] = (val & 0xff); 3043 } 3044} 3045 3046 3047static void 3048nfe_set_macaddr(struct nfe_softc *sc, uint8_t *addr) 3049{ 3050 3051 NFE_WRITE(sc, NFE_MACADDR_LO, addr[5] << 8 | addr[4]); 3052 NFE_WRITE(sc, NFE_MACADDR_HI, addr[3] << 24 | addr[2] << 16 | 3053 addr[1] << 8 | addr[0]); 3054} 3055 3056 3057/* 3058 * Map a single buffer address. 3059 */ 3060 3061static void 3062nfe_dma_map_segs(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3063{ 3064 struct nfe_dmamap_arg *ctx; 3065 3066 if (error != 0) 3067 return; 3068 3069 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 3070 3071 ctx = (struct nfe_dmamap_arg *)arg; 3072 ctx->nfe_busaddr = segs[0].ds_addr; 3073} 3074 3075 3076static int 3077sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3078{ 3079 int error, value; 3080 3081 if (!arg1) 3082 return (EINVAL); 3083 value = *(int *)arg1; 3084 error = sysctl_handle_int(oidp, &value, 0, req); 3085 if (error || !req->newptr) 3086 return (error); 3087 if (value < low || value > high) 3088 return (EINVAL); 3089 *(int *)arg1 = value; 3090 3091 return (0); 3092} 3093 3094 3095static int 3096sysctl_hw_nfe_proc_limit(SYSCTL_HANDLER_ARGS) 3097{ 3098 3099 return (sysctl_int_range(oidp, arg1, arg2, req, NFE_PROC_MIN, 3100 NFE_PROC_MAX)); 3101} 3102 3103 3104#define NFE_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 3105 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 3106#define NFE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 3107 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 3108 3109static void 3110nfe_sysctl_node(struct nfe_softc *sc) 3111{ 3112 struct sysctl_ctx_list *ctx; 3113 struct sysctl_oid_list *child, *parent; 3114 struct sysctl_oid *tree; 3115 struct nfe_hw_stats *stats; 3116 int error; 3117 3118 stats = &sc->nfe_stats; 3119 ctx = device_get_sysctl_ctx(sc->nfe_dev); 3120 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->nfe_dev)); 3121 SYSCTL_ADD_PROC(ctx, child, 3122 OID_AUTO, "process_limit", CTLTYPE_INT | CTLFLAG_RW, 3123 &sc->nfe_process_limit, 0, sysctl_hw_nfe_proc_limit, "I", 3124 "max number of Rx events to process"); 3125 3126 sc->nfe_process_limit = NFE_PROC_DEFAULT; 3127 error = resource_int_value(device_get_name(sc->nfe_dev), 3128 device_get_unit(sc->nfe_dev), "process_limit", 3129 &sc->nfe_process_limit); 3130 if (error == 0) { 3131 if (sc->nfe_process_limit < NFE_PROC_MIN || 3132 sc->nfe_process_limit > NFE_PROC_MAX) { 3133 device_printf(sc->nfe_dev, 3134 "process_limit value out of range; " 3135 "using default: %d\n", NFE_PROC_DEFAULT); 3136 sc->nfe_process_limit = NFE_PROC_DEFAULT; 3137 } 3138 } 3139 3140 if ((sc->nfe_flags & (NFE_MIB_V1 | NFE_MIB_V2 | NFE_MIB_V3)) == 0) 3141 return; 3142 3143 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 3144 NULL, "NFE statistics"); 3145 parent = SYSCTL_CHILDREN(tree); 3146 3147 /* Rx statistics. */ 3148 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 3149 NULL, "Rx MAC statistics"); 3150 child = SYSCTL_CHILDREN(tree); 3151 3152 NFE_SYSCTL_STAT_ADD32(ctx, child, "frame_errors", 3153 &stats->rx_frame_errors, "Framing Errors"); 3154 NFE_SYSCTL_STAT_ADD32(ctx, child, "extra_bytes", 3155 &stats->rx_extra_bytes, "Extra Bytes"); 3156 NFE_SYSCTL_STAT_ADD32(ctx, child, "late_cols", 3157 &stats->rx_late_cols, "Late Collisions"); 3158 NFE_SYSCTL_STAT_ADD32(ctx, child, "runts", 3159 &stats->rx_runts, "Runts"); 3160 NFE_SYSCTL_STAT_ADD32(ctx, child, "jumbos", 3161 &stats->rx_jumbos, "Jumbos"); 3162 NFE_SYSCTL_STAT_ADD32(ctx, child, "fifo_overuns", 3163 &stats->rx_fifo_overuns, "FIFO Overruns"); 3164 NFE_SYSCTL_STAT_ADD32(ctx, child, "crc_errors", 3165 &stats->rx_crc_errors, "CRC Errors"); 3166 NFE_SYSCTL_STAT_ADD32(ctx, child, "fae", 3167 &stats->rx_fae, "Frame Alignment Errors"); 3168 NFE_SYSCTL_STAT_ADD32(ctx, child, "len_errors", 3169 &stats->rx_len_errors, "Length Errors"); 3170 NFE_SYSCTL_STAT_ADD32(ctx, child, "unicast", 3171 &stats->rx_unicast, "Unicast Frames"); 3172 NFE_SYSCTL_STAT_ADD32(ctx, child, "multicast", 3173 &stats->rx_multicast, "Multicast Frames"); 3174 NFE_SYSCTL_STAT_ADD32(ctx, child, "broadcast", 3175 &stats->rx_broadcast, "Broadcast Frames"); 3176 if ((sc->nfe_flags & NFE_MIB_V2) != 0) { 3177 NFE_SYSCTL_STAT_ADD64(ctx, child, "octets", 3178 &stats->rx_octets, "Octets"); 3179 NFE_SYSCTL_STAT_ADD32(ctx, child, "pause", 3180 &stats->rx_pause, "Pause frames"); 3181 NFE_SYSCTL_STAT_ADD32(ctx, child, "drops", 3182 &stats->rx_drops, "Drop frames"); 3183 } 3184 3185 /* Tx statistics. */ 3186 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 3187 NULL, "Tx MAC statistics"); 3188 child = SYSCTL_CHILDREN(tree); 3189 NFE_SYSCTL_STAT_ADD64(ctx, child, "octets", 3190 &stats->tx_octets, "Octets"); 3191 NFE_SYSCTL_STAT_ADD32(ctx, child, "zero_rexmits", 3192 &stats->tx_zero_rexmits, "Zero Retransmits"); 3193 NFE_SYSCTL_STAT_ADD32(ctx, child, "one_rexmits", 3194 &stats->tx_one_rexmits, "One Retransmits"); 3195 NFE_SYSCTL_STAT_ADD32(ctx, child, "multi_rexmits", 3196 &stats->tx_multi_rexmits, "Multiple Retransmits"); 3197 NFE_SYSCTL_STAT_ADD32(ctx, child, "late_cols", 3198 &stats->tx_late_cols, "Late Collisions"); 3199 NFE_SYSCTL_STAT_ADD32(ctx, child, "fifo_underuns", 3200 &stats->tx_fifo_underuns, "FIFO Underruns"); 3201 NFE_SYSCTL_STAT_ADD32(ctx, child, "carrier_losts", 3202 &stats->tx_carrier_losts, "Carrier Losts"); 3203 NFE_SYSCTL_STAT_ADD32(ctx, child, "excess_deferrals", 3204 &stats->tx_excess_deferals, "Excess Deferrals"); 3205 NFE_SYSCTL_STAT_ADD32(ctx, child, "retry_errors", 3206 &stats->tx_retry_errors, "Retry Errors"); 3207 if ((sc->nfe_flags & NFE_MIB_V2) != 0) { 3208 NFE_SYSCTL_STAT_ADD32(ctx, child, "deferrals", 3209 &stats->tx_deferals, "Deferrals"); 3210 NFE_SYSCTL_STAT_ADD32(ctx, child, "frames", 3211 &stats->tx_frames, "Frames"); 3212 NFE_SYSCTL_STAT_ADD32(ctx, child, "pause", 3213 &stats->tx_pause, "Pause Frames"); 3214 } 3215 if ((sc->nfe_flags & NFE_MIB_V3) != 0) { 3216 NFE_SYSCTL_STAT_ADD32(ctx, child, "unicast", 3217 &stats->tx_deferals, "Unicast Frames"); 3218 NFE_SYSCTL_STAT_ADD32(ctx, child, "multicast", 3219 &stats->tx_frames, "Multicast Frames"); 3220 NFE_SYSCTL_STAT_ADD32(ctx, child, "broadcast", 3221 &stats->tx_pause, "Broadcast Frames"); 3222 } 3223} 3224 3225#undef NFE_SYSCTL_STAT_ADD32 3226#undef NFE_SYSCTL_STAT_ADD64 3227 3228static void 3229nfe_stats_clear(struct nfe_softc *sc) 3230{ 3231 int i, mib_cnt; 3232 3233 if ((sc->nfe_flags & NFE_MIB_V1) != 0) 3234 mib_cnt = NFE_NUM_MIB_STATV1; 3235 else if ((sc->nfe_flags & (NFE_MIB_V2 | NFE_MIB_V3)) != 0) 3236 mib_cnt = NFE_NUM_MIB_STATV2; 3237 else 3238 return; 3239 3240 for (i = 0; i < mib_cnt; i++) 3241 NFE_READ(sc, NFE_TX_OCTET + i * sizeof(uint32_t)); 3242 3243 if ((sc->nfe_flags & NFE_MIB_V3) != 0) { 3244 NFE_READ(sc, NFE_TX_UNICAST); 3245 NFE_READ(sc, NFE_TX_MULTICAST); 3246 NFE_READ(sc, NFE_TX_BROADCAST); 3247 } 3248} 3249 3250static void 3251nfe_stats_update(struct nfe_softc *sc) 3252{ 3253 struct nfe_hw_stats *stats; 3254 3255 NFE_LOCK_ASSERT(sc); 3256 3257 if ((sc->nfe_flags & (NFE_MIB_V1 | NFE_MIB_V2 | NFE_MIB_V3)) == 0) 3258 return; 3259 3260 stats = &sc->nfe_stats; 3261 stats->tx_octets += NFE_READ(sc, NFE_TX_OCTET); 3262 stats->tx_zero_rexmits += NFE_READ(sc, NFE_TX_ZERO_REXMIT); 3263 stats->tx_one_rexmits += NFE_READ(sc, NFE_TX_ONE_REXMIT); 3264 stats->tx_multi_rexmits += NFE_READ(sc, NFE_TX_MULTI_REXMIT); 3265 stats->tx_late_cols += NFE_READ(sc, NFE_TX_LATE_COL); 3266 stats->tx_fifo_underuns += NFE_READ(sc, NFE_TX_FIFO_UNDERUN); 3267 stats->tx_carrier_losts += NFE_READ(sc, NFE_TX_CARRIER_LOST); 3268 stats->tx_excess_deferals += NFE_READ(sc, NFE_TX_EXCESS_DEFERRAL); 3269 stats->tx_retry_errors += NFE_READ(sc, NFE_TX_RETRY_ERROR); 3270 stats->rx_frame_errors += NFE_READ(sc, NFE_RX_FRAME_ERROR); 3271 stats->rx_extra_bytes += NFE_READ(sc, NFE_RX_EXTRA_BYTES); 3272 stats->rx_late_cols += NFE_READ(sc, NFE_RX_LATE_COL); 3273 stats->rx_runts += NFE_READ(sc, NFE_RX_RUNT); 3274 stats->rx_jumbos += NFE_READ(sc, NFE_RX_JUMBO); 3275 stats->rx_fifo_overuns += NFE_READ(sc, NFE_RX_FIFO_OVERUN); 3276 stats->rx_crc_errors += NFE_READ(sc, NFE_RX_CRC_ERROR); 3277 stats->rx_fae += NFE_READ(sc, NFE_RX_FAE); 3278 stats->rx_len_errors += NFE_READ(sc, NFE_RX_LEN_ERROR); 3279 stats->rx_unicast += NFE_READ(sc, NFE_RX_UNICAST); 3280 stats->rx_multicast += NFE_READ(sc, NFE_RX_MULTICAST); 3281 stats->rx_broadcast += NFE_READ(sc, NFE_RX_BROADCAST); 3282 3283 if ((sc->nfe_flags & NFE_MIB_V2) != 0) { 3284 stats->tx_deferals += NFE_READ(sc, NFE_TX_DEFERAL); 3285 stats->tx_frames += NFE_READ(sc, NFE_TX_FRAME); 3286 stats->rx_octets += NFE_READ(sc, NFE_RX_OCTET); 3287 stats->tx_pause += NFE_READ(sc, NFE_TX_PAUSE); 3288 stats->rx_pause += NFE_READ(sc, NFE_RX_PAUSE); 3289 stats->rx_drops += NFE_READ(sc, NFE_RX_DROP); 3290 } 3291 3292 if ((sc->nfe_flags & NFE_MIB_V3) != 0) { 3293 stats->tx_unicast += NFE_READ(sc, NFE_TX_UNICAST); 3294 stats->tx_multicast += NFE_READ(sc, NFE_TX_MULTICAST); 3295 stats->tx_broadcast += NFE_READ(sc, NFE_TX_BROADCAST); 3296 } 3297} 3298 3299 3300static void 3301nfe_set_linkspeed(struct nfe_softc *sc) 3302{ 3303 struct mii_softc *miisc; 3304 struct mii_data *mii; 3305 int aneg, i, phyno; 3306 3307 NFE_LOCK_ASSERT(sc); 3308 3309 mii = device_get_softc(sc->nfe_miibus); 3310 mii_pollstat(mii); 3311 aneg = 0; 3312 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 3313 (IFM_ACTIVE | IFM_AVALID)) { 3314 switch IFM_SUBTYPE(mii->mii_media_active) { 3315 case IFM_10_T: 3316 case IFM_100_TX: 3317 return; 3318 case IFM_1000_T: 3319 aneg++; 3320 break; 3321 default: 3322 break; 3323 } 3324 } 3325 miisc = LIST_FIRST(&mii->mii_phys); 3326 phyno = miisc->mii_phy; 3327 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 3328 PHY_RESET(miisc); 3329 nfe_miibus_writereg(sc->nfe_dev, phyno, MII_100T2CR, 0); 3330 nfe_miibus_writereg(sc->nfe_dev, phyno, 3331 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 3332 nfe_miibus_writereg(sc->nfe_dev, phyno, 3333 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 3334 DELAY(1000); 3335 if (aneg != 0) { 3336 /* 3337 * Poll link state until nfe(4) get a 10/100Mbps link. 3338 */ 3339 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 3340 mii_pollstat(mii); 3341 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 3342 == (IFM_ACTIVE | IFM_AVALID)) { 3343 switch (IFM_SUBTYPE(mii->mii_media_active)) { 3344 case IFM_10_T: 3345 case IFM_100_TX: 3346 nfe_mac_config(sc, mii); 3347 return; 3348 default: 3349 break; 3350 } 3351 } 3352 NFE_UNLOCK(sc); 3353 pause("nfelnk", hz); 3354 NFE_LOCK(sc); 3355 } 3356 if (i == MII_ANEGTICKS_GIGE) 3357 device_printf(sc->nfe_dev, 3358 "establishing a link failed, WOL may not work!"); 3359 } 3360 /* 3361 * No link, force MAC to have 100Mbps, full-duplex link. 3362 * This is the last resort and may/may not work. 3363 */ 3364 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 3365 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 3366 nfe_mac_config(sc, mii); 3367} 3368 3369 3370static void 3371nfe_set_wol(struct nfe_softc *sc) 3372{ 3373 struct ifnet *ifp; 3374 uint32_t wolctl; 3375 int pmc; 3376 uint16_t pmstat; 3377 3378 NFE_LOCK_ASSERT(sc); 3379 3380 if (pci_find_cap(sc->nfe_dev, PCIY_PMG, &pmc) != 0) 3381 return; 3382 ifp = sc->nfe_ifp; 3383 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3384 wolctl = NFE_WOL_MAGIC; 3385 else 3386 wolctl = 0; 3387 NFE_WRITE(sc, NFE_WOL_CTL, wolctl); 3388 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) { 3389 nfe_set_linkspeed(sc); 3390 if ((sc->nfe_flags & NFE_PWR_MGMT) != 0) 3391 NFE_WRITE(sc, NFE_PWR2_CTL, 3392 NFE_READ(sc, NFE_PWR2_CTL) & ~NFE_PWR2_GATE_CLOCKS); 3393 /* Enable RX. */ 3394 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, 0); 3395 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, 0); 3396 NFE_WRITE(sc, NFE_RX_CTL, NFE_READ(sc, NFE_RX_CTL) | 3397 NFE_RX_START); 3398 } 3399 /* Request PME if WOL is requested. */ 3400 pmstat = pci_read_config(sc->nfe_dev, pmc + PCIR_POWER_STATUS, 2); 3401 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3402 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3403 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3404 pci_write_config(sc->nfe_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 3405} 3406