if_nfe.c revision 176859
1/* $OpenBSD: if_nfe.c,v 1.54 2006/04/07 12:38:12 jsg Exp $ */ 2 3/*- 4 * Copyright (c) 2006 Shigeaki Tagashira <shigeaki@se.hiroshima-u.ac.jp> 5 * Copyright (c) 2006 Damien Bergamini <damien.bergamini@free.fr> 6 * Copyright (c) 2005, 2006 Jonathan Gray <jsg@openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21/* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */ 22 23#include <sys/cdefs.h> 24__FBSDID("$FreeBSD: head/sys/dev/nfe/if_nfe.c 176859 2008-03-06 01:47:53Z yongari $"); 25 26#ifdef HAVE_KERNEL_OPTION_HEADERS 27#include "opt_device_polling.h" 28#endif 29 30#include <sys/param.h> 31#include <sys/endian.h> 32#include <sys/systm.h> 33#include <sys/sockio.h> 34#include <sys/mbuf.h> 35#include <sys/malloc.h> 36#include <sys/module.h> 37#include <sys/kernel.h> 38#include <sys/queue.h> 39#include <sys/socket.h> 40#include <sys/sysctl.h> 41#include <sys/taskqueue.h> 42 43#include <net/if.h> 44#include <net/if_arp.h> 45#include <net/ethernet.h> 46#include <net/if_dl.h> 47#include <net/if_media.h> 48#include <net/if_types.h> 49#include <net/if_vlan_var.h> 50 51#include <net/bpf.h> 52 53#include <machine/bus.h> 54#include <machine/resource.h> 55#include <sys/bus.h> 56#include <sys/rman.h> 57 58#include <dev/mii/mii.h> 59#include <dev/mii/miivar.h> 60 61#include <dev/pci/pcireg.h> 62#include <dev/pci/pcivar.h> 63 64#include <dev/nfe/if_nfereg.h> 65#include <dev/nfe/if_nfevar.h> 66 67MODULE_DEPEND(nfe, pci, 1, 1, 1); 68MODULE_DEPEND(nfe, ether, 1, 1, 1); 69MODULE_DEPEND(nfe, miibus, 1, 1, 1); 70 71/* "device miibus" required. See GENERIC if you get errors here. */ 72#include "miibus_if.h" 73 74static int nfe_probe(device_t); 75static int nfe_attach(device_t); 76static int nfe_detach(device_t); 77static int nfe_suspend(device_t); 78static int nfe_resume(device_t); 79static int nfe_shutdown(device_t); 80static void nfe_power(struct nfe_softc *); 81static int nfe_miibus_readreg(device_t, int, int); 82static int nfe_miibus_writereg(device_t, int, int, int); 83static void nfe_miibus_statchg(device_t); 84static void nfe_link_task(void *, int); 85static void nfe_set_intr(struct nfe_softc *); 86static __inline void nfe_enable_intr(struct nfe_softc *); 87static __inline void nfe_disable_intr(struct nfe_softc *); 88static int nfe_ioctl(struct ifnet *, u_long, caddr_t); 89static void nfe_alloc_msix(struct nfe_softc *, int); 90static int nfe_intr(void *); 91static void nfe_int_task(void *, int); 92static __inline void nfe_discard_rxbuf(struct nfe_softc *, int); 93static __inline void nfe_discard_jrxbuf(struct nfe_softc *, int); 94static int nfe_newbuf(struct nfe_softc *, int); 95static int nfe_jnewbuf(struct nfe_softc *, int); 96static int nfe_rxeof(struct nfe_softc *, int); 97static int nfe_jrxeof(struct nfe_softc *, int); 98static void nfe_txeof(struct nfe_softc *); 99static int nfe_encap(struct nfe_softc *, struct mbuf **); 100static void nfe_setmulti(struct nfe_softc *); 101static void nfe_tx_task(void *, int); 102static void nfe_start(struct ifnet *); 103static void nfe_watchdog(struct ifnet *); 104static void nfe_init(void *); 105static void nfe_init_locked(void *); 106static void nfe_stop(struct ifnet *); 107static int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 108static void nfe_alloc_jrx_ring(struct nfe_softc *, struct nfe_jrx_ring *); 109static int nfe_init_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 110static int nfe_init_jrx_ring(struct nfe_softc *, struct nfe_jrx_ring *); 111static void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 112static void nfe_free_jrx_ring(struct nfe_softc *, struct nfe_jrx_ring *); 113static int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 114static void nfe_init_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 115static void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 116static int nfe_ifmedia_upd(struct ifnet *); 117static void nfe_ifmedia_sts(struct ifnet *, struct ifmediareq *); 118static void nfe_tick(void *); 119static void nfe_get_macaddr(struct nfe_softc *, uint8_t *); 120static void nfe_set_macaddr(struct nfe_softc *, uint8_t *); 121static void nfe_dma_map_segs(void *, bus_dma_segment_t *, int, int); 122 123static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 124static int sysctl_hw_nfe_proc_limit(SYSCTL_HANDLER_ARGS); 125 126#ifdef NFE_DEBUG 127static int nfedebug = 0; 128#define DPRINTF(sc, ...) do { \ 129 if (nfedebug) \ 130 device_printf((sc)->nfe_dev, __VA_ARGS__); \ 131} while (0) 132#define DPRINTFN(sc, n, ...) do { \ 133 if (nfedebug >= (n)) \ 134 device_printf((sc)->nfe_dev, __VA_ARGS__); \ 135} while (0) 136#else 137#define DPRINTF(sc, ...) 138#define DPRINTFN(sc, n, ...) 139#endif 140 141#define NFE_LOCK(_sc) mtx_lock(&(_sc)->nfe_mtx) 142#define NFE_UNLOCK(_sc) mtx_unlock(&(_sc)->nfe_mtx) 143#define NFE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->nfe_mtx, MA_OWNED) 144 145/* Tunables. */ 146static int msi_disable = 0; 147static int msix_disable = 0; 148static int jumbo_disable = 0; 149TUNABLE_INT("hw.nfe.msi_disable", &msi_disable); 150TUNABLE_INT("hw.nfe.msix_disable", &msix_disable); 151TUNABLE_INT("hw.nfe.jumbo_disable", &jumbo_disable); 152 153static device_method_t nfe_methods[] = { 154 /* Device interface */ 155 DEVMETHOD(device_probe, nfe_probe), 156 DEVMETHOD(device_attach, nfe_attach), 157 DEVMETHOD(device_detach, nfe_detach), 158 DEVMETHOD(device_suspend, nfe_suspend), 159 DEVMETHOD(device_resume, nfe_resume), 160 DEVMETHOD(device_shutdown, nfe_shutdown), 161 162 /* bus interface */ 163 DEVMETHOD(bus_print_child, bus_generic_print_child), 164 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 165 166 /* MII interface */ 167 DEVMETHOD(miibus_readreg, nfe_miibus_readreg), 168 DEVMETHOD(miibus_writereg, nfe_miibus_writereg), 169 DEVMETHOD(miibus_statchg, nfe_miibus_statchg), 170 171 { NULL, NULL } 172}; 173 174static driver_t nfe_driver = { 175 "nfe", 176 nfe_methods, 177 sizeof(struct nfe_softc) 178}; 179 180static devclass_t nfe_devclass; 181 182DRIVER_MODULE(nfe, pci, nfe_driver, nfe_devclass, 0, 0); 183DRIVER_MODULE(miibus, nfe, miibus_driver, miibus_devclass, 0, 0); 184 185static struct nfe_type nfe_devs[] = { 186 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN, 187 "NVIDIA nForce MCP Networking Adapter"}, 188 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN, 189 "NVIDIA nForce2 MCP2 Networking Adapter"}, 190 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1, 191 "NVIDIA nForce2 400 MCP4 Networking Adapter"}, 192 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2, 193 "NVIDIA nForce2 400 MCP5 Networking Adapter"}, 194 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1, 195 "NVIDIA nForce3 MCP3 Networking Adapter"}, 196 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN, 197 "NVIDIA nForce3 250 MCP6 Networking Adapter"}, 198 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4, 199 "NVIDIA nForce3 MCP7 Networking Adapter"}, 200 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE4_LAN1, 201 "NVIDIA nForce4 CK804 MCP8 Networking Adapter"}, 202 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE4_LAN2, 203 "NVIDIA nForce4 CK804 MCP9 Networking Adapter"}, 204 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1, 205 "NVIDIA nForce MCP04 Networking Adapter"}, /* MCP10 */ 206 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2, 207 "NVIDIA nForce MCP04 Networking Adapter"}, /* MCP11 */ 208 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE430_LAN1, 209 "NVIDIA nForce 430 MCP12 Networking Adapter"}, 210 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE430_LAN2, 211 "NVIDIA nForce 430 MCP13 Networking Adapter"}, 212 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1, 213 "NVIDIA nForce MCP55 Networking Adapter"}, 214 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2, 215 "NVIDIA nForce MCP55 Networking Adapter"}, 216 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1, 217 "NVIDIA nForce MCP61 Networking Adapter"}, 218 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2, 219 "NVIDIA nForce MCP61 Networking Adapter"}, 220 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3, 221 "NVIDIA nForce MCP61 Networking Adapter"}, 222 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4, 223 "NVIDIA nForce MCP61 Networking Adapter"}, 224 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1, 225 "NVIDIA nForce MCP65 Networking Adapter"}, 226 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2, 227 "NVIDIA nForce MCP65 Networking Adapter"}, 228 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3, 229 "NVIDIA nForce MCP65 Networking Adapter"}, 230 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4, 231 "NVIDIA nForce MCP65 Networking Adapter"}, 232 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN1, 233 "NVIDIA nForce MCP67 Networking Adapter"}, 234 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN2, 235 "NVIDIA nForce MCP67 Networking Adapter"}, 236 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN3, 237 "NVIDIA nForce MCP67 Networking Adapter"}, 238 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN4, 239 "NVIDIA nForce MCP67 Networking Adapter"}, 240 {0, 0, NULL} 241}; 242 243 244/* Probe for supported hardware ID's */ 245static int 246nfe_probe(device_t dev) 247{ 248 struct nfe_type *t; 249 250 t = nfe_devs; 251 /* Check for matching PCI DEVICE ID's */ 252 while (t->name != NULL) { 253 if ((pci_get_vendor(dev) == t->vid_id) && 254 (pci_get_device(dev) == t->dev_id)) { 255 device_set_desc(dev, t->name); 256 return (BUS_PROBE_DEFAULT); 257 } 258 t++; 259 } 260 261 return (ENXIO); 262} 263 264static void 265nfe_alloc_msix(struct nfe_softc *sc, int count) 266{ 267 int rid; 268 269 rid = PCIR_BAR(2); 270 sc->nfe_msix_res = bus_alloc_resource_any(sc->nfe_dev, SYS_RES_MEMORY, 271 &rid, RF_ACTIVE); 272 if (sc->nfe_msix_res == NULL) { 273 device_printf(sc->nfe_dev, 274 "couldn't allocate MSIX table resource\n"); 275 return; 276 } 277 rid = PCIR_BAR(3); 278 sc->nfe_msix_pba_res = bus_alloc_resource_any(sc->nfe_dev, 279 SYS_RES_MEMORY, &rid, RF_ACTIVE); 280 if (sc->nfe_msix_pba_res == NULL) { 281 device_printf(sc->nfe_dev, 282 "couldn't allocate MSIX PBA resource\n"); 283 bus_release_resource(sc->nfe_dev, SYS_RES_MEMORY, PCIR_BAR(2), 284 sc->nfe_msix_res); 285 sc->nfe_msix_res = NULL; 286 return; 287 } 288 289 if (pci_alloc_msix(sc->nfe_dev, &count) == 0) { 290 if (count == NFE_MSI_MESSAGES) { 291 if (bootverbose) 292 device_printf(sc->nfe_dev, 293 "Using %d MSIX messages\n", count); 294 sc->nfe_msix = 1; 295 } else { 296 if (bootverbose) 297 device_printf(sc->nfe_dev, 298 "couldn't allocate MSIX\n"); 299 pci_release_msi(sc->nfe_dev); 300 bus_release_resource(sc->nfe_dev, SYS_RES_MEMORY, 301 PCIR_BAR(3), sc->nfe_msix_pba_res); 302 bus_release_resource(sc->nfe_dev, SYS_RES_MEMORY, 303 PCIR_BAR(2), sc->nfe_msix_res); 304 sc->nfe_msix_pba_res = NULL; 305 sc->nfe_msix_res = NULL; 306 } 307 } 308} 309 310static int 311nfe_attach(device_t dev) 312{ 313 struct nfe_softc *sc; 314 struct ifnet *ifp; 315 bus_addr_t dma_addr_max; 316 int error = 0, i, msic, reg, rid; 317 318 sc = device_get_softc(dev); 319 sc->nfe_dev = dev; 320 321 mtx_init(&sc->nfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 322 MTX_DEF); 323 callout_init_mtx(&sc->nfe_stat_ch, &sc->nfe_mtx, 0); 324 TASK_INIT(&sc->nfe_link_task, 0, nfe_link_task, sc); 325 326 pci_enable_busmaster(dev); 327 328 rid = PCIR_BAR(0); 329 sc->nfe_res[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 330 RF_ACTIVE); 331 if (sc->nfe_res[0] == NULL) { 332 device_printf(dev, "couldn't map memory resources\n"); 333 mtx_destroy(&sc->nfe_mtx); 334 return (ENXIO); 335 } 336 337 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 338 uint16_t v, width; 339 340 v = pci_read_config(dev, reg + 0x08, 2); 341 /* Change max. read request size to 4096. */ 342 v &= ~(7 << 12); 343 v |= (5 << 12); 344 pci_write_config(dev, reg + 0x08, v, 2); 345 346 v = pci_read_config(dev, reg + 0x0c, 2); 347 /* link capability */ 348 v = (v >> 4) & 0x0f; 349 width = pci_read_config(dev, reg + 0x12, 2); 350 /* negotiated link width */ 351 width = (width >> 4) & 0x3f; 352 if (v != width) 353 device_printf(sc->nfe_dev, 354 "warning, negotiated width of link(x%d) != " 355 "max. width of link(x%d)\n", width, v); 356 } 357 358 /* Allocate interrupt */ 359 if (msix_disable == 0 || msi_disable == 0) { 360 if (msix_disable == 0 && 361 (msic = pci_msix_count(dev)) == NFE_MSI_MESSAGES) 362 nfe_alloc_msix(sc, msic); 363 if (msi_disable == 0 && sc->nfe_msix == 0 && 364 (msic = pci_msi_count(dev)) == NFE_MSI_MESSAGES && 365 pci_alloc_msi(dev, &msic) == 0) { 366 if (msic == NFE_MSI_MESSAGES) { 367 if (bootverbose) 368 device_printf(dev, 369 "Using %d MSI messages\n", msic); 370 sc->nfe_msi = 1; 371 } else 372 pci_release_msi(dev); 373 } 374 } 375 376 if (sc->nfe_msix == 0 && sc->nfe_msi == 0) { 377 rid = 0; 378 sc->nfe_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 379 RF_SHAREABLE | RF_ACTIVE); 380 if (sc->nfe_irq[0] == NULL) { 381 device_printf(dev, "couldn't allocate IRQ resources\n"); 382 error = ENXIO; 383 goto fail; 384 } 385 } else { 386 for (i = 0, rid = 1; i < NFE_MSI_MESSAGES; i++, rid++) { 387 sc->nfe_irq[i] = bus_alloc_resource_any(dev, 388 SYS_RES_IRQ, &rid, RF_ACTIVE); 389 if (sc->nfe_irq[i] == NULL) { 390 device_printf(dev, 391 "couldn't allocate IRQ resources for " 392 "message %d\n", rid); 393 error = ENXIO; 394 goto fail; 395 } 396 } 397 /* Map interrupts to vector 0. */ 398 if (sc->nfe_msix != 0) { 399 NFE_WRITE(sc, NFE_MSIX_MAP0, 0); 400 NFE_WRITE(sc, NFE_MSIX_MAP1, 0); 401 } else if (sc->nfe_msi != 0) { 402 NFE_WRITE(sc, NFE_MSI_MAP0, 0); 403 NFE_WRITE(sc, NFE_MSI_MAP1, 0); 404 } 405 } 406 407 /* Set IRQ status/mask register. */ 408 sc->nfe_irq_status = NFE_IRQ_STATUS; 409 sc->nfe_irq_mask = NFE_IRQ_MASK; 410 sc->nfe_intrs = NFE_IRQ_WANTED; 411 sc->nfe_nointrs = 0; 412 if (sc->nfe_msix != 0) { 413 sc->nfe_irq_status = NFE_MSIX_IRQ_STATUS; 414 sc->nfe_nointrs = NFE_IRQ_WANTED; 415 } else if (sc->nfe_msi != 0) { 416 sc->nfe_irq_mask = NFE_MSI_IRQ_MASK; 417 sc->nfe_intrs = NFE_MSI_VECTOR_0_ENABLED; 418 } 419 420 sc->nfe_devid = pci_get_device(dev); 421 sc->nfe_revid = pci_get_revid(dev); 422 sc->nfe_flags = 0; 423 424 switch (sc->nfe_devid) { 425 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2: 426 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3: 427 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4: 428 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5: 429 sc->nfe_flags |= NFE_JUMBO_SUP | NFE_HW_CSUM; 430 break; 431 case PCI_PRODUCT_NVIDIA_MCP51_LAN1: 432 case PCI_PRODUCT_NVIDIA_MCP51_LAN2: 433 sc->nfe_flags |= NFE_40BIT_ADDR | NFE_PWR_MGMT; 434 break; 435 case PCI_PRODUCT_NVIDIA_CK804_LAN1: 436 case PCI_PRODUCT_NVIDIA_CK804_LAN2: 437 case PCI_PRODUCT_NVIDIA_MCP04_LAN1: 438 case PCI_PRODUCT_NVIDIA_MCP04_LAN2: 439 sc->nfe_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM; 440 break; 441 case PCI_PRODUCT_NVIDIA_MCP55_LAN1: 442 case PCI_PRODUCT_NVIDIA_MCP55_LAN2: 443 sc->nfe_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 444 NFE_HW_VLAN | NFE_PWR_MGMT | NFE_TX_FLOW_CTRL; 445 break; 446 447 case PCI_PRODUCT_NVIDIA_MCP61_LAN1: 448 case PCI_PRODUCT_NVIDIA_MCP61_LAN2: 449 case PCI_PRODUCT_NVIDIA_MCP61_LAN3: 450 case PCI_PRODUCT_NVIDIA_MCP61_LAN4: 451 case PCI_PRODUCT_NVIDIA_MCP67_LAN1: 452 case PCI_PRODUCT_NVIDIA_MCP67_LAN2: 453 case PCI_PRODUCT_NVIDIA_MCP67_LAN3: 454 case PCI_PRODUCT_NVIDIA_MCP67_LAN4: 455 sc->nfe_flags |= NFE_40BIT_ADDR | NFE_PWR_MGMT | 456 NFE_CORRECT_MACADDR | NFE_TX_FLOW_CTRL; 457 break; 458 case PCI_PRODUCT_NVIDIA_MCP65_LAN1: 459 case PCI_PRODUCT_NVIDIA_MCP65_LAN2: 460 case PCI_PRODUCT_NVIDIA_MCP65_LAN3: 461 case PCI_PRODUCT_NVIDIA_MCP65_LAN4: 462 sc->nfe_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | 463 NFE_PWR_MGMT | NFE_CORRECT_MACADDR | NFE_TX_FLOW_CTRL; 464 break; 465 } 466 467 nfe_power(sc); 468 /* Check for reversed ethernet address */ 469 if ((NFE_READ(sc, NFE_TX_UNK) & NFE_MAC_ADDR_INORDER) != 0) 470 sc->nfe_flags |= NFE_CORRECT_MACADDR; 471 nfe_get_macaddr(sc, sc->eaddr); 472 /* 473 * Allocate the parent bus DMA tag appropriate for PCI. 474 */ 475 dma_addr_max = BUS_SPACE_MAXADDR_32BIT; 476 if ((sc->nfe_flags & NFE_40BIT_ADDR) != 0) 477 dma_addr_max = NFE_DMA_MAXADDR; 478 error = bus_dma_tag_create( 479 bus_get_dma_tag(sc->nfe_dev), /* parent */ 480 1, 0, /* alignment, boundary */ 481 dma_addr_max, /* lowaddr */ 482 BUS_SPACE_MAXADDR, /* highaddr */ 483 NULL, NULL, /* filter, filterarg */ 484 BUS_SPACE_MAXSIZE_32BIT, 0, /* maxsize, nsegments */ 485 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 486 0, /* flags */ 487 NULL, NULL, /* lockfunc, lockarg */ 488 &sc->nfe_parent_tag); 489 if (error) 490 goto fail; 491 492 ifp = sc->nfe_ifp = if_alloc(IFT_ETHER); 493 if (ifp == NULL) { 494 device_printf(dev, "can not if_alloc()\n"); 495 error = ENOSPC; 496 goto fail; 497 } 498 TASK_INIT(&sc->nfe_tx_task, 1, nfe_tx_task, ifp); 499 500 /* 501 * Allocate Tx and Rx rings. 502 */ 503 if ((error = nfe_alloc_tx_ring(sc, &sc->txq)) != 0) 504 goto fail; 505 506 if ((error = nfe_alloc_rx_ring(sc, &sc->rxq)) != 0) 507 goto fail; 508 509 nfe_alloc_jrx_ring(sc, &sc->jrxq); 510 511 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 512 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 513 OID_AUTO, "process_limit", CTLTYPE_INT | CTLFLAG_RW, 514 &sc->nfe_process_limit, 0, sysctl_hw_nfe_proc_limit, "I", 515 "max number of Rx events to process"); 516 517 sc->nfe_process_limit = NFE_PROC_DEFAULT; 518 error = resource_int_value(device_get_name(dev), device_get_unit(dev), 519 "process_limit", &sc->nfe_process_limit); 520 if (error == 0) { 521 if (sc->nfe_process_limit < NFE_PROC_MIN || 522 sc->nfe_process_limit > NFE_PROC_MAX) { 523 device_printf(dev, "process_limit value out of range; " 524 "using default: %d\n", NFE_PROC_DEFAULT); 525 sc->nfe_process_limit = NFE_PROC_DEFAULT; 526 } 527 } 528 529 ifp->if_softc = sc; 530 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 531 ifp->if_mtu = ETHERMTU; 532 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 533 ifp->if_ioctl = nfe_ioctl; 534 ifp->if_start = nfe_start; 535 ifp->if_hwassist = 0; 536 ifp->if_capabilities = 0; 537 ifp->if_watchdog = NULL; 538 ifp->if_init = nfe_init; 539 IFQ_SET_MAXLEN(&ifp->if_snd, NFE_TX_RING_COUNT - 1); 540 ifp->if_snd.ifq_drv_maxlen = NFE_TX_RING_COUNT - 1; 541 IFQ_SET_READY(&ifp->if_snd); 542 543 if (sc->nfe_flags & NFE_HW_CSUM) { 544 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_TSO4; 545 ifp->if_hwassist |= NFE_CSUM_FEATURES | CSUM_TSO; 546 } 547 ifp->if_capenable = ifp->if_capabilities; 548 549 sc->nfe_framesize = ifp->if_mtu + NFE_RX_HEADERS; 550 /* VLAN capability setup. */ 551 ifp->if_capabilities |= IFCAP_VLAN_MTU; 552 if ((sc->nfe_flags & NFE_HW_VLAN) != 0) { 553 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 554 if ((ifp->if_capabilities & IFCAP_HWCSUM) != 0) 555 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 556 } 557 ifp->if_capenable = ifp->if_capabilities; 558 559 /* 560 * Tell the upper layer(s) we support long frames. 561 * Must appear after the call to ether_ifattach() because 562 * ether_ifattach() sets ifi_hdrlen to the default value. 563 */ 564 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 565 566#ifdef DEVICE_POLLING 567 ifp->if_capabilities |= IFCAP_POLLING; 568#endif 569 570 /* Do MII setup */ 571 if (mii_phy_probe(dev, &sc->nfe_miibus, nfe_ifmedia_upd, 572 nfe_ifmedia_sts)) { 573 device_printf(dev, "MII without any phy!\n"); 574 error = ENXIO; 575 goto fail; 576 } 577 ether_ifattach(ifp, sc->eaddr); 578 579 TASK_INIT(&sc->nfe_int_task, 0, nfe_int_task, sc); 580 sc->nfe_tq = taskqueue_create_fast("nfe_taskq", M_WAITOK, 581 taskqueue_thread_enqueue, &sc->nfe_tq); 582 taskqueue_start_threads(&sc->nfe_tq, 1, PI_NET, "%s taskq", 583 device_get_nameunit(sc->nfe_dev)); 584 error = 0; 585 if (sc->nfe_msi == 0 && sc->nfe_msix == 0) { 586 error = bus_setup_intr(dev, sc->nfe_irq[0], 587 INTR_TYPE_NET | INTR_MPSAFE, nfe_intr, NULL, sc, 588 &sc->nfe_intrhand[0]); 589 } else { 590 for (i = 0; i < NFE_MSI_MESSAGES; i++) { 591 error = bus_setup_intr(dev, sc->nfe_irq[i], 592 INTR_TYPE_NET | INTR_MPSAFE, nfe_intr, NULL, sc, 593 &sc->nfe_intrhand[i]); 594 if (error != 0) 595 break; 596 } 597 } 598 if (error) { 599 device_printf(dev, "couldn't set up irq\n"); 600 taskqueue_free(sc->nfe_tq); 601 sc->nfe_tq = NULL; 602 ether_ifdetach(ifp); 603 goto fail; 604 } 605 606fail: 607 if (error) 608 nfe_detach(dev); 609 610 return (error); 611} 612 613 614static int 615nfe_detach(device_t dev) 616{ 617 struct nfe_softc *sc; 618 struct ifnet *ifp; 619 uint8_t eaddr[ETHER_ADDR_LEN]; 620 int i, rid; 621 622 sc = device_get_softc(dev); 623 KASSERT(mtx_initialized(&sc->nfe_mtx), ("nfe mutex not initialized")); 624 ifp = sc->nfe_ifp; 625 626#ifdef DEVICE_POLLING 627 if (ifp != NULL && ifp->if_capenable & IFCAP_POLLING) 628 ether_poll_deregister(ifp); 629#endif 630 if (device_is_attached(dev)) { 631 NFE_LOCK(sc); 632 nfe_stop(ifp); 633 ifp->if_flags &= ~IFF_UP; 634 NFE_UNLOCK(sc); 635 callout_drain(&sc->nfe_stat_ch); 636 taskqueue_drain(taskqueue_fast, &sc->nfe_tx_task); 637 taskqueue_drain(taskqueue_swi, &sc->nfe_link_task); 638 ether_ifdetach(ifp); 639 } 640 641 if (ifp) { 642 /* restore ethernet address */ 643 if ((sc->nfe_flags & NFE_CORRECT_MACADDR) == 0) { 644 for (i = 0; i < ETHER_ADDR_LEN; i++) { 645 eaddr[i] = sc->eaddr[5 - i]; 646 } 647 } else 648 bcopy(sc->eaddr, eaddr, ETHER_ADDR_LEN); 649 nfe_set_macaddr(sc, eaddr); 650 if_free(ifp); 651 } 652 if (sc->nfe_miibus) 653 device_delete_child(dev, sc->nfe_miibus); 654 bus_generic_detach(dev); 655 if (sc->nfe_tq != NULL) { 656 taskqueue_drain(sc->nfe_tq, &sc->nfe_int_task); 657 taskqueue_free(sc->nfe_tq); 658 sc->nfe_tq = NULL; 659 } 660 661 for (i = 0; i < NFE_MSI_MESSAGES; i++) { 662 if (sc->nfe_intrhand[i] != NULL) { 663 bus_teardown_intr(dev, sc->nfe_irq[i], 664 sc->nfe_intrhand[i]); 665 sc->nfe_intrhand[i] = NULL; 666 } 667 } 668 669 if (sc->nfe_msi == 0 && sc->nfe_msix == 0) { 670 if (sc->nfe_irq[0] != NULL) 671 bus_release_resource(dev, SYS_RES_IRQ, 0, 672 sc->nfe_irq[0]); 673 } else { 674 for (i = 0, rid = 1; i < NFE_MSI_MESSAGES; i++, rid++) { 675 if (sc->nfe_irq[i] != NULL) { 676 bus_release_resource(dev, SYS_RES_IRQ, rid, 677 sc->nfe_irq[i]); 678 sc->nfe_irq[i] = NULL; 679 } 680 } 681 pci_release_msi(dev); 682 } 683 if (sc->nfe_msix_pba_res != NULL) { 684 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(3), 685 sc->nfe_msix_pba_res); 686 sc->nfe_msix_pba_res = NULL; 687 } 688 if (sc->nfe_msix_res != NULL) { 689 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(2), 690 sc->nfe_msix_res); 691 sc->nfe_msix_res = NULL; 692 } 693 if (sc->nfe_res[0] != NULL) { 694 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), 695 sc->nfe_res[0]); 696 sc->nfe_res[0] = NULL; 697 } 698 699 nfe_free_tx_ring(sc, &sc->txq); 700 nfe_free_rx_ring(sc, &sc->rxq); 701 nfe_free_jrx_ring(sc, &sc->jrxq); 702 703 if (sc->nfe_parent_tag) { 704 bus_dma_tag_destroy(sc->nfe_parent_tag); 705 sc->nfe_parent_tag = NULL; 706 } 707 708 mtx_destroy(&sc->nfe_mtx); 709 710 return (0); 711} 712 713 714static int 715nfe_suspend(device_t dev) 716{ 717 struct nfe_softc *sc; 718 719 sc = device_get_softc(dev); 720 721 NFE_LOCK(sc); 722 nfe_stop(sc->nfe_ifp); 723 sc->nfe_suspended = 1; 724 NFE_UNLOCK(sc); 725 726 return (0); 727} 728 729 730static int 731nfe_resume(device_t dev) 732{ 733 struct nfe_softc *sc; 734 struct ifnet *ifp; 735 736 sc = device_get_softc(dev); 737 738 NFE_LOCK(sc); 739 ifp = sc->nfe_ifp; 740 if (ifp->if_flags & IFF_UP) 741 nfe_init_locked(sc); 742 sc->nfe_suspended = 0; 743 NFE_UNLOCK(sc); 744 745 return (0); 746} 747 748 749/* Take PHY/NIC out of powerdown, from Linux */ 750static void 751nfe_power(struct nfe_softc *sc) 752{ 753 uint32_t pwr; 754 755 if ((sc->nfe_flags & NFE_PWR_MGMT) == 0) 756 return; 757 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | NFE_RXTX_BIT2); 758 NFE_WRITE(sc, NFE_MAC_RESET, NFE_MAC_RESET_MAGIC); 759 DELAY(100); 760 NFE_WRITE(sc, NFE_MAC_RESET, 0); 761 DELAY(100); 762 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT2); 763 pwr = NFE_READ(sc, NFE_PWR2_CTL); 764 pwr &= ~NFE_PWR2_WAKEUP_MASK; 765 if (sc->nfe_revid >= 0xa3 && 766 (sc->nfe_devid == PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 || 767 sc->nfe_devid == PCI_PRODUCT_NVIDIA_NFORCE430_LAN2)) 768 pwr |= NFE_PWR2_REVA3; 769 NFE_WRITE(sc, NFE_PWR2_CTL, pwr); 770} 771 772 773static void 774nfe_miibus_statchg(device_t dev) 775{ 776 struct nfe_softc *sc; 777 778 sc = device_get_softc(dev); 779 taskqueue_enqueue(taskqueue_swi, &sc->nfe_link_task); 780} 781 782 783static void 784nfe_link_task(void *arg, int pending) 785{ 786 struct nfe_softc *sc; 787 struct mii_data *mii; 788 struct ifnet *ifp; 789 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET; 790 uint32_t gmask, rxctl, txctl, val; 791 792 sc = (struct nfe_softc *)arg; 793 794 NFE_LOCK(sc); 795 796 mii = device_get_softc(sc->nfe_miibus); 797 ifp = sc->nfe_ifp; 798 if (mii == NULL || ifp == NULL) { 799 NFE_UNLOCK(sc); 800 return; 801 } 802 803 if (mii->mii_media_status & IFM_ACTIVE) { 804 if (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 805 sc->nfe_link = 1; 806 } else 807 sc->nfe_link = 0; 808 809 phy = NFE_READ(sc, NFE_PHY_IFACE); 810 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T); 811 812 seed = NFE_READ(sc, NFE_RNDSEED); 813 seed &= ~NFE_SEED_MASK; 814 815 if (((mii->mii_media_active & IFM_GMASK) & IFM_FDX) == 0) { 816 phy |= NFE_PHY_HDX; /* half-duplex */ 817 misc |= NFE_MISC1_HDX; 818 } 819 820 switch (IFM_SUBTYPE(mii->mii_media_active)) { 821 case IFM_1000_T: /* full-duplex only */ 822 link |= NFE_MEDIA_1000T; 823 seed |= NFE_SEED_1000T; 824 phy |= NFE_PHY_1000T; 825 break; 826 case IFM_100_TX: 827 link |= NFE_MEDIA_100TX; 828 seed |= NFE_SEED_100TX; 829 phy |= NFE_PHY_100TX; 830 break; 831 case IFM_10_T: 832 link |= NFE_MEDIA_10T; 833 seed |= NFE_SEED_10T; 834 break; 835 } 836 837 if ((phy & 0x10000000) != 0) { 838 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) 839 val = NFE_R1_MAGIC_1000; 840 else 841 val = NFE_R1_MAGIC_10_100; 842 } else 843 val = NFE_R1_MAGIC_DEFAULT; 844 NFE_WRITE(sc, NFE_SETUP_R1, val); 845 846 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */ 847 848 NFE_WRITE(sc, NFE_PHY_IFACE, phy); 849 NFE_WRITE(sc, NFE_MISC1, misc); 850 NFE_WRITE(sc, NFE_LINKSPEED, link); 851 852 gmask = mii->mii_media_active & IFM_GMASK; 853 if ((gmask & IFM_FDX) != 0) { 854 /* It seems all hardwares supports Rx pause frames. */ 855 val = NFE_READ(sc, NFE_RXFILTER); 856 if ((gmask & IFM_FLAG0) != 0) 857 val |= NFE_PFF_RX_PAUSE; 858 else 859 val &= ~NFE_PFF_RX_PAUSE; 860 NFE_WRITE(sc, NFE_RXFILTER, val); 861 if ((sc->nfe_flags & NFE_TX_FLOW_CTRL) != 0) { 862 val = NFE_READ(sc, NFE_MISC1); 863 if ((gmask & IFM_FLAG1) != 0) { 864 NFE_WRITE(sc, NFE_TX_PAUSE_FRAME, 865 NFE_TX_PAUSE_FRAME_ENABLE); 866 val |= NFE_MISC1_TX_PAUSE; 867 } else { 868 val &= ~NFE_MISC1_TX_PAUSE; 869 NFE_WRITE(sc, NFE_TX_PAUSE_FRAME, 870 NFE_TX_PAUSE_FRAME_DISABLE); 871 } 872 NFE_WRITE(sc, NFE_MISC1, val); 873 } 874 } else { 875 /* disable rx/tx pause frames */ 876 val = NFE_READ(sc, NFE_RXFILTER); 877 val &= ~NFE_PFF_RX_PAUSE; 878 NFE_WRITE(sc, NFE_RXFILTER, val); 879 if ((sc->nfe_flags & NFE_TX_FLOW_CTRL) != 0) { 880 NFE_WRITE(sc, NFE_TX_PAUSE_FRAME, 881 NFE_TX_PAUSE_FRAME_DISABLE); 882 val = NFE_READ(sc, NFE_MISC1); 883 val &= ~NFE_MISC1_TX_PAUSE; 884 NFE_WRITE(sc, NFE_MISC1, val); 885 } 886 } 887 888 txctl = NFE_READ(sc, NFE_TX_CTL); 889 rxctl = NFE_READ(sc, NFE_RX_CTL); 890 if (sc->nfe_link != 0 && (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 891 txctl |= NFE_TX_START; 892 rxctl |= NFE_RX_START; 893 } else { 894 txctl &= ~NFE_TX_START; 895 rxctl &= ~NFE_RX_START; 896 } 897 NFE_WRITE(sc, NFE_TX_CTL, txctl); 898 NFE_WRITE(sc, NFE_RX_CTL, rxctl); 899 900 NFE_UNLOCK(sc); 901} 902 903 904static int 905nfe_miibus_readreg(device_t dev, int phy, int reg) 906{ 907 struct nfe_softc *sc = device_get_softc(dev); 908 uint32_t val; 909 int ntries; 910 911 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 912 913 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 914 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 915 DELAY(100); 916 } 917 918 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg); 919 920 for (ntries = 0; ntries < NFE_TIMEOUT; ntries++) { 921 DELAY(100); 922 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 923 break; 924 } 925 if (ntries == NFE_TIMEOUT) { 926 DPRINTFN(sc, 2, "timeout waiting for PHY\n"); 927 return 0; 928 } 929 930 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) { 931 DPRINTFN(sc, 2, "could not read PHY\n"); 932 return 0; 933 } 934 935 val = NFE_READ(sc, NFE_PHY_DATA); 936 if (val != 0xffffffff && val != 0) 937 sc->mii_phyaddr = phy; 938 939 DPRINTFN(sc, 2, "mii read phy %d reg 0x%x ret 0x%x\n", phy, reg, val); 940 941 return (val); 942} 943 944 945static int 946nfe_miibus_writereg(device_t dev, int phy, int reg, int val) 947{ 948 struct nfe_softc *sc = device_get_softc(dev); 949 uint32_t ctl; 950 int ntries; 951 952 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 953 954 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 955 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 956 DELAY(100); 957 } 958 959 NFE_WRITE(sc, NFE_PHY_DATA, val); 960 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg; 961 NFE_WRITE(sc, NFE_PHY_CTL, ctl); 962 963 for (ntries = 0; ntries < NFE_TIMEOUT; ntries++) { 964 DELAY(100); 965 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 966 break; 967 } 968#ifdef NFE_DEBUG 969 if (nfedebug >= 2 && ntries == NFE_TIMEOUT) 970 device_printf(sc->nfe_dev, "could not write to PHY\n"); 971#endif 972 return (0); 973} 974 975struct nfe_dmamap_arg { 976 bus_addr_t nfe_busaddr; 977}; 978 979static int 980nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 981{ 982 struct nfe_dmamap_arg ctx; 983 struct nfe_rx_data *data; 984 void *desc; 985 int i, error, descsize; 986 987 if (sc->nfe_flags & NFE_40BIT_ADDR) { 988 desc = ring->desc64; 989 descsize = sizeof (struct nfe_desc64); 990 } else { 991 desc = ring->desc32; 992 descsize = sizeof (struct nfe_desc32); 993 } 994 995 ring->cur = ring->next = 0; 996 997 error = bus_dma_tag_create(sc->nfe_parent_tag, 998 NFE_RING_ALIGN, 0, /* alignment, boundary */ 999 BUS_SPACE_MAXADDR, /* lowaddr */ 1000 BUS_SPACE_MAXADDR, /* highaddr */ 1001 NULL, NULL, /* filter, filterarg */ 1002 NFE_RX_RING_COUNT * descsize, 1, /* maxsize, nsegments */ 1003 NFE_RX_RING_COUNT * descsize, /* maxsegsize */ 1004 0, /* flags */ 1005 NULL, NULL, /* lockfunc, lockarg */ 1006 &ring->rx_desc_tag); 1007 if (error != 0) { 1008 device_printf(sc->nfe_dev, "could not create desc DMA tag\n"); 1009 goto fail; 1010 } 1011 1012 /* allocate memory to desc */ 1013 error = bus_dmamem_alloc(ring->rx_desc_tag, &desc, BUS_DMA_WAITOK | 1014 BUS_DMA_COHERENT | BUS_DMA_ZERO, &ring->rx_desc_map); 1015 if (error != 0) { 1016 device_printf(sc->nfe_dev, "could not create desc DMA map\n"); 1017 goto fail; 1018 } 1019 if (sc->nfe_flags & NFE_40BIT_ADDR) 1020 ring->desc64 = desc; 1021 else 1022 ring->desc32 = desc; 1023 1024 /* map desc to device visible address space */ 1025 ctx.nfe_busaddr = 0; 1026 error = bus_dmamap_load(ring->rx_desc_tag, ring->rx_desc_map, desc, 1027 NFE_RX_RING_COUNT * descsize, nfe_dma_map_segs, &ctx, 0); 1028 if (error != 0) { 1029 device_printf(sc->nfe_dev, "could not load desc DMA map\n"); 1030 goto fail; 1031 } 1032 ring->physaddr = ctx.nfe_busaddr; 1033 1034 error = bus_dma_tag_create(sc->nfe_parent_tag, 1035 1, 0, /* alignment, boundary */ 1036 BUS_SPACE_MAXADDR, /* lowaddr */ 1037 BUS_SPACE_MAXADDR, /* highaddr */ 1038 NULL, NULL, /* filter, filterarg */ 1039 MCLBYTES, 1, /* maxsize, nsegments */ 1040 MCLBYTES, /* maxsegsize */ 1041 0, /* flags */ 1042 NULL, NULL, /* lockfunc, lockarg */ 1043 &ring->rx_data_tag); 1044 if (error != 0) { 1045 device_printf(sc->nfe_dev, "could not create Rx DMA tag\n"); 1046 goto fail; 1047 } 1048 1049 error = bus_dmamap_create(ring->rx_data_tag, 0, &ring->rx_spare_map); 1050 if (error != 0) { 1051 device_printf(sc->nfe_dev, 1052 "could not create Rx DMA spare map\n"); 1053 goto fail; 1054 } 1055 1056 /* 1057 * Pre-allocate Rx buffers and populate Rx ring. 1058 */ 1059 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1060 data = &sc->rxq.data[i]; 1061 data->rx_data_map = NULL; 1062 data->m = NULL; 1063 error = bus_dmamap_create(ring->rx_data_tag, 0, 1064 &data->rx_data_map); 1065 if (error != 0) { 1066 device_printf(sc->nfe_dev, 1067 "could not create Rx DMA map\n"); 1068 goto fail; 1069 } 1070 } 1071 1072fail: 1073 return (error); 1074} 1075 1076 1077static void 1078nfe_alloc_jrx_ring(struct nfe_softc *sc, struct nfe_jrx_ring *ring) 1079{ 1080 struct nfe_dmamap_arg ctx; 1081 struct nfe_rx_data *data; 1082 void *desc; 1083 int i, error, descsize; 1084 1085 if ((sc->nfe_flags & NFE_JUMBO_SUP) == 0) 1086 return; 1087 if (jumbo_disable != 0) { 1088 device_printf(sc->nfe_dev, "disabling jumbo frame support\n"); 1089 sc->nfe_jumbo_disable = 1; 1090 return; 1091 } 1092 1093 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1094 desc = ring->jdesc64; 1095 descsize = sizeof (struct nfe_desc64); 1096 } else { 1097 desc = ring->jdesc32; 1098 descsize = sizeof (struct nfe_desc32); 1099 } 1100 1101 ring->jcur = ring->jnext = 0; 1102 1103 /* Create DMA tag for jumbo Rx ring. */ 1104 error = bus_dma_tag_create(sc->nfe_parent_tag, 1105 NFE_RING_ALIGN, 0, /* alignment, boundary */ 1106 BUS_SPACE_MAXADDR, /* lowaddr */ 1107 BUS_SPACE_MAXADDR, /* highaddr */ 1108 NULL, NULL, /* filter, filterarg */ 1109 NFE_JUMBO_RX_RING_COUNT * descsize, /* maxsize */ 1110 1, /* nsegments */ 1111 NFE_JUMBO_RX_RING_COUNT * descsize, /* maxsegsize */ 1112 0, /* flags */ 1113 NULL, NULL, /* lockfunc, lockarg */ 1114 &ring->jrx_desc_tag); 1115 if (error != 0) { 1116 device_printf(sc->nfe_dev, 1117 "could not create jumbo ring DMA tag\n"); 1118 goto fail; 1119 } 1120 1121 /* Create DMA tag for jumbo Rx buffers. */ 1122 error = bus_dma_tag_create(sc->nfe_parent_tag, 1123 PAGE_SIZE, 0, /* alignment, boundary */ 1124 BUS_SPACE_MAXADDR, /* lowaddr */ 1125 BUS_SPACE_MAXADDR, /* highaddr */ 1126 NULL, NULL, /* filter, filterarg */ 1127 MJUM9BYTES, /* maxsize */ 1128 1, /* nsegments */ 1129 MJUM9BYTES, /* maxsegsize */ 1130 0, /* flags */ 1131 NULL, NULL, /* lockfunc, lockarg */ 1132 &ring->jrx_data_tag); 1133 if (error != 0) { 1134 device_printf(sc->nfe_dev, 1135 "could not create jumbo Rx buffer DMA tag\n"); 1136 goto fail; 1137 } 1138 1139 /* Allocate DMA'able memory and load the DMA map for jumbo Rx ring. */ 1140 error = bus_dmamem_alloc(ring->jrx_desc_tag, &desc, BUS_DMA_WAITOK | 1141 BUS_DMA_COHERENT | BUS_DMA_ZERO, &ring->jrx_desc_map); 1142 if (error != 0) { 1143 device_printf(sc->nfe_dev, 1144 "could not allocate DMA'able memory for jumbo Rx ring\n"); 1145 goto fail; 1146 } 1147 if (sc->nfe_flags & NFE_40BIT_ADDR) 1148 ring->jdesc64 = desc; 1149 else 1150 ring->jdesc32 = desc; 1151 1152 ctx.nfe_busaddr = 0; 1153 error = bus_dmamap_load(ring->jrx_desc_tag, ring->jrx_desc_map, desc, 1154 NFE_JUMBO_RX_RING_COUNT * descsize, nfe_dma_map_segs, &ctx, 0); 1155 if (error != 0) { 1156 device_printf(sc->nfe_dev, 1157 "could not load DMA'able memory for jumbo Rx ring\n"); 1158 goto fail; 1159 } 1160 ring->jphysaddr = ctx.nfe_busaddr; 1161 1162 /* Create DMA maps for jumbo Rx buffers. */ 1163 error = bus_dmamap_create(ring->jrx_data_tag, 0, &ring->jrx_spare_map); 1164 if (error != 0) { 1165 device_printf(sc->nfe_dev, 1166 "could not create jumbo Rx DMA spare map\n"); 1167 goto fail; 1168 } 1169 1170 for (i = 0; i < NFE_JUMBO_RX_RING_COUNT; i++) { 1171 data = &sc->jrxq.jdata[i]; 1172 data->rx_data_map = NULL; 1173 data->m = NULL; 1174 error = bus_dmamap_create(ring->jrx_data_tag, 0, 1175 &data->rx_data_map); 1176 if (error != 0) { 1177 device_printf(sc->nfe_dev, 1178 "could not create jumbo Rx DMA map\n"); 1179 goto fail; 1180 } 1181 } 1182 1183 return; 1184 1185fail: 1186 /* 1187 * Running without jumbo frame support is ok for most cases 1188 * so don't fail on creating dma tag/map for jumbo frame. 1189 */ 1190 nfe_free_jrx_ring(sc, ring); 1191 device_printf(sc->nfe_dev, "disabling jumbo frame support due to " 1192 "resource shortage\n"); 1193 sc->nfe_jumbo_disable = 1; 1194} 1195 1196 1197static int 1198nfe_init_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1199{ 1200 void *desc; 1201 size_t descsize; 1202 int i; 1203 1204 ring->cur = ring->next = 0; 1205 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1206 desc = ring->desc64; 1207 descsize = sizeof (struct nfe_desc64); 1208 } else { 1209 desc = ring->desc32; 1210 descsize = sizeof (struct nfe_desc32); 1211 } 1212 bzero(desc, descsize * NFE_RX_RING_COUNT); 1213 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1214 if (nfe_newbuf(sc, i) != 0) 1215 return (ENOBUFS); 1216 } 1217 1218 bus_dmamap_sync(ring->rx_desc_tag, ring->rx_desc_map, 1219 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1220 1221 return (0); 1222} 1223 1224 1225static int 1226nfe_init_jrx_ring(struct nfe_softc *sc, struct nfe_jrx_ring *ring) 1227{ 1228 void *desc; 1229 size_t descsize; 1230 int i; 1231 1232 ring->jcur = ring->jnext = 0; 1233 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1234 desc = ring->jdesc64; 1235 descsize = sizeof (struct nfe_desc64); 1236 } else { 1237 desc = ring->jdesc32; 1238 descsize = sizeof (struct nfe_desc32); 1239 } 1240 bzero(desc, descsize * NFE_JUMBO_RX_RING_COUNT); 1241 for (i = 0; i < NFE_JUMBO_RX_RING_COUNT; i++) { 1242 if (nfe_jnewbuf(sc, i) != 0) 1243 return (ENOBUFS); 1244 } 1245 1246 bus_dmamap_sync(ring->jrx_desc_tag, ring->jrx_desc_map, 1247 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1248 1249 return (0); 1250} 1251 1252 1253static void 1254nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1255{ 1256 struct nfe_rx_data *data; 1257 void *desc; 1258 int i, descsize; 1259 1260 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1261 desc = ring->desc64; 1262 descsize = sizeof (struct nfe_desc64); 1263 } else { 1264 desc = ring->desc32; 1265 descsize = sizeof (struct nfe_desc32); 1266 } 1267 1268 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1269 data = &ring->data[i]; 1270 if (data->rx_data_map != NULL) { 1271 bus_dmamap_destroy(ring->rx_data_tag, 1272 data->rx_data_map); 1273 data->rx_data_map = NULL; 1274 } 1275 if (data->m != NULL) { 1276 m_freem(data->m); 1277 data->m = NULL; 1278 } 1279 } 1280 if (ring->rx_data_tag != NULL) { 1281 if (ring->rx_spare_map != NULL) { 1282 bus_dmamap_destroy(ring->rx_data_tag, 1283 ring->rx_spare_map); 1284 ring->rx_spare_map = NULL; 1285 } 1286 bus_dma_tag_destroy(ring->rx_data_tag); 1287 ring->rx_data_tag = NULL; 1288 } 1289 1290 if (desc != NULL) { 1291 bus_dmamap_unload(ring->rx_desc_tag, ring->rx_desc_map); 1292 bus_dmamem_free(ring->rx_desc_tag, desc, ring->rx_desc_map); 1293 ring->desc64 = NULL; 1294 ring->desc32 = NULL; 1295 ring->rx_desc_map = NULL; 1296 } 1297 if (ring->rx_desc_tag != NULL) { 1298 bus_dma_tag_destroy(ring->rx_desc_tag); 1299 ring->rx_desc_tag = NULL; 1300 } 1301} 1302 1303 1304static void 1305nfe_free_jrx_ring(struct nfe_softc *sc, struct nfe_jrx_ring *ring) 1306{ 1307 struct nfe_rx_data *data; 1308 void *desc; 1309 int i, descsize; 1310 1311 if ((sc->nfe_flags & NFE_JUMBO_SUP) == 0) 1312 return; 1313 1314 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1315 desc = ring->jdesc64; 1316 descsize = sizeof (struct nfe_desc64); 1317 } else { 1318 desc = ring->jdesc32; 1319 descsize = sizeof (struct nfe_desc32); 1320 } 1321 1322 for (i = 0; i < NFE_JUMBO_RX_RING_COUNT; i++) { 1323 data = &ring->jdata[i]; 1324 if (data->rx_data_map != NULL) { 1325 bus_dmamap_destroy(ring->jrx_data_tag, 1326 data->rx_data_map); 1327 data->rx_data_map = NULL; 1328 } 1329 if (data->m != NULL) { 1330 m_freem(data->m); 1331 data->m = NULL; 1332 } 1333 } 1334 if (ring->jrx_data_tag != NULL) { 1335 if (ring->jrx_spare_map != NULL) { 1336 bus_dmamap_destroy(ring->jrx_data_tag, 1337 ring->jrx_spare_map); 1338 ring->jrx_spare_map = NULL; 1339 } 1340 bus_dma_tag_destroy(ring->jrx_data_tag); 1341 ring->jrx_data_tag = NULL; 1342 } 1343 1344 if (desc != NULL) { 1345 bus_dmamap_unload(ring->jrx_desc_tag, ring->jrx_desc_map); 1346 bus_dmamem_free(ring->jrx_desc_tag, desc, ring->jrx_desc_map); 1347 ring->jdesc64 = NULL; 1348 ring->jdesc32 = NULL; 1349 ring->jrx_desc_map = NULL; 1350 } 1351 1352 if (ring->jrx_desc_tag != NULL) { 1353 bus_dma_tag_destroy(ring->jrx_desc_tag); 1354 ring->jrx_desc_tag = NULL; 1355 } 1356} 1357 1358 1359static int 1360nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1361{ 1362 struct nfe_dmamap_arg ctx; 1363 int i, error; 1364 void *desc; 1365 int descsize; 1366 1367 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1368 desc = ring->desc64; 1369 descsize = sizeof (struct nfe_desc64); 1370 } else { 1371 desc = ring->desc32; 1372 descsize = sizeof (struct nfe_desc32); 1373 } 1374 1375 ring->queued = 0; 1376 ring->cur = ring->next = 0; 1377 1378 error = bus_dma_tag_create(sc->nfe_parent_tag, 1379 NFE_RING_ALIGN, 0, /* alignment, boundary */ 1380 BUS_SPACE_MAXADDR, /* lowaddr */ 1381 BUS_SPACE_MAXADDR, /* highaddr */ 1382 NULL, NULL, /* filter, filterarg */ 1383 NFE_TX_RING_COUNT * descsize, 1, /* maxsize, nsegments */ 1384 NFE_TX_RING_COUNT * descsize, /* maxsegsize */ 1385 0, /* flags */ 1386 NULL, NULL, /* lockfunc, lockarg */ 1387 &ring->tx_desc_tag); 1388 if (error != 0) { 1389 device_printf(sc->nfe_dev, "could not create desc DMA tag\n"); 1390 goto fail; 1391 } 1392 1393 error = bus_dmamem_alloc(ring->tx_desc_tag, &desc, BUS_DMA_WAITOK | 1394 BUS_DMA_COHERENT | BUS_DMA_ZERO, &ring->tx_desc_map); 1395 if (error != 0) { 1396 device_printf(sc->nfe_dev, "could not create desc DMA map\n"); 1397 goto fail; 1398 } 1399 if (sc->nfe_flags & NFE_40BIT_ADDR) 1400 ring->desc64 = desc; 1401 else 1402 ring->desc32 = desc; 1403 1404 ctx.nfe_busaddr = 0; 1405 error = bus_dmamap_load(ring->tx_desc_tag, ring->tx_desc_map, desc, 1406 NFE_TX_RING_COUNT * descsize, nfe_dma_map_segs, &ctx, 0); 1407 if (error != 0) { 1408 device_printf(sc->nfe_dev, "could not load desc DMA map\n"); 1409 goto fail; 1410 } 1411 ring->physaddr = ctx.nfe_busaddr; 1412 1413 error = bus_dma_tag_create(sc->nfe_parent_tag, 1414 1, 0, 1415 BUS_SPACE_MAXADDR, 1416 BUS_SPACE_MAXADDR, 1417 NULL, NULL, 1418 NFE_TSO_MAXSIZE, 1419 NFE_MAX_SCATTER, 1420 NFE_TSO_MAXSGSIZE, 1421 0, 1422 NULL, NULL, 1423 &ring->tx_data_tag); 1424 if (error != 0) { 1425 device_printf(sc->nfe_dev, "could not create Tx DMA tag\n"); 1426 goto fail; 1427 } 1428 1429 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1430 error = bus_dmamap_create(ring->tx_data_tag, 0, 1431 &ring->data[i].tx_data_map); 1432 if (error != 0) { 1433 device_printf(sc->nfe_dev, 1434 "could not create Tx DMA map\n"); 1435 goto fail; 1436 } 1437 } 1438 1439fail: 1440 return (error); 1441} 1442 1443 1444static void 1445nfe_init_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1446{ 1447 void *desc; 1448 size_t descsize; 1449 1450 sc->nfe_force_tx = 0; 1451 ring->queued = 0; 1452 ring->cur = ring->next = 0; 1453 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1454 desc = ring->desc64; 1455 descsize = sizeof (struct nfe_desc64); 1456 } else { 1457 desc = ring->desc32; 1458 descsize = sizeof (struct nfe_desc32); 1459 } 1460 bzero(desc, descsize * NFE_TX_RING_COUNT); 1461 1462 bus_dmamap_sync(ring->tx_desc_tag, ring->tx_desc_map, 1463 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1464} 1465 1466 1467static void 1468nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1469{ 1470 struct nfe_tx_data *data; 1471 void *desc; 1472 int i, descsize; 1473 1474 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1475 desc = ring->desc64; 1476 descsize = sizeof (struct nfe_desc64); 1477 } else { 1478 desc = ring->desc32; 1479 descsize = sizeof (struct nfe_desc32); 1480 } 1481 1482 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1483 data = &ring->data[i]; 1484 1485 if (data->m != NULL) { 1486 bus_dmamap_sync(ring->tx_data_tag, data->tx_data_map, 1487 BUS_DMASYNC_POSTWRITE); 1488 bus_dmamap_unload(ring->tx_data_tag, data->tx_data_map); 1489 m_freem(data->m); 1490 data->m = NULL; 1491 } 1492 if (data->tx_data_map != NULL) { 1493 bus_dmamap_destroy(ring->tx_data_tag, 1494 data->tx_data_map); 1495 data->tx_data_map = NULL; 1496 } 1497 } 1498 1499 if (ring->tx_data_tag != NULL) { 1500 bus_dma_tag_destroy(ring->tx_data_tag); 1501 ring->tx_data_tag = NULL; 1502 } 1503 1504 if (desc != NULL) { 1505 bus_dmamap_sync(ring->tx_desc_tag, ring->tx_desc_map, 1506 BUS_DMASYNC_POSTWRITE); 1507 bus_dmamap_unload(ring->tx_desc_tag, ring->tx_desc_map); 1508 bus_dmamem_free(ring->tx_desc_tag, desc, ring->tx_desc_map); 1509 ring->desc64 = NULL; 1510 ring->desc32 = NULL; 1511 ring->tx_desc_map = NULL; 1512 bus_dma_tag_destroy(ring->tx_desc_tag); 1513 ring->tx_desc_tag = NULL; 1514 } 1515} 1516 1517#ifdef DEVICE_POLLING 1518static poll_handler_t nfe_poll; 1519 1520 1521static void 1522nfe_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1523{ 1524 struct nfe_softc *sc = ifp->if_softc; 1525 uint32_t r; 1526 1527 NFE_LOCK(sc); 1528 1529 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1530 NFE_UNLOCK(sc); 1531 return; 1532 } 1533 1534 if (sc->nfe_framesize > MCLBYTES - ETHER_HDR_LEN) 1535 nfe_jrxeof(sc, count); 1536 else 1537 nfe_rxeof(sc, count); 1538 nfe_txeof(sc); 1539 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1540 taskqueue_enqueue_fast(sc->nfe_tq, &sc->nfe_tx_task); 1541 1542 if (cmd == POLL_AND_CHECK_STATUS) { 1543 if ((r = NFE_READ(sc, sc->nfe_irq_status)) == 0) { 1544 NFE_UNLOCK(sc); 1545 return; 1546 } 1547 NFE_WRITE(sc, sc->nfe_irq_status, r); 1548 1549 if (r & NFE_IRQ_LINK) { 1550 NFE_READ(sc, NFE_PHY_STATUS); 1551 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1552 DPRINTF(sc, "link state changed\n"); 1553 } 1554 } 1555 NFE_UNLOCK(sc); 1556} 1557#endif /* DEVICE_POLLING */ 1558 1559static void 1560nfe_set_intr(struct nfe_softc *sc) 1561{ 1562 1563 if (sc->nfe_msi != 0) 1564 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1565} 1566 1567 1568/* In MSIX, a write to mask reegisters behaves as XOR. */ 1569static __inline void 1570nfe_enable_intr(struct nfe_softc *sc) 1571{ 1572 1573 if (sc->nfe_msix != 0) { 1574 /* XXX Should have a better way to enable interrupts! */ 1575 if (NFE_READ(sc, sc->nfe_irq_mask) == 0) 1576 NFE_WRITE(sc, sc->nfe_irq_mask, sc->nfe_intrs); 1577 } else 1578 NFE_WRITE(sc, sc->nfe_irq_mask, sc->nfe_intrs); 1579} 1580 1581 1582static __inline void 1583nfe_disable_intr(struct nfe_softc *sc) 1584{ 1585 1586 if (sc->nfe_msix != 0) { 1587 /* XXX Should have a better way to disable interrupts! */ 1588 if (NFE_READ(sc, sc->nfe_irq_mask) != 0) 1589 NFE_WRITE(sc, sc->nfe_irq_mask, sc->nfe_nointrs); 1590 } else 1591 NFE_WRITE(sc, sc->nfe_irq_mask, sc->nfe_nointrs); 1592} 1593 1594 1595static int 1596nfe_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1597{ 1598 struct nfe_softc *sc; 1599 struct ifreq *ifr; 1600 struct mii_data *mii; 1601 int error, init, mask; 1602 1603 sc = ifp->if_softc; 1604 ifr = (struct ifreq *) data; 1605 error = 0; 1606 init = 0; 1607 switch (cmd) { 1608 case SIOCSIFMTU: 1609 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > NFE_JUMBO_MTU) 1610 error = EINVAL; 1611 else if (ifp->if_mtu != ifr->ifr_mtu) { 1612 if ((((sc->nfe_flags & NFE_JUMBO_SUP) == 0) || 1613 (sc->nfe_jumbo_disable != 0)) && 1614 ifr->ifr_mtu > ETHERMTU) 1615 error = EINVAL; 1616 else { 1617 NFE_LOCK(sc); 1618 ifp->if_mtu = ifr->ifr_mtu; 1619 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1620 nfe_init_locked(sc); 1621 NFE_UNLOCK(sc); 1622 } 1623 } 1624 break; 1625 case SIOCSIFFLAGS: 1626 NFE_LOCK(sc); 1627 if (ifp->if_flags & IFF_UP) { 1628 /* 1629 * If only the PROMISC or ALLMULTI flag changes, then 1630 * don't do a full re-init of the chip, just update 1631 * the Rx filter. 1632 */ 1633 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) && 1634 ((ifp->if_flags ^ sc->nfe_if_flags) & 1635 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 1636 nfe_setmulti(sc); 1637 else 1638 nfe_init_locked(sc); 1639 } else { 1640 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1641 nfe_stop(ifp); 1642 } 1643 sc->nfe_if_flags = ifp->if_flags; 1644 NFE_UNLOCK(sc); 1645 error = 0; 1646 break; 1647 case SIOCADDMULTI: 1648 case SIOCDELMULTI: 1649 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1650 NFE_LOCK(sc); 1651 nfe_setmulti(sc); 1652 NFE_UNLOCK(sc); 1653 error = 0; 1654 } 1655 break; 1656 case SIOCSIFMEDIA: 1657 case SIOCGIFMEDIA: 1658 mii = device_get_softc(sc->nfe_miibus); 1659 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1660 break; 1661 case SIOCSIFCAP: 1662 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1663#ifdef DEVICE_POLLING 1664 if ((mask & IFCAP_POLLING) != 0) { 1665 if ((ifr->ifr_reqcap & IFCAP_POLLING) != 0) { 1666 error = ether_poll_register(nfe_poll, ifp); 1667 if (error) 1668 break; 1669 NFE_LOCK(sc); 1670 nfe_disable_intr(sc); 1671 ifp->if_capenable |= IFCAP_POLLING; 1672 NFE_UNLOCK(sc); 1673 } else { 1674 error = ether_poll_deregister(ifp); 1675 /* Enable interrupt even in error case */ 1676 NFE_LOCK(sc); 1677 nfe_enable_intr(sc); 1678 ifp->if_capenable &= ~IFCAP_POLLING; 1679 NFE_UNLOCK(sc); 1680 } 1681 } 1682#endif /* DEVICE_POLLING */ 1683 if ((sc->nfe_flags & NFE_HW_CSUM) != 0 && 1684 (mask & IFCAP_HWCSUM) != 0) { 1685 ifp->if_capenable ^= IFCAP_HWCSUM; 1686 if ((IFCAP_TXCSUM & ifp->if_capenable) != 0 && 1687 (IFCAP_TXCSUM & ifp->if_capabilities) != 0) 1688 ifp->if_hwassist |= NFE_CSUM_FEATURES; 1689 else 1690 ifp->if_hwassist &= ~NFE_CSUM_FEATURES; 1691 init++; 1692 } 1693 if ((sc->nfe_flags & NFE_HW_VLAN) != 0 && 1694 (mask & IFCAP_VLAN_HWTAGGING) != 0) { 1695 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1696 init++; 1697 } 1698 /* 1699 * XXX 1700 * It seems that VLAN stripping requires Rx checksum offload. 1701 * Unfortunately FreeBSD has no way to disable only Rx side 1702 * VLAN stripping. So when we know Rx checksum offload is 1703 * disabled turn entire hardware VLAN assist off. 1704 */ 1705 if ((sc->nfe_flags & (NFE_HW_CSUM | NFE_HW_VLAN)) == 1706 (NFE_HW_CSUM | NFE_HW_VLAN)) { 1707 if ((ifp->if_capenable & IFCAP_RXCSUM) == 0) 1708 ifp->if_capenable &= ~IFCAP_VLAN_HWTAGGING; 1709 } 1710 1711 if ((sc->nfe_flags & NFE_HW_CSUM) != 0 && 1712 (mask & IFCAP_TSO4) != 0) { 1713 ifp->if_capenable ^= IFCAP_TSO4; 1714 if ((IFCAP_TSO4 & ifp->if_capenable) != 0 && 1715 (IFCAP_TSO4 & ifp->if_capabilities) != 0) 1716 ifp->if_hwassist |= CSUM_TSO; 1717 else 1718 ifp->if_hwassist &= ~CSUM_TSO; 1719 } 1720 1721 if (init > 0 && (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1722 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1723 nfe_init(sc); 1724 } 1725 if ((sc->nfe_flags & NFE_HW_VLAN) != 0) 1726 VLAN_CAPABILITIES(ifp); 1727 break; 1728 default: 1729 error = ether_ioctl(ifp, cmd, data); 1730 break; 1731 } 1732 1733 return (error); 1734} 1735 1736 1737static int 1738nfe_intr(void *arg) 1739{ 1740 struct nfe_softc *sc; 1741 uint32_t status; 1742 1743 sc = (struct nfe_softc *)arg; 1744 1745 status = NFE_READ(sc, sc->nfe_irq_status); 1746 if (status == 0 || status == 0xffffffff) 1747 return (FILTER_STRAY); 1748 nfe_disable_intr(sc); 1749 taskqueue_enqueue_fast(sc->nfe_tq, &sc->nfe_int_task); 1750 1751 return (FILTER_HANDLED); 1752} 1753 1754 1755static void 1756nfe_int_task(void *arg, int pending) 1757{ 1758 struct nfe_softc *sc = arg; 1759 struct ifnet *ifp = sc->nfe_ifp; 1760 uint32_t r; 1761 int domore; 1762 1763 NFE_LOCK(sc); 1764 1765 if ((r = NFE_READ(sc, sc->nfe_irq_status)) == 0) { 1766 nfe_enable_intr(sc); 1767 NFE_UNLOCK(sc); 1768 return; /* not for us */ 1769 } 1770 NFE_WRITE(sc, sc->nfe_irq_status, r); 1771 1772 DPRINTFN(sc, 5, "nfe_intr: interrupt register %x\n", r); 1773 1774#ifdef DEVICE_POLLING 1775 if (ifp->if_capenable & IFCAP_POLLING) { 1776 NFE_UNLOCK(sc); 1777 return; 1778 } 1779#endif 1780 1781 if (r & NFE_IRQ_LINK) { 1782 NFE_READ(sc, NFE_PHY_STATUS); 1783 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1784 DPRINTF(sc, "link state changed\n"); 1785 } 1786 1787 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1788 NFE_UNLOCK(sc); 1789 nfe_enable_intr(sc); 1790 return; 1791 } 1792 1793 domore = 0; 1794 /* check Rx ring */ 1795 if (sc->nfe_framesize > MCLBYTES - ETHER_HDR_LEN) 1796 domore = nfe_jrxeof(sc, sc->nfe_process_limit); 1797 else 1798 domore = nfe_rxeof(sc, sc->nfe_process_limit); 1799 /* check Tx ring */ 1800 nfe_txeof(sc); 1801 1802 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1803 taskqueue_enqueue_fast(sc->nfe_tq, &sc->nfe_tx_task); 1804 1805 NFE_UNLOCK(sc); 1806 1807 if (domore || (NFE_READ(sc, sc->nfe_irq_status) != 0)) { 1808 taskqueue_enqueue_fast(sc->nfe_tq, &sc->nfe_int_task); 1809 return; 1810 } 1811 1812 /* Reenable interrupts. */ 1813 nfe_enable_intr(sc); 1814} 1815 1816 1817static __inline void 1818nfe_discard_rxbuf(struct nfe_softc *sc, int idx) 1819{ 1820 struct nfe_desc32 *desc32; 1821 struct nfe_desc64 *desc64; 1822 struct nfe_rx_data *data; 1823 struct mbuf *m; 1824 1825 data = &sc->rxq.data[idx]; 1826 m = data->m; 1827 1828 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1829 desc64 = &sc->rxq.desc64[idx]; 1830 /* VLAN packet may have overwritten it. */ 1831 desc64->physaddr[0] = htole32(NFE_ADDR_HI(data->paddr)); 1832 desc64->physaddr[1] = htole32(NFE_ADDR_LO(data->paddr)); 1833 desc64->length = htole16(m->m_len); 1834 desc64->flags = htole16(NFE_RX_READY); 1835 } else { 1836 desc32 = &sc->rxq.desc32[idx]; 1837 desc32->length = htole16(m->m_len); 1838 desc32->flags = htole16(NFE_RX_READY); 1839 } 1840} 1841 1842 1843static __inline void 1844nfe_discard_jrxbuf(struct nfe_softc *sc, int idx) 1845{ 1846 struct nfe_desc32 *desc32; 1847 struct nfe_desc64 *desc64; 1848 struct nfe_rx_data *data; 1849 struct mbuf *m; 1850 1851 data = &sc->jrxq.jdata[idx]; 1852 m = data->m; 1853 1854 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1855 desc64 = &sc->jrxq.jdesc64[idx]; 1856 /* VLAN packet may have overwritten it. */ 1857 desc64->physaddr[0] = htole32(NFE_ADDR_HI(data->paddr)); 1858 desc64->physaddr[1] = htole32(NFE_ADDR_LO(data->paddr)); 1859 desc64->length = htole16(m->m_len); 1860 desc64->flags = htole16(NFE_RX_READY); 1861 } else { 1862 desc32 = &sc->jrxq.jdesc32[idx]; 1863 desc32->length = htole16(m->m_len); 1864 desc32->flags = htole16(NFE_RX_READY); 1865 } 1866} 1867 1868 1869static int 1870nfe_newbuf(struct nfe_softc *sc, int idx) 1871{ 1872 struct nfe_rx_data *data; 1873 struct nfe_desc32 *desc32; 1874 struct nfe_desc64 *desc64; 1875 struct mbuf *m; 1876 bus_dma_segment_t segs[1]; 1877 bus_dmamap_t map; 1878 int nsegs; 1879 1880 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1881 if (m == NULL) 1882 return (ENOBUFS); 1883 1884 m->m_len = m->m_pkthdr.len = MCLBYTES; 1885 m_adj(m, ETHER_ALIGN); 1886 1887 if (bus_dmamap_load_mbuf_sg(sc->rxq.rx_data_tag, sc->rxq.rx_spare_map, 1888 m, segs, &nsegs, BUS_DMA_NOWAIT) != 0) { 1889 m_freem(m); 1890 return (ENOBUFS); 1891 } 1892 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1893 1894 data = &sc->rxq.data[idx]; 1895 if (data->m != NULL) { 1896 bus_dmamap_sync(sc->rxq.rx_data_tag, data->rx_data_map, 1897 BUS_DMASYNC_POSTREAD); 1898 bus_dmamap_unload(sc->rxq.rx_data_tag, data->rx_data_map); 1899 } 1900 map = data->rx_data_map; 1901 data->rx_data_map = sc->rxq.rx_spare_map; 1902 sc->rxq.rx_spare_map = map; 1903 bus_dmamap_sync(sc->rxq.rx_data_tag, data->rx_data_map, 1904 BUS_DMASYNC_PREREAD); 1905 data->paddr = segs[0].ds_addr; 1906 data->m = m; 1907 /* update mapping address in h/w descriptor */ 1908 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1909 desc64 = &sc->rxq.desc64[idx]; 1910 desc64->physaddr[0] = htole32(NFE_ADDR_HI(segs[0].ds_addr)); 1911 desc64->physaddr[1] = htole32(NFE_ADDR_LO(segs[0].ds_addr)); 1912 desc64->length = htole16(segs[0].ds_len); 1913 desc64->flags = htole16(NFE_RX_READY); 1914 } else { 1915 desc32 = &sc->rxq.desc32[idx]; 1916 desc32->physaddr = htole32(NFE_ADDR_LO(segs[0].ds_addr)); 1917 desc32->length = htole16(segs[0].ds_len); 1918 desc32->flags = htole16(NFE_RX_READY); 1919 } 1920 1921 return (0); 1922} 1923 1924 1925static int 1926nfe_jnewbuf(struct nfe_softc *sc, int idx) 1927{ 1928 struct nfe_rx_data *data; 1929 struct nfe_desc32 *desc32; 1930 struct nfe_desc64 *desc64; 1931 struct mbuf *m; 1932 bus_dma_segment_t segs[1]; 1933 bus_dmamap_t map; 1934 int nsegs; 1935 1936 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 1937 if (m == NULL) 1938 return (ENOBUFS); 1939 if ((m->m_flags & M_EXT) == 0) { 1940 m_freem(m); 1941 return (ENOBUFS); 1942 } 1943 m->m_pkthdr.len = m->m_len = MJUM9BYTES; 1944 m_adj(m, ETHER_ALIGN); 1945 1946 if (bus_dmamap_load_mbuf_sg(sc->jrxq.jrx_data_tag, 1947 sc->jrxq.jrx_spare_map, m, segs, &nsegs, BUS_DMA_NOWAIT) != 0) { 1948 m_freem(m); 1949 return (ENOBUFS); 1950 } 1951 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1952 1953 data = &sc->jrxq.jdata[idx]; 1954 if (data->m != NULL) { 1955 bus_dmamap_sync(sc->jrxq.jrx_data_tag, data->rx_data_map, 1956 BUS_DMASYNC_POSTREAD); 1957 bus_dmamap_unload(sc->jrxq.jrx_data_tag, data->rx_data_map); 1958 } 1959 map = data->rx_data_map; 1960 data->rx_data_map = sc->jrxq.jrx_spare_map; 1961 sc->jrxq.jrx_spare_map = map; 1962 bus_dmamap_sync(sc->jrxq.jrx_data_tag, data->rx_data_map, 1963 BUS_DMASYNC_PREREAD); 1964 data->paddr = segs[0].ds_addr; 1965 data->m = m; 1966 /* update mapping address in h/w descriptor */ 1967 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1968 desc64 = &sc->jrxq.jdesc64[idx]; 1969 desc64->physaddr[0] = htole32(NFE_ADDR_HI(segs[0].ds_addr)); 1970 desc64->physaddr[1] = htole32(NFE_ADDR_LO(segs[0].ds_addr)); 1971 desc64->length = htole16(segs[0].ds_len); 1972 desc64->flags = htole16(NFE_RX_READY); 1973 } else { 1974 desc32 = &sc->jrxq.jdesc32[idx]; 1975 desc32->physaddr = htole32(NFE_ADDR_LO(segs[0].ds_addr)); 1976 desc32->length = htole16(segs[0].ds_len); 1977 desc32->flags = htole16(NFE_RX_READY); 1978 } 1979 1980 return (0); 1981} 1982 1983 1984static int 1985nfe_rxeof(struct nfe_softc *sc, int count) 1986{ 1987 struct ifnet *ifp = sc->nfe_ifp; 1988 struct nfe_desc32 *desc32; 1989 struct nfe_desc64 *desc64; 1990 struct nfe_rx_data *data; 1991 struct mbuf *m; 1992 uint16_t flags; 1993 int len, prog; 1994 uint32_t vtag = 0; 1995 1996 NFE_LOCK_ASSERT(sc); 1997 1998 bus_dmamap_sync(sc->rxq.rx_desc_tag, sc->rxq.rx_desc_map, 1999 BUS_DMASYNC_POSTREAD); 2000 2001 for (prog = 0;;NFE_INC(sc->rxq.cur, NFE_RX_RING_COUNT), vtag = 0) { 2002 if (count <= 0) 2003 break; 2004 count--; 2005 2006 data = &sc->rxq.data[sc->rxq.cur]; 2007 2008 if (sc->nfe_flags & NFE_40BIT_ADDR) { 2009 desc64 = &sc->rxq.desc64[sc->rxq.cur]; 2010 vtag = le32toh(desc64->physaddr[1]); 2011 flags = le16toh(desc64->flags); 2012 len = le16toh(desc64->length) & NFE_RX_LEN_MASK; 2013 } else { 2014 desc32 = &sc->rxq.desc32[sc->rxq.cur]; 2015 flags = le16toh(desc32->flags); 2016 len = le16toh(desc32->length) & NFE_RX_LEN_MASK; 2017 } 2018 2019 if (flags & NFE_RX_READY) 2020 break; 2021 prog++; 2022 if ((sc->nfe_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 2023 if (!(flags & NFE_RX_VALID_V1)) { 2024 ifp->if_ierrors++; 2025 nfe_discard_rxbuf(sc, sc->rxq.cur); 2026 continue; 2027 } 2028 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) { 2029 flags &= ~NFE_RX_ERROR; 2030 len--; /* fix buffer length */ 2031 } 2032 } else { 2033 if (!(flags & NFE_RX_VALID_V2)) { 2034 ifp->if_ierrors++; 2035 nfe_discard_rxbuf(sc, sc->rxq.cur); 2036 continue; 2037 } 2038 2039 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) { 2040 flags &= ~NFE_RX_ERROR; 2041 len--; /* fix buffer length */ 2042 } 2043 } 2044 2045 if (flags & NFE_RX_ERROR) { 2046 ifp->if_ierrors++; 2047 nfe_discard_rxbuf(sc, sc->rxq.cur); 2048 continue; 2049 } 2050 2051 m = data->m; 2052 if (nfe_newbuf(sc, sc->rxq.cur) != 0) { 2053 ifp->if_iqdrops++; 2054 nfe_discard_rxbuf(sc, sc->rxq.cur); 2055 continue; 2056 } 2057 2058 if ((vtag & NFE_RX_VTAG) != 0 && 2059 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 2060 m->m_pkthdr.ether_vtag = vtag & 0xffff; 2061 m->m_flags |= M_VLANTAG; 2062 } 2063 2064 m->m_pkthdr.len = m->m_len = len; 2065 m->m_pkthdr.rcvif = ifp; 2066 2067 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) { 2068 if ((flags & NFE_RX_IP_CSUMOK) != 0) { 2069 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2070 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2071 if ((flags & NFE_RX_TCP_CSUMOK) != 0 || 2072 (flags & NFE_RX_UDP_CSUMOK) != 0) { 2073 m->m_pkthdr.csum_flags |= 2074 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2075 m->m_pkthdr.csum_data = 0xffff; 2076 } 2077 } 2078 } 2079 2080 ifp->if_ipackets++; 2081 2082 NFE_UNLOCK(sc); 2083 (*ifp->if_input)(ifp, m); 2084 NFE_LOCK(sc); 2085 } 2086 2087 if (prog > 0) 2088 bus_dmamap_sync(sc->rxq.rx_desc_tag, sc->rxq.rx_desc_map, 2089 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2090 2091 return (count > 0 ? 0 : EAGAIN); 2092} 2093 2094 2095static int 2096nfe_jrxeof(struct nfe_softc *sc, int count) 2097{ 2098 struct ifnet *ifp = sc->nfe_ifp; 2099 struct nfe_desc32 *desc32; 2100 struct nfe_desc64 *desc64; 2101 struct nfe_rx_data *data; 2102 struct mbuf *m; 2103 uint16_t flags; 2104 int len, prog; 2105 uint32_t vtag = 0; 2106 2107 NFE_LOCK_ASSERT(sc); 2108 2109 bus_dmamap_sync(sc->jrxq.jrx_desc_tag, sc->jrxq.jrx_desc_map, 2110 BUS_DMASYNC_POSTREAD); 2111 2112 for (prog = 0;;NFE_INC(sc->jrxq.jcur, NFE_JUMBO_RX_RING_COUNT), 2113 vtag = 0) { 2114 if (count <= 0) 2115 break; 2116 count--; 2117 2118 data = &sc->jrxq.jdata[sc->jrxq.jcur]; 2119 2120 if (sc->nfe_flags & NFE_40BIT_ADDR) { 2121 desc64 = &sc->jrxq.jdesc64[sc->jrxq.jcur]; 2122 vtag = le32toh(desc64->physaddr[1]); 2123 flags = le16toh(desc64->flags); 2124 len = le16toh(desc64->length) & NFE_RX_LEN_MASK; 2125 } else { 2126 desc32 = &sc->jrxq.jdesc32[sc->jrxq.jcur]; 2127 flags = le16toh(desc32->flags); 2128 len = le16toh(desc32->length) & NFE_RX_LEN_MASK; 2129 } 2130 2131 if (flags & NFE_RX_READY) 2132 break; 2133 prog++; 2134 if ((sc->nfe_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 2135 if (!(flags & NFE_RX_VALID_V1)) { 2136 ifp->if_ierrors++; 2137 nfe_discard_jrxbuf(sc, sc->jrxq.jcur); 2138 continue; 2139 } 2140 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) { 2141 flags &= ~NFE_RX_ERROR; 2142 len--; /* fix buffer length */ 2143 } 2144 } else { 2145 if (!(flags & NFE_RX_VALID_V2)) { 2146 ifp->if_ierrors++; 2147 nfe_discard_jrxbuf(sc, sc->jrxq.jcur); 2148 continue; 2149 } 2150 2151 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) { 2152 flags &= ~NFE_RX_ERROR; 2153 len--; /* fix buffer length */ 2154 } 2155 } 2156 2157 if (flags & NFE_RX_ERROR) { 2158 ifp->if_ierrors++; 2159 nfe_discard_jrxbuf(sc, sc->jrxq.jcur); 2160 continue; 2161 } 2162 2163 m = data->m; 2164 if (nfe_jnewbuf(sc, sc->jrxq.jcur) != 0) { 2165 ifp->if_iqdrops++; 2166 nfe_discard_jrxbuf(sc, sc->jrxq.jcur); 2167 continue; 2168 } 2169 2170 if ((vtag & NFE_RX_VTAG) != 0 && 2171 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 2172 m->m_pkthdr.ether_vtag = vtag & 0xffff; 2173 m->m_flags |= M_VLANTAG; 2174 } 2175 2176 m->m_pkthdr.len = m->m_len = len; 2177 m->m_pkthdr.rcvif = ifp; 2178 2179 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) { 2180 if ((flags & NFE_RX_IP_CSUMOK) != 0) { 2181 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2182 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2183 if ((flags & NFE_RX_TCP_CSUMOK) != 0 || 2184 (flags & NFE_RX_UDP_CSUMOK) != 0) { 2185 m->m_pkthdr.csum_flags |= 2186 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2187 m->m_pkthdr.csum_data = 0xffff; 2188 } 2189 } 2190 } 2191 2192 ifp->if_ipackets++; 2193 2194 NFE_UNLOCK(sc); 2195 (*ifp->if_input)(ifp, m); 2196 NFE_LOCK(sc); 2197 } 2198 2199 if (prog > 0) 2200 bus_dmamap_sync(sc->jrxq.jrx_desc_tag, sc->jrxq.jrx_desc_map, 2201 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2202 2203 return (count > 0 ? 0 : EAGAIN); 2204} 2205 2206 2207static void 2208nfe_txeof(struct nfe_softc *sc) 2209{ 2210 struct ifnet *ifp = sc->nfe_ifp; 2211 struct nfe_desc32 *desc32; 2212 struct nfe_desc64 *desc64; 2213 struct nfe_tx_data *data = NULL; 2214 uint16_t flags; 2215 int cons, prog; 2216 2217 NFE_LOCK_ASSERT(sc); 2218 2219 bus_dmamap_sync(sc->txq.tx_desc_tag, sc->txq.tx_desc_map, 2220 BUS_DMASYNC_POSTREAD); 2221 2222 prog = 0; 2223 for (cons = sc->txq.next; cons != sc->txq.cur; 2224 NFE_INC(cons, NFE_TX_RING_COUNT)) { 2225 if (sc->nfe_flags & NFE_40BIT_ADDR) { 2226 desc64 = &sc->txq.desc64[cons]; 2227 flags = le16toh(desc64->flags); 2228 } else { 2229 desc32 = &sc->txq.desc32[cons]; 2230 flags = le16toh(desc32->flags); 2231 } 2232 2233 if (flags & NFE_TX_VALID) 2234 break; 2235 2236 prog++; 2237 sc->txq.queued--; 2238 data = &sc->txq.data[cons]; 2239 2240 if ((sc->nfe_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 2241 if ((flags & NFE_TX_LASTFRAG_V1) == 0) 2242 continue; 2243 if ((flags & NFE_TX_ERROR_V1) != 0) { 2244 device_printf(sc->nfe_dev, 2245 "tx v1 error 0x%4b\n", flags, NFE_V1_TXERR); 2246 2247 ifp->if_oerrors++; 2248 } else 2249 ifp->if_opackets++; 2250 } else { 2251 if ((flags & NFE_TX_LASTFRAG_V2) == 0) 2252 continue; 2253 if ((flags & NFE_TX_ERROR_V2) != 0) { 2254 device_printf(sc->nfe_dev, 2255 "tx v2 error 0x%4b\n", flags, NFE_V2_TXERR); 2256 ifp->if_oerrors++; 2257 } else 2258 ifp->if_opackets++; 2259 } 2260 2261 /* last fragment of the mbuf chain transmitted */ 2262 KASSERT(data->m != NULL, ("%s: freeing NULL mbuf!", __func__)); 2263 bus_dmamap_sync(sc->txq.tx_data_tag, data->tx_data_map, 2264 BUS_DMASYNC_POSTWRITE); 2265 bus_dmamap_unload(sc->txq.tx_data_tag, data->tx_data_map); 2266 m_freem(data->m); 2267 data->m = NULL; 2268 } 2269 2270 if (prog > 0) { 2271 sc->nfe_force_tx = 0; 2272 sc->txq.next = cons; 2273 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2274 if (sc->txq.queued == 0) 2275 sc->nfe_watchdog_timer = 0; 2276 } 2277} 2278 2279static int 2280nfe_encap(struct nfe_softc *sc, struct mbuf **m_head) 2281{ 2282 struct nfe_desc32 *desc32 = NULL; 2283 struct nfe_desc64 *desc64 = NULL; 2284 bus_dmamap_t map; 2285 bus_dma_segment_t segs[NFE_MAX_SCATTER]; 2286 int error, i, nsegs, prod, si; 2287 uint32_t tso_segsz; 2288 uint16_t cflags, flags; 2289 struct mbuf *m; 2290 2291 prod = si = sc->txq.cur; 2292 map = sc->txq.data[prod].tx_data_map; 2293 2294 error = bus_dmamap_load_mbuf_sg(sc->txq.tx_data_tag, map, *m_head, segs, 2295 &nsegs, BUS_DMA_NOWAIT); 2296 if (error == EFBIG) { 2297 m = m_collapse(*m_head, M_DONTWAIT, NFE_MAX_SCATTER); 2298 if (m == NULL) { 2299 m_freem(*m_head); 2300 *m_head = NULL; 2301 return (ENOBUFS); 2302 } 2303 *m_head = m; 2304 error = bus_dmamap_load_mbuf_sg(sc->txq.tx_data_tag, map, 2305 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2306 if (error != 0) { 2307 m_freem(*m_head); 2308 *m_head = NULL; 2309 return (ENOBUFS); 2310 } 2311 } else if (error != 0) 2312 return (error); 2313 if (nsegs == 0) { 2314 m_freem(*m_head); 2315 *m_head = NULL; 2316 return (EIO); 2317 } 2318 2319 if (sc->txq.queued + nsegs >= NFE_TX_RING_COUNT - 2) { 2320 bus_dmamap_unload(sc->txq.tx_data_tag, map); 2321 return (ENOBUFS); 2322 } 2323 2324 m = *m_head; 2325 cflags = flags = 0; 2326 tso_segsz = 0; 2327 if ((m->m_pkthdr.csum_flags & NFE_CSUM_FEATURES) != 0) { 2328 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 2329 cflags |= NFE_TX_IP_CSUM; 2330 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 2331 cflags |= NFE_TX_TCP_UDP_CSUM; 2332 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2333 cflags |= NFE_TX_TCP_UDP_CSUM; 2334 } 2335 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2336 tso_segsz = (uint32_t)m->m_pkthdr.tso_segsz << 2337 NFE_TX_TSO_SHIFT; 2338 cflags &= ~(NFE_TX_IP_CSUM | NFE_TX_TCP_UDP_CSUM); 2339 cflags |= NFE_TX_TSO; 2340 } 2341 2342 for (i = 0; i < nsegs; i++) { 2343 if (sc->nfe_flags & NFE_40BIT_ADDR) { 2344 desc64 = &sc->txq.desc64[prod]; 2345 desc64->physaddr[0] = 2346 htole32(NFE_ADDR_HI(segs[i].ds_addr)); 2347 desc64->physaddr[1] = 2348 htole32(NFE_ADDR_LO(segs[i].ds_addr)); 2349 desc64->vtag = 0; 2350 desc64->length = htole16(segs[i].ds_len - 1); 2351 desc64->flags = htole16(flags); 2352 } else { 2353 desc32 = &sc->txq.desc32[prod]; 2354 desc32->physaddr = 2355 htole32(NFE_ADDR_LO(segs[i].ds_addr)); 2356 desc32->length = htole16(segs[i].ds_len - 1); 2357 desc32->flags = htole16(flags); 2358 } 2359 2360 /* 2361 * Setting of the valid bit in the first descriptor is 2362 * deferred until the whole chain is fully setup. 2363 */ 2364 flags |= NFE_TX_VALID; 2365 2366 sc->txq.queued++; 2367 NFE_INC(prod, NFE_TX_RING_COUNT); 2368 } 2369 2370 /* 2371 * the whole mbuf chain has been DMA mapped, fix last/first descriptor. 2372 * csum flags, vtag and TSO belong to the first fragment only. 2373 */ 2374 if (sc->nfe_flags & NFE_40BIT_ADDR) { 2375 desc64->flags |= htole16(NFE_TX_LASTFRAG_V2); 2376 desc64 = &sc->txq.desc64[si]; 2377 if ((m->m_flags & M_VLANTAG) != 0) 2378 desc64->vtag = htole32(NFE_TX_VTAG | 2379 m->m_pkthdr.ether_vtag); 2380 if (tso_segsz != 0) { 2381 /* 2382 * XXX 2383 * The following indicates the descriptor element 2384 * is a 32bit quantity. 2385 */ 2386 desc64->length |= htole16((uint16_t)tso_segsz); 2387 desc64->flags |= htole16(tso_segsz >> 16); 2388 } 2389 /* 2390 * finally, set the valid/checksum/TSO bit in the first 2391 * descriptor. 2392 */ 2393 desc64->flags |= htole16(NFE_TX_VALID | cflags); 2394 } else { 2395 if (sc->nfe_flags & NFE_JUMBO_SUP) 2396 desc32->flags |= htole16(NFE_TX_LASTFRAG_V2); 2397 else 2398 desc32->flags |= htole16(NFE_TX_LASTFRAG_V1); 2399 desc32 = &sc->txq.desc32[si]; 2400 if (tso_segsz != 0) { 2401 /* 2402 * XXX 2403 * The following indicates the descriptor element 2404 * is a 32bit quantity. 2405 */ 2406 desc32->length |= htole16((uint16_t)tso_segsz); 2407 desc32->flags |= htole16(tso_segsz >> 16); 2408 } 2409 /* 2410 * finally, set the valid/checksum/TSO bit in the first 2411 * descriptor. 2412 */ 2413 desc32->flags |= htole16(NFE_TX_VALID | cflags); 2414 } 2415 2416 sc->txq.cur = prod; 2417 prod = (prod + NFE_TX_RING_COUNT - 1) % NFE_TX_RING_COUNT; 2418 sc->txq.data[si].tx_data_map = sc->txq.data[prod].tx_data_map; 2419 sc->txq.data[prod].tx_data_map = map; 2420 sc->txq.data[prod].m = m; 2421 2422 bus_dmamap_sync(sc->txq.tx_data_tag, map, BUS_DMASYNC_PREWRITE); 2423 2424 return (0); 2425} 2426 2427 2428static void 2429nfe_setmulti(struct nfe_softc *sc) 2430{ 2431 struct ifnet *ifp = sc->nfe_ifp; 2432 struct ifmultiaddr *ifma; 2433 int i; 2434 uint32_t filter; 2435 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN]; 2436 uint8_t etherbroadcastaddr[ETHER_ADDR_LEN] = { 2437 0xff, 0xff, 0xff, 0xff, 0xff, 0xff 2438 }; 2439 2440 NFE_LOCK_ASSERT(sc); 2441 2442 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 2443 bzero(addr, ETHER_ADDR_LEN); 2444 bzero(mask, ETHER_ADDR_LEN); 2445 goto done; 2446 } 2447 2448 bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN); 2449 bcopy(etherbroadcastaddr, mask, ETHER_ADDR_LEN); 2450 2451 IF_ADDR_LOCK(ifp); 2452 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2453 u_char *addrp; 2454 2455 if (ifma->ifma_addr->sa_family != AF_LINK) 2456 continue; 2457 2458 addrp = LLADDR((struct sockaddr_dl *) ifma->ifma_addr); 2459 for (i = 0; i < ETHER_ADDR_LEN; i++) { 2460 u_int8_t mcaddr = addrp[i]; 2461 addr[i] &= mcaddr; 2462 mask[i] &= ~mcaddr; 2463 } 2464 } 2465 IF_ADDR_UNLOCK(ifp); 2466 2467 for (i = 0; i < ETHER_ADDR_LEN; i++) { 2468 mask[i] |= addr[i]; 2469 } 2470 2471done: 2472 addr[0] |= 0x01; /* make sure multicast bit is set */ 2473 2474 NFE_WRITE(sc, NFE_MULTIADDR_HI, 2475 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 2476 NFE_WRITE(sc, NFE_MULTIADDR_LO, 2477 addr[5] << 8 | addr[4]); 2478 NFE_WRITE(sc, NFE_MULTIMASK_HI, 2479 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]); 2480 NFE_WRITE(sc, NFE_MULTIMASK_LO, 2481 mask[5] << 8 | mask[4]); 2482 2483 filter = NFE_READ(sc, NFE_RXFILTER); 2484 filter &= NFE_PFF_RX_PAUSE; 2485 filter |= NFE_RXFILTER_MAGIC; 2486 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PFF_PROMISC : NFE_PFF_U2M; 2487 NFE_WRITE(sc, NFE_RXFILTER, filter); 2488} 2489 2490 2491static void 2492nfe_tx_task(void *arg, int pending) 2493{ 2494 struct ifnet *ifp; 2495 2496 ifp = (struct ifnet *)arg; 2497 nfe_start(ifp); 2498} 2499 2500 2501static void 2502nfe_start(struct ifnet *ifp) 2503{ 2504 struct nfe_softc *sc = ifp->if_softc; 2505 struct mbuf *m0; 2506 int enq; 2507 2508 NFE_LOCK(sc); 2509 2510 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2511 IFF_DRV_RUNNING || sc->nfe_link == 0) { 2512 NFE_UNLOCK(sc); 2513 return; 2514 } 2515 2516 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) { 2517 IFQ_DRV_DEQUEUE(&ifp->if_snd, m0); 2518 if (m0 == NULL) 2519 break; 2520 2521 if (nfe_encap(sc, &m0) != 0) { 2522 if (m0 == NULL) 2523 break; 2524 IFQ_DRV_PREPEND(&ifp->if_snd, m0); 2525 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2526 break; 2527 } 2528 enq++; 2529 ETHER_BPF_MTAP(ifp, m0); 2530 } 2531 2532 if (enq > 0) { 2533 bus_dmamap_sync(sc->txq.tx_desc_tag, sc->txq.tx_desc_map, 2534 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2535 2536 /* kick Tx */ 2537 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl); 2538 2539 /* 2540 * Set a timeout in case the chip goes out to lunch. 2541 */ 2542 sc->nfe_watchdog_timer = 5; 2543 } 2544 2545 NFE_UNLOCK(sc); 2546} 2547 2548 2549static void 2550nfe_watchdog(struct ifnet *ifp) 2551{ 2552 struct nfe_softc *sc = ifp->if_softc; 2553 2554 if (sc->nfe_watchdog_timer == 0 || --sc->nfe_watchdog_timer) 2555 return; 2556 2557 /* Check if we've lost Tx completion interrupt. */ 2558 nfe_txeof(sc); 2559 if (sc->txq.queued == 0) { 2560 if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 2561 "-- recovering\n"); 2562 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2563 taskqueue_enqueue_fast(sc->nfe_tq, &sc->nfe_tx_task); 2564 return; 2565 } 2566 /* Check if we've lost start Tx command. */ 2567 sc->nfe_force_tx++; 2568 if (sc->nfe_force_tx <= 3) { 2569 /* 2570 * If this is the case for watchdog timeout, the following 2571 * code should go to nfe_txeof(). 2572 */ 2573 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl); 2574 return; 2575 } 2576 sc->nfe_force_tx = 0; 2577 2578 if_printf(ifp, "watchdog timeout\n"); 2579 2580 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2581 ifp->if_oerrors++; 2582 nfe_init_locked(sc); 2583} 2584 2585 2586static void 2587nfe_init(void *xsc) 2588{ 2589 struct nfe_softc *sc = xsc; 2590 2591 NFE_LOCK(sc); 2592 nfe_init_locked(sc); 2593 NFE_UNLOCK(sc); 2594} 2595 2596 2597static void 2598nfe_init_locked(void *xsc) 2599{ 2600 struct nfe_softc *sc = xsc; 2601 struct ifnet *ifp = sc->nfe_ifp; 2602 struct mii_data *mii; 2603 uint32_t val; 2604 int error; 2605 2606 NFE_LOCK_ASSERT(sc); 2607 2608 mii = device_get_softc(sc->nfe_miibus); 2609 2610 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2611 return; 2612 2613 nfe_stop(ifp); 2614 2615 sc->nfe_framesize = ifp->if_mtu + NFE_RX_HEADERS; 2616 2617 nfe_init_tx_ring(sc, &sc->txq); 2618 if (sc->nfe_framesize > (MCLBYTES - ETHER_HDR_LEN)) 2619 error = nfe_init_jrx_ring(sc, &sc->jrxq); 2620 else 2621 error = nfe_init_rx_ring(sc, &sc->rxq); 2622 if (error != 0) { 2623 device_printf(sc->nfe_dev, 2624 "initialization failed: no memory for rx buffers\n"); 2625 nfe_stop(ifp); 2626 return; 2627 } 2628 2629 val = 0; 2630 if ((sc->nfe_flags & NFE_CORRECT_MACADDR) != 0) 2631 val |= NFE_MAC_ADDR_INORDER; 2632 NFE_WRITE(sc, NFE_TX_UNK, val); 2633 NFE_WRITE(sc, NFE_STATUS, 0); 2634 2635 if ((sc->nfe_flags & NFE_TX_FLOW_CTRL) != 0) 2636 NFE_WRITE(sc, NFE_TX_PAUSE_FRAME, NFE_TX_PAUSE_FRAME_DISABLE); 2637 2638 sc->rxtxctl = NFE_RXTX_BIT2; 2639 if (sc->nfe_flags & NFE_40BIT_ADDR) 2640 sc->rxtxctl |= NFE_RXTX_V3MAGIC; 2641 else if (sc->nfe_flags & NFE_JUMBO_SUP) 2642 sc->rxtxctl |= NFE_RXTX_V2MAGIC; 2643 2644 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2645 sc->rxtxctl |= NFE_RXTX_RXCSUM; 2646 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2647 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT | NFE_RXTX_VTAG_STRIP; 2648 2649 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl); 2650 DELAY(10); 2651 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 2652 2653 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2654 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE); 2655 else 2656 NFE_WRITE(sc, NFE_VTAG_CTL, 0); 2657 2658 NFE_WRITE(sc, NFE_SETUP_R6, 0); 2659 2660 /* set MAC address */ 2661 nfe_set_macaddr(sc, IF_LLADDR(ifp)); 2662 2663 /* tell MAC where rings are in memory */ 2664 if (sc->nfe_framesize > MCLBYTES - ETHER_HDR_LEN) { 2665 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, 2666 NFE_ADDR_HI(sc->jrxq.jphysaddr)); 2667 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, 2668 NFE_ADDR_LO(sc->jrxq.jphysaddr)); 2669 } else { 2670 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, 2671 NFE_ADDR_HI(sc->rxq.physaddr)); 2672 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, 2673 NFE_ADDR_LO(sc->rxq.physaddr)); 2674 } 2675 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, NFE_ADDR_HI(sc->txq.physaddr)); 2676 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, NFE_ADDR_LO(sc->txq.physaddr)); 2677 2678 NFE_WRITE(sc, NFE_RING_SIZE, 2679 (NFE_RX_RING_COUNT - 1) << 16 | 2680 (NFE_TX_RING_COUNT - 1)); 2681 2682 NFE_WRITE(sc, NFE_RXBUFSZ, sc->nfe_framesize); 2683 2684 /* force MAC to wakeup */ 2685 val = NFE_READ(sc, NFE_PWR_STATE); 2686 if ((val & NFE_PWR_WAKEUP) == 0) 2687 NFE_WRITE(sc, NFE_PWR_STATE, val | NFE_PWR_WAKEUP); 2688 DELAY(10); 2689 val = NFE_READ(sc, NFE_PWR_STATE); 2690 NFE_WRITE(sc, NFE_PWR_STATE, val | NFE_PWR_VALID); 2691 2692#if 1 2693 /* configure interrupts coalescing/mitigation */ 2694 NFE_WRITE(sc, NFE_IMTIMER, NFE_IM_DEFAULT); 2695#else 2696 /* no interrupt mitigation: one interrupt per packet */ 2697 NFE_WRITE(sc, NFE_IMTIMER, 970); 2698#endif 2699 2700 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC_10_100); 2701 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC); 2702 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC); 2703 2704 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */ 2705 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC); 2706 2707 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC); 2708 NFE_WRITE(sc, NFE_WOL_CTL, NFE_WOL_MAGIC); 2709 2710 sc->rxtxctl &= ~NFE_RXTX_BIT2; 2711 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 2712 DELAY(10); 2713 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl); 2714 2715 /* set Rx filter */ 2716 nfe_setmulti(sc); 2717 2718 /* enable Rx */ 2719 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START); 2720 2721 /* enable Tx */ 2722 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START); 2723 2724 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 2725 2726#ifdef DEVICE_POLLING 2727 if (ifp->if_capenable & IFCAP_POLLING) 2728 nfe_disable_intr(sc); 2729 else 2730#endif 2731 nfe_set_intr(sc); 2732 nfe_enable_intr(sc); /* enable interrupts */ 2733 2734 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2735 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2736 2737 sc->nfe_link = 0; 2738 mii_mediachg(mii); 2739 2740 callout_reset(&sc->nfe_stat_ch, hz, nfe_tick, sc); 2741} 2742 2743 2744static void 2745nfe_stop(struct ifnet *ifp) 2746{ 2747 struct nfe_softc *sc = ifp->if_softc; 2748 struct nfe_rx_ring *rx_ring; 2749 struct nfe_jrx_ring *jrx_ring; 2750 struct nfe_tx_ring *tx_ring; 2751 struct nfe_rx_data *rdata; 2752 struct nfe_tx_data *tdata; 2753 int i; 2754 2755 NFE_LOCK_ASSERT(sc); 2756 2757 sc->nfe_watchdog_timer = 0; 2758 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2759 2760 callout_stop(&sc->nfe_stat_ch); 2761 2762 /* abort Tx */ 2763 NFE_WRITE(sc, NFE_TX_CTL, 0); 2764 2765 /* disable Rx */ 2766 NFE_WRITE(sc, NFE_RX_CTL, 0); 2767 2768 /* disable interrupts */ 2769 nfe_disable_intr(sc); 2770 2771 sc->nfe_link = 0; 2772 2773 /* free Rx and Tx mbufs still in the queues. */ 2774 rx_ring = &sc->rxq; 2775 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 2776 rdata = &rx_ring->data[i]; 2777 if (rdata->m != NULL) { 2778 bus_dmamap_sync(rx_ring->rx_data_tag, 2779 rdata->rx_data_map, BUS_DMASYNC_POSTREAD); 2780 bus_dmamap_unload(rx_ring->rx_data_tag, 2781 rdata->rx_data_map); 2782 m_freem(rdata->m); 2783 rdata->m = NULL; 2784 } 2785 } 2786 2787 if ((sc->nfe_flags & NFE_JUMBO_SUP) != 0) { 2788 jrx_ring = &sc->jrxq; 2789 for (i = 0; i < NFE_JUMBO_RX_RING_COUNT; i++) { 2790 rdata = &jrx_ring->jdata[i]; 2791 if (rdata->m != NULL) { 2792 bus_dmamap_sync(jrx_ring->jrx_data_tag, 2793 rdata->rx_data_map, BUS_DMASYNC_POSTREAD); 2794 bus_dmamap_unload(jrx_ring->jrx_data_tag, 2795 rdata->rx_data_map); 2796 m_freem(rdata->m); 2797 rdata->m = NULL; 2798 } 2799 } 2800 } 2801 2802 tx_ring = &sc->txq; 2803 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 2804 tdata = &tx_ring->data[i]; 2805 if (tdata->m != NULL) { 2806 bus_dmamap_sync(tx_ring->tx_data_tag, 2807 tdata->tx_data_map, BUS_DMASYNC_POSTWRITE); 2808 bus_dmamap_unload(tx_ring->tx_data_tag, 2809 tdata->tx_data_map); 2810 m_freem(tdata->m); 2811 tdata->m = NULL; 2812 } 2813 } 2814} 2815 2816 2817static int 2818nfe_ifmedia_upd(struct ifnet *ifp) 2819{ 2820 struct nfe_softc *sc = ifp->if_softc; 2821 struct mii_data *mii; 2822 2823 NFE_LOCK(sc); 2824 mii = device_get_softc(sc->nfe_miibus); 2825 mii_mediachg(mii); 2826 NFE_UNLOCK(sc); 2827 2828 return (0); 2829} 2830 2831 2832static void 2833nfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2834{ 2835 struct nfe_softc *sc; 2836 struct mii_data *mii; 2837 2838 sc = ifp->if_softc; 2839 2840 NFE_LOCK(sc); 2841 mii = device_get_softc(sc->nfe_miibus); 2842 mii_pollstat(mii); 2843 NFE_UNLOCK(sc); 2844 2845 ifmr->ifm_active = mii->mii_media_active; 2846 ifmr->ifm_status = mii->mii_media_status; 2847} 2848 2849 2850void 2851nfe_tick(void *xsc) 2852{ 2853 struct nfe_softc *sc; 2854 struct mii_data *mii; 2855 struct ifnet *ifp; 2856 2857 sc = (struct nfe_softc *)xsc; 2858 2859 NFE_LOCK_ASSERT(sc); 2860 2861 ifp = sc->nfe_ifp; 2862 2863 mii = device_get_softc(sc->nfe_miibus); 2864 mii_tick(mii); 2865 nfe_watchdog(ifp); 2866 callout_reset(&sc->nfe_stat_ch, hz, nfe_tick, sc); 2867} 2868 2869 2870static int 2871nfe_shutdown(device_t dev) 2872{ 2873 struct nfe_softc *sc; 2874 struct ifnet *ifp; 2875 2876 sc = device_get_softc(dev); 2877 2878 NFE_LOCK(sc); 2879 ifp = sc->nfe_ifp; 2880 nfe_stop(ifp); 2881 /* nfe_reset(sc); */ 2882 NFE_UNLOCK(sc); 2883 2884 return (0); 2885} 2886 2887 2888static void 2889nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr) 2890{ 2891 uint32_t val; 2892 2893 if ((sc->nfe_flags & NFE_CORRECT_MACADDR) == 0) { 2894 val = NFE_READ(sc, NFE_MACADDR_LO); 2895 addr[0] = (val >> 8) & 0xff; 2896 addr[1] = (val & 0xff); 2897 2898 val = NFE_READ(sc, NFE_MACADDR_HI); 2899 addr[2] = (val >> 24) & 0xff; 2900 addr[3] = (val >> 16) & 0xff; 2901 addr[4] = (val >> 8) & 0xff; 2902 addr[5] = (val & 0xff); 2903 } else { 2904 val = NFE_READ(sc, NFE_MACADDR_LO); 2905 addr[5] = (val >> 8) & 0xff; 2906 addr[4] = (val & 0xff); 2907 2908 val = NFE_READ(sc, NFE_MACADDR_HI); 2909 addr[3] = (val >> 24) & 0xff; 2910 addr[2] = (val >> 16) & 0xff; 2911 addr[1] = (val >> 8) & 0xff; 2912 addr[0] = (val & 0xff); 2913 } 2914} 2915 2916 2917static void 2918nfe_set_macaddr(struct nfe_softc *sc, uint8_t *addr) 2919{ 2920 2921 NFE_WRITE(sc, NFE_MACADDR_LO, addr[5] << 8 | addr[4]); 2922 NFE_WRITE(sc, NFE_MACADDR_HI, addr[3] << 24 | addr[2] << 16 | 2923 addr[1] << 8 | addr[0]); 2924} 2925 2926 2927/* 2928 * Map a single buffer address. 2929 */ 2930 2931static void 2932nfe_dma_map_segs(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2933{ 2934 struct nfe_dmamap_arg *ctx; 2935 2936 if (error != 0) 2937 return; 2938 2939 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 2940 2941 ctx = (struct nfe_dmamap_arg *)arg; 2942 ctx->nfe_busaddr = segs[0].ds_addr; 2943} 2944 2945 2946static int 2947sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2948{ 2949 int error, value; 2950 2951 if (!arg1) 2952 return (EINVAL); 2953 value = *(int *)arg1; 2954 error = sysctl_handle_int(oidp, &value, 0, req); 2955 if (error || !req->newptr) 2956 return (error); 2957 if (value < low || value > high) 2958 return (EINVAL); 2959 *(int *)arg1 = value; 2960 2961 return (0); 2962} 2963 2964 2965static int 2966sysctl_hw_nfe_proc_limit(SYSCTL_HANDLER_ARGS) 2967{ 2968 2969 return (sysctl_int_range(oidp, arg1, arg2, req, NFE_PROC_MIN, 2970 NFE_PROC_MAX)); 2971} 2972