if_nfe.c revision 264293
1/* $OpenBSD: if_nfe.c,v 1.54 2006/04/07 12:38:12 jsg Exp $ */ 2 3/*- 4 * Copyright (c) 2006 Shigeaki Tagashira <shigeaki@se.hiroshima-u.ac.jp> 5 * Copyright (c) 2006 Damien Bergamini <damien.bergamini@free.fr> 6 * Copyright (c) 2005, 2006 Jonathan Gray <jsg@openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21/* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */ 22 23#include <sys/cdefs.h> 24__FBSDID("$FreeBSD: head/sys/dev/nfe/if_nfe.c 264293 2014-04-09 05:15:40Z yongari $"); 25 26#ifdef HAVE_KERNEL_OPTION_HEADERS 27#include "opt_device_polling.h" 28#endif 29 30#include <sys/param.h> 31#include <sys/endian.h> 32#include <sys/systm.h> 33#include <sys/sockio.h> 34#include <sys/mbuf.h> 35#include <sys/malloc.h> 36#include <sys/module.h> 37#include <sys/kernel.h> 38#include <sys/queue.h> 39#include <sys/socket.h> 40#include <sys/sysctl.h> 41#include <sys/taskqueue.h> 42 43#include <net/if.h> 44#include <net/if_var.h> 45#include <net/if_arp.h> 46#include <net/ethernet.h> 47#include <net/if_dl.h> 48#include <net/if_media.h> 49#include <net/if_types.h> 50#include <net/if_vlan_var.h> 51 52#include <net/bpf.h> 53 54#include <machine/bus.h> 55#include <machine/resource.h> 56#include <sys/bus.h> 57#include <sys/rman.h> 58 59#include <dev/mii/mii.h> 60#include <dev/mii/miivar.h> 61 62#include <dev/pci/pcireg.h> 63#include <dev/pci/pcivar.h> 64 65#include <dev/nfe/if_nfereg.h> 66#include <dev/nfe/if_nfevar.h> 67 68MODULE_DEPEND(nfe, pci, 1, 1, 1); 69MODULE_DEPEND(nfe, ether, 1, 1, 1); 70MODULE_DEPEND(nfe, miibus, 1, 1, 1); 71 72/* "device miibus" required. See GENERIC if you get errors here. */ 73#include "miibus_if.h" 74 75static int nfe_probe(device_t); 76static int nfe_attach(device_t); 77static int nfe_detach(device_t); 78static int nfe_suspend(device_t); 79static int nfe_resume(device_t); 80static int nfe_shutdown(device_t); 81static int nfe_can_use_msix(struct nfe_softc *); 82static int nfe_detect_msik9(struct nfe_softc *); 83static void nfe_power(struct nfe_softc *); 84static int nfe_miibus_readreg(device_t, int, int); 85static int nfe_miibus_writereg(device_t, int, int, int); 86static void nfe_miibus_statchg(device_t); 87static void nfe_mac_config(struct nfe_softc *, struct mii_data *); 88static void nfe_set_intr(struct nfe_softc *); 89static __inline void nfe_enable_intr(struct nfe_softc *); 90static __inline void nfe_disable_intr(struct nfe_softc *); 91static int nfe_ioctl(struct ifnet *, u_long, caddr_t); 92static void nfe_alloc_msix(struct nfe_softc *, int); 93static int nfe_intr(void *); 94static void nfe_int_task(void *, int); 95static __inline void nfe_discard_rxbuf(struct nfe_softc *, int); 96static __inline void nfe_discard_jrxbuf(struct nfe_softc *, int); 97static int nfe_newbuf(struct nfe_softc *, int); 98static int nfe_jnewbuf(struct nfe_softc *, int); 99static int nfe_rxeof(struct nfe_softc *, int, int *); 100static int nfe_jrxeof(struct nfe_softc *, int, int *); 101static void nfe_txeof(struct nfe_softc *); 102static int nfe_encap(struct nfe_softc *, struct mbuf **); 103static void nfe_setmulti(struct nfe_softc *); 104static void nfe_start(struct ifnet *); 105static void nfe_start_locked(struct ifnet *); 106static void nfe_watchdog(struct ifnet *); 107static void nfe_init(void *); 108static void nfe_init_locked(void *); 109static void nfe_stop(struct ifnet *); 110static int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 111static void nfe_alloc_jrx_ring(struct nfe_softc *, struct nfe_jrx_ring *); 112static int nfe_init_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 113static int nfe_init_jrx_ring(struct nfe_softc *, struct nfe_jrx_ring *); 114static void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 115static void nfe_free_jrx_ring(struct nfe_softc *, struct nfe_jrx_ring *); 116static int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 117static void nfe_init_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 118static void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 119static int nfe_ifmedia_upd(struct ifnet *); 120static void nfe_ifmedia_sts(struct ifnet *, struct ifmediareq *); 121static void nfe_tick(void *); 122static void nfe_get_macaddr(struct nfe_softc *, uint8_t *); 123static void nfe_set_macaddr(struct nfe_softc *, uint8_t *); 124static void nfe_dma_map_segs(void *, bus_dma_segment_t *, int, int); 125 126static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 127static int sysctl_hw_nfe_proc_limit(SYSCTL_HANDLER_ARGS); 128static void nfe_sysctl_node(struct nfe_softc *); 129static void nfe_stats_clear(struct nfe_softc *); 130static void nfe_stats_update(struct nfe_softc *); 131static void nfe_set_linkspeed(struct nfe_softc *); 132static void nfe_set_wol(struct nfe_softc *); 133 134#ifdef NFE_DEBUG 135static int nfedebug = 0; 136#define DPRINTF(sc, ...) do { \ 137 if (nfedebug) \ 138 device_printf((sc)->nfe_dev, __VA_ARGS__); \ 139} while (0) 140#define DPRINTFN(sc, n, ...) do { \ 141 if (nfedebug >= (n)) \ 142 device_printf((sc)->nfe_dev, __VA_ARGS__); \ 143} while (0) 144#else 145#define DPRINTF(sc, ...) 146#define DPRINTFN(sc, n, ...) 147#endif 148 149#define NFE_LOCK(_sc) mtx_lock(&(_sc)->nfe_mtx) 150#define NFE_UNLOCK(_sc) mtx_unlock(&(_sc)->nfe_mtx) 151#define NFE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->nfe_mtx, MA_OWNED) 152 153/* Tunables. */ 154static int msi_disable = 0; 155static int msix_disable = 0; 156static int jumbo_disable = 0; 157TUNABLE_INT("hw.nfe.msi_disable", &msi_disable); 158TUNABLE_INT("hw.nfe.msix_disable", &msix_disable); 159TUNABLE_INT("hw.nfe.jumbo_disable", &jumbo_disable); 160 161static device_method_t nfe_methods[] = { 162 /* Device interface */ 163 DEVMETHOD(device_probe, nfe_probe), 164 DEVMETHOD(device_attach, nfe_attach), 165 DEVMETHOD(device_detach, nfe_detach), 166 DEVMETHOD(device_suspend, nfe_suspend), 167 DEVMETHOD(device_resume, nfe_resume), 168 DEVMETHOD(device_shutdown, nfe_shutdown), 169 170 /* MII interface */ 171 DEVMETHOD(miibus_readreg, nfe_miibus_readreg), 172 DEVMETHOD(miibus_writereg, nfe_miibus_writereg), 173 DEVMETHOD(miibus_statchg, nfe_miibus_statchg), 174 175 DEVMETHOD_END 176}; 177 178static driver_t nfe_driver = { 179 "nfe", 180 nfe_methods, 181 sizeof(struct nfe_softc) 182}; 183 184static devclass_t nfe_devclass; 185 186DRIVER_MODULE(nfe, pci, nfe_driver, nfe_devclass, 0, 0); 187DRIVER_MODULE(miibus, nfe, miibus_driver, miibus_devclass, 0, 0); 188 189static struct nfe_type nfe_devs[] = { 190 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN, 191 "NVIDIA nForce MCP Networking Adapter"}, 192 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN, 193 "NVIDIA nForce2 MCP2 Networking Adapter"}, 194 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1, 195 "NVIDIA nForce2 400 MCP4 Networking Adapter"}, 196 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2, 197 "NVIDIA nForce2 400 MCP5 Networking Adapter"}, 198 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1, 199 "NVIDIA nForce3 MCP3 Networking Adapter"}, 200 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN, 201 "NVIDIA nForce3 250 MCP6 Networking Adapter"}, 202 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4, 203 "NVIDIA nForce3 MCP7 Networking Adapter"}, 204 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE4_LAN1, 205 "NVIDIA nForce4 CK804 MCP8 Networking Adapter"}, 206 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE4_LAN2, 207 "NVIDIA nForce4 CK804 MCP9 Networking Adapter"}, 208 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1, 209 "NVIDIA nForce MCP04 Networking Adapter"}, /* MCP10 */ 210 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2, 211 "NVIDIA nForce MCP04 Networking Adapter"}, /* MCP11 */ 212 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE430_LAN1, 213 "NVIDIA nForce 430 MCP12 Networking Adapter"}, 214 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE430_LAN2, 215 "NVIDIA nForce 430 MCP13 Networking Adapter"}, 216 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1, 217 "NVIDIA nForce MCP55 Networking Adapter"}, 218 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2, 219 "NVIDIA nForce MCP55 Networking Adapter"}, 220 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1, 221 "NVIDIA nForce MCP61 Networking Adapter"}, 222 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2, 223 "NVIDIA nForce MCP61 Networking Adapter"}, 224 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3, 225 "NVIDIA nForce MCP61 Networking Adapter"}, 226 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4, 227 "NVIDIA nForce MCP61 Networking Adapter"}, 228 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1, 229 "NVIDIA nForce MCP65 Networking Adapter"}, 230 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2, 231 "NVIDIA nForce MCP65 Networking Adapter"}, 232 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3, 233 "NVIDIA nForce MCP65 Networking Adapter"}, 234 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4, 235 "NVIDIA nForce MCP65 Networking Adapter"}, 236 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN1, 237 "NVIDIA nForce MCP67 Networking Adapter"}, 238 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN2, 239 "NVIDIA nForce MCP67 Networking Adapter"}, 240 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN3, 241 "NVIDIA nForce MCP67 Networking Adapter"}, 242 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN4, 243 "NVIDIA nForce MCP67 Networking Adapter"}, 244 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN1, 245 "NVIDIA nForce MCP73 Networking Adapter"}, 246 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN2, 247 "NVIDIA nForce MCP73 Networking Adapter"}, 248 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN3, 249 "NVIDIA nForce MCP73 Networking Adapter"}, 250 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN4, 251 "NVIDIA nForce MCP73 Networking Adapter"}, 252 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN1, 253 "NVIDIA nForce MCP77 Networking Adapter"}, 254 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN2, 255 "NVIDIA nForce MCP77 Networking Adapter"}, 256 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN3, 257 "NVIDIA nForce MCP77 Networking Adapter"}, 258 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN4, 259 "NVIDIA nForce MCP77 Networking Adapter"}, 260 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN1, 261 "NVIDIA nForce MCP79 Networking Adapter"}, 262 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN2, 263 "NVIDIA nForce MCP79 Networking Adapter"}, 264 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN3, 265 "NVIDIA nForce MCP79 Networking Adapter"}, 266 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN4, 267 "NVIDIA nForce MCP79 Networking Adapter"}, 268 {0, 0, NULL} 269}; 270 271 272/* Probe for supported hardware ID's */ 273static int 274nfe_probe(device_t dev) 275{ 276 struct nfe_type *t; 277 278 t = nfe_devs; 279 /* Check for matching PCI DEVICE ID's */ 280 while (t->name != NULL) { 281 if ((pci_get_vendor(dev) == t->vid_id) && 282 (pci_get_device(dev) == t->dev_id)) { 283 device_set_desc(dev, t->name); 284 return (BUS_PROBE_DEFAULT); 285 } 286 t++; 287 } 288 289 return (ENXIO); 290} 291 292static void 293nfe_alloc_msix(struct nfe_softc *sc, int count) 294{ 295 int rid; 296 297 rid = PCIR_BAR(2); 298 sc->nfe_msix_res = bus_alloc_resource_any(sc->nfe_dev, SYS_RES_MEMORY, 299 &rid, RF_ACTIVE); 300 if (sc->nfe_msix_res == NULL) { 301 device_printf(sc->nfe_dev, 302 "couldn't allocate MSIX table resource\n"); 303 return; 304 } 305 rid = PCIR_BAR(3); 306 sc->nfe_msix_pba_res = bus_alloc_resource_any(sc->nfe_dev, 307 SYS_RES_MEMORY, &rid, RF_ACTIVE); 308 if (sc->nfe_msix_pba_res == NULL) { 309 device_printf(sc->nfe_dev, 310 "couldn't allocate MSIX PBA resource\n"); 311 bus_release_resource(sc->nfe_dev, SYS_RES_MEMORY, PCIR_BAR(2), 312 sc->nfe_msix_res); 313 sc->nfe_msix_res = NULL; 314 return; 315 } 316 317 if (pci_alloc_msix(sc->nfe_dev, &count) == 0) { 318 if (count == NFE_MSI_MESSAGES) { 319 if (bootverbose) 320 device_printf(sc->nfe_dev, 321 "Using %d MSIX messages\n", count); 322 sc->nfe_msix = 1; 323 } else { 324 if (bootverbose) 325 device_printf(sc->nfe_dev, 326 "couldn't allocate MSIX\n"); 327 pci_release_msi(sc->nfe_dev); 328 bus_release_resource(sc->nfe_dev, SYS_RES_MEMORY, 329 PCIR_BAR(3), sc->nfe_msix_pba_res); 330 bus_release_resource(sc->nfe_dev, SYS_RES_MEMORY, 331 PCIR_BAR(2), sc->nfe_msix_res); 332 sc->nfe_msix_pba_res = NULL; 333 sc->nfe_msix_res = NULL; 334 } 335 } 336} 337 338 339static int 340nfe_detect_msik9(struct nfe_softc *sc) 341{ 342 static const char *maker = "MSI"; 343 static const char *product = "K9N6PGM2-V2 (MS-7309)"; 344 char *m, *p; 345 int found; 346 347 found = 0; 348 m = getenv("smbios.planar.maker"); 349 p = getenv("smbios.planar.product"); 350 if (m != NULL && p != NULL) { 351 if (strcmp(m, maker) == 0 && strcmp(p, product) == 0) 352 found = 1; 353 } 354 if (m != NULL) 355 freeenv(m); 356 if (p != NULL) 357 freeenv(p); 358 359 return (found); 360} 361 362 363static int 364nfe_attach(device_t dev) 365{ 366 struct nfe_softc *sc; 367 struct ifnet *ifp; 368 bus_addr_t dma_addr_max; 369 int error = 0, i, msic, phyloc, reg, rid; 370 371 sc = device_get_softc(dev); 372 sc->nfe_dev = dev; 373 374 mtx_init(&sc->nfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 375 MTX_DEF); 376 callout_init_mtx(&sc->nfe_stat_ch, &sc->nfe_mtx, 0); 377 378 pci_enable_busmaster(dev); 379 380 rid = PCIR_BAR(0); 381 sc->nfe_res[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 382 RF_ACTIVE); 383 if (sc->nfe_res[0] == NULL) { 384 device_printf(dev, "couldn't map memory resources\n"); 385 mtx_destroy(&sc->nfe_mtx); 386 return (ENXIO); 387 } 388 389 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 390 uint16_t v, width; 391 392 v = pci_read_config(dev, reg + 0x08, 2); 393 /* Change max. read request size to 4096. */ 394 v &= ~(7 << 12); 395 v |= (5 << 12); 396 pci_write_config(dev, reg + 0x08, v, 2); 397 398 v = pci_read_config(dev, reg + 0x0c, 2); 399 /* link capability */ 400 v = (v >> 4) & 0x0f; 401 width = pci_read_config(dev, reg + 0x12, 2); 402 /* negotiated link width */ 403 width = (width >> 4) & 0x3f; 404 if (v != width) 405 device_printf(sc->nfe_dev, 406 "warning, negotiated width of link(x%d) != " 407 "max. width of link(x%d)\n", width, v); 408 } 409 410 if (nfe_can_use_msix(sc) == 0) { 411 device_printf(sc->nfe_dev, 412 "MSI/MSI-X capability black-listed, will use INTx\n"); 413 msix_disable = 1; 414 msi_disable = 1; 415 } 416 417 /* Allocate interrupt */ 418 if (msix_disable == 0 || msi_disable == 0) { 419 if (msix_disable == 0 && 420 (msic = pci_msix_count(dev)) == NFE_MSI_MESSAGES) 421 nfe_alloc_msix(sc, msic); 422 if (msi_disable == 0 && sc->nfe_msix == 0 && 423 (msic = pci_msi_count(dev)) == NFE_MSI_MESSAGES && 424 pci_alloc_msi(dev, &msic) == 0) { 425 if (msic == NFE_MSI_MESSAGES) { 426 if (bootverbose) 427 device_printf(dev, 428 "Using %d MSI messages\n", msic); 429 sc->nfe_msi = 1; 430 } else 431 pci_release_msi(dev); 432 } 433 } 434 435 if (sc->nfe_msix == 0 && sc->nfe_msi == 0) { 436 rid = 0; 437 sc->nfe_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 438 RF_SHAREABLE | RF_ACTIVE); 439 if (sc->nfe_irq[0] == NULL) { 440 device_printf(dev, "couldn't allocate IRQ resources\n"); 441 error = ENXIO; 442 goto fail; 443 } 444 } else { 445 for (i = 0, rid = 1; i < NFE_MSI_MESSAGES; i++, rid++) { 446 sc->nfe_irq[i] = bus_alloc_resource_any(dev, 447 SYS_RES_IRQ, &rid, RF_ACTIVE); 448 if (sc->nfe_irq[i] == NULL) { 449 device_printf(dev, 450 "couldn't allocate IRQ resources for " 451 "message %d\n", rid); 452 error = ENXIO; 453 goto fail; 454 } 455 } 456 /* Map interrupts to vector 0. */ 457 if (sc->nfe_msix != 0) { 458 NFE_WRITE(sc, NFE_MSIX_MAP0, 0); 459 NFE_WRITE(sc, NFE_MSIX_MAP1, 0); 460 } else if (sc->nfe_msi != 0) { 461 NFE_WRITE(sc, NFE_MSI_MAP0, 0); 462 NFE_WRITE(sc, NFE_MSI_MAP1, 0); 463 } 464 } 465 466 /* Set IRQ status/mask register. */ 467 sc->nfe_irq_status = NFE_IRQ_STATUS; 468 sc->nfe_irq_mask = NFE_IRQ_MASK; 469 sc->nfe_intrs = NFE_IRQ_WANTED; 470 sc->nfe_nointrs = 0; 471 if (sc->nfe_msix != 0) { 472 sc->nfe_irq_status = NFE_MSIX_IRQ_STATUS; 473 sc->nfe_nointrs = NFE_IRQ_WANTED; 474 } else if (sc->nfe_msi != 0) { 475 sc->nfe_irq_mask = NFE_MSI_IRQ_MASK; 476 sc->nfe_intrs = NFE_MSI_VECTOR_0_ENABLED; 477 } 478 479 sc->nfe_devid = pci_get_device(dev); 480 sc->nfe_revid = pci_get_revid(dev); 481 sc->nfe_flags = 0; 482 483 switch (sc->nfe_devid) { 484 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2: 485 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3: 486 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4: 487 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5: 488 sc->nfe_flags |= NFE_JUMBO_SUP | NFE_HW_CSUM; 489 break; 490 case PCI_PRODUCT_NVIDIA_MCP51_LAN1: 491 case PCI_PRODUCT_NVIDIA_MCP51_LAN2: 492 sc->nfe_flags |= NFE_40BIT_ADDR | NFE_PWR_MGMT | NFE_MIB_V1; 493 break; 494 case PCI_PRODUCT_NVIDIA_CK804_LAN1: 495 case PCI_PRODUCT_NVIDIA_CK804_LAN2: 496 case PCI_PRODUCT_NVIDIA_MCP04_LAN1: 497 case PCI_PRODUCT_NVIDIA_MCP04_LAN2: 498 sc->nfe_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 499 NFE_MIB_V1; 500 break; 501 case PCI_PRODUCT_NVIDIA_MCP55_LAN1: 502 case PCI_PRODUCT_NVIDIA_MCP55_LAN2: 503 sc->nfe_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 504 NFE_HW_VLAN | NFE_PWR_MGMT | NFE_TX_FLOW_CTRL | NFE_MIB_V2; 505 break; 506 507 case PCI_PRODUCT_NVIDIA_MCP61_LAN1: 508 case PCI_PRODUCT_NVIDIA_MCP61_LAN2: 509 case PCI_PRODUCT_NVIDIA_MCP61_LAN3: 510 case PCI_PRODUCT_NVIDIA_MCP61_LAN4: 511 case PCI_PRODUCT_NVIDIA_MCP67_LAN1: 512 case PCI_PRODUCT_NVIDIA_MCP67_LAN2: 513 case PCI_PRODUCT_NVIDIA_MCP67_LAN3: 514 case PCI_PRODUCT_NVIDIA_MCP67_LAN4: 515 case PCI_PRODUCT_NVIDIA_MCP73_LAN1: 516 case PCI_PRODUCT_NVIDIA_MCP73_LAN2: 517 case PCI_PRODUCT_NVIDIA_MCP73_LAN3: 518 case PCI_PRODUCT_NVIDIA_MCP73_LAN4: 519 sc->nfe_flags |= NFE_40BIT_ADDR | NFE_PWR_MGMT | 520 NFE_CORRECT_MACADDR | NFE_TX_FLOW_CTRL | NFE_MIB_V2; 521 break; 522 case PCI_PRODUCT_NVIDIA_MCP77_LAN1: 523 case PCI_PRODUCT_NVIDIA_MCP77_LAN2: 524 case PCI_PRODUCT_NVIDIA_MCP77_LAN3: 525 case PCI_PRODUCT_NVIDIA_MCP77_LAN4: 526 /* XXX flow control */ 527 sc->nfe_flags |= NFE_40BIT_ADDR | NFE_HW_CSUM | NFE_PWR_MGMT | 528 NFE_CORRECT_MACADDR | NFE_MIB_V3; 529 break; 530 case PCI_PRODUCT_NVIDIA_MCP79_LAN1: 531 case PCI_PRODUCT_NVIDIA_MCP79_LAN2: 532 case PCI_PRODUCT_NVIDIA_MCP79_LAN3: 533 case PCI_PRODUCT_NVIDIA_MCP79_LAN4: 534 /* XXX flow control */ 535 sc->nfe_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 536 NFE_PWR_MGMT | NFE_CORRECT_MACADDR | NFE_MIB_V3; 537 break; 538 case PCI_PRODUCT_NVIDIA_MCP65_LAN1: 539 case PCI_PRODUCT_NVIDIA_MCP65_LAN2: 540 case PCI_PRODUCT_NVIDIA_MCP65_LAN3: 541 case PCI_PRODUCT_NVIDIA_MCP65_LAN4: 542 sc->nfe_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | 543 NFE_PWR_MGMT | NFE_CORRECT_MACADDR | NFE_TX_FLOW_CTRL | 544 NFE_MIB_V2; 545 break; 546 } 547 548 nfe_power(sc); 549 /* Check for reversed ethernet address */ 550 if ((NFE_READ(sc, NFE_TX_UNK) & NFE_MAC_ADDR_INORDER) != 0) 551 sc->nfe_flags |= NFE_CORRECT_MACADDR; 552 nfe_get_macaddr(sc, sc->eaddr); 553 /* 554 * Allocate the parent bus DMA tag appropriate for PCI. 555 */ 556 dma_addr_max = BUS_SPACE_MAXADDR_32BIT; 557 if ((sc->nfe_flags & NFE_40BIT_ADDR) != 0) 558 dma_addr_max = NFE_DMA_MAXADDR; 559 error = bus_dma_tag_create( 560 bus_get_dma_tag(sc->nfe_dev), /* parent */ 561 1, 0, /* alignment, boundary */ 562 dma_addr_max, /* lowaddr */ 563 BUS_SPACE_MAXADDR, /* highaddr */ 564 NULL, NULL, /* filter, filterarg */ 565 BUS_SPACE_MAXSIZE_32BIT, 0, /* maxsize, nsegments */ 566 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 567 0, /* flags */ 568 NULL, NULL, /* lockfunc, lockarg */ 569 &sc->nfe_parent_tag); 570 if (error) 571 goto fail; 572 573 ifp = sc->nfe_ifp = if_alloc(IFT_ETHER); 574 if (ifp == NULL) { 575 device_printf(dev, "can not if_alloc()\n"); 576 error = ENOSPC; 577 goto fail; 578 } 579 580 /* 581 * Allocate Tx and Rx rings. 582 */ 583 if ((error = nfe_alloc_tx_ring(sc, &sc->txq)) != 0) 584 goto fail; 585 586 if ((error = nfe_alloc_rx_ring(sc, &sc->rxq)) != 0) 587 goto fail; 588 589 nfe_alloc_jrx_ring(sc, &sc->jrxq); 590 /* Create sysctl node. */ 591 nfe_sysctl_node(sc); 592 593 ifp->if_softc = sc; 594 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 595 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 596 ifp->if_ioctl = nfe_ioctl; 597 ifp->if_start = nfe_start; 598 ifp->if_hwassist = 0; 599 ifp->if_capabilities = 0; 600 ifp->if_init = nfe_init; 601 IFQ_SET_MAXLEN(&ifp->if_snd, NFE_TX_RING_COUNT - 1); 602 ifp->if_snd.ifq_drv_maxlen = NFE_TX_RING_COUNT - 1; 603 IFQ_SET_READY(&ifp->if_snd); 604 605 if (sc->nfe_flags & NFE_HW_CSUM) { 606 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_TSO4; 607 ifp->if_hwassist |= NFE_CSUM_FEATURES | CSUM_TSO; 608 } 609 ifp->if_capenable = ifp->if_capabilities; 610 611 sc->nfe_framesize = ifp->if_mtu + NFE_RX_HEADERS; 612 /* VLAN capability setup. */ 613 ifp->if_capabilities |= IFCAP_VLAN_MTU; 614 if ((sc->nfe_flags & NFE_HW_VLAN) != 0) { 615 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 616 if ((ifp->if_capabilities & IFCAP_HWCSUM) != 0) 617 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | 618 IFCAP_VLAN_HWTSO; 619 } 620 621 if (pci_find_cap(dev, PCIY_PMG, ®) == 0) 622 ifp->if_capabilities |= IFCAP_WOL_MAGIC; 623 ifp->if_capenable = ifp->if_capabilities; 624 625 /* 626 * Tell the upper layer(s) we support long frames. 627 * Must appear after the call to ether_ifattach() because 628 * ether_ifattach() sets ifi_hdrlen to the default value. 629 */ 630 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 631 632#ifdef DEVICE_POLLING 633 ifp->if_capabilities |= IFCAP_POLLING; 634#endif 635 636 /* Do MII setup */ 637 phyloc = MII_PHY_ANY; 638 if (sc->nfe_devid == PCI_PRODUCT_NVIDIA_MCP61_LAN1 || 639 sc->nfe_devid == PCI_PRODUCT_NVIDIA_MCP61_LAN2 || 640 sc->nfe_devid == PCI_PRODUCT_NVIDIA_MCP61_LAN3 || 641 sc->nfe_devid == PCI_PRODUCT_NVIDIA_MCP61_LAN4) { 642 if (nfe_detect_msik9(sc) != 0) 643 phyloc = 0; 644 } 645 error = mii_attach(dev, &sc->nfe_miibus, ifp, nfe_ifmedia_upd, 646 nfe_ifmedia_sts, BMSR_DEFCAPMASK, phyloc, MII_OFFSET_ANY, 647 MIIF_DOPAUSE); 648 if (error != 0) { 649 device_printf(dev, "attaching PHYs failed\n"); 650 goto fail; 651 } 652 ether_ifattach(ifp, sc->eaddr); 653 654 TASK_INIT(&sc->nfe_int_task, 0, nfe_int_task, sc); 655 sc->nfe_tq = taskqueue_create_fast("nfe_taskq", M_WAITOK, 656 taskqueue_thread_enqueue, &sc->nfe_tq); 657 taskqueue_start_threads(&sc->nfe_tq, 1, PI_NET, "%s taskq", 658 device_get_nameunit(sc->nfe_dev)); 659 error = 0; 660 if (sc->nfe_msi == 0 && sc->nfe_msix == 0) { 661 error = bus_setup_intr(dev, sc->nfe_irq[0], 662 INTR_TYPE_NET | INTR_MPSAFE, nfe_intr, NULL, sc, 663 &sc->nfe_intrhand[0]); 664 } else { 665 for (i = 0; i < NFE_MSI_MESSAGES; i++) { 666 error = bus_setup_intr(dev, sc->nfe_irq[i], 667 INTR_TYPE_NET | INTR_MPSAFE, nfe_intr, NULL, sc, 668 &sc->nfe_intrhand[i]); 669 if (error != 0) 670 break; 671 } 672 } 673 if (error) { 674 device_printf(dev, "couldn't set up irq\n"); 675 taskqueue_free(sc->nfe_tq); 676 sc->nfe_tq = NULL; 677 ether_ifdetach(ifp); 678 goto fail; 679 } 680 681fail: 682 if (error) 683 nfe_detach(dev); 684 685 return (error); 686} 687 688 689static int 690nfe_detach(device_t dev) 691{ 692 struct nfe_softc *sc; 693 struct ifnet *ifp; 694 uint8_t eaddr[ETHER_ADDR_LEN]; 695 int i, rid; 696 697 sc = device_get_softc(dev); 698 KASSERT(mtx_initialized(&sc->nfe_mtx), ("nfe mutex not initialized")); 699 ifp = sc->nfe_ifp; 700 701#ifdef DEVICE_POLLING 702 if (ifp != NULL && ifp->if_capenable & IFCAP_POLLING) 703 ether_poll_deregister(ifp); 704#endif 705 if (device_is_attached(dev)) { 706 NFE_LOCK(sc); 707 nfe_stop(ifp); 708 ifp->if_flags &= ~IFF_UP; 709 NFE_UNLOCK(sc); 710 callout_drain(&sc->nfe_stat_ch); 711 ether_ifdetach(ifp); 712 } 713 714 if (ifp) { 715 /* restore ethernet address */ 716 if ((sc->nfe_flags & NFE_CORRECT_MACADDR) == 0) { 717 for (i = 0; i < ETHER_ADDR_LEN; i++) { 718 eaddr[i] = sc->eaddr[5 - i]; 719 } 720 } else 721 bcopy(sc->eaddr, eaddr, ETHER_ADDR_LEN); 722 nfe_set_macaddr(sc, eaddr); 723 if_free(ifp); 724 } 725 if (sc->nfe_miibus) 726 device_delete_child(dev, sc->nfe_miibus); 727 bus_generic_detach(dev); 728 if (sc->nfe_tq != NULL) { 729 taskqueue_drain(sc->nfe_tq, &sc->nfe_int_task); 730 taskqueue_free(sc->nfe_tq); 731 sc->nfe_tq = NULL; 732 } 733 734 for (i = 0; i < NFE_MSI_MESSAGES; i++) { 735 if (sc->nfe_intrhand[i] != NULL) { 736 bus_teardown_intr(dev, sc->nfe_irq[i], 737 sc->nfe_intrhand[i]); 738 sc->nfe_intrhand[i] = NULL; 739 } 740 } 741 742 if (sc->nfe_msi == 0 && sc->nfe_msix == 0) { 743 if (sc->nfe_irq[0] != NULL) 744 bus_release_resource(dev, SYS_RES_IRQ, 0, 745 sc->nfe_irq[0]); 746 } else { 747 for (i = 0, rid = 1; i < NFE_MSI_MESSAGES; i++, rid++) { 748 if (sc->nfe_irq[i] != NULL) { 749 bus_release_resource(dev, SYS_RES_IRQ, rid, 750 sc->nfe_irq[i]); 751 sc->nfe_irq[i] = NULL; 752 } 753 } 754 pci_release_msi(dev); 755 } 756 if (sc->nfe_msix_pba_res != NULL) { 757 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(3), 758 sc->nfe_msix_pba_res); 759 sc->nfe_msix_pba_res = NULL; 760 } 761 if (sc->nfe_msix_res != NULL) { 762 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(2), 763 sc->nfe_msix_res); 764 sc->nfe_msix_res = NULL; 765 } 766 if (sc->nfe_res[0] != NULL) { 767 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), 768 sc->nfe_res[0]); 769 sc->nfe_res[0] = NULL; 770 } 771 772 nfe_free_tx_ring(sc, &sc->txq); 773 nfe_free_rx_ring(sc, &sc->rxq); 774 nfe_free_jrx_ring(sc, &sc->jrxq); 775 776 if (sc->nfe_parent_tag) { 777 bus_dma_tag_destroy(sc->nfe_parent_tag); 778 sc->nfe_parent_tag = NULL; 779 } 780 781 mtx_destroy(&sc->nfe_mtx); 782 783 return (0); 784} 785 786 787static int 788nfe_suspend(device_t dev) 789{ 790 struct nfe_softc *sc; 791 792 sc = device_get_softc(dev); 793 794 NFE_LOCK(sc); 795 nfe_stop(sc->nfe_ifp); 796 nfe_set_wol(sc); 797 sc->nfe_suspended = 1; 798 NFE_UNLOCK(sc); 799 800 return (0); 801} 802 803 804static int 805nfe_resume(device_t dev) 806{ 807 struct nfe_softc *sc; 808 struct ifnet *ifp; 809 810 sc = device_get_softc(dev); 811 812 NFE_LOCK(sc); 813 nfe_power(sc); 814 ifp = sc->nfe_ifp; 815 if (ifp->if_flags & IFF_UP) 816 nfe_init_locked(sc); 817 sc->nfe_suspended = 0; 818 NFE_UNLOCK(sc); 819 820 return (0); 821} 822 823 824static int 825nfe_can_use_msix(struct nfe_softc *sc) 826{ 827 static struct msix_blacklist { 828 char *maker; 829 char *product; 830 } msix_blacklists[] = { 831 { "ASUSTeK Computer INC.", "P5N32-SLI PREMIUM" } 832 }; 833 834 struct msix_blacklist *mblp; 835 char *maker, *product; 836 int count, n, use_msix; 837 838 /* 839 * Search base board manufacturer and product name table 840 * to see this system has a known MSI/MSI-X issue. 841 */ 842 maker = getenv("smbios.planar.maker"); 843 product = getenv("smbios.planar.product"); 844 use_msix = 1; 845 if (maker != NULL && product != NULL) { 846 count = sizeof(msix_blacklists) / sizeof(msix_blacklists[0]); 847 mblp = msix_blacklists; 848 for (n = 0; n < count; n++) { 849 if (strcmp(maker, mblp->maker) == 0 && 850 strcmp(product, mblp->product) == 0) { 851 use_msix = 0; 852 break; 853 } 854 mblp++; 855 } 856 } 857 if (maker != NULL) 858 freeenv(maker); 859 if (product != NULL) 860 freeenv(product); 861 862 return (use_msix); 863} 864 865 866/* Take PHY/NIC out of powerdown, from Linux */ 867static void 868nfe_power(struct nfe_softc *sc) 869{ 870 uint32_t pwr; 871 872 if ((sc->nfe_flags & NFE_PWR_MGMT) == 0) 873 return; 874 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | NFE_RXTX_BIT2); 875 NFE_WRITE(sc, NFE_MAC_RESET, NFE_MAC_RESET_MAGIC); 876 DELAY(100); 877 NFE_WRITE(sc, NFE_MAC_RESET, 0); 878 DELAY(100); 879 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT2); 880 pwr = NFE_READ(sc, NFE_PWR2_CTL); 881 pwr &= ~NFE_PWR2_WAKEUP_MASK; 882 if (sc->nfe_revid >= 0xa3 && 883 (sc->nfe_devid == PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 || 884 sc->nfe_devid == PCI_PRODUCT_NVIDIA_NFORCE430_LAN2)) 885 pwr |= NFE_PWR2_REVA3; 886 NFE_WRITE(sc, NFE_PWR2_CTL, pwr); 887} 888 889 890static void 891nfe_miibus_statchg(device_t dev) 892{ 893 struct nfe_softc *sc; 894 struct mii_data *mii; 895 struct ifnet *ifp; 896 uint32_t rxctl, txctl; 897 898 sc = device_get_softc(dev); 899 900 mii = device_get_softc(sc->nfe_miibus); 901 ifp = sc->nfe_ifp; 902 903 sc->nfe_link = 0; 904 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 905 (IFM_ACTIVE | IFM_AVALID)) { 906 switch (IFM_SUBTYPE(mii->mii_media_active)) { 907 case IFM_10_T: 908 case IFM_100_TX: 909 case IFM_1000_T: 910 sc->nfe_link = 1; 911 break; 912 default: 913 break; 914 } 915 } 916 917 nfe_mac_config(sc, mii); 918 txctl = NFE_READ(sc, NFE_TX_CTL); 919 rxctl = NFE_READ(sc, NFE_RX_CTL); 920 if (sc->nfe_link != 0 && (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 921 txctl |= NFE_TX_START; 922 rxctl |= NFE_RX_START; 923 } else { 924 txctl &= ~NFE_TX_START; 925 rxctl &= ~NFE_RX_START; 926 } 927 NFE_WRITE(sc, NFE_TX_CTL, txctl); 928 NFE_WRITE(sc, NFE_RX_CTL, rxctl); 929} 930 931 932static void 933nfe_mac_config(struct nfe_softc *sc, struct mii_data *mii) 934{ 935 uint32_t link, misc, phy, seed; 936 uint32_t val; 937 938 NFE_LOCK_ASSERT(sc); 939 940 phy = NFE_READ(sc, NFE_PHY_IFACE); 941 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T); 942 943 seed = NFE_READ(sc, NFE_RNDSEED); 944 seed &= ~NFE_SEED_MASK; 945 946 misc = NFE_MISC1_MAGIC; 947 link = NFE_MEDIA_SET; 948 949 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0) { 950 phy |= NFE_PHY_HDX; /* half-duplex */ 951 misc |= NFE_MISC1_HDX; 952 } 953 954 switch (IFM_SUBTYPE(mii->mii_media_active)) { 955 case IFM_1000_T: /* full-duplex only */ 956 link |= NFE_MEDIA_1000T; 957 seed |= NFE_SEED_1000T; 958 phy |= NFE_PHY_1000T; 959 break; 960 case IFM_100_TX: 961 link |= NFE_MEDIA_100TX; 962 seed |= NFE_SEED_100TX; 963 phy |= NFE_PHY_100TX; 964 break; 965 case IFM_10_T: 966 link |= NFE_MEDIA_10T; 967 seed |= NFE_SEED_10T; 968 break; 969 } 970 971 if ((phy & 0x10000000) != 0) { 972 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) 973 val = NFE_R1_MAGIC_1000; 974 else 975 val = NFE_R1_MAGIC_10_100; 976 } else 977 val = NFE_R1_MAGIC_DEFAULT; 978 NFE_WRITE(sc, NFE_SETUP_R1, val); 979 980 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */ 981 982 NFE_WRITE(sc, NFE_PHY_IFACE, phy); 983 NFE_WRITE(sc, NFE_MISC1, misc); 984 NFE_WRITE(sc, NFE_LINKSPEED, link); 985 986 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 987 /* It seems all hardwares supports Rx pause frames. */ 988 val = NFE_READ(sc, NFE_RXFILTER); 989 if ((IFM_OPTIONS(mii->mii_media_active) & 990 IFM_ETH_RXPAUSE) != 0) 991 val |= NFE_PFF_RX_PAUSE; 992 else 993 val &= ~NFE_PFF_RX_PAUSE; 994 NFE_WRITE(sc, NFE_RXFILTER, val); 995 if ((sc->nfe_flags & NFE_TX_FLOW_CTRL) != 0) { 996 val = NFE_READ(sc, NFE_MISC1); 997 if ((IFM_OPTIONS(mii->mii_media_active) & 998 IFM_ETH_TXPAUSE) != 0) { 999 NFE_WRITE(sc, NFE_TX_PAUSE_FRAME, 1000 NFE_TX_PAUSE_FRAME_ENABLE); 1001 val |= NFE_MISC1_TX_PAUSE; 1002 } else { 1003 val &= ~NFE_MISC1_TX_PAUSE; 1004 NFE_WRITE(sc, NFE_TX_PAUSE_FRAME, 1005 NFE_TX_PAUSE_FRAME_DISABLE); 1006 } 1007 NFE_WRITE(sc, NFE_MISC1, val); 1008 } 1009 } else { 1010 /* disable rx/tx pause frames */ 1011 val = NFE_READ(sc, NFE_RXFILTER); 1012 val &= ~NFE_PFF_RX_PAUSE; 1013 NFE_WRITE(sc, NFE_RXFILTER, val); 1014 if ((sc->nfe_flags & NFE_TX_FLOW_CTRL) != 0) { 1015 NFE_WRITE(sc, NFE_TX_PAUSE_FRAME, 1016 NFE_TX_PAUSE_FRAME_DISABLE); 1017 val = NFE_READ(sc, NFE_MISC1); 1018 val &= ~NFE_MISC1_TX_PAUSE; 1019 NFE_WRITE(sc, NFE_MISC1, val); 1020 } 1021 } 1022} 1023 1024 1025static int 1026nfe_miibus_readreg(device_t dev, int phy, int reg) 1027{ 1028 struct nfe_softc *sc = device_get_softc(dev); 1029 uint32_t val; 1030 int ntries; 1031 1032 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1033 1034 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 1035 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 1036 DELAY(100); 1037 } 1038 1039 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg); 1040 1041 for (ntries = 0; ntries < NFE_TIMEOUT; ntries++) { 1042 DELAY(100); 1043 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 1044 break; 1045 } 1046 if (ntries == NFE_TIMEOUT) { 1047 DPRINTFN(sc, 2, "timeout waiting for PHY\n"); 1048 return 0; 1049 } 1050 1051 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) { 1052 DPRINTFN(sc, 2, "could not read PHY\n"); 1053 return 0; 1054 } 1055 1056 val = NFE_READ(sc, NFE_PHY_DATA); 1057 if (val != 0xffffffff && val != 0) 1058 sc->mii_phyaddr = phy; 1059 1060 DPRINTFN(sc, 2, "mii read phy %d reg 0x%x ret 0x%x\n", phy, reg, val); 1061 1062 return (val); 1063} 1064 1065 1066static int 1067nfe_miibus_writereg(device_t dev, int phy, int reg, int val) 1068{ 1069 struct nfe_softc *sc = device_get_softc(dev); 1070 uint32_t ctl; 1071 int ntries; 1072 1073 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1074 1075 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 1076 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 1077 DELAY(100); 1078 } 1079 1080 NFE_WRITE(sc, NFE_PHY_DATA, val); 1081 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg; 1082 NFE_WRITE(sc, NFE_PHY_CTL, ctl); 1083 1084 for (ntries = 0; ntries < NFE_TIMEOUT; ntries++) { 1085 DELAY(100); 1086 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 1087 break; 1088 } 1089#ifdef NFE_DEBUG 1090 if (nfedebug >= 2 && ntries == NFE_TIMEOUT) 1091 device_printf(sc->nfe_dev, "could not write to PHY\n"); 1092#endif 1093 return (0); 1094} 1095 1096struct nfe_dmamap_arg { 1097 bus_addr_t nfe_busaddr; 1098}; 1099 1100static int 1101nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1102{ 1103 struct nfe_dmamap_arg ctx; 1104 struct nfe_rx_data *data; 1105 void *desc; 1106 int i, error, descsize; 1107 1108 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1109 desc = ring->desc64; 1110 descsize = sizeof (struct nfe_desc64); 1111 } else { 1112 desc = ring->desc32; 1113 descsize = sizeof (struct nfe_desc32); 1114 } 1115 1116 ring->cur = ring->next = 0; 1117 1118 error = bus_dma_tag_create(sc->nfe_parent_tag, 1119 NFE_RING_ALIGN, 0, /* alignment, boundary */ 1120 BUS_SPACE_MAXADDR, /* lowaddr */ 1121 BUS_SPACE_MAXADDR, /* highaddr */ 1122 NULL, NULL, /* filter, filterarg */ 1123 NFE_RX_RING_COUNT * descsize, 1, /* maxsize, nsegments */ 1124 NFE_RX_RING_COUNT * descsize, /* maxsegsize */ 1125 0, /* flags */ 1126 NULL, NULL, /* lockfunc, lockarg */ 1127 &ring->rx_desc_tag); 1128 if (error != 0) { 1129 device_printf(sc->nfe_dev, "could not create desc DMA tag\n"); 1130 goto fail; 1131 } 1132 1133 /* allocate memory to desc */ 1134 error = bus_dmamem_alloc(ring->rx_desc_tag, &desc, BUS_DMA_WAITOK | 1135 BUS_DMA_COHERENT | BUS_DMA_ZERO, &ring->rx_desc_map); 1136 if (error != 0) { 1137 device_printf(sc->nfe_dev, "could not create desc DMA map\n"); 1138 goto fail; 1139 } 1140 if (sc->nfe_flags & NFE_40BIT_ADDR) 1141 ring->desc64 = desc; 1142 else 1143 ring->desc32 = desc; 1144 1145 /* map desc to device visible address space */ 1146 ctx.nfe_busaddr = 0; 1147 error = bus_dmamap_load(ring->rx_desc_tag, ring->rx_desc_map, desc, 1148 NFE_RX_RING_COUNT * descsize, nfe_dma_map_segs, &ctx, 0); 1149 if (error != 0) { 1150 device_printf(sc->nfe_dev, "could not load desc DMA map\n"); 1151 goto fail; 1152 } 1153 ring->physaddr = ctx.nfe_busaddr; 1154 1155 error = bus_dma_tag_create(sc->nfe_parent_tag, 1156 1, 0, /* alignment, boundary */ 1157 BUS_SPACE_MAXADDR, /* lowaddr */ 1158 BUS_SPACE_MAXADDR, /* highaddr */ 1159 NULL, NULL, /* filter, filterarg */ 1160 MCLBYTES, 1, /* maxsize, nsegments */ 1161 MCLBYTES, /* maxsegsize */ 1162 0, /* flags */ 1163 NULL, NULL, /* lockfunc, lockarg */ 1164 &ring->rx_data_tag); 1165 if (error != 0) { 1166 device_printf(sc->nfe_dev, "could not create Rx DMA tag\n"); 1167 goto fail; 1168 } 1169 1170 error = bus_dmamap_create(ring->rx_data_tag, 0, &ring->rx_spare_map); 1171 if (error != 0) { 1172 device_printf(sc->nfe_dev, 1173 "could not create Rx DMA spare map\n"); 1174 goto fail; 1175 } 1176 1177 /* 1178 * Pre-allocate Rx buffers and populate Rx ring. 1179 */ 1180 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1181 data = &sc->rxq.data[i]; 1182 data->rx_data_map = NULL; 1183 data->m = NULL; 1184 error = bus_dmamap_create(ring->rx_data_tag, 0, 1185 &data->rx_data_map); 1186 if (error != 0) { 1187 device_printf(sc->nfe_dev, 1188 "could not create Rx DMA map\n"); 1189 goto fail; 1190 } 1191 } 1192 1193fail: 1194 return (error); 1195} 1196 1197 1198static void 1199nfe_alloc_jrx_ring(struct nfe_softc *sc, struct nfe_jrx_ring *ring) 1200{ 1201 struct nfe_dmamap_arg ctx; 1202 struct nfe_rx_data *data; 1203 void *desc; 1204 int i, error, descsize; 1205 1206 if ((sc->nfe_flags & NFE_JUMBO_SUP) == 0) 1207 return; 1208 if (jumbo_disable != 0) { 1209 device_printf(sc->nfe_dev, "disabling jumbo frame support\n"); 1210 sc->nfe_jumbo_disable = 1; 1211 return; 1212 } 1213 1214 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1215 desc = ring->jdesc64; 1216 descsize = sizeof (struct nfe_desc64); 1217 } else { 1218 desc = ring->jdesc32; 1219 descsize = sizeof (struct nfe_desc32); 1220 } 1221 1222 ring->jcur = ring->jnext = 0; 1223 1224 /* Create DMA tag for jumbo Rx ring. */ 1225 error = bus_dma_tag_create(sc->nfe_parent_tag, 1226 NFE_RING_ALIGN, 0, /* alignment, boundary */ 1227 BUS_SPACE_MAXADDR, /* lowaddr */ 1228 BUS_SPACE_MAXADDR, /* highaddr */ 1229 NULL, NULL, /* filter, filterarg */ 1230 NFE_JUMBO_RX_RING_COUNT * descsize, /* maxsize */ 1231 1, /* nsegments */ 1232 NFE_JUMBO_RX_RING_COUNT * descsize, /* maxsegsize */ 1233 0, /* flags */ 1234 NULL, NULL, /* lockfunc, lockarg */ 1235 &ring->jrx_desc_tag); 1236 if (error != 0) { 1237 device_printf(sc->nfe_dev, 1238 "could not create jumbo ring DMA tag\n"); 1239 goto fail; 1240 } 1241 1242 /* Create DMA tag for jumbo Rx buffers. */ 1243 error = bus_dma_tag_create(sc->nfe_parent_tag, 1244 1, 0, /* alignment, boundary */ 1245 BUS_SPACE_MAXADDR, /* lowaddr */ 1246 BUS_SPACE_MAXADDR, /* highaddr */ 1247 NULL, NULL, /* filter, filterarg */ 1248 MJUM9BYTES, /* maxsize */ 1249 1, /* nsegments */ 1250 MJUM9BYTES, /* maxsegsize */ 1251 0, /* flags */ 1252 NULL, NULL, /* lockfunc, lockarg */ 1253 &ring->jrx_data_tag); 1254 if (error != 0) { 1255 device_printf(sc->nfe_dev, 1256 "could not create jumbo Rx buffer DMA tag\n"); 1257 goto fail; 1258 } 1259 1260 /* Allocate DMA'able memory and load the DMA map for jumbo Rx ring. */ 1261 error = bus_dmamem_alloc(ring->jrx_desc_tag, &desc, BUS_DMA_WAITOK | 1262 BUS_DMA_COHERENT | BUS_DMA_ZERO, &ring->jrx_desc_map); 1263 if (error != 0) { 1264 device_printf(sc->nfe_dev, 1265 "could not allocate DMA'able memory for jumbo Rx ring\n"); 1266 goto fail; 1267 } 1268 if (sc->nfe_flags & NFE_40BIT_ADDR) 1269 ring->jdesc64 = desc; 1270 else 1271 ring->jdesc32 = desc; 1272 1273 ctx.nfe_busaddr = 0; 1274 error = bus_dmamap_load(ring->jrx_desc_tag, ring->jrx_desc_map, desc, 1275 NFE_JUMBO_RX_RING_COUNT * descsize, nfe_dma_map_segs, &ctx, 0); 1276 if (error != 0) { 1277 device_printf(sc->nfe_dev, 1278 "could not load DMA'able memory for jumbo Rx ring\n"); 1279 goto fail; 1280 } 1281 ring->jphysaddr = ctx.nfe_busaddr; 1282 1283 /* Create DMA maps for jumbo Rx buffers. */ 1284 error = bus_dmamap_create(ring->jrx_data_tag, 0, &ring->jrx_spare_map); 1285 if (error != 0) { 1286 device_printf(sc->nfe_dev, 1287 "could not create jumbo Rx DMA spare map\n"); 1288 goto fail; 1289 } 1290 1291 for (i = 0; i < NFE_JUMBO_RX_RING_COUNT; i++) { 1292 data = &sc->jrxq.jdata[i]; 1293 data->rx_data_map = NULL; 1294 data->m = NULL; 1295 error = bus_dmamap_create(ring->jrx_data_tag, 0, 1296 &data->rx_data_map); 1297 if (error != 0) { 1298 device_printf(sc->nfe_dev, 1299 "could not create jumbo Rx DMA map\n"); 1300 goto fail; 1301 } 1302 } 1303 1304 return; 1305 1306fail: 1307 /* 1308 * Running without jumbo frame support is ok for most cases 1309 * so don't fail on creating dma tag/map for jumbo frame. 1310 */ 1311 nfe_free_jrx_ring(sc, ring); 1312 device_printf(sc->nfe_dev, "disabling jumbo frame support due to " 1313 "resource shortage\n"); 1314 sc->nfe_jumbo_disable = 1; 1315} 1316 1317 1318static int 1319nfe_init_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1320{ 1321 void *desc; 1322 size_t descsize; 1323 int i; 1324 1325 ring->cur = ring->next = 0; 1326 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1327 desc = ring->desc64; 1328 descsize = sizeof (struct nfe_desc64); 1329 } else { 1330 desc = ring->desc32; 1331 descsize = sizeof (struct nfe_desc32); 1332 } 1333 bzero(desc, descsize * NFE_RX_RING_COUNT); 1334 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1335 if (nfe_newbuf(sc, i) != 0) 1336 return (ENOBUFS); 1337 } 1338 1339 bus_dmamap_sync(ring->rx_desc_tag, ring->rx_desc_map, 1340 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1341 1342 return (0); 1343} 1344 1345 1346static int 1347nfe_init_jrx_ring(struct nfe_softc *sc, struct nfe_jrx_ring *ring) 1348{ 1349 void *desc; 1350 size_t descsize; 1351 int i; 1352 1353 ring->jcur = ring->jnext = 0; 1354 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1355 desc = ring->jdesc64; 1356 descsize = sizeof (struct nfe_desc64); 1357 } else { 1358 desc = ring->jdesc32; 1359 descsize = sizeof (struct nfe_desc32); 1360 } 1361 bzero(desc, descsize * NFE_JUMBO_RX_RING_COUNT); 1362 for (i = 0; i < NFE_JUMBO_RX_RING_COUNT; i++) { 1363 if (nfe_jnewbuf(sc, i) != 0) 1364 return (ENOBUFS); 1365 } 1366 1367 bus_dmamap_sync(ring->jrx_desc_tag, ring->jrx_desc_map, 1368 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1369 1370 return (0); 1371} 1372 1373 1374static void 1375nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1376{ 1377 struct nfe_rx_data *data; 1378 void *desc; 1379 int i, descsize; 1380 1381 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1382 desc = ring->desc64; 1383 descsize = sizeof (struct nfe_desc64); 1384 } else { 1385 desc = ring->desc32; 1386 descsize = sizeof (struct nfe_desc32); 1387 } 1388 1389 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1390 data = &ring->data[i]; 1391 if (data->rx_data_map != NULL) { 1392 bus_dmamap_destroy(ring->rx_data_tag, 1393 data->rx_data_map); 1394 data->rx_data_map = NULL; 1395 } 1396 if (data->m != NULL) { 1397 m_freem(data->m); 1398 data->m = NULL; 1399 } 1400 } 1401 if (ring->rx_data_tag != NULL) { 1402 if (ring->rx_spare_map != NULL) { 1403 bus_dmamap_destroy(ring->rx_data_tag, 1404 ring->rx_spare_map); 1405 ring->rx_spare_map = NULL; 1406 } 1407 bus_dma_tag_destroy(ring->rx_data_tag); 1408 ring->rx_data_tag = NULL; 1409 } 1410 1411 if (desc != NULL) { 1412 bus_dmamap_unload(ring->rx_desc_tag, ring->rx_desc_map); 1413 bus_dmamem_free(ring->rx_desc_tag, desc, ring->rx_desc_map); 1414 ring->desc64 = NULL; 1415 ring->desc32 = NULL; 1416 ring->rx_desc_map = NULL; 1417 } 1418 if (ring->rx_desc_tag != NULL) { 1419 bus_dma_tag_destroy(ring->rx_desc_tag); 1420 ring->rx_desc_tag = NULL; 1421 } 1422} 1423 1424 1425static void 1426nfe_free_jrx_ring(struct nfe_softc *sc, struct nfe_jrx_ring *ring) 1427{ 1428 struct nfe_rx_data *data; 1429 void *desc; 1430 int i, descsize; 1431 1432 if ((sc->nfe_flags & NFE_JUMBO_SUP) == 0) 1433 return; 1434 1435 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1436 desc = ring->jdesc64; 1437 descsize = sizeof (struct nfe_desc64); 1438 } else { 1439 desc = ring->jdesc32; 1440 descsize = sizeof (struct nfe_desc32); 1441 } 1442 1443 for (i = 0; i < NFE_JUMBO_RX_RING_COUNT; i++) { 1444 data = &ring->jdata[i]; 1445 if (data->rx_data_map != NULL) { 1446 bus_dmamap_destroy(ring->jrx_data_tag, 1447 data->rx_data_map); 1448 data->rx_data_map = NULL; 1449 } 1450 if (data->m != NULL) { 1451 m_freem(data->m); 1452 data->m = NULL; 1453 } 1454 } 1455 if (ring->jrx_data_tag != NULL) { 1456 if (ring->jrx_spare_map != NULL) { 1457 bus_dmamap_destroy(ring->jrx_data_tag, 1458 ring->jrx_spare_map); 1459 ring->jrx_spare_map = NULL; 1460 } 1461 bus_dma_tag_destroy(ring->jrx_data_tag); 1462 ring->jrx_data_tag = NULL; 1463 } 1464 1465 if (desc != NULL) { 1466 bus_dmamap_unload(ring->jrx_desc_tag, ring->jrx_desc_map); 1467 bus_dmamem_free(ring->jrx_desc_tag, desc, ring->jrx_desc_map); 1468 ring->jdesc64 = NULL; 1469 ring->jdesc32 = NULL; 1470 ring->jrx_desc_map = NULL; 1471 } 1472 1473 if (ring->jrx_desc_tag != NULL) { 1474 bus_dma_tag_destroy(ring->jrx_desc_tag); 1475 ring->jrx_desc_tag = NULL; 1476 } 1477} 1478 1479 1480static int 1481nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1482{ 1483 struct nfe_dmamap_arg ctx; 1484 int i, error; 1485 void *desc; 1486 int descsize; 1487 1488 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1489 desc = ring->desc64; 1490 descsize = sizeof (struct nfe_desc64); 1491 } else { 1492 desc = ring->desc32; 1493 descsize = sizeof (struct nfe_desc32); 1494 } 1495 1496 ring->queued = 0; 1497 ring->cur = ring->next = 0; 1498 1499 error = bus_dma_tag_create(sc->nfe_parent_tag, 1500 NFE_RING_ALIGN, 0, /* alignment, boundary */ 1501 BUS_SPACE_MAXADDR, /* lowaddr */ 1502 BUS_SPACE_MAXADDR, /* highaddr */ 1503 NULL, NULL, /* filter, filterarg */ 1504 NFE_TX_RING_COUNT * descsize, 1, /* maxsize, nsegments */ 1505 NFE_TX_RING_COUNT * descsize, /* maxsegsize */ 1506 0, /* flags */ 1507 NULL, NULL, /* lockfunc, lockarg */ 1508 &ring->tx_desc_tag); 1509 if (error != 0) { 1510 device_printf(sc->nfe_dev, "could not create desc DMA tag\n"); 1511 goto fail; 1512 } 1513 1514 error = bus_dmamem_alloc(ring->tx_desc_tag, &desc, BUS_DMA_WAITOK | 1515 BUS_DMA_COHERENT | BUS_DMA_ZERO, &ring->tx_desc_map); 1516 if (error != 0) { 1517 device_printf(sc->nfe_dev, "could not create desc DMA map\n"); 1518 goto fail; 1519 } 1520 if (sc->nfe_flags & NFE_40BIT_ADDR) 1521 ring->desc64 = desc; 1522 else 1523 ring->desc32 = desc; 1524 1525 ctx.nfe_busaddr = 0; 1526 error = bus_dmamap_load(ring->tx_desc_tag, ring->tx_desc_map, desc, 1527 NFE_TX_RING_COUNT * descsize, nfe_dma_map_segs, &ctx, 0); 1528 if (error != 0) { 1529 device_printf(sc->nfe_dev, "could not load desc DMA map\n"); 1530 goto fail; 1531 } 1532 ring->physaddr = ctx.nfe_busaddr; 1533 1534 error = bus_dma_tag_create(sc->nfe_parent_tag, 1535 1, 0, 1536 BUS_SPACE_MAXADDR, 1537 BUS_SPACE_MAXADDR, 1538 NULL, NULL, 1539 NFE_TSO_MAXSIZE, 1540 NFE_MAX_SCATTER, 1541 NFE_TSO_MAXSGSIZE, 1542 0, 1543 NULL, NULL, 1544 &ring->tx_data_tag); 1545 if (error != 0) { 1546 device_printf(sc->nfe_dev, "could not create Tx DMA tag\n"); 1547 goto fail; 1548 } 1549 1550 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1551 error = bus_dmamap_create(ring->tx_data_tag, 0, 1552 &ring->data[i].tx_data_map); 1553 if (error != 0) { 1554 device_printf(sc->nfe_dev, 1555 "could not create Tx DMA map\n"); 1556 goto fail; 1557 } 1558 } 1559 1560fail: 1561 return (error); 1562} 1563 1564 1565static void 1566nfe_init_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1567{ 1568 void *desc; 1569 size_t descsize; 1570 1571 sc->nfe_force_tx = 0; 1572 ring->queued = 0; 1573 ring->cur = ring->next = 0; 1574 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1575 desc = ring->desc64; 1576 descsize = sizeof (struct nfe_desc64); 1577 } else { 1578 desc = ring->desc32; 1579 descsize = sizeof (struct nfe_desc32); 1580 } 1581 bzero(desc, descsize * NFE_TX_RING_COUNT); 1582 1583 bus_dmamap_sync(ring->tx_desc_tag, ring->tx_desc_map, 1584 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1585} 1586 1587 1588static void 1589nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1590{ 1591 struct nfe_tx_data *data; 1592 void *desc; 1593 int i, descsize; 1594 1595 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1596 desc = ring->desc64; 1597 descsize = sizeof (struct nfe_desc64); 1598 } else { 1599 desc = ring->desc32; 1600 descsize = sizeof (struct nfe_desc32); 1601 } 1602 1603 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1604 data = &ring->data[i]; 1605 1606 if (data->m != NULL) { 1607 bus_dmamap_sync(ring->tx_data_tag, data->tx_data_map, 1608 BUS_DMASYNC_POSTWRITE); 1609 bus_dmamap_unload(ring->tx_data_tag, data->tx_data_map); 1610 m_freem(data->m); 1611 data->m = NULL; 1612 } 1613 if (data->tx_data_map != NULL) { 1614 bus_dmamap_destroy(ring->tx_data_tag, 1615 data->tx_data_map); 1616 data->tx_data_map = NULL; 1617 } 1618 } 1619 1620 if (ring->tx_data_tag != NULL) { 1621 bus_dma_tag_destroy(ring->tx_data_tag); 1622 ring->tx_data_tag = NULL; 1623 } 1624 1625 if (desc != NULL) { 1626 bus_dmamap_sync(ring->tx_desc_tag, ring->tx_desc_map, 1627 BUS_DMASYNC_POSTWRITE); 1628 bus_dmamap_unload(ring->tx_desc_tag, ring->tx_desc_map); 1629 bus_dmamem_free(ring->tx_desc_tag, desc, ring->tx_desc_map); 1630 ring->desc64 = NULL; 1631 ring->desc32 = NULL; 1632 ring->tx_desc_map = NULL; 1633 bus_dma_tag_destroy(ring->tx_desc_tag); 1634 ring->tx_desc_tag = NULL; 1635 } 1636} 1637 1638#ifdef DEVICE_POLLING 1639static poll_handler_t nfe_poll; 1640 1641 1642static int 1643nfe_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1644{ 1645 struct nfe_softc *sc = ifp->if_softc; 1646 uint32_t r; 1647 int rx_npkts = 0; 1648 1649 NFE_LOCK(sc); 1650 1651 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1652 NFE_UNLOCK(sc); 1653 return (rx_npkts); 1654 } 1655 1656 if (sc->nfe_framesize > MCLBYTES - ETHER_HDR_LEN) 1657 rx_npkts = nfe_jrxeof(sc, count, &rx_npkts); 1658 else 1659 rx_npkts = nfe_rxeof(sc, count, &rx_npkts); 1660 nfe_txeof(sc); 1661 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1662 nfe_start_locked(ifp); 1663 1664 if (cmd == POLL_AND_CHECK_STATUS) { 1665 if ((r = NFE_READ(sc, sc->nfe_irq_status)) == 0) { 1666 NFE_UNLOCK(sc); 1667 return (rx_npkts); 1668 } 1669 NFE_WRITE(sc, sc->nfe_irq_status, r); 1670 1671 if (r & NFE_IRQ_LINK) { 1672 NFE_READ(sc, NFE_PHY_STATUS); 1673 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1674 DPRINTF(sc, "link state changed\n"); 1675 } 1676 } 1677 NFE_UNLOCK(sc); 1678 return (rx_npkts); 1679} 1680#endif /* DEVICE_POLLING */ 1681 1682static void 1683nfe_set_intr(struct nfe_softc *sc) 1684{ 1685 1686 if (sc->nfe_msi != 0) 1687 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1688} 1689 1690 1691/* In MSIX, a write to mask reegisters behaves as XOR. */ 1692static __inline void 1693nfe_enable_intr(struct nfe_softc *sc) 1694{ 1695 1696 if (sc->nfe_msix != 0) { 1697 /* XXX Should have a better way to enable interrupts! */ 1698 if (NFE_READ(sc, sc->nfe_irq_mask) == 0) 1699 NFE_WRITE(sc, sc->nfe_irq_mask, sc->nfe_intrs); 1700 } else 1701 NFE_WRITE(sc, sc->nfe_irq_mask, sc->nfe_intrs); 1702} 1703 1704 1705static __inline void 1706nfe_disable_intr(struct nfe_softc *sc) 1707{ 1708 1709 if (sc->nfe_msix != 0) { 1710 /* XXX Should have a better way to disable interrupts! */ 1711 if (NFE_READ(sc, sc->nfe_irq_mask) != 0) 1712 NFE_WRITE(sc, sc->nfe_irq_mask, sc->nfe_nointrs); 1713 } else 1714 NFE_WRITE(sc, sc->nfe_irq_mask, sc->nfe_nointrs); 1715} 1716 1717 1718static int 1719nfe_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1720{ 1721 struct nfe_softc *sc; 1722 struct ifreq *ifr; 1723 struct mii_data *mii; 1724 int error, init, mask; 1725 1726 sc = ifp->if_softc; 1727 ifr = (struct ifreq *) data; 1728 error = 0; 1729 init = 0; 1730 switch (cmd) { 1731 case SIOCSIFMTU: 1732 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > NFE_JUMBO_MTU) 1733 error = EINVAL; 1734 else if (ifp->if_mtu != ifr->ifr_mtu) { 1735 if ((((sc->nfe_flags & NFE_JUMBO_SUP) == 0) || 1736 (sc->nfe_jumbo_disable != 0)) && 1737 ifr->ifr_mtu > ETHERMTU) 1738 error = EINVAL; 1739 else { 1740 NFE_LOCK(sc); 1741 ifp->if_mtu = ifr->ifr_mtu; 1742 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1743 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1744 nfe_init_locked(sc); 1745 } 1746 NFE_UNLOCK(sc); 1747 } 1748 } 1749 break; 1750 case SIOCSIFFLAGS: 1751 NFE_LOCK(sc); 1752 if (ifp->if_flags & IFF_UP) { 1753 /* 1754 * If only the PROMISC or ALLMULTI flag changes, then 1755 * don't do a full re-init of the chip, just update 1756 * the Rx filter. 1757 */ 1758 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) && 1759 ((ifp->if_flags ^ sc->nfe_if_flags) & 1760 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 1761 nfe_setmulti(sc); 1762 else 1763 nfe_init_locked(sc); 1764 } else { 1765 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1766 nfe_stop(ifp); 1767 } 1768 sc->nfe_if_flags = ifp->if_flags; 1769 NFE_UNLOCK(sc); 1770 error = 0; 1771 break; 1772 case SIOCADDMULTI: 1773 case SIOCDELMULTI: 1774 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1775 NFE_LOCK(sc); 1776 nfe_setmulti(sc); 1777 NFE_UNLOCK(sc); 1778 error = 0; 1779 } 1780 break; 1781 case SIOCSIFMEDIA: 1782 case SIOCGIFMEDIA: 1783 mii = device_get_softc(sc->nfe_miibus); 1784 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1785 break; 1786 case SIOCSIFCAP: 1787 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1788#ifdef DEVICE_POLLING 1789 if ((mask & IFCAP_POLLING) != 0) { 1790 if ((ifr->ifr_reqcap & IFCAP_POLLING) != 0) { 1791 error = ether_poll_register(nfe_poll, ifp); 1792 if (error) 1793 break; 1794 NFE_LOCK(sc); 1795 nfe_disable_intr(sc); 1796 ifp->if_capenable |= IFCAP_POLLING; 1797 NFE_UNLOCK(sc); 1798 } else { 1799 error = ether_poll_deregister(ifp); 1800 /* Enable interrupt even in error case */ 1801 NFE_LOCK(sc); 1802 nfe_enable_intr(sc); 1803 ifp->if_capenable &= ~IFCAP_POLLING; 1804 NFE_UNLOCK(sc); 1805 } 1806 } 1807#endif /* DEVICE_POLLING */ 1808 if ((mask & IFCAP_WOL_MAGIC) != 0 && 1809 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 1810 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 1811 if ((mask & IFCAP_TXCSUM) != 0 && 1812 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 1813 ifp->if_capenable ^= IFCAP_TXCSUM; 1814 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 1815 ifp->if_hwassist |= NFE_CSUM_FEATURES; 1816 else 1817 ifp->if_hwassist &= ~NFE_CSUM_FEATURES; 1818 } 1819 if ((mask & IFCAP_RXCSUM) != 0 && 1820 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 1821 ifp->if_capenable ^= IFCAP_RXCSUM; 1822 init++; 1823 } 1824 if ((mask & IFCAP_TSO4) != 0 && 1825 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 1826 ifp->if_capenable ^= IFCAP_TSO4; 1827 if ((IFCAP_TSO4 & ifp->if_capenable) != 0) 1828 ifp->if_hwassist |= CSUM_TSO; 1829 else 1830 ifp->if_hwassist &= ~CSUM_TSO; 1831 } 1832 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 1833 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 1834 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 1835 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 1836 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 1837 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1838 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 1839 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 1840 init++; 1841 } 1842 /* 1843 * XXX 1844 * It seems that VLAN stripping requires Rx checksum offload. 1845 * Unfortunately FreeBSD has no way to disable only Rx side 1846 * VLAN stripping. So when we know Rx checksum offload is 1847 * disabled turn entire hardware VLAN assist off. 1848 */ 1849 if ((ifp->if_capenable & IFCAP_RXCSUM) == 0) { 1850 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 1851 init++; 1852 ifp->if_capenable &= ~(IFCAP_VLAN_HWTAGGING | 1853 IFCAP_VLAN_HWTSO); 1854 } 1855 if (init > 0 && (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1856 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1857 nfe_init(sc); 1858 } 1859 VLAN_CAPABILITIES(ifp); 1860 break; 1861 default: 1862 error = ether_ioctl(ifp, cmd, data); 1863 break; 1864 } 1865 1866 return (error); 1867} 1868 1869 1870static int 1871nfe_intr(void *arg) 1872{ 1873 struct nfe_softc *sc; 1874 uint32_t status; 1875 1876 sc = (struct nfe_softc *)arg; 1877 1878 status = NFE_READ(sc, sc->nfe_irq_status); 1879 if (status == 0 || status == 0xffffffff) 1880 return (FILTER_STRAY); 1881 nfe_disable_intr(sc); 1882 taskqueue_enqueue_fast(sc->nfe_tq, &sc->nfe_int_task); 1883 1884 return (FILTER_HANDLED); 1885} 1886 1887 1888static void 1889nfe_int_task(void *arg, int pending) 1890{ 1891 struct nfe_softc *sc = arg; 1892 struct ifnet *ifp = sc->nfe_ifp; 1893 uint32_t r; 1894 int domore; 1895 1896 NFE_LOCK(sc); 1897 1898 if ((r = NFE_READ(sc, sc->nfe_irq_status)) == 0) { 1899 nfe_enable_intr(sc); 1900 NFE_UNLOCK(sc); 1901 return; /* not for us */ 1902 } 1903 NFE_WRITE(sc, sc->nfe_irq_status, r); 1904 1905 DPRINTFN(sc, 5, "nfe_intr: interrupt register %x\n", r); 1906 1907#ifdef DEVICE_POLLING 1908 if (ifp->if_capenable & IFCAP_POLLING) { 1909 NFE_UNLOCK(sc); 1910 return; 1911 } 1912#endif 1913 1914 if (r & NFE_IRQ_LINK) { 1915 NFE_READ(sc, NFE_PHY_STATUS); 1916 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1917 DPRINTF(sc, "link state changed\n"); 1918 } 1919 1920 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1921 NFE_UNLOCK(sc); 1922 nfe_disable_intr(sc); 1923 return; 1924 } 1925 1926 domore = 0; 1927 /* check Rx ring */ 1928 if (sc->nfe_framesize > MCLBYTES - ETHER_HDR_LEN) 1929 domore = nfe_jrxeof(sc, sc->nfe_process_limit, NULL); 1930 else 1931 domore = nfe_rxeof(sc, sc->nfe_process_limit, NULL); 1932 /* check Tx ring */ 1933 nfe_txeof(sc); 1934 1935 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1936 nfe_start_locked(ifp); 1937 1938 NFE_UNLOCK(sc); 1939 1940 if (domore || (NFE_READ(sc, sc->nfe_irq_status) != 0)) { 1941 taskqueue_enqueue_fast(sc->nfe_tq, &sc->nfe_int_task); 1942 return; 1943 } 1944 1945 /* Reenable interrupts. */ 1946 nfe_enable_intr(sc); 1947} 1948 1949 1950static __inline void 1951nfe_discard_rxbuf(struct nfe_softc *sc, int idx) 1952{ 1953 struct nfe_desc32 *desc32; 1954 struct nfe_desc64 *desc64; 1955 struct nfe_rx_data *data; 1956 struct mbuf *m; 1957 1958 data = &sc->rxq.data[idx]; 1959 m = data->m; 1960 1961 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1962 desc64 = &sc->rxq.desc64[idx]; 1963 /* VLAN packet may have overwritten it. */ 1964 desc64->physaddr[0] = htole32(NFE_ADDR_HI(data->paddr)); 1965 desc64->physaddr[1] = htole32(NFE_ADDR_LO(data->paddr)); 1966 desc64->length = htole16(m->m_len); 1967 desc64->flags = htole16(NFE_RX_READY); 1968 } else { 1969 desc32 = &sc->rxq.desc32[idx]; 1970 desc32->length = htole16(m->m_len); 1971 desc32->flags = htole16(NFE_RX_READY); 1972 } 1973} 1974 1975 1976static __inline void 1977nfe_discard_jrxbuf(struct nfe_softc *sc, int idx) 1978{ 1979 struct nfe_desc32 *desc32; 1980 struct nfe_desc64 *desc64; 1981 struct nfe_rx_data *data; 1982 struct mbuf *m; 1983 1984 data = &sc->jrxq.jdata[idx]; 1985 m = data->m; 1986 1987 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1988 desc64 = &sc->jrxq.jdesc64[idx]; 1989 /* VLAN packet may have overwritten it. */ 1990 desc64->physaddr[0] = htole32(NFE_ADDR_HI(data->paddr)); 1991 desc64->physaddr[1] = htole32(NFE_ADDR_LO(data->paddr)); 1992 desc64->length = htole16(m->m_len); 1993 desc64->flags = htole16(NFE_RX_READY); 1994 } else { 1995 desc32 = &sc->jrxq.jdesc32[idx]; 1996 desc32->length = htole16(m->m_len); 1997 desc32->flags = htole16(NFE_RX_READY); 1998 } 1999} 2000 2001 2002static int 2003nfe_newbuf(struct nfe_softc *sc, int idx) 2004{ 2005 struct nfe_rx_data *data; 2006 struct nfe_desc32 *desc32; 2007 struct nfe_desc64 *desc64; 2008 struct mbuf *m; 2009 bus_dma_segment_t segs[1]; 2010 bus_dmamap_t map; 2011 int nsegs; 2012 2013 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 2014 if (m == NULL) 2015 return (ENOBUFS); 2016 2017 m->m_len = m->m_pkthdr.len = MCLBYTES; 2018 m_adj(m, ETHER_ALIGN); 2019 2020 if (bus_dmamap_load_mbuf_sg(sc->rxq.rx_data_tag, sc->rxq.rx_spare_map, 2021 m, segs, &nsegs, BUS_DMA_NOWAIT) != 0) { 2022 m_freem(m); 2023 return (ENOBUFS); 2024 } 2025 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 2026 2027 data = &sc->rxq.data[idx]; 2028 if (data->m != NULL) { 2029 bus_dmamap_sync(sc->rxq.rx_data_tag, data->rx_data_map, 2030 BUS_DMASYNC_POSTREAD); 2031 bus_dmamap_unload(sc->rxq.rx_data_tag, data->rx_data_map); 2032 } 2033 map = data->rx_data_map; 2034 data->rx_data_map = sc->rxq.rx_spare_map; 2035 sc->rxq.rx_spare_map = map; 2036 bus_dmamap_sync(sc->rxq.rx_data_tag, data->rx_data_map, 2037 BUS_DMASYNC_PREREAD); 2038 data->paddr = segs[0].ds_addr; 2039 data->m = m; 2040 /* update mapping address in h/w descriptor */ 2041 if (sc->nfe_flags & NFE_40BIT_ADDR) { 2042 desc64 = &sc->rxq.desc64[idx]; 2043 desc64->physaddr[0] = htole32(NFE_ADDR_HI(segs[0].ds_addr)); 2044 desc64->physaddr[1] = htole32(NFE_ADDR_LO(segs[0].ds_addr)); 2045 desc64->length = htole16(segs[0].ds_len); 2046 desc64->flags = htole16(NFE_RX_READY); 2047 } else { 2048 desc32 = &sc->rxq.desc32[idx]; 2049 desc32->physaddr = htole32(NFE_ADDR_LO(segs[0].ds_addr)); 2050 desc32->length = htole16(segs[0].ds_len); 2051 desc32->flags = htole16(NFE_RX_READY); 2052 } 2053 2054 return (0); 2055} 2056 2057 2058static int 2059nfe_jnewbuf(struct nfe_softc *sc, int idx) 2060{ 2061 struct nfe_rx_data *data; 2062 struct nfe_desc32 *desc32; 2063 struct nfe_desc64 *desc64; 2064 struct mbuf *m; 2065 bus_dma_segment_t segs[1]; 2066 bus_dmamap_t map; 2067 int nsegs; 2068 2069 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 2070 if (m == NULL) 2071 return (ENOBUFS); 2072 if ((m->m_flags & M_EXT) == 0) { 2073 m_freem(m); 2074 return (ENOBUFS); 2075 } 2076 m->m_pkthdr.len = m->m_len = MJUM9BYTES; 2077 m_adj(m, ETHER_ALIGN); 2078 2079 if (bus_dmamap_load_mbuf_sg(sc->jrxq.jrx_data_tag, 2080 sc->jrxq.jrx_spare_map, m, segs, &nsegs, BUS_DMA_NOWAIT) != 0) { 2081 m_freem(m); 2082 return (ENOBUFS); 2083 } 2084 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 2085 2086 data = &sc->jrxq.jdata[idx]; 2087 if (data->m != NULL) { 2088 bus_dmamap_sync(sc->jrxq.jrx_data_tag, data->rx_data_map, 2089 BUS_DMASYNC_POSTREAD); 2090 bus_dmamap_unload(sc->jrxq.jrx_data_tag, data->rx_data_map); 2091 } 2092 map = data->rx_data_map; 2093 data->rx_data_map = sc->jrxq.jrx_spare_map; 2094 sc->jrxq.jrx_spare_map = map; 2095 bus_dmamap_sync(sc->jrxq.jrx_data_tag, data->rx_data_map, 2096 BUS_DMASYNC_PREREAD); 2097 data->paddr = segs[0].ds_addr; 2098 data->m = m; 2099 /* update mapping address in h/w descriptor */ 2100 if (sc->nfe_flags & NFE_40BIT_ADDR) { 2101 desc64 = &sc->jrxq.jdesc64[idx]; 2102 desc64->physaddr[0] = htole32(NFE_ADDR_HI(segs[0].ds_addr)); 2103 desc64->physaddr[1] = htole32(NFE_ADDR_LO(segs[0].ds_addr)); 2104 desc64->length = htole16(segs[0].ds_len); 2105 desc64->flags = htole16(NFE_RX_READY); 2106 } else { 2107 desc32 = &sc->jrxq.jdesc32[idx]; 2108 desc32->physaddr = htole32(NFE_ADDR_LO(segs[0].ds_addr)); 2109 desc32->length = htole16(segs[0].ds_len); 2110 desc32->flags = htole16(NFE_RX_READY); 2111 } 2112 2113 return (0); 2114} 2115 2116 2117static int 2118nfe_rxeof(struct nfe_softc *sc, int count, int *rx_npktsp) 2119{ 2120 struct ifnet *ifp = sc->nfe_ifp; 2121 struct nfe_desc32 *desc32; 2122 struct nfe_desc64 *desc64; 2123 struct nfe_rx_data *data; 2124 struct mbuf *m; 2125 uint16_t flags; 2126 int len, prog, rx_npkts; 2127 uint32_t vtag = 0; 2128 2129 rx_npkts = 0; 2130 NFE_LOCK_ASSERT(sc); 2131 2132 bus_dmamap_sync(sc->rxq.rx_desc_tag, sc->rxq.rx_desc_map, 2133 BUS_DMASYNC_POSTREAD); 2134 2135 for (prog = 0;;NFE_INC(sc->rxq.cur, NFE_RX_RING_COUNT), vtag = 0) { 2136 if (count <= 0) 2137 break; 2138 count--; 2139 2140 data = &sc->rxq.data[sc->rxq.cur]; 2141 2142 if (sc->nfe_flags & NFE_40BIT_ADDR) { 2143 desc64 = &sc->rxq.desc64[sc->rxq.cur]; 2144 vtag = le32toh(desc64->physaddr[1]); 2145 flags = le16toh(desc64->flags); 2146 len = le16toh(desc64->length) & NFE_RX_LEN_MASK; 2147 } else { 2148 desc32 = &sc->rxq.desc32[sc->rxq.cur]; 2149 flags = le16toh(desc32->flags); 2150 len = le16toh(desc32->length) & NFE_RX_LEN_MASK; 2151 } 2152 2153 if (flags & NFE_RX_READY) 2154 break; 2155 prog++; 2156 if ((sc->nfe_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 2157 if (!(flags & NFE_RX_VALID_V1)) { 2158 ifp->if_ierrors++; 2159 nfe_discard_rxbuf(sc, sc->rxq.cur); 2160 continue; 2161 } 2162 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) { 2163 flags &= ~NFE_RX_ERROR; 2164 len--; /* fix buffer length */ 2165 } 2166 } else { 2167 if (!(flags & NFE_RX_VALID_V2)) { 2168 ifp->if_ierrors++; 2169 nfe_discard_rxbuf(sc, sc->rxq.cur); 2170 continue; 2171 } 2172 2173 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) { 2174 flags &= ~NFE_RX_ERROR; 2175 len--; /* fix buffer length */ 2176 } 2177 } 2178 2179 if (flags & NFE_RX_ERROR) { 2180 ifp->if_ierrors++; 2181 nfe_discard_rxbuf(sc, sc->rxq.cur); 2182 continue; 2183 } 2184 2185 m = data->m; 2186 if (nfe_newbuf(sc, sc->rxq.cur) != 0) { 2187 ifp->if_iqdrops++; 2188 nfe_discard_rxbuf(sc, sc->rxq.cur); 2189 continue; 2190 } 2191 2192 if ((vtag & NFE_RX_VTAG) != 0 && 2193 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 2194 m->m_pkthdr.ether_vtag = vtag & 0xffff; 2195 m->m_flags |= M_VLANTAG; 2196 } 2197 2198 m->m_pkthdr.len = m->m_len = len; 2199 m->m_pkthdr.rcvif = ifp; 2200 2201 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) { 2202 if ((flags & NFE_RX_IP_CSUMOK) != 0) { 2203 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2204 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2205 if ((flags & NFE_RX_TCP_CSUMOK) != 0 || 2206 (flags & NFE_RX_UDP_CSUMOK) != 0) { 2207 m->m_pkthdr.csum_flags |= 2208 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2209 m->m_pkthdr.csum_data = 0xffff; 2210 } 2211 } 2212 } 2213 2214 ifp->if_ipackets++; 2215 2216 NFE_UNLOCK(sc); 2217 (*ifp->if_input)(ifp, m); 2218 NFE_LOCK(sc); 2219 rx_npkts++; 2220 } 2221 2222 if (prog > 0) 2223 bus_dmamap_sync(sc->rxq.rx_desc_tag, sc->rxq.rx_desc_map, 2224 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2225 2226 if (rx_npktsp != NULL) 2227 *rx_npktsp = rx_npkts; 2228 return (count > 0 ? 0 : EAGAIN); 2229} 2230 2231 2232static int 2233nfe_jrxeof(struct nfe_softc *sc, int count, int *rx_npktsp) 2234{ 2235 struct ifnet *ifp = sc->nfe_ifp; 2236 struct nfe_desc32 *desc32; 2237 struct nfe_desc64 *desc64; 2238 struct nfe_rx_data *data; 2239 struct mbuf *m; 2240 uint16_t flags; 2241 int len, prog, rx_npkts; 2242 uint32_t vtag = 0; 2243 2244 rx_npkts = 0; 2245 NFE_LOCK_ASSERT(sc); 2246 2247 bus_dmamap_sync(sc->jrxq.jrx_desc_tag, sc->jrxq.jrx_desc_map, 2248 BUS_DMASYNC_POSTREAD); 2249 2250 for (prog = 0;;NFE_INC(sc->jrxq.jcur, NFE_JUMBO_RX_RING_COUNT), 2251 vtag = 0) { 2252 if (count <= 0) 2253 break; 2254 count--; 2255 2256 data = &sc->jrxq.jdata[sc->jrxq.jcur]; 2257 2258 if (sc->nfe_flags & NFE_40BIT_ADDR) { 2259 desc64 = &sc->jrxq.jdesc64[sc->jrxq.jcur]; 2260 vtag = le32toh(desc64->physaddr[1]); 2261 flags = le16toh(desc64->flags); 2262 len = le16toh(desc64->length) & NFE_RX_LEN_MASK; 2263 } else { 2264 desc32 = &sc->jrxq.jdesc32[sc->jrxq.jcur]; 2265 flags = le16toh(desc32->flags); 2266 len = le16toh(desc32->length) & NFE_RX_LEN_MASK; 2267 } 2268 2269 if (flags & NFE_RX_READY) 2270 break; 2271 prog++; 2272 if ((sc->nfe_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 2273 if (!(flags & NFE_RX_VALID_V1)) { 2274 ifp->if_ierrors++; 2275 nfe_discard_jrxbuf(sc, sc->jrxq.jcur); 2276 continue; 2277 } 2278 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) { 2279 flags &= ~NFE_RX_ERROR; 2280 len--; /* fix buffer length */ 2281 } 2282 } else { 2283 if (!(flags & NFE_RX_VALID_V2)) { 2284 ifp->if_ierrors++; 2285 nfe_discard_jrxbuf(sc, sc->jrxq.jcur); 2286 continue; 2287 } 2288 2289 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) { 2290 flags &= ~NFE_RX_ERROR; 2291 len--; /* fix buffer length */ 2292 } 2293 } 2294 2295 if (flags & NFE_RX_ERROR) { 2296 ifp->if_ierrors++; 2297 nfe_discard_jrxbuf(sc, sc->jrxq.jcur); 2298 continue; 2299 } 2300 2301 m = data->m; 2302 if (nfe_jnewbuf(sc, sc->jrxq.jcur) != 0) { 2303 ifp->if_iqdrops++; 2304 nfe_discard_jrxbuf(sc, sc->jrxq.jcur); 2305 continue; 2306 } 2307 2308 if ((vtag & NFE_RX_VTAG) != 0 && 2309 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 2310 m->m_pkthdr.ether_vtag = vtag & 0xffff; 2311 m->m_flags |= M_VLANTAG; 2312 } 2313 2314 m->m_pkthdr.len = m->m_len = len; 2315 m->m_pkthdr.rcvif = ifp; 2316 2317 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) { 2318 if ((flags & NFE_RX_IP_CSUMOK) != 0) { 2319 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2320 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2321 if ((flags & NFE_RX_TCP_CSUMOK) != 0 || 2322 (flags & NFE_RX_UDP_CSUMOK) != 0) { 2323 m->m_pkthdr.csum_flags |= 2324 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2325 m->m_pkthdr.csum_data = 0xffff; 2326 } 2327 } 2328 } 2329 2330 ifp->if_ipackets++; 2331 2332 NFE_UNLOCK(sc); 2333 (*ifp->if_input)(ifp, m); 2334 NFE_LOCK(sc); 2335 rx_npkts++; 2336 } 2337 2338 if (prog > 0) 2339 bus_dmamap_sync(sc->jrxq.jrx_desc_tag, sc->jrxq.jrx_desc_map, 2340 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2341 2342 if (rx_npktsp != NULL) 2343 *rx_npktsp = rx_npkts; 2344 return (count > 0 ? 0 : EAGAIN); 2345} 2346 2347 2348static void 2349nfe_txeof(struct nfe_softc *sc) 2350{ 2351 struct ifnet *ifp = sc->nfe_ifp; 2352 struct nfe_desc32 *desc32; 2353 struct nfe_desc64 *desc64; 2354 struct nfe_tx_data *data = NULL; 2355 uint16_t flags; 2356 int cons, prog; 2357 2358 NFE_LOCK_ASSERT(sc); 2359 2360 bus_dmamap_sync(sc->txq.tx_desc_tag, sc->txq.tx_desc_map, 2361 BUS_DMASYNC_POSTREAD); 2362 2363 prog = 0; 2364 for (cons = sc->txq.next; cons != sc->txq.cur; 2365 NFE_INC(cons, NFE_TX_RING_COUNT)) { 2366 if (sc->nfe_flags & NFE_40BIT_ADDR) { 2367 desc64 = &sc->txq.desc64[cons]; 2368 flags = le16toh(desc64->flags); 2369 } else { 2370 desc32 = &sc->txq.desc32[cons]; 2371 flags = le16toh(desc32->flags); 2372 } 2373 2374 if (flags & NFE_TX_VALID) 2375 break; 2376 2377 prog++; 2378 sc->txq.queued--; 2379 data = &sc->txq.data[cons]; 2380 2381 if ((sc->nfe_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 2382 if ((flags & NFE_TX_LASTFRAG_V1) == 0) 2383 continue; 2384 if ((flags & NFE_TX_ERROR_V1) != 0) { 2385 device_printf(sc->nfe_dev, 2386 "tx v1 error 0x%4b\n", flags, NFE_V1_TXERR); 2387 2388 ifp->if_oerrors++; 2389 } else 2390 ifp->if_opackets++; 2391 } else { 2392 if ((flags & NFE_TX_LASTFRAG_V2) == 0) 2393 continue; 2394 if ((flags & NFE_TX_ERROR_V2) != 0) { 2395 device_printf(sc->nfe_dev, 2396 "tx v2 error 0x%4b\n", flags, NFE_V2_TXERR); 2397 ifp->if_oerrors++; 2398 } else 2399 ifp->if_opackets++; 2400 } 2401 2402 /* last fragment of the mbuf chain transmitted */ 2403 KASSERT(data->m != NULL, ("%s: freeing NULL mbuf!", __func__)); 2404 bus_dmamap_sync(sc->txq.tx_data_tag, data->tx_data_map, 2405 BUS_DMASYNC_POSTWRITE); 2406 bus_dmamap_unload(sc->txq.tx_data_tag, data->tx_data_map); 2407 m_freem(data->m); 2408 data->m = NULL; 2409 } 2410 2411 if (prog > 0) { 2412 sc->nfe_force_tx = 0; 2413 sc->txq.next = cons; 2414 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2415 if (sc->txq.queued == 0) 2416 sc->nfe_watchdog_timer = 0; 2417 } 2418} 2419 2420static int 2421nfe_encap(struct nfe_softc *sc, struct mbuf **m_head) 2422{ 2423 struct nfe_desc32 *desc32 = NULL; 2424 struct nfe_desc64 *desc64 = NULL; 2425 bus_dmamap_t map; 2426 bus_dma_segment_t segs[NFE_MAX_SCATTER]; 2427 int error, i, nsegs, prod, si; 2428 uint32_t tsosegsz; 2429 uint16_t cflags, flags; 2430 struct mbuf *m; 2431 2432 prod = si = sc->txq.cur; 2433 map = sc->txq.data[prod].tx_data_map; 2434 2435 error = bus_dmamap_load_mbuf_sg(sc->txq.tx_data_tag, map, *m_head, segs, 2436 &nsegs, BUS_DMA_NOWAIT); 2437 if (error == EFBIG) { 2438 m = m_collapse(*m_head, M_NOWAIT, NFE_MAX_SCATTER); 2439 if (m == NULL) { 2440 m_freem(*m_head); 2441 *m_head = NULL; 2442 return (ENOBUFS); 2443 } 2444 *m_head = m; 2445 error = bus_dmamap_load_mbuf_sg(sc->txq.tx_data_tag, map, 2446 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2447 if (error != 0) { 2448 m_freem(*m_head); 2449 *m_head = NULL; 2450 return (ENOBUFS); 2451 } 2452 } else if (error != 0) 2453 return (error); 2454 if (nsegs == 0) { 2455 m_freem(*m_head); 2456 *m_head = NULL; 2457 return (EIO); 2458 } 2459 2460 if (sc->txq.queued + nsegs >= NFE_TX_RING_COUNT - 2) { 2461 bus_dmamap_unload(sc->txq.tx_data_tag, map); 2462 return (ENOBUFS); 2463 } 2464 2465 m = *m_head; 2466 cflags = flags = 0; 2467 tsosegsz = 0; 2468 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2469 tsosegsz = (uint32_t)m->m_pkthdr.tso_segsz << 2470 NFE_TX_TSO_SHIFT; 2471 cflags &= ~(NFE_TX_IP_CSUM | NFE_TX_TCP_UDP_CSUM); 2472 cflags |= NFE_TX_TSO; 2473 } else if ((m->m_pkthdr.csum_flags & NFE_CSUM_FEATURES) != 0) { 2474 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 2475 cflags |= NFE_TX_IP_CSUM; 2476 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 2477 cflags |= NFE_TX_TCP_UDP_CSUM; 2478 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2479 cflags |= NFE_TX_TCP_UDP_CSUM; 2480 } 2481 2482 for (i = 0; i < nsegs; i++) { 2483 if (sc->nfe_flags & NFE_40BIT_ADDR) { 2484 desc64 = &sc->txq.desc64[prod]; 2485 desc64->physaddr[0] = 2486 htole32(NFE_ADDR_HI(segs[i].ds_addr)); 2487 desc64->physaddr[1] = 2488 htole32(NFE_ADDR_LO(segs[i].ds_addr)); 2489 desc64->vtag = 0; 2490 desc64->length = htole16(segs[i].ds_len - 1); 2491 desc64->flags = htole16(flags); 2492 } else { 2493 desc32 = &sc->txq.desc32[prod]; 2494 desc32->physaddr = 2495 htole32(NFE_ADDR_LO(segs[i].ds_addr)); 2496 desc32->length = htole16(segs[i].ds_len - 1); 2497 desc32->flags = htole16(flags); 2498 } 2499 2500 /* 2501 * Setting of the valid bit in the first descriptor is 2502 * deferred until the whole chain is fully setup. 2503 */ 2504 flags |= NFE_TX_VALID; 2505 2506 sc->txq.queued++; 2507 NFE_INC(prod, NFE_TX_RING_COUNT); 2508 } 2509 2510 /* 2511 * the whole mbuf chain has been DMA mapped, fix last/first descriptor. 2512 * csum flags, vtag and TSO belong to the first fragment only. 2513 */ 2514 if (sc->nfe_flags & NFE_40BIT_ADDR) { 2515 desc64->flags |= htole16(NFE_TX_LASTFRAG_V2); 2516 desc64 = &sc->txq.desc64[si]; 2517 if ((m->m_flags & M_VLANTAG) != 0) 2518 desc64->vtag = htole32(NFE_TX_VTAG | 2519 m->m_pkthdr.ether_vtag); 2520 if (tsosegsz != 0) { 2521 /* 2522 * XXX 2523 * The following indicates the descriptor element 2524 * is a 32bit quantity. 2525 */ 2526 desc64->length |= htole16((uint16_t)tsosegsz); 2527 desc64->flags |= htole16(tsosegsz >> 16); 2528 } 2529 /* 2530 * finally, set the valid/checksum/TSO bit in the first 2531 * descriptor. 2532 */ 2533 desc64->flags |= htole16(NFE_TX_VALID | cflags); 2534 } else { 2535 if (sc->nfe_flags & NFE_JUMBO_SUP) 2536 desc32->flags |= htole16(NFE_TX_LASTFRAG_V2); 2537 else 2538 desc32->flags |= htole16(NFE_TX_LASTFRAG_V1); 2539 desc32 = &sc->txq.desc32[si]; 2540 if (tsosegsz != 0) { 2541 /* 2542 * XXX 2543 * The following indicates the descriptor element 2544 * is a 32bit quantity. 2545 */ 2546 desc32->length |= htole16((uint16_t)tsosegsz); 2547 desc32->flags |= htole16(tsosegsz >> 16); 2548 } 2549 /* 2550 * finally, set the valid/checksum/TSO bit in the first 2551 * descriptor. 2552 */ 2553 desc32->flags |= htole16(NFE_TX_VALID | cflags); 2554 } 2555 2556 sc->txq.cur = prod; 2557 prod = (prod + NFE_TX_RING_COUNT - 1) % NFE_TX_RING_COUNT; 2558 sc->txq.data[si].tx_data_map = sc->txq.data[prod].tx_data_map; 2559 sc->txq.data[prod].tx_data_map = map; 2560 sc->txq.data[prod].m = m; 2561 2562 bus_dmamap_sync(sc->txq.tx_data_tag, map, BUS_DMASYNC_PREWRITE); 2563 2564 return (0); 2565} 2566 2567 2568static void 2569nfe_setmulti(struct nfe_softc *sc) 2570{ 2571 struct ifnet *ifp = sc->nfe_ifp; 2572 struct ifmultiaddr *ifma; 2573 int i; 2574 uint32_t filter; 2575 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN]; 2576 uint8_t etherbroadcastaddr[ETHER_ADDR_LEN] = { 2577 0xff, 0xff, 0xff, 0xff, 0xff, 0xff 2578 }; 2579 2580 NFE_LOCK_ASSERT(sc); 2581 2582 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 2583 bzero(addr, ETHER_ADDR_LEN); 2584 bzero(mask, ETHER_ADDR_LEN); 2585 goto done; 2586 } 2587 2588 bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN); 2589 bcopy(etherbroadcastaddr, mask, ETHER_ADDR_LEN); 2590 2591 if_maddr_rlock(ifp); 2592 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2593 u_char *addrp; 2594 2595 if (ifma->ifma_addr->sa_family != AF_LINK) 2596 continue; 2597 2598 addrp = LLADDR((struct sockaddr_dl *) ifma->ifma_addr); 2599 for (i = 0; i < ETHER_ADDR_LEN; i++) { 2600 u_int8_t mcaddr = addrp[i]; 2601 addr[i] &= mcaddr; 2602 mask[i] &= ~mcaddr; 2603 } 2604 } 2605 if_maddr_runlock(ifp); 2606 2607 for (i = 0; i < ETHER_ADDR_LEN; i++) { 2608 mask[i] |= addr[i]; 2609 } 2610 2611done: 2612 addr[0] |= 0x01; /* make sure multicast bit is set */ 2613 2614 NFE_WRITE(sc, NFE_MULTIADDR_HI, 2615 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 2616 NFE_WRITE(sc, NFE_MULTIADDR_LO, 2617 addr[5] << 8 | addr[4]); 2618 NFE_WRITE(sc, NFE_MULTIMASK_HI, 2619 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]); 2620 NFE_WRITE(sc, NFE_MULTIMASK_LO, 2621 mask[5] << 8 | mask[4]); 2622 2623 filter = NFE_READ(sc, NFE_RXFILTER); 2624 filter &= NFE_PFF_RX_PAUSE; 2625 filter |= NFE_RXFILTER_MAGIC; 2626 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PFF_PROMISC : NFE_PFF_U2M; 2627 NFE_WRITE(sc, NFE_RXFILTER, filter); 2628} 2629 2630 2631static void 2632nfe_start(struct ifnet *ifp) 2633{ 2634 struct nfe_softc *sc = ifp->if_softc; 2635 2636 NFE_LOCK(sc); 2637 nfe_start_locked(ifp); 2638 NFE_UNLOCK(sc); 2639} 2640 2641static void 2642nfe_start_locked(struct ifnet *ifp) 2643{ 2644 struct nfe_softc *sc = ifp->if_softc; 2645 struct mbuf *m0; 2646 int enq; 2647 2648 NFE_LOCK_ASSERT(sc); 2649 2650 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2651 IFF_DRV_RUNNING || sc->nfe_link == 0) 2652 return; 2653 2654 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) { 2655 IFQ_DRV_DEQUEUE(&ifp->if_snd, m0); 2656 if (m0 == NULL) 2657 break; 2658 2659 if (nfe_encap(sc, &m0) != 0) { 2660 if (m0 == NULL) 2661 break; 2662 IFQ_DRV_PREPEND(&ifp->if_snd, m0); 2663 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2664 break; 2665 } 2666 enq++; 2667 ETHER_BPF_MTAP(ifp, m0); 2668 } 2669 2670 if (enq > 0) { 2671 bus_dmamap_sync(sc->txq.tx_desc_tag, sc->txq.tx_desc_map, 2672 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2673 2674 /* kick Tx */ 2675 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl); 2676 2677 /* 2678 * Set a timeout in case the chip goes out to lunch. 2679 */ 2680 sc->nfe_watchdog_timer = 5; 2681 } 2682} 2683 2684 2685static void 2686nfe_watchdog(struct ifnet *ifp) 2687{ 2688 struct nfe_softc *sc = ifp->if_softc; 2689 2690 if (sc->nfe_watchdog_timer == 0 || --sc->nfe_watchdog_timer) 2691 return; 2692 2693 /* Check if we've lost Tx completion interrupt. */ 2694 nfe_txeof(sc); 2695 if (sc->txq.queued == 0) { 2696 if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 2697 "-- recovering\n"); 2698 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2699 nfe_start_locked(ifp); 2700 return; 2701 } 2702 /* Check if we've lost start Tx command. */ 2703 sc->nfe_force_tx++; 2704 if (sc->nfe_force_tx <= 3) { 2705 /* 2706 * If this is the case for watchdog timeout, the following 2707 * code should go to nfe_txeof(). 2708 */ 2709 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl); 2710 return; 2711 } 2712 sc->nfe_force_tx = 0; 2713 2714 if_printf(ifp, "watchdog timeout\n"); 2715 2716 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2717 ifp->if_oerrors++; 2718 nfe_init_locked(sc); 2719} 2720 2721 2722static void 2723nfe_init(void *xsc) 2724{ 2725 struct nfe_softc *sc = xsc; 2726 2727 NFE_LOCK(sc); 2728 nfe_init_locked(sc); 2729 NFE_UNLOCK(sc); 2730} 2731 2732 2733static void 2734nfe_init_locked(void *xsc) 2735{ 2736 struct nfe_softc *sc = xsc; 2737 struct ifnet *ifp = sc->nfe_ifp; 2738 struct mii_data *mii; 2739 uint32_t val; 2740 int error; 2741 2742 NFE_LOCK_ASSERT(sc); 2743 2744 mii = device_get_softc(sc->nfe_miibus); 2745 2746 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2747 return; 2748 2749 nfe_stop(ifp); 2750 2751 sc->nfe_framesize = ifp->if_mtu + NFE_RX_HEADERS; 2752 2753 nfe_init_tx_ring(sc, &sc->txq); 2754 if (sc->nfe_framesize > (MCLBYTES - ETHER_HDR_LEN)) 2755 error = nfe_init_jrx_ring(sc, &sc->jrxq); 2756 else 2757 error = nfe_init_rx_ring(sc, &sc->rxq); 2758 if (error != 0) { 2759 device_printf(sc->nfe_dev, 2760 "initialization failed: no memory for rx buffers\n"); 2761 nfe_stop(ifp); 2762 return; 2763 } 2764 2765 val = 0; 2766 if ((sc->nfe_flags & NFE_CORRECT_MACADDR) != 0) 2767 val |= NFE_MAC_ADDR_INORDER; 2768 NFE_WRITE(sc, NFE_TX_UNK, val); 2769 NFE_WRITE(sc, NFE_STATUS, 0); 2770 2771 if ((sc->nfe_flags & NFE_TX_FLOW_CTRL) != 0) 2772 NFE_WRITE(sc, NFE_TX_PAUSE_FRAME, NFE_TX_PAUSE_FRAME_DISABLE); 2773 2774 sc->rxtxctl = NFE_RXTX_BIT2; 2775 if (sc->nfe_flags & NFE_40BIT_ADDR) 2776 sc->rxtxctl |= NFE_RXTX_V3MAGIC; 2777 else if (sc->nfe_flags & NFE_JUMBO_SUP) 2778 sc->rxtxctl |= NFE_RXTX_V2MAGIC; 2779 2780 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2781 sc->rxtxctl |= NFE_RXTX_RXCSUM; 2782 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2783 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT | NFE_RXTX_VTAG_STRIP; 2784 2785 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl); 2786 DELAY(10); 2787 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 2788 2789 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2790 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE); 2791 else 2792 NFE_WRITE(sc, NFE_VTAG_CTL, 0); 2793 2794 NFE_WRITE(sc, NFE_SETUP_R6, 0); 2795 2796 /* set MAC address */ 2797 nfe_set_macaddr(sc, IF_LLADDR(ifp)); 2798 2799 /* tell MAC where rings are in memory */ 2800 if (sc->nfe_framesize > MCLBYTES - ETHER_HDR_LEN) { 2801 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, 2802 NFE_ADDR_HI(sc->jrxq.jphysaddr)); 2803 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, 2804 NFE_ADDR_LO(sc->jrxq.jphysaddr)); 2805 } else { 2806 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, 2807 NFE_ADDR_HI(sc->rxq.physaddr)); 2808 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, 2809 NFE_ADDR_LO(sc->rxq.physaddr)); 2810 } 2811 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, NFE_ADDR_HI(sc->txq.physaddr)); 2812 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, NFE_ADDR_LO(sc->txq.physaddr)); 2813 2814 NFE_WRITE(sc, NFE_RING_SIZE, 2815 (NFE_RX_RING_COUNT - 1) << 16 | 2816 (NFE_TX_RING_COUNT - 1)); 2817 2818 NFE_WRITE(sc, NFE_RXBUFSZ, sc->nfe_framesize); 2819 2820 /* force MAC to wakeup */ 2821 val = NFE_READ(sc, NFE_PWR_STATE); 2822 if ((val & NFE_PWR_WAKEUP) == 0) 2823 NFE_WRITE(sc, NFE_PWR_STATE, val | NFE_PWR_WAKEUP); 2824 DELAY(10); 2825 val = NFE_READ(sc, NFE_PWR_STATE); 2826 NFE_WRITE(sc, NFE_PWR_STATE, val | NFE_PWR_VALID); 2827 2828#if 1 2829 /* configure interrupts coalescing/mitigation */ 2830 NFE_WRITE(sc, NFE_IMTIMER, NFE_IM_DEFAULT); 2831#else 2832 /* no interrupt mitigation: one interrupt per packet */ 2833 NFE_WRITE(sc, NFE_IMTIMER, 970); 2834#endif 2835 2836 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC_10_100); 2837 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC); 2838 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC); 2839 2840 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */ 2841 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC); 2842 2843 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC); 2844 /* Disable WOL. */ 2845 NFE_WRITE(sc, NFE_WOL_CTL, 0); 2846 2847 sc->rxtxctl &= ~NFE_RXTX_BIT2; 2848 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 2849 DELAY(10); 2850 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl); 2851 2852 /* set Rx filter */ 2853 nfe_setmulti(sc); 2854 2855 /* enable Rx */ 2856 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START); 2857 2858 /* enable Tx */ 2859 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START); 2860 2861 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 2862 2863 /* Clear hardware stats. */ 2864 nfe_stats_clear(sc); 2865 2866#ifdef DEVICE_POLLING 2867 if (ifp->if_capenable & IFCAP_POLLING) 2868 nfe_disable_intr(sc); 2869 else 2870#endif 2871 nfe_set_intr(sc); 2872 nfe_enable_intr(sc); /* enable interrupts */ 2873 2874 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2875 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2876 2877 sc->nfe_link = 0; 2878 mii_mediachg(mii); 2879 2880 callout_reset(&sc->nfe_stat_ch, hz, nfe_tick, sc); 2881} 2882 2883 2884static void 2885nfe_stop(struct ifnet *ifp) 2886{ 2887 struct nfe_softc *sc = ifp->if_softc; 2888 struct nfe_rx_ring *rx_ring; 2889 struct nfe_jrx_ring *jrx_ring; 2890 struct nfe_tx_ring *tx_ring; 2891 struct nfe_rx_data *rdata; 2892 struct nfe_tx_data *tdata; 2893 int i; 2894 2895 NFE_LOCK_ASSERT(sc); 2896 2897 sc->nfe_watchdog_timer = 0; 2898 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2899 2900 callout_stop(&sc->nfe_stat_ch); 2901 2902 /* abort Tx */ 2903 NFE_WRITE(sc, NFE_TX_CTL, 0); 2904 2905 /* disable Rx */ 2906 NFE_WRITE(sc, NFE_RX_CTL, 0); 2907 2908 /* disable interrupts */ 2909 nfe_disable_intr(sc); 2910 2911 sc->nfe_link = 0; 2912 2913 /* free Rx and Tx mbufs still in the queues. */ 2914 rx_ring = &sc->rxq; 2915 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 2916 rdata = &rx_ring->data[i]; 2917 if (rdata->m != NULL) { 2918 bus_dmamap_sync(rx_ring->rx_data_tag, 2919 rdata->rx_data_map, BUS_DMASYNC_POSTREAD); 2920 bus_dmamap_unload(rx_ring->rx_data_tag, 2921 rdata->rx_data_map); 2922 m_freem(rdata->m); 2923 rdata->m = NULL; 2924 } 2925 } 2926 2927 if ((sc->nfe_flags & NFE_JUMBO_SUP) != 0) { 2928 jrx_ring = &sc->jrxq; 2929 for (i = 0; i < NFE_JUMBO_RX_RING_COUNT; i++) { 2930 rdata = &jrx_ring->jdata[i]; 2931 if (rdata->m != NULL) { 2932 bus_dmamap_sync(jrx_ring->jrx_data_tag, 2933 rdata->rx_data_map, BUS_DMASYNC_POSTREAD); 2934 bus_dmamap_unload(jrx_ring->jrx_data_tag, 2935 rdata->rx_data_map); 2936 m_freem(rdata->m); 2937 rdata->m = NULL; 2938 } 2939 } 2940 } 2941 2942 tx_ring = &sc->txq; 2943 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 2944 tdata = &tx_ring->data[i]; 2945 if (tdata->m != NULL) { 2946 bus_dmamap_sync(tx_ring->tx_data_tag, 2947 tdata->tx_data_map, BUS_DMASYNC_POSTWRITE); 2948 bus_dmamap_unload(tx_ring->tx_data_tag, 2949 tdata->tx_data_map); 2950 m_freem(tdata->m); 2951 tdata->m = NULL; 2952 } 2953 } 2954 /* Update hardware stats. */ 2955 nfe_stats_update(sc); 2956} 2957 2958 2959static int 2960nfe_ifmedia_upd(struct ifnet *ifp) 2961{ 2962 struct nfe_softc *sc = ifp->if_softc; 2963 struct mii_data *mii; 2964 2965 NFE_LOCK(sc); 2966 mii = device_get_softc(sc->nfe_miibus); 2967 mii_mediachg(mii); 2968 NFE_UNLOCK(sc); 2969 2970 return (0); 2971} 2972 2973 2974static void 2975nfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2976{ 2977 struct nfe_softc *sc; 2978 struct mii_data *mii; 2979 2980 sc = ifp->if_softc; 2981 2982 NFE_LOCK(sc); 2983 mii = device_get_softc(sc->nfe_miibus); 2984 mii_pollstat(mii); 2985 2986 ifmr->ifm_active = mii->mii_media_active; 2987 ifmr->ifm_status = mii->mii_media_status; 2988 NFE_UNLOCK(sc); 2989} 2990 2991 2992void 2993nfe_tick(void *xsc) 2994{ 2995 struct nfe_softc *sc; 2996 struct mii_data *mii; 2997 struct ifnet *ifp; 2998 2999 sc = (struct nfe_softc *)xsc; 3000 3001 NFE_LOCK_ASSERT(sc); 3002 3003 ifp = sc->nfe_ifp; 3004 3005 mii = device_get_softc(sc->nfe_miibus); 3006 mii_tick(mii); 3007 nfe_stats_update(sc); 3008 nfe_watchdog(ifp); 3009 callout_reset(&sc->nfe_stat_ch, hz, nfe_tick, sc); 3010} 3011 3012 3013static int 3014nfe_shutdown(device_t dev) 3015{ 3016 3017 return (nfe_suspend(dev)); 3018} 3019 3020 3021static void 3022nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr) 3023{ 3024 uint32_t val; 3025 3026 if ((sc->nfe_flags & NFE_CORRECT_MACADDR) == 0) { 3027 val = NFE_READ(sc, NFE_MACADDR_LO); 3028 addr[0] = (val >> 8) & 0xff; 3029 addr[1] = (val & 0xff); 3030 3031 val = NFE_READ(sc, NFE_MACADDR_HI); 3032 addr[2] = (val >> 24) & 0xff; 3033 addr[3] = (val >> 16) & 0xff; 3034 addr[4] = (val >> 8) & 0xff; 3035 addr[5] = (val & 0xff); 3036 } else { 3037 val = NFE_READ(sc, NFE_MACADDR_LO); 3038 addr[5] = (val >> 8) & 0xff; 3039 addr[4] = (val & 0xff); 3040 3041 val = NFE_READ(sc, NFE_MACADDR_HI); 3042 addr[3] = (val >> 24) & 0xff; 3043 addr[2] = (val >> 16) & 0xff; 3044 addr[1] = (val >> 8) & 0xff; 3045 addr[0] = (val & 0xff); 3046 } 3047} 3048 3049 3050static void 3051nfe_set_macaddr(struct nfe_softc *sc, uint8_t *addr) 3052{ 3053 3054 NFE_WRITE(sc, NFE_MACADDR_LO, addr[5] << 8 | addr[4]); 3055 NFE_WRITE(sc, NFE_MACADDR_HI, addr[3] << 24 | addr[2] << 16 | 3056 addr[1] << 8 | addr[0]); 3057} 3058 3059 3060/* 3061 * Map a single buffer address. 3062 */ 3063 3064static void 3065nfe_dma_map_segs(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3066{ 3067 struct nfe_dmamap_arg *ctx; 3068 3069 if (error != 0) 3070 return; 3071 3072 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 3073 3074 ctx = (struct nfe_dmamap_arg *)arg; 3075 ctx->nfe_busaddr = segs[0].ds_addr; 3076} 3077 3078 3079static int 3080sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3081{ 3082 int error, value; 3083 3084 if (!arg1) 3085 return (EINVAL); 3086 value = *(int *)arg1; 3087 error = sysctl_handle_int(oidp, &value, 0, req); 3088 if (error || !req->newptr) 3089 return (error); 3090 if (value < low || value > high) 3091 return (EINVAL); 3092 *(int *)arg1 = value; 3093 3094 return (0); 3095} 3096 3097 3098static int 3099sysctl_hw_nfe_proc_limit(SYSCTL_HANDLER_ARGS) 3100{ 3101 3102 return (sysctl_int_range(oidp, arg1, arg2, req, NFE_PROC_MIN, 3103 NFE_PROC_MAX)); 3104} 3105 3106 3107#define NFE_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 3108 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 3109#define NFE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 3110 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 3111 3112static void 3113nfe_sysctl_node(struct nfe_softc *sc) 3114{ 3115 struct sysctl_ctx_list *ctx; 3116 struct sysctl_oid_list *child, *parent; 3117 struct sysctl_oid *tree; 3118 struct nfe_hw_stats *stats; 3119 int error; 3120 3121 stats = &sc->nfe_stats; 3122 ctx = device_get_sysctl_ctx(sc->nfe_dev); 3123 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->nfe_dev)); 3124 SYSCTL_ADD_PROC(ctx, child, 3125 OID_AUTO, "process_limit", CTLTYPE_INT | CTLFLAG_RW, 3126 &sc->nfe_process_limit, 0, sysctl_hw_nfe_proc_limit, "I", 3127 "max number of Rx events to process"); 3128 3129 sc->nfe_process_limit = NFE_PROC_DEFAULT; 3130 error = resource_int_value(device_get_name(sc->nfe_dev), 3131 device_get_unit(sc->nfe_dev), "process_limit", 3132 &sc->nfe_process_limit); 3133 if (error == 0) { 3134 if (sc->nfe_process_limit < NFE_PROC_MIN || 3135 sc->nfe_process_limit > NFE_PROC_MAX) { 3136 device_printf(sc->nfe_dev, 3137 "process_limit value out of range; " 3138 "using default: %d\n", NFE_PROC_DEFAULT); 3139 sc->nfe_process_limit = NFE_PROC_DEFAULT; 3140 } 3141 } 3142 3143 if ((sc->nfe_flags & (NFE_MIB_V1 | NFE_MIB_V2 | NFE_MIB_V3)) == 0) 3144 return; 3145 3146 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 3147 NULL, "NFE statistics"); 3148 parent = SYSCTL_CHILDREN(tree); 3149 3150 /* Rx statistics. */ 3151 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 3152 NULL, "Rx MAC statistics"); 3153 child = SYSCTL_CHILDREN(tree); 3154 3155 NFE_SYSCTL_STAT_ADD32(ctx, child, "frame_errors", 3156 &stats->rx_frame_errors, "Framing Errors"); 3157 NFE_SYSCTL_STAT_ADD32(ctx, child, "extra_bytes", 3158 &stats->rx_extra_bytes, "Extra Bytes"); 3159 NFE_SYSCTL_STAT_ADD32(ctx, child, "late_cols", 3160 &stats->rx_late_cols, "Late Collisions"); 3161 NFE_SYSCTL_STAT_ADD32(ctx, child, "runts", 3162 &stats->rx_runts, "Runts"); 3163 NFE_SYSCTL_STAT_ADD32(ctx, child, "jumbos", 3164 &stats->rx_jumbos, "Jumbos"); 3165 NFE_SYSCTL_STAT_ADD32(ctx, child, "fifo_overuns", 3166 &stats->rx_fifo_overuns, "FIFO Overruns"); 3167 NFE_SYSCTL_STAT_ADD32(ctx, child, "crc_errors", 3168 &stats->rx_crc_errors, "CRC Errors"); 3169 NFE_SYSCTL_STAT_ADD32(ctx, child, "fae", 3170 &stats->rx_fae, "Frame Alignment Errors"); 3171 NFE_SYSCTL_STAT_ADD32(ctx, child, "len_errors", 3172 &stats->rx_len_errors, "Length Errors"); 3173 NFE_SYSCTL_STAT_ADD32(ctx, child, "unicast", 3174 &stats->rx_unicast, "Unicast Frames"); 3175 NFE_SYSCTL_STAT_ADD32(ctx, child, "multicast", 3176 &stats->rx_multicast, "Multicast Frames"); 3177 NFE_SYSCTL_STAT_ADD32(ctx, child, "broadcast", 3178 &stats->rx_broadcast, "Broadcast Frames"); 3179 if ((sc->nfe_flags & NFE_MIB_V2) != 0) { 3180 NFE_SYSCTL_STAT_ADD64(ctx, child, "octets", 3181 &stats->rx_octets, "Octets"); 3182 NFE_SYSCTL_STAT_ADD32(ctx, child, "pause", 3183 &stats->rx_pause, "Pause frames"); 3184 NFE_SYSCTL_STAT_ADD32(ctx, child, "drops", 3185 &stats->rx_drops, "Drop frames"); 3186 } 3187 3188 /* Tx statistics. */ 3189 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 3190 NULL, "Tx MAC statistics"); 3191 child = SYSCTL_CHILDREN(tree); 3192 NFE_SYSCTL_STAT_ADD64(ctx, child, "octets", 3193 &stats->tx_octets, "Octets"); 3194 NFE_SYSCTL_STAT_ADD32(ctx, child, "zero_rexmits", 3195 &stats->tx_zero_rexmits, "Zero Retransmits"); 3196 NFE_SYSCTL_STAT_ADD32(ctx, child, "one_rexmits", 3197 &stats->tx_one_rexmits, "One Retransmits"); 3198 NFE_SYSCTL_STAT_ADD32(ctx, child, "multi_rexmits", 3199 &stats->tx_multi_rexmits, "Multiple Retransmits"); 3200 NFE_SYSCTL_STAT_ADD32(ctx, child, "late_cols", 3201 &stats->tx_late_cols, "Late Collisions"); 3202 NFE_SYSCTL_STAT_ADD32(ctx, child, "fifo_underuns", 3203 &stats->tx_fifo_underuns, "FIFO Underruns"); 3204 NFE_SYSCTL_STAT_ADD32(ctx, child, "carrier_losts", 3205 &stats->tx_carrier_losts, "Carrier Losts"); 3206 NFE_SYSCTL_STAT_ADD32(ctx, child, "excess_deferrals", 3207 &stats->tx_excess_deferals, "Excess Deferrals"); 3208 NFE_SYSCTL_STAT_ADD32(ctx, child, "retry_errors", 3209 &stats->tx_retry_errors, "Retry Errors"); 3210 if ((sc->nfe_flags & NFE_MIB_V2) != 0) { 3211 NFE_SYSCTL_STAT_ADD32(ctx, child, "deferrals", 3212 &stats->tx_deferals, "Deferrals"); 3213 NFE_SYSCTL_STAT_ADD32(ctx, child, "frames", 3214 &stats->tx_frames, "Frames"); 3215 NFE_SYSCTL_STAT_ADD32(ctx, child, "pause", 3216 &stats->tx_pause, "Pause Frames"); 3217 } 3218 if ((sc->nfe_flags & NFE_MIB_V3) != 0) { 3219 NFE_SYSCTL_STAT_ADD32(ctx, child, "unicast", 3220 &stats->tx_deferals, "Unicast Frames"); 3221 NFE_SYSCTL_STAT_ADD32(ctx, child, "multicast", 3222 &stats->tx_frames, "Multicast Frames"); 3223 NFE_SYSCTL_STAT_ADD32(ctx, child, "broadcast", 3224 &stats->tx_pause, "Broadcast Frames"); 3225 } 3226} 3227 3228#undef NFE_SYSCTL_STAT_ADD32 3229#undef NFE_SYSCTL_STAT_ADD64 3230 3231static void 3232nfe_stats_clear(struct nfe_softc *sc) 3233{ 3234 int i, mib_cnt; 3235 3236 if ((sc->nfe_flags & NFE_MIB_V1) != 0) 3237 mib_cnt = NFE_NUM_MIB_STATV1; 3238 else if ((sc->nfe_flags & (NFE_MIB_V2 | NFE_MIB_V3)) != 0) 3239 mib_cnt = NFE_NUM_MIB_STATV2; 3240 else 3241 return; 3242 3243 for (i = 0; i < mib_cnt; i++) 3244 NFE_READ(sc, NFE_TX_OCTET + i * sizeof(uint32_t)); 3245 3246 if ((sc->nfe_flags & NFE_MIB_V3) != 0) { 3247 NFE_READ(sc, NFE_TX_UNICAST); 3248 NFE_READ(sc, NFE_TX_MULTICAST); 3249 NFE_READ(sc, NFE_TX_BROADCAST); 3250 } 3251} 3252 3253static void 3254nfe_stats_update(struct nfe_softc *sc) 3255{ 3256 struct nfe_hw_stats *stats; 3257 3258 NFE_LOCK_ASSERT(sc); 3259 3260 if ((sc->nfe_flags & (NFE_MIB_V1 | NFE_MIB_V2 | NFE_MIB_V3)) == 0) 3261 return; 3262 3263 stats = &sc->nfe_stats; 3264 stats->tx_octets += NFE_READ(sc, NFE_TX_OCTET); 3265 stats->tx_zero_rexmits += NFE_READ(sc, NFE_TX_ZERO_REXMIT); 3266 stats->tx_one_rexmits += NFE_READ(sc, NFE_TX_ONE_REXMIT); 3267 stats->tx_multi_rexmits += NFE_READ(sc, NFE_TX_MULTI_REXMIT); 3268 stats->tx_late_cols += NFE_READ(sc, NFE_TX_LATE_COL); 3269 stats->tx_fifo_underuns += NFE_READ(sc, NFE_TX_FIFO_UNDERUN); 3270 stats->tx_carrier_losts += NFE_READ(sc, NFE_TX_CARRIER_LOST); 3271 stats->tx_excess_deferals += NFE_READ(sc, NFE_TX_EXCESS_DEFERRAL); 3272 stats->tx_retry_errors += NFE_READ(sc, NFE_TX_RETRY_ERROR); 3273 stats->rx_frame_errors += NFE_READ(sc, NFE_RX_FRAME_ERROR); 3274 stats->rx_extra_bytes += NFE_READ(sc, NFE_RX_EXTRA_BYTES); 3275 stats->rx_late_cols += NFE_READ(sc, NFE_RX_LATE_COL); 3276 stats->rx_runts += NFE_READ(sc, NFE_RX_RUNT); 3277 stats->rx_jumbos += NFE_READ(sc, NFE_RX_JUMBO); 3278 stats->rx_fifo_overuns += NFE_READ(sc, NFE_RX_FIFO_OVERUN); 3279 stats->rx_crc_errors += NFE_READ(sc, NFE_RX_CRC_ERROR); 3280 stats->rx_fae += NFE_READ(sc, NFE_RX_FAE); 3281 stats->rx_len_errors += NFE_READ(sc, NFE_RX_LEN_ERROR); 3282 stats->rx_unicast += NFE_READ(sc, NFE_RX_UNICAST); 3283 stats->rx_multicast += NFE_READ(sc, NFE_RX_MULTICAST); 3284 stats->rx_broadcast += NFE_READ(sc, NFE_RX_BROADCAST); 3285 3286 if ((sc->nfe_flags & NFE_MIB_V2) != 0) { 3287 stats->tx_deferals += NFE_READ(sc, NFE_TX_DEFERAL); 3288 stats->tx_frames += NFE_READ(sc, NFE_TX_FRAME); 3289 stats->rx_octets += NFE_READ(sc, NFE_RX_OCTET); 3290 stats->tx_pause += NFE_READ(sc, NFE_TX_PAUSE); 3291 stats->rx_pause += NFE_READ(sc, NFE_RX_PAUSE); 3292 stats->rx_drops += NFE_READ(sc, NFE_RX_DROP); 3293 } 3294 3295 if ((sc->nfe_flags & NFE_MIB_V3) != 0) { 3296 stats->tx_unicast += NFE_READ(sc, NFE_TX_UNICAST); 3297 stats->tx_multicast += NFE_READ(sc, NFE_TX_MULTICAST); 3298 stats->tx_broadcast += NFE_READ(sc, NFE_TX_BROADCAST); 3299 } 3300} 3301 3302 3303static void 3304nfe_set_linkspeed(struct nfe_softc *sc) 3305{ 3306 struct mii_softc *miisc; 3307 struct mii_data *mii; 3308 int aneg, i, phyno; 3309 3310 NFE_LOCK_ASSERT(sc); 3311 3312 mii = device_get_softc(sc->nfe_miibus); 3313 mii_pollstat(mii); 3314 aneg = 0; 3315 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 3316 (IFM_ACTIVE | IFM_AVALID)) { 3317 switch IFM_SUBTYPE(mii->mii_media_active) { 3318 case IFM_10_T: 3319 case IFM_100_TX: 3320 return; 3321 case IFM_1000_T: 3322 aneg++; 3323 break; 3324 default: 3325 break; 3326 } 3327 } 3328 miisc = LIST_FIRST(&mii->mii_phys); 3329 phyno = miisc->mii_phy; 3330 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 3331 PHY_RESET(miisc); 3332 nfe_miibus_writereg(sc->nfe_dev, phyno, MII_100T2CR, 0); 3333 nfe_miibus_writereg(sc->nfe_dev, phyno, 3334 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 3335 nfe_miibus_writereg(sc->nfe_dev, phyno, 3336 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 3337 DELAY(1000); 3338 if (aneg != 0) { 3339 /* 3340 * Poll link state until nfe(4) get a 10/100Mbps link. 3341 */ 3342 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 3343 mii_pollstat(mii); 3344 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 3345 == (IFM_ACTIVE | IFM_AVALID)) { 3346 switch (IFM_SUBTYPE(mii->mii_media_active)) { 3347 case IFM_10_T: 3348 case IFM_100_TX: 3349 nfe_mac_config(sc, mii); 3350 return; 3351 default: 3352 break; 3353 } 3354 } 3355 NFE_UNLOCK(sc); 3356 pause("nfelnk", hz); 3357 NFE_LOCK(sc); 3358 } 3359 if (i == MII_ANEGTICKS_GIGE) 3360 device_printf(sc->nfe_dev, 3361 "establishing a link failed, WOL may not work!"); 3362 } 3363 /* 3364 * No link, force MAC to have 100Mbps, full-duplex link. 3365 * This is the last resort and may/may not work. 3366 */ 3367 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 3368 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 3369 nfe_mac_config(sc, mii); 3370} 3371 3372 3373static void 3374nfe_set_wol(struct nfe_softc *sc) 3375{ 3376 struct ifnet *ifp; 3377 uint32_t wolctl; 3378 int pmc; 3379 uint16_t pmstat; 3380 3381 NFE_LOCK_ASSERT(sc); 3382 3383 if (pci_find_cap(sc->nfe_dev, PCIY_PMG, &pmc) != 0) 3384 return; 3385 ifp = sc->nfe_ifp; 3386 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3387 wolctl = NFE_WOL_MAGIC; 3388 else 3389 wolctl = 0; 3390 NFE_WRITE(sc, NFE_WOL_CTL, wolctl); 3391 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) { 3392 nfe_set_linkspeed(sc); 3393 if ((sc->nfe_flags & NFE_PWR_MGMT) != 0) 3394 NFE_WRITE(sc, NFE_PWR2_CTL, 3395 NFE_READ(sc, NFE_PWR2_CTL) & ~NFE_PWR2_GATE_CLOCKS); 3396 /* Enable RX. */ 3397 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, 0); 3398 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, 0); 3399 NFE_WRITE(sc, NFE_RX_CTL, NFE_READ(sc, NFE_RX_CTL) | 3400 NFE_RX_START); 3401 } 3402 /* Request PME if WOL is requested. */ 3403 pmstat = pci_read_config(sc->nfe_dev, pmc + PCIR_POWER_STATUS, 2); 3404 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3405 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3406 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3407 pci_write_config(sc->nfe_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 3408} 3409