1/*- 2 * Copyright (C) 2012 Juniper Networks, Inc. 3 * Copyright (C) 2009-2012 Semihalf 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30#ifndef _NAND_NFC_FSL_H_ 31#define _NAND_NFC_FSL_H_ 32 33/* LBC BR/OR Registers layout definitions */ 34#define BR_V 0x00000001 35#define BR_V_SHIFT 0 36#define BR_MSEL 0x000000E0 37#define BR_MSEL_SHIFT 5 38#define BR_DECC_CHECK_MODE 0x00000600 39#define BR_DECC_CHECK_GEN 0x00000400 40 41#define OR_FCM_PAGESIZE 0x00000400 42 43/* Options definitions */ 44#define NAND_OPT_ECC_MODE_HW 1 45#define NAND_OPT_ECC_MODE_SOFT (1 << 1) 46 47/* FMR - Flash Mode Register */ 48#define FMR_CWTO 0xF000 49#define FMR_CWTO_SHIFT 12 50#define FMR_BOOT 0x0800 51#define FMR_ECCM 0x0100 52#define FMR_AL 0x0030 53#define FMR_AL_SHIFT 4 54#define FMR_OP 0x0003 55#define FMR_OP_SHIFT 0 56 57#define FIR_OP_NOP 0x0 /* No operation and end of sequence */ 58#define FIR_OP_CA 0x1 /* Issue current column address */ 59#define FIR_OP_PA 0x2 /* Issue current block+page address */ 60#define FIR_OP_UA 0x3 /* Issue user defined address */ 61#define FIR_OP_CM(x) (4 + (x)) /* Issue command from FCR[CMD(x)] */ 62#define FIR_OP_WB 0x8 /* Write FBCR bytes from FCM buffer */ 63#define FIR_OP_WS 0x9 /* Write 1 or 2 bytes from MDR[AS] */ 64#define FIR_OP_RB 0xA /* Read FBCR bytes to FCM buffer */ 65#define FIR_OP_RS 0xB /* Read 1 or 2 bytes to MDR[AS] */ 66#define FIR_OP_CW0 0xC /* Wait then issue FCR[CMD0] */ 67#define FIR_OP_CW1 0xD /* Wait then issue FCR[CMD1] */ 68#define FIR_OP_RBW 0xE /* Wait then read FBCR bytes */ 69#define FIR_OP_RSW 0xF /* Wait then read 1 or 2 bytes */ 70 71/* LTESR - Transfer Error Status Register */ 72#define LTESR_BM 0x80000000 73#define LTESR_FCT 0x40000000 74#define LTESR_PAR 0x20000000 75#define LTESR_WP 0x04000000 76#define LTESR_ATMW 0x00800000 77#define LTESR_ATMR 0x00400000 78#define LTESR_CS 0x00080000 79#define LTESR_CC 0x00000001 80 81#define LTESR_NAND_MASK (LTESR_FCT | LTESR_CC | LTESR_CS) 82 83/* FPAR - Flash Page Address Register */ 84#define FPAR_SP_PI 0x00007C00 85#define FPAR_SP_PI_SHIFT 10 86#define FPAR_SP_MS 0x00000200 87#define FPAR_SP_CI 0x000001FF 88#define FPAR_SP_CI_SHIFT 0 89#define FPAR_LP_PI 0x0003F000 90#define FPAR_LP_PI_SHIFT 12 91#define FPAR_LP_MS 0x00000800 92#define FPAR_LP_CI 0x000007FF 93#define FPAR_LP_CI_SHIFT 0 94 95#define FSL_FCM_WAIT_TIMEOUT 10 96 97#endif /* _NAND_NFC_FSL_H_ */ 98