1/*- 2 * Copyright (C) 2009-2012 Semihalf 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27/* Generic NAND driver */ 28 29#include <sys/cdefs.h> 30__FBSDID("$FreeBSD$"); 31 32#include <sys/param.h> 33#include <sys/systm.h> 34#include <sys/proc.h> 35#include <sys/bus.h> 36#include <sys/conf.h> 37#include <sys/endian.h> 38#include <sys/kernel.h> 39#include <sys/module.h> 40#include <sys/rman.h> 41#include <sys/lock.h> 42#include <sys/mutex.h> 43#include <sys/time.h> 44#include <sys/malloc.h> 45 46#include <dev/nand/nand.h> 47#include <dev/nand/nandbus.h> 48#include "nfc_if.h" 49#include "nand_if.h" 50#include "nandbus_if.h" 51 52 53static int onfi_nand_probe(device_t dev); 54static int large_nand_probe(device_t dev); 55static int small_nand_probe(device_t dev); 56static int generic_nand_attach(device_t dev); 57static int generic_nand_detach(device_t dev); 58 59static int generic_erase_block(device_t, uint32_t); 60static int generic_erase_block_intlv(device_t, uint32_t); 61static int generic_read_page (device_t, uint32_t, void *, uint32_t, uint32_t); 62static int generic_read_oob(device_t, uint32_t, void *, uint32_t, uint32_t); 63static int generic_program_page(device_t, uint32_t, void *, uint32_t, uint32_t); 64static int generic_program_page_intlv(device_t, uint32_t, void *, uint32_t, 65 uint32_t); 66static int generic_program_oob(device_t, uint32_t, void *, uint32_t, uint32_t); 67static int generic_is_blk_bad(device_t, uint32_t, uint8_t *); 68static int generic_get_ecc(device_t, void *, void *, int *); 69static int generic_correct_ecc(device_t, void *, void *, void *); 70 71static int small_read_page(device_t, uint32_t, void *, uint32_t, uint32_t); 72static int small_read_oob(device_t, uint32_t, void *, uint32_t, uint32_t); 73static int small_program_page(device_t, uint32_t, void *, uint32_t, uint32_t); 74static int small_program_oob(device_t, uint32_t, void *, uint32_t, uint32_t); 75 76static int onfi_is_blk_bad(device_t, uint32_t, uint8_t *); 77static int onfi_read_parameter(struct nand_chip *, struct onfi_chip_params *); 78 79static int nand_send_address(device_t, int32_t, int32_t, int8_t); 80 81static device_method_t onand_methods[] = { 82 /* Device interface */ 83 DEVMETHOD(device_probe, onfi_nand_probe), 84 DEVMETHOD(device_attach, generic_nand_attach), 85 DEVMETHOD(device_detach, generic_nand_detach), 86 87 DEVMETHOD(nand_read_page, generic_read_page), 88 DEVMETHOD(nand_program_page, generic_program_page), 89 DEVMETHOD(nand_program_page_intlv, generic_program_page_intlv), 90 DEVMETHOD(nand_read_oob, generic_read_oob), 91 DEVMETHOD(nand_program_oob, generic_program_oob), 92 DEVMETHOD(nand_erase_block, generic_erase_block), 93 DEVMETHOD(nand_erase_block_intlv, generic_erase_block_intlv), 94 95 DEVMETHOD(nand_is_blk_bad, onfi_is_blk_bad), 96 DEVMETHOD(nand_get_ecc, generic_get_ecc), 97 DEVMETHOD(nand_correct_ecc, generic_correct_ecc), 98 { 0, 0 } 99}; 100 101static device_method_t lnand_methods[] = { 102 /* Device interface */ 103 DEVMETHOD(device_probe, large_nand_probe), 104 DEVMETHOD(device_attach, generic_nand_attach), 105 DEVMETHOD(device_detach, generic_nand_detach), 106 107 DEVMETHOD(nand_read_page, generic_read_page), 108 DEVMETHOD(nand_program_page, generic_program_page), 109 DEVMETHOD(nand_read_oob, generic_read_oob), 110 DEVMETHOD(nand_program_oob, generic_program_oob), 111 DEVMETHOD(nand_erase_block, generic_erase_block), 112 113 DEVMETHOD(nand_is_blk_bad, generic_is_blk_bad), 114 DEVMETHOD(nand_get_ecc, generic_get_ecc), 115 DEVMETHOD(nand_correct_ecc, generic_correct_ecc), 116 { 0, 0 } 117}; 118 119static device_method_t snand_methods[] = { 120 /* Device interface */ 121 DEVMETHOD(device_probe, small_nand_probe), 122 DEVMETHOD(device_attach, generic_nand_attach), 123 DEVMETHOD(device_detach, generic_nand_detach), 124 125 DEVMETHOD(nand_read_page, small_read_page), 126 DEVMETHOD(nand_program_page, small_program_page), 127 DEVMETHOD(nand_read_oob, small_read_oob), 128 DEVMETHOD(nand_program_oob, small_program_oob), 129 DEVMETHOD(nand_erase_block, generic_erase_block), 130 131 DEVMETHOD(nand_is_blk_bad, generic_is_blk_bad), 132 DEVMETHOD(nand_get_ecc, generic_get_ecc), 133 DEVMETHOD(nand_correct_ecc, generic_correct_ecc), 134 { 0, 0 } 135}; 136 137devclass_t onand_devclass; 138devclass_t lnand_devclass; 139devclass_t snand_devclass; 140 141driver_t onand_driver = { 142 "onand", 143 onand_methods, 144 sizeof(struct nand_chip) 145}; 146 147driver_t lnand_driver = { 148 "lnand", 149 lnand_methods, 150 sizeof(struct nand_chip) 151}; 152 153driver_t snand_driver = { 154 "snand", 155 snand_methods, 156 sizeof(struct nand_chip) 157}; 158 159DRIVER_MODULE(onand, nandbus, onand_driver, onand_devclass, 0, 0); 160DRIVER_MODULE(lnand, nandbus, lnand_driver, lnand_devclass, 0, 0); 161DRIVER_MODULE(snand, nandbus, snand_driver, snand_devclass, 0, 0); 162 163static int 164onfi_nand_probe(device_t dev) 165{ 166 struct nandbus_ivar *ivar; 167 168 ivar = device_get_ivars(dev); 169 if (ivar && ivar->is_onfi) { 170 device_set_desc(dev, "ONFI compliant NAND"); 171 return (BUS_PROBE_DEFAULT); 172 } 173 174 return (ENODEV); 175} 176 177static int 178large_nand_probe(device_t dev) 179{ 180 struct nandbus_ivar *ivar; 181 182 ivar = device_get_ivars(dev); 183 if (ivar && !ivar->is_onfi && ivar->params->page_size >= 512) { 184 device_set_desc(dev, ivar->params->name); 185 return (BUS_PROBE_DEFAULT); 186 } 187 188 return (ENODEV); 189} 190 191static int 192small_nand_probe(device_t dev) 193{ 194 struct nandbus_ivar *ivar; 195 196 ivar = device_get_ivars(dev); 197 if (ivar && !ivar->is_onfi && ivar->params->page_size == 512) { 198 device_set_desc(dev, ivar->params->name); 199 return (BUS_PROBE_DEFAULT); 200 } 201 202 return (ENODEV); 203} 204 205static int 206generic_nand_attach(device_t dev) 207{ 208 struct nand_chip *chip; 209 struct nandbus_ivar *ivar; 210 struct onfi_chip_params *onfi_chip_params; 211 device_t nandbus, nfc; 212 int err; 213 214 chip = device_get_softc(dev); 215 chip->dev = dev; 216 217 ivar = device_get_ivars(dev); 218 chip->id.man_id = ivar->man_id; 219 chip->id.dev_id = ivar->dev_id; 220 chip->num = ivar->cs; 221 222 /* TODO remove when HW ECC supported */ 223 nandbus = device_get_parent(dev); 224 nfc = device_get_parent(nandbus); 225 226 chip->nand = device_get_softc(nfc); 227 228 if (ivar->is_onfi) { 229 onfi_chip_params = malloc(sizeof(struct onfi_chip_params), 230 M_NAND, M_WAITOK | M_ZERO); 231 if (onfi_chip_params == NULL) 232 return (ENOMEM); 233 234 if (onfi_read_parameter(chip, onfi_chip_params)) { 235 nand_debug(NDBG_GEN,"Could not read parameter page!\n"); 236 free(onfi_chip_params, M_NAND); 237 return (ENXIO); 238 } 239 240 nand_onfi_set_params(chip, onfi_chip_params); 241 /* Set proper column and row cycles */ 242 ivar->cols = (onfi_chip_params->address_cycles >> 4) & 0xf; 243 ivar->rows = onfi_chip_params->address_cycles & 0xf; 244 free(onfi_chip_params, M_NAND); 245 246 } else { 247 nand_set_params(chip, ivar->params); 248 } 249 250 err = nand_init_stat(chip); 251 if (err) { 252 generic_nand_detach(dev); 253 return (err); 254 } 255 256 err = nand_init_bbt(chip); 257 if (err) { 258 generic_nand_detach(dev); 259 return (err); 260 } 261 262 err = nand_make_dev(chip); 263 if (err) { 264 generic_nand_detach(dev); 265 return (err); 266 } 267 268 err = create_geom_disk(chip); 269 if (err) { 270 generic_nand_detach(dev); 271 return (err); 272 } 273 274 return (0); 275} 276 277static int 278generic_nand_detach(device_t dev) 279{ 280 struct nand_chip *chip; 281 282 chip = device_get_softc(dev); 283 284 nand_destroy_bbt(chip); 285 destroy_geom_disk(chip); 286 nand_destroy_dev(chip); 287 nand_destroy_stat(chip); 288 289 return (0); 290} 291 292static int 293can_write(device_t nandbus) 294{ 295 uint8_t status; 296 297 if (NANDBUS_WAIT_READY(nandbus, &status)) 298 return (0); 299 300 if (!(status & NAND_STATUS_WP)) { 301 nand_debug(NDBG_GEN,"Chip is write-protected"); 302 return (0); 303 } 304 305 return (1); 306} 307 308static int 309check_fail(device_t nandbus) 310{ 311 uint8_t status; 312 313 NANDBUS_WAIT_READY(nandbus, &status); 314 if (status & NAND_STATUS_FAIL) { 315 nand_debug(NDBG_GEN,"Status failed %x", status); 316 return (ENXIO); 317 } 318 319 return (0); 320} 321 322static uint16_t 323onfi_crc(const void *buf, size_t buflen) 324{ 325 int i, j; 326 uint16_t crc; 327 const uint8_t *bufptr; 328 329 bufptr = buf; 330 crc = 0x4f4e; 331 for (j = 0; j < buflen; j++) { 332 crc ^= *bufptr++ << 8; 333 for (i = 0; i < 8; i++) 334 if (crc & 0x8000) 335 crc = (crc << 1) ^ 0x8005; 336 else 337 crc <<= 1; 338 } 339 return crc; 340} 341 342static int 343onfi_read_parameter(struct nand_chip *chip, struct onfi_chip_params *chip_params) 344{ 345 device_t nandbus; 346 struct onfi_params params; 347 int found, sigcount, trycopy; 348 349 nand_debug(NDBG_GEN,"read parameter"); 350 351 nandbus = device_get_parent(chip->dev); 352 353 NANDBUS_SELECT_CS(nandbus, chip->num); 354 355 if (NANDBUS_SEND_COMMAND(nandbus, NAND_CMD_READ_PARAMETER)) 356 return (ENXIO); 357 358 if (nand_send_address(chip->dev, -1, -1, PAGE_PARAMETER_DEF)) 359 return (ENXIO); 360 361 if (NANDBUS_START_COMMAND(nandbus)) 362 return (ENXIO); 363 364 /* 365 * XXX Bogus DELAY, we really need a nandbus_wait_ready() here, but it's 366 * not accessible from here (static to nandbus). 367 */ 368 DELAY(1000); 369 370 /* 371 * The ONFI spec mandates a minimum of three copies of the parameter 372 * data, so loop up to 3 times trying to find good data. Each copy is 373 * validated by a signature of "ONFI" and a crc. There is a very strange 374 * rule that the signature is valid if any 2 of the 4 bytes are correct. 375 */ 376 for (found= 0, trycopy = 0; !found && trycopy < 3; trycopy++) { 377 NANDBUS_READ_BUFFER(nandbus, ¶ms, sizeof(struct onfi_params)); 378 sigcount = params.signature[0] == 'O'; 379 sigcount += params.signature[1] == 'N'; 380 sigcount += params.signature[2] == 'F'; 381 sigcount += params.signature[3] == 'I'; 382 if (sigcount < 2) 383 continue; 384 if (onfi_crc(¶ms, 254) != params.crc) 385 continue; 386 found = 1; 387 } 388 if (!found) 389 return (ENXIO); 390 391 chip_params->luns = params.luns; 392 chip_params->blocks_per_lun = le32dec(¶ms.blocks_per_lun); 393 chip_params->pages_per_block = le32dec(¶ms.pages_per_block); 394 chip_params->bytes_per_page = le32dec(¶ms.bytes_per_page); 395 chip_params->spare_bytes_per_page = le16dec(¶ms.spare_bytes_per_page); 396 chip_params->t_bers = le16dec(¶ms.t_bers); 397 chip_params->t_prog = le16dec(¶ms.t_prog); 398 chip_params->t_r = le16dec(¶ms.t_r); 399 chip_params->t_ccs = le16dec(¶ms.t_ccs); 400 chip_params->features = le16dec(¶ms.features); 401 chip_params->address_cycles = params.address_cycles; 402 403 return (0); 404} 405 406static int 407send_read_page(device_t nand, uint8_t start_command, uint8_t end_command, 408 uint32_t row, uint32_t column) 409{ 410 device_t nandbus = device_get_parent(nand); 411 412 if (NANDBUS_SEND_COMMAND(nandbus, start_command)) 413 return (ENXIO); 414 415 if (nand_send_address(nand, row, column, -1)) 416 return (ENXIO); 417 418 if (NANDBUS_SEND_COMMAND(nandbus, end_command)) 419 return (ENXIO); 420 421 if (NANDBUS_START_COMMAND(nandbus)) 422 return (ENXIO); 423 424 return (0); 425} 426 427static int 428generic_read_page(device_t nand, uint32_t page, void *buf, uint32_t len, 429 uint32_t offset) 430{ 431 struct nand_chip *chip; 432 struct page_stat *pg_stat; 433 device_t nandbus; 434 uint32_t row; 435 436 nand_debug(NDBG_GEN,"%p raw read page %x[%x] at %x", nand, page, len, offset); 437 chip = device_get_softc(nand); 438 nandbus = device_get_parent(nand); 439 440 if (nand_check_page_boundary(chip, page)) 441 return (ENXIO); 442 443 page_to_row(&chip->chip_geom, page, &row); 444 445 if (send_read_page(nand, NAND_CMD_READ, NAND_CMD_READ_END, row, 446 offset)) 447 return (ENXIO); 448 449 DELAY(chip->t_r); 450 451 NANDBUS_READ_BUFFER(nandbus, buf, len); 452 453 if (check_fail(nandbus)) 454 return (ENXIO); 455 456 pg_stat = &(chip->pg_stat[page]); 457 pg_stat->page_raw_read++; 458 459 return (0); 460} 461 462static int 463generic_read_oob(device_t nand, uint32_t page, void* buf, uint32_t len, 464 uint32_t offset) 465{ 466 struct nand_chip *chip; 467 device_t nandbus; 468 uint32_t row; 469 470 nand_debug(NDBG_GEN,"%p raw read oob %x[%x] at %x", nand, page, len, offset); 471 chip = device_get_softc(nand); 472 nandbus = device_get_parent(nand); 473 474 if (nand_check_page_boundary(chip, page)) { 475 nand_debug(NDBG_GEN,"page boundary check failed: %08x\n", page); 476 return (ENXIO); 477 } 478 479 page_to_row(&chip->chip_geom, page, &row); 480 481 offset += chip->chip_geom.page_size; 482 483 if (send_read_page(nand, NAND_CMD_READ, NAND_CMD_READ_END, row, 484 offset)) 485 return (ENXIO); 486 487 DELAY(chip->t_r); 488 489 NANDBUS_READ_BUFFER(nandbus, buf, len); 490 491 if (check_fail(nandbus)) 492 return (ENXIO); 493 494 return (0); 495} 496 497static int 498send_start_program_page(device_t nand, uint32_t row, uint32_t column) 499{ 500 device_t nandbus = device_get_parent(nand); 501 502 if (NANDBUS_SEND_COMMAND(nandbus, NAND_CMD_PROG)) 503 return (ENXIO); 504 505 if (nand_send_address(nand, row, column, -1)) 506 return (ENXIO); 507 508 return (0); 509} 510 511static int 512send_end_program_page(device_t nandbus, uint8_t end_command) 513{ 514 515 if (NANDBUS_SEND_COMMAND(nandbus, end_command)) 516 return (ENXIO); 517 518 if (NANDBUS_START_COMMAND(nandbus)) 519 return (ENXIO); 520 521 return (0); 522} 523 524static int 525generic_program_page(device_t nand, uint32_t page, void *buf, uint32_t len, 526 uint32_t offset) 527{ 528 struct nand_chip *chip; 529 struct page_stat *pg_stat; 530 device_t nandbus; 531 uint32_t row; 532 533 nand_debug(NDBG_GEN,"%p raw prog page %x[%x] at %x", nand, page, len, 534 offset); 535 chip = device_get_softc(nand); 536 nandbus = device_get_parent(nand); 537 538 if (nand_check_page_boundary(chip, page)) 539 return (ENXIO); 540 541 page_to_row(&chip->chip_geom, page, &row); 542 543 if (!can_write(nandbus)) 544 return (ENXIO); 545 546 if (send_start_program_page(nand, row, offset)) 547 return (ENXIO); 548 549 NANDBUS_WRITE_BUFFER(nandbus, buf, len); 550 551 if (send_end_program_page(nandbus, NAND_CMD_PROG_END)) 552 return (ENXIO); 553 554 DELAY(chip->t_prog); 555 556 if (check_fail(nandbus)) 557 return (ENXIO); 558 559 pg_stat = &(chip->pg_stat[page]); 560 pg_stat->page_raw_written++; 561 562 return (0); 563} 564 565static int 566generic_program_page_intlv(device_t nand, uint32_t page, void *buf, 567 uint32_t len, uint32_t offset) 568{ 569 struct nand_chip *chip; 570 struct page_stat *pg_stat; 571 device_t nandbus; 572 uint32_t row; 573 574 nand_debug(NDBG_GEN,"%p raw prog page %x[%x] at %x", nand, page, len, offset); 575 chip = device_get_softc(nand); 576 nandbus = device_get_parent(nand); 577 578 if (nand_check_page_boundary(chip, page)) 579 return (ENXIO); 580 581 page_to_row(&chip->chip_geom, page, &row); 582 583 if (!can_write(nandbus)) 584 return (ENXIO); 585 586 if (send_start_program_page(nand, row, offset)) 587 return (ENXIO); 588 589 NANDBUS_WRITE_BUFFER(nandbus, buf, len); 590 591 if (send_end_program_page(nandbus, NAND_CMD_PROG_INTLV)) 592 return (ENXIO); 593 594 DELAY(chip->t_prog); 595 596 if (check_fail(nandbus)) 597 return (ENXIO); 598 599 pg_stat = &(chip->pg_stat[page]); 600 pg_stat->page_raw_written++; 601 602 return (0); 603} 604 605static int 606generic_program_oob(device_t nand, uint32_t page, void* buf, uint32_t len, 607 uint32_t offset) 608{ 609 struct nand_chip *chip; 610 device_t nandbus; 611 uint32_t row; 612 613 nand_debug(NDBG_GEN,"%p raw prog oob %x[%x] at %x", nand, page, len, 614 offset); 615 chip = device_get_softc(nand); 616 nandbus = device_get_parent(nand); 617 618 if (nand_check_page_boundary(chip, page)) 619 return (ENXIO); 620 621 page_to_row(&chip->chip_geom, page, &row); 622 offset += chip->chip_geom.page_size; 623 624 if (!can_write(nandbus)) 625 return (ENXIO); 626 627 if (send_start_program_page(nand, row, offset)) 628 return (ENXIO); 629 630 NANDBUS_WRITE_BUFFER(nandbus, buf, len); 631 632 if (send_end_program_page(nandbus, NAND_CMD_PROG_END)) 633 return (ENXIO); 634 635 DELAY(chip->t_prog); 636 637 if (check_fail(nandbus)) 638 return (ENXIO); 639 640 return (0); 641} 642 643static int 644send_erase_block(device_t nand, uint32_t row, uint8_t second_command) 645{ 646 device_t nandbus = device_get_parent(nand); 647 648 if (NANDBUS_SEND_COMMAND(nandbus, NAND_CMD_ERASE)) 649 return (ENXIO); 650 651 if (nand_send_address(nand, row, -1, -1)) 652 return (ENXIO); 653 654 if (NANDBUS_SEND_COMMAND(nandbus, second_command)) 655 return (ENXIO); 656 657 if (NANDBUS_START_COMMAND(nandbus)) 658 return (ENXIO); 659 660 return (0); 661} 662 663static int 664generic_erase_block(device_t nand, uint32_t block) 665{ 666 struct block_stat *blk_stat; 667 struct nand_chip *chip; 668 device_t nandbus; 669 int row; 670 671 nand_debug(NDBG_GEN,"%p erase block %x", nand, block); 672 nandbus = device_get_parent(nand); 673 chip = device_get_softc(nand); 674 675 if (block >= (chip->chip_geom.blks_per_lun * chip->chip_geom.luns)) 676 return (ENXIO); 677 678 row = (block << chip->chip_geom.blk_shift) & 679 chip->chip_geom.blk_mask; 680 681 nand_debug(NDBG_GEN,"%p erase block row %x", nand, row); 682 683 if (!can_write(nandbus)) 684 return (ENXIO); 685 686 send_erase_block(nand, row, NAND_CMD_ERASE_END); 687 688 DELAY(chip->t_bers); 689 690 if (check_fail(nandbus)) 691 return (ENXIO); 692 693 blk_stat = &(chip->blk_stat[block]); 694 blk_stat->block_erased++; 695 696 return (0); 697} 698 699static int 700generic_erase_block_intlv(device_t nand, uint32_t block) 701{ 702 struct block_stat *blk_stat; 703 struct nand_chip *chip; 704 device_t nandbus; 705 int row; 706 707 nand_debug(NDBG_GEN,"%p erase block %x", nand, block); 708 nandbus = device_get_parent(nand); 709 chip = device_get_softc(nand); 710 711 if (block >= (chip->chip_geom.blks_per_lun * chip->chip_geom.luns)) 712 return (ENXIO); 713 714 row = (block << chip->chip_geom.blk_shift) & 715 chip->chip_geom.blk_mask; 716 717 if (!can_write(nandbus)) 718 return (ENXIO); 719 720 send_erase_block(nand, row, NAND_CMD_ERASE_INTLV); 721 722 DELAY(chip->t_bers); 723 724 if (check_fail(nandbus)) 725 return (ENXIO); 726 727 blk_stat = &(chip->blk_stat[block]); 728 blk_stat->block_erased++; 729 730 return (0); 731 732} 733 734static int 735onfi_is_blk_bad(device_t device, uint32_t block_number, uint8_t *bad) 736{ 737 struct nand_chip *chip; 738 int page_number, i, j, err; 739 uint8_t *oob; 740 741 chip = device_get_softc(device); 742 743 oob = malloc(chip->chip_geom.oob_size, M_NAND, M_WAITOK); 744 if (!oob) { 745 device_printf(device, "%s: cannot allocate oob\n", __func__); 746 return (ENOMEM); 747 } 748 749 page_number = block_number * chip->chip_geom.pgs_per_blk; 750 *bad = 0; 751 /* Check OOB of first and last page */ 752 for (i = 0; i < 2; i++, page_number+= chip->chip_geom.pgs_per_blk - 1) { 753 err = generic_read_oob(device, page_number, oob, 754 chip->chip_geom.oob_size, 0); 755 if (err) { 756 device_printf(device, "%s: cannot allocate oob\n", 757 __func__); 758 free(oob, M_NAND); 759 return (ENOMEM); 760 } 761 762 for (j = 0; j < chip->chip_geom.oob_size; j++) { 763 if (!oob[j]) { 764 *bad = 1; 765 free(oob, M_NAND); 766 return (0); 767 } 768 } 769 } 770 771 free(oob, M_NAND); 772 773 return (0); 774} 775 776static int 777send_small_read_page(device_t nand, uint8_t start_command, 778 uint32_t row, uint32_t column) 779{ 780 device_t nandbus = device_get_parent(nand); 781 782 if (NANDBUS_SEND_COMMAND(nandbus, start_command)) 783 return (ENXIO); 784 785 if (nand_send_address(nand, row, column, -1)) 786 return (ENXIO); 787 788 if (NANDBUS_START_COMMAND(nandbus)) 789 return (ENXIO); 790 791 return (0); 792} 793 794 795static int 796small_read_page(device_t nand, uint32_t page, void *buf, uint32_t len, 797 uint32_t offset) 798{ 799 struct nand_chip *chip; 800 struct page_stat *pg_stat; 801 device_t nandbus; 802 uint32_t row; 803 804 nand_debug(NDBG_GEN,"%p small read page %x[%x] at %x", nand, page, len, offset); 805 chip = device_get_softc(nand); 806 nandbus = device_get_parent(nand); 807 808 if (nand_check_page_boundary(chip, page)) 809 return (ENXIO); 810 811 page_to_row(&chip->chip_geom, page, &row); 812 813 if (offset < 256) { 814 if (send_small_read_page(nand, NAND_CMD_SMALLA, row, offset)) 815 return (ENXIO); 816 } else { 817 offset -= 256; 818 if (send_small_read_page(nandbus, NAND_CMD_SMALLB, row, offset)) 819 return (ENXIO); 820 } 821 822 DELAY(chip->t_r); 823 824 NANDBUS_READ_BUFFER(nandbus, buf, len); 825 826 if (check_fail(nandbus)) 827 return (ENXIO); 828 829 pg_stat = &(chip->pg_stat[page]); 830 pg_stat->page_raw_read++; 831 832 return (0); 833} 834 835static int 836small_read_oob(device_t nand, uint32_t page, void *buf, uint32_t len, 837 uint32_t offset) 838{ 839 struct nand_chip *chip; 840 struct page_stat *pg_stat; 841 device_t nandbus; 842 uint32_t row; 843 844 nand_debug(NDBG_GEN,"%p small read oob %x[%x] at %x", nand, page, len, offset); 845 chip = device_get_softc(nand); 846 nandbus = device_get_parent(nand); 847 848 if (nand_check_page_boundary(chip, page)) 849 return (ENXIO); 850 851 page_to_row(&chip->chip_geom, page, &row); 852 853 if (send_small_read_page(nand, NAND_CMD_SMALLOOB, row, 0)) 854 return (ENXIO); 855 856 DELAY(chip->t_r); 857 858 NANDBUS_READ_BUFFER(nandbus, buf, len); 859 860 if (check_fail(nandbus)) 861 return (ENXIO); 862 863 pg_stat = &(chip->pg_stat[page]); 864 pg_stat->page_raw_read++; 865 866 return (0); 867} 868 869static int 870small_program_page(device_t nand, uint32_t page, void* buf, uint32_t len, 871 uint32_t offset) 872{ 873 struct nand_chip *chip; 874 device_t nandbus; 875 uint32_t row; 876 877 nand_debug(NDBG_GEN,"%p small prog page %x[%x] at %x", nand, page, len, offset); 878 chip = device_get_softc(nand); 879 nandbus = device_get_parent(nand); 880 881 if (nand_check_page_boundary(chip, page)) 882 return (ENXIO); 883 884 page_to_row(&chip->chip_geom, page, &row); 885 886 if (!can_write(nandbus)) 887 return (ENXIO); 888 889 if (offset < 256) { 890 if (NANDBUS_SEND_COMMAND(nandbus, NAND_CMD_SMALLA)) 891 return (ENXIO); 892 } else { 893 if (NANDBUS_SEND_COMMAND(nandbus, NAND_CMD_SMALLB)) 894 return (ENXIO); 895 } 896 897 if (send_start_program_page(nand, row, offset)) 898 return (ENXIO); 899 900 NANDBUS_WRITE_BUFFER(nandbus, buf, len); 901 902 if (send_end_program_page(nandbus, NAND_CMD_PROG_END)) 903 return (ENXIO); 904 905 DELAY(chip->t_prog); 906 907 if (check_fail(nandbus)) 908 return (ENXIO); 909 910 return (0); 911} 912 913static int 914small_program_oob(device_t nand, uint32_t page, void* buf, uint32_t len, 915 uint32_t offset) 916{ 917 struct nand_chip *chip; 918 device_t nandbus; 919 uint32_t row; 920 921 nand_debug(NDBG_GEN,"%p small prog oob %x[%x] at %x", nand, page, len, offset); 922 chip = device_get_softc(nand); 923 nandbus = device_get_parent(nand); 924 925 if (nand_check_page_boundary(chip, page)) 926 return (ENXIO); 927 928 page_to_row(&chip->chip_geom, page, &row); 929 930 if (!can_write(nandbus)) 931 return (ENXIO); 932 933 if (NANDBUS_SEND_COMMAND(nandbus, NAND_CMD_SMALLOOB)) 934 return (ENXIO); 935 936 if (send_start_program_page(nand, row, offset)) 937 return (ENXIO); 938 939 NANDBUS_WRITE_BUFFER(nandbus, buf, len); 940 941 if (send_end_program_page(nandbus, NAND_CMD_PROG_END)) 942 return (ENXIO); 943 944 DELAY(chip->t_prog); 945 946 if (check_fail(nandbus)) 947 return (ENXIO); 948 949 return (0); 950} 951 952int 953nand_send_address(device_t nand, int32_t row, int32_t col, int8_t id) 954{ 955 struct nandbus_ivar *ivar; 956 device_t nandbus; 957 uint8_t addr; 958 int err = 0; 959 int i; 960 961 nandbus = device_get_parent(nand); 962 ivar = device_get_ivars(nand); 963 964 if (id != -1) { 965 nand_debug(NDBG_GEN,"send_address: send id %02x", id); 966 err = NANDBUS_SEND_ADDRESS(nandbus, id); 967 } 968 969 if (!err && col != -1) { 970 for (i = 0; i < ivar->cols; i++, col >>= 8) { 971 addr = (uint8_t)(col & 0xff); 972 nand_debug(NDBG_GEN,"send_address: send address column " 973 "%02x", addr); 974 err = NANDBUS_SEND_ADDRESS(nandbus, addr); 975 if (err) 976 break; 977 } 978 } 979 980 if (!err && row != -1) { 981 for (i = 0; i < ivar->rows; i++, row >>= 8) { 982 addr = (uint8_t)(row & 0xff); 983 nand_debug(NDBG_GEN,"send_address: send address row " 984 "%02x", addr); 985 err = NANDBUS_SEND_ADDRESS(nandbus, addr); 986 if (err) 987 break; 988 } 989 } 990 991 return (err); 992} 993 994static int 995generic_is_blk_bad(device_t dev, uint32_t block, uint8_t *bad) 996{ 997 struct nand_chip *chip; 998 int page_number, err, i; 999 uint8_t *oob; 1000 1001 chip = device_get_softc(dev); 1002 1003 oob = malloc(chip->chip_geom.oob_size, M_NAND, M_WAITOK); 1004 if (!oob) { 1005 device_printf(dev, "%s: cannot allocate OOB\n", __func__); 1006 return (ENOMEM); 1007 } 1008 1009 page_number = block * chip->chip_geom.pgs_per_blk; 1010 *bad = 0; 1011 1012 /* Check OOB of first and second page */ 1013 for (i = 0; i < 2; i++) { 1014 err = NAND_READ_OOB(dev, page_number + i, oob, 1015 chip->chip_geom.oob_size, 0); 1016 if (err) { 1017 device_printf(dev, "%s: cannot allocate OOB\n", 1018 __func__); 1019 free(oob, M_NAND); 1020 return (ENOMEM); 1021 } 1022 1023 if (!oob[0]) { 1024 *bad = 1; 1025 free(oob, M_NAND); 1026 return (0); 1027 } 1028 } 1029 1030 free(oob, M_NAND); 1031 1032 return (0); 1033} 1034 1035static int 1036generic_get_ecc(device_t dev, void *buf, void *ecc, int *needwrite) 1037{ 1038 struct nand_chip *chip = device_get_softc(dev); 1039 struct chip_geom *cg = &chip->chip_geom; 1040 1041 return (NANDBUS_GET_ECC(device_get_parent(dev), buf, cg->page_size, 1042 ecc, needwrite)); 1043} 1044 1045static int 1046generic_correct_ecc(device_t dev, void *buf, void *readecc, void *calcecc) 1047{ 1048 struct nand_chip *chip = device_get_softc(dev); 1049 struct chip_geom *cg = &chip->chip_geom; 1050 1051 return (NANDBUS_CORRECT_ECC(device_get_parent(dev), buf, 1052 cg->page_size, readecc, calcecc)); 1053} 1054 1055 1056#if 0 1057int 1058nand_chng_read_col(device_t nand, uint32_t col, void *buf, size_t len) 1059{ 1060 struct nand_chip *chip; 1061 device_t nandbus; 1062 1063 chip = device_get_softc(nand); 1064 nandbus = device_get_parent(nand); 1065 1066 if (NANDBUS_SEND_COMMAND(nandbus, NAND_CMD_CHNG_READ_COL)) 1067 return (ENXIO); 1068 1069 if (NANDBUS_SEND_ADDRESS(nandbus, -1, col, -1)) 1070 return (ENXIO); 1071 1072 if (NANDBUS_SEND_COMMAND(nandbus, NAND_CMD_CHNG_READ_COL_END)) 1073 return (ENXIO); 1074 1075 if (NANDBUS_START_COMMAND(nandbus)) 1076 return (ENXIO); 1077 1078 if (buf != NULL && len > 0) 1079 NANDBUS_READ_BUFFER(nandbus, buf, len); 1080 1081 return (0); 1082} 1083 1084int 1085nand_chng_write_col(device_t dev, uint32_t col, void *buf, 1086 size_t len) 1087{ 1088 struct nand_chip *chip; 1089 device_t nandbus; 1090 1091 chip = device_get_softc(dev); 1092 nandbus = device_get_parent(dev); 1093 1094 if (NANDBUS_SEND_COMMAND(nandbus, NAND_CMD_CHNG_WRITE_COL)) 1095 return (ENXIO); 1096 1097 if (NANDBUS_SEND_ADDRESS(nandbus, -1, col, -1)) 1098 return (ENXIO); 1099 1100 if (buf != NULL && len > 0) 1101 NANDBUS_WRITE_BUFFER(nandbus, buf, len); 1102 1103 if (NANDBUS_SEND_COMMAND(nandbus, NAND_CMD_CHNG_READ_COL_END)) 1104 return (ENXIO); 1105 1106 if (NANDBUS_START_COMMAND(nandbus)) 1107 return (ENXIO); 1108 1109 return (0); 1110} 1111 1112int 1113nand_copyback_read(device_t dev, uint32_t page, uint32_t col, 1114 void *buf, size_t len) 1115{ 1116 struct nand_chip *chip; 1117 struct page_stat *pg_stat; 1118 device_t nandbus; 1119 uint32_t row; 1120 1121 nand_debug(NDBG_GEN," raw read page %x[%x] at %x", page, col, len); 1122 chip = device_get_softc(dev); 1123 nandbus = device_get_parent(dev); 1124 1125 if (nand_check_page_boundary(chip, page)) 1126 return (ENXIO); 1127 1128 page_to_row(&chip->chip_geom, page, &row); 1129 1130 if (send_read_page(nand, NAND_CMD_READ, NAND_CMD_READ_CPBK, row, 0)) 1131 return (ENXIO); 1132 1133 DELAY(chip->t_r); 1134 if (check_fail(nandbus)) 1135 return (ENXIO); 1136 1137 if (buf != NULL && len > 0) 1138 NANDBUS_READ_BUFFER(nandbus, buf, len); 1139 1140 pg_stat = &(chip->pg_stat[page]); 1141 pg_stat->page_raw_read++; 1142 1143 return (0); 1144} 1145 1146int 1147nand_copyback_prog(device_t dev, uint32_t page, uint32_t col, 1148 void *buf, size_t len) 1149{ 1150 struct nand_chip *chip; 1151 struct page_stat *pg_stat; 1152 device_t nandbus; 1153 uint32_t row; 1154 1155 nand_debug(NDBG_GEN,"copyback prog page %x[%x]", page, len); 1156 chip = device_get_softc(dev); 1157 nandbus = device_get_parent(dev); 1158 1159 if (nand_check_page_boundary(chip, page)) 1160 return (ENXIO); 1161 1162 page_to_row(&chip->chip_geom, page, &row); 1163 1164 if (!can_write(nandbus)) 1165 return (ENXIO); 1166 1167 if (NANDBUS_SEND_COMMAND(nandbus, NAND_CMD_CHNG_WRITE_COL)) 1168 return (ENXIO); 1169 1170 if (NANDBUS_SEND_ADDRESS(nandbus, row, col, -1)) 1171 return (ENXIO); 1172 1173 if (buf != NULL && len > 0) 1174 NANDBUS_WRITE_BUFFER(nandbus, buf, len); 1175 1176 if (send_end_program_page(nandbus, NAND_CMD_PROG_END)) 1177 return (ENXIO); 1178 1179 DELAY(chip->t_prog); 1180 1181 if (check_fail(nandbus)) 1182 return (ENXIO); 1183 1184 pg_stat = &(chip->pg_stat[page]); 1185 pg_stat->page_raw_written++; 1186 1187 return (0); 1188} 1189 1190int 1191nand_copyback_prog_intlv(device_t dev, uint32_t page) 1192{ 1193 struct nand_chip *chip; 1194 struct page_stat *pg_stat; 1195 device_t nandbus; 1196 uint32_t row; 1197 1198 nand_debug(NDBG_GEN,"cache prog page %x", page); 1199 chip = device_get_softc(dev); 1200 nandbus = device_get_parent(dev); 1201 1202 if (nand_check_page_boundary(chip, page)) 1203 return (ENXIO); 1204 1205 page_to_row(&chip->chip_geom, page, &row); 1206 1207 if (!can_write(nandbus)) 1208 return (ENXIO); 1209 1210 if (send_start_program_page(nand, row, 0)) 1211 return (ENXIO); 1212 1213 if (send_end_program_page(nandbus, NAND_CMD_PROG_INTLV)) 1214 return (ENXIO); 1215 1216 DELAY(chip->t_prog); 1217 1218 if (check_fail(nandbus)) 1219 return (ENXIO); 1220 1221 pg_stat = &(chip->pg_stat[page]); 1222 pg_stat->page_raw_written++; 1223 1224 return (0); 1225} 1226 1227int 1228nand_prog_cache(device_t dev, uint32_t page, uint32_t col, 1229 void *buf, size_t len, uint8_t end) 1230{ 1231 struct nand_chip *chip; 1232 struct page_stat *pg_stat; 1233 device_t nandbus; 1234 uint32_t row; 1235 uint8_t command; 1236 1237 nand_debug(NDBG_GEN,"cache prog page %x[%x]", page, len); 1238 chip = device_get_softc(dev); 1239 nandbus = device_get_parent(dev); 1240 1241 if (nand_check_page_boundary(chip, page)) 1242 return (ENXIO); 1243 1244 page_to_row(&chip->chip_geom, page, &row); 1245 1246 if (!can_write(nandbus)) 1247 return (ENXIO); 1248 1249 if (send_start_program_page(dev, row, 0)) 1250 return (ENXIO); 1251 1252 NANDBUS_WRITE_BUFFER(nandbus, buf, len); 1253 1254 if (end) 1255 command = NAND_CMD_PROG_END; 1256 else 1257 command = NAND_CMD_PROG_CACHE; 1258 1259 if (send_end_program_page(nandbus, command)) 1260 return (ENXIO); 1261 1262 DELAY(chip->t_prog); 1263 1264 if (check_fail(nandbus)) 1265 return (ENXIO); 1266 1267 pg_stat = &(chip->pg_stat[page]); 1268 pg_stat->page_raw_written++; 1269 1270 return (0); 1271} 1272 1273int 1274nand_read_cache(device_t dev, uint32_t page, uint32_t col, 1275 void *buf, size_t len, uint8_t end) 1276{ 1277 struct nand_chip *chip; 1278 struct page_stat *pg_stat; 1279 device_t nandbus; 1280 uint32_t row; 1281 uint8_t command; 1282 1283 nand_debug(NDBG_GEN,"cache read page %x[%x] ", page, len); 1284 chip = device_get_softc(dev); 1285 nandbus = device_get_parent(dev); 1286 1287 if (nand_check_page_boundary(chip, page)) 1288 return (ENXIO); 1289 1290 page_to_row(&chip->chip_geom, page, &row); 1291 1292 if (page != -1) { 1293 if (NANDBUS_SEND_COMMAND(nandbus, NAND_CMD_READ)) 1294 return (ENXIO); 1295 1296 if (NANDBUS_SEND_ADDRESS(nandbus, row, col, -1)) 1297 return (ENXIO); 1298 } 1299 1300 if (end) 1301 command = NAND_CMD_READ_CACHE_END; 1302 else 1303 command = NAND_CMD_READ_CACHE; 1304 1305 if (NANDBUS_SEND_COMMAND(nandbus, command)) 1306 return (ENXIO); 1307 1308 if (NANDBUS_START_COMMAND(nandbus)) 1309 return (ENXIO); 1310 1311 DELAY(chip->t_r); 1312 if (check_fail(nandbus)) 1313 return (ENXIO); 1314 1315 if (buf != NULL && len > 0) 1316 NANDBUS_READ_BUFFER(nandbus, buf, len); 1317 1318 pg_stat = &(chip->pg_stat[page]); 1319 pg_stat->page_raw_read++; 1320 1321 return (0); 1322} 1323 1324int 1325nand_get_feature(device_t dev, uint8_t feat, void *buf) 1326{ 1327 struct nand_chip *chip; 1328 device_t nandbus; 1329 1330 nand_debug(NDBG_GEN,"nand get feature"); 1331 1332 chip = device_get_softc(dev); 1333 nandbus = device_get_parent(dev); 1334 1335 if (NANDBUS_SEND_COMMAND(nandbus, NAND_CMD_GET_FEATURE)) 1336 return (ENXIO); 1337 1338 if (NANDBUS_SEND_ADDRESS(nandbus, -1, -1, feat)) 1339 return (ENXIO); 1340 1341 if (NANDBUS_START_COMMAND(nandbus)) 1342 return (ENXIO); 1343 1344 DELAY(chip->t_r); 1345 NANDBUS_READ_BUFFER(nandbus, buf, 4); 1346 1347 return (0); 1348} 1349 1350int 1351nand_set_feature(device_t dev, uint8_t feat, void *buf) 1352{ 1353 struct nand_chip *chip; 1354 device_t nandbus; 1355 1356 nand_debug(NDBG_GEN,"nand set feature"); 1357 1358 chip = device_get_softc(dev); 1359 nandbus = device_get_parent(dev); 1360 1361 if (NANDBUS_SEND_COMMAND(nandbus, NAND_CMD_SET_FEATURE)) 1362 return (ENXIO); 1363 1364 if (NANDBUS_SEND_ADDRESS(nandbus, -1, -1, feat)) 1365 return (ENXIO); 1366 1367 NANDBUS_WRITE_BUFFER(nandbus, buf, 4); 1368 1369 if (NANDBUS_START_COMMAND(nandbus)) 1370 return (ENXIO); 1371 1372 return (0); 1373} 1374#endif 1375