if_my.c revision 148654
1/*- 2 * Written by: yen_cw@myson.com.tw 3 * Copyright (c) 2002 Myson Technology Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer, 11 * without modification, immediately at the beginning of the file. 12 * 2. The name of the author may not be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 19 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * Myson fast ethernet PCI NIC driver, available at: http://www.myson.com.tw/ 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/my/if_my.c 148654 2005-08-03 00:18:35Z rwatson $"); 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/sockio.h> 36#include <sys/mbuf.h> 37#include <sys/malloc.h> 38#include <sys/kernel.h> 39#include <sys/socket.h> 40#include <sys/queue.h> 41#include <sys/types.h> 42#include <sys/bus.h> 43#include <sys/module.h> 44#include <sys/lock.h> 45#include <sys/mutex.h> 46 47#define NBPFILTER 1 48 49#include <net/if.h> 50#include <net/if_arp.h> 51#include <net/ethernet.h> 52#include <net/if_media.h> 53#include <net/if_types.h> 54#include <net/if_dl.h> 55#include <net/bpf.h> 56 57#include <vm/vm.h> /* for vtophys */ 58#include <vm/pmap.h> /* for vtophys */ 59#include <machine/clock.h> /* for DELAY */ 60#include <machine/bus.h> 61#include <machine/resource.h> 62#include <sys/bus.h> 63#include <sys/rman.h> 64 65#include <dev/pci/pcireg.h> 66#include <dev/pci/pcivar.h> 67 68#include <dev/mii/mii.h> 69#include <dev/mii/miivar.h> 70 71#include "miibus_if.h" 72 73/* 74 * #define MY_USEIOSPACE 75 */ 76 77static int MY_USEIOSPACE = 1; 78 79#if (MY_USEIOSPACE) 80#define MY_RES SYS_RES_IOPORT 81#define MY_RID MY_PCI_LOIO 82#else 83#define MY_RES SYS_RES_MEMORY 84#define MY_RID MY_PCI_LOMEM 85#endif 86 87 88#include <dev/my/if_myreg.h> 89 90#ifndef lint 91static const char rcsid[] = 92"$Id: if_my.c,v 1.16 2003/04/15 06:37:25 mdodd Exp $"; 93#endif 94 95/* 96 * Various supported device vendors/types and their names. 97 */ 98struct my_type *my_info_tmp; 99static struct my_type my_devs[] = { 100 {MYSONVENDORID, MTD800ID, "Myson MTD80X Based Fast Ethernet Card"}, 101 {MYSONVENDORID, MTD803ID, "Myson MTD80X Based Fast Ethernet Card"}, 102 {MYSONVENDORID, MTD891ID, "Myson MTD89X Based Giga Ethernet Card"}, 103 {0, 0, NULL} 104}; 105 106/* 107 * Various supported PHY vendors/types and their names. Note that this driver 108 * will work with pretty much any MII-compliant PHY, so failure to positively 109 * identify the chip is not a fatal error. 110 */ 111static struct my_type my_phys[] = { 112 {MysonPHYID0, MysonPHYID0, "<MYSON MTD981>"}, 113 {SeeqPHYID0, SeeqPHYID0, "<SEEQ 80225>"}, 114 {AhdocPHYID0, AhdocPHYID0, "<AHDOC 101>"}, 115 {MarvellPHYID0, MarvellPHYID0, "<MARVELL 88E1000>"}, 116 {LevelOnePHYID0, LevelOnePHYID0, "<LevelOne LXT1000>"}, 117 {0, 0, "<MII-compliant physical interface>"} 118}; 119 120static int my_probe(device_t); 121static int my_attach(device_t); 122static int my_detach(device_t); 123static int my_newbuf(struct my_softc *, struct my_chain_onefrag *); 124static int my_encap(struct my_softc *, struct my_chain *, struct mbuf *); 125static void my_rxeof(struct my_softc *); 126static void my_txeof(struct my_softc *); 127static void my_txeoc(struct my_softc *); 128static void my_intr(void *); 129static void my_start(struct ifnet *); 130static int my_ioctl(struct ifnet *, u_long, caddr_t); 131static void my_init(void *); 132static void my_stop(struct my_softc *); 133static void my_watchdog(struct ifnet *); 134static void my_shutdown(device_t); 135static int my_ifmedia_upd(struct ifnet *); 136static void my_ifmedia_sts(struct ifnet *, struct ifmediareq *); 137static u_int16_t my_phy_readreg(struct my_softc *, int); 138static void my_phy_writereg(struct my_softc *, int, int); 139static void my_autoneg_xmit(struct my_softc *); 140static void my_autoneg_mii(struct my_softc *, int, int); 141static void my_setmode_mii(struct my_softc *, int); 142static void my_getmode_mii(struct my_softc *); 143static void my_setcfg(struct my_softc *, int); 144static void my_setmulti(struct my_softc *); 145static void my_reset(struct my_softc *); 146static int my_list_rx_init(struct my_softc *); 147static int my_list_tx_init(struct my_softc *); 148static long my_send_cmd_to_phy(struct my_softc *, int, int); 149 150#define MY_SETBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 151#define MY_CLRBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 152 153static device_method_t my_methods[] = { 154 /* Device interface */ 155 DEVMETHOD(device_probe, my_probe), 156 DEVMETHOD(device_attach, my_attach), 157 DEVMETHOD(device_detach, my_detach), 158 DEVMETHOD(device_shutdown, my_shutdown), 159 160 {0, 0} 161}; 162 163static driver_t my_driver = { 164 "my", 165 my_methods, 166 sizeof(struct my_softc) 167}; 168 169static devclass_t my_devclass; 170 171DRIVER_MODULE(my, pci, my_driver, my_devclass, 0, 0); 172MODULE_DEPEND(my, pci, 1, 1, 1); 173MODULE_DEPEND(my, ether, 1, 1, 1); 174 175static long 176my_send_cmd_to_phy(struct my_softc * sc, int opcode, int regad) 177{ 178 long miir; 179 int i; 180 int mask, data; 181 182 MY_LOCK(sc); 183 184 /* enable MII output */ 185 miir = CSR_READ_4(sc, MY_MANAGEMENT); 186 miir &= 0xfffffff0; 187 188 miir |= MY_MASK_MIIR_MII_WRITE + MY_MASK_MIIR_MII_MDO; 189 190 /* send 32 1's preamble */ 191 for (i = 0; i < 32; i++) { 192 /* low MDC; MDO is already high (miir) */ 193 miir &= ~MY_MASK_MIIR_MII_MDC; 194 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 195 196 /* high MDC */ 197 miir |= MY_MASK_MIIR_MII_MDC; 198 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 199 } 200 201 /* calculate ST+OP+PHYAD+REGAD+TA */ 202 data = opcode | (sc->my_phy_addr << 7) | (regad << 2); 203 204 /* sent out */ 205 mask = 0x8000; 206 while (mask) { 207 /* low MDC, prepare MDO */ 208 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO); 209 if (mask & data) 210 miir |= MY_MASK_MIIR_MII_MDO; 211 212 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 213 /* high MDC */ 214 miir |= MY_MASK_MIIR_MII_MDC; 215 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 216 DELAY(30); 217 218 /* next */ 219 mask >>= 1; 220 if (mask == 0x2 && opcode == MY_OP_READ) 221 miir &= ~MY_MASK_MIIR_MII_WRITE; 222 } 223 224 MY_UNLOCK(sc); 225 return miir; 226} 227 228 229static u_int16_t 230my_phy_readreg(struct my_softc * sc, int reg) 231{ 232 long miir; 233 int mask, data; 234 235 MY_LOCK(sc); 236 237 if (sc->my_info->my_did == MTD803ID) 238 data = CSR_READ_2(sc, MY_PHYBASE + reg * 2); 239 else { 240 miir = my_send_cmd_to_phy(sc, MY_OP_READ, reg); 241 242 /* read data */ 243 mask = 0x8000; 244 data = 0; 245 while (mask) { 246 /* low MDC */ 247 miir &= ~MY_MASK_MIIR_MII_MDC; 248 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 249 250 /* read MDI */ 251 miir = CSR_READ_4(sc, MY_MANAGEMENT); 252 if (miir & MY_MASK_MIIR_MII_MDI) 253 data |= mask; 254 255 /* high MDC, and wait */ 256 miir |= MY_MASK_MIIR_MII_MDC; 257 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 258 DELAY(30); 259 260 /* next */ 261 mask >>= 1; 262 } 263 264 /* low MDC */ 265 miir &= ~MY_MASK_MIIR_MII_MDC; 266 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 267 } 268 269 MY_UNLOCK(sc); 270 return (u_int16_t) data; 271} 272 273 274static void 275my_phy_writereg(struct my_softc * sc, int reg, int data) 276{ 277 long miir; 278 int mask; 279 280 MY_LOCK(sc); 281 282 if (sc->my_info->my_did == MTD803ID) 283 CSR_WRITE_2(sc, MY_PHYBASE + reg * 2, data); 284 else { 285 miir = my_send_cmd_to_phy(sc, MY_OP_WRITE, reg); 286 287 /* write data */ 288 mask = 0x8000; 289 while (mask) { 290 /* low MDC, prepare MDO */ 291 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO); 292 if (mask & data) 293 miir |= MY_MASK_MIIR_MII_MDO; 294 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 295 DELAY(1); 296 297 /* high MDC */ 298 miir |= MY_MASK_MIIR_MII_MDC; 299 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 300 DELAY(1); 301 302 /* next */ 303 mask >>= 1; 304 } 305 306 /* low MDC */ 307 miir &= ~MY_MASK_MIIR_MII_MDC; 308 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 309 } 310 MY_UNLOCK(sc); 311 return; 312} 313 314 315/* 316 * Program the 64-bit multicast hash filter. 317 */ 318static void 319my_setmulti(struct my_softc * sc) 320{ 321 struct ifnet *ifp; 322 int h = 0; 323 u_int32_t hashes[2] = {0, 0}; 324 struct ifmultiaddr *ifma; 325 u_int32_t rxfilt; 326 int mcnt = 0; 327 328 MY_LOCK(sc); 329 330 ifp = sc->my_ifp; 331 332 rxfilt = CSR_READ_4(sc, MY_TCRRCR); 333 334 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 335 rxfilt |= MY_AM; 336 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt); 337 CSR_WRITE_4(sc, MY_MAR0, 0xFFFFFFFF); 338 CSR_WRITE_4(sc, MY_MAR1, 0xFFFFFFFF); 339 340 MY_UNLOCK(sc); 341 342 return; 343 } 344 /* first, zot all the existing hash bits */ 345 CSR_WRITE_4(sc, MY_MAR0, 0); 346 CSR_WRITE_4(sc, MY_MAR1, 0); 347 348 /* now program new ones */ 349 IF_ADDR_LOCK(ifp); 350 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 351 if (ifma->ifma_addr->sa_family != AF_LINK) 352 continue; 353 h = ~ether_crc32_be(LLADDR((struct sockaddr_dl *) 354 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 355 if (h < 32) 356 hashes[0] |= (1 << h); 357 else 358 hashes[1] |= (1 << (h - 32)); 359 mcnt++; 360 } 361 IF_ADDR_UNLOCK(ifp); 362 363 if (mcnt) 364 rxfilt |= MY_AM; 365 else 366 rxfilt &= ~MY_AM; 367 CSR_WRITE_4(sc, MY_MAR0, hashes[0]); 368 CSR_WRITE_4(sc, MY_MAR1, hashes[1]); 369 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt); 370 MY_UNLOCK(sc); 371 return; 372} 373 374/* 375 * Initiate an autonegotiation session. 376 */ 377static void 378my_autoneg_xmit(struct my_softc * sc) 379{ 380 u_int16_t phy_sts = 0; 381 382 MY_LOCK(sc); 383 384 my_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); 385 DELAY(500); 386 while (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_RESET); 387 388 phy_sts = my_phy_readreg(sc, PHY_BMCR); 389 phy_sts |= PHY_BMCR_AUTONEGENBL | PHY_BMCR_AUTONEGRSTR; 390 my_phy_writereg(sc, PHY_BMCR, phy_sts); 391 392 MY_UNLOCK(sc); 393 return; 394} 395 396 397/* 398 * Invoke autonegotiation on a PHY. 399 */ 400static void 401my_autoneg_mii(struct my_softc * sc, int flag, int verbose) 402{ 403 u_int16_t phy_sts = 0, media, advert, ability; 404 u_int16_t ability2 = 0; 405 struct ifnet *ifp; 406 struct ifmedia *ifm; 407 408 MY_LOCK(sc); 409 410 ifm = &sc->ifmedia; 411 ifp = sc->my_ifp; 412 413 ifm->ifm_media = IFM_ETHER | IFM_AUTO; 414 415#ifndef FORCE_AUTONEG_TFOUR 416 /* 417 * First, see if autoneg is supported. If not, there's no point in 418 * continuing. 419 */ 420 phy_sts = my_phy_readreg(sc, PHY_BMSR); 421 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) { 422 if (verbose) 423 printf("my%d: autonegotiation not supported\n", 424 sc->my_unit); 425 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 426 MY_UNLOCK(sc); 427 return; 428 } 429#endif 430 switch (flag) { 431 case MY_FLAG_FORCEDELAY: 432 /* 433 * XXX Never use this option anywhere but in the probe 434 * routine: making the kernel stop dead in its tracks for 435 * three whole seconds after we've gone multi-user is really 436 * bad manners. 437 */ 438 my_autoneg_xmit(sc); 439 DELAY(5000000); 440 break; 441 case MY_FLAG_SCHEDDELAY: 442 /* 443 * Wait for the transmitter to go idle before starting an 444 * autoneg session, otherwise my_start() may clobber our 445 * timeout, and we don't want to allow transmission during an 446 * autoneg session since that can screw it up. 447 */ 448 if (sc->my_cdata.my_tx_head != NULL) { 449 sc->my_want_auto = 1; 450 MY_UNLOCK(sc); 451 return; 452 } 453 my_autoneg_xmit(sc); 454 ifp->if_timer = 5; 455 sc->my_autoneg = 1; 456 sc->my_want_auto = 0; 457 MY_UNLOCK(sc); 458 return; 459 case MY_FLAG_DELAYTIMEO: 460 ifp->if_timer = 0; 461 sc->my_autoneg = 0; 462 break; 463 default: 464 printf("my%d: invalid autoneg flag: %d\n", sc->my_unit, flag); 465 MY_UNLOCK(sc); 466 return; 467 } 468 469 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) { 470 if (verbose) 471 printf("my%d: autoneg complete, ", sc->my_unit); 472 phy_sts = my_phy_readreg(sc, PHY_BMSR); 473 } else { 474 if (verbose) 475 printf("my%d: autoneg not complete, ", sc->my_unit); 476 } 477 478 media = my_phy_readreg(sc, PHY_BMCR); 479 480 /* Link is good. Report modes and set duplex mode. */ 481 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) { 482 if (verbose) 483 printf("my%d: link status good. ", sc->my_unit); 484 advert = my_phy_readreg(sc, PHY_ANAR); 485 ability = my_phy_readreg(sc, PHY_LPAR); 486 if ((sc->my_pinfo->my_vid == MarvellPHYID0) || 487 (sc->my_pinfo->my_vid == LevelOnePHYID0)) { 488 ability2 = my_phy_readreg(sc, PHY_1000SR); 489 if (ability2 & PHY_1000SR_1000BTXFULL) { 490 advert = 0; 491 ability = 0; 492 /* 493 * this version did not support 1000M, 494 * ifm->ifm_media = 495 * IFM_ETHER|IFM_1000_T|IFM_FDX; 496 */ 497 ifm->ifm_media = 498 IFM_ETHER | IFM_100_TX | IFM_FDX; 499 media &= ~PHY_BMCR_SPEEDSEL; 500 media |= PHY_BMCR_1000; 501 media |= PHY_BMCR_DUPLEX; 502 printf("(full-duplex, 1000Mbps)\n"); 503 } else if (ability2 & PHY_1000SR_1000BTXHALF) { 504 advert = 0; 505 ability = 0; 506 /* 507 * this version did not support 1000M, 508 * ifm->ifm_media = IFM_ETHER|IFM_1000_T; 509 */ 510 ifm->ifm_media = IFM_ETHER | IFM_100_TX; 511 media &= ~PHY_BMCR_SPEEDSEL; 512 media &= ~PHY_BMCR_DUPLEX; 513 media |= PHY_BMCR_1000; 514 printf("(half-duplex, 1000Mbps)\n"); 515 } 516 } 517 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) { 518 ifm->ifm_media = IFM_ETHER | IFM_100_T4; 519 media |= PHY_BMCR_SPEEDSEL; 520 media &= ~PHY_BMCR_DUPLEX; 521 printf("(100baseT4)\n"); 522 } else if (advert & PHY_ANAR_100BTXFULL && 523 ability & PHY_ANAR_100BTXFULL) { 524 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX; 525 media |= PHY_BMCR_SPEEDSEL; 526 media |= PHY_BMCR_DUPLEX; 527 printf("(full-duplex, 100Mbps)\n"); 528 } else if (advert & PHY_ANAR_100BTXHALF && 529 ability & PHY_ANAR_100BTXHALF) { 530 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX; 531 media |= PHY_BMCR_SPEEDSEL; 532 media &= ~PHY_BMCR_DUPLEX; 533 printf("(half-duplex, 100Mbps)\n"); 534 } else if (advert & PHY_ANAR_10BTFULL && 535 ability & PHY_ANAR_10BTFULL) { 536 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX; 537 media &= ~PHY_BMCR_SPEEDSEL; 538 media |= PHY_BMCR_DUPLEX; 539 printf("(full-duplex, 10Mbps)\n"); 540 } else if (advert) { 541 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 542 media &= ~PHY_BMCR_SPEEDSEL; 543 media &= ~PHY_BMCR_DUPLEX; 544 printf("(half-duplex, 10Mbps)\n"); 545 } 546 media &= ~PHY_BMCR_AUTONEGENBL; 547 548 /* Set ASIC's duplex mode to match the PHY. */ 549 my_phy_writereg(sc, PHY_BMCR, media); 550 my_setcfg(sc, media); 551 } else { 552 if (verbose) 553 printf("my%d: no carrier\n", sc->my_unit); 554 } 555 556 my_init(sc); 557 if (sc->my_tx_pend) { 558 sc->my_autoneg = 0; 559 sc->my_tx_pend = 0; 560 my_start(ifp); 561 } 562 MY_UNLOCK(sc); 563 return; 564} 565 566/* 567 * To get PHY ability. 568 */ 569static void 570my_getmode_mii(struct my_softc * sc) 571{ 572 u_int16_t bmsr; 573 struct ifnet *ifp; 574 575 MY_LOCK(sc); 576 ifp = sc->my_ifp; 577 bmsr = my_phy_readreg(sc, PHY_BMSR); 578 if (bootverbose) 579 printf("my%d: PHY status word: %x\n", sc->my_unit, bmsr); 580 581 /* fallback */ 582 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 583 584 if (bmsr & PHY_BMSR_10BTHALF) { 585 if (bootverbose) 586 printf("my%d: 10Mbps half-duplex mode supported\n", 587 sc->my_unit); 588 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_HDX, 589 0, NULL); 590 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T, 0, NULL); 591 } 592 if (bmsr & PHY_BMSR_10BTFULL) { 593 if (bootverbose) 594 printf("my%d: 10Mbps full-duplex mode supported\n", 595 sc->my_unit); 596 597 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 598 0, NULL); 599 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX; 600 } 601 if (bmsr & PHY_BMSR_100BTXHALF) { 602 if (bootverbose) 603 printf("my%d: 100Mbps half-duplex mode supported\n", 604 sc->my_unit); 605 ifp->if_baudrate = 100000000; 606 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL); 607 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_HDX, 608 0, NULL); 609 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX; 610 } 611 if (bmsr & PHY_BMSR_100BTXFULL) { 612 if (bootverbose) 613 printf("my%d: 100Mbps full-duplex mode supported\n", 614 sc->my_unit); 615 ifp->if_baudrate = 100000000; 616 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 617 0, NULL); 618 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX; 619 } 620 /* Some also support 100BaseT4. */ 621 if (bmsr & PHY_BMSR_100BT4) { 622 if (bootverbose) 623 printf("my%d: 100baseT4 mode supported\n", sc->my_unit); 624 ifp->if_baudrate = 100000000; 625 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_T4, 0, NULL); 626 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_T4; 627#ifdef FORCE_AUTONEG_TFOUR 628 if (bootverbose) 629 printf("my%d: forcing on autoneg support for BT4\n", 630 sc->my_unit); 631 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0 NULL): 632 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO; 633#endif 634 } 635#if 0 /* this version did not support 1000M, */ 636 if (sc->my_pinfo->my_vid == MarvellPHYID0) { 637 if (bootverbose) 638 printf("my%d: 1000Mbps half-duplex mode supported\n", 639 sc->my_unit); 640 641 ifp->if_baudrate = 1000000000; 642 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL); 643 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_HDX, 644 0, NULL); 645 if (bootverbose) 646 printf("my%d: 1000Mbps full-duplex mode supported\n", 647 sc->my_unit); 648 ifp->if_baudrate = 1000000000; 649 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX, 650 0, NULL); 651 sc->ifmedia.ifm_media = IFM_ETHER | IFM_1000_T | IFM_FDX; 652 } 653#endif 654 if (bmsr & PHY_BMSR_CANAUTONEG) { 655 if (bootverbose) 656 printf("my%d: autoneg supported\n", sc->my_unit); 657 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 658 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO; 659 } 660 MY_UNLOCK(sc); 661 return; 662} 663 664/* 665 * Set speed and duplex mode. 666 */ 667static void 668my_setmode_mii(struct my_softc * sc, int media) 669{ 670 u_int16_t bmcr; 671 struct ifnet *ifp; 672 673 MY_LOCK(sc); 674 ifp = sc->my_ifp; 675 /* 676 * If an autoneg session is in progress, stop it. 677 */ 678 if (sc->my_autoneg) { 679 printf("my%d: canceling autoneg session\n", sc->my_unit); 680 ifp->if_timer = sc->my_autoneg = sc->my_want_auto = 0; 681 bmcr = my_phy_readreg(sc, PHY_BMCR); 682 bmcr &= ~PHY_BMCR_AUTONEGENBL; 683 my_phy_writereg(sc, PHY_BMCR, bmcr); 684 } 685 printf("my%d: selecting MII, ", sc->my_unit); 686 bmcr = my_phy_readreg(sc, PHY_BMCR); 687 bmcr &= ~(PHY_BMCR_AUTONEGENBL | PHY_BMCR_SPEEDSEL | PHY_BMCR_1000 | 688 PHY_BMCR_DUPLEX | PHY_BMCR_LOOPBK); 689 690#if 0 /* this version did not support 1000M, */ 691 if (IFM_SUBTYPE(media) == IFM_1000_T) { 692 printf("1000Mbps/T4, half-duplex\n"); 693 bmcr &= ~PHY_BMCR_SPEEDSEL; 694 bmcr &= ~PHY_BMCR_DUPLEX; 695 bmcr |= PHY_BMCR_1000; 696 } 697#endif 698 if (IFM_SUBTYPE(media) == IFM_100_T4) { 699 printf("100Mbps/T4, half-duplex\n"); 700 bmcr |= PHY_BMCR_SPEEDSEL; 701 bmcr &= ~PHY_BMCR_DUPLEX; 702 } 703 if (IFM_SUBTYPE(media) == IFM_100_TX) { 704 printf("100Mbps, "); 705 bmcr |= PHY_BMCR_SPEEDSEL; 706 } 707 if (IFM_SUBTYPE(media) == IFM_10_T) { 708 printf("10Mbps, "); 709 bmcr &= ~PHY_BMCR_SPEEDSEL; 710 } 711 if ((media & IFM_GMASK) == IFM_FDX) { 712 printf("full duplex\n"); 713 bmcr |= PHY_BMCR_DUPLEX; 714 } else { 715 printf("half duplex\n"); 716 bmcr &= ~PHY_BMCR_DUPLEX; 717 } 718 my_phy_writereg(sc, PHY_BMCR, bmcr); 719 my_setcfg(sc, bmcr); 720 MY_UNLOCK(sc); 721 return; 722} 723 724/* 725 * The Myson manual states that in order to fiddle with the 'full-duplex' and 726 * '100Mbps' bits in the netconfig register, we first have to put the 727 * transmit and/or receive logic in the idle state. 728 */ 729static void 730my_setcfg(struct my_softc * sc, int bmcr) 731{ 732 int i, restart = 0; 733 734 MY_LOCK(sc); 735 if (CSR_READ_4(sc, MY_TCRRCR) & (MY_TE | MY_RE)) { 736 restart = 1; 737 MY_CLRBIT(sc, MY_TCRRCR, (MY_TE | MY_RE)); 738 for (i = 0; i < MY_TIMEOUT; i++) { 739 DELAY(10); 740 if (!(CSR_READ_4(sc, MY_TCRRCR) & 741 (MY_TXRUN | MY_RXRUN))) 742 break; 743 } 744 if (i == MY_TIMEOUT) 745 printf("my%d: failed to force tx and rx to idle \n", 746 sc->my_unit); 747 } 748 MY_CLRBIT(sc, MY_TCRRCR, MY_PS1000); 749 MY_CLRBIT(sc, MY_TCRRCR, MY_PS10); 750 if (bmcr & PHY_BMCR_1000) 751 MY_SETBIT(sc, MY_TCRRCR, MY_PS1000); 752 else if (!(bmcr & PHY_BMCR_SPEEDSEL)) 753 MY_SETBIT(sc, MY_TCRRCR, MY_PS10); 754 if (bmcr & PHY_BMCR_DUPLEX) 755 MY_SETBIT(sc, MY_TCRRCR, MY_FD); 756 else 757 MY_CLRBIT(sc, MY_TCRRCR, MY_FD); 758 if (restart) 759 MY_SETBIT(sc, MY_TCRRCR, MY_TE | MY_RE); 760 MY_UNLOCK(sc); 761 return; 762} 763 764static void 765my_reset(struct my_softc * sc) 766{ 767 register int i; 768 769 MY_LOCK(sc); 770 MY_SETBIT(sc, MY_BCR, MY_SWR); 771 for (i = 0; i < MY_TIMEOUT; i++) { 772 DELAY(10); 773 if (!(CSR_READ_4(sc, MY_BCR) & MY_SWR)) 774 break; 775 } 776 if (i == MY_TIMEOUT) 777 printf("m0x%d: reset never completed!\n", sc->my_unit); 778 779 /* Wait a little while for the chip to get its brains in order. */ 780 DELAY(1000); 781 MY_UNLOCK(sc); 782 return; 783} 784 785/* 786 * Probe for a Myson chip. Check the PCI vendor and device IDs against our 787 * list and return a device name if we find a match. 788 */ 789static int 790my_probe(device_t dev) 791{ 792 struct my_type *t; 793 794 t = my_devs; 795 while (t->my_name != NULL) { 796 if ((pci_get_vendor(dev) == t->my_vid) && 797 (pci_get_device(dev) == t->my_did)) { 798 device_set_desc(dev, t->my_name); 799 my_info_tmp = t; 800 return (BUS_PROBE_DEFAULT); 801 } 802 t++; 803 } 804 return (ENXIO); 805} 806 807/* 808 * Attach the interface. Allocate softc structures, do ifmedia setup and 809 * ethernet/BPF attach. 810 */ 811static int 812my_attach(device_t dev) 813{ 814 int s, i; 815 u_char eaddr[ETHER_ADDR_LEN]; 816 u_int32_t command, iobase; 817 struct my_softc *sc; 818 struct ifnet *ifp; 819 int media = IFM_ETHER | IFM_100_TX | IFM_FDX; 820 unsigned int round; 821 caddr_t roundptr; 822 struct my_type *p; 823 u_int16_t phy_vid, phy_did, phy_sts = 0; 824 int rid, unit, error = 0; 825 826 s = splimp(); 827 sc = device_get_softc(dev); 828 unit = device_get_unit(dev); 829 bzero(sc, sizeof(struct my_softc)); 830 mtx_init(&sc->my_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 831 MTX_DEF | MTX_RECURSE); 832 MY_LOCK(sc); 833 834 /* 835 * Map control/status registers. 836 */ 837#if 0 838 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 839 command |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 840 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command & 0x000000ff, 4); 841 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 842#endif 843 command = pci_read_config(dev, PCIR_COMMAND, 4); 844 command |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 845 pci_write_config(dev, PCIR_COMMAND, command & 0x000000ff, 4); 846 command = pci_read_config(dev, PCIR_COMMAND, 4); 847 848 if (my_info_tmp->my_did == MTD800ID) { 849 iobase = pci_read_config(dev, MY_PCI_LOIO, 4); 850 if (iobase & 0x300) 851 MY_USEIOSPACE = 0; 852 } 853 if (MY_USEIOSPACE) { 854 if (!(command & PCIM_CMD_PORTEN)) { 855 printf("my%d: failed to enable I/O ports!\n", unit); 856 free(sc, M_DEVBUF); 857 error = ENXIO; 858 goto fail; 859 } 860#if 0 861 if (!pci_map_port(config_id, MY_PCI_LOIO, (u_int16_t *) & (sc->my_bhandle))) { 862 printf("my%d: couldn't map ports\n", unit); 863 error = ENXIO; 864 goto fail; 865 } 866 867 sc->my_btag = I386_BUS_SPACE_IO; 868#endif 869 } else { 870 if (!(command & PCIM_CMD_MEMEN)) { 871 printf("my%d: failed to enable memory mapping!\n", 872 unit); 873 error = ENXIO; 874 goto fail; 875 } 876#if 0 877 if (!pci_map_mem(config_id, MY_PCI_LOMEM, &vbase, &pbase)) { 878 printf ("my%d: couldn't map memory\n", unit); 879 error = ENXIO; 880 goto fail; 881 } 882 sc->my_btag = I386_BUS_SPACE_MEM; 883 sc->my_bhandle = vbase; 884#endif 885 } 886 887 rid = MY_RID; 888 sc->my_res = bus_alloc_resource_any(dev, MY_RES, &rid, RF_ACTIVE); 889 890 if (sc->my_res == NULL) { 891 printf("my%d: couldn't map ports/memory\n", unit); 892 error = ENXIO; 893 goto fail; 894 } 895 sc->my_btag = rman_get_bustag(sc->my_res); 896 sc->my_bhandle = rman_get_bushandle(sc->my_res); 897 898 rid = 0; 899 sc->my_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 900 RF_SHAREABLE | RF_ACTIVE); 901 902 if (sc->my_irq == NULL) { 903 printf("my%d: couldn't map interrupt\n", unit); 904 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res); 905 error = ENXIO; 906 goto fail; 907 } 908 error = bus_setup_intr(dev, sc->my_irq, INTR_TYPE_NET, 909 my_intr, sc, &sc->my_intrhand); 910 911 if (error) { 912 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq); 913 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res); 914 printf("my%d: couldn't set up irq\n", unit); 915 goto fail; 916 } 917 callout_handle_init(&sc->my_stat_ch); 918 919 sc->my_info = my_info_tmp; 920 921 /* Reset the adapter. */ 922 my_reset(sc); 923 924 /* 925 * Get station address 926 */ 927 for (i = 0; i < ETHER_ADDR_LEN; ++i) 928 eaddr[i] = CSR_READ_1(sc, MY_PAR0 + i); 929 930 sc->my_unit = unit; 931 932 sc->my_ldata_ptr = malloc(sizeof(struct my_list_data) + 8, 933 M_DEVBUF, M_NOWAIT); 934 if (sc->my_ldata_ptr == NULL) { 935 free(sc, M_DEVBUF); 936 printf("my%d: no memory for list buffers!\n", unit); 937 error = ENXIO; 938 goto fail; 939 } 940 sc->my_ldata = (struct my_list_data *) sc->my_ldata_ptr; 941 round = (uintptr_t)sc->my_ldata_ptr & 0xF; 942 roundptr = sc->my_ldata_ptr; 943 for (i = 0; i < 8; i++) { 944 if (round % 8) { 945 round++; 946 roundptr++; 947 } else 948 break; 949 } 950 sc->my_ldata = (struct my_list_data *) roundptr; 951 bzero(sc->my_ldata, sizeof(struct my_list_data)); 952 953 ifp = sc->my_ifp = if_alloc(IFT_ETHER); 954 if (ifp == NULL) { 955 device_printf(dev, "can not if_alloc()\n"); 956 error = ENOSPC; 957 goto fail; 958 } 959 ifp->if_softc = sc; 960 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 961 ifp->if_mtu = ETHERMTU; 962 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 963 ifp->if_ioctl = my_ioctl; 964 ifp->if_start = my_start; 965 ifp->if_watchdog = my_watchdog; 966 ifp->if_init = my_init; 967 ifp->if_baudrate = 10000000; 968 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 969 970 if (sc->my_info->my_did == MTD803ID) 971 sc->my_pinfo = my_phys; 972 else { 973 if (bootverbose) 974 printf("my%d: probing for a PHY\n", sc->my_unit); 975 for (i = MY_PHYADDR_MIN; i < MY_PHYADDR_MAX + 1; i++) { 976 if (bootverbose) 977 printf("my%d: checking address: %d\n", 978 sc->my_unit, i); 979 sc->my_phy_addr = i; 980 phy_sts = my_phy_readreg(sc, PHY_BMSR); 981 if ((phy_sts != 0) && (phy_sts != 0xffff)) 982 break; 983 else 984 phy_sts = 0; 985 } 986 if (phy_sts) { 987 phy_vid = my_phy_readreg(sc, PHY_VENID); 988 phy_did = my_phy_readreg(sc, PHY_DEVID); 989 if (bootverbose) { 990 printf("my%d: found PHY at address %d, ", 991 sc->my_unit, sc->my_phy_addr); 992 printf("vendor id: %x device id: %x\n", 993 phy_vid, phy_did); 994 } 995 p = my_phys; 996 while (p->my_vid) { 997 if (phy_vid == p->my_vid) { 998 sc->my_pinfo = p; 999 break; 1000 } 1001 p++; 1002 } 1003 if (sc->my_pinfo == NULL) 1004 sc->my_pinfo = &my_phys[PHY_UNKNOWN]; 1005 if (bootverbose) 1006 printf("my%d: PHY type: %s\n", 1007 sc->my_unit, sc->my_pinfo->my_name); 1008 } else { 1009 printf("my%d: MII without any phy!\n", sc->my_unit); 1010 error = ENXIO; 1011 goto fail; 1012 } 1013 } 1014 1015 /* Do ifmedia setup. */ 1016 ifmedia_init(&sc->ifmedia, 0, my_ifmedia_upd, my_ifmedia_sts); 1017 my_getmode_mii(sc); 1018 my_autoneg_mii(sc, MY_FLAG_FORCEDELAY, 1); 1019 media = sc->ifmedia.ifm_media; 1020 my_stop(sc); 1021 ifmedia_set(&sc->ifmedia, media); 1022 1023 ether_ifattach(ifp, eaddr); 1024 1025#if 0 1026 at_shutdown(my_shutdown, sc, SHUTDOWN_POST_SYNC); 1027 shutdownhook_establish(my_shutdown, sc); 1028#endif 1029 1030 MY_UNLOCK(sc); 1031 return (0); 1032 1033fail: 1034 MY_UNLOCK(sc); 1035 mtx_destroy(&sc->my_mtx); 1036 if (sc->my_ldata_ptr != NULL) 1037 free(sc->my_ldata_ptr, M_DEVBUF); 1038 splx(s); 1039 return (error); 1040} 1041 1042static int 1043my_detach(device_t dev) 1044{ 1045 struct my_softc *sc; 1046 struct ifnet *ifp; 1047 int s; 1048 1049 s = splimp(); 1050 sc = device_get_softc(dev); 1051 MY_LOCK(sc); 1052 ifp = sc->my_ifp; 1053 ether_ifdetach(ifp); 1054 if_free(ifp); 1055 my_stop(sc); 1056 1057#if 0 1058 bus_generic_detach(dev); 1059 device_delete_child(dev, sc->rl_miibus); 1060#endif 1061 1062 bus_teardown_intr(dev, sc->my_irq, sc->my_intrhand); 1063 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq); 1064 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res); 1065#if 0 1066 contigfree(sc->my_cdata.my_rx_buf, MY_RXBUFLEN + 32, M_DEVBUF); 1067#endif 1068 free(sc, M_DEVBUF); 1069 MY_UNLOCK(sc); 1070 splx(s); 1071 mtx_destroy(&sc->my_mtx); 1072 return (0); 1073} 1074 1075 1076/* 1077 * Initialize the transmit descriptors. 1078 */ 1079static int 1080my_list_tx_init(struct my_softc * sc) 1081{ 1082 struct my_chain_data *cd; 1083 struct my_list_data *ld; 1084 int i; 1085 1086 MY_LOCK(sc); 1087 cd = &sc->my_cdata; 1088 ld = sc->my_ldata; 1089 for (i = 0; i < MY_TX_LIST_CNT; i++) { 1090 cd->my_tx_chain[i].my_ptr = &ld->my_tx_list[i]; 1091 if (i == (MY_TX_LIST_CNT - 1)) 1092 cd->my_tx_chain[i].my_nextdesc = &cd->my_tx_chain[0]; 1093 else 1094 cd->my_tx_chain[i].my_nextdesc = 1095 &cd->my_tx_chain[i + 1]; 1096 } 1097 cd->my_tx_free = &cd->my_tx_chain[0]; 1098 cd->my_tx_tail = cd->my_tx_head = NULL; 1099 MY_UNLOCK(sc); 1100 return (0); 1101} 1102 1103/* 1104 * Initialize the RX descriptors and allocate mbufs for them. Note that we 1105 * arrange the descriptors in a closed ring, so that the last descriptor 1106 * points back to the first. 1107 */ 1108static int 1109my_list_rx_init(struct my_softc * sc) 1110{ 1111 struct my_chain_data *cd; 1112 struct my_list_data *ld; 1113 int i; 1114 1115 MY_LOCK(sc); 1116 cd = &sc->my_cdata; 1117 ld = sc->my_ldata; 1118 for (i = 0; i < MY_RX_LIST_CNT; i++) { 1119 cd->my_rx_chain[i].my_ptr = 1120 (struct my_desc *) & ld->my_rx_list[i]; 1121 if (my_newbuf(sc, &cd->my_rx_chain[i]) == ENOBUFS) { 1122 MY_UNLOCK(sc); 1123 return (ENOBUFS); 1124 } 1125 if (i == (MY_RX_LIST_CNT - 1)) { 1126 cd->my_rx_chain[i].my_nextdesc = &cd->my_rx_chain[0]; 1127 ld->my_rx_list[i].my_next = vtophys(&ld->my_rx_list[0]); 1128 } else { 1129 cd->my_rx_chain[i].my_nextdesc = 1130 &cd->my_rx_chain[i + 1]; 1131 ld->my_rx_list[i].my_next = 1132 vtophys(&ld->my_rx_list[i + 1]); 1133 } 1134 } 1135 cd->my_rx_head = &cd->my_rx_chain[0]; 1136 MY_UNLOCK(sc); 1137 return (0); 1138} 1139 1140/* 1141 * Initialize an RX descriptor and attach an MBUF cluster. 1142 */ 1143static int 1144my_newbuf(struct my_softc * sc, struct my_chain_onefrag * c) 1145{ 1146 struct mbuf *m_new = NULL; 1147 1148 MY_LOCK(sc); 1149 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1150 if (m_new == NULL) { 1151 printf("my%d: no memory for rx list -- packet dropped!\n", 1152 sc->my_unit); 1153 MY_UNLOCK(sc); 1154 return (ENOBUFS); 1155 } 1156 MCLGET(m_new, M_DONTWAIT); 1157 if (!(m_new->m_flags & M_EXT)) { 1158 printf("my%d: no memory for rx list -- packet dropped!\n", 1159 sc->my_unit); 1160 m_freem(m_new); 1161 MY_UNLOCK(sc); 1162 return (ENOBUFS); 1163 } 1164 c->my_mbuf = m_new; 1165 c->my_ptr->my_data = vtophys(mtod(m_new, caddr_t)); 1166 c->my_ptr->my_ctl = (MCLBYTES - 1) << MY_RBSShift; 1167 c->my_ptr->my_status = MY_OWNByNIC; 1168 MY_UNLOCK(sc); 1169 return (0); 1170} 1171 1172/* 1173 * A frame has been uploaded: pass the resulting mbuf chain up to the higher 1174 * level protocols. 1175 */ 1176static void 1177my_rxeof(struct my_softc * sc) 1178{ 1179 struct ether_header *eh; 1180 struct mbuf *m; 1181 struct ifnet *ifp; 1182 struct my_chain_onefrag *cur_rx; 1183 int total_len = 0; 1184 u_int32_t rxstat; 1185 1186 MY_LOCK(sc); 1187 ifp = sc->my_ifp; 1188 while (!((rxstat = sc->my_cdata.my_rx_head->my_ptr->my_status) 1189 & MY_OWNByNIC)) { 1190 cur_rx = sc->my_cdata.my_rx_head; 1191 sc->my_cdata.my_rx_head = cur_rx->my_nextdesc; 1192 1193 if (rxstat & MY_ES) { /* error summary: give up this rx pkt */ 1194 ifp->if_ierrors++; 1195 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1196 continue; 1197 } 1198 /* No errors; receive the packet. */ 1199 total_len = (rxstat & MY_FLNGMASK) >> MY_FLNGShift; 1200 total_len -= ETHER_CRC_LEN; 1201 1202 if (total_len < MINCLSIZE) { 1203 m = m_devget(mtod(cur_rx->my_mbuf, char *), 1204 total_len, 0, ifp, NULL); 1205 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1206 if (m == NULL) { 1207 ifp->if_ierrors++; 1208 continue; 1209 } 1210 } else { 1211 m = cur_rx->my_mbuf; 1212 /* 1213 * Try to conjure up a new mbuf cluster. If that 1214 * fails, it means we have an out of memory condition 1215 * and should leave the buffer in place and continue. 1216 * This will result in a lost packet, but there's 1217 * little else we can do in this situation. 1218 */ 1219 if (my_newbuf(sc, cur_rx) == ENOBUFS) { 1220 ifp->if_ierrors++; 1221 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1222 continue; 1223 } 1224 m->m_pkthdr.rcvif = ifp; 1225 m->m_pkthdr.len = m->m_len = total_len; 1226 } 1227 ifp->if_ipackets++; 1228 eh = mtod(m, struct ether_header *); 1229#if NBPFILTER > 0 1230 /* 1231 * Handle BPF listeners. Let the BPF user see the packet, but 1232 * don't pass it up to the ether_input() layer unless it's a 1233 * broadcast packet, multicast packet, matches our ethernet 1234 * address or the interface is in promiscuous mode. 1235 */ 1236 if (ifp->if_bpf) { 1237 BPF_MTAP(ifp, m); 1238 if (ifp->if_flags & IFF_PROMISC && 1239 (bcmp(eh->ether_dhost, IFP2ENADDR(sc->my_ifp), 1240 ETHER_ADDR_LEN) && 1241 (eh->ether_dhost[0] & 1) == 0)) { 1242 m_freem(m); 1243 continue; 1244 } 1245 } 1246#endif 1247 MY_UNLOCK(sc); 1248 (*ifp->if_input)(ifp, m); 1249 MY_LOCK(sc); 1250 } 1251 MY_UNLOCK(sc); 1252 return; 1253} 1254 1255 1256/* 1257 * A frame was downloaded to the chip. It's safe for us to clean up the list 1258 * buffers. 1259 */ 1260static void 1261my_txeof(struct my_softc * sc) 1262{ 1263 struct my_chain *cur_tx; 1264 struct ifnet *ifp; 1265 1266 MY_LOCK(sc); 1267 ifp = sc->my_ifp; 1268 /* Clear the timeout timer. */ 1269 ifp->if_timer = 0; 1270 if (sc->my_cdata.my_tx_head == NULL) { 1271 MY_UNLOCK(sc); 1272 return; 1273 } 1274 /* 1275 * Go through our tx list and free mbufs for those frames that have 1276 * been transmitted. 1277 */ 1278 while (sc->my_cdata.my_tx_head->my_mbuf != NULL) { 1279 u_int32_t txstat; 1280 1281 cur_tx = sc->my_cdata.my_tx_head; 1282 txstat = MY_TXSTATUS(cur_tx); 1283 if ((txstat & MY_OWNByNIC) || txstat == MY_UNSENT) 1284 break; 1285 if (!(CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced)) { 1286 if (txstat & MY_TXERR) { 1287 ifp->if_oerrors++; 1288 if (txstat & MY_EC) /* excessive collision */ 1289 ifp->if_collisions++; 1290 if (txstat & MY_LC) /* late collision */ 1291 ifp->if_collisions++; 1292 } 1293 ifp->if_collisions += (txstat & MY_NCRMASK) >> 1294 MY_NCRShift; 1295 } 1296 ifp->if_opackets++; 1297 m_freem(cur_tx->my_mbuf); 1298 cur_tx->my_mbuf = NULL; 1299 if (sc->my_cdata.my_tx_head == sc->my_cdata.my_tx_tail) { 1300 sc->my_cdata.my_tx_head = NULL; 1301 sc->my_cdata.my_tx_tail = NULL; 1302 break; 1303 } 1304 sc->my_cdata.my_tx_head = cur_tx->my_nextdesc; 1305 } 1306 if (CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced) { 1307 ifp->if_collisions += (CSR_READ_4(sc, MY_TSR) & MY_NCRMask); 1308 } 1309 MY_UNLOCK(sc); 1310 return; 1311} 1312 1313/* 1314 * TX 'end of channel' interrupt handler. 1315 */ 1316static void 1317my_txeoc(struct my_softc * sc) 1318{ 1319 struct ifnet *ifp; 1320 1321 MY_LOCK(sc); 1322 ifp = sc->my_ifp; 1323 ifp->if_timer = 0; 1324 if (sc->my_cdata.my_tx_head == NULL) { 1325 ifp->if_flags &= ~IFF_OACTIVE; 1326 sc->my_cdata.my_tx_tail = NULL; 1327 if (sc->my_want_auto) 1328 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1); 1329 } else { 1330 if (MY_TXOWN(sc->my_cdata.my_tx_head) == MY_UNSENT) { 1331 MY_TXOWN(sc->my_cdata.my_tx_head) = MY_OWNByNIC; 1332 ifp->if_timer = 5; 1333 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); 1334 } 1335 } 1336 MY_UNLOCK(sc); 1337 return; 1338} 1339 1340static void 1341my_intr(void *arg) 1342{ 1343 struct my_softc *sc; 1344 struct ifnet *ifp; 1345 u_int32_t status; 1346 1347 sc = arg; 1348 MY_LOCK(sc); 1349 ifp = sc->my_ifp; 1350 if (!(ifp->if_flags & IFF_UP)) { 1351 MY_UNLOCK(sc); 1352 return; 1353 } 1354 /* Disable interrupts. */ 1355 CSR_WRITE_4(sc, MY_IMR, 0x00000000); 1356 1357 for (;;) { 1358 status = CSR_READ_4(sc, MY_ISR); 1359 status &= MY_INTRS; 1360 if (status) 1361 CSR_WRITE_4(sc, MY_ISR, status); 1362 else 1363 break; 1364 1365 if (status & MY_RI) /* receive interrupt */ 1366 my_rxeof(sc); 1367 1368 if ((status & MY_RBU) || (status & MY_RxErr)) { 1369 /* rx buffer unavailable or rx error */ 1370 ifp->if_ierrors++; 1371#ifdef foo 1372 my_stop(sc); 1373 my_reset(sc); 1374 my_init(sc); 1375#endif 1376 } 1377 if (status & MY_TI) /* tx interrupt */ 1378 my_txeof(sc); 1379 if (status & MY_ETI) /* tx early interrupt */ 1380 my_txeof(sc); 1381 if (status & MY_TBU) /* tx buffer unavailable */ 1382 my_txeoc(sc); 1383 1384#if 0 /* 90/1/18 delete */ 1385 if (status & MY_FBE) { 1386 my_reset(sc); 1387 my_init(sc); 1388 } 1389#endif 1390 1391 } 1392 1393 /* Re-enable interrupts. */ 1394 CSR_WRITE_4(sc, MY_IMR, MY_INTRS); 1395 if (ifp->if_snd.ifq_head != NULL) 1396 my_start(ifp); 1397 MY_UNLOCK(sc); 1398 return; 1399} 1400 1401/* 1402 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1403 * pointers to the fragment pointers. 1404 */ 1405static int 1406my_encap(struct my_softc * sc, struct my_chain * c, struct mbuf * m_head) 1407{ 1408 struct my_desc *f = NULL; 1409 int total_len; 1410 struct mbuf *m, *m_new = NULL; 1411 1412 MY_LOCK(sc); 1413 /* calculate the total tx pkt length */ 1414 total_len = 0; 1415 for (m = m_head; m != NULL; m = m->m_next) 1416 total_len += m->m_len; 1417 /* 1418 * Start packing the mbufs in this chain into the fragment pointers. 1419 * Stop when we run out of fragments or hit the end of the mbuf 1420 * chain. 1421 */ 1422 m = m_head; 1423 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1424 if (m_new == NULL) { 1425 printf("my%d: no memory for tx list", sc->my_unit); 1426 MY_UNLOCK(sc); 1427 return (1); 1428 } 1429 if (m_head->m_pkthdr.len > MHLEN) { 1430 MCLGET(m_new, M_DONTWAIT); 1431 if (!(m_new->m_flags & M_EXT)) { 1432 m_freem(m_new); 1433 printf("my%d: no memory for tx list", sc->my_unit); 1434 MY_UNLOCK(sc); 1435 return (1); 1436 } 1437 } 1438 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t)); 1439 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1440 m_freem(m_head); 1441 m_head = m_new; 1442 f = &c->my_ptr->my_frag[0]; 1443 f->my_status = 0; 1444 f->my_data = vtophys(mtod(m_new, caddr_t)); 1445 total_len = m_new->m_len; 1446 f->my_ctl = MY_TXFD | MY_TXLD | MY_CRCEnable | MY_PADEnable; 1447 f->my_ctl |= total_len << MY_PKTShift; /* pkt size */ 1448 f->my_ctl |= total_len; /* buffer size */ 1449 /* 89/12/29 add, for mtd891 *//* [ 89? ] */ 1450 if (sc->my_info->my_did == MTD891ID) 1451 f->my_ctl |= MY_ETIControl | MY_RetryTxLC; 1452 c->my_mbuf = m_head; 1453 c->my_lastdesc = 0; 1454 MY_TXNEXT(c) = vtophys(&c->my_nextdesc->my_ptr->my_frag[0]); 1455 MY_UNLOCK(sc); 1456 return (0); 1457} 1458 1459/* 1460 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1461 * to the mbuf data regions directly in the transmit lists. We also save a 1462 * copy of the pointers since the transmit list fragment pointers are 1463 * physical addresses. 1464 */ 1465static void 1466my_start(struct ifnet * ifp) 1467{ 1468 struct my_softc *sc; 1469 struct mbuf *m_head = NULL; 1470 struct my_chain *cur_tx = NULL, *start_tx; 1471 1472 sc = ifp->if_softc; 1473 MY_LOCK(sc); 1474 if (sc->my_autoneg) { 1475 sc->my_tx_pend = 1; 1476 MY_UNLOCK(sc); 1477 return; 1478 } 1479 /* 1480 * Check for an available queue slot. If there are none, punt. 1481 */ 1482 if (sc->my_cdata.my_tx_free->my_mbuf != NULL) { 1483 ifp->if_flags |= IFF_OACTIVE; 1484 MY_UNLOCK(sc); 1485 return; 1486 } 1487 start_tx = sc->my_cdata.my_tx_free; 1488 while (sc->my_cdata.my_tx_free->my_mbuf == NULL) { 1489 IF_DEQUEUE(&ifp->if_snd, m_head); 1490 if (m_head == NULL) 1491 break; 1492 1493 /* Pick a descriptor off the free list. */ 1494 cur_tx = sc->my_cdata.my_tx_free; 1495 sc->my_cdata.my_tx_free = cur_tx->my_nextdesc; 1496 1497 /* Pack the data into the descriptor. */ 1498 my_encap(sc, cur_tx, m_head); 1499 1500 if (cur_tx != start_tx) 1501 MY_TXOWN(cur_tx) = MY_OWNByNIC; 1502#if NBPFILTER > 0 1503 /* 1504 * If there's a BPF listener, bounce a copy of this frame to 1505 * him. 1506 */ 1507 BPF_MTAP(ifp, cur_tx->my_mbuf); 1508#endif 1509 } 1510 /* 1511 * If there are no packets queued, bail. 1512 */ 1513 if (cur_tx == NULL) { 1514 MY_UNLOCK(sc); 1515 return; 1516 } 1517 /* 1518 * Place the request for the upload interrupt in the last descriptor 1519 * in the chain. This way, if we're chaining several packets at once, 1520 * we'll only get an interupt once for the whole chain rather than 1521 * once for each packet. 1522 */ 1523 MY_TXCTL(cur_tx) |= MY_TXIC; 1524 cur_tx->my_ptr->my_frag[0].my_ctl |= MY_TXIC; 1525 sc->my_cdata.my_tx_tail = cur_tx; 1526 if (sc->my_cdata.my_tx_head == NULL) 1527 sc->my_cdata.my_tx_head = start_tx; 1528 MY_TXOWN(start_tx) = MY_OWNByNIC; 1529 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); /* tx polling demand */ 1530 1531 /* 1532 * Set a timeout in case the chip goes out to lunch. 1533 */ 1534 ifp->if_timer = 5; 1535 MY_UNLOCK(sc); 1536 return; 1537} 1538 1539static void 1540my_init(void *xsc) 1541{ 1542 struct my_softc *sc = xsc; 1543 struct ifnet *ifp = sc->my_ifp; 1544 int s; 1545 u_int16_t phy_bmcr = 0; 1546 1547 MY_LOCK(sc); 1548 if (sc->my_autoneg) { 1549 MY_UNLOCK(sc); 1550 return; 1551 } 1552 s = splimp(); 1553 if (sc->my_pinfo != NULL) 1554 phy_bmcr = my_phy_readreg(sc, PHY_BMCR); 1555 /* 1556 * Cancel pending I/O and free all RX/TX buffers. 1557 */ 1558 my_stop(sc); 1559 my_reset(sc); 1560 1561 /* 1562 * Set cache alignment and burst length. 1563 */ 1564#if 0 /* 89/9/1 modify, */ 1565 CSR_WRITE_4(sc, MY_BCR, MY_RPBLE512); 1566 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF); 1567#endif 1568 CSR_WRITE_4(sc, MY_BCR, MY_PBL8); 1569 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF | MY_RBLEN | MY_RPBLE512); 1570 /* 1571 * 89/12/29 add, for mtd891, 1572 */ 1573 if (sc->my_info->my_did == MTD891ID) { 1574 MY_SETBIT(sc, MY_BCR, MY_PROG); 1575 MY_SETBIT(sc, MY_TCRRCR, MY_Enhanced); 1576 } 1577 my_setcfg(sc, phy_bmcr); 1578 /* Init circular RX list. */ 1579 if (my_list_rx_init(sc) == ENOBUFS) { 1580 printf("my%d: init failed: no memory for rx buffers\n", 1581 sc->my_unit); 1582 my_stop(sc); 1583 (void)splx(s); 1584 MY_UNLOCK(sc); 1585 return; 1586 } 1587 /* Init TX descriptors. */ 1588 my_list_tx_init(sc); 1589 1590 /* If we want promiscuous mode, set the allframes bit. */ 1591 if (ifp->if_flags & IFF_PROMISC) 1592 MY_SETBIT(sc, MY_TCRRCR, MY_PROM); 1593 else 1594 MY_CLRBIT(sc, MY_TCRRCR, MY_PROM); 1595 1596 /* 1597 * Set capture broadcast bit to capture broadcast frames. 1598 */ 1599 if (ifp->if_flags & IFF_BROADCAST) 1600 MY_SETBIT(sc, MY_TCRRCR, MY_AB); 1601 else 1602 MY_CLRBIT(sc, MY_TCRRCR, MY_AB); 1603 1604 /* 1605 * Program the multicast filter, if necessary. 1606 */ 1607 my_setmulti(sc); 1608 1609 /* 1610 * Load the address of the RX list. 1611 */ 1612 MY_CLRBIT(sc, MY_TCRRCR, MY_RE); 1613 CSR_WRITE_4(sc, MY_RXLBA, vtophys(&sc->my_ldata->my_rx_list[0])); 1614 1615 /* 1616 * Enable interrupts. 1617 */ 1618 CSR_WRITE_4(sc, MY_IMR, MY_INTRS); 1619 CSR_WRITE_4(sc, MY_ISR, 0xFFFFFFFF); 1620 1621 /* Enable receiver and transmitter. */ 1622 MY_SETBIT(sc, MY_TCRRCR, MY_RE); 1623 MY_CLRBIT(sc, MY_TCRRCR, MY_TE); 1624 CSR_WRITE_4(sc, MY_TXLBA, vtophys(&sc->my_ldata->my_tx_list[0])); 1625 MY_SETBIT(sc, MY_TCRRCR, MY_TE); 1626 1627 /* Restore state of BMCR */ 1628 if (sc->my_pinfo != NULL) 1629 my_phy_writereg(sc, PHY_BMCR, phy_bmcr); 1630 ifp->if_flags |= IFF_RUNNING; 1631 ifp->if_flags &= ~IFF_OACTIVE; 1632 (void)splx(s); 1633 MY_UNLOCK(sc); 1634 return; 1635} 1636 1637/* 1638 * Set media options. 1639 */ 1640 1641static int 1642my_ifmedia_upd(struct ifnet * ifp) 1643{ 1644 struct my_softc *sc; 1645 struct ifmedia *ifm; 1646 1647 sc = ifp->if_softc; 1648 MY_LOCK(sc); 1649 ifm = &sc->ifmedia; 1650 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) { 1651 MY_UNLOCK(sc); 1652 return (EINVAL); 1653 } 1654 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) 1655 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1); 1656 else 1657 my_setmode_mii(sc, ifm->ifm_media); 1658 MY_UNLOCK(sc); 1659 return (0); 1660} 1661 1662/* 1663 * Report current media status. 1664 */ 1665 1666static void 1667my_ifmedia_sts(struct ifnet * ifp, struct ifmediareq * ifmr) 1668{ 1669 struct my_softc *sc; 1670 u_int16_t advert = 0, ability = 0; 1671 1672 sc = ifp->if_softc; 1673 MY_LOCK(sc); 1674 ifmr->ifm_active = IFM_ETHER; 1675 if (!(my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) { 1676#if 0 /* this version did not support 1000M, */ 1677 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_1000) 1678 ifmr->ifm_active = IFM_ETHER | IFM_1000TX; 1679#endif 1680 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL) 1681 ifmr->ifm_active = IFM_ETHER | IFM_100_TX; 1682 else 1683 ifmr->ifm_active = IFM_ETHER | IFM_10_T; 1684 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX) 1685 ifmr->ifm_active |= IFM_FDX; 1686 else 1687 ifmr->ifm_active |= IFM_HDX; 1688 1689 MY_UNLOCK(sc); 1690 return; 1691 } 1692 ability = my_phy_readreg(sc, PHY_LPAR); 1693 advert = my_phy_readreg(sc, PHY_ANAR); 1694 1695#if 0 /* this version did not support 1000M, */ 1696 if (sc->my_pinfo->my_vid = MarvellPHYID0) { 1697 ability2 = my_phy_readreg(sc, PHY_1000SR); 1698 if (ability2 & PHY_1000SR_1000BTXFULL) { 1699 advert = 0; 1700 ability = 0; 1701 ifmr->ifm_active = IFM_ETHER|IFM_1000_T|IFM_FDX; 1702 } else if (ability & PHY_1000SR_1000BTXHALF) { 1703 advert = 0; 1704 ability = 0; 1705 ifmr->ifm_active = IFM_ETHER|IFM_1000_T|IFM_HDX; 1706 } 1707 } 1708#endif 1709 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) 1710 ifmr->ifm_active = IFM_ETHER | IFM_100_T4; 1711 else if (advert & PHY_ANAR_100BTXFULL && ability & PHY_ANAR_100BTXFULL) 1712 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1713 else if (advert & PHY_ANAR_100BTXHALF && ability & PHY_ANAR_100BTXHALF) 1714 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_HDX; 1715 else if (advert & PHY_ANAR_10BTFULL && ability & PHY_ANAR_10BTFULL) 1716 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_FDX; 1717 else if (advert & PHY_ANAR_10BTHALF && ability & PHY_ANAR_10BTHALF) 1718 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_HDX; 1719 MY_UNLOCK(sc); 1720 return; 1721} 1722 1723static int 1724my_ioctl(struct ifnet * ifp, u_long command, caddr_t data) 1725{ 1726 struct my_softc *sc = ifp->if_softc; 1727 struct ifreq *ifr = (struct ifreq *) data; 1728 int s, error = 0; 1729 1730 s = splimp(); 1731 MY_LOCK(sc); 1732 switch (command) { 1733 case SIOCSIFFLAGS: 1734 if (ifp->if_flags & IFF_UP) 1735 my_init(sc); 1736 else if (ifp->if_flags & IFF_RUNNING) 1737 my_stop(sc); 1738 error = 0; 1739 break; 1740 case SIOCADDMULTI: 1741 case SIOCDELMULTI: 1742 my_setmulti(sc); 1743 error = 0; 1744 break; 1745 case SIOCGIFMEDIA: 1746 case SIOCSIFMEDIA: 1747 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 1748 break; 1749 default: 1750 error = ether_ioctl(ifp, command, data); 1751 break; 1752 } 1753 MY_UNLOCK(sc); 1754 (void)splx(s); 1755 return (error); 1756} 1757 1758static void 1759my_watchdog(struct ifnet * ifp) 1760{ 1761 struct my_softc *sc; 1762 1763 sc = ifp->if_softc; 1764 MY_LOCK(sc); 1765 if (sc->my_autoneg) { 1766 my_autoneg_mii(sc, MY_FLAG_DELAYTIMEO, 1); 1767 MY_UNLOCK(sc); 1768 return; 1769 } 1770 ifp->if_oerrors++; 1771 printf("my%d: watchdog timeout\n", sc->my_unit); 1772 if (!(my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1773 printf("my%d: no carrier - transceiver cable problem?\n", 1774 sc->my_unit); 1775 my_stop(sc); 1776 my_reset(sc); 1777 my_init(sc); 1778 if (ifp->if_snd.ifq_head != NULL) 1779 my_start(ifp); 1780 MY_LOCK(sc); 1781 return; 1782} 1783 1784 1785/* 1786 * Stop the adapter and free any mbufs allocated to the RX and TX lists. 1787 */ 1788static void 1789my_stop(struct my_softc * sc) 1790{ 1791 register int i; 1792 struct ifnet *ifp; 1793 1794 MY_LOCK(sc); 1795 ifp = sc->my_ifp; 1796 ifp->if_timer = 0; 1797 1798 MY_CLRBIT(sc, MY_TCRRCR, (MY_RE | MY_TE)); 1799 CSR_WRITE_4(sc, MY_IMR, 0x00000000); 1800 CSR_WRITE_4(sc, MY_TXLBA, 0x00000000); 1801 CSR_WRITE_4(sc, MY_RXLBA, 0x00000000); 1802 1803 /* 1804 * Free data in the RX lists. 1805 */ 1806 for (i = 0; i < MY_RX_LIST_CNT; i++) { 1807 if (sc->my_cdata.my_rx_chain[i].my_mbuf != NULL) { 1808 m_freem(sc->my_cdata.my_rx_chain[i].my_mbuf); 1809 sc->my_cdata.my_rx_chain[i].my_mbuf = NULL; 1810 } 1811 } 1812 bzero((char *)&sc->my_ldata->my_rx_list, 1813 sizeof(sc->my_ldata->my_rx_list)); 1814 /* 1815 * Free the TX list buffers. 1816 */ 1817 for (i = 0; i < MY_TX_LIST_CNT; i++) { 1818 if (sc->my_cdata.my_tx_chain[i].my_mbuf != NULL) { 1819 m_freem(sc->my_cdata.my_tx_chain[i].my_mbuf); 1820 sc->my_cdata.my_tx_chain[i].my_mbuf = NULL; 1821 } 1822 } 1823 bzero((char *)&sc->my_ldata->my_tx_list, 1824 sizeof(sc->my_ldata->my_tx_list)); 1825 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1826 MY_UNLOCK(sc); 1827 return; 1828} 1829 1830/* 1831 * Stop all chip I/O so that the kernel's probe routines don't get confused 1832 * by errant DMAs when rebooting. 1833 */ 1834static void 1835my_shutdown(device_t dev) 1836{ 1837 struct my_softc *sc; 1838 1839 sc = device_get_softc(dev); 1840 my_stop(sc); 1841 return; 1842} 1843