if_my.c revision 143158
1/*- 2 * Written by: yen_cw@myson.com.tw 3 * Copyright (c) 2002 Myson Technology Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer, 11 * without modification, immediately at the beginning of the file. 12 * 2. The name of the author may not be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 19 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * Myson fast ethernet PCI NIC driver, available at: http://www.myson.com.tw/ 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/my/if_my.c 143158 2005-03-05 18:10:49Z imp $"); 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/sockio.h> 36#include <sys/mbuf.h> 37#include <sys/malloc.h> 38#include <sys/kernel.h> 39#include <sys/socket.h> 40#include <sys/queue.h> 41#include <sys/types.h> 42#include <sys/bus.h> 43#include <sys/module.h> 44#include <sys/lock.h> 45#include <sys/mutex.h> 46 47#define NBPFILTER 1 48 49#include <net/if.h> 50#include <net/if_arp.h> 51#include <net/ethernet.h> 52#include <net/if_media.h> 53#include <net/if_dl.h> 54#include <net/bpf.h> 55 56#include <vm/vm.h> /* for vtophys */ 57#include <vm/pmap.h> /* for vtophys */ 58#include <machine/clock.h> /* for DELAY */ 59#include <machine/bus_memio.h> 60#include <machine/bus_pio.h> 61#include <machine/bus.h> 62#include <machine/resource.h> 63#include <sys/bus.h> 64#include <sys/rman.h> 65 66#include <dev/pci/pcireg.h> 67#include <dev/pci/pcivar.h> 68 69#include <dev/mii/mii.h> 70#include <dev/mii/miivar.h> 71 72#include "miibus_if.h" 73 74/* 75 * #define MY_USEIOSPACE 76 */ 77 78static int MY_USEIOSPACE = 1; 79 80#if (MY_USEIOSPACE) 81#define MY_RES SYS_RES_IOPORT 82#define MY_RID MY_PCI_LOIO 83#else 84#define MY_RES SYS_RES_MEMORY 85#define MY_RID MY_PCI_LOMEM 86#endif 87 88 89#include <dev/my/if_myreg.h> 90 91#ifndef lint 92static const char rcsid[] = 93"$Id: if_my.c,v 1.16 2003/04/15 06:37:25 mdodd Exp $"; 94#endif 95 96/* 97 * Various supported device vendors/types and their names. 98 */ 99struct my_type *my_info_tmp; 100static struct my_type my_devs[] = { 101 {MYSONVENDORID, MTD800ID, "Myson MTD80X Based Fast Ethernet Card"}, 102 {MYSONVENDORID, MTD803ID, "Myson MTD80X Based Fast Ethernet Card"}, 103 {MYSONVENDORID, MTD891ID, "Myson MTD89X Based Giga Ethernet Card"}, 104 {0, 0, NULL} 105}; 106 107/* 108 * Various supported PHY vendors/types and their names. Note that this driver 109 * will work with pretty much any MII-compliant PHY, so failure to positively 110 * identify the chip is not a fatal error. 111 */ 112static struct my_type my_phys[] = { 113 {MysonPHYID0, MysonPHYID0, "<MYSON MTD981>"}, 114 {SeeqPHYID0, SeeqPHYID0, "<SEEQ 80225>"}, 115 {AhdocPHYID0, AhdocPHYID0, "<AHDOC 101>"}, 116 {MarvellPHYID0, MarvellPHYID0, "<MARVELL 88E1000>"}, 117 {LevelOnePHYID0, LevelOnePHYID0, "<LevelOne LXT1000>"}, 118 {0, 0, "<MII-compliant physical interface>"} 119}; 120 121static int my_probe(device_t); 122static int my_attach(device_t); 123static int my_detach(device_t); 124static int my_newbuf(struct my_softc *, struct my_chain_onefrag *); 125static int my_encap(struct my_softc *, struct my_chain *, struct mbuf *); 126static void my_rxeof(struct my_softc *); 127static void my_txeof(struct my_softc *); 128static void my_txeoc(struct my_softc *); 129static void my_intr(void *); 130static void my_start(struct ifnet *); 131static int my_ioctl(struct ifnet *, u_long, caddr_t); 132static void my_init(void *); 133static void my_stop(struct my_softc *); 134static void my_watchdog(struct ifnet *); 135static void my_shutdown(device_t); 136static int my_ifmedia_upd(struct ifnet *); 137static void my_ifmedia_sts(struct ifnet *, struct ifmediareq *); 138static u_int16_t my_phy_readreg(struct my_softc *, int); 139static void my_phy_writereg(struct my_softc *, int, int); 140static void my_autoneg_xmit(struct my_softc *); 141static void my_autoneg_mii(struct my_softc *, int, int); 142static void my_setmode_mii(struct my_softc *, int); 143static void my_getmode_mii(struct my_softc *); 144static void my_setcfg(struct my_softc *, int); 145static void my_setmulti(struct my_softc *); 146static void my_reset(struct my_softc *); 147static int my_list_rx_init(struct my_softc *); 148static int my_list_tx_init(struct my_softc *); 149static long my_send_cmd_to_phy(struct my_softc *, int, int); 150 151#define MY_SETBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 152#define MY_CLRBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 153 154static device_method_t my_methods[] = { 155 /* Device interface */ 156 DEVMETHOD(device_probe, my_probe), 157 DEVMETHOD(device_attach, my_attach), 158 DEVMETHOD(device_detach, my_detach), 159 DEVMETHOD(device_shutdown, my_shutdown), 160 161 {0, 0} 162}; 163 164static driver_t my_driver = { 165 "my", 166 my_methods, 167 sizeof(struct my_softc) 168}; 169 170static devclass_t my_devclass; 171 172DRIVER_MODULE(my, pci, my_driver, my_devclass, 0, 0); 173MODULE_DEPEND(my, pci, 1, 1, 1); 174MODULE_DEPEND(my, ether, 1, 1, 1); 175 176static long 177my_send_cmd_to_phy(struct my_softc * sc, int opcode, int regad) 178{ 179 long miir; 180 int i; 181 int mask, data; 182 183 MY_LOCK(sc); 184 185 /* enable MII output */ 186 miir = CSR_READ_4(sc, MY_MANAGEMENT); 187 miir &= 0xfffffff0; 188 189 miir |= MY_MASK_MIIR_MII_WRITE + MY_MASK_MIIR_MII_MDO; 190 191 /* send 32 1's preamble */ 192 for (i = 0; i < 32; i++) { 193 /* low MDC; MDO is already high (miir) */ 194 miir &= ~MY_MASK_MIIR_MII_MDC; 195 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 196 197 /* high MDC */ 198 miir |= MY_MASK_MIIR_MII_MDC; 199 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 200 } 201 202 /* calculate ST+OP+PHYAD+REGAD+TA */ 203 data = opcode | (sc->my_phy_addr << 7) | (regad << 2); 204 205 /* sent out */ 206 mask = 0x8000; 207 while (mask) { 208 /* low MDC, prepare MDO */ 209 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO); 210 if (mask & data) 211 miir |= MY_MASK_MIIR_MII_MDO; 212 213 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 214 /* high MDC */ 215 miir |= MY_MASK_MIIR_MII_MDC; 216 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 217 DELAY(30); 218 219 /* next */ 220 mask >>= 1; 221 if (mask == 0x2 && opcode == MY_OP_READ) 222 miir &= ~MY_MASK_MIIR_MII_WRITE; 223 } 224 225 MY_UNLOCK(sc); 226 return miir; 227} 228 229 230static u_int16_t 231my_phy_readreg(struct my_softc * sc, int reg) 232{ 233 long miir; 234 int mask, data; 235 236 MY_LOCK(sc); 237 238 if (sc->my_info->my_did == MTD803ID) 239 data = CSR_READ_2(sc, MY_PHYBASE + reg * 2); 240 else { 241 miir = my_send_cmd_to_phy(sc, MY_OP_READ, reg); 242 243 /* read data */ 244 mask = 0x8000; 245 data = 0; 246 while (mask) { 247 /* low MDC */ 248 miir &= ~MY_MASK_MIIR_MII_MDC; 249 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 250 251 /* read MDI */ 252 miir = CSR_READ_4(sc, MY_MANAGEMENT); 253 if (miir & MY_MASK_MIIR_MII_MDI) 254 data |= mask; 255 256 /* high MDC, and wait */ 257 miir |= MY_MASK_MIIR_MII_MDC; 258 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 259 DELAY(30); 260 261 /* next */ 262 mask >>= 1; 263 } 264 265 /* low MDC */ 266 miir &= ~MY_MASK_MIIR_MII_MDC; 267 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 268 } 269 270 MY_UNLOCK(sc); 271 return (u_int16_t) data; 272} 273 274 275static void 276my_phy_writereg(struct my_softc * sc, int reg, int data) 277{ 278 long miir; 279 int mask; 280 281 MY_LOCK(sc); 282 283 if (sc->my_info->my_did == MTD803ID) 284 CSR_WRITE_2(sc, MY_PHYBASE + reg * 2, data); 285 else { 286 miir = my_send_cmd_to_phy(sc, MY_OP_WRITE, reg); 287 288 /* write data */ 289 mask = 0x8000; 290 while (mask) { 291 /* low MDC, prepare MDO */ 292 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO); 293 if (mask & data) 294 miir |= MY_MASK_MIIR_MII_MDO; 295 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 296 DELAY(1); 297 298 /* high MDC */ 299 miir |= MY_MASK_MIIR_MII_MDC; 300 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 301 DELAY(1); 302 303 /* next */ 304 mask >>= 1; 305 } 306 307 /* low MDC */ 308 miir &= ~MY_MASK_MIIR_MII_MDC; 309 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 310 } 311 MY_UNLOCK(sc); 312 return; 313} 314 315 316/* 317 * Program the 64-bit multicast hash filter. 318 */ 319static void 320my_setmulti(struct my_softc * sc) 321{ 322 struct ifnet *ifp; 323 int h = 0; 324 u_int32_t hashes[2] = {0, 0}; 325 struct ifmultiaddr *ifma; 326 u_int32_t rxfilt; 327 int mcnt = 0; 328 329 MY_LOCK(sc); 330 331 ifp = &sc->arpcom.ac_if; 332 333 rxfilt = CSR_READ_4(sc, MY_TCRRCR); 334 335 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 336 rxfilt |= MY_AM; 337 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt); 338 CSR_WRITE_4(sc, MY_MAR0, 0xFFFFFFFF); 339 CSR_WRITE_4(sc, MY_MAR1, 0xFFFFFFFF); 340 341 MY_UNLOCK(sc); 342 343 return; 344 } 345 /* first, zot all the existing hash bits */ 346 CSR_WRITE_4(sc, MY_MAR0, 0); 347 CSR_WRITE_4(sc, MY_MAR1, 0); 348 349 /* now program new ones */ 350 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 351 if (ifma->ifma_addr->sa_family != AF_LINK) 352 continue; 353 h = ~ether_crc32_be(LLADDR((struct sockaddr_dl *) 354 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 355 if (h < 32) 356 hashes[0] |= (1 << h); 357 else 358 hashes[1] |= (1 << (h - 32)); 359 mcnt++; 360 } 361 362 if (mcnt) 363 rxfilt |= MY_AM; 364 else 365 rxfilt &= ~MY_AM; 366 CSR_WRITE_4(sc, MY_MAR0, hashes[0]); 367 CSR_WRITE_4(sc, MY_MAR1, hashes[1]); 368 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt); 369 MY_UNLOCK(sc); 370 return; 371} 372 373/* 374 * Initiate an autonegotiation session. 375 */ 376static void 377my_autoneg_xmit(struct my_softc * sc) 378{ 379 u_int16_t phy_sts = 0; 380 381 MY_LOCK(sc); 382 383 my_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); 384 DELAY(500); 385 while (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_RESET); 386 387 phy_sts = my_phy_readreg(sc, PHY_BMCR); 388 phy_sts |= PHY_BMCR_AUTONEGENBL | PHY_BMCR_AUTONEGRSTR; 389 my_phy_writereg(sc, PHY_BMCR, phy_sts); 390 391 MY_UNLOCK(sc); 392 return; 393} 394 395 396/* 397 * Invoke autonegotiation on a PHY. 398 */ 399static void 400my_autoneg_mii(struct my_softc * sc, int flag, int verbose) 401{ 402 u_int16_t phy_sts = 0, media, advert, ability; 403 u_int16_t ability2 = 0; 404 struct ifnet *ifp; 405 struct ifmedia *ifm; 406 407 MY_LOCK(sc); 408 409 ifm = &sc->ifmedia; 410 ifp = &sc->arpcom.ac_if; 411 412 ifm->ifm_media = IFM_ETHER | IFM_AUTO; 413 414#ifndef FORCE_AUTONEG_TFOUR 415 /* 416 * First, see if autoneg is supported. If not, there's no point in 417 * continuing. 418 */ 419 phy_sts = my_phy_readreg(sc, PHY_BMSR); 420 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) { 421 if (verbose) 422 printf("my%d: autonegotiation not supported\n", 423 sc->my_unit); 424 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 425 MY_UNLOCK(sc); 426 return; 427 } 428#endif 429 switch (flag) { 430 case MY_FLAG_FORCEDELAY: 431 /* 432 * XXX Never use this option anywhere but in the probe 433 * routine: making the kernel stop dead in its tracks for 434 * three whole seconds after we've gone multi-user is really 435 * bad manners. 436 */ 437 my_autoneg_xmit(sc); 438 DELAY(5000000); 439 break; 440 case MY_FLAG_SCHEDDELAY: 441 /* 442 * Wait for the transmitter to go idle before starting an 443 * autoneg session, otherwise my_start() may clobber our 444 * timeout, and we don't want to allow transmission during an 445 * autoneg session since that can screw it up. 446 */ 447 if (sc->my_cdata.my_tx_head != NULL) { 448 sc->my_want_auto = 1; 449 MY_UNLOCK(sc); 450 return; 451 } 452 my_autoneg_xmit(sc); 453 ifp->if_timer = 5; 454 sc->my_autoneg = 1; 455 sc->my_want_auto = 0; 456 MY_UNLOCK(sc); 457 return; 458 case MY_FLAG_DELAYTIMEO: 459 ifp->if_timer = 0; 460 sc->my_autoneg = 0; 461 break; 462 default: 463 printf("my%d: invalid autoneg flag: %d\n", sc->my_unit, flag); 464 MY_UNLOCK(sc); 465 return; 466 } 467 468 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) { 469 if (verbose) 470 printf("my%d: autoneg complete, ", sc->my_unit); 471 phy_sts = my_phy_readreg(sc, PHY_BMSR); 472 } else { 473 if (verbose) 474 printf("my%d: autoneg not complete, ", sc->my_unit); 475 } 476 477 media = my_phy_readreg(sc, PHY_BMCR); 478 479 /* Link is good. Report modes and set duplex mode. */ 480 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) { 481 if (verbose) 482 printf("my%d: link status good. ", sc->my_unit); 483 advert = my_phy_readreg(sc, PHY_ANAR); 484 ability = my_phy_readreg(sc, PHY_LPAR); 485 if ((sc->my_pinfo->my_vid == MarvellPHYID0) || 486 (sc->my_pinfo->my_vid == LevelOnePHYID0)) { 487 ability2 = my_phy_readreg(sc, PHY_1000SR); 488 if (ability2 & PHY_1000SR_1000BTXFULL) { 489 advert = 0; 490 ability = 0; 491 /* 492 * this version did not support 1000M, 493 * ifm->ifm_media = 494 * IFM_ETHER|IFM_1000_T|IFM_FDX; 495 */ 496 ifm->ifm_media = 497 IFM_ETHER | IFM_100_TX | IFM_FDX; 498 media &= ~PHY_BMCR_SPEEDSEL; 499 media |= PHY_BMCR_1000; 500 media |= PHY_BMCR_DUPLEX; 501 printf("(full-duplex, 1000Mbps)\n"); 502 } else if (ability2 & PHY_1000SR_1000BTXHALF) { 503 advert = 0; 504 ability = 0; 505 /* 506 * this version did not support 1000M, 507 * ifm->ifm_media = IFM_ETHER|IFM_1000_T; 508 */ 509 ifm->ifm_media = IFM_ETHER | IFM_100_TX; 510 media &= ~PHY_BMCR_SPEEDSEL; 511 media &= ~PHY_BMCR_DUPLEX; 512 media |= PHY_BMCR_1000; 513 printf("(half-duplex, 1000Mbps)\n"); 514 } 515 } 516 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) { 517 ifm->ifm_media = IFM_ETHER | IFM_100_T4; 518 media |= PHY_BMCR_SPEEDSEL; 519 media &= ~PHY_BMCR_DUPLEX; 520 printf("(100baseT4)\n"); 521 } else if (advert & PHY_ANAR_100BTXFULL && 522 ability & PHY_ANAR_100BTXFULL) { 523 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX; 524 media |= PHY_BMCR_SPEEDSEL; 525 media |= PHY_BMCR_DUPLEX; 526 printf("(full-duplex, 100Mbps)\n"); 527 } else if (advert & PHY_ANAR_100BTXHALF && 528 ability & PHY_ANAR_100BTXHALF) { 529 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX; 530 media |= PHY_BMCR_SPEEDSEL; 531 media &= ~PHY_BMCR_DUPLEX; 532 printf("(half-duplex, 100Mbps)\n"); 533 } else if (advert & PHY_ANAR_10BTFULL && 534 ability & PHY_ANAR_10BTFULL) { 535 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX; 536 media &= ~PHY_BMCR_SPEEDSEL; 537 media |= PHY_BMCR_DUPLEX; 538 printf("(full-duplex, 10Mbps)\n"); 539 } else if (advert) { 540 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 541 media &= ~PHY_BMCR_SPEEDSEL; 542 media &= ~PHY_BMCR_DUPLEX; 543 printf("(half-duplex, 10Mbps)\n"); 544 } 545 media &= ~PHY_BMCR_AUTONEGENBL; 546 547 /* Set ASIC's duplex mode to match the PHY. */ 548 my_phy_writereg(sc, PHY_BMCR, media); 549 my_setcfg(sc, media); 550 } else { 551 if (verbose) 552 printf("my%d: no carrier\n", sc->my_unit); 553 } 554 555 my_init(sc); 556 if (sc->my_tx_pend) { 557 sc->my_autoneg = 0; 558 sc->my_tx_pend = 0; 559 my_start(ifp); 560 } 561 MY_UNLOCK(sc); 562 return; 563} 564 565/* 566 * To get PHY ability. 567 */ 568static void 569my_getmode_mii(struct my_softc * sc) 570{ 571 u_int16_t bmsr; 572 struct ifnet *ifp; 573 574 MY_LOCK(sc); 575 ifp = &sc->arpcom.ac_if; 576 bmsr = my_phy_readreg(sc, PHY_BMSR); 577 if (bootverbose) 578 printf("my%d: PHY status word: %x\n", sc->my_unit, bmsr); 579 580 /* fallback */ 581 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 582 583 if (bmsr & PHY_BMSR_10BTHALF) { 584 if (bootverbose) 585 printf("my%d: 10Mbps half-duplex mode supported\n", 586 sc->my_unit); 587 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_HDX, 588 0, NULL); 589 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T, 0, NULL); 590 } 591 if (bmsr & PHY_BMSR_10BTFULL) { 592 if (bootverbose) 593 printf("my%d: 10Mbps full-duplex mode supported\n", 594 sc->my_unit); 595 596 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 597 0, NULL); 598 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX; 599 } 600 if (bmsr & PHY_BMSR_100BTXHALF) { 601 if (bootverbose) 602 printf("my%d: 100Mbps half-duplex mode supported\n", 603 sc->my_unit); 604 ifp->if_baudrate = 100000000; 605 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL); 606 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_HDX, 607 0, NULL); 608 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX; 609 } 610 if (bmsr & PHY_BMSR_100BTXFULL) { 611 if (bootverbose) 612 printf("my%d: 100Mbps full-duplex mode supported\n", 613 sc->my_unit); 614 ifp->if_baudrate = 100000000; 615 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 616 0, NULL); 617 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX; 618 } 619 /* Some also support 100BaseT4. */ 620 if (bmsr & PHY_BMSR_100BT4) { 621 if (bootverbose) 622 printf("my%d: 100baseT4 mode supported\n", sc->my_unit); 623 ifp->if_baudrate = 100000000; 624 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_T4, 0, NULL); 625 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_T4; 626#ifdef FORCE_AUTONEG_TFOUR 627 if (bootverbose) 628 printf("my%d: forcing on autoneg support for BT4\n", 629 sc->my_unit); 630 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0 NULL): 631 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO; 632#endif 633 } 634#if 0 /* this version did not support 1000M, */ 635 if (sc->my_pinfo->my_vid == MarvellPHYID0) { 636 if (bootverbose) 637 printf("my%d: 1000Mbps half-duplex mode supported\n", 638 sc->my_unit); 639 640 ifp->if_baudrate = 1000000000; 641 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL); 642 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_HDX, 643 0, NULL); 644 if (bootverbose) 645 printf("my%d: 1000Mbps full-duplex mode supported\n", 646 sc->my_unit); 647 ifp->if_baudrate = 1000000000; 648 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX, 649 0, NULL); 650 sc->ifmedia.ifm_media = IFM_ETHER | IFM_1000_T | IFM_FDX; 651 } 652#endif 653 if (bmsr & PHY_BMSR_CANAUTONEG) { 654 if (bootverbose) 655 printf("my%d: autoneg supported\n", sc->my_unit); 656 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 657 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO; 658 } 659 MY_UNLOCK(sc); 660 return; 661} 662 663/* 664 * Set speed and duplex mode. 665 */ 666static void 667my_setmode_mii(struct my_softc * sc, int media) 668{ 669 u_int16_t bmcr; 670 struct ifnet *ifp; 671 672 MY_LOCK(sc); 673 ifp = &sc->arpcom.ac_if; 674 /* 675 * If an autoneg session is in progress, stop it. 676 */ 677 if (sc->my_autoneg) { 678 printf("my%d: canceling autoneg session\n", sc->my_unit); 679 ifp->if_timer = sc->my_autoneg = sc->my_want_auto = 0; 680 bmcr = my_phy_readreg(sc, PHY_BMCR); 681 bmcr &= ~PHY_BMCR_AUTONEGENBL; 682 my_phy_writereg(sc, PHY_BMCR, bmcr); 683 } 684 printf("my%d: selecting MII, ", sc->my_unit); 685 bmcr = my_phy_readreg(sc, PHY_BMCR); 686 bmcr &= ~(PHY_BMCR_AUTONEGENBL | PHY_BMCR_SPEEDSEL | PHY_BMCR_1000 | 687 PHY_BMCR_DUPLEX | PHY_BMCR_LOOPBK); 688 689#if 0 /* this version did not support 1000M, */ 690 if (IFM_SUBTYPE(media) == IFM_1000_T) { 691 printf("1000Mbps/T4, half-duplex\n"); 692 bmcr &= ~PHY_BMCR_SPEEDSEL; 693 bmcr &= ~PHY_BMCR_DUPLEX; 694 bmcr |= PHY_BMCR_1000; 695 } 696#endif 697 if (IFM_SUBTYPE(media) == IFM_100_T4) { 698 printf("100Mbps/T4, half-duplex\n"); 699 bmcr |= PHY_BMCR_SPEEDSEL; 700 bmcr &= ~PHY_BMCR_DUPLEX; 701 } 702 if (IFM_SUBTYPE(media) == IFM_100_TX) { 703 printf("100Mbps, "); 704 bmcr |= PHY_BMCR_SPEEDSEL; 705 } 706 if (IFM_SUBTYPE(media) == IFM_10_T) { 707 printf("10Mbps, "); 708 bmcr &= ~PHY_BMCR_SPEEDSEL; 709 } 710 if ((media & IFM_GMASK) == IFM_FDX) { 711 printf("full duplex\n"); 712 bmcr |= PHY_BMCR_DUPLEX; 713 } else { 714 printf("half duplex\n"); 715 bmcr &= ~PHY_BMCR_DUPLEX; 716 } 717 my_phy_writereg(sc, PHY_BMCR, bmcr); 718 my_setcfg(sc, bmcr); 719 MY_UNLOCK(sc); 720 return; 721} 722 723/* 724 * The Myson manual states that in order to fiddle with the 'full-duplex' and 725 * '100Mbps' bits in the netconfig register, we first have to put the 726 * transmit and/or receive logic in the idle state. 727 */ 728static void 729my_setcfg(struct my_softc * sc, int bmcr) 730{ 731 int i, restart = 0; 732 733 MY_LOCK(sc); 734 if (CSR_READ_4(sc, MY_TCRRCR) & (MY_TE | MY_RE)) { 735 restart = 1; 736 MY_CLRBIT(sc, MY_TCRRCR, (MY_TE | MY_RE)); 737 for (i = 0; i < MY_TIMEOUT; i++) { 738 DELAY(10); 739 if (!(CSR_READ_4(sc, MY_TCRRCR) & 740 (MY_TXRUN | MY_RXRUN))) 741 break; 742 } 743 if (i == MY_TIMEOUT) 744 printf("my%d: failed to force tx and rx to idle \n", 745 sc->my_unit); 746 } 747 MY_CLRBIT(sc, MY_TCRRCR, MY_PS1000); 748 MY_CLRBIT(sc, MY_TCRRCR, MY_PS10); 749 if (bmcr & PHY_BMCR_1000) 750 MY_SETBIT(sc, MY_TCRRCR, MY_PS1000); 751 else if (!(bmcr & PHY_BMCR_SPEEDSEL)) 752 MY_SETBIT(sc, MY_TCRRCR, MY_PS10); 753 if (bmcr & PHY_BMCR_DUPLEX) 754 MY_SETBIT(sc, MY_TCRRCR, MY_FD); 755 else 756 MY_CLRBIT(sc, MY_TCRRCR, MY_FD); 757 if (restart) 758 MY_SETBIT(sc, MY_TCRRCR, MY_TE | MY_RE); 759 MY_UNLOCK(sc); 760 return; 761} 762 763static void 764my_reset(struct my_softc * sc) 765{ 766 register int i; 767 768 MY_LOCK(sc); 769 MY_SETBIT(sc, MY_BCR, MY_SWR); 770 for (i = 0; i < MY_TIMEOUT; i++) { 771 DELAY(10); 772 if (!(CSR_READ_4(sc, MY_BCR) & MY_SWR)) 773 break; 774 } 775 if (i == MY_TIMEOUT) 776 printf("m0x%d: reset never completed!\n", sc->my_unit); 777 778 /* Wait a little while for the chip to get its brains in order. */ 779 DELAY(1000); 780 MY_UNLOCK(sc); 781 return; 782} 783 784/* 785 * Probe for a Myson chip. Check the PCI vendor and device IDs against our 786 * list and return a device name if we find a match. 787 */ 788static int 789my_probe(device_t dev) 790{ 791 struct my_type *t; 792 793 t = my_devs; 794 while (t->my_name != NULL) { 795 if ((pci_get_vendor(dev) == t->my_vid) && 796 (pci_get_device(dev) == t->my_did)) { 797 device_set_desc(dev, t->my_name); 798 my_info_tmp = t; 799 return (BUS_PROBE_DEFAULT); 800 } 801 t++; 802 } 803 return (ENXIO); 804} 805 806/* 807 * Attach the interface. Allocate softc structures, do ifmedia setup and 808 * ethernet/BPF attach. 809 */ 810static int 811my_attach(device_t dev) 812{ 813 int s, i; 814 u_char eaddr[ETHER_ADDR_LEN]; 815 u_int32_t command, iobase; 816 struct my_softc *sc; 817 struct ifnet *ifp; 818 int media = IFM_ETHER | IFM_100_TX | IFM_FDX; 819 unsigned int round; 820 caddr_t roundptr; 821 struct my_type *p; 822 u_int16_t phy_vid, phy_did, phy_sts = 0; 823 int rid, unit, error = 0; 824 825 s = splimp(); 826 sc = device_get_softc(dev); 827 unit = device_get_unit(dev); 828 if (sc == NULL) { 829 printf("my%d: no memory for softc struct!\n", unit); 830 error = ENXIO; 831 goto fail; 832 833 } 834 bzero(sc, sizeof(struct my_softc)); 835 mtx_init(&sc->my_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 836 MTX_DEF | MTX_RECURSE); 837 MY_LOCK(sc); 838 839 /* 840 * Map control/status registers. 841 */ 842#if 0 843 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 844 command |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 845 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command & 0x000000ff, 4); 846 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 847#endif 848 command = pci_read_config(dev, PCIR_COMMAND, 4); 849 command |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 850 pci_write_config(dev, PCIR_COMMAND, command & 0x000000ff, 4); 851 command = pci_read_config(dev, PCIR_COMMAND, 4); 852 853 if (my_info_tmp->my_did == MTD800ID) { 854 iobase = pci_read_config(dev, MY_PCI_LOIO, 4); 855 if (iobase & 0x300) 856 MY_USEIOSPACE = 0; 857 } 858 if (MY_USEIOSPACE) { 859 if (!(command & PCIM_CMD_PORTEN)) { 860 printf("my%d: failed to enable I/O ports!\n", unit); 861 free(sc, M_DEVBUF); 862 error = ENXIO; 863 goto fail; 864 } 865#if 0 866 if (!pci_map_port(config_id, MY_PCI_LOIO, (u_int16_t *) & (sc->my_bhandle))) { 867 printf("my%d: couldn't map ports\n", unit); 868 error = ENXIO; 869 goto fail; 870 } 871 872 sc->my_btag = I386_BUS_SPACE_IO; 873#endif 874 } else { 875 if (!(command & PCIM_CMD_MEMEN)) { 876 printf("my%d: failed to enable memory mapping!\n", 877 unit); 878 error = ENXIO; 879 goto fail; 880 } 881#if 0 882 if (!pci_map_mem(config_id, MY_PCI_LOMEM, &vbase, &pbase)) { 883 printf ("my%d: couldn't map memory\n", unit); 884 error = ENXIO; 885 goto fail; 886 } 887 sc->my_btag = I386_BUS_SPACE_MEM; 888 sc->my_bhandle = vbase; 889#endif 890 } 891 892 rid = MY_RID; 893 sc->my_res = bus_alloc_resource_any(dev, MY_RES, &rid, RF_ACTIVE); 894 895 if (sc->my_res == NULL) { 896 printf("my%d: couldn't map ports/memory\n", unit); 897 error = ENXIO; 898 goto fail; 899 } 900 sc->my_btag = rman_get_bustag(sc->my_res); 901 sc->my_bhandle = rman_get_bushandle(sc->my_res); 902 903 rid = 0; 904 sc->my_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 905 RF_SHAREABLE | RF_ACTIVE); 906 907 if (sc->my_irq == NULL) { 908 printf("my%d: couldn't map interrupt\n", unit); 909 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res); 910 error = ENXIO; 911 goto fail; 912 } 913 error = bus_setup_intr(dev, sc->my_irq, INTR_TYPE_NET, 914 my_intr, sc, &sc->my_intrhand); 915 916 if (error) { 917 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq); 918 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res); 919 printf("my%d: couldn't set up irq\n", unit); 920 goto fail; 921 } 922 callout_handle_init(&sc->my_stat_ch); 923 924 sc->my_info = my_info_tmp; 925 926 /* Reset the adapter. */ 927 my_reset(sc); 928 929 /* 930 * Get station address 931 */ 932 for (i = 0; i < ETHER_ADDR_LEN; ++i) 933 eaddr[i] = CSR_READ_1(sc, MY_PAR0 + i); 934 935 sc->my_unit = unit; 936 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 937 938 sc->my_ldata_ptr = malloc(sizeof(struct my_list_data) + 8, 939 M_DEVBUF, M_NOWAIT); 940 if (sc->my_ldata_ptr == NULL) { 941 free(sc, M_DEVBUF); 942 printf("my%d: no memory for list buffers!\n", unit); 943 error = ENXIO; 944 goto fail; 945 } 946 sc->my_ldata = (struct my_list_data *) sc->my_ldata_ptr; 947 round = (uintptr_t)sc->my_ldata_ptr & 0xF; 948 roundptr = sc->my_ldata_ptr; 949 for (i = 0; i < 8; i++) { 950 if (round % 8) { 951 round++; 952 roundptr++; 953 } else 954 break; 955 } 956 sc->my_ldata = (struct my_list_data *) roundptr; 957 bzero(sc->my_ldata, sizeof(struct my_list_data)); 958 959 ifp = &sc->arpcom.ac_if; 960 ifp->if_softc = sc; 961 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 962 ifp->if_mtu = ETHERMTU; 963 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 964 ifp->if_ioctl = my_ioctl; 965 ifp->if_start = my_start; 966 ifp->if_watchdog = my_watchdog; 967 ifp->if_init = my_init; 968 ifp->if_baudrate = 10000000; 969 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 970 971 if (sc->my_info->my_did == MTD803ID) 972 sc->my_pinfo = my_phys; 973 else { 974 if (bootverbose) 975 printf("my%d: probing for a PHY\n", sc->my_unit); 976 for (i = MY_PHYADDR_MIN; i < MY_PHYADDR_MAX + 1; i++) { 977 if (bootverbose) 978 printf("my%d: checking address: %d\n", 979 sc->my_unit, i); 980 sc->my_phy_addr = i; 981 phy_sts = my_phy_readreg(sc, PHY_BMSR); 982 if ((phy_sts != 0) && (phy_sts != 0xffff)) 983 break; 984 else 985 phy_sts = 0; 986 } 987 if (phy_sts) { 988 phy_vid = my_phy_readreg(sc, PHY_VENID); 989 phy_did = my_phy_readreg(sc, PHY_DEVID); 990 if (bootverbose) { 991 printf("my%d: found PHY at address %d, ", 992 sc->my_unit, sc->my_phy_addr); 993 printf("vendor id: %x device id: %x\n", 994 phy_vid, phy_did); 995 } 996 p = my_phys; 997 while (p->my_vid) { 998 if (phy_vid == p->my_vid) { 999 sc->my_pinfo = p; 1000 break; 1001 } 1002 p++; 1003 } 1004 if (sc->my_pinfo == NULL) 1005 sc->my_pinfo = &my_phys[PHY_UNKNOWN]; 1006 if (bootverbose) 1007 printf("my%d: PHY type: %s\n", 1008 sc->my_unit, sc->my_pinfo->my_name); 1009 } else { 1010 printf("my%d: MII without any phy!\n", sc->my_unit); 1011 error = ENXIO; 1012 goto fail; 1013 } 1014 } 1015 1016 /* Do ifmedia setup. */ 1017 ifmedia_init(&sc->ifmedia, 0, my_ifmedia_upd, my_ifmedia_sts); 1018 my_getmode_mii(sc); 1019 my_autoneg_mii(sc, MY_FLAG_FORCEDELAY, 1); 1020 media = sc->ifmedia.ifm_media; 1021 my_stop(sc); 1022 ifmedia_set(&sc->ifmedia, media); 1023 1024 ether_ifattach(ifp, eaddr); 1025 1026#if 0 1027 at_shutdown(my_shutdown, sc, SHUTDOWN_POST_SYNC); 1028 shutdownhook_establish(my_shutdown, sc); 1029#endif 1030 1031 MY_UNLOCK(sc); 1032 return (0); 1033 1034fail: 1035 MY_UNLOCK(sc); 1036 mtx_destroy(&sc->my_mtx); 1037 splx(s); 1038 return (error); 1039} 1040 1041static int 1042my_detach(device_t dev) 1043{ 1044 struct my_softc *sc; 1045 struct ifnet *ifp; 1046 int s; 1047 1048 s = splimp(); 1049 sc = device_get_softc(dev); 1050 MY_LOCK(sc); 1051 ifp = &sc->arpcom.ac_if; 1052 ether_ifdetach(ifp); 1053 my_stop(sc); 1054 1055#if 0 1056 bus_generic_detach(dev); 1057 device_delete_child(dev, sc->rl_miibus); 1058#endif 1059 1060 bus_teardown_intr(dev, sc->my_irq, sc->my_intrhand); 1061 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq); 1062 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res); 1063#if 0 1064 contigfree(sc->my_cdata.my_rx_buf, MY_RXBUFLEN + 32, M_DEVBUF); 1065#endif 1066 free(sc, M_DEVBUF); 1067 MY_UNLOCK(sc); 1068 splx(s); 1069 mtx_destroy(&sc->my_mtx); 1070 return (0); 1071} 1072 1073 1074/* 1075 * Initialize the transmit descriptors. 1076 */ 1077static int 1078my_list_tx_init(struct my_softc * sc) 1079{ 1080 struct my_chain_data *cd; 1081 struct my_list_data *ld; 1082 int i; 1083 1084 MY_LOCK(sc); 1085 cd = &sc->my_cdata; 1086 ld = sc->my_ldata; 1087 for (i = 0; i < MY_TX_LIST_CNT; i++) { 1088 cd->my_tx_chain[i].my_ptr = &ld->my_tx_list[i]; 1089 if (i == (MY_TX_LIST_CNT - 1)) 1090 cd->my_tx_chain[i].my_nextdesc = &cd->my_tx_chain[0]; 1091 else 1092 cd->my_tx_chain[i].my_nextdesc = 1093 &cd->my_tx_chain[i + 1]; 1094 } 1095 cd->my_tx_free = &cd->my_tx_chain[0]; 1096 cd->my_tx_tail = cd->my_tx_head = NULL; 1097 MY_UNLOCK(sc); 1098 return (0); 1099} 1100 1101/* 1102 * Initialize the RX descriptors and allocate mbufs for them. Note that we 1103 * arrange the descriptors in a closed ring, so that the last descriptor 1104 * points back to the first. 1105 */ 1106static int 1107my_list_rx_init(struct my_softc * sc) 1108{ 1109 struct my_chain_data *cd; 1110 struct my_list_data *ld; 1111 int i; 1112 1113 MY_LOCK(sc); 1114 cd = &sc->my_cdata; 1115 ld = sc->my_ldata; 1116 for (i = 0; i < MY_RX_LIST_CNT; i++) { 1117 cd->my_rx_chain[i].my_ptr = 1118 (struct my_desc *) & ld->my_rx_list[i]; 1119 if (my_newbuf(sc, &cd->my_rx_chain[i]) == ENOBUFS) { 1120 MY_UNLOCK(sc); 1121 return (ENOBUFS); 1122 } 1123 if (i == (MY_RX_LIST_CNT - 1)) { 1124 cd->my_rx_chain[i].my_nextdesc = &cd->my_rx_chain[0]; 1125 ld->my_rx_list[i].my_next = vtophys(&ld->my_rx_list[0]); 1126 } else { 1127 cd->my_rx_chain[i].my_nextdesc = 1128 &cd->my_rx_chain[i + 1]; 1129 ld->my_rx_list[i].my_next = 1130 vtophys(&ld->my_rx_list[i + 1]); 1131 } 1132 } 1133 cd->my_rx_head = &cd->my_rx_chain[0]; 1134 MY_UNLOCK(sc); 1135 return (0); 1136} 1137 1138/* 1139 * Initialize an RX descriptor and attach an MBUF cluster. 1140 */ 1141static int 1142my_newbuf(struct my_softc * sc, struct my_chain_onefrag * c) 1143{ 1144 struct mbuf *m_new = NULL; 1145 1146 MY_LOCK(sc); 1147 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1148 if (m_new == NULL) { 1149 printf("my%d: no memory for rx list -- packet dropped!\n", 1150 sc->my_unit); 1151 MY_UNLOCK(sc); 1152 return (ENOBUFS); 1153 } 1154 MCLGET(m_new, M_DONTWAIT); 1155 if (!(m_new->m_flags & M_EXT)) { 1156 printf("my%d: no memory for rx list -- packet dropped!\n", 1157 sc->my_unit); 1158 m_freem(m_new); 1159 MY_UNLOCK(sc); 1160 return (ENOBUFS); 1161 } 1162 c->my_mbuf = m_new; 1163 c->my_ptr->my_data = vtophys(mtod(m_new, caddr_t)); 1164 c->my_ptr->my_ctl = (MCLBYTES - 1) << MY_RBSShift; 1165 c->my_ptr->my_status = MY_OWNByNIC; 1166 MY_UNLOCK(sc); 1167 return (0); 1168} 1169 1170/* 1171 * A frame has been uploaded: pass the resulting mbuf chain up to the higher 1172 * level protocols. 1173 */ 1174static void 1175my_rxeof(struct my_softc * sc) 1176{ 1177 struct ether_header *eh; 1178 struct mbuf *m; 1179 struct ifnet *ifp; 1180 struct my_chain_onefrag *cur_rx; 1181 int total_len = 0; 1182 u_int32_t rxstat; 1183 1184 MY_LOCK(sc); 1185 ifp = &sc->arpcom.ac_if; 1186 while (!((rxstat = sc->my_cdata.my_rx_head->my_ptr->my_status) 1187 & MY_OWNByNIC)) { 1188 cur_rx = sc->my_cdata.my_rx_head; 1189 sc->my_cdata.my_rx_head = cur_rx->my_nextdesc; 1190 1191 if (rxstat & MY_ES) { /* error summary: give up this rx pkt */ 1192 ifp->if_ierrors++; 1193 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1194 continue; 1195 } 1196 /* No errors; receive the packet. */ 1197 total_len = (rxstat & MY_FLNGMASK) >> MY_FLNGShift; 1198 total_len -= ETHER_CRC_LEN; 1199 1200 if (total_len < MINCLSIZE) { 1201 m = m_devget(mtod(cur_rx->my_mbuf, char *), 1202 total_len, 0, ifp, NULL); 1203 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1204 if (m == NULL) { 1205 ifp->if_ierrors++; 1206 continue; 1207 } 1208 } else { 1209 m = cur_rx->my_mbuf; 1210 /* 1211 * Try to conjure up a new mbuf cluster. If that 1212 * fails, it means we have an out of memory condition 1213 * and should leave the buffer in place and continue. 1214 * This will result in a lost packet, but there's 1215 * little else we can do in this situation. 1216 */ 1217 if (my_newbuf(sc, cur_rx) == ENOBUFS) { 1218 ifp->if_ierrors++; 1219 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1220 continue; 1221 } 1222 m->m_pkthdr.rcvif = ifp; 1223 m->m_pkthdr.len = m->m_len = total_len; 1224 } 1225 ifp->if_ipackets++; 1226 eh = mtod(m, struct ether_header *); 1227#if NBPFILTER > 0 1228 /* 1229 * Handle BPF listeners. Let the BPF user see the packet, but 1230 * don't pass it up to the ether_input() layer unless it's a 1231 * broadcast packet, multicast packet, matches our ethernet 1232 * address or the interface is in promiscuous mode. 1233 */ 1234 if (ifp->if_bpf) { 1235 BPF_MTAP(ifp, m); 1236 if (ifp->if_flags & IFF_PROMISC && 1237 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 1238 ETHER_ADDR_LEN) && 1239 (eh->ether_dhost[0] & 1) == 0)) { 1240 m_freem(m); 1241 continue; 1242 } 1243 } 1244#endif 1245 MY_UNLOCK(sc); 1246 (*ifp->if_input)(ifp, m); 1247 MY_LOCK(sc); 1248 } 1249 MY_UNLOCK(sc); 1250 return; 1251} 1252 1253 1254/* 1255 * A frame was downloaded to the chip. It's safe for us to clean up the list 1256 * buffers. 1257 */ 1258static void 1259my_txeof(struct my_softc * sc) 1260{ 1261 struct my_chain *cur_tx; 1262 struct ifnet *ifp; 1263 1264 MY_LOCK(sc); 1265 ifp = &sc->arpcom.ac_if; 1266 /* Clear the timeout timer. */ 1267 ifp->if_timer = 0; 1268 if (sc->my_cdata.my_tx_head == NULL) { 1269 MY_UNLOCK(sc); 1270 return; 1271 } 1272 /* 1273 * Go through our tx list and free mbufs for those frames that have 1274 * been transmitted. 1275 */ 1276 while (sc->my_cdata.my_tx_head->my_mbuf != NULL) { 1277 u_int32_t txstat; 1278 1279 cur_tx = sc->my_cdata.my_tx_head; 1280 txstat = MY_TXSTATUS(cur_tx); 1281 if ((txstat & MY_OWNByNIC) || txstat == MY_UNSENT) 1282 break; 1283 if (!(CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced)) { 1284 if (txstat & MY_TXERR) { 1285 ifp->if_oerrors++; 1286 if (txstat & MY_EC) /* excessive collision */ 1287 ifp->if_collisions++; 1288 if (txstat & MY_LC) /* late collision */ 1289 ifp->if_collisions++; 1290 } 1291 ifp->if_collisions += (txstat & MY_NCRMASK) >> 1292 MY_NCRShift; 1293 } 1294 ifp->if_opackets++; 1295 m_freem(cur_tx->my_mbuf); 1296 cur_tx->my_mbuf = NULL; 1297 if (sc->my_cdata.my_tx_head == sc->my_cdata.my_tx_tail) { 1298 sc->my_cdata.my_tx_head = NULL; 1299 sc->my_cdata.my_tx_tail = NULL; 1300 break; 1301 } 1302 sc->my_cdata.my_tx_head = cur_tx->my_nextdesc; 1303 } 1304 if (CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced) { 1305 ifp->if_collisions += (CSR_READ_4(sc, MY_TSR) & MY_NCRMask); 1306 } 1307 MY_UNLOCK(sc); 1308 return; 1309} 1310 1311/* 1312 * TX 'end of channel' interrupt handler. 1313 */ 1314static void 1315my_txeoc(struct my_softc * sc) 1316{ 1317 struct ifnet *ifp; 1318 1319 MY_LOCK(sc); 1320 ifp = &sc->arpcom.ac_if; 1321 ifp->if_timer = 0; 1322 if (sc->my_cdata.my_tx_head == NULL) { 1323 ifp->if_flags &= ~IFF_OACTIVE; 1324 sc->my_cdata.my_tx_tail = NULL; 1325 if (sc->my_want_auto) 1326 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1); 1327 } else { 1328 if (MY_TXOWN(sc->my_cdata.my_tx_head) == MY_UNSENT) { 1329 MY_TXOWN(sc->my_cdata.my_tx_head) = MY_OWNByNIC; 1330 ifp->if_timer = 5; 1331 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); 1332 } 1333 } 1334 MY_UNLOCK(sc); 1335 return; 1336} 1337 1338static void 1339my_intr(void *arg) 1340{ 1341 struct my_softc *sc; 1342 struct ifnet *ifp; 1343 u_int32_t status; 1344 1345 sc = arg; 1346 MY_LOCK(sc); 1347 ifp = &sc->arpcom.ac_if; 1348 if (!(ifp->if_flags & IFF_UP)) { 1349 MY_UNLOCK(sc); 1350 return; 1351 } 1352 /* Disable interrupts. */ 1353 CSR_WRITE_4(sc, MY_IMR, 0x00000000); 1354 1355 for (;;) { 1356 status = CSR_READ_4(sc, MY_ISR); 1357 status &= MY_INTRS; 1358 if (status) 1359 CSR_WRITE_4(sc, MY_ISR, status); 1360 else 1361 break; 1362 1363 if (status & MY_RI) /* receive interrupt */ 1364 my_rxeof(sc); 1365 1366 if ((status & MY_RBU) || (status & MY_RxErr)) { 1367 /* rx buffer unavailable or rx error */ 1368 ifp->if_ierrors++; 1369#ifdef foo 1370 my_stop(sc); 1371 my_reset(sc); 1372 my_init(sc); 1373#endif 1374 } 1375 if (status & MY_TI) /* tx interrupt */ 1376 my_txeof(sc); 1377 if (status & MY_ETI) /* tx early interrupt */ 1378 my_txeof(sc); 1379 if (status & MY_TBU) /* tx buffer unavailable */ 1380 my_txeoc(sc); 1381 1382#if 0 /* 90/1/18 delete */ 1383 if (status & MY_FBE) { 1384 my_reset(sc); 1385 my_init(sc); 1386 } 1387#endif 1388 1389 } 1390 1391 /* Re-enable interrupts. */ 1392 CSR_WRITE_4(sc, MY_IMR, MY_INTRS); 1393 if (ifp->if_snd.ifq_head != NULL) 1394 my_start(ifp); 1395 MY_UNLOCK(sc); 1396 return; 1397} 1398 1399/* 1400 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1401 * pointers to the fragment pointers. 1402 */ 1403static int 1404my_encap(struct my_softc * sc, struct my_chain * c, struct mbuf * m_head) 1405{ 1406 struct my_desc *f = NULL; 1407 int total_len; 1408 struct mbuf *m, *m_new = NULL; 1409 1410 MY_LOCK(sc); 1411 /* calculate the total tx pkt length */ 1412 total_len = 0; 1413 for (m = m_head; m != NULL; m = m->m_next) 1414 total_len += m->m_len; 1415 /* 1416 * Start packing the mbufs in this chain into the fragment pointers. 1417 * Stop when we run out of fragments or hit the end of the mbuf 1418 * chain. 1419 */ 1420 m = m_head; 1421 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1422 if (m_new == NULL) { 1423 printf("my%d: no memory for tx list", sc->my_unit); 1424 MY_UNLOCK(sc); 1425 return (1); 1426 } 1427 if (m_head->m_pkthdr.len > MHLEN) { 1428 MCLGET(m_new, M_DONTWAIT); 1429 if (!(m_new->m_flags & M_EXT)) { 1430 m_freem(m_new); 1431 printf("my%d: no memory for tx list", sc->my_unit); 1432 MY_UNLOCK(sc); 1433 return (1); 1434 } 1435 } 1436 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t)); 1437 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1438 m_freem(m_head); 1439 m_head = m_new; 1440 f = &c->my_ptr->my_frag[0]; 1441 f->my_status = 0; 1442 f->my_data = vtophys(mtod(m_new, caddr_t)); 1443 total_len = m_new->m_len; 1444 f->my_ctl = MY_TXFD | MY_TXLD | MY_CRCEnable | MY_PADEnable; 1445 f->my_ctl |= total_len << MY_PKTShift; /* pkt size */ 1446 f->my_ctl |= total_len; /* buffer size */ 1447 /* 89/12/29 add, for mtd891 *//* [ 89? ] */ 1448 if (sc->my_info->my_did == MTD891ID) 1449 f->my_ctl |= MY_ETIControl | MY_RetryTxLC; 1450 c->my_mbuf = m_head; 1451 c->my_lastdesc = 0; 1452 MY_TXNEXT(c) = vtophys(&c->my_nextdesc->my_ptr->my_frag[0]); 1453 MY_UNLOCK(sc); 1454 return (0); 1455} 1456 1457/* 1458 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1459 * to the mbuf data regions directly in the transmit lists. We also save a 1460 * copy of the pointers since the transmit list fragment pointers are 1461 * physical addresses. 1462 */ 1463static void 1464my_start(struct ifnet * ifp) 1465{ 1466 struct my_softc *sc; 1467 struct mbuf *m_head = NULL; 1468 struct my_chain *cur_tx = NULL, *start_tx; 1469 1470 sc = ifp->if_softc; 1471 MY_LOCK(sc); 1472 if (sc->my_autoneg) { 1473 sc->my_tx_pend = 1; 1474 MY_UNLOCK(sc); 1475 return; 1476 } 1477 /* 1478 * Check for an available queue slot. If there are none, punt. 1479 */ 1480 if (sc->my_cdata.my_tx_free->my_mbuf != NULL) { 1481 ifp->if_flags |= IFF_OACTIVE; 1482 MY_UNLOCK(sc); 1483 return; 1484 } 1485 start_tx = sc->my_cdata.my_tx_free; 1486 while (sc->my_cdata.my_tx_free->my_mbuf == NULL) { 1487 IF_DEQUEUE(&ifp->if_snd, m_head); 1488 if (m_head == NULL) 1489 break; 1490 1491 /* Pick a descriptor off the free list. */ 1492 cur_tx = sc->my_cdata.my_tx_free; 1493 sc->my_cdata.my_tx_free = cur_tx->my_nextdesc; 1494 1495 /* Pack the data into the descriptor. */ 1496 my_encap(sc, cur_tx, m_head); 1497 1498 if (cur_tx != start_tx) 1499 MY_TXOWN(cur_tx) = MY_OWNByNIC; 1500#if NBPFILTER > 0 1501 /* 1502 * If there's a BPF listener, bounce a copy of this frame to 1503 * him. 1504 */ 1505 BPF_MTAP(ifp, cur_tx->my_mbuf); 1506#endif 1507 } 1508 /* 1509 * If there are no packets queued, bail. 1510 */ 1511 if (cur_tx == NULL) { 1512 MY_UNLOCK(sc); 1513 return; 1514 } 1515 /* 1516 * Place the request for the upload interrupt in the last descriptor 1517 * in the chain. This way, if we're chaining several packets at once, 1518 * we'll only get an interupt once for the whole chain rather than 1519 * once for each packet. 1520 */ 1521 MY_TXCTL(cur_tx) |= MY_TXIC; 1522 cur_tx->my_ptr->my_frag[0].my_ctl |= MY_TXIC; 1523 sc->my_cdata.my_tx_tail = cur_tx; 1524 if (sc->my_cdata.my_tx_head == NULL) 1525 sc->my_cdata.my_tx_head = start_tx; 1526 MY_TXOWN(start_tx) = MY_OWNByNIC; 1527 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); /* tx polling demand */ 1528 1529 /* 1530 * Set a timeout in case the chip goes out to lunch. 1531 */ 1532 ifp->if_timer = 5; 1533 MY_UNLOCK(sc); 1534 return; 1535} 1536 1537static void 1538my_init(void *xsc) 1539{ 1540 struct my_softc *sc = xsc; 1541 struct ifnet *ifp = &sc->arpcom.ac_if; 1542 int s; 1543 u_int16_t phy_bmcr = 0; 1544 1545 MY_LOCK(sc); 1546 if (sc->my_autoneg) { 1547 MY_UNLOCK(sc); 1548 return; 1549 } 1550 s = splimp(); 1551 if (sc->my_pinfo != NULL) 1552 phy_bmcr = my_phy_readreg(sc, PHY_BMCR); 1553 /* 1554 * Cancel pending I/O and free all RX/TX buffers. 1555 */ 1556 my_stop(sc); 1557 my_reset(sc); 1558 1559 /* 1560 * Set cache alignment and burst length. 1561 */ 1562#if 0 /* 89/9/1 modify, */ 1563 CSR_WRITE_4(sc, MY_BCR, MY_RPBLE512); 1564 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF); 1565#endif 1566 CSR_WRITE_4(sc, MY_BCR, MY_PBL8); 1567 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF | MY_RBLEN | MY_RPBLE512); 1568 /* 1569 * 89/12/29 add, for mtd891, 1570 */ 1571 if (sc->my_info->my_did == MTD891ID) { 1572 MY_SETBIT(sc, MY_BCR, MY_PROG); 1573 MY_SETBIT(sc, MY_TCRRCR, MY_Enhanced); 1574 } 1575 my_setcfg(sc, phy_bmcr); 1576 /* Init circular RX list. */ 1577 if (my_list_rx_init(sc) == ENOBUFS) { 1578 printf("my%d: init failed: no memory for rx buffers\n", 1579 sc->my_unit); 1580 my_stop(sc); 1581 (void)splx(s); 1582 MY_UNLOCK(sc); 1583 return; 1584 } 1585 /* Init TX descriptors. */ 1586 my_list_tx_init(sc); 1587 1588 /* If we want promiscuous mode, set the allframes bit. */ 1589 if (ifp->if_flags & IFF_PROMISC) 1590 MY_SETBIT(sc, MY_TCRRCR, MY_PROM); 1591 else 1592 MY_CLRBIT(sc, MY_TCRRCR, MY_PROM); 1593 1594 /* 1595 * Set capture broadcast bit to capture broadcast frames. 1596 */ 1597 if (ifp->if_flags & IFF_BROADCAST) 1598 MY_SETBIT(sc, MY_TCRRCR, MY_AB); 1599 else 1600 MY_CLRBIT(sc, MY_TCRRCR, MY_AB); 1601 1602 /* 1603 * Program the multicast filter, if necessary. 1604 */ 1605 my_setmulti(sc); 1606 1607 /* 1608 * Load the address of the RX list. 1609 */ 1610 MY_CLRBIT(sc, MY_TCRRCR, MY_RE); 1611 CSR_WRITE_4(sc, MY_RXLBA, vtophys(&sc->my_ldata->my_rx_list[0])); 1612 1613 /* 1614 * Enable interrupts. 1615 */ 1616 CSR_WRITE_4(sc, MY_IMR, MY_INTRS); 1617 CSR_WRITE_4(sc, MY_ISR, 0xFFFFFFFF); 1618 1619 /* Enable receiver and transmitter. */ 1620 MY_SETBIT(sc, MY_TCRRCR, MY_RE); 1621 MY_CLRBIT(sc, MY_TCRRCR, MY_TE); 1622 CSR_WRITE_4(sc, MY_TXLBA, vtophys(&sc->my_ldata->my_tx_list[0])); 1623 MY_SETBIT(sc, MY_TCRRCR, MY_TE); 1624 1625 /* Restore state of BMCR */ 1626 if (sc->my_pinfo != NULL) 1627 my_phy_writereg(sc, PHY_BMCR, phy_bmcr); 1628 ifp->if_flags |= IFF_RUNNING; 1629 ifp->if_flags &= ~IFF_OACTIVE; 1630 (void)splx(s); 1631 MY_UNLOCK(sc); 1632 return; 1633} 1634 1635/* 1636 * Set media options. 1637 */ 1638 1639static int 1640my_ifmedia_upd(struct ifnet * ifp) 1641{ 1642 struct my_softc *sc; 1643 struct ifmedia *ifm; 1644 1645 sc = ifp->if_softc; 1646 MY_LOCK(sc); 1647 ifm = &sc->ifmedia; 1648 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) { 1649 MY_UNLOCK(sc); 1650 return (EINVAL); 1651 } 1652 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) 1653 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1); 1654 else 1655 my_setmode_mii(sc, ifm->ifm_media); 1656 MY_UNLOCK(sc); 1657 return (0); 1658} 1659 1660/* 1661 * Report current media status. 1662 */ 1663 1664static void 1665my_ifmedia_sts(struct ifnet * ifp, struct ifmediareq * ifmr) 1666{ 1667 struct my_softc *sc; 1668 u_int16_t advert = 0, ability = 0; 1669 1670 sc = ifp->if_softc; 1671 MY_LOCK(sc); 1672 ifmr->ifm_active = IFM_ETHER; 1673 if (!(my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) { 1674#if 0 /* this version did not support 1000M, */ 1675 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_1000) 1676 ifmr->ifm_active = IFM_ETHER | IFM_1000TX; 1677#endif 1678 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL) 1679 ifmr->ifm_active = IFM_ETHER | IFM_100_TX; 1680 else 1681 ifmr->ifm_active = IFM_ETHER | IFM_10_T; 1682 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX) 1683 ifmr->ifm_active |= IFM_FDX; 1684 else 1685 ifmr->ifm_active |= IFM_HDX; 1686 1687 MY_UNLOCK(sc); 1688 return; 1689 } 1690 ability = my_phy_readreg(sc, PHY_LPAR); 1691 advert = my_phy_readreg(sc, PHY_ANAR); 1692 1693#if 0 /* this version did not support 1000M, */ 1694 if (sc->my_pinfo->my_vid = MarvellPHYID0) { 1695 ability2 = my_phy_readreg(sc, PHY_1000SR); 1696 if (ability2 & PHY_1000SR_1000BTXFULL) { 1697 advert = 0; 1698 ability = 0; 1699 ifmr->ifm_active = IFM_ETHER|IFM_1000_T|IFM_FDX; 1700 } else if (ability & PHY_1000SR_1000BTXHALF) { 1701 advert = 0; 1702 ability = 0; 1703 ifmr->ifm_active = IFM_ETHER|IFM_1000_T|IFM_HDX; 1704 } 1705 } 1706#endif 1707 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) 1708 ifmr->ifm_active = IFM_ETHER | IFM_100_T4; 1709 else if (advert & PHY_ANAR_100BTXFULL && ability & PHY_ANAR_100BTXFULL) 1710 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1711 else if (advert & PHY_ANAR_100BTXHALF && ability & PHY_ANAR_100BTXHALF) 1712 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_HDX; 1713 else if (advert & PHY_ANAR_10BTFULL && ability & PHY_ANAR_10BTFULL) 1714 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_FDX; 1715 else if (advert & PHY_ANAR_10BTHALF && ability & PHY_ANAR_10BTHALF) 1716 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_HDX; 1717 MY_UNLOCK(sc); 1718 return; 1719} 1720 1721static int 1722my_ioctl(struct ifnet * ifp, u_long command, caddr_t data) 1723{ 1724 struct my_softc *sc = ifp->if_softc; 1725 struct ifreq *ifr = (struct ifreq *) data; 1726 int s, error = 0; 1727 1728 s = splimp(); 1729 MY_LOCK(sc); 1730 switch (command) { 1731 case SIOCSIFFLAGS: 1732 if (ifp->if_flags & IFF_UP) 1733 my_init(sc); 1734 else if (ifp->if_flags & IFF_RUNNING) 1735 my_stop(sc); 1736 error = 0; 1737 break; 1738 case SIOCADDMULTI: 1739 case SIOCDELMULTI: 1740 my_setmulti(sc); 1741 error = 0; 1742 break; 1743 case SIOCGIFMEDIA: 1744 case SIOCSIFMEDIA: 1745 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 1746 break; 1747 default: 1748 error = ether_ioctl(ifp, command, data); 1749 break; 1750 } 1751 MY_UNLOCK(sc); 1752 (void)splx(s); 1753 return (error); 1754} 1755 1756static void 1757my_watchdog(struct ifnet * ifp) 1758{ 1759 struct my_softc *sc; 1760 1761 sc = ifp->if_softc; 1762 MY_LOCK(sc); 1763 if (sc->my_autoneg) { 1764 my_autoneg_mii(sc, MY_FLAG_DELAYTIMEO, 1); 1765 MY_UNLOCK(sc); 1766 return; 1767 } 1768 ifp->if_oerrors++; 1769 printf("my%d: watchdog timeout\n", sc->my_unit); 1770 if (!(my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1771 printf("my%d: no carrier - transceiver cable problem?\n", 1772 sc->my_unit); 1773 my_stop(sc); 1774 my_reset(sc); 1775 my_init(sc); 1776 if (ifp->if_snd.ifq_head != NULL) 1777 my_start(ifp); 1778 MY_LOCK(sc); 1779 return; 1780} 1781 1782 1783/* 1784 * Stop the adapter and free any mbufs allocated to the RX and TX lists. 1785 */ 1786static void 1787my_stop(struct my_softc * sc) 1788{ 1789 register int i; 1790 struct ifnet *ifp; 1791 1792 MY_LOCK(sc); 1793 ifp = &sc->arpcom.ac_if; 1794 ifp->if_timer = 0; 1795 1796 MY_CLRBIT(sc, MY_TCRRCR, (MY_RE | MY_TE)); 1797 CSR_WRITE_4(sc, MY_IMR, 0x00000000); 1798 CSR_WRITE_4(sc, MY_TXLBA, 0x00000000); 1799 CSR_WRITE_4(sc, MY_RXLBA, 0x00000000); 1800 1801 /* 1802 * Free data in the RX lists. 1803 */ 1804 for (i = 0; i < MY_RX_LIST_CNT; i++) { 1805 if (sc->my_cdata.my_rx_chain[i].my_mbuf != NULL) { 1806 m_freem(sc->my_cdata.my_rx_chain[i].my_mbuf); 1807 sc->my_cdata.my_rx_chain[i].my_mbuf = NULL; 1808 } 1809 } 1810 bzero((char *)&sc->my_ldata->my_rx_list, 1811 sizeof(sc->my_ldata->my_rx_list)); 1812 /* 1813 * Free the TX list buffers. 1814 */ 1815 for (i = 0; i < MY_TX_LIST_CNT; i++) { 1816 if (sc->my_cdata.my_tx_chain[i].my_mbuf != NULL) { 1817 m_freem(sc->my_cdata.my_tx_chain[i].my_mbuf); 1818 sc->my_cdata.my_tx_chain[i].my_mbuf = NULL; 1819 } 1820 } 1821 bzero((char *)&sc->my_ldata->my_tx_list, 1822 sizeof(sc->my_ldata->my_tx_list)); 1823 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1824 MY_UNLOCK(sc); 1825 return; 1826} 1827 1828/* 1829 * Stop all chip I/O so that the kernel's probe routines don't get confused 1830 * by errant DMAs when rebooting. 1831 */ 1832static void 1833my_shutdown(device_t dev) 1834{ 1835 struct my_softc *sc; 1836 1837 sc = device_get_softc(dev); 1838 my_stop(sc); 1839 return; 1840} 1841