if_my.c revision 127135
1/*- 2 * Written by: yen_cw@myson.com.tw 3 * Copyright (c) 2002 Myson Technology Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer, 11 * without modification, immediately at the beginning of the file. 12 * 2. The name of the author may not be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 19 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * Myson fast ethernet PCI NIC driver, available at: http://www.myson.com.tw/ 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/my/if_my.c 127135 2004-03-17 17:50:55Z njl $"); 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/sockio.h> 36#include <sys/mbuf.h> 37#include <sys/malloc.h> 38#include <sys/kernel.h> 39#include <sys/socket.h> 40#include <sys/queue.h> 41#include <sys/types.h> 42#include <sys/bus.h> 43#include <sys/module.h> 44#include <sys/lock.h> 45#include <sys/mutex.h> 46 47#define NBPFILTER 1 48 49#include <net/if.h> 50#include <net/if_arp.h> 51#include <net/ethernet.h> 52#include <net/if_media.h> 53#include <net/if_dl.h> 54#include <net/bpf.h> 55 56#include <vm/vm.h> /* for vtophys */ 57#include <vm/pmap.h> /* for vtophys */ 58#include <machine/clock.h> /* for DELAY */ 59#include <machine/bus_memio.h> 60#include <machine/bus_pio.h> 61#include <machine/bus.h> 62#include <machine/resource.h> 63#include <sys/bus.h> 64#include <sys/rman.h> 65 66#include <dev/pci/pcireg.h> 67#include <dev/pci/pcivar.h> 68 69#include <dev/mii/mii.h> 70#include <dev/mii/miivar.h> 71 72#include "miibus_if.h" 73 74/* 75 * #define MY_USEIOSPACE 76 */ 77 78static int MY_USEIOSPACE = 1; 79 80#if (MY_USEIOSPACE) 81#define MY_RES SYS_RES_IOPORT 82#define MY_RID MY_PCI_LOIO 83#else 84#define MY_RES SYS_RES_MEMORY 85#define MY_RID MY_PCI_LOMEM 86#endif 87 88 89#include <dev/my/if_myreg.h> 90 91#ifndef lint 92static const char rcsid[] = 93"$Id: if_my.c,v 1.16 2003/04/15 06:37:25 mdodd Exp $"; 94#endif 95 96/* 97 * Various supported device vendors/types and their names. 98 */ 99struct my_type *my_info_tmp; 100static struct my_type my_devs[] = { 101 {MYSONVENDORID, MTD800ID, "Myson MTD80X Based Fast Ethernet Card"}, 102 {MYSONVENDORID, MTD803ID, "Myson MTD80X Based Fast Ethernet Card"}, 103 {MYSONVENDORID, MTD891ID, "Myson MTD89X Based Giga Ethernet Card"}, 104 {0, 0, NULL} 105}; 106 107/* 108 * Various supported PHY vendors/types and their names. Note that this driver 109 * will work with pretty much any MII-compliant PHY, so failure to positively 110 * identify the chip is not a fatal error. 111 */ 112static struct my_type my_phys[] = { 113 {MysonPHYID0, MysonPHYID0, "<MYSON MTD981>"}, 114 {SeeqPHYID0, SeeqPHYID0, "<SEEQ 80225>"}, 115 {AhdocPHYID0, AhdocPHYID0, "<AHDOC 101>"}, 116 {MarvellPHYID0, MarvellPHYID0, "<MARVELL 88E1000>"}, 117 {LevelOnePHYID0, LevelOnePHYID0, "<LevelOne LXT1000>"}, 118 {0, 0, "<MII-compliant physical interface>"} 119}; 120 121static int my_probe(device_t); 122static int my_attach(device_t); 123static int my_detach(device_t); 124static int my_newbuf(struct my_softc *, struct my_chain_onefrag *); 125static int my_encap(struct my_softc *, struct my_chain *, struct mbuf *); 126static void my_rxeof(struct my_softc *); 127static void my_txeof(struct my_softc *); 128static void my_txeoc(struct my_softc *); 129static void my_intr(void *); 130static void my_start(struct ifnet *); 131static int my_ioctl(struct ifnet *, u_long, caddr_t); 132static void my_init(void *); 133static void my_stop(struct my_softc *); 134static void my_watchdog(struct ifnet *); 135static void my_shutdown(device_t); 136static int my_ifmedia_upd(struct ifnet *); 137static void my_ifmedia_sts(struct ifnet *, struct ifmediareq *); 138static u_int16_t my_phy_readreg(struct my_softc *, int); 139static void my_phy_writereg(struct my_softc *, int, int); 140static void my_autoneg_xmit(struct my_softc *); 141static void my_autoneg_mii(struct my_softc *, int, int); 142static void my_setmode_mii(struct my_softc *, int); 143static void my_getmode_mii(struct my_softc *); 144static void my_setcfg(struct my_softc *, int); 145static uint32_t my_mchash(const uint8_t *); 146static void my_setmulti(struct my_softc *); 147static void my_reset(struct my_softc *); 148static int my_list_rx_init(struct my_softc *); 149static int my_list_tx_init(struct my_softc *); 150static long my_send_cmd_to_phy(struct my_softc *, int, int); 151 152#define MY_SETBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 153#define MY_CLRBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 154 155static device_method_t my_methods[] = { 156 /* Device interface */ 157 DEVMETHOD(device_probe, my_probe), 158 DEVMETHOD(device_attach, my_attach), 159 DEVMETHOD(device_detach, my_detach), 160 DEVMETHOD(device_shutdown, my_shutdown), 161 162 {0, 0} 163}; 164 165static driver_t my_driver = { 166 "my", 167 my_methods, 168 sizeof(struct my_softc) 169}; 170 171static devclass_t my_devclass; 172 173DRIVER_MODULE(my, pci, my_driver, my_devclass, 0, 0); 174MODULE_DEPEND(my, pci, 1, 1, 1); 175MODULE_DEPEND(my, ether, 1, 1, 1); 176 177static long 178my_send_cmd_to_phy(struct my_softc * sc, int opcode, int regad) 179{ 180 long miir; 181 int i; 182 int mask, data; 183 184 MY_LOCK(sc); 185 186 /* enable MII output */ 187 miir = CSR_READ_4(sc, MY_MANAGEMENT); 188 miir &= 0xfffffff0; 189 190 miir |= MY_MASK_MIIR_MII_WRITE + MY_MASK_MIIR_MII_MDO; 191 192 /* send 32 1's preamble */ 193 for (i = 0; i < 32; i++) { 194 /* low MDC; MDO is already high (miir) */ 195 miir &= ~MY_MASK_MIIR_MII_MDC; 196 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 197 198 /* high MDC */ 199 miir |= MY_MASK_MIIR_MII_MDC; 200 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 201 } 202 203 /* calculate ST+OP+PHYAD+REGAD+TA */ 204 data = opcode | (sc->my_phy_addr << 7) | (regad << 2); 205 206 /* sent out */ 207 mask = 0x8000; 208 while (mask) { 209 /* low MDC, prepare MDO */ 210 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO); 211 if (mask & data) 212 miir |= MY_MASK_MIIR_MII_MDO; 213 214 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 215 /* high MDC */ 216 miir |= MY_MASK_MIIR_MII_MDC; 217 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 218 DELAY(30); 219 220 /* next */ 221 mask >>= 1; 222 if (mask == 0x2 && opcode == MY_OP_READ) 223 miir &= ~MY_MASK_MIIR_MII_WRITE; 224 } 225 226 MY_UNLOCK(sc); 227 return miir; 228} 229 230 231static u_int16_t 232my_phy_readreg(struct my_softc * sc, int reg) 233{ 234 long miir; 235 int mask, data; 236 237 MY_LOCK(sc); 238 239 if (sc->my_info->my_did == MTD803ID) 240 data = CSR_READ_2(sc, MY_PHYBASE + reg * 2); 241 else { 242 miir = my_send_cmd_to_phy(sc, MY_OP_READ, reg); 243 244 /* read data */ 245 mask = 0x8000; 246 data = 0; 247 while (mask) { 248 /* low MDC */ 249 miir &= ~MY_MASK_MIIR_MII_MDC; 250 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 251 252 /* read MDI */ 253 miir = CSR_READ_4(sc, MY_MANAGEMENT); 254 if (miir & MY_MASK_MIIR_MII_MDI) 255 data |= mask; 256 257 /* high MDC, and wait */ 258 miir |= MY_MASK_MIIR_MII_MDC; 259 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 260 DELAY(30); 261 262 /* next */ 263 mask >>= 1; 264 } 265 266 /* low MDC */ 267 miir &= ~MY_MASK_MIIR_MII_MDC; 268 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 269 } 270 271 MY_UNLOCK(sc); 272 return (u_int16_t) data; 273} 274 275 276static void 277my_phy_writereg(struct my_softc * sc, int reg, int data) 278{ 279 long miir; 280 int mask; 281 282 MY_LOCK(sc); 283 284 if (sc->my_info->my_did == MTD803ID) 285 CSR_WRITE_2(sc, MY_PHYBASE + reg * 2, data); 286 else { 287 miir = my_send_cmd_to_phy(sc, MY_OP_WRITE, reg); 288 289 /* write data */ 290 mask = 0x8000; 291 while (mask) { 292 /* low MDC, prepare MDO */ 293 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO); 294 if (mask & data) 295 miir |= MY_MASK_MIIR_MII_MDO; 296 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 297 DELAY(1); 298 299 /* high MDC */ 300 miir |= MY_MASK_MIIR_MII_MDC; 301 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 302 DELAY(1); 303 304 /* next */ 305 mask >>= 1; 306 } 307 308 /* low MDC */ 309 miir &= ~MY_MASK_MIIR_MII_MDC; 310 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 311 } 312 MY_UNLOCK(sc); 313 return; 314} 315 316static uint32_t 317my_mchash(const uint8_t *addr) 318{ 319 uint32_t crc, carry; 320 int idx, bit; 321 uint8_t data; 322 323 /* Compute CRC for the address value. */ 324 crc = 0xFFFFFFFF; /* initial value */ 325 326 for (idx = 0; idx < 6; idx++) { 327 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) { 328 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01); 329 crc <<= 1; 330 if (carry) 331 crc = (crc ^ 0x04c11db6) | carry; 332 } 333 } 334 335 /* 336 * return the filter bit position Note: I arrived at the following 337 * nonsense through experimentation. It's not the usual way to 338 * generate the bit position but it's the only thing I could come up 339 * with that works. 340 */ 341 return (~(crc >> 26) & 0x0000003F); 342} 343 344 345/* 346 * Program the 64-bit multicast hash filter. 347 */ 348static void 349my_setmulti(struct my_softc * sc) 350{ 351 struct ifnet *ifp; 352 int h = 0; 353 u_int32_t hashes[2] = {0, 0}; 354 struct ifmultiaddr *ifma; 355 u_int32_t rxfilt; 356 int mcnt = 0; 357 358 MY_LOCK(sc); 359 360 ifp = &sc->arpcom.ac_if; 361 362 rxfilt = CSR_READ_4(sc, MY_TCRRCR); 363 364 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 365 rxfilt |= MY_AM; 366 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt); 367 CSR_WRITE_4(sc, MY_MAR0, 0xFFFFFFFF); 368 CSR_WRITE_4(sc, MY_MAR1, 0xFFFFFFFF); 369 370 MY_UNLOCK(sc); 371 372 return; 373 } 374 /* first, zot all the existing hash bits */ 375 CSR_WRITE_4(sc, MY_MAR0, 0); 376 CSR_WRITE_4(sc, MY_MAR1, 0); 377 378 /* now program new ones */ 379 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 380 if (ifma->ifma_addr->sa_family != AF_LINK) 381 continue; 382 h = my_mchash(LLADDR((struct sockaddr_dl *) ifma->ifma_addr)); 383 if (h < 32) 384 hashes[0] |= (1 << h); 385 else 386 hashes[1] |= (1 << (h - 32)); 387 mcnt++; 388 } 389 390 if (mcnt) 391 rxfilt |= MY_AM; 392 else 393 rxfilt &= ~MY_AM; 394 CSR_WRITE_4(sc, MY_MAR0, hashes[0]); 395 CSR_WRITE_4(sc, MY_MAR1, hashes[1]); 396 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt); 397 MY_UNLOCK(sc); 398 return; 399} 400 401/* 402 * Initiate an autonegotiation session. 403 */ 404static void 405my_autoneg_xmit(struct my_softc * sc) 406{ 407 u_int16_t phy_sts = 0; 408 409 MY_LOCK(sc); 410 411 my_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); 412 DELAY(500); 413 while (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_RESET); 414 415 phy_sts = my_phy_readreg(sc, PHY_BMCR); 416 phy_sts |= PHY_BMCR_AUTONEGENBL | PHY_BMCR_AUTONEGRSTR; 417 my_phy_writereg(sc, PHY_BMCR, phy_sts); 418 419 MY_UNLOCK(sc); 420 return; 421} 422 423 424/* 425 * Invoke autonegotiation on a PHY. 426 */ 427static void 428my_autoneg_mii(struct my_softc * sc, int flag, int verbose) 429{ 430 u_int16_t phy_sts = 0, media, advert, ability; 431 u_int16_t ability2 = 0; 432 struct ifnet *ifp; 433 struct ifmedia *ifm; 434 435 MY_LOCK(sc); 436 437 ifm = &sc->ifmedia; 438 ifp = &sc->arpcom.ac_if; 439 440 ifm->ifm_media = IFM_ETHER | IFM_AUTO; 441 442#ifndef FORCE_AUTONEG_TFOUR 443 /* 444 * First, see if autoneg is supported. If not, there's no point in 445 * continuing. 446 */ 447 phy_sts = my_phy_readreg(sc, PHY_BMSR); 448 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) { 449 if (verbose) 450 printf("my%d: autonegotiation not supported\n", 451 sc->my_unit); 452 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 453 MY_UNLOCK(sc); 454 return; 455 } 456#endif 457 switch (flag) { 458 case MY_FLAG_FORCEDELAY: 459 /* 460 * XXX Never use this option anywhere but in the probe 461 * routine: making the kernel stop dead in its tracks for 462 * three whole seconds after we've gone multi-user is really 463 * bad manners. 464 */ 465 my_autoneg_xmit(sc); 466 DELAY(5000000); 467 break; 468 case MY_FLAG_SCHEDDELAY: 469 /* 470 * Wait for the transmitter to go idle before starting an 471 * autoneg session, otherwise my_start() may clobber our 472 * timeout, and we don't want to allow transmission during an 473 * autoneg session since that can screw it up. 474 */ 475 if (sc->my_cdata.my_tx_head != NULL) { 476 sc->my_want_auto = 1; 477 MY_UNLOCK(sc); 478 return; 479 } 480 my_autoneg_xmit(sc); 481 ifp->if_timer = 5; 482 sc->my_autoneg = 1; 483 sc->my_want_auto = 0; 484 MY_UNLOCK(sc); 485 return; 486 case MY_FLAG_DELAYTIMEO: 487 ifp->if_timer = 0; 488 sc->my_autoneg = 0; 489 break; 490 default: 491 printf("my%d: invalid autoneg flag: %d\n", sc->my_unit, flag); 492 MY_UNLOCK(sc); 493 return; 494 } 495 496 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) { 497 if (verbose) 498 printf("my%d: autoneg complete, ", sc->my_unit); 499 phy_sts = my_phy_readreg(sc, PHY_BMSR); 500 } else { 501 if (verbose) 502 printf("my%d: autoneg not complete, ", sc->my_unit); 503 } 504 505 media = my_phy_readreg(sc, PHY_BMCR); 506 507 /* Link is good. Report modes and set duplex mode. */ 508 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) { 509 if (verbose) 510 printf("my%d: link status good. ", sc->my_unit); 511 advert = my_phy_readreg(sc, PHY_ANAR); 512 ability = my_phy_readreg(sc, PHY_LPAR); 513 if ((sc->my_pinfo->my_vid == MarvellPHYID0) || 514 (sc->my_pinfo->my_vid == LevelOnePHYID0)) { 515 ability2 = my_phy_readreg(sc, PHY_1000SR); 516 if (ability2 & PHY_1000SR_1000BTXFULL) { 517 advert = 0; 518 ability = 0; 519 /* 520 * this version did not support 1000M, 521 * ifm->ifm_media = 522 * IFM_ETHER|IFM_1000_T|IFM_FDX; 523 */ 524 ifm->ifm_media = 525 IFM_ETHER | IFM_100_TX | IFM_FDX; 526 media &= ~PHY_BMCR_SPEEDSEL; 527 media |= PHY_BMCR_1000; 528 media |= PHY_BMCR_DUPLEX; 529 printf("(full-duplex, 1000Mbps)\n"); 530 } else if (ability2 & PHY_1000SR_1000BTXHALF) { 531 advert = 0; 532 ability = 0; 533 /* 534 * this version did not support 1000M, 535 * ifm->ifm_media = IFM_ETHER|IFM_1000_T; 536 */ 537 ifm->ifm_media = IFM_ETHER | IFM_100_TX; 538 media &= ~PHY_BMCR_SPEEDSEL; 539 media &= ~PHY_BMCR_DUPLEX; 540 media |= PHY_BMCR_1000; 541 printf("(half-duplex, 1000Mbps)\n"); 542 } 543 } 544 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) { 545 ifm->ifm_media = IFM_ETHER | IFM_100_T4; 546 media |= PHY_BMCR_SPEEDSEL; 547 media &= ~PHY_BMCR_DUPLEX; 548 printf("(100baseT4)\n"); 549 } else if (advert & PHY_ANAR_100BTXFULL && 550 ability & PHY_ANAR_100BTXFULL) { 551 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX; 552 media |= PHY_BMCR_SPEEDSEL; 553 media |= PHY_BMCR_DUPLEX; 554 printf("(full-duplex, 100Mbps)\n"); 555 } else if (advert & PHY_ANAR_100BTXHALF && 556 ability & PHY_ANAR_100BTXHALF) { 557 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX; 558 media |= PHY_BMCR_SPEEDSEL; 559 media &= ~PHY_BMCR_DUPLEX; 560 printf("(half-duplex, 100Mbps)\n"); 561 } else if (advert & PHY_ANAR_10BTFULL && 562 ability & PHY_ANAR_10BTFULL) { 563 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX; 564 media &= ~PHY_BMCR_SPEEDSEL; 565 media |= PHY_BMCR_DUPLEX; 566 printf("(full-duplex, 10Mbps)\n"); 567 } else if (advert) { 568 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 569 media &= ~PHY_BMCR_SPEEDSEL; 570 media &= ~PHY_BMCR_DUPLEX; 571 printf("(half-duplex, 10Mbps)\n"); 572 } 573 media &= ~PHY_BMCR_AUTONEGENBL; 574 575 /* Set ASIC's duplex mode to match the PHY. */ 576 my_phy_writereg(sc, PHY_BMCR, media); 577 my_setcfg(sc, media); 578 } else { 579 if (verbose) 580 printf("my%d: no carrier\n", sc->my_unit); 581 } 582 583 my_init(sc); 584 if (sc->my_tx_pend) { 585 sc->my_autoneg = 0; 586 sc->my_tx_pend = 0; 587 my_start(ifp); 588 } 589 MY_UNLOCK(sc); 590 return; 591} 592 593/* 594 * To get PHY ability. 595 */ 596static void 597my_getmode_mii(struct my_softc * sc) 598{ 599 u_int16_t bmsr; 600 struct ifnet *ifp; 601 602 MY_LOCK(sc); 603 ifp = &sc->arpcom.ac_if; 604 bmsr = my_phy_readreg(sc, PHY_BMSR); 605 if (bootverbose) 606 printf("my%d: PHY status word: %x\n", sc->my_unit, bmsr); 607 608 /* fallback */ 609 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 610 611 if (bmsr & PHY_BMSR_10BTHALF) { 612 if (bootverbose) 613 printf("my%d: 10Mbps half-duplex mode supported\n", 614 sc->my_unit); 615 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_HDX, 616 0, NULL); 617 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T, 0, NULL); 618 } 619 if (bmsr & PHY_BMSR_10BTFULL) { 620 if (bootverbose) 621 printf("my%d: 10Mbps full-duplex mode supported\n", 622 sc->my_unit); 623 624 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 625 0, NULL); 626 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX; 627 } 628 if (bmsr & PHY_BMSR_100BTXHALF) { 629 if (bootverbose) 630 printf("my%d: 100Mbps half-duplex mode supported\n", 631 sc->my_unit); 632 ifp->if_baudrate = 100000000; 633 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL); 634 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_HDX, 635 0, NULL); 636 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX; 637 } 638 if (bmsr & PHY_BMSR_100BTXFULL) { 639 if (bootverbose) 640 printf("my%d: 100Mbps full-duplex mode supported\n", 641 sc->my_unit); 642 ifp->if_baudrate = 100000000; 643 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 644 0, NULL); 645 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX; 646 } 647 /* Some also support 100BaseT4. */ 648 if (bmsr & PHY_BMSR_100BT4) { 649 if (bootverbose) 650 printf("my%d: 100baseT4 mode supported\n", sc->my_unit); 651 ifp->if_baudrate = 100000000; 652 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_T4, 0, NULL); 653 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_T4; 654#ifdef FORCE_AUTONEG_TFOUR 655 if (bootverbose) 656 printf("my%d: forcing on autoneg support for BT4\n", 657 sc->my_unit); 658 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0 NULL): 659 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO; 660#endif 661 } 662#if 0 /* this version did not support 1000M, */ 663 if (sc->my_pinfo->my_vid == MarvellPHYID0) { 664 if (bootverbose) 665 printf("my%d: 1000Mbps half-duplex mode supported\n", 666 sc->my_unit); 667 668 ifp->if_baudrate = 1000000000; 669 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL); 670 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_HDX, 671 0, NULL); 672 if (bootverbose) 673 printf("my%d: 1000Mbps full-duplex mode supported\n", 674 sc->my_unit); 675 ifp->if_baudrate = 1000000000; 676 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX, 677 0, NULL); 678 sc->ifmedia.ifm_media = IFM_ETHER | IFM_1000_T | IFM_FDX; 679 } 680#endif 681 if (bmsr & PHY_BMSR_CANAUTONEG) { 682 if (bootverbose) 683 printf("my%d: autoneg supported\n", sc->my_unit); 684 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 685 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO; 686 } 687 MY_UNLOCK(sc); 688 return; 689} 690 691/* 692 * Set speed and duplex mode. 693 */ 694static void 695my_setmode_mii(struct my_softc * sc, int media) 696{ 697 u_int16_t bmcr; 698 struct ifnet *ifp; 699 700 MY_LOCK(sc); 701 ifp = &sc->arpcom.ac_if; 702 /* 703 * If an autoneg session is in progress, stop it. 704 */ 705 if (sc->my_autoneg) { 706 printf("my%d: canceling autoneg session\n", sc->my_unit); 707 ifp->if_timer = sc->my_autoneg = sc->my_want_auto = 0; 708 bmcr = my_phy_readreg(sc, PHY_BMCR); 709 bmcr &= ~PHY_BMCR_AUTONEGENBL; 710 my_phy_writereg(sc, PHY_BMCR, bmcr); 711 } 712 printf("my%d: selecting MII, ", sc->my_unit); 713 bmcr = my_phy_readreg(sc, PHY_BMCR); 714 bmcr &= ~(PHY_BMCR_AUTONEGENBL | PHY_BMCR_SPEEDSEL | PHY_BMCR_1000 | 715 PHY_BMCR_DUPLEX | PHY_BMCR_LOOPBK); 716 717#if 0 /* this version did not support 1000M, */ 718 if (IFM_SUBTYPE(media) == IFM_1000_T) { 719 printf("1000Mbps/T4, half-duplex\n"); 720 bmcr &= ~PHY_BMCR_SPEEDSEL; 721 bmcr &= ~PHY_BMCR_DUPLEX; 722 bmcr |= PHY_BMCR_1000; 723 } 724#endif 725 if (IFM_SUBTYPE(media) == IFM_100_T4) { 726 printf("100Mbps/T4, half-duplex\n"); 727 bmcr |= PHY_BMCR_SPEEDSEL; 728 bmcr &= ~PHY_BMCR_DUPLEX; 729 } 730 if (IFM_SUBTYPE(media) == IFM_100_TX) { 731 printf("100Mbps, "); 732 bmcr |= PHY_BMCR_SPEEDSEL; 733 } 734 if (IFM_SUBTYPE(media) == IFM_10_T) { 735 printf("10Mbps, "); 736 bmcr &= ~PHY_BMCR_SPEEDSEL; 737 } 738 if ((media & IFM_GMASK) == IFM_FDX) { 739 printf("full duplex\n"); 740 bmcr |= PHY_BMCR_DUPLEX; 741 } else { 742 printf("half duplex\n"); 743 bmcr &= ~PHY_BMCR_DUPLEX; 744 } 745 my_phy_writereg(sc, PHY_BMCR, bmcr); 746 my_setcfg(sc, bmcr); 747 MY_UNLOCK(sc); 748 return; 749} 750 751/* 752 * The Myson manual states that in order to fiddle with the 'full-duplex' and 753 * '100Mbps' bits in the netconfig register, we first have to put the 754 * transmit and/or receive logic in the idle state. 755 */ 756static void 757my_setcfg(struct my_softc * sc, int bmcr) 758{ 759 int i, restart = 0; 760 761 MY_LOCK(sc); 762 if (CSR_READ_4(sc, MY_TCRRCR) & (MY_TE | MY_RE)) { 763 restart = 1; 764 MY_CLRBIT(sc, MY_TCRRCR, (MY_TE | MY_RE)); 765 for (i = 0; i < MY_TIMEOUT; i++) { 766 DELAY(10); 767 if (!(CSR_READ_4(sc, MY_TCRRCR) & 768 (MY_TXRUN | MY_RXRUN))) 769 break; 770 } 771 if (i == MY_TIMEOUT) 772 printf("my%d: failed to force tx and rx to idle \n", 773 sc->my_unit); 774 } 775 MY_CLRBIT(sc, MY_TCRRCR, MY_PS1000); 776 MY_CLRBIT(sc, MY_TCRRCR, MY_PS10); 777 if (bmcr & PHY_BMCR_1000) 778 MY_SETBIT(sc, MY_TCRRCR, MY_PS1000); 779 else if (!(bmcr & PHY_BMCR_SPEEDSEL)) 780 MY_SETBIT(sc, MY_TCRRCR, MY_PS10); 781 if (bmcr & PHY_BMCR_DUPLEX) 782 MY_SETBIT(sc, MY_TCRRCR, MY_FD); 783 else 784 MY_CLRBIT(sc, MY_TCRRCR, MY_FD); 785 if (restart) 786 MY_SETBIT(sc, MY_TCRRCR, MY_TE | MY_RE); 787 MY_UNLOCK(sc); 788 return; 789} 790 791static void 792my_reset(struct my_softc * sc) 793{ 794 register int i; 795 796 MY_LOCK(sc); 797 MY_SETBIT(sc, MY_BCR, MY_SWR); 798 for (i = 0; i < MY_TIMEOUT; i++) { 799 DELAY(10); 800 if (!(CSR_READ_4(sc, MY_BCR) & MY_SWR)) 801 break; 802 } 803 if (i == MY_TIMEOUT) 804 printf("m0x%d: reset never completed!\n", sc->my_unit); 805 806 /* Wait a little while for the chip to get its brains in order. */ 807 DELAY(1000); 808 MY_UNLOCK(sc); 809 return; 810} 811 812/* 813 * Probe for a Myson chip. Check the PCI vendor and device IDs against our 814 * list and return a device name if we find a match. 815 */ 816static int 817my_probe(device_t dev) 818{ 819 struct my_type *t; 820 821 t = my_devs; 822 while (t->my_name != NULL) { 823 if ((pci_get_vendor(dev) == t->my_vid) && 824 (pci_get_device(dev) == t->my_did)) { 825 device_set_desc(dev, t->my_name); 826 my_info_tmp = t; 827 return (0); 828 } 829 t++; 830 } 831 return (ENXIO); 832} 833 834/* 835 * Attach the interface. Allocate softc structures, do ifmedia setup and 836 * ethernet/BPF attach. 837 */ 838static int 839my_attach(device_t dev) 840{ 841 int s, i; 842 u_char eaddr[ETHER_ADDR_LEN]; 843 u_int32_t command, iobase; 844 struct my_softc *sc; 845 struct ifnet *ifp; 846 int media = IFM_ETHER | IFM_100_TX | IFM_FDX; 847 unsigned int round; 848 caddr_t roundptr; 849 struct my_type *p; 850 u_int16_t phy_vid, phy_did, phy_sts = 0; 851 int rid, unit, error = 0; 852 853 s = splimp(); 854 sc = device_get_softc(dev); 855 unit = device_get_unit(dev); 856 if (sc == NULL) { 857 printf("my%d: no memory for softc struct!\n", unit); 858 error = ENXIO; 859 goto fail; 860 861 } 862 bzero(sc, sizeof(struct my_softc)); 863 mtx_init(&sc->my_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 864 MTX_DEF | MTX_RECURSE); 865 MY_LOCK(sc); 866 867 /* 868 * Map control/status registers. 869 */ 870#if 0 871 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 872 command |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 873 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command & 0x000000ff, 4); 874 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 875#endif 876 command = pci_read_config(dev, PCIR_COMMAND, 4); 877 command |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 878 pci_write_config(dev, PCIR_COMMAND, command & 0x000000ff, 4); 879 command = pci_read_config(dev, PCIR_COMMAND, 4); 880 881 if (my_info_tmp->my_did == MTD800ID) { 882 iobase = pci_read_config(dev, MY_PCI_LOIO, 4); 883 if (iobase & 0x300) 884 MY_USEIOSPACE = 0; 885 } 886 if (MY_USEIOSPACE) { 887 if (!(command & PCIM_CMD_PORTEN)) { 888 printf("my%d: failed to enable I/O ports!\n", unit); 889 free(sc, M_DEVBUF); 890 error = ENXIO; 891 goto fail; 892 } 893#if 0 894 if (!pci_map_port(config_id, MY_PCI_LOIO, (u_int16_t *) & (sc->my_bhandle))) { 895 printf("my%d: couldn't map ports\n", unit); 896 error = ENXIO; 897 goto fail; 898 } 899 900 sc->my_btag = I386_BUS_SPACE_IO; 901#endif 902 } else { 903 if (!(command & PCIM_CMD_MEMEN)) { 904 printf("my%d: failed to enable memory mapping!\n", 905 unit); 906 error = ENXIO; 907 goto fail; 908 } 909#if 0 910 if (!pci_map_mem(config_id, MY_PCI_LOMEM, &vbase, &pbase)) { 911 printf ("my%d: couldn't map memory\n", unit); 912 error = ENXIO; 913 goto fail; 914 } 915 sc->my_btag = I386_BUS_SPACE_MEM; 916 sc->my_bhandle = vbase; 917#endif 918 } 919 920 rid = MY_RID; 921 sc->my_res = bus_alloc_resource_any(dev, MY_RES, &rid, RF_ACTIVE); 922 923 if (sc->my_res == NULL) { 924 printf("my%d: couldn't map ports/memory\n", unit); 925 error = ENXIO; 926 goto fail; 927 } 928 sc->my_btag = rman_get_bustag(sc->my_res); 929 sc->my_bhandle = rman_get_bushandle(sc->my_res); 930 931 rid = 0; 932 sc->my_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 933 RF_SHAREABLE | RF_ACTIVE); 934 935 if (sc->my_irq == NULL) { 936 printf("my%d: couldn't map interrupt\n", unit); 937 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res); 938 error = ENXIO; 939 goto fail; 940 } 941 error = bus_setup_intr(dev, sc->my_irq, INTR_TYPE_NET, 942 my_intr, sc, &sc->my_intrhand); 943 944 if (error) { 945 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq); 946 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res); 947 printf("my%d: couldn't set up irq\n", unit); 948 goto fail; 949 } 950 callout_handle_init(&sc->my_stat_ch); 951 952 sc->my_info = my_info_tmp; 953 954 /* Reset the adapter. */ 955 my_reset(sc); 956 957 /* 958 * Get station address 959 */ 960 for (i = 0; i < ETHER_ADDR_LEN; ++i) 961 eaddr[i] = CSR_READ_1(sc, MY_PAR0 + i); 962 963 sc->my_unit = unit; 964 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 965 966 sc->my_ldata_ptr = malloc(sizeof(struct my_list_data) + 8, 967 M_DEVBUF, M_NOWAIT); 968 if (sc->my_ldata_ptr == NULL) { 969 free(sc, M_DEVBUF); 970 printf("my%d: no memory for list buffers!\n", unit); 971 error = ENXIO; 972 goto fail; 973 } 974 sc->my_ldata = (struct my_list_data *) sc->my_ldata_ptr; 975 round = (uintptr_t)sc->my_ldata_ptr & 0xF; 976 roundptr = sc->my_ldata_ptr; 977 for (i = 0; i < 8; i++) { 978 if (round % 8) { 979 round++; 980 roundptr++; 981 } else 982 break; 983 } 984 sc->my_ldata = (struct my_list_data *) roundptr; 985 bzero(sc->my_ldata, sizeof(struct my_list_data)); 986 987 ifp = &sc->arpcom.ac_if; 988 ifp->if_softc = sc; 989 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 990 ifp->if_mtu = ETHERMTU; 991 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 992 ifp->if_ioctl = my_ioctl; 993 ifp->if_output = ether_output; 994 ifp->if_start = my_start; 995 ifp->if_watchdog = my_watchdog; 996 ifp->if_init = my_init; 997 ifp->if_baudrate = 10000000; 998 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 999 1000 if (sc->my_info->my_did == MTD803ID) 1001 sc->my_pinfo = my_phys; 1002 else { 1003 if (bootverbose) 1004 printf("my%d: probing for a PHY\n", sc->my_unit); 1005 for (i = MY_PHYADDR_MIN; i < MY_PHYADDR_MAX + 1; i++) { 1006 if (bootverbose) 1007 printf("my%d: checking address: %d\n", 1008 sc->my_unit, i); 1009 sc->my_phy_addr = i; 1010 phy_sts = my_phy_readreg(sc, PHY_BMSR); 1011 if ((phy_sts != 0) && (phy_sts != 0xffff)) 1012 break; 1013 else 1014 phy_sts = 0; 1015 } 1016 if (phy_sts) { 1017 phy_vid = my_phy_readreg(sc, PHY_VENID); 1018 phy_did = my_phy_readreg(sc, PHY_DEVID); 1019 if (bootverbose) { 1020 printf("my%d: found PHY at address %d, ", 1021 sc->my_unit, sc->my_phy_addr); 1022 printf("vendor id: %x device id: %x\n", 1023 phy_vid, phy_did); 1024 } 1025 p = my_phys; 1026 while (p->my_vid) { 1027 if (phy_vid == p->my_vid) { 1028 sc->my_pinfo = p; 1029 break; 1030 } 1031 p++; 1032 } 1033 if (sc->my_pinfo == NULL) 1034 sc->my_pinfo = &my_phys[PHY_UNKNOWN]; 1035 if (bootverbose) 1036 printf("my%d: PHY type: %s\n", 1037 sc->my_unit, sc->my_pinfo->my_name); 1038 } else { 1039 printf("my%d: MII without any phy!\n", sc->my_unit); 1040 error = ENXIO; 1041 goto fail; 1042 } 1043 } 1044 1045 /* Do ifmedia setup. */ 1046 ifmedia_init(&sc->ifmedia, 0, my_ifmedia_upd, my_ifmedia_sts); 1047 my_getmode_mii(sc); 1048 my_autoneg_mii(sc, MY_FLAG_FORCEDELAY, 1); 1049 media = sc->ifmedia.ifm_media; 1050 my_stop(sc); 1051 ifmedia_set(&sc->ifmedia, media); 1052 1053 ether_ifattach(ifp, eaddr); 1054 1055#if 0 1056 at_shutdown(my_shutdown, sc, SHUTDOWN_POST_SYNC); 1057 shutdownhook_establish(my_shutdown, sc); 1058#endif 1059 1060 MY_UNLOCK(sc); 1061 return (0); 1062 1063fail: 1064 MY_UNLOCK(sc); 1065 mtx_destroy(&sc->my_mtx); 1066 splx(s); 1067 return (error); 1068} 1069 1070static int 1071my_detach(device_t dev) 1072{ 1073 struct my_softc *sc; 1074 struct ifnet *ifp; 1075 int s; 1076 1077 s = splimp(); 1078 sc = device_get_softc(dev); 1079 MY_LOCK(sc); 1080 ifp = &sc->arpcom.ac_if; 1081 ether_ifdetach(ifp); 1082 my_stop(sc); 1083 1084#if 0 1085 bus_generic_detach(dev); 1086 device_delete_child(dev, sc->rl_miibus); 1087#endif 1088 1089 bus_teardown_intr(dev, sc->my_irq, sc->my_intrhand); 1090 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq); 1091 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res); 1092#if 0 1093 contigfree(sc->my_cdata.my_rx_buf, MY_RXBUFLEN + 32, M_DEVBUF); 1094#endif 1095 free(sc, M_DEVBUF); 1096 MY_UNLOCK(sc); 1097 splx(s); 1098 mtx_destroy(&sc->my_mtx); 1099 return (0); 1100} 1101 1102 1103/* 1104 * Initialize the transmit descriptors. 1105 */ 1106static int 1107my_list_tx_init(struct my_softc * sc) 1108{ 1109 struct my_chain_data *cd; 1110 struct my_list_data *ld; 1111 int i; 1112 1113 MY_LOCK(sc); 1114 cd = &sc->my_cdata; 1115 ld = sc->my_ldata; 1116 for (i = 0; i < MY_TX_LIST_CNT; i++) { 1117 cd->my_tx_chain[i].my_ptr = &ld->my_tx_list[i]; 1118 if (i == (MY_TX_LIST_CNT - 1)) 1119 cd->my_tx_chain[i].my_nextdesc = &cd->my_tx_chain[0]; 1120 else 1121 cd->my_tx_chain[i].my_nextdesc = 1122 &cd->my_tx_chain[i + 1]; 1123 } 1124 cd->my_tx_free = &cd->my_tx_chain[0]; 1125 cd->my_tx_tail = cd->my_tx_head = NULL; 1126 MY_UNLOCK(sc); 1127 return (0); 1128} 1129 1130/* 1131 * Initialize the RX descriptors and allocate mbufs for them. Note that we 1132 * arrange the descriptors in a closed ring, so that the last descriptor 1133 * points back to the first. 1134 */ 1135static int 1136my_list_rx_init(struct my_softc * sc) 1137{ 1138 struct my_chain_data *cd; 1139 struct my_list_data *ld; 1140 int i; 1141 1142 MY_LOCK(sc); 1143 cd = &sc->my_cdata; 1144 ld = sc->my_ldata; 1145 for (i = 0; i < MY_RX_LIST_CNT; i++) { 1146 cd->my_rx_chain[i].my_ptr = 1147 (struct my_desc *) & ld->my_rx_list[i]; 1148 if (my_newbuf(sc, &cd->my_rx_chain[i]) == ENOBUFS) { 1149 MY_UNLOCK(sc); 1150 return (ENOBUFS); 1151 } 1152 if (i == (MY_RX_LIST_CNT - 1)) { 1153 cd->my_rx_chain[i].my_nextdesc = &cd->my_rx_chain[0]; 1154 ld->my_rx_list[i].my_next = vtophys(&ld->my_rx_list[0]); 1155 } else { 1156 cd->my_rx_chain[i].my_nextdesc = 1157 &cd->my_rx_chain[i + 1]; 1158 ld->my_rx_list[i].my_next = 1159 vtophys(&ld->my_rx_list[i + 1]); 1160 } 1161 } 1162 cd->my_rx_head = &cd->my_rx_chain[0]; 1163 MY_UNLOCK(sc); 1164 return (0); 1165} 1166 1167/* 1168 * Initialize an RX descriptor and attach an MBUF cluster. 1169 */ 1170static int 1171my_newbuf(struct my_softc * sc, struct my_chain_onefrag * c) 1172{ 1173 struct mbuf *m_new = NULL; 1174 1175 MY_LOCK(sc); 1176 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1177 if (m_new == NULL) { 1178 printf("my%d: no memory for rx list -- packet dropped!\n", 1179 sc->my_unit); 1180 MY_UNLOCK(sc); 1181 return (ENOBUFS); 1182 } 1183 MCLGET(m_new, M_DONTWAIT); 1184 if (!(m_new->m_flags & M_EXT)) { 1185 printf("my%d: no memory for rx list -- packet dropped!\n", 1186 sc->my_unit); 1187 m_freem(m_new); 1188 MY_UNLOCK(sc); 1189 return (ENOBUFS); 1190 } 1191 c->my_mbuf = m_new; 1192 c->my_ptr->my_data = vtophys(mtod(m_new, caddr_t)); 1193 c->my_ptr->my_ctl = (MCLBYTES - 1) << MY_RBSShift; 1194 c->my_ptr->my_status = MY_OWNByNIC; 1195 MY_UNLOCK(sc); 1196 return (0); 1197} 1198 1199/* 1200 * A frame has been uploaded: pass the resulting mbuf chain up to the higher 1201 * level protocols. 1202 */ 1203static void 1204my_rxeof(struct my_softc * sc) 1205{ 1206 struct ether_header *eh; 1207 struct mbuf *m; 1208 struct ifnet *ifp; 1209 struct my_chain_onefrag *cur_rx; 1210 int total_len = 0; 1211 u_int32_t rxstat; 1212 1213 MY_LOCK(sc); 1214 ifp = &sc->arpcom.ac_if; 1215 while (!((rxstat = sc->my_cdata.my_rx_head->my_ptr->my_status) 1216 & MY_OWNByNIC)) { 1217 cur_rx = sc->my_cdata.my_rx_head; 1218 sc->my_cdata.my_rx_head = cur_rx->my_nextdesc; 1219 1220 if (rxstat & MY_ES) { /* error summary: give up this rx pkt */ 1221 ifp->if_ierrors++; 1222 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1223 continue; 1224 } 1225 /* No errors; receive the packet. */ 1226 total_len = (rxstat & MY_FLNGMASK) >> MY_FLNGShift; 1227 total_len -= ETHER_CRC_LEN; 1228 1229 if (total_len < MINCLSIZE) { 1230 m = m_devget(mtod(cur_rx->my_mbuf, char *), 1231 total_len, 0, ifp, NULL); 1232 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1233 if (m == NULL) { 1234 ifp->if_ierrors++; 1235 continue; 1236 } 1237 } else { 1238 m = cur_rx->my_mbuf; 1239 /* 1240 * Try to conjure up a new mbuf cluster. If that 1241 * fails, it means we have an out of memory condition 1242 * and should leave the buffer in place and continue. 1243 * This will result in a lost packet, but there's 1244 * little else we can do in this situation. 1245 */ 1246 if (my_newbuf(sc, cur_rx) == ENOBUFS) { 1247 ifp->if_ierrors++; 1248 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1249 continue; 1250 } 1251 m->m_pkthdr.rcvif = ifp; 1252 m->m_pkthdr.len = m->m_len = total_len; 1253 } 1254 ifp->if_ipackets++; 1255 eh = mtod(m, struct ether_header *); 1256#if NBPFILTER > 0 1257 /* 1258 * Handle BPF listeners. Let the BPF user see the packet, but 1259 * don't pass it up to the ether_input() layer unless it's a 1260 * broadcast packet, multicast packet, matches our ethernet 1261 * address or the interface is in promiscuous mode. 1262 */ 1263 if (ifp->if_bpf) { 1264 BPF_MTAP(ifp, m); 1265 if (ifp->if_flags & IFF_PROMISC && 1266 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 1267 ETHER_ADDR_LEN) && 1268 (eh->ether_dhost[0] & 1) == 0)) { 1269 m_freem(m); 1270 continue; 1271 } 1272 } 1273#endif 1274 MY_UNLOCK(sc); 1275 (*ifp->if_input)(ifp, m); 1276 MY_LOCK(sc); 1277 } 1278 MY_UNLOCK(sc); 1279 return; 1280} 1281 1282 1283/* 1284 * A frame was downloaded to the chip. It's safe for us to clean up the list 1285 * buffers. 1286 */ 1287static void 1288my_txeof(struct my_softc * sc) 1289{ 1290 struct my_chain *cur_tx; 1291 struct ifnet *ifp; 1292 1293 MY_LOCK(sc); 1294 ifp = &sc->arpcom.ac_if; 1295 /* Clear the timeout timer. */ 1296 ifp->if_timer = 0; 1297 if (sc->my_cdata.my_tx_head == NULL) { 1298 MY_UNLOCK(sc); 1299 return; 1300 } 1301 /* 1302 * Go through our tx list and free mbufs for those frames that have 1303 * been transmitted. 1304 */ 1305 while (sc->my_cdata.my_tx_head->my_mbuf != NULL) { 1306 u_int32_t txstat; 1307 1308 cur_tx = sc->my_cdata.my_tx_head; 1309 txstat = MY_TXSTATUS(cur_tx); 1310 if ((txstat & MY_OWNByNIC) || txstat == MY_UNSENT) 1311 break; 1312 if (!(CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced)) { 1313 if (txstat & MY_TXERR) { 1314 ifp->if_oerrors++; 1315 if (txstat & MY_EC) /* excessive collision */ 1316 ifp->if_collisions++; 1317 if (txstat & MY_LC) /* late collision */ 1318 ifp->if_collisions++; 1319 } 1320 ifp->if_collisions += (txstat & MY_NCRMASK) >> 1321 MY_NCRShift; 1322 } 1323 ifp->if_opackets++; 1324 m_freem(cur_tx->my_mbuf); 1325 cur_tx->my_mbuf = NULL; 1326 if (sc->my_cdata.my_tx_head == sc->my_cdata.my_tx_tail) { 1327 sc->my_cdata.my_tx_head = NULL; 1328 sc->my_cdata.my_tx_tail = NULL; 1329 break; 1330 } 1331 sc->my_cdata.my_tx_head = cur_tx->my_nextdesc; 1332 } 1333 if (CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced) { 1334 ifp->if_collisions += (CSR_READ_4(sc, MY_TSR) & MY_NCRMask); 1335 } 1336 MY_UNLOCK(sc); 1337 return; 1338} 1339 1340/* 1341 * TX 'end of channel' interrupt handler. 1342 */ 1343static void 1344my_txeoc(struct my_softc * sc) 1345{ 1346 struct ifnet *ifp; 1347 1348 MY_LOCK(sc); 1349 ifp = &sc->arpcom.ac_if; 1350 ifp->if_timer = 0; 1351 if (sc->my_cdata.my_tx_head == NULL) { 1352 ifp->if_flags &= ~IFF_OACTIVE; 1353 sc->my_cdata.my_tx_tail = NULL; 1354 if (sc->my_want_auto) 1355 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1); 1356 } else { 1357 if (MY_TXOWN(sc->my_cdata.my_tx_head) == MY_UNSENT) { 1358 MY_TXOWN(sc->my_cdata.my_tx_head) = MY_OWNByNIC; 1359 ifp->if_timer = 5; 1360 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); 1361 } 1362 } 1363 MY_UNLOCK(sc); 1364 return; 1365} 1366 1367static void 1368my_intr(void *arg) 1369{ 1370 struct my_softc *sc; 1371 struct ifnet *ifp; 1372 u_int32_t status; 1373 1374 sc = arg; 1375 MY_LOCK(sc); 1376 ifp = &sc->arpcom.ac_if; 1377 if (!(ifp->if_flags & IFF_UP)) { 1378 MY_UNLOCK(sc); 1379 return; 1380 } 1381 /* Disable interrupts. */ 1382 CSR_WRITE_4(sc, MY_IMR, 0x00000000); 1383 1384 for (;;) { 1385 status = CSR_READ_4(sc, MY_ISR); 1386 status &= MY_INTRS; 1387 if (status) 1388 CSR_WRITE_4(sc, MY_ISR, status); 1389 else 1390 break; 1391 1392 if (status & MY_RI) /* receive interrupt */ 1393 my_rxeof(sc); 1394 1395 if ((status & MY_RBU) || (status & MY_RxErr)) { 1396 /* rx buffer unavailable or rx error */ 1397 ifp->if_ierrors++; 1398#ifdef foo 1399 my_stop(sc); 1400 my_reset(sc); 1401 my_init(sc); 1402#endif 1403 } 1404 if (status & MY_TI) /* tx interrupt */ 1405 my_txeof(sc); 1406 if (status & MY_ETI) /* tx early interrupt */ 1407 my_txeof(sc); 1408 if (status & MY_TBU) /* tx buffer unavailable */ 1409 my_txeoc(sc); 1410 1411#if 0 /* 90/1/18 delete */ 1412 if (status & MY_FBE) { 1413 my_reset(sc); 1414 my_init(sc); 1415 } 1416#endif 1417 1418 } 1419 1420 /* Re-enable interrupts. */ 1421 CSR_WRITE_4(sc, MY_IMR, MY_INTRS); 1422 if (ifp->if_snd.ifq_head != NULL) 1423 my_start(ifp); 1424 MY_UNLOCK(sc); 1425 return; 1426} 1427 1428/* 1429 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1430 * pointers to the fragment pointers. 1431 */ 1432static int 1433my_encap(struct my_softc * sc, struct my_chain * c, struct mbuf * m_head) 1434{ 1435 struct my_desc *f = NULL; 1436 int total_len; 1437 struct mbuf *m, *m_new = NULL; 1438 1439 MY_LOCK(sc); 1440 /* calculate the total tx pkt length */ 1441 total_len = 0; 1442 for (m = m_head; m != NULL; m = m->m_next) 1443 total_len += m->m_len; 1444 /* 1445 * Start packing the mbufs in this chain into the fragment pointers. 1446 * Stop when we run out of fragments or hit the end of the mbuf 1447 * chain. 1448 */ 1449 m = m_head; 1450 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1451 if (m_new == NULL) { 1452 printf("my%d: no memory for tx list", sc->my_unit); 1453 MY_UNLOCK(sc); 1454 return (1); 1455 } 1456 if (m_head->m_pkthdr.len > MHLEN) { 1457 MCLGET(m_new, M_DONTWAIT); 1458 if (!(m_new->m_flags & M_EXT)) { 1459 m_freem(m_new); 1460 printf("my%d: no memory for tx list", sc->my_unit); 1461 MY_UNLOCK(sc); 1462 return (1); 1463 } 1464 } 1465 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t)); 1466 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1467 m_freem(m_head); 1468 m_head = m_new; 1469 f = &c->my_ptr->my_frag[0]; 1470 f->my_status = 0; 1471 f->my_data = vtophys(mtod(m_new, caddr_t)); 1472 total_len = m_new->m_len; 1473 f->my_ctl = MY_TXFD | MY_TXLD | MY_CRCEnable | MY_PADEnable; 1474 f->my_ctl |= total_len << MY_PKTShift; /* pkt size */ 1475 f->my_ctl |= total_len; /* buffer size */ 1476 /* 89/12/29 add, for mtd891 *//* [ 89? ] */ 1477 if (sc->my_info->my_did == MTD891ID) 1478 f->my_ctl |= MY_ETIControl | MY_RetryTxLC; 1479 c->my_mbuf = m_head; 1480 c->my_lastdesc = 0; 1481 MY_TXNEXT(c) = vtophys(&c->my_nextdesc->my_ptr->my_frag[0]); 1482 MY_UNLOCK(sc); 1483 return (0); 1484} 1485 1486/* 1487 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1488 * to the mbuf data regions directly in the transmit lists. We also save a 1489 * copy of the pointers since the transmit list fragment pointers are 1490 * physical addresses. 1491 */ 1492static void 1493my_start(struct ifnet * ifp) 1494{ 1495 struct my_softc *sc; 1496 struct mbuf *m_head = NULL; 1497 struct my_chain *cur_tx = NULL, *start_tx; 1498 1499 sc = ifp->if_softc; 1500 MY_LOCK(sc); 1501 if (sc->my_autoneg) { 1502 sc->my_tx_pend = 1; 1503 MY_UNLOCK(sc); 1504 return; 1505 } 1506 /* 1507 * Check for an available queue slot. If there are none, punt. 1508 */ 1509 if (sc->my_cdata.my_tx_free->my_mbuf != NULL) { 1510 ifp->if_flags |= IFF_OACTIVE; 1511 MY_UNLOCK(sc); 1512 return; 1513 } 1514 start_tx = sc->my_cdata.my_tx_free; 1515 while (sc->my_cdata.my_tx_free->my_mbuf == NULL) { 1516 IF_DEQUEUE(&ifp->if_snd, m_head); 1517 if (m_head == NULL) 1518 break; 1519 1520 /* Pick a descriptor off the free list. */ 1521 cur_tx = sc->my_cdata.my_tx_free; 1522 sc->my_cdata.my_tx_free = cur_tx->my_nextdesc; 1523 1524 /* Pack the data into the descriptor. */ 1525 my_encap(sc, cur_tx, m_head); 1526 1527 if (cur_tx != start_tx) 1528 MY_TXOWN(cur_tx) = MY_OWNByNIC; 1529#if NBPFILTER > 0 1530 /* 1531 * If there's a BPF listener, bounce a copy of this frame to 1532 * him. 1533 */ 1534 BPF_MTAP(ifp, cur_tx->my_mbuf); 1535#endif 1536 } 1537 /* 1538 * If there are no packets queued, bail. 1539 */ 1540 if (cur_tx == NULL) { 1541 MY_UNLOCK(sc); 1542 return; 1543 } 1544 /* 1545 * Place the request for the upload interrupt in the last descriptor 1546 * in the chain. This way, if we're chaining several packets at once, 1547 * we'll only get an interupt once for the whole chain rather than 1548 * once for each packet. 1549 */ 1550 MY_TXCTL(cur_tx) |= MY_TXIC; 1551 cur_tx->my_ptr->my_frag[0].my_ctl |= MY_TXIC; 1552 sc->my_cdata.my_tx_tail = cur_tx; 1553 if (sc->my_cdata.my_tx_head == NULL) 1554 sc->my_cdata.my_tx_head = start_tx; 1555 MY_TXOWN(start_tx) = MY_OWNByNIC; 1556 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); /* tx polling demand */ 1557 1558 /* 1559 * Set a timeout in case the chip goes out to lunch. 1560 */ 1561 ifp->if_timer = 5; 1562 MY_UNLOCK(sc); 1563 return; 1564} 1565 1566static void 1567my_init(void *xsc) 1568{ 1569 struct my_softc *sc = xsc; 1570 struct ifnet *ifp = &sc->arpcom.ac_if; 1571 int s; 1572 u_int16_t phy_bmcr = 0; 1573 1574 MY_LOCK(sc); 1575 if (sc->my_autoneg) { 1576 MY_UNLOCK(sc); 1577 return; 1578 } 1579 s = splimp(); 1580 if (sc->my_pinfo != NULL) 1581 phy_bmcr = my_phy_readreg(sc, PHY_BMCR); 1582 /* 1583 * Cancel pending I/O and free all RX/TX buffers. 1584 */ 1585 my_stop(sc); 1586 my_reset(sc); 1587 1588 /* 1589 * Set cache alignment and burst length. 1590 */ 1591#if 0 /* 89/9/1 modify, */ 1592 CSR_WRITE_4(sc, MY_BCR, MY_RPBLE512); 1593 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF); 1594#endif 1595 CSR_WRITE_4(sc, MY_BCR, MY_PBL8); 1596 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF | MY_RBLEN | MY_RPBLE512); 1597 /* 1598 * 89/12/29 add, for mtd891, 1599 */ 1600 if (sc->my_info->my_did == MTD891ID) { 1601 MY_SETBIT(sc, MY_BCR, MY_PROG); 1602 MY_SETBIT(sc, MY_TCRRCR, MY_Enhanced); 1603 } 1604 my_setcfg(sc, phy_bmcr); 1605 /* Init circular RX list. */ 1606 if (my_list_rx_init(sc) == ENOBUFS) { 1607 printf("my%d: init failed: no memory for rx buffers\n", 1608 sc->my_unit); 1609 my_stop(sc); 1610 (void)splx(s); 1611 MY_UNLOCK(sc); 1612 return; 1613 } 1614 /* Init TX descriptors. */ 1615 my_list_tx_init(sc); 1616 1617 /* If we want promiscuous mode, set the allframes bit. */ 1618 if (ifp->if_flags & IFF_PROMISC) 1619 MY_SETBIT(sc, MY_TCRRCR, MY_PROM); 1620 else 1621 MY_CLRBIT(sc, MY_TCRRCR, MY_PROM); 1622 1623 /* 1624 * Set capture broadcast bit to capture broadcast frames. 1625 */ 1626 if (ifp->if_flags & IFF_BROADCAST) 1627 MY_SETBIT(sc, MY_TCRRCR, MY_AB); 1628 else 1629 MY_CLRBIT(sc, MY_TCRRCR, MY_AB); 1630 1631 /* 1632 * Program the multicast filter, if necessary. 1633 */ 1634 my_setmulti(sc); 1635 1636 /* 1637 * Load the address of the RX list. 1638 */ 1639 MY_CLRBIT(sc, MY_TCRRCR, MY_RE); 1640 CSR_WRITE_4(sc, MY_RXLBA, vtophys(&sc->my_ldata->my_rx_list[0])); 1641 1642 /* 1643 * Enable interrupts. 1644 */ 1645 CSR_WRITE_4(sc, MY_IMR, MY_INTRS); 1646 CSR_WRITE_4(sc, MY_ISR, 0xFFFFFFFF); 1647 1648 /* Enable receiver and transmitter. */ 1649 MY_SETBIT(sc, MY_TCRRCR, MY_RE); 1650 MY_CLRBIT(sc, MY_TCRRCR, MY_TE); 1651 CSR_WRITE_4(sc, MY_TXLBA, vtophys(&sc->my_ldata->my_tx_list[0])); 1652 MY_SETBIT(sc, MY_TCRRCR, MY_TE); 1653 1654 /* Restore state of BMCR */ 1655 if (sc->my_pinfo != NULL) 1656 my_phy_writereg(sc, PHY_BMCR, phy_bmcr); 1657 ifp->if_flags |= IFF_RUNNING; 1658 ifp->if_flags &= ~IFF_OACTIVE; 1659 (void)splx(s); 1660 MY_UNLOCK(sc); 1661 return; 1662} 1663 1664/* 1665 * Set media options. 1666 */ 1667 1668static int 1669my_ifmedia_upd(struct ifnet * ifp) 1670{ 1671 struct my_softc *sc; 1672 struct ifmedia *ifm; 1673 1674 sc = ifp->if_softc; 1675 MY_LOCK(sc); 1676 ifm = &sc->ifmedia; 1677 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) { 1678 MY_UNLOCK(sc); 1679 return (EINVAL); 1680 } 1681 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) 1682 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1); 1683 else 1684 my_setmode_mii(sc, ifm->ifm_media); 1685 MY_UNLOCK(sc); 1686 return (0); 1687} 1688 1689/* 1690 * Report current media status. 1691 */ 1692 1693static void 1694my_ifmedia_sts(struct ifnet * ifp, struct ifmediareq * ifmr) 1695{ 1696 struct my_softc *sc; 1697 u_int16_t advert = 0, ability = 0; 1698 1699 sc = ifp->if_softc; 1700 MY_LOCK(sc); 1701 ifmr->ifm_active = IFM_ETHER; 1702 if (!(my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) { 1703#if 0 /* this version did not support 1000M, */ 1704 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_1000) 1705 ifmr->ifm_active = IFM_ETHER | IFM_1000TX; 1706#endif 1707 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL) 1708 ifmr->ifm_active = IFM_ETHER | IFM_100_TX; 1709 else 1710 ifmr->ifm_active = IFM_ETHER | IFM_10_T; 1711 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX) 1712 ifmr->ifm_active |= IFM_FDX; 1713 else 1714 ifmr->ifm_active |= IFM_HDX; 1715 1716 MY_UNLOCK(sc); 1717 return; 1718 } 1719 ability = my_phy_readreg(sc, PHY_LPAR); 1720 advert = my_phy_readreg(sc, PHY_ANAR); 1721 1722#if 0 /* this version did not support 1000M, */ 1723 if (sc->my_pinfo->my_vid = MarvellPHYID0) { 1724 ability2 = my_phy_readreg(sc, PHY_1000SR); 1725 if (ability2 & PHY_1000SR_1000BTXFULL) { 1726 advert = 0; 1727 ability = 0; 1728 ifmr->ifm_active = IFM_ETHER|IFM_1000_T|IFM_FDX; 1729 } else if (ability & PHY_1000SR_1000BTXHALF) { 1730 advert = 0; 1731 ability = 0; 1732 ifmr->ifm_active = IFM_ETHER|IFM_1000_T|IFM_HDX; 1733 } 1734 } 1735#endif 1736 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) 1737 ifmr->ifm_active = IFM_ETHER | IFM_100_T4; 1738 else if (advert & PHY_ANAR_100BTXFULL && ability & PHY_ANAR_100BTXFULL) 1739 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1740 else if (advert & PHY_ANAR_100BTXHALF && ability & PHY_ANAR_100BTXHALF) 1741 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_HDX; 1742 else if (advert & PHY_ANAR_10BTFULL && ability & PHY_ANAR_10BTFULL) 1743 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_FDX; 1744 else if (advert & PHY_ANAR_10BTHALF && ability & PHY_ANAR_10BTHALF) 1745 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_HDX; 1746 MY_UNLOCK(sc); 1747 return; 1748} 1749 1750static int 1751my_ioctl(struct ifnet * ifp, u_long command, caddr_t data) 1752{ 1753 struct my_softc *sc = ifp->if_softc; 1754 struct ifreq *ifr = (struct ifreq *) data; 1755 int s, error = 0; 1756 1757 s = splimp(); 1758 MY_LOCK(sc); 1759 switch (command) { 1760 case SIOCSIFFLAGS: 1761 if (ifp->if_flags & IFF_UP) 1762 my_init(sc); 1763 else if (ifp->if_flags & IFF_RUNNING) 1764 my_stop(sc); 1765 error = 0; 1766 break; 1767 case SIOCADDMULTI: 1768 case SIOCDELMULTI: 1769 my_setmulti(sc); 1770 error = 0; 1771 break; 1772 case SIOCGIFMEDIA: 1773 case SIOCSIFMEDIA: 1774 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 1775 break; 1776 default: 1777 error = ether_ioctl(ifp, command, data); 1778 break; 1779 } 1780 MY_UNLOCK(sc); 1781 (void)splx(s); 1782 return (error); 1783} 1784 1785static void 1786my_watchdog(struct ifnet * ifp) 1787{ 1788 struct my_softc *sc; 1789 1790 sc = ifp->if_softc; 1791 MY_LOCK(sc); 1792 if (sc->my_autoneg) { 1793 my_autoneg_mii(sc, MY_FLAG_DELAYTIMEO, 1); 1794 MY_UNLOCK(sc); 1795 return; 1796 } 1797 ifp->if_oerrors++; 1798 printf("my%d: watchdog timeout\n", sc->my_unit); 1799 if (!(my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1800 printf("my%d: no carrier - transceiver cable problem?\n", 1801 sc->my_unit); 1802 my_stop(sc); 1803 my_reset(sc); 1804 my_init(sc); 1805 if (ifp->if_snd.ifq_head != NULL) 1806 my_start(ifp); 1807 MY_LOCK(sc); 1808 return; 1809} 1810 1811 1812/* 1813 * Stop the adapter and free any mbufs allocated to the RX and TX lists. 1814 */ 1815static void 1816my_stop(struct my_softc * sc) 1817{ 1818 register int i; 1819 struct ifnet *ifp; 1820 1821 MY_LOCK(sc); 1822 ifp = &sc->arpcom.ac_if; 1823 ifp->if_timer = 0; 1824 1825 MY_CLRBIT(sc, MY_TCRRCR, (MY_RE | MY_TE)); 1826 CSR_WRITE_4(sc, MY_IMR, 0x00000000); 1827 CSR_WRITE_4(sc, MY_TXLBA, 0x00000000); 1828 CSR_WRITE_4(sc, MY_RXLBA, 0x00000000); 1829 1830 /* 1831 * Free data in the RX lists. 1832 */ 1833 for (i = 0; i < MY_RX_LIST_CNT; i++) { 1834 if (sc->my_cdata.my_rx_chain[i].my_mbuf != NULL) { 1835 m_freem(sc->my_cdata.my_rx_chain[i].my_mbuf); 1836 sc->my_cdata.my_rx_chain[i].my_mbuf = NULL; 1837 } 1838 } 1839 bzero((char *)&sc->my_ldata->my_rx_list, 1840 sizeof(sc->my_ldata->my_rx_list)); 1841 /* 1842 * Free the TX list buffers. 1843 */ 1844 for (i = 0; i < MY_TX_LIST_CNT; i++) { 1845 if (sc->my_cdata.my_tx_chain[i].my_mbuf != NULL) { 1846 m_freem(sc->my_cdata.my_tx_chain[i].my_mbuf); 1847 sc->my_cdata.my_tx_chain[i].my_mbuf = NULL; 1848 } 1849 } 1850 bzero((char *)&sc->my_ldata->my_tx_list, 1851 sizeof(sc->my_ldata->my_tx_list)); 1852 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1853 MY_UNLOCK(sc); 1854 return; 1855} 1856 1857/* 1858 * Stop all chip I/O so that the kernel's probe routines don't get confused 1859 * by errant DMAs when rebooting. 1860 */ 1861static void 1862my_shutdown(device_t dev) 1863{ 1864 struct my_softc *sc; 1865 1866 sc = device_get_softc(dev); 1867 my_stop(sc); 1868 return; 1869} 1870