if_my.c revision 121816
1/*- 2 * Written by: yen_cw@myson.com.tw 3 * Copyright (c) 2002 Myson Technology Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer, 11 * without modification, immediately at the beginning of the file. 12 * 2. The name of the author may not be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 19 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * Myson fast ethernet PCI NIC driver, available at: http://www.myson.com.tw/ 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/my/if_my.c 121816 2003-10-31 18:32:15Z brooks $"); 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/sockio.h> 36#include <sys/mbuf.h> 37#include <sys/malloc.h> 38#include <sys/kernel.h> 39#include <sys/socket.h> 40#include <sys/queue.h> 41#include <sys/types.h> 42#include <sys/bus.h> 43#include <sys/module.h> 44#include <sys/lock.h> 45#include <sys/mutex.h> 46 47#define NBPFILTER 1 48 49#include <net/if.h> 50#include <net/if_arp.h> 51#include <net/ethernet.h> 52#include <net/if_media.h> 53#include <net/if_dl.h> 54#include <net/bpf.h> 55 56#include <vm/vm.h> /* for vtophys */ 57#include <vm/pmap.h> /* for vtophys */ 58#include <machine/clock.h> /* for DELAY */ 59#include <machine/bus_memio.h> 60#include <machine/bus_pio.h> 61#include <machine/bus.h> 62#include <machine/resource.h> 63#include <sys/bus.h> 64#include <sys/rman.h> 65 66#include <dev/pci/pcireg.h> 67#include <dev/pci/pcivar.h> 68 69#include <dev/mii/mii.h> 70#include <dev/mii/miivar.h> 71 72#include "miibus_if.h" 73 74/* 75 * #define MY_USEIOSPACE 76 */ 77 78static int MY_USEIOSPACE = 1; 79 80#if (MY_USEIOSPACE) 81#define MY_RES SYS_RES_IOPORT 82#define MY_RID MY_PCI_LOIO 83#else 84#define MY_RES SYS_RES_MEMORY 85#define MY_RID MY_PCI_LOMEM 86#endif 87 88 89#include <dev/my/if_myreg.h> 90 91#ifndef lint 92static const char rcsid[] = 93"$Id: if_my.c,v 1.16 2003/04/15 06:37:25 mdodd Exp $"; 94#endif 95 96/* 97 * Various supported device vendors/types and their names. 98 */ 99struct my_type *my_info_tmp; 100static struct my_type my_devs[] = { 101 {MYSONVENDORID, MTD800ID, "Myson MTD80X Based Fast Ethernet Card"}, 102 {MYSONVENDORID, MTD803ID, "Myson MTD80X Based Fast Ethernet Card"}, 103 {MYSONVENDORID, MTD891ID, "Myson MTD89X Based Giga Ethernet Card"}, 104 {0, 0, NULL} 105}; 106 107/* 108 * Various supported PHY vendors/types and their names. Note that this driver 109 * will work with pretty much any MII-compliant PHY, so failure to positively 110 * identify the chip is not a fatal error. 111 */ 112static struct my_type my_phys[] = { 113 {MysonPHYID0, MysonPHYID0, "<MYSON MTD981>"}, 114 {SeeqPHYID0, SeeqPHYID0, "<SEEQ 80225>"}, 115 {AhdocPHYID0, AhdocPHYID0, "<AHDOC 101>"}, 116 {MarvellPHYID0, MarvellPHYID0, "<MARVELL 88E1000>"}, 117 {LevelOnePHYID0, LevelOnePHYID0, "<LevelOne LXT1000>"}, 118 {0, 0, "<MII-compliant physical interface>"} 119}; 120 121static int my_probe(device_t); 122static int my_attach(device_t); 123static int my_detach(device_t); 124static int my_newbuf(struct my_softc *, struct my_chain_onefrag *); 125static int my_encap(struct my_softc *, struct my_chain *, struct mbuf *); 126static void my_rxeof(struct my_softc *); 127static void my_txeof(struct my_softc *); 128static void my_txeoc(struct my_softc *); 129static void my_intr(void *); 130static void my_start(struct ifnet *); 131static int my_ioctl(struct ifnet *, u_long, caddr_t); 132static void my_init(void *); 133static void my_stop(struct my_softc *); 134static void my_watchdog(struct ifnet *); 135static void my_shutdown(device_t); 136static int my_ifmedia_upd(struct ifnet *); 137static void my_ifmedia_sts(struct ifnet *, struct ifmediareq *); 138static u_int16_t my_phy_readreg(struct my_softc *, int); 139static void my_phy_writereg(struct my_softc *, int, int); 140static void my_autoneg_xmit(struct my_softc *); 141static void my_autoneg_mii(struct my_softc *, int, int); 142static void my_setmode_mii(struct my_softc *, int); 143static void my_getmode_mii(struct my_softc *); 144static void my_setcfg(struct my_softc *, int); 145static u_int8_t my_calchash(caddr_t); 146static void my_setmulti(struct my_softc *); 147static void my_reset(struct my_softc *); 148static int my_list_rx_init(struct my_softc *); 149static int my_list_tx_init(struct my_softc *); 150static long my_send_cmd_to_phy(struct my_softc *, int, int); 151 152#define MY_SETBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 153#define MY_CLRBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 154 155static device_method_t my_methods[] = { 156 /* Device interface */ 157 DEVMETHOD(device_probe, my_probe), 158 DEVMETHOD(device_attach, my_attach), 159 DEVMETHOD(device_detach, my_detach), 160 DEVMETHOD(device_shutdown, my_shutdown), 161 162 {0, 0} 163}; 164 165static driver_t my_driver = { 166 "my", 167 my_methods, 168 sizeof(struct my_softc) 169}; 170 171static devclass_t my_devclass; 172 173DRIVER_MODULE(my, pci, my_driver, my_devclass, 0, 0); 174MODULE_DEPEND(my, pci, 1, 1, 1); 175MODULE_DEPEND(my, ether, 1, 1, 1); 176 177static long 178my_send_cmd_to_phy(struct my_softc * sc, int opcode, int regad) 179{ 180 long miir; 181 int i; 182 int mask, data; 183 184 MY_LOCK(sc); 185 186 /* enable MII output */ 187 miir = CSR_READ_4(sc, MY_MANAGEMENT); 188 miir &= 0xfffffff0; 189 190 miir |= MY_MASK_MIIR_MII_WRITE + MY_MASK_MIIR_MII_MDO; 191 192 /* send 32 1's preamble */ 193 for (i = 0; i < 32; i++) { 194 /* low MDC; MDO is already high (miir) */ 195 miir &= ~MY_MASK_MIIR_MII_MDC; 196 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 197 198 /* high MDC */ 199 miir |= MY_MASK_MIIR_MII_MDC; 200 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 201 } 202 203 /* calculate ST+OP+PHYAD+REGAD+TA */ 204 data = opcode | (sc->my_phy_addr << 7) | (regad << 2); 205 206 /* sent out */ 207 mask = 0x8000; 208 while (mask) { 209 /* low MDC, prepare MDO */ 210 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO); 211 if (mask & data) 212 miir |= MY_MASK_MIIR_MII_MDO; 213 214 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 215 /* high MDC */ 216 miir |= MY_MASK_MIIR_MII_MDC; 217 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 218 DELAY(30); 219 220 /* next */ 221 mask >>= 1; 222 if (mask == 0x2 && opcode == MY_OP_READ) 223 miir &= ~MY_MASK_MIIR_MII_WRITE; 224 } 225 226 MY_UNLOCK(sc); 227 return miir; 228} 229 230 231static u_int16_t 232my_phy_readreg(struct my_softc * sc, int reg) 233{ 234 long miir; 235 int mask, data; 236 237 MY_LOCK(sc); 238 239 if (sc->my_info->my_did == MTD803ID) 240 data = CSR_READ_2(sc, MY_PHYBASE + reg * 2); 241 else { 242 miir = my_send_cmd_to_phy(sc, MY_OP_READ, reg); 243 244 /* read data */ 245 mask = 0x8000; 246 data = 0; 247 while (mask) { 248 /* low MDC */ 249 miir &= ~MY_MASK_MIIR_MII_MDC; 250 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 251 252 /* read MDI */ 253 miir = CSR_READ_4(sc, MY_MANAGEMENT); 254 if (miir & MY_MASK_MIIR_MII_MDI) 255 data |= mask; 256 257 /* high MDC, and wait */ 258 miir |= MY_MASK_MIIR_MII_MDC; 259 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 260 DELAY(30); 261 262 /* next */ 263 mask >>= 1; 264 } 265 266 /* low MDC */ 267 miir &= ~MY_MASK_MIIR_MII_MDC; 268 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 269 } 270 271 MY_UNLOCK(sc); 272 return (u_int16_t) data; 273} 274 275 276static void 277my_phy_writereg(struct my_softc * sc, int reg, int data) 278{ 279 long miir; 280 int mask; 281 282 MY_LOCK(sc); 283 284 if (sc->my_info->my_did == MTD803ID) 285 CSR_WRITE_2(sc, MY_PHYBASE + reg * 2, data); 286 else { 287 miir = my_send_cmd_to_phy(sc, MY_OP_WRITE, reg); 288 289 /* write data */ 290 mask = 0x8000; 291 while (mask) { 292 /* low MDC, prepare MDO */ 293 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO); 294 if (mask & data) 295 miir |= MY_MASK_MIIR_MII_MDO; 296 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 297 DELAY(1); 298 299 /* high MDC */ 300 miir |= MY_MASK_MIIR_MII_MDC; 301 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 302 DELAY(1); 303 304 /* next */ 305 mask >>= 1; 306 } 307 308 /* low MDC */ 309 miir &= ~MY_MASK_MIIR_MII_MDC; 310 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 311 } 312 MY_UNLOCK(sc); 313 return; 314} 315 316static u_int8_t 317my_calchash(caddr_t addr) 318{ 319 u_int32_t crc, carry; 320 int i, j; 321 u_int8_t c; 322 323 /* Compute CRC for the address value. */ 324 crc = 0xFFFFFFFF; /* initial value */ 325 326 for (i = 0; i < 6; i++) { 327 c = *(addr + i); 328 for (j = 0; j < 8; j++) { 329 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 330 crc <<= 1; 331 c >>= 1; 332 if (carry) 333 crc = (crc ^ 0x04c11db6) | carry; 334 } 335 } 336 337 /* 338 * return the filter bit position Note: I arrived at the following 339 * nonsense through experimentation. It's not the usual way to 340 * generate the bit position but it's the only thing I could come up 341 * with that works. 342 */ 343 return (~(crc >> 26) & 0x0000003F); 344} 345 346 347/* 348 * Program the 64-bit multicast hash filter. 349 */ 350static void 351my_setmulti(struct my_softc * sc) 352{ 353 struct ifnet *ifp; 354 int h = 0; 355 u_int32_t hashes[2] = {0, 0}; 356 struct ifmultiaddr *ifma; 357 u_int32_t rxfilt; 358 int mcnt = 0; 359 360 MY_LOCK(sc); 361 362 ifp = &sc->arpcom.ac_if; 363 364 rxfilt = CSR_READ_4(sc, MY_TCRRCR); 365 366 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 367 rxfilt |= MY_AM; 368 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt); 369 CSR_WRITE_4(sc, MY_MAR0, 0xFFFFFFFF); 370 CSR_WRITE_4(sc, MY_MAR1, 0xFFFFFFFF); 371 372 MY_UNLOCK(sc); 373 374 return; 375 } 376 /* first, zot all the existing hash bits */ 377 CSR_WRITE_4(sc, MY_MAR0, 0); 378 CSR_WRITE_4(sc, MY_MAR1, 0); 379 380 /* now program new ones */ 381 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 382 if (ifma->ifma_addr->sa_family != AF_LINK) 383 continue; 384 h = my_calchash(LLADDR((struct sockaddr_dl *) ifma->ifma_addr)); 385 if (h < 32) 386 hashes[0] |= (1 << h); 387 else 388 hashes[1] |= (1 << (h - 32)); 389 mcnt++; 390 } 391 392 if (mcnt) 393 rxfilt |= MY_AM; 394 else 395 rxfilt &= ~MY_AM; 396 CSR_WRITE_4(sc, MY_MAR0, hashes[0]); 397 CSR_WRITE_4(sc, MY_MAR1, hashes[1]); 398 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt); 399 MY_UNLOCK(sc); 400 return; 401} 402 403/* 404 * Initiate an autonegotiation session. 405 */ 406static void 407my_autoneg_xmit(struct my_softc * sc) 408{ 409 u_int16_t phy_sts = 0; 410 411 MY_LOCK(sc); 412 413 my_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); 414 DELAY(500); 415 while (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_RESET); 416 417 phy_sts = my_phy_readreg(sc, PHY_BMCR); 418 phy_sts |= PHY_BMCR_AUTONEGENBL | PHY_BMCR_AUTONEGRSTR; 419 my_phy_writereg(sc, PHY_BMCR, phy_sts); 420 421 MY_UNLOCK(sc); 422 return; 423} 424 425 426/* 427 * Invoke autonegotiation on a PHY. 428 */ 429static void 430my_autoneg_mii(struct my_softc * sc, int flag, int verbose) 431{ 432 u_int16_t phy_sts = 0, media, advert, ability; 433 u_int16_t ability2 = 0; 434 struct ifnet *ifp; 435 struct ifmedia *ifm; 436 437 MY_LOCK(sc); 438 439 ifm = &sc->ifmedia; 440 ifp = &sc->arpcom.ac_if; 441 442 ifm->ifm_media = IFM_ETHER | IFM_AUTO; 443 444#ifndef FORCE_AUTONEG_TFOUR 445 /* 446 * First, see if autoneg is supported. If not, there's no point in 447 * continuing. 448 */ 449 phy_sts = my_phy_readreg(sc, PHY_BMSR); 450 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) { 451 if (verbose) 452 printf("my%d: autonegotiation not supported\n", 453 sc->my_unit); 454 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 455 MY_UNLOCK(sc); 456 return; 457 } 458#endif 459 switch (flag) { 460 case MY_FLAG_FORCEDELAY: 461 /* 462 * XXX Never use this option anywhere but in the probe 463 * routine: making the kernel stop dead in its tracks for 464 * three whole seconds after we've gone multi-user is really 465 * bad manners. 466 */ 467 my_autoneg_xmit(sc); 468 DELAY(5000000); 469 break; 470 case MY_FLAG_SCHEDDELAY: 471 /* 472 * Wait for the transmitter to go idle before starting an 473 * autoneg session, otherwise my_start() may clobber our 474 * timeout, and we don't want to allow transmission during an 475 * autoneg session since that can screw it up. 476 */ 477 if (sc->my_cdata.my_tx_head != NULL) { 478 sc->my_want_auto = 1; 479 MY_UNLOCK(sc); 480 return; 481 } 482 my_autoneg_xmit(sc); 483 ifp->if_timer = 5; 484 sc->my_autoneg = 1; 485 sc->my_want_auto = 0; 486 MY_UNLOCK(sc); 487 return; 488 case MY_FLAG_DELAYTIMEO: 489 ifp->if_timer = 0; 490 sc->my_autoneg = 0; 491 break; 492 default: 493 printf("my%d: invalid autoneg flag: %d\n", sc->my_unit, flag); 494 MY_UNLOCK(sc); 495 return; 496 } 497 498 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) { 499 if (verbose) 500 printf("my%d: autoneg complete, ", sc->my_unit); 501 phy_sts = my_phy_readreg(sc, PHY_BMSR); 502 } else { 503 if (verbose) 504 printf("my%d: autoneg not complete, ", sc->my_unit); 505 } 506 507 media = my_phy_readreg(sc, PHY_BMCR); 508 509 /* Link is good. Report modes and set duplex mode. */ 510 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) { 511 if (verbose) 512 printf("my%d: link status good. ", sc->my_unit); 513 advert = my_phy_readreg(sc, PHY_ANAR); 514 ability = my_phy_readreg(sc, PHY_LPAR); 515 if ((sc->my_pinfo->my_vid == MarvellPHYID0) || 516 (sc->my_pinfo->my_vid == LevelOnePHYID0)) { 517 ability2 = my_phy_readreg(sc, PHY_1000SR); 518 if (ability2 & PHY_1000SR_1000BTXFULL) { 519 advert = 0; 520 ability = 0; 521 /* 522 * this version did not support 1000M, 523 * ifm->ifm_media = 524 * IFM_ETHER|IFM_1000_T|IFM_FDX; 525 */ 526 ifm->ifm_media = 527 IFM_ETHER | IFM_100_TX | IFM_FDX; 528 media &= ~PHY_BMCR_SPEEDSEL; 529 media |= PHY_BMCR_1000; 530 media |= PHY_BMCR_DUPLEX; 531 printf("(full-duplex, 1000Mbps)\n"); 532 } else if (ability2 & PHY_1000SR_1000BTXHALF) { 533 advert = 0; 534 ability = 0; 535 /* 536 * this version did not support 1000M, 537 * ifm->ifm_media = IFM_ETHER|IFM_1000_T; 538 */ 539 ifm->ifm_media = IFM_ETHER | IFM_100_TX; 540 media &= ~PHY_BMCR_SPEEDSEL; 541 media &= ~PHY_BMCR_DUPLEX; 542 media |= PHY_BMCR_1000; 543 printf("(half-duplex, 1000Mbps)\n"); 544 } 545 } 546 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) { 547 ifm->ifm_media = IFM_ETHER | IFM_100_T4; 548 media |= PHY_BMCR_SPEEDSEL; 549 media &= ~PHY_BMCR_DUPLEX; 550 printf("(100baseT4)\n"); 551 } else if (advert & PHY_ANAR_100BTXFULL && 552 ability & PHY_ANAR_100BTXFULL) { 553 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX; 554 media |= PHY_BMCR_SPEEDSEL; 555 media |= PHY_BMCR_DUPLEX; 556 printf("(full-duplex, 100Mbps)\n"); 557 } else if (advert & PHY_ANAR_100BTXHALF && 558 ability & PHY_ANAR_100BTXHALF) { 559 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX; 560 media |= PHY_BMCR_SPEEDSEL; 561 media &= ~PHY_BMCR_DUPLEX; 562 printf("(half-duplex, 100Mbps)\n"); 563 } else if (advert & PHY_ANAR_10BTFULL && 564 ability & PHY_ANAR_10BTFULL) { 565 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX; 566 media &= ~PHY_BMCR_SPEEDSEL; 567 media |= PHY_BMCR_DUPLEX; 568 printf("(full-duplex, 10Mbps)\n"); 569 } else if (advert) { 570 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 571 media &= ~PHY_BMCR_SPEEDSEL; 572 media &= ~PHY_BMCR_DUPLEX; 573 printf("(half-duplex, 10Mbps)\n"); 574 } 575 media &= ~PHY_BMCR_AUTONEGENBL; 576 577 /* Set ASIC's duplex mode to match the PHY. */ 578 my_phy_writereg(sc, PHY_BMCR, media); 579 my_setcfg(sc, media); 580 } else { 581 if (verbose) 582 printf("my%d: no carrier\n", sc->my_unit); 583 } 584 585 my_init(sc); 586 if (sc->my_tx_pend) { 587 sc->my_autoneg = 0; 588 sc->my_tx_pend = 0; 589 my_start(ifp); 590 } 591 MY_UNLOCK(sc); 592 return; 593} 594 595/* 596 * To get PHY ability. 597 */ 598static void 599my_getmode_mii(struct my_softc * sc) 600{ 601 u_int16_t bmsr; 602 struct ifnet *ifp; 603 604 MY_LOCK(sc); 605 ifp = &sc->arpcom.ac_if; 606 bmsr = my_phy_readreg(sc, PHY_BMSR); 607 if (bootverbose) 608 printf("my%d: PHY status word: %x\n", sc->my_unit, bmsr); 609 610 /* fallback */ 611 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 612 613 if (bmsr & PHY_BMSR_10BTHALF) { 614 if (bootverbose) 615 printf("my%d: 10Mbps half-duplex mode supported\n", 616 sc->my_unit); 617 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_HDX, 618 0, NULL); 619 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T, 0, NULL); 620 } 621 if (bmsr & PHY_BMSR_10BTFULL) { 622 if (bootverbose) 623 printf("my%d: 10Mbps full-duplex mode supported\n", 624 sc->my_unit); 625 626 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 627 0, NULL); 628 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX; 629 } 630 if (bmsr & PHY_BMSR_100BTXHALF) { 631 if (bootverbose) 632 printf("my%d: 100Mbps half-duplex mode supported\n", 633 sc->my_unit); 634 ifp->if_baudrate = 100000000; 635 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL); 636 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_HDX, 637 0, NULL); 638 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX; 639 } 640 if (bmsr & PHY_BMSR_100BTXFULL) { 641 if (bootverbose) 642 printf("my%d: 100Mbps full-duplex mode supported\n", 643 sc->my_unit); 644 ifp->if_baudrate = 100000000; 645 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 646 0, NULL); 647 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX; 648 } 649 /* Some also support 100BaseT4. */ 650 if (bmsr & PHY_BMSR_100BT4) { 651 if (bootverbose) 652 printf("my%d: 100baseT4 mode supported\n", sc->my_unit); 653 ifp->if_baudrate = 100000000; 654 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_T4, 0, NULL); 655 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_T4; 656#ifdef FORCE_AUTONEG_TFOUR 657 if (bootverbose) 658 printf("my%d: forcing on autoneg support for BT4\n", 659 sc->my_unit); 660 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0 NULL): 661 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO; 662#endif 663 } 664#if 0 /* this version did not support 1000M, */ 665 if (sc->my_pinfo->my_vid == MarvellPHYID0) { 666 if (bootverbose) 667 printf("my%d: 1000Mbps half-duplex mode supported\n", 668 sc->my_unit); 669 670 ifp->if_baudrate = 1000000000; 671 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL); 672 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_HDX, 673 0, NULL); 674 if (bootverbose) 675 printf("my%d: 1000Mbps full-duplex mode supported\n", 676 sc->my_unit); 677 ifp->if_baudrate = 1000000000; 678 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX, 679 0, NULL); 680 sc->ifmedia.ifm_media = IFM_ETHER | IFM_1000_T | IFM_FDX; 681 } 682#endif 683 if (bmsr & PHY_BMSR_CANAUTONEG) { 684 if (bootverbose) 685 printf("my%d: autoneg supported\n", sc->my_unit); 686 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 687 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO; 688 } 689 MY_UNLOCK(sc); 690 return; 691} 692 693/* 694 * Set speed and duplex mode. 695 */ 696static void 697my_setmode_mii(struct my_softc * sc, int media) 698{ 699 u_int16_t bmcr; 700 struct ifnet *ifp; 701 702 MY_LOCK(sc); 703 ifp = &sc->arpcom.ac_if; 704 /* 705 * If an autoneg session is in progress, stop it. 706 */ 707 if (sc->my_autoneg) { 708 printf("my%d: canceling autoneg session\n", sc->my_unit); 709 ifp->if_timer = sc->my_autoneg = sc->my_want_auto = 0; 710 bmcr = my_phy_readreg(sc, PHY_BMCR); 711 bmcr &= ~PHY_BMCR_AUTONEGENBL; 712 my_phy_writereg(sc, PHY_BMCR, bmcr); 713 } 714 printf("my%d: selecting MII, ", sc->my_unit); 715 bmcr = my_phy_readreg(sc, PHY_BMCR); 716 bmcr &= ~(PHY_BMCR_AUTONEGENBL | PHY_BMCR_SPEEDSEL | PHY_BMCR_1000 | 717 PHY_BMCR_DUPLEX | PHY_BMCR_LOOPBK); 718 719#if 0 /* this version did not support 1000M, */ 720 if (IFM_SUBTYPE(media) == IFM_1000_T) { 721 printf("1000Mbps/T4, half-duplex\n"); 722 bmcr &= ~PHY_BMCR_SPEEDSEL; 723 bmcr &= ~PHY_BMCR_DUPLEX; 724 bmcr |= PHY_BMCR_1000; 725 } 726#endif 727 if (IFM_SUBTYPE(media) == IFM_100_T4) { 728 printf("100Mbps/T4, half-duplex\n"); 729 bmcr |= PHY_BMCR_SPEEDSEL; 730 bmcr &= ~PHY_BMCR_DUPLEX; 731 } 732 if (IFM_SUBTYPE(media) == IFM_100_TX) { 733 printf("100Mbps, "); 734 bmcr |= PHY_BMCR_SPEEDSEL; 735 } 736 if (IFM_SUBTYPE(media) == IFM_10_T) { 737 printf("10Mbps, "); 738 bmcr &= ~PHY_BMCR_SPEEDSEL; 739 } 740 if ((media & IFM_GMASK) == IFM_FDX) { 741 printf("full duplex\n"); 742 bmcr |= PHY_BMCR_DUPLEX; 743 } else { 744 printf("half duplex\n"); 745 bmcr &= ~PHY_BMCR_DUPLEX; 746 } 747 my_phy_writereg(sc, PHY_BMCR, bmcr); 748 my_setcfg(sc, bmcr); 749 MY_UNLOCK(sc); 750 return; 751} 752 753/* 754 * The Myson manual states that in order to fiddle with the 'full-duplex' and 755 * '100Mbps' bits in the netconfig register, we first have to put the 756 * transmit and/or receive logic in the idle state. 757 */ 758static void 759my_setcfg(struct my_softc * sc, int bmcr) 760{ 761 int i, restart = 0; 762 763 MY_LOCK(sc); 764 if (CSR_READ_4(sc, MY_TCRRCR) & (MY_TE | MY_RE)) { 765 restart = 1; 766 MY_CLRBIT(sc, MY_TCRRCR, (MY_TE | MY_RE)); 767 for (i = 0; i < MY_TIMEOUT; i++) { 768 DELAY(10); 769 if (!(CSR_READ_4(sc, MY_TCRRCR) & 770 (MY_TXRUN | MY_RXRUN))) 771 break; 772 } 773 if (i == MY_TIMEOUT) 774 printf("my%d: failed to force tx and rx to idle \n", 775 sc->my_unit); 776 } 777 MY_CLRBIT(sc, MY_TCRRCR, MY_PS1000); 778 MY_CLRBIT(sc, MY_TCRRCR, MY_PS10); 779 if (bmcr & PHY_BMCR_1000) 780 MY_SETBIT(sc, MY_TCRRCR, MY_PS1000); 781 else if (!(bmcr & PHY_BMCR_SPEEDSEL)) 782 MY_SETBIT(sc, MY_TCRRCR, MY_PS10); 783 if (bmcr & PHY_BMCR_DUPLEX) 784 MY_SETBIT(sc, MY_TCRRCR, MY_FD); 785 else 786 MY_CLRBIT(sc, MY_TCRRCR, MY_FD); 787 if (restart) 788 MY_SETBIT(sc, MY_TCRRCR, MY_TE | MY_RE); 789 MY_UNLOCK(sc); 790 return; 791} 792 793static void 794my_reset(struct my_softc * sc) 795{ 796 register int i; 797 798 MY_LOCK(sc); 799 MY_SETBIT(sc, MY_BCR, MY_SWR); 800 for (i = 0; i < MY_TIMEOUT; i++) { 801 DELAY(10); 802 if (!(CSR_READ_4(sc, MY_BCR) & MY_SWR)) 803 break; 804 } 805 if (i == MY_TIMEOUT) 806 printf("m0x%d: reset never completed!\n", sc->my_unit); 807 808 /* Wait a little while for the chip to get its brains in order. */ 809 DELAY(1000); 810 MY_UNLOCK(sc); 811 return; 812} 813 814/* 815 * Probe for a Myson chip. Check the PCI vendor and device IDs against our 816 * list and return a device name if we find a match. 817 */ 818static int 819my_probe(device_t dev) 820{ 821 struct my_type *t; 822 823 t = my_devs; 824 while (t->my_name != NULL) { 825 if ((pci_get_vendor(dev) == t->my_vid) && 826 (pci_get_device(dev) == t->my_did)) { 827 device_set_desc(dev, t->my_name); 828 my_info_tmp = t; 829 return (0); 830 } 831 t++; 832 } 833 return (ENXIO); 834} 835 836/* 837 * Attach the interface. Allocate softc structures, do ifmedia setup and 838 * ethernet/BPF attach. 839 */ 840static int 841my_attach(device_t dev) 842{ 843 int s, i; 844 u_char eaddr[ETHER_ADDR_LEN]; 845 u_int32_t command, iobase; 846 struct my_softc *sc; 847 struct ifnet *ifp; 848 int media = IFM_ETHER | IFM_100_TX | IFM_FDX; 849 unsigned int round; 850 caddr_t roundptr; 851 struct my_type *p; 852 u_int16_t phy_vid, phy_did, phy_sts = 0; 853 int rid, unit, error = 0; 854 855 s = splimp(); 856 sc = device_get_softc(dev); 857 unit = device_get_unit(dev); 858 if (sc == NULL) { 859 printf("my%d: no memory for softc struct!\n", unit); 860 error = ENXIO; 861 goto fail; 862 863 } 864 bzero(sc, sizeof(struct my_softc)); 865 mtx_init(&sc->my_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 866 MTX_DEF | MTX_RECURSE); 867 MY_LOCK(sc); 868 869 /* 870 * Map control/status registers. 871 */ 872#if 0 873 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 874 command |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 875 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command & 0x000000ff, 4); 876 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 877#endif 878 command = pci_read_config(dev, PCIR_COMMAND, 4); 879 command |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 880 pci_write_config(dev, PCIR_COMMAND, command & 0x000000ff, 4); 881 command = pci_read_config(dev, PCIR_COMMAND, 4); 882 883 if (my_info_tmp->my_did == MTD800ID) { 884 iobase = pci_read_config(dev, MY_PCI_LOIO, 4); 885 if (iobase & 0x300) 886 MY_USEIOSPACE = 0; 887 } 888 if (MY_USEIOSPACE) { 889 if (!(command & PCIM_CMD_PORTEN)) { 890 printf("my%d: failed to enable I/O ports!\n", unit); 891 free(sc, M_DEVBUF); 892 error = ENXIO; 893 goto fail; 894 } 895#if 0 896 if (!pci_map_port(config_id, MY_PCI_LOIO, (u_int16_t *) & (sc->my_bhandle))) { 897 printf("my%d: couldn't map ports\n", unit); 898 error = ENXIO; 899 goto fail; 900 } 901 902 sc->my_btag = I386_BUS_SPACE_IO; 903#endif 904 } else { 905 if (!(command & PCIM_CMD_MEMEN)) { 906 printf("my%d: failed to enable memory mapping!\n", 907 unit); 908 error = ENXIO; 909 goto fail; 910 } 911#if 0 912 if (!pci_map_mem(config_id, MY_PCI_LOMEM, &vbase, &pbase)) { 913 printf ("my%d: couldn't map memory\n", unit); 914 error = ENXIO; 915 goto fail; 916 } 917 sc->my_btag = I386_BUS_SPACE_MEM; 918 sc->my_bhandle = vbase; 919#endif 920 } 921 922 rid = MY_RID; 923 sc->my_res = bus_alloc_resource(dev, MY_RES, &rid, 924 0, ~0, 1, RF_ACTIVE); 925 926 if (sc->my_res == NULL) { 927 printf("my%d: couldn't map ports/memory\n", unit); 928 error = ENXIO; 929 goto fail; 930 } 931 sc->my_btag = rman_get_bustag(sc->my_res); 932 sc->my_bhandle = rman_get_bushandle(sc->my_res); 933 934 rid = 0; 935 sc->my_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 936 RF_SHAREABLE | RF_ACTIVE); 937 938 if (sc->my_irq == NULL) { 939 printf("my%d: couldn't map interrupt\n", unit); 940 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res); 941 error = ENXIO; 942 goto fail; 943 } 944 error = bus_setup_intr(dev, sc->my_irq, INTR_TYPE_NET, 945 my_intr, sc, &sc->my_intrhand); 946 947 if (error) { 948 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq); 949 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res); 950 printf("my%d: couldn't set up irq\n", unit); 951 goto fail; 952 } 953 callout_handle_init(&sc->my_stat_ch); 954 955 sc->my_info = my_info_tmp; 956 957 /* Reset the adapter. */ 958 my_reset(sc); 959 960 /* 961 * Get station address 962 */ 963 for (i = 0; i < ETHER_ADDR_LEN; ++i) 964 eaddr[i] = CSR_READ_1(sc, MY_PAR0 + i); 965 966 /* 967 * A Myson chip was detected. Inform the world. 968 */ 969 printf("my%d: Ethernet address: %6D\n", unit, eaddr, ":"); 970 971 sc->my_unit = unit; 972 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 973 974 sc->my_ldata_ptr = malloc(sizeof(struct my_list_data) + 8, 975 M_DEVBUF, M_NOWAIT); 976 if (sc->my_ldata_ptr == NULL) { 977 free(sc, M_DEVBUF); 978 printf("my%d: no memory for list buffers!\n", unit); 979 error = ENXIO; 980 goto fail; 981 } 982 sc->my_ldata = (struct my_list_data *) sc->my_ldata_ptr; 983 round = (uintptr_t)sc->my_ldata_ptr & 0xF; 984 roundptr = sc->my_ldata_ptr; 985 for (i = 0; i < 8; i++) { 986 if (round % 8) { 987 round++; 988 roundptr++; 989 } else 990 break; 991 } 992 sc->my_ldata = (struct my_list_data *) roundptr; 993 bzero(sc->my_ldata, sizeof(struct my_list_data)); 994 995 ifp = &sc->arpcom.ac_if; 996 ifp->if_softc = sc; 997 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 998 ifp->if_mtu = ETHERMTU; 999 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1000 ifp->if_ioctl = my_ioctl; 1001 ifp->if_output = ether_output; 1002 ifp->if_start = my_start; 1003 ifp->if_watchdog = my_watchdog; 1004 ifp->if_init = my_init; 1005 ifp->if_baudrate = 10000000; 1006 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 1007 1008 if (sc->my_info->my_did == MTD803ID) 1009 sc->my_pinfo = my_phys; 1010 else { 1011 if (bootverbose) 1012 printf("my%d: probing for a PHY\n", sc->my_unit); 1013 for (i = MY_PHYADDR_MIN; i < MY_PHYADDR_MAX + 1; i++) { 1014 if (bootverbose) 1015 printf("my%d: checking address: %d\n", 1016 sc->my_unit, i); 1017 sc->my_phy_addr = i; 1018 phy_sts = my_phy_readreg(sc, PHY_BMSR); 1019 if ((phy_sts != 0) && (phy_sts != 0xffff)) 1020 break; 1021 else 1022 phy_sts = 0; 1023 } 1024 if (phy_sts) { 1025 phy_vid = my_phy_readreg(sc, PHY_VENID); 1026 phy_did = my_phy_readreg(sc, PHY_DEVID); 1027 if (bootverbose) { 1028 printf("my%d: found PHY at address %d, ", 1029 sc->my_unit, sc->my_phy_addr); 1030 printf("vendor id: %x device id: %x\n", 1031 phy_vid, phy_did); 1032 } 1033 p = my_phys; 1034 while (p->my_vid) { 1035 if (phy_vid == p->my_vid) { 1036 sc->my_pinfo = p; 1037 break; 1038 } 1039 p++; 1040 } 1041 if (sc->my_pinfo == NULL) 1042 sc->my_pinfo = &my_phys[PHY_UNKNOWN]; 1043 if (bootverbose) 1044 printf("my%d: PHY type: %s\n", 1045 sc->my_unit, sc->my_pinfo->my_name); 1046 } else { 1047 printf("my%d: MII without any phy!\n", sc->my_unit); 1048 error = ENXIO; 1049 goto fail; 1050 } 1051 } 1052 1053 /* Do ifmedia setup. */ 1054 ifmedia_init(&sc->ifmedia, 0, my_ifmedia_upd, my_ifmedia_sts); 1055 my_getmode_mii(sc); 1056 my_autoneg_mii(sc, MY_FLAG_FORCEDELAY, 1); 1057 media = sc->ifmedia.ifm_media; 1058 my_stop(sc); 1059 ifmedia_set(&sc->ifmedia, media); 1060 1061 ether_ifattach(ifp, eaddr); 1062 1063#if 0 1064 at_shutdown(my_shutdown, sc, SHUTDOWN_POST_SYNC); 1065 shutdownhook_establish(my_shutdown, sc); 1066#endif 1067 1068 MY_UNLOCK(sc); 1069 return (0); 1070 1071fail: 1072 MY_UNLOCK(sc); 1073 mtx_destroy(&sc->my_mtx); 1074 splx(s); 1075 return (error); 1076} 1077 1078static int 1079my_detach(device_t dev) 1080{ 1081 struct my_softc *sc; 1082 struct ifnet *ifp; 1083 int s; 1084 1085 s = splimp(); 1086 sc = device_get_softc(dev); 1087 MY_LOCK(sc); 1088 ifp = &sc->arpcom.ac_if; 1089 ether_ifdetach(ifp); 1090 my_stop(sc); 1091 1092#if 0 1093 bus_generic_detach(dev); 1094 device_delete_child(dev, sc->rl_miibus); 1095#endif 1096 1097 bus_teardown_intr(dev, sc->my_irq, sc->my_intrhand); 1098 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq); 1099 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res); 1100#if 0 1101 contigfree(sc->my_cdata.my_rx_buf, MY_RXBUFLEN + 32, M_DEVBUF); 1102#endif 1103 free(sc, M_DEVBUF); 1104 MY_UNLOCK(sc); 1105 splx(s); 1106 mtx_destroy(&sc->my_mtx); 1107 return (0); 1108} 1109 1110 1111/* 1112 * Initialize the transmit descriptors. 1113 */ 1114static int 1115my_list_tx_init(struct my_softc * sc) 1116{ 1117 struct my_chain_data *cd; 1118 struct my_list_data *ld; 1119 int i; 1120 1121 MY_LOCK(sc); 1122 cd = &sc->my_cdata; 1123 ld = sc->my_ldata; 1124 for (i = 0; i < MY_TX_LIST_CNT; i++) { 1125 cd->my_tx_chain[i].my_ptr = &ld->my_tx_list[i]; 1126 if (i == (MY_TX_LIST_CNT - 1)) 1127 cd->my_tx_chain[i].my_nextdesc = &cd->my_tx_chain[0]; 1128 else 1129 cd->my_tx_chain[i].my_nextdesc = 1130 &cd->my_tx_chain[i + 1]; 1131 } 1132 cd->my_tx_free = &cd->my_tx_chain[0]; 1133 cd->my_tx_tail = cd->my_tx_head = NULL; 1134 MY_UNLOCK(sc); 1135 return (0); 1136} 1137 1138/* 1139 * Initialize the RX descriptors and allocate mbufs for them. Note that we 1140 * arrange the descriptors in a closed ring, so that the last descriptor 1141 * points back to the first. 1142 */ 1143static int 1144my_list_rx_init(struct my_softc * sc) 1145{ 1146 struct my_chain_data *cd; 1147 struct my_list_data *ld; 1148 int i; 1149 1150 MY_LOCK(sc); 1151 cd = &sc->my_cdata; 1152 ld = sc->my_ldata; 1153 for (i = 0; i < MY_RX_LIST_CNT; i++) { 1154 cd->my_rx_chain[i].my_ptr = 1155 (struct my_desc *) & ld->my_rx_list[i]; 1156 if (my_newbuf(sc, &cd->my_rx_chain[i]) == ENOBUFS) { 1157 MY_UNLOCK(sc); 1158 return (ENOBUFS); 1159 } 1160 if (i == (MY_RX_LIST_CNT - 1)) { 1161 cd->my_rx_chain[i].my_nextdesc = &cd->my_rx_chain[0]; 1162 ld->my_rx_list[i].my_next = vtophys(&ld->my_rx_list[0]); 1163 } else { 1164 cd->my_rx_chain[i].my_nextdesc = 1165 &cd->my_rx_chain[i + 1]; 1166 ld->my_rx_list[i].my_next = 1167 vtophys(&ld->my_rx_list[i + 1]); 1168 } 1169 } 1170 cd->my_rx_head = &cd->my_rx_chain[0]; 1171 MY_UNLOCK(sc); 1172 return (0); 1173} 1174 1175/* 1176 * Initialize an RX descriptor and attach an MBUF cluster. 1177 */ 1178static int 1179my_newbuf(struct my_softc * sc, struct my_chain_onefrag * c) 1180{ 1181 struct mbuf *m_new = NULL; 1182 1183 MY_LOCK(sc); 1184 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1185 if (m_new == NULL) { 1186 printf("my%d: no memory for rx list -- packet dropped!\n", 1187 sc->my_unit); 1188 MY_UNLOCK(sc); 1189 return (ENOBUFS); 1190 } 1191 MCLGET(m_new, M_DONTWAIT); 1192 if (!(m_new->m_flags & M_EXT)) { 1193 printf("my%d: no memory for rx list -- packet dropped!\n", 1194 sc->my_unit); 1195 m_freem(m_new); 1196 MY_UNLOCK(sc); 1197 return (ENOBUFS); 1198 } 1199 c->my_mbuf = m_new; 1200 c->my_ptr->my_data = vtophys(mtod(m_new, caddr_t)); 1201 c->my_ptr->my_ctl = (MCLBYTES - 1) << MY_RBSShift; 1202 c->my_ptr->my_status = MY_OWNByNIC; 1203 MY_UNLOCK(sc); 1204 return (0); 1205} 1206 1207/* 1208 * A frame has been uploaded: pass the resulting mbuf chain up to the higher 1209 * level protocols. 1210 */ 1211static void 1212my_rxeof(struct my_softc * sc) 1213{ 1214 struct ether_header *eh; 1215 struct mbuf *m; 1216 struct ifnet *ifp; 1217 struct my_chain_onefrag *cur_rx; 1218 int total_len = 0; 1219 u_int32_t rxstat; 1220 1221 MY_LOCK(sc); 1222 ifp = &sc->arpcom.ac_if; 1223 while (!((rxstat = sc->my_cdata.my_rx_head->my_ptr->my_status) 1224 & MY_OWNByNIC)) { 1225 cur_rx = sc->my_cdata.my_rx_head; 1226 sc->my_cdata.my_rx_head = cur_rx->my_nextdesc; 1227 1228 if (rxstat & MY_ES) { /* error summary: give up this rx pkt */ 1229 ifp->if_ierrors++; 1230 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1231 continue; 1232 } 1233 /* No errors; receive the packet. */ 1234 total_len = (rxstat & MY_FLNGMASK) >> MY_FLNGShift; 1235 total_len -= ETHER_CRC_LEN; 1236 1237 if (total_len < MINCLSIZE) { 1238 m = m_devget(mtod(cur_rx->my_mbuf, char *), 1239 total_len, 0, ifp, NULL); 1240 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1241 if (m == NULL) { 1242 ifp->if_ierrors++; 1243 continue; 1244 } 1245 } else { 1246 m = cur_rx->my_mbuf; 1247 /* 1248 * Try to conjure up a new mbuf cluster. If that 1249 * fails, it means we have an out of memory condition 1250 * and should leave the buffer in place and continue. 1251 * This will result in a lost packet, but there's 1252 * little else we can do in this situation. 1253 */ 1254 if (my_newbuf(sc, cur_rx) == ENOBUFS) { 1255 ifp->if_ierrors++; 1256 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1257 continue; 1258 } 1259 m->m_pkthdr.rcvif = ifp; 1260 m->m_pkthdr.len = m->m_len = total_len; 1261 } 1262 ifp->if_ipackets++; 1263 eh = mtod(m, struct ether_header *); 1264#if NBPFILTER > 0 1265 /* 1266 * Handle BPF listeners. Let the BPF user see the packet, but 1267 * don't pass it up to the ether_input() layer unless it's a 1268 * broadcast packet, multicast packet, matches our ethernet 1269 * address or the interface is in promiscuous mode. 1270 */ 1271 if (ifp->if_bpf) { 1272 BPF_MTAP(ifp, m); 1273 if (ifp->if_flags & IFF_PROMISC && 1274 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 1275 ETHER_ADDR_LEN) && 1276 (eh->ether_dhost[0] & 1) == 0)) { 1277 m_freem(m); 1278 continue; 1279 } 1280 } 1281#endif 1282 (*ifp->if_input)(ifp, m); 1283 } 1284 MY_UNLOCK(sc); 1285 return; 1286} 1287 1288 1289/* 1290 * A frame was downloaded to the chip. It's safe for us to clean up the list 1291 * buffers. 1292 */ 1293static void 1294my_txeof(struct my_softc * sc) 1295{ 1296 struct my_chain *cur_tx; 1297 struct ifnet *ifp; 1298 1299 MY_LOCK(sc); 1300 ifp = &sc->arpcom.ac_if; 1301 /* Clear the timeout timer. */ 1302 ifp->if_timer = 0; 1303 if (sc->my_cdata.my_tx_head == NULL) { 1304 MY_UNLOCK(sc); 1305 return; 1306 } 1307 /* 1308 * Go through our tx list and free mbufs for those frames that have 1309 * been transmitted. 1310 */ 1311 while (sc->my_cdata.my_tx_head->my_mbuf != NULL) { 1312 u_int32_t txstat; 1313 1314 cur_tx = sc->my_cdata.my_tx_head; 1315 txstat = MY_TXSTATUS(cur_tx); 1316 if ((txstat & MY_OWNByNIC) || txstat == MY_UNSENT) 1317 break; 1318 if (!(CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced)) { 1319 if (txstat & MY_TXERR) { 1320 ifp->if_oerrors++; 1321 if (txstat & MY_EC) /* excessive collision */ 1322 ifp->if_collisions++; 1323 if (txstat & MY_LC) /* late collision */ 1324 ifp->if_collisions++; 1325 } 1326 ifp->if_collisions += (txstat & MY_NCRMASK) >> 1327 MY_NCRShift; 1328 } 1329 ifp->if_opackets++; 1330 m_freem(cur_tx->my_mbuf); 1331 cur_tx->my_mbuf = NULL; 1332 if (sc->my_cdata.my_tx_head == sc->my_cdata.my_tx_tail) { 1333 sc->my_cdata.my_tx_head = NULL; 1334 sc->my_cdata.my_tx_tail = NULL; 1335 break; 1336 } 1337 sc->my_cdata.my_tx_head = cur_tx->my_nextdesc; 1338 } 1339 if (CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced) { 1340 ifp->if_collisions += (CSR_READ_4(sc, MY_TSR) & MY_NCRMask); 1341 } 1342 MY_UNLOCK(sc); 1343 return; 1344} 1345 1346/* 1347 * TX 'end of channel' interrupt handler. 1348 */ 1349static void 1350my_txeoc(struct my_softc * sc) 1351{ 1352 struct ifnet *ifp; 1353 1354 MY_LOCK(sc); 1355 ifp = &sc->arpcom.ac_if; 1356 ifp->if_timer = 0; 1357 if (sc->my_cdata.my_tx_head == NULL) { 1358 ifp->if_flags &= ~IFF_OACTIVE; 1359 sc->my_cdata.my_tx_tail = NULL; 1360 if (sc->my_want_auto) 1361 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1); 1362 } else { 1363 if (MY_TXOWN(sc->my_cdata.my_tx_head) == MY_UNSENT) { 1364 MY_TXOWN(sc->my_cdata.my_tx_head) = MY_OWNByNIC; 1365 ifp->if_timer = 5; 1366 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); 1367 } 1368 } 1369 MY_UNLOCK(sc); 1370 return; 1371} 1372 1373static void 1374my_intr(void *arg) 1375{ 1376 struct my_softc *sc; 1377 struct ifnet *ifp; 1378 u_int32_t status; 1379 1380 sc = arg; 1381 MY_LOCK(sc); 1382 ifp = &sc->arpcom.ac_if; 1383 if (!(ifp->if_flags & IFF_UP)) { 1384 MY_UNLOCK(sc); 1385 return; 1386 } 1387 /* Disable interrupts. */ 1388 CSR_WRITE_4(sc, MY_IMR, 0x00000000); 1389 1390 for (;;) { 1391 status = CSR_READ_4(sc, MY_ISR); 1392 status &= MY_INTRS; 1393 if (status) 1394 CSR_WRITE_4(sc, MY_ISR, status); 1395 else 1396 break; 1397 1398 if (status & MY_RI) /* receive interrupt */ 1399 my_rxeof(sc); 1400 1401 if ((status & MY_RBU) || (status & MY_RxErr)) { 1402 /* rx buffer unavailable or rx error */ 1403 ifp->if_ierrors++; 1404#ifdef foo 1405 my_stop(sc); 1406 my_reset(sc); 1407 my_init(sc); 1408#endif 1409 } 1410 if (status & MY_TI) /* tx interrupt */ 1411 my_txeof(sc); 1412 if (status & MY_ETI) /* tx early interrupt */ 1413 my_txeof(sc); 1414 if (status & MY_TBU) /* tx buffer unavailable */ 1415 my_txeoc(sc); 1416 1417#if 0 /* 90/1/18 delete */ 1418 if (status & MY_FBE) { 1419 my_reset(sc); 1420 my_init(sc); 1421 } 1422#endif 1423 1424 } 1425 1426 /* Re-enable interrupts. */ 1427 CSR_WRITE_4(sc, MY_IMR, MY_INTRS); 1428 if (ifp->if_snd.ifq_head != NULL) 1429 my_start(ifp); 1430 MY_UNLOCK(sc); 1431 return; 1432} 1433 1434/* 1435 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1436 * pointers to the fragment pointers. 1437 */ 1438static int 1439my_encap(struct my_softc * sc, struct my_chain * c, struct mbuf * m_head) 1440{ 1441 struct my_desc *f = NULL; 1442 int total_len; 1443 struct mbuf *m, *m_new = NULL; 1444 1445 MY_LOCK(sc); 1446 /* calculate the total tx pkt length */ 1447 total_len = 0; 1448 for (m = m_head; m != NULL; m = m->m_next) 1449 total_len += m->m_len; 1450 /* 1451 * Start packing the mbufs in this chain into the fragment pointers. 1452 * Stop when we run out of fragments or hit the end of the mbuf 1453 * chain. 1454 */ 1455 m = m_head; 1456 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1457 if (m_new == NULL) { 1458 printf("my%d: no memory for tx list", sc->my_unit); 1459 MY_UNLOCK(sc); 1460 return (1); 1461 } 1462 if (m_head->m_pkthdr.len > MHLEN) { 1463 MCLGET(m_new, M_DONTWAIT); 1464 if (!(m_new->m_flags & M_EXT)) { 1465 m_freem(m_new); 1466 printf("my%d: no memory for tx list", sc->my_unit); 1467 MY_UNLOCK(sc); 1468 return (1); 1469 } 1470 } 1471 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t)); 1472 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1473 m_freem(m_head); 1474 m_head = m_new; 1475 f = &c->my_ptr->my_frag[0]; 1476 f->my_status = 0; 1477 f->my_data = vtophys(mtod(m_new, caddr_t)); 1478 total_len = m_new->m_len; 1479 f->my_ctl = MY_TXFD | MY_TXLD | MY_CRCEnable | MY_PADEnable; 1480 f->my_ctl |= total_len << MY_PKTShift; /* pkt size */ 1481 f->my_ctl |= total_len; /* buffer size */ 1482 /* 89/12/29 add, for mtd891 *//* [ 89? ] */ 1483 if (sc->my_info->my_did == MTD891ID) 1484 f->my_ctl |= MY_ETIControl | MY_RetryTxLC; 1485 c->my_mbuf = m_head; 1486 c->my_lastdesc = 0; 1487 MY_TXNEXT(c) = vtophys(&c->my_nextdesc->my_ptr->my_frag[0]); 1488 MY_UNLOCK(sc); 1489 return (0); 1490} 1491 1492/* 1493 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1494 * to the mbuf data regions directly in the transmit lists. We also save a 1495 * copy of the pointers since the transmit list fragment pointers are 1496 * physical addresses. 1497 */ 1498static void 1499my_start(struct ifnet * ifp) 1500{ 1501 struct my_softc *sc; 1502 struct mbuf *m_head = NULL; 1503 struct my_chain *cur_tx = NULL, *start_tx; 1504 1505 sc = ifp->if_softc; 1506 MY_LOCK(sc); 1507 if (sc->my_autoneg) { 1508 sc->my_tx_pend = 1; 1509 MY_UNLOCK(sc); 1510 return; 1511 } 1512 /* 1513 * Check for an available queue slot. If there are none, punt. 1514 */ 1515 if (sc->my_cdata.my_tx_free->my_mbuf != NULL) { 1516 ifp->if_flags |= IFF_OACTIVE; 1517 MY_UNLOCK(sc); 1518 return; 1519 } 1520 start_tx = sc->my_cdata.my_tx_free; 1521 while (sc->my_cdata.my_tx_free->my_mbuf == NULL) { 1522 IF_DEQUEUE(&ifp->if_snd, m_head); 1523 if (m_head == NULL) 1524 break; 1525 1526 /* Pick a descriptor off the free list. */ 1527 cur_tx = sc->my_cdata.my_tx_free; 1528 sc->my_cdata.my_tx_free = cur_tx->my_nextdesc; 1529 1530 /* Pack the data into the descriptor. */ 1531 my_encap(sc, cur_tx, m_head); 1532 1533 if (cur_tx != start_tx) 1534 MY_TXOWN(cur_tx) = MY_OWNByNIC; 1535#if NBPFILTER > 0 1536 /* 1537 * If there's a BPF listener, bounce a copy of this frame to 1538 * him. 1539 */ 1540 BPF_MTAP(ifp, cur_tx->my_mbuf); 1541#endif 1542 } 1543 /* 1544 * If there are no packets queued, bail. 1545 */ 1546 if (cur_tx == NULL) { 1547 MY_UNLOCK(sc); 1548 return; 1549 } 1550 /* 1551 * Place the request for the upload interrupt in the last descriptor 1552 * in the chain. This way, if we're chaining several packets at once, 1553 * we'll only get an interupt once for the whole chain rather than 1554 * once for each packet. 1555 */ 1556 MY_TXCTL(cur_tx) |= MY_TXIC; 1557 cur_tx->my_ptr->my_frag[0].my_ctl |= MY_TXIC; 1558 sc->my_cdata.my_tx_tail = cur_tx; 1559 if (sc->my_cdata.my_tx_head == NULL) 1560 sc->my_cdata.my_tx_head = start_tx; 1561 MY_TXOWN(start_tx) = MY_OWNByNIC; 1562 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); /* tx polling demand */ 1563 1564 /* 1565 * Set a timeout in case the chip goes out to lunch. 1566 */ 1567 ifp->if_timer = 5; 1568 MY_UNLOCK(sc); 1569 return; 1570} 1571 1572static void 1573my_init(void *xsc) 1574{ 1575 struct my_softc *sc = xsc; 1576 struct ifnet *ifp = &sc->arpcom.ac_if; 1577 int s; 1578 u_int16_t phy_bmcr = 0; 1579 1580 MY_LOCK(sc); 1581 if (sc->my_autoneg) { 1582 MY_UNLOCK(sc); 1583 return; 1584 } 1585 s = splimp(); 1586 if (sc->my_pinfo != NULL) 1587 phy_bmcr = my_phy_readreg(sc, PHY_BMCR); 1588 /* 1589 * Cancel pending I/O and free all RX/TX buffers. 1590 */ 1591 my_stop(sc); 1592 my_reset(sc); 1593 1594 /* 1595 * Set cache alignment and burst length. 1596 */ 1597#if 0 /* 89/9/1 modify, */ 1598 CSR_WRITE_4(sc, MY_BCR, MY_RPBLE512); 1599 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF); 1600#endif 1601 CSR_WRITE_4(sc, MY_BCR, MY_PBL8); 1602 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF | MY_RBLEN | MY_RPBLE512); 1603 /* 1604 * 89/12/29 add, for mtd891, 1605 */ 1606 if (sc->my_info->my_did == MTD891ID) { 1607 MY_SETBIT(sc, MY_BCR, MY_PROG); 1608 MY_SETBIT(sc, MY_TCRRCR, MY_Enhanced); 1609 } 1610 my_setcfg(sc, phy_bmcr); 1611 /* Init circular RX list. */ 1612 if (my_list_rx_init(sc) == ENOBUFS) { 1613 printf("my%d: init failed: no memory for rx buffers\n", 1614 sc->my_unit); 1615 my_stop(sc); 1616 (void)splx(s); 1617 MY_UNLOCK(sc); 1618 return; 1619 } 1620 /* Init TX descriptors. */ 1621 my_list_tx_init(sc); 1622 1623 /* If we want promiscuous mode, set the allframes bit. */ 1624 if (ifp->if_flags & IFF_PROMISC) 1625 MY_SETBIT(sc, MY_TCRRCR, MY_PROM); 1626 else 1627 MY_CLRBIT(sc, MY_TCRRCR, MY_PROM); 1628 1629 /* 1630 * Set capture broadcast bit to capture broadcast frames. 1631 */ 1632 if (ifp->if_flags & IFF_BROADCAST) 1633 MY_SETBIT(sc, MY_TCRRCR, MY_AB); 1634 else 1635 MY_CLRBIT(sc, MY_TCRRCR, MY_AB); 1636 1637 /* 1638 * Program the multicast filter, if necessary. 1639 */ 1640 my_setmulti(sc); 1641 1642 /* 1643 * Load the address of the RX list. 1644 */ 1645 MY_CLRBIT(sc, MY_TCRRCR, MY_RE); 1646 CSR_WRITE_4(sc, MY_RXLBA, vtophys(&sc->my_ldata->my_rx_list[0])); 1647 1648 /* 1649 * Enable interrupts. 1650 */ 1651 CSR_WRITE_4(sc, MY_IMR, MY_INTRS); 1652 CSR_WRITE_4(sc, MY_ISR, 0xFFFFFFFF); 1653 1654 /* Enable receiver and transmitter. */ 1655 MY_SETBIT(sc, MY_TCRRCR, MY_RE); 1656 MY_CLRBIT(sc, MY_TCRRCR, MY_TE); 1657 CSR_WRITE_4(sc, MY_TXLBA, vtophys(&sc->my_ldata->my_tx_list[0])); 1658 MY_SETBIT(sc, MY_TCRRCR, MY_TE); 1659 1660 /* Restore state of BMCR */ 1661 if (sc->my_pinfo != NULL) 1662 my_phy_writereg(sc, PHY_BMCR, phy_bmcr); 1663 ifp->if_flags |= IFF_RUNNING; 1664 ifp->if_flags &= ~IFF_OACTIVE; 1665 (void)splx(s); 1666 MY_UNLOCK(sc); 1667 return; 1668} 1669 1670/* 1671 * Set media options. 1672 */ 1673 1674static int 1675my_ifmedia_upd(struct ifnet * ifp) 1676{ 1677 struct my_softc *sc; 1678 struct ifmedia *ifm; 1679 1680 sc = ifp->if_softc; 1681 MY_LOCK(sc); 1682 ifm = &sc->ifmedia; 1683 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) { 1684 MY_UNLOCK(sc); 1685 return (EINVAL); 1686 } 1687 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) 1688 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1); 1689 else 1690 my_setmode_mii(sc, ifm->ifm_media); 1691 MY_UNLOCK(sc); 1692 return (0); 1693} 1694 1695/* 1696 * Report current media status. 1697 */ 1698 1699static void 1700my_ifmedia_sts(struct ifnet * ifp, struct ifmediareq * ifmr) 1701{ 1702 struct my_softc *sc; 1703 u_int16_t advert = 0, ability = 0; 1704 1705 sc = ifp->if_softc; 1706 MY_LOCK(sc); 1707 ifmr->ifm_active = IFM_ETHER; 1708 if (!(my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) { 1709#if 0 /* this version did not support 1000M, */ 1710 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_1000) 1711 ifmr->ifm_active = IFM_ETHER | IFM_1000TX; 1712#endif 1713 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL) 1714 ifmr->ifm_active = IFM_ETHER | IFM_100_TX; 1715 else 1716 ifmr->ifm_active = IFM_ETHER | IFM_10_T; 1717 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX) 1718 ifmr->ifm_active |= IFM_FDX; 1719 else 1720 ifmr->ifm_active |= IFM_HDX; 1721 1722 MY_UNLOCK(sc); 1723 return; 1724 } 1725 ability = my_phy_readreg(sc, PHY_LPAR); 1726 advert = my_phy_readreg(sc, PHY_ANAR); 1727 1728#if 0 /* this version did not support 1000M, */ 1729 if (sc->my_pinfo->my_vid = MarvellPHYID0) { 1730 ability2 = my_phy_readreg(sc, PHY_1000SR); 1731 if (ability2 & PHY_1000SR_1000BTXFULL) { 1732 advert = 0; 1733 ability = 0; 1734 ifmr->ifm_active = IFM_ETHER|IFM_1000_T|IFM_FDX; 1735 } else if (ability & PHY_1000SR_1000BTXHALF) { 1736 advert = 0; 1737 ability = 0; 1738 ifmr->ifm_active = IFM_ETHER|IFM_1000_T|IFM_HDX; 1739 } 1740 } 1741#endif 1742 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) 1743 ifmr->ifm_active = IFM_ETHER | IFM_100_T4; 1744 else if (advert & PHY_ANAR_100BTXFULL && ability & PHY_ANAR_100BTXFULL) 1745 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1746 else if (advert & PHY_ANAR_100BTXHALF && ability & PHY_ANAR_100BTXHALF) 1747 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_HDX; 1748 else if (advert & PHY_ANAR_10BTFULL && ability & PHY_ANAR_10BTFULL) 1749 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_FDX; 1750 else if (advert & PHY_ANAR_10BTHALF && ability & PHY_ANAR_10BTHALF) 1751 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_HDX; 1752 MY_UNLOCK(sc); 1753 return; 1754} 1755 1756static int 1757my_ioctl(struct ifnet * ifp, u_long command, caddr_t data) 1758{ 1759 struct my_softc *sc = ifp->if_softc; 1760 struct ifreq *ifr = (struct ifreq *) data; 1761 int s, error = 0; 1762 1763 s = splimp(); 1764 MY_LOCK(sc); 1765 switch (command) { 1766 case SIOCSIFFLAGS: 1767 if (ifp->if_flags & IFF_UP) 1768 my_init(sc); 1769 else if (ifp->if_flags & IFF_RUNNING) 1770 my_stop(sc); 1771 error = 0; 1772 break; 1773 case SIOCADDMULTI: 1774 case SIOCDELMULTI: 1775 my_setmulti(sc); 1776 error = 0; 1777 break; 1778 case SIOCGIFMEDIA: 1779 case SIOCSIFMEDIA: 1780 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 1781 break; 1782 default: 1783 error = ether_ioctl(ifp, command, data); 1784 break; 1785 } 1786 MY_UNLOCK(sc); 1787 (void)splx(s); 1788 return (error); 1789} 1790 1791static void 1792my_watchdog(struct ifnet * ifp) 1793{ 1794 struct my_softc *sc; 1795 1796 sc = ifp->if_softc; 1797 MY_LOCK(sc); 1798 if (sc->my_autoneg) { 1799 my_autoneg_mii(sc, MY_FLAG_DELAYTIMEO, 1); 1800 MY_UNLOCK(sc); 1801 return; 1802 } 1803 ifp->if_oerrors++; 1804 printf("my%d: watchdog timeout\n", sc->my_unit); 1805 if (!(my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1806 printf("my%d: no carrier - transceiver cable problem?\n", 1807 sc->my_unit); 1808 my_stop(sc); 1809 my_reset(sc); 1810 my_init(sc); 1811 if (ifp->if_snd.ifq_head != NULL) 1812 my_start(ifp); 1813 MY_LOCK(sc); 1814 return; 1815} 1816 1817 1818/* 1819 * Stop the adapter and free any mbufs allocated to the RX and TX lists. 1820 */ 1821static void 1822my_stop(struct my_softc * sc) 1823{ 1824 register int i; 1825 struct ifnet *ifp; 1826 1827 MY_LOCK(sc); 1828 ifp = &sc->arpcom.ac_if; 1829 ifp->if_timer = 0; 1830 1831 MY_CLRBIT(sc, MY_TCRRCR, (MY_RE | MY_TE)); 1832 CSR_WRITE_4(sc, MY_IMR, 0x00000000); 1833 CSR_WRITE_4(sc, MY_TXLBA, 0x00000000); 1834 CSR_WRITE_4(sc, MY_RXLBA, 0x00000000); 1835 1836 /* 1837 * Free data in the RX lists. 1838 */ 1839 for (i = 0; i < MY_RX_LIST_CNT; i++) { 1840 if (sc->my_cdata.my_rx_chain[i].my_mbuf != NULL) { 1841 m_freem(sc->my_cdata.my_rx_chain[i].my_mbuf); 1842 sc->my_cdata.my_rx_chain[i].my_mbuf = NULL; 1843 } 1844 } 1845 bzero((char *)&sc->my_ldata->my_rx_list, 1846 sizeof(sc->my_ldata->my_rx_list)); 1847 /* 1848 * Free the TX list buffers. 1849 */ 1850 for (i = 0; i < MY_TX_LIST_CNT; i++) { 1851 if (sc->my_cdata.my_tx_chain[i].my_mbuf != NULL) { 1852 m_freem(sc->my_cdata.my_tx_chain[i].my_mbuf); 1853 sc->my_cdata.my_tx_chain[i].my_mbuf = NULL; 1854 } 1855 } 1856 bzero((char *)&sc->my_ldata->my_tx_list, 1857 sizeof(sc->my_ldata->my_tx_list)); 1858 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1859 MY_UNLOCK(sc); 1860 return; 1861} 1862 1863/* 1864 * Stop all chip I/O so that the kernel's probe routines don't get confused 1865 * by errant DMAs when rebooting. 1866 */ 1867static void 1868my_shutdown(device_t dev) 1869{ 1870 struct my_softc *sc; 1871 1872 sc = device_get_softc(dev); 1873 my_stop(sc); 1874 return; 1875} 1876