if_my.c revision 95939
1/* 2 * Copyright (c) 2002 Myson Technology Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions, and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. The name of the author may not be used to endorse or promote products 12 * derived from this software without specific prior written permission. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 18 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * Written by: yen_cw@myson.com.tw available at: http://www.myson.com.tw/ 27 * 28 * $FreeBSD: head/sys/dev/my/if_my.c 95939 2002-05-02 15:58:04Z julian $ 29 * 30 * Myson fast ethernet PCI NIC driver 31 */ 32#include <sys/param.h> 33#include <sys/systm.h> 34#include <sys/sockio.h> 35#include <sys/mbuf.h> 36#include <sys/malloc.h> 37#include <sys/kernel.h> 38#include <sys/socket.h> 39#include <sys/queue.h> 40#include <sys/types.h> 41#include <sys/bus.h> 42#include <sys/module.h> 43#include <sys/lock.h> 44#include <sys/mutex.h> 45 46#define NBPFILTER 1 47 48#include <net/if.h> 49#include <net/if_arp.h> 50#include <net/ethernet.h> 51#include <net/if_media.h> 52#include <net/if_dl.h> 53#include <net/bpf.h> 54 55#include <vm/vm.h> /* for vtophys */ 56#include <vm/pmap.h> /* for vtophys */ 57#include <machine/clock.h> /* for DELAY */ 58#include <machine/bus_memio.h> 59#include <machine/bus_pio.h> 60#include <machine/bus.h> 61#include <machine/resource.h> 62#include <sys/bus.h> 63#include <sys/rman.h> 64 65#include <pci/pcireg.h> 66#include <pci/pcivar.h> 67 68#include <dev/mii/mii.h> 69#include <dev/mii/miivar.h> 70 71#include "miibus_if.h" 72 73/* 74 * #define MY_USEIOSPACE 75 */ 76 77static int MY_USEIOSPACE = 1; 78 79#if (MY_USEIOSPACE) 80#define MY_RES SYS_RES_IOPORT 81#define MY_RID MY_PCI_LOIO 82#else 83#define MY_RES SYS_RES_MEMORY 84#define MY_RID MY_PCI_LOMEM 85#endif 86 87 88#include <dev/my/if_myreg.h> 89 90#ifndef lint 91static const char rcsid[] = 92"$Id: if_my.c,v 1.50 2001/12/03 04:15:33 <yen_cw@myson.com.tw> wpaul Exp $"; 93#endif 94 95/* 96 * Various supported device vendors/types and their names. 97 */ 98struct my_type *my_info_tmp; 99static struct my_type my_devs[] = { 100 {MYSONVENDORID, MTD800ID, "Myson MTD80X Based Fast Ethernet Card"}, 101 {MYSONVENDORID, MTD803ID, "Myson MTD80X Based Fast Ethernet Card"}, 102 {MYSONVENDORID, MTD891ID, "Myson MTD89X Based Giga Ethernet Card"}, 103 {0, 0, NULL} 104}; 105 106/* 107 * Various supported PHY vendors/types and their names. Note that this driver 108 * will work with pretty much any MII-compliant PHY, so failure to positively 109 * identify the chip is not a fatal error. 110 */ 111static struct my_type my_phys[] = { 112 {MysonPHYID0, MysonPHYID0, "<MYSON MTD981>"}, 113 {SeeqPHYID0, SeeqPHYID0, "<SEEQ 80225>"}, 114 {AhdocPHYID0, AhdocPHYID0, "<AHDOC 101>"}, 115 {MarvellPHYID0, MarvellPHYID0, "<MARVELL 88E1000>"}, 116 {LevelOnePHYID0, LevelOnePHYID0, "<LevelOne LXT1000>"}, 117 {0, 0, "<MII-compliant physical interface>"} 118}; 119 120static int my_probe(device_t); 121static int my_attach(device_t); 122static int my_detach(device_t); 123static int my_newbuf(struct my_softc *, struct my_chain_onefrag *); 124static int my_encap(struct my_softc *, struct my_chain *, struct mbuf *); 125static void my_rxeof(struct my_softc *); 126static void my_txeof(struct my_softc *); 127static void my_txeoc(struct my_softc *); 128static void my_intr(void *); 129static void my_start(struct ifnet *); 130static int my_ioctl(struct ifnet *, u_long, caddr_t); 131static void my_init(void *); 132static void my_stop(struct my_softc *); 133static void my_watchdog(struct ifnet *); 134static void my_shutdown(device_t); 135static int my_ifmedia_upd(struct ifnet *); 136static void my_ifmedia_sts(struct ifnet *, struct ifmediareq *); 137static u_int16_t my_phy_readreg(struct my_softc *, int); 138static void my_phy_writereg(struct my_softc *, int, int); 139static void my_autoneg_xmit(struct my_softc *); 140static void my_autoneg_mii(struct my_softc *, int, int); 141static void my_setmode_mii(struct my_softc *, int); 142static void my_getmode_mii(struct my_softc *); 143static void my_setcfg(struct my_softc *, int); 144static u_int8_t my_calchash(caddr_t); 145static void my_setmulti(struct my_softc *); 146static void my_reset(struct my_softc *); 147static int my_list_rx_init(struct my_softc *); 148static int my_list_tx_init(struct my_softc *); 149static long my_send_cmd_to_phy(struct my_softc *, int, int); 150 151#define MY_SETBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 152#define MY_CLRBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 153 154static device_method_t my_methods[] = { 155 /* Device interface */ 156 DEVMETHOD(device_probe, my_probe), 157 DEVMETHOD(device_attach, my_attach), 158 DEVMETHOD(device_detach, my_detach), 159 DEVMETHOD(device_shutdown, my_shutdown), 160 161 {0, 0} 162}; 163 164static driver_t my_driver = { 165 "my", 166 my_methods, 167 sizeof(struct my_softc) 168}; 169 170static devclass_t my_devclass; 171 172DRIVER_MODULE(if_my, pci, my_driver, my_devclass, 0, 0); 173 174static long 175my_send_cmd_to_phy(struct my_softc * sc, int opcode, int regad) 176{ 177 long miir; 178 int i; 179 int mask, data; 180 181 MY_LOCK(sc); 182 183 /* enable MII output */ 184 miir = CSR_READ_4(sc, MY_MANAGEMENT); 185 miir &= 0xfffffff0; 186 187 miir |= MY_MASK_MIIR_MII_WRITE + MY_MASK_MIIR_MII_MDO; 188 189 /* send 32 1's preamble */ 190 for (i = 0; i < 32; i++) { 191 /* low MDC; MDO is already high (miir) */ 192 miir &= ~MY_MASK_MIIR_MII_MDC; 193 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 194 195 /* high MDC */ 196 miir |= MY_MASK_MIIR_MII_MDC; 197 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 198 } 199 200 /* calculate ST+OP+PHYAD+REGAD+TA */ 201 data = opcode | (sc->my_phy_addr << 7) | (regad << 2); 202 203 /* sent out */ 204 mask = 0x8000; 205 while (mask) { 206 /* low MDC, prepare MDO */ 207 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO); 208 if (mask & data) 209 miir |= MY_MASK_MIIR_MII_MDO; 210 211 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 212 /* high MDC */ 213 miir |= MY_MASK_MIIR_MII_MDC; 214 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 215 DELAY(30); 216 217 /* next */ 218 mask >>= 1; 219 if (mask == 0x2 && opcode == MY_OP_READ) 220 miir &= ~MY_MASK_MIIR_MII_WRITE; 221 } 222 223 MY_UNLOCK(sc); 224 return miir; 225} 226 227 228static u_int16_t 229my_phy_readreg(struct my_softc * sc, int reg) 230{ 231 long miir; 232 int mask, data; 233 234 MY_LOCK(sc); 235 236 if (sc->my_info->my_did == MTD803ID) 237 data = CSR_READ_2(sc, MY_PHYBASE + reg * 2); 238 else { 239 miir = my_send_cmd_to_phy(sc, MY_OP_READ, reg); 240 241 /* read data */ 242 mask = 0x8000; 243 data = 0; 244 while (mask) { 245 /* low MDC */ 246 miir &= ~MY_MASK_MIIR_MII_MDC; 247 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 248 249 /* read MDI */ 250 miir = CSR_READ_4(sc, MY_MANAGEMENT); 251 if (miir & MY_MASK_MIIR_MII_MDI) 252 data |= mask; 253 254 /* high MDC, and wait */ 255 miir |= MY_MASK_MIIR_MII_MDC; 256 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 257 DELAY(30); 258 259 /* next */ 260 mask >>= 1; 261 } 262 263 /* low MDC */ 264 miir &= ~MY_MASK_MIIR_MII_MDC; 265 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 266 } 267 268 MY_UNLOCK(sc); 269 return (u_int16_t) data; 270} 271 272 273static void 274my_phy_writereg(struct my_softc * sc, int reg, int data) 275{ 276 long miir; 277 int mask; 278 279 MY_LOCK(sc); 280 281 if (sc->my_info->my_did == MTD803ID) 282 CSR_WRITE_2(sc, MY_PHYBASE + reg * 2, data); 283 else { 284 miir = my_send_cmd_to_phy(sc, MY_OP_WRITE, reg); 285 286 /* write data */ 287 mask = 0x8000; 288 while (mask) { 289 /* low MDC, prepare MDO */ 290 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO); 291 if (mask & data) 292 miir |= MY_MASK_MIIR_MII_MDO; 293 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 294 DELAY(1); 295 296 /* high MDC */ 297 miir |= MY_MASK_MIIR_MII_MDC; 298 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 299 DELAY(1); 300 301 /* next */ 302 mask >>= 1; 303 } 304 305 /* low MDC */ 306 miir &= ~MY_MASK_MIIR_MII_MDC; 307 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 308 } 309 MY_UNLOCK(sc); 310 return; 311} 312 313static u_int8_t 314my_calchash(caddr_t addr) 315{ 316 u_int32_t crc, carry; 317 int i, j; 318 u_int8_t c; 319 320 /* Compute CRC for the address value. */ 321 crc = 0xFFFFFFFF; /* initial value */ 322 323 for (i = 0; i < 6; i++) { 324 c = *(addr + i); 325 for (j = 0; j < 8; j++) { 326 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 327 crc <<= 1; 328 c >>= 1; 329 if (carry) 330 crc = (crc ^ 0x04c11db6) | carry; 331 } 332 } 333 334 /* 335 * return the filter bit position Note: I arrived at the following 336 * nonsense through experimentation. It's not the usual way to 337 * generate the bit position but it's the only thing I could come up 338 * with that works. 339 */ 340 return (~(crc >> 26) & 0x0000003F); 341} 342 343 344/* 345 * Program the 64-bit multicast hash filter. 346 */ 347static void 348my_setmulti(struct my_softc * sc) 349{ 350 struct ifnet *ifp; 351 int h = 0; 352 u_int32_t hashes[2] = {0, 0}; 353 struct ifmultiaddr *ifma; 354 u_int32_t rxfilt; 355 int mcnt = 0; 356 357 MY_LOCK(sc); 358 359 ifp = &sc->arpcom.ac_if; 360 361 rxfilt = CSR_READ_4(sc, MY_TCRRCR); 362 363 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 364 rxfilt |= MY_AM; 365 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt); 366 CSR_WRITE_4(sc, MY_MAR0, 0xFFFFFFFF); 367 CSR_WRITE_4(sc, MY_MAR1, 0xFFFFFFFF); 368 369 MY_UNLOCK(sc); 370 371 return; 372 } 373 /* first, zot all the existing hash bits */ 374 CSR_WRITE_4(sc, MY_MAR0, 0); 375 CSR_WRITE_4(sc, MY_MAR1, 0); 376 377 /* now program new ones */ 378 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 379 if (ifma->ifma_addr->sa_family != AF_LINK) 380 continue; 381 h = my_calchash(LLADDR((struct sockaddr_dl *) ifma->ifma_addr)); 382 if (h < 32) 383 hashes[0] |= (1 << h); 384 else 385 hashes[1] |= (1 << (h - 32)); 386 mcnt++; 387 } 388 389 if (mcnt) 390 rxfilt |= MY_AM; 391 else 392 rxfilt &= ~MY_AM; 393 CSR_WRITE_4(sc, MY_MAR0, hashes[0]); 394 CSR_WRITE_4(sc, MY_MAR1, hashes[1]); 395 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt); 396 MY_UNLOCK(sc); 397 return; 398} 399 400/* 401 * Initiate an autonegotiation session. 402 */ 403static void 404my_autoneg_xmit(struct my_softc * sc) 405{ 406 u_int16_t phy_sts = 0; 407 408 MY_LOCK(sc); 409 410 my_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); 411 DELAY(500); 412 while (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_RESET); 413 414 phy_sts = my_phy_readreg(sc, PHY_BMCR); 415 phy_sts |= PHY_BMCR_AUTONEGENBL | PHY_BMCR_AUTONEGRSTR; 416 my_phy_writereg(sc, PHY_BMCR, phy_sts); 417 418 MY_UNLOCK(sc); 419 return; 420} 421 422 423/* 424 * Invoke autonegotiation on a PHY. 425 */ 426static void 427my_autoneg_mii(struct my_softc * sc, int flag, int verbose) 428{ 429 u_int16_t phy_sts = 0, media, advert, ability; 430 u_int16_t ability2 = 0; 431 struct ifnet *ifp; 432 struct ifmedia *ifm; 433 434 MY_LOCK(sc); 435 436 ifm = &sc->ifmedia; 437 ifp = &sc->arpcom.ac_if; 438 439 ifm->ifm_media = IFM_ETHER | IFM_AUTO; 440 441#ifndef FORCE_AUTONEG_TFOUR 442 /* 443 * First, see if autoneg is supported. If not, there's no point in 444 * continuing. 445 */ 446 phy_sts = my_phy_readreg(sc, PHY_BMSR); 447 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) { 448 if (verbose) 449 printf("my%d: autonegotiation not supported\n", 450 sc->my_unit); 451 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 452 MY_UNLOCK(sc); 453 return; 454 } 455#endif 456 switch (flag) { 457 case MY_FLAG_FORCEDELAY: 458 /* 459 * XXX Never use this option anywhere but in the probe 460 * routine: making the kernel stop dead in its tracks for 461 * three whole seconds after we've gone multi-user is really 462 * bad manners. 463 */ 464 my_autoneg_xmit(sc); 465 DELAY(5000000); 466 break; 467 case MY_FLAG_SCHEDDELAY: 468 /* 469 * Wait for the transmitter to go idle before starting an 470 * autoneg session, otherwise my_start() may clobber our 471 * timeout, and we don't want to allow transmission during an 472 * autoneg session since that can screw it up. 473 */ 474 if (sc->my_cdata.my_tx_head != NULL) { 475 sc->my_want_auto = 1; 476 MY_UNLOCK(sc); 477 return; 478 } 479 my_autoneg_xmit(sc); 480 ifp->if_timer = 5; 481 sc->my_autoneg = 1; 482 sc->my_want_auto = 0; 483 MY_UNLOCK(sc); 484 return; 485 case MY_FLAG_DELAYTIMEO: 486 ifp->if_timer = 0; 487 sc->my_autoneg = 0; 488 break; 489 default: 490 printf("my%d: invalid autoneg flag: %d\n", sc->my_unit, flag); 491 MY_UNLOCK(sc); 492 return; 493 } 494 495 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) { 496 if (verbose) 497 printf("my%d: autoneg complete, ", sc->my_unit); 498 phy_sts = my_phy_readreg(sc, PHY_BMSR); 499 } else { 500 if (verbose) 501 printf("my%d: autoneg not complete, ", sc->my_unit); 502 } 503 504 media = my_phy_readreg(sc, PHY_BMCR); 505 506 /* Link is good. Report modes and set duplex mode. */ 507 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) { 508 if (verbose) 509 printf("my%d: link status good. ", sc->my_unit); 510 advert = my_phy_readreg(sc, PHY_ANAR); 511 ability = my_phy_readreg(sc, PHY_LPAR); 512 if ((sc->my_pinfo->my_vid == MarvellPHYID0) || 513 (sc->my_pinfo->my_vid == LevelOnePHYID0)) { 514 ability2 = my_phy_readreg(sc, PHY_1000SR); 515 if (ability2 & PHY_1000SR_1000BTXFULL) { 516 advert = 0; 517 ability = 0; 518 /* 519 * this version did not support 1000M, 520 * ifm->ifm_media = 521 * IFM_ETHER|IFM_1000_T|IFM_FDX; 522 */ 523 ifm->ifm_media = 524 IFM_ETHER | IFM_100_TX | IFM_FDX; 525 media &= ~PHY_BMCR_SPEEDSEL; 526 media |= PHY_BMCR_1000; 527 media |= PHY_BMCR_DUPLEX; 528 printf("(full-duplex, 1000Mbps)\n"); 529 } else if (ability2 & PHY_1000SR_1000BTXHALF) { 530 advert = 0; 531 ability = 0; 532 /* 533 * this version did not support 1000M, 534 * ifm->ifm_media = IFM_ETHER|IFM_1000_T; 535 */ 536 ifm->ifm_media = IFM_ETHER | IFM_100_TX; 537 media &= ~PHY_BMCR_SPEEDSEL; 538 media &= ~PHY_BMCR_DUPLEX; 539 media |= PHY_BMCR_1000; 540 printf("(half-duplex, 1000Mbps)\n"); 541 } 542 } 543 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) { 544 ifm->ifm_media = IFM_ETHER | IFM_100_T4; 545 media |= PHY_BMCR_SPEEDSEL; 546 media &= ~PHY_BMCR_DUPLEX; 547 printf("(100baseT4)\n"); 548 } else if (advert & PHY_ANAR_100BTXFULL && 549 ability & PHY_ANAR_100BTXFULL) { 550 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX; 551 media |= PHY_BMCR_SPEEDSEL; 552 media |= PHY_BMCR_DUPLEX; 553 printf("(full-duplex, 100Mbps)\n"); 554 } else if (advert & PHY_ANAR_100BTXHALF && 555 ability & PHY_ANAR_100BTXHALF) { 556 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX; 557 media |= PHY_BMCR_SPEEDSEL; 558 media &= ~PHY_BMCR_DUPLEX; 559 printf("(half-duplex, 100Mbps)\n"); 560 } else if (advert & PHY_ANAR_10BTFULL && 561 ability & PHY_ANAR_10BTFULL) { 562 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX; 563 media &= ~PHY_BMCR_SPEEDSEL; 564 media |= PHY_BMCR_DUPLEX; 565 printf("(full-duplex, 10Mbps)\n"); 566 } else if (advert) { 567 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 568 media &= ~PHY_BMCR_SPEEDSEL; 569 media &= ~PHY_BMCR_DUPLEX; 570 printf("(half-duplex, 10Mbps)\n"); 571 } 572 media &= ~PHY_BMCR_AUTONEGENBL; 573 574 /* Set ASIC's duplex mode to match the PHY. */ 575 my_phy_writereg(sc, PHY_BMCR, media); 576 my_setcfg(sc, media); 577 } else { 578 if (verbose) 579 printf("my%d: no carrier\n", sc->my_unit); 580 } 581 582 my_init(sc); 583 if (sc->my_tx_pend) { 584 sc->my_autoneg = 0; 585 sc->my_tx_pend = 0; 586 my_start(ifp); 587 } 588 MY_UNLOCK(sc); 589 return; 590} 591 592/* 593 * To get PHY ability. 594 */ 595static void 596my_getmode_mii(struct my_softc * sc) 597{ 598 u_int16_t bmsr; 599 struct ifnet *ifp; 600 601 MY_LOCK(sc); 602 ifp = &sc->arpcom.ac_if; 603 bmsr = my_phy_readreg(sc, PHY_BMSR); 604 if (bootverbose) 605 printf("my%d: PHY status word: %x\n", sc->my_unit, bmsr); 606 607 /* fallback */ 608 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 609 610 if (bmsr & PHY_BMSR_10BTHALF) { 611 if (bootverbose) 612 printf("my%d: 10Mbps half-duplex mode supported\n", 613 sc->my_unit); 614 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_HDX, 615 0, NULL); 616 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T, 0, NULL); 617 } 618 if (bmsr & PHY_BMSR_10BTFULL) { 619 if (bootverbose) 620 printf("my%d: 10Mbps full-duplex mode supported\n", 621 sc->my_unit); 622 623 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 624 0, NULL); 625 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX; 626 } 627 if (bmsr & PHY_BMSR_100BTXHALF) { 628 if (bootverbose) 629 printf("my%d: 100Mbps half-duplex mode supported\n", 630 sc->my_unit); 631 ifp->if_baudrate = 100000000; 632 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL); 633 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_HDX, 634 0, NULL); 635 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX; 636 } 637 if (bmsr & PHY_BMSR_100BTXFULL) { 638 if (bootverbose) 639 printf("my%d: 100Mbps full-duplex mode supported\n", 640 sc->my_unit); 641 ifp->if_baudrate = 100000000; 642 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 643 0, NULL); 644 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX; 645 } 646 /* Some also support 100BaseT4. */ 647 if (bmsr & PHY_BMSR_100BT4) { 648 if (bootverbose) 649 printf("my%d: 100baseT4 mode supported\n", sc->my_unit); 650 ifp->if_baudrate = 100000000; 651 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_T4, 0, NULL); 652 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_T4; 653#ifdef FORCE_AUTONEG_TFOUR 654 if (bootverbose) 655 printf("my%d: forcing on autoneg support for BT4\n", 656 sc->my_unit); 657 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0 NULL): 658 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO; 659#endif 660 } 661#if 0 /* this version did not support 1000M, */ 662 if (sc->my_pinfo->my_vid == MarvellPHYID0) { 663 if (bootverbose) 664 printf("my%d: 1000Mbps half-duplex mode supported\n", 665 sc->my_unit); 666 667 ifp->if_baudrate = 1000000000; 668 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL); 669 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_HDX, 670 0, NULL); 671 if (bootverbose) 672 printf("my%d: 1000Mbps full-duplex mode supported\n", 673 sc->my_unit); 674 ifp->if_baudrate = 1000000000; 675 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX, 676 0, NULL); 677 sc->ifmedia.ifm_media = IFM_ETHER | IFM_1000_T | IFM_FDX; 678 } 679#endif 680 if (bmsr & PHY_BMSR_CANAUTONEG) { 681 if (bootverbose) 682 printf("my%d: autoneg supported\n", sc->my_unit); 683 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 684 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO; 685 } 686 MY_UNLOCK(sc); 687 return; 688} 689 690/* 691 * Set speed and duplex mode. 692 */ 693static void 694my_setmode_mii(struct my_softc * sc, int media) 695{ 696 u_int16_t bmcr; 697 struct ifnet *ifp; 698 699 MY_LOCK(sc); 700 ifp = &sc->arpcom.ac_if; 701 /* 702 * If an autoneg session is in progress, stop it. 703 */ 704 if (sc->my_autoneg) { 705 printf("my%d: canceling autoneg session\n", sc->my_unit); 706 ifp->if_timer = sc->my_autoneg = sc->my_want_auto = 0; 707 bmcr = my_phy_readreg(sc, PHY_BMCR); 708 bmcr &= ~PHY_BMCR_AUTONEGENBL; 709 my_phy_writereg(sc, PHY_BMCR, bmcr); 710 } 711 printf("my%d: selecting MII, ", sc->my_unit); 712 bmcr = my_phy_readreg(sc, PHY_BMCR); 713 bmcr &= ~(PHY_BMCR_AUTONEGENBL | PHY_BMCR_SPEEDSEL | PHY_BMCR_1000 | 714 PHY_BMCR_DUPLEX | PHY_BMCR_LOOPBK); 715 716#if 0 /* this version did not support 1000M, */ 717 if (IFM_SUBTYPE(media) == IFM_1000_T) { 718 printf("1000Mbps/T4, half-duplex\n"); 719 bmcr &= ~PHY_BMCR_SPEEDSEL; 720 bmcr &= ~PHY_BMCR_DUPLEX; 721 bmcr |= PHY_BMCR_1000; 722 } 723#endif 724 if (IFM_SUBTYPE(media) == IFM_100_T4) { 725 printf("100Mbps/T4, half-duplex\n"); 726 bmcr |= PHY_BMCR_SPEEDSEL; 727 bmcr &= ~PHY_BMCR_DUPLEX; 728 } 729 if (IFM_SUBTYPE(media) == IFM_100_TX) { 730 printf("100Mbps, "); 731 bmcr |= PHY_BMCR_SPEEDSEL; 732 } 733 if (IFM_SUBTYPE(media) == IFM_10_T) { 734 printf("10Mbps, "); 735 bmcr &= ~PHY_BMCR_SPEEDSEL; 736 } 737 if ((media & IFM_GMASK) == IFM_FDX) { 738 printf("full duplex\n"); 739 bmcr |= PHY_BMCR_DUPLEX; 740 } else { 741 printf("half duplex\n"); 742 bmcr &= ~PHY_BMCR_DUPLEX; 743 } 744 my_phy_writereg(sc, PHY_BMCR, bmcr); 745 my_setcfg(sc, bmcr); 746 MY_UNLOCK(sc); 747 return; 748} 749 750/* 751 * The Myson manual states that in order to fiddle with the 'full-duplex' and 752 * '100Mbps' bits in the netconfig register, we first have to put the 753 * transmit and/or receive logic in the idle state. 754 */ 755static void 756my_setcfg(struct my_softc * sc, int bmcr) 757{ 758 int i, restart = 0; 759 760 MY_LOCK(sc); 761 if (CSR_READ_4(sc, MY_TCRRCR) & (MY_TE | MY_RE)) { 762 restart = 1; 763 MY_CLRBIT(sc, MY_TCRRCR, (MY_TE | MY_RE)); 764 for (i = 0; i < MY_TIMEOUT; i++) { 765 DELAY(10); 766 if (!(CSR_READ_4(sc, MY_TCRRCR) & 767 (MY_TXRUN | MY_RXRUN))) 768 break; 769 } 770 if (i == MY_TIMEOUT) 771 printf("my%d: failed to force tx and rx to idle \n", 772 sc->my_unit); 773 } 774 MY_CLRBIT(sc, MY_TCRRCR, MY_PS1000); 775 MY_CLRBIT(sc, MY_TCRRCR, MY_PS10); 776 if (bmcr & PHY_BMCR_1000) 777 MY_SETBIT(sc, MY_TCRRCR, MY_PS1000); 778 else if (!(bmcr & PHY_BMCR_SPEEDSEL)) 779 MY_SETBIT(sc, MY_TCRRCR, MY_PS10); 780 if (bmcr & PHY_BMCR_DUPLEX) 781 MY_SETBIT(sc, MY_TCRRCR, MY_FD); 782 else 783 MY_CLRBIT(sc, MY_TCRRCR, MY_FD); 784 if (restart) 785 MY_SETBIT(sc, MY_TCRRCR, MY_TE | MY_RE); 786 MY_UNLOCK(sc); 787 return; 788} 789 790static void 791my_reset(struct my_softc * sc) 792{ 793 register int i; 794 795 MY_LOCK(sc); 796 MY_SETBIT(sc, MY_BCR, MY_SWR); 797 for (i = 0; i < MY_TIMEOUT; i++) { 798 DELAY(10); 799 if (!(CSR_READ_4(sc, MY_BCR) & MY_SWR)) 800 break; 801 } 802 if (i == MY_TIMEOUT) 803 printf("m0x%d: reset never completed!\n", sc->my_unit); 804 805 /* Wait a little while for the chip to get its brains in order. */ 806 DELAY(1000); 807 MY_UNLOCK(sc); 808 return; 809} 810 811/* 812 * Probe for a Myson chip. Check the PCI vendor and device IDs against our 813 * list and return a device name if we find a match. 814 */ 815static int 816my_probe(device_t dev) 817{ 818 struct my_type *t; 819 820 t = my_devs; 821 while (t->my_name != NULL) { 822 if ((pci_get_vendor(dev) == t->my_vid) && 823 (pci_get_device(dev) == t->my_did)) { 824 device_set_desc(dev, t->my_name); 825 my_info_tmp = t; 826 return (0); 827 } 828 t++; 829 } 830 return (ENXIO); 831} 832 833/* 834 * Attach the interface. Allocate softc structures, do ifmedia setup and 835 * ethernet/BPF attach. 836 */ 837static int 838my_attach(device_t dev) 839{ 840 int s, i; 841 u_char eaddr[ETHER_ADDR_LEN]; 842 u_int32_t command, iobase; 843 struct my_softc *sc; 844 struct ifnet *ifp; 845 int media = IFM_ETHER | IFM_100_TX | IFM_FDX; 846 unsigned int round; 847 caddr_t roundptr; 848 struct my_type *p; 849 u_int16_t phy_vid, phy_did, phy_sts = 0; 850 int rid, unit, error = 0; 851 852 s = splimp(); 853 sc = device_get_softc(dev); 854 unit = device_get_unit(dev); 855 if (sc == NULL) { 856 printf("my%d: no memory for softc struct!\n", unit); 857 error = ENXIO; 858 goto fail; 859 860 } 861 bzero(sc, sizeof(struct my_softc)); 862 mtx_init(&sc->my_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 863 MTX_DEF | MTX_RECURSE); 864 MY_LOCK(sc); 865 866 /* 867 * Map control/status registers. 868 */ 869#if 0 870 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 871 command |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 872 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command & 0x000000ff, 4); 873 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 874#endif 875 command = pci_read_config(dev, PCIR_COMMAND, 4); 876 command |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 877 pci_write_config(dev, PCIR_COMMAND, command & 0x000000ff, 4); 878 command = pci_read_config(dev, PCIR_COMMAND, 4); 879 880 if (my_info_tmp->my_did == MTD800ID) { 881 iobase = pci_read_config(dev, MY_PCI_LOIO, 4); 882 if (iobase & 0x300) 883 MY_USEIOSPACE = 0; 884 } 885 if (MY_USEIOSPACE) { 886 if (!(command & PCIM_CMD_PORTEN)) { 887 printf("my%d: failed to enable I/O ports!\n", unit); 888 free(sc, M_DEVBUF); 889 error = ENXIO; 890 goto fail; 891 } 892#if 0 893 if (!pci_map_port(config_id, MY_PCI_LOIO, (u_int16_t *) & (sc->my_bhandle))) { 894 printf("my%d: couldn't map ports\n", unit); 895 error = ENXIO; 896 goto fail; 897 } 898 899 sc->my_btag = I386_BUS_SPACE_IO; 900#endif 901 } else { 902 if (!(command & PCIM_CMD_MEMEN)) { 903 printf("my%d: failed to enable memory mapping!\n", 904 unit); 905 error = ENXIO; 906 goto fail; 907 } 908#if 0 909 if (!pci_map_mem(config_id, MY_PCI_LOMEM, &vbase, &pbase)) { 910 printf ("my%d: couldn't map memory\n", unit); 911 error = ENXIO; 912 goto fail; 913 } 914 sc->my_btag = I386_BUS_SPACE_MEM; 915 sc->my_bhandle = vbase; 916#endif 917 } 918 919 rid = MY_RID; 920 sc->my_res = bus_alloc_resource(dev, MY_RES, &rid, 921 0, ~0, 1, RF_ACTIVE); 922 923 if (sc->my_res == NULL) { 924 printf("my%d: couldn't map ports/memory\n", unit); 925 error = ENXIO; 926 goto fail; 927 } 928 sc->my_btag = rman_get_bustag(sc->my_res); 929 sc->my_bhandle = rman_get_bushandle(sc->my_res); 930 931 rid = 0; 932 sc->my_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 933 RF_SHAREABLE | RF_ACTIVE); 934 935 if (sc->my_irq == NULL) { 936 printf("my%d: couldn't map interrupt\n", unit); 937 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res); 938 error = ENXIO; 939 goto fail; 940 } 941 error = bus_setup_intr(dev, sc->my_irq, INTR_TYPE_NET, 942 my_intr, sc, &sc->my_intrhand); 943 944 if (error) { 945 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq); 946 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res); 947 printf("my%d: couldn't set up irq\n", unit); 948 goto fail; 949 } 950 callout_handle_init(&sc->my_stat_ch); 951 952 sc->my_info = my_info_tmp; 953 954 /* Reset the adapter. */ 955 my_reset(sc); 956 957 /* 958 * Get station address 959 */ 960 for (i = 0; i < ETHER_ADDR_LEN; ++i) 961 eaddr[i] = CSR_READ_1(sc, MY_PAR0 + i); 962 963 /* 964 * A Myson chip was detected. Inform the world. 965 */ 966 printf("my%d: Ethernet address: %6D\n", unit, eaddr, ":"); 967 968 sc->my_unit = unit; 969 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 970 971 sc->my_ldata_ptr = malloc(sizeof(struct my_list_data) + 8, 972 M_DEVBUF, M_NOWAIT); 973 if (sc->my_ldata_ptr == NULL) { 974 free(sc, M_DEVBUF); 975 printf("my%d: no memory for list buffers!\n", unit); 976 error = ENXIO; 977 goto fail; 978 } 979 sc->my_ldata = (struct my_list_data *) sc->my_ldata_ptr; 980 round = (unsigned int)sc->my_ldata_ptr & 0xF; 981 roundptr = sc->my_ldata_ptr; 982 for (i = 0; i < 8; i++) { 983 if (round % 8) { 984 round++; 985 roundptr++; 986 } else 987 break; 988 } 989 sc->my_ldata = (struct my_list_data *) roundptr; 990 bzero(sc->my_ldata, sizeof(struct my_list_data)); 991 992 ifp = &sc->arpcom.ac_if; 993 ifp->if_softc = sc; 994 ifp->if_unit = unit; 995 ifp->if_name = "my"; 996 ifp->if_mtu = ETHERMTU; 997 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 998 ifp->if_ioctl = my_ioctl; 999 ifp->if_output = ether_output; 1000 ifp->if_start = my_start; 1001 ifp->if_watchdog = my_watchdog; 1002 ifp->if_init = my_init; 1003 ifp->if_baudrate = 10000000; 1004 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 1005 1006 if (sc->my_info->my_did == MTD803ID) 1007 sc->my_pinfo = my_phys; 1008 else { 1009 if (bootverbose) 1010 printf("my%d: probing for a PHY\n", sc->my_unit); 1011 for (i = MY_PHYADDR_MIN; i < MY_PHYADDR_MAX + 1; i++) { 1012 if (bootverbose) 1013 printf("my%d: checking address: %d\n", 1014 sc->my_unit, i); 1015 sc->my_phy_addr = i; 1016 phy_sts = my_phy_readreg(sc, PHY_BMSR); 1017 if ((phy_sts != 0) && (phy_sts != 0xffff)) 1018 break; 1019 else 1020 phy_sts = 0; 1021 } 1022 if (phy_sts) { 1023 phy_vid = my_phy_readreg(sc, PHY_VENID); 1024 phy_did = my_phy_readreg(sc, PHY_DEVID); 1025 if (bootverbose) { 1026 printf("my%d: found PHY at address %d, ", 1027 sc->my_unit, sc->my_phy_addr); 1028 printf("vendor id: %x device id: %x\n", 1029 phy_vid, phy_did); 1030 } 1031 p = my_phys; 1032 while (p->my_vid) { 1033 if (phy_vid == p->my_vid) { 1034 sc->my_pinfo = p; 1035 break; 1036 } 1037 p++; 1038 } 1039 if (sc->my_pinfo == NULL) 1040 sc->my_pinfo = &my_phys[PHY_UNKNOWN]; 1041 if (bootverbose) 1042 printf("my%d: PHY type: %s\n", 1043 sc->my_unit, sc->my_pinfo->my_name); 1044 } else { 1045 printf("my%d: MII without any phy!\n", sc->my_unit); 1046 error = ENXIO; 1047 goto fail; 1048 } 1049 } 1050 1051 /* Do ifmedia setup. */ 1052 ifmedia_init(&sc->ifmedia, 0, my_ifmedia_upd, my_ifmedia_sts); 1053 my_getmode_mii(sc); 1054 my_autoneg_mii(sc, MY_FLAG_FORCEDELAY, 1); 1055 media = sc->ifmedia.ifm_media; 1056 my_stop(sc); 1057 ifmedia_set(&sc->ifmedia, media); 1058 1059 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 1060 1061#if 0 1062 at_shutdown(my_shutdown, sc, SHUTDOWN_POST_SYNC); 1063 shutdownhook_establish(my_shutdown, sc); 1064#endif 1065 1066 MY_UNLOCK(sc); 1067 return (0); 1068 1069fail: 1070 MY_UNLOCK(sc); 1071 mtx_destroy(&sc->my_mtx); 1072 splx(s); 1073 return (error); 1074} 1075 1076static int 1077my_detach(device_t dev) 1078{ 1079 struct my_softc *sc; 1080 struct ifnet *ifp; 1081 int s; 1082 1083 s = splimp(); 1084 sc = device_get_softc(dev); 1085 MY_LOCK(sc); 1086 ifp = &sc->arpcom.ac_if; 1087 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 1088 my_stop(sc); 1089 1090#if 0 1091 bus_generic_detach(dev); 1092 device_delete_child(dev, sc->rl_miibus); 1093#endif 1094 1095 bus_teardown_intr(dev, sc->my_irq, sc->my_intrhand); 1096 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq); 1097 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res); 1098#if 0 1099 contigfree(sc->my_cdata.my_rx_buf, MY_RXBUFLEN + 32, M_DEVBUF); 1100#endif 1101 free(sc, M_DEVBUF); 1102 MY_UNLOCK(sc); 1103 splx(s); 1104 mtx_destroy(&sc->my_mtx); 1105 return (0); 1106} 1107 1108 1109/* 1110 * Initialize the transmit descriptors. 1111 */ 1112static int 1113my_list_tx_init(struct my_softc * sc) 1114{ 1115 struct my_chain_data *cd; 1116 struct my_list_data *ld; 1117 int i; 1118 1119 MY_LOCK(sc); 1120 cd = &sc->my_cdata; 1121 ld = sc->my_ldata; 1122 for (i = 0; i < MY_TX_LIST_CNT; i++) { 1123 cd->my_tx_chain[i].my_ptr = &ld->my_tx_list[i]; 1124 if (i == (MY_TX_LIST_CNT - 1)) 1125 cd->my_tx_chain[i].my_nextdesc = &cd->my_tx_chain[0]; 1126 else 1127 cd->my_tx_chain[i].my_nextdesc = 1128 &cd->my_tx_chain[i + 1]; 1129 } 1130 cd->my_tx_free = &cd->my_tx_chain[0]; 1131 cd->my_tx_tail = cd->my_tx_head = NULL; 1132 MY_UNLOCK(sc); 1133 return (0); 1134} 1135 1136/* 1137 * Initialize the RX descriptors and allocate mbufs for them. Note that we 1138 * arrange the descriptors in a closed ring, so that the last descriptor 1139 * points back to the first. 1140 */ 1141static int 1142my_list_rx_init(struct my_softc * sc) 1143{ 1144 struct my_chain_data *cd; 1145 struct my_list_data *ld; 1146 int i; 1147 1148 MY_LOCK(sc); 1149 cd = &sc->my_cdata; 1150 ld = sc->my_ldata; 1151 for (i = 0; i < MY_RX_LIST_CNT; i++) { 1152 cd->my_rx_chain[i].my_ptr = 1153 (struct my_desc *) & ld->my_rx_list[i]; 1154 if (my_newbuf(sc, &cd->my_rx_chain[i]) == ENOBUFS) 1155 return (ENOBUFS); 1156 if (i == (MY_RX_LIST_CNT - 1)) { 1157 cd->my_rx_chain[i].my_nextdesc = &cd->my_rx_chain[0]; 1158 ld->my_rx_list[i].my_next = vtophys(&ld->my_rx_list[0]); 1159 } else { 1160 cd->my_rx_chain[i].my_nextdesc = 1161 &cd->my_rx_chain[i + 1]; 1162 ld->my_rx_list[i].my_next = 1163 vtophys(&ld->my_rx_list[i + 1]); 1164 } 1165 } 1166 cd->my_rx_head = &cd->my_rx_chain[0]; 1167 MY_UNLOCK(sc); 1168 return (0); 1169} 1170 1171/* 1172 * Initialize an RX descriptor and attach an MBUF cluster. 1173 */ 1174static int 1175my_newbuf(struct my_softc * sc, struct my_chain_onefrag * c) 1176{ 1177 struct mbuf *m_new = NULL; 1178 1179 MY_LOCK(sc); 1180 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1181 if (m_new == NULL) { 1182 printf("my%d: no memory for rx list -- packet dropped!\n", 1183 sc->my_unit); 1184 MY_UNLOCK(sc); 1185 return (ENOBUFS); 1186 } 1187 MCLGET(m_new, M_DONTWAIT); 1188 if (!(m_new->m_flags & M_EXT)) { 1189 printf("my%d: no memory for rx list -- packet dropped!\n", 1190 sc->my_unit); 1191 m_freem(m_new); 1192 MY_UNLOCK(sc); 1193 return (ENOBUFS); 1194 } 1195 c->my_mbuf = m_new; 1196 c->my_ptr->my_data = vtophys(mtod(m_new, caddr_t)); 1197 c->my_ptr->my_ctl = (MCLBYTES - 1) << MY_RBSShift; 1198 c->my_ptr->my_status = MY_OWNByNIC; 1199 MY_UNLOCK(sc); 1200 return (0); 1201} 1202 1203/* 1204 * A frame has been uploaded: pass the resulting mbuf chain up to the higher 1205 * level protocols. 1206 */ 1207static void 1208my_rxeof(struct my_softc * sc) 1209{ 1210 struct ether_header *eh; 1211 struct mbuf *m; 1212 struct ifnet *ifp; 1213 struct my_chain_onefrag *cur_rx; 1214 int total_len = 0; 1215 u_int32_t rxstat; 1216 1217 MY_LOCK(sc); 1218 ifp = &sc->arpcom.ac_if; 1219 while (!((rxstat = sc->my_cdata.my_rx_head->my_ptr->my_status) 1220 & MY_OWNByNIC)) { 1221 cur_rx = sc->my_cdata.my_rx_head; 1222 sc->my_cdata.my_rx_head = cur_rx->my_nextdesc; 1223 1224 if (rxstat & MY_ES) { /* error summary: give up this rx pkt */ 1225 ifp->if_ierrors++; 1226 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1227 continue; 1228 } 1229 /* No errors; receive the packet. */ 1230 total_len = (rxstat & MY_FLNGMASK) >> MY_FLNGShift; 1231 total_len -= ETHER_CRC_LEN; 1232 1233 if (total_len < MINCLSIZE) { 1234 m = m_devget(mtod(cur_rx->my_mbuf, char *), 1235 total_len, 0, ifp, NULL); 1236 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1237 if (m == NULL) { 1238 ifp->if_ierrors++; 1239 continue; 1240 } 1241 } else { 1242 m = cur_rx->my_mbuf; 1243 /* 1244 * Try to conjure up a new mbuf cluster. If that 1245 * fails, it means we have an out of memory condition 1246 * and should leave the buffer in place and continue. 1247 * This will result in a lost packet, but there's 1248 * little else we can do in this situation. 1249 */ 1250 if (my_newbuf(sc, cur_rx) == ENOBUFS) { 1251 ifp->if_ierrors++; 1252 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1253 continue; 1254 } 1255 m->m_pkthdr.rcvif = ifp; 1256 m->m_pkthdr.len = m->m_len = total_len; 1257 } 1258 ifp->if_ipackets++; 1259 eh = mtod(m, struct ether_header *); 1260#if NBPFILTER > 0 1261 /* 1262 * Handle BPF listeners. Let the BPF user see the packet, but 1263 * don't pass it up to the ether_input() layer unless it's a 1264 * broadcast packet, multicast packet, matches our ethernet 1265 * address or the interface is in promiscuous mode. 1266 */ 1267 if (ifp->if_bpf) { 1268 bpf_mtap(ifp, m); 1269 if (ifp->if_flags & IFF_PROMISC && 1270 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 1271 ETHER_ADDR_LEN) && 1272 (eh->ether_dhost[0] & 1) == 0)) { 1273 m_freem(m); 1274 continue; 1275 } 1276 } 1277#endif 1278 /* Remove header from mbuf and pass it on. */ 1279 m_adj(m, sizeof(struct ether_header)); 1280 ether_input(ifp, eh, m); 1281 } 1282 MY_UNLOCK(sc); 1283 return; 1284} 1285 1286 1287/* 1288 * A frame was downloaded to the chip. It's safe for us to clean up the list 1289 * buffers. 1290 */ 1291static void 1292my_txeof(struct my_softc * sc) 1293{ 1294 struct my_chain *cur_tx; 1295 struct ifnet *ifp; 1296 1297 MY_LOCK(sc); 1298 ifp = &sc->arpcom.ac_if; 1299 /* Clear the timeout timer. */ 1300 ifp->if_timer = 0; 1301 if (sc->my_cdata.my_tx_head == NULL) { 1302 MY_UNLOCK(sc); 1303 return; 1304 } 1305 /* 1306 * Go through our tx list and free mbufs for those frames that have 1307 * been transmitted. 1308 */ 1309 while (sc->my_cdata.my_tx_head->my_mbuf != NULL) { 1310 u_int32_t txstat; 1311 1312 cur_tx = sc->my_cdata.my_tx_head; 1313 txstat = MY_TXSTATUS(cur_tx); 1314 if ((txstat & MY_OWNByNIC) || txstat == MY_UNSENT) 1315 break; 1316 if (!(CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced)) { 1317 if (txstat & MY_TXERR) { 1318 ifp->if_oerrors++; 1319 if (txstat & MY_EC) /* excessive collision */ 1320 ifp->if_collisions++; 1321 if (txstat & MY_LC) /* late collision */ 1322 ifp->if_collisions++; 1323 } 1324 ifp->if_collisions += (txstat & MY_NCRMASK) >> 1325 MY_NCRShift; 1326 } 1327 ifp->if_opackets++; 1328 m_freem(cur_tx->my_mbuf); 1329 cur_tx->my_mbuf = NULL; 1330 if (sc->my_cdata.my_tx_head == sc->my_cdata.my_tx_tail) { 1331 sc->my_cdata.my_tx_head = NULL; 1332 sc->my_cdata.my_tx_tail = NULL; 1333 break; 1334 } 1335 sc->my_cdata.my_tx_head = cur_tx->my_nextdesc; 1336 } 1337 if (CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced) { 1338 ifp->if_collisions += (CSR_READ_4(sc, MY_TSR) & MY_NCRMask); 1339 } 1340 MY_UNLOCK(sc); 1341 return; 1342} 1343 1344/* 1345 * TX 'end of channel' interrupt handler. 1346 */ 1347static void 1348my_txeoc(struct my_softc * sc) 1349{ 1350 struct ifnet *ifp; 1351 1352 MY_LOCK(sc); 1353 ifp = &sc->arpcom.ac_if; 1354 ifp->if_timer = 0; 1355 if (sc->my_cdata.my_tx_head == NULL) { 1356 ifp->if_flags &= ~IFF_OACTIVE; 1357 sc->my_cdata.my_tx_tail = NULL; 1358 if (sc->my_want_auto) 1359 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1); 1360 } else { 1361 if (MY_TXOWN(sc->my_cdata.my_tx_head) == MY_UNSENT) { 1362 MY_TXOWN(sc->my_cdata.my_tx_head) = MY_OWNByNIC; 1363 ifp->if_timer = 5; 1364 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); 1365 } 1366 } 1367 MY_UNLOCK(sc); 1368 return; 1369} 1370 1371static void 1372my_intr(void *arg) 1373{ 1374 struct my_softc *sc; 1375 struct ifnet *ifp; 1376 u_int32_t status; 1377 1378 sc = arg; 1379 MY_LOCK(sc); 1380 ifp = &sc->arpcom.ac_if; 1381 if (!(ifp->if_flags & IFF_UP)) { 1382 MY_UNLOCK(sc); 1383 return; 1384 } 1385 /* Disable interrupts. */ 1386 CSR_WRITE_4(sc, MY_IMR, 0x00000000); 1387 1388 for (;;) { 1389 status = CSR_READ_4(sc, MY_ISR); 1390 status &= MY_INTRS; 1391 if (status) 1392 CSR_WRITE_4(sc, MY_ISR, status); 1393 else 1394 break; 1395 1396 if (status & MY_RI) /* receive interrupt */ 1397 my_rxeof(sc); 1398 1399 if ((status & MY_RBU) || (status & MY_RxErr)) { 1400 /* rx buffer unavailable or rx error */ 1401 ifp->if_ierrors++; 1402#ifdef foo 1403 my_stop(sc); 1404 my_reset(sc); 1405 my_init(sc); 1406#endif 1407 } 1408 if (status & MY_TI) /* tx interrupt */ 1409 my_txeof(sc); 1410 if (status & MY_ETI) /* tx early interrupt */ 1411 my_txeof(sc); 1412 if (status & MY_TBU) /* tx buffer unavailable */ 1413 my_txeoc(sc); 1414 1415#if 0 /* 90/1/18 delete */ 1416 if (status & MY_FBE) { 1417 my_reset(sc); 1418 my_init(sc); 1419 } 1420#endif 1421 1422 } 1423 1424 /* Re-enable interrupts. */ 1425 CSR_WRITE_4(sc, MY_IMR, MY_INTRS); 1426 if (ifp->if_snd.ifq_head != NULL) 1427 my_start(ifp); 1428 MY_UNLOCK(sc); 1429 return; 1430} 1431 1432/* 1433 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1434 * pointers to the fragment pointers. 1435 */ 1436static int 1437my_encap(struct my_softc * sc, struct my_chain * c, struct mbuf * m_head) 1438{ 1439 struct my_desc *f = NULL; 1440 int total_len; 1441 struct mbuf *m, *m_new = NULL; 1442 1443 MY_LOCK(sc); 1444 /* calculate the total tx pkt length */ 1445 total_len = 0; 1446 for (m = m_head; m != NULL; m = m->m_next) 1447 total_len += m->m_len; 1448 /* 1449 * Start packing the mbufs in this chain into the fragment pointers. 1450 * Stop when we run out of fragments or hit the end of the mbuf 1451 * chain. 1452 */ 1453 m = m_head; 1454 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1455 if (m_new == NULL) { 1456 printf("my%d: no memory for tx list", sc->my_unit); 1457 MY_UNLOCK(sc); 1458 return (1); 1459 } 1460 if (m_head->m_pkthdr.len > MHLEN) { 1461 MCLGET(m_new, M_DONTWAIT); 1462 if (!(m_new->m_flags & M_EXT)) { 1463 m_freem(m_new); 1464 printf("my%d: no memory for tx list", sc->my_unit); 1465 MY_UNLOCK(sc); 1466 return (1); 1467 } 1468 } 1469 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t)); 1470 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1471 m_freem(m_head); 1472 m_head = m_new; 1473 f = &c->my_ptr->my_frag[0]; 1474 f->my_status = 0; 1475 f->my_data = vtophys(mtod(m_new, caddr_t)); 1476 total_len = m_new->m_len; 1477 f->my_ctl = MY_TXFD | MY_TXLD | MY_CRCEnable | MY_PADEnable; 1478 f->my_ctl |= total_len << MY_PKTShift; /* pkt size */ 1479 f->my_ctl |= total_len; /* buffer size */ 1480 /* 89/12/29 add, for mtd891 *//* [ 89? ] */ 1481 if (sc->my_info->my_did == MTD891ID) 1482 f->my_ctl |= MY_ETIControl | MY_RetryTxLC; 1483 c->my_mbuf = m_head; 1484 c->my_lastdesc = 0; 1485 MY_TXNEXT(c) = vtophys(&c->my_nextdesc->my_ptr->my_frag[0]); 1486 MY_UNLOCK(sc); 1487 return (0); 1488} 1489 1490/* 1491 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1492 * to the mbuf data regions directly in the transmit lists. We also save a 1493 * copy of the pointers since the transmit list fragment pointers are 1494 * physical addresses. 1495 */ 1496static void 1497my_start(struct ifnet * ifp) 1498{ 1499 struct my_softc *sc; 1500 struct mbuf *m_head = NULL; 1501 struct my_chain *cur_tx = NULL, *start_tx; 1502 1503 sc = ifp->if_softc; 1504 MY_LOCK(sc); 1505 if (sc->my_autoneg) { 1506 sc->my_tx_pend = 1; 1507 MY_UNLOCK(sc); 1508 return; 1509 } 1510 /* 1511 * Check for an available queue slot. If there are none, punt. 1512 */ 1513 if (sc->my_cdata.my_tx_free->my_mbuf != NULL) { 1514 ifp->if_flags |= IFF_OACTIVE; 1515 MY_UNLOCK(sc); 1516 return; 1517 } 1518 start_tx = sc->my_cdata.my_tx_free; 1519 while (sc->my_cdata.my_tx_free->my_mbuf == NULL) { 1520 IF_DEQUEUE(&ifp->if_snd, m_head); 1521 if (m_head == NULL) 1522 break; 1523 1524 /* Pick a descriptor off the free list. */ 1525 cur_tx = sc->my_cdata.my_tx_free; 1526 sc->my_cdata.my_tx_free = cur_tx->my_nextdesc; 1527 1528 /* Pack the data into the descriptor. */ 1529 my_encap(sc, cur_tx, m_head); 1530 1531 if (cur_tx != start_tx) 1532 MY_TXOWN(cur_tx) = MY_OWNByNIC; 1533#if NBPFILTER > 0 1534 /* 1535 * If there's a BPF listener, bounce a copy of this frame to 1536 * him. 1537 */ 1538 if (ifp->if_bpf) 1539 bpf_mtap(ifp, cur_tx->my_mbuf); 1540#endif 1541 } 1542 /* 1543 * If there are no packets queued, bail. 1544 */ 1545 if (cur_tx == NULL) { 1546 MY_UNLOCK(sc); 1547 return; 1548 } 1549 /* 1550 * Place the request for the upload interrupt in the last descriptor 1551 * in the chain. This way, if we're chaining several packets at once, 1552 * we'll only get an interupt once for the whole chain rather than 1553 * once for each packet. 1554 */ 1555 MY_TXCTL(cur_tx) |= MY_TXIC; 1556 cur_tx->my_ptr->my_frag[0].my_ctl |= MY_TXIC; 1557 sc->my_cdata.my_tx_tail = cur_tx; 1558 if (sc->my_cdata.my_tx_head == NULL) 1559 sc->my_cdata.my_tx_head = start_tx; 1560 MY_TXOWN(start_tx) = MY_OWNByNIC; 1561 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); /* tx polling demand */ 1562 1563 /* 1564 * Set a timeout in case the chip goes out to lunch. 1565 */ 1566 ifp->if_timer = 5; 1567 MY_UNLOCK(sc); 1568 return; 1569} 1570 1571static void 1572my_init(void *xsc) 1573{ 1574 struct my_softc *sc = xsc; 1575 struct ifnet *ifp = &sc->arpcom.ac_if; 1576 int s; 1577 u_int16_t phy_bmcr = 0; 1578 1579 MY_LOCK(sc); 1580 if (sc->my_autoneg) { 1581 MY_UNLOCK(sc); 1582 return; 1583 } 1584 s = splimp(); 1585 if (sc->my_pinfo != NULL) 1586 phy_bmcr = my_phy_readreg(sc, PHY_BMCR); 1587 /* 1588 * Cancel pending I/O and free all RX/TX buffers. 1589 */ 1590 my_stop(sc); 1591 my_reset(sc); 1592 1593 /* 1594 * Set cache alignment and burst length. 1595 */ 1596#if 0 /* 89/9/1 modify, */ 1597 CSR_WRITE_4(sc, MY_BCR, MY_RPBLE512); 1598 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF); 1599#endif 1600 CSR_WRITE_4(sc, MY_BCR, MY_PBL8); 1601 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF | MY_RBLEN | MY_RPBLE512); 1602 /* 1603 * 89/12/29 add, for mtd891, 1604 */ 1605 if (sc->my_info->my_did == MTD891ID) { 1606 MY_SETBIT(sc, MY_BCR, MY_PROG); 1607 MY_SETBIT(sc, MY_TCRRCR, MY_Enhanced); 1608 } 1609 my_setcfg(sc, phy_bmcr); 1610 /* Init circular RX list. */ 1611 if (my_list_rx_init(sc) == ENOBUFS) { 1612 printf("my%d: init failed: no memory for rx buffers\n", 1613 sc->my_unit); 1614 my_stop(sc); 1615 (void)splx(s); 1616 MY_UNLOCK(sc); 1617 return; 1618 } 1619 /* Init TX descriptors. */ 1620 my_list_tx_init(sc); 1621 1622 /* If we want promiscuous mode, set the allframes bit. */ 1623 if (ifp->if_flags & IFF_PROMISC) 1624 MY_SETBIT(sc, MY_TCRRCR, MY_PROM); 1625 else 1626 MY_CLRBIT(sc, MY_TCRRCR, MY_PROM); 1627 1628 /* 1629 * Set capture broadcast bit to capture broadcast frames. 1630 */ 1631 if (ifp->if_flags & IFF_BROADCAST) 1632 MY_SETBIT(sc, MY_TCRRCR, MY_AB); 1633 else 1634 MY_CLRBIT(sc, MY_TCRRCR, MY_AB); 1635 1636 /* 1637 * Program the multicast filter, if necessary. 1638 */ 1639 my_setmulti(sc); 1640 1641 /* 1642 * Load the address of the RX list. 1643 */ 1644 MY_CLRBIT(sc, MY_TCRRCR, MY_RE); 1645 CSR_WRITE_4(sc, MY_RXLBA, vtophys(&sc->my_ldata->my_rx_list[0])); 1646 1647 /* 1648 * Enable interrupts. 1649 */ 1650 CSR_WRITE_4(sc, MY_IMR, MY_INTRS); 1651 CSR_WRITE_4(sc, MY_ISR, 0xFFFFFFFF); 1652 1653 /* Enable receiver and transmitter. */ 1654 MY_SETBIT(sc, MY_TCRRCR, MY_RE); 1655 MY_CLRBIT(sc, MY_TCRRCR, MY_TE); 1656 CSR_WRITE_4(sc, MY_TXLBA, vtophys(&sc->my_ldata->my_tx_list[0])); 1657 MY_SETBIT(sc, MY_TCRRCR, MY_TE); 1658 1659 /* Restore state of BMCR */ 1660 if (sc->my_pinfo != NULL) 1661 my_phy_writereg(sc, PHY_BMCR, phy_bmcr); 1662 ifp->if_flags |= IFF_RUNNING; 1663 ifp->if_flags &= ~IFF_OACTIVE; 1664 (void)splx(s); 1665 MY_UNLOCK(sc); 1666 return; 1667} 1668 1669/* 1670 * Set media options. 1671 */ 1672 1673static int 1674my_ifmedia_upd(struct ifnet * ifp) 1675{ 1676 struct my_softc *sc; 1677 struct ifmedia *ifm; 1678 1679 sc = ifp->if_softc; 1680 MY_LOCK(sc); 1681 ifm = &sc->ifmedia; 1682 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) { 1683 MY_UNLOCK(sc); 1684 return (EINVAL); 1685 } 1686 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) 1687 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1); 1688 else 1689 my_setmode_mii(sc, ifm->ifm_media); 1690 MY_UNLOCK(sc); 1691 return (0); 1692} 1693 1694/* 1695 * Report current media status. 1696 */ 1697 1698static void 1699my_ifmedia_sts(struct ifnet * ifp, struct ifmediareq * ifmr) 1700{ 1701 struct my_softc *sc; 1702 u_int16_t advert = 0, ability = 0; 1703 1704 sc = ifp->if_softc; 1705 MY_LOCK(sc); 1706 ifmr->ifm_active = IFM_ETHER; 1707 if (!(my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) { 1708#if 0 /* this version did not support 1000M, */ 1709 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_1000) 1710 ifmr->ifm_active = IFM_ETHER | IFM_1000TX; 1711#endif 1712 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL) 1713 ifmr->ifm_active = IFM_ETHER | IFM_100_TX; 1714 else 1715 ifmr->ifm_active = IFM_ETHER | IFM_10_T; 1716 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX) 1717 ifmr->ifm_active |= IFM_FDX; 1718 else 1719 ifmr->ifm_active |= IFM_HDX; 1720 1721 MY_UNLOCK(sc); 1722 return; 1723 } 1724 ability = my_phy_readreg(sc, PHY_LPAR); 1725 advert = my_phy_readreg(sc, PHY_ANAR); 1726 1727#if 0 /* this version did not support 1000M, */ 1728 if (sc->my_pinfo->my_vid = MarvellPHYID0) { 1729 ability2 = my_phy_readreg(sc, PHY_1000SR); 1730 if (ability2 & PHY_1000SR_1000BTXFULL) { 1731 advert = 0; 1732 ability = 0; 1733 ifmr->ifm_active = IFM_ETHER|IFM_1000_T|IFM_FDX; 1734 } else if (ability & PHY_1000SR_1000BTXHALF) { 1735 advert = 0; 1736 ability = 0; 1737 ifmr->ifm_active = IFM_ETHER|IFM_1000_T|IFM_HDX; 1738 } 1739 } 1740#endif 1741 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) 1742 ifmr->ifm_active = IFM_ETHER | IFM_100_T4; 1743 else if (advert & PHY_ANAR_100BTXFULL && ability & PHY_ANAR_100BTXFULL) 1744 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1745 else if (advert & PHY_ANAR_100BTXHALF && ability & PHY_ANAR_100BTXHALF) 1746 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_HDX; 1747 else if (advert & PHY_ANAR_10BTFULL && ability & PHY_ANAR_10BTFULL) 1748 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_FDX; 1749 else if (advert & PHY_ANAR_10BTHALF && ability & PHY_ANAR_10BTHALF) 1750 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_HDX; 1751 MY_UNLOCK(sc); 1752 return; 1753} 1754 1755static int 1756my_ioctl(struct ifnet * ifp, u_long command, caddr_t data) 1757{ 1758 struct my_softc *sc = ifp->if_softc; 1759 struct ifreq *ifr = (struct ifreq *) data; 1760 int s, error = 0; 1761 1762 s = splimp(); 1763 MY_LOCK(sc); 1764 switch (command) { 1765 case SIOCSIFADDR: 1766 case SIOCGIFADDR: 1767 case SIOCSIFMTU: 1768 error = ether_ioctl(ifp, command, data); 1769 break; 1770 case SIOCSIFFLAGS: 1771 if (ifp->if_flags & IFF_UP) 1772 my_init(sc); 1773 else if (ifp->if_flags & IFF_RUNNING) 1774 my_stop(sc); 1775 error = 0; 1776 break; 1777 case SIOCADDMULTI: 1778 case SIOCDELMULTI: 1779 my_setmulti(sc); 1780 error = 0; 1781 break; 1782 case SIOCGIFMEDIA: 1783 case SIOCSIFMEDIA: 1784 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 1785 break; 1786 default: 1787 error = EINVAL; 1788 break; 1789 } 1790 MY_UNLOCK(sc); 1791 (void)splx(s); 1792 return (error); 1793} 1794 1795static void 1796my_watchdog(struct ifnet * ifp) 1797{ 1798 struct my_softc *sc; 1799 1800 sc = ifp->if_softc; 1801 MY_LOCK(sc); 1802 if (sc->my_autoneg) { 1803 my_autoneg_mii(sc, MY_FLAG_DELAYTIMEO, 1); 1804 MY_UNLOCK(sc); 1805 return; 1806 } 1807 ifp->if_oerrors++; 1808 printf("my%d: watchdog timeout\n", sc->my_unit); 1809 if (!(my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1810 printf("my%d: no carrier - transceiver cable problem?\n", 1811 sc->my_unit); 1812 my_stop(sc); 1813 my_reset(sc); 1814 my_init(sc); 1815 if (ifp->if_snd.ifq_head != NULL) 1816 my_start(ifp); 1817 MY_LOCK(sc); 1818 return; 1819} 1820 1821 1822/* 1823 * Stop the adapter and free any mbufs allocated to the RX and TX lists. 1824 */ 1825static void 1826my_stop(struct my_softc * sc) 1827{ 1828 register int i; 1829 struct ifnet *ifp; 1830 1831 MY_LOCK(sc); 1832 ifp = &sc->arpcom.ac_if; 1833 ifp->if_timer = 0; 1834 1835 MY_CLRBIT(sc, MY_TCRRCR, (MY_RE | MY_TE)); 1836 CSR_WRITE_4(sc, MY_IMR, 0x00000000); 1837 CSR_WRITE_4(sc, MY_TXLBA, 0x00000000); 1838 CSR_WRITE_4(sc, MY_RXLBA, 0x00000000); 1839 1840 /* 1841 * Free data in the RX lists. 1842 */ 1843 for (i = 0; i < MY_RX_LIST_CNT; i++) { 1844 if (sc->my_cdata.my_rx_chain[i].my_mbuf != NULL) { 1845 m_freem(sc->my_cdata.my_rx_chain[i].my_mbuf); 1846 sc->my_cdata.my_rx_chain[i].my_mbuf = NULL; 1847 } 1848 } 1849 bzero((char *)&sc->my_ldata->my_rx_list, 1850 sizeof(sc->my_ldata->my_rx_list)); 1851 /* 1852 * Free the TX list buffers. 1853 */ 1854 for (i = 0; i < MY_TX_LIST_CNT; i++) { 1855 if (sc->my_cdata.my_tx_chain[i].my_mbuf != NULL) { 1856 m_freem(sc->my_cdata.my_tx_chain[i].my_mbuf); 1857 sc->my_cdata.my_tx_chain[i].my_mbuf = NULL; 1858 } 1859 } 1860 bzero((char *)&sc->my_ldata->my_tx_list, 1861 sizeof(sc->my_ldata->my_tx_list)); 1862 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1863 MY_UNLOCK(sc); 1864 return; 1865} 1866 1867/* 1868 * Stop all chip I/O so that the kernel's probe routines don't get confused 1869 * by errant DMAs when rebooting. 1870 */ 1871static void 1872my_shutdown(device_t dev) 1873{ 1874 struct my_softc *sc; 1875 1876 sc = device_get_softc(dev); 1877 my_stop(sc); 1878 return; 1879} 1880 1881 1882