mxge_mcp.h revision 258780
1327Sjkh/******************************************************************************* 2327Sjkh 3327SjkhCopyright (c) 2006-2009, Myricom Inc. 4327SjkhAll rights reserved. 5327Sjkh 6327SjkhRedistribution and use in source and binary forms, with or without 7327Sjkhmodification, are permitted provided that the following conditions are met: 8327Sjkh 9327Sjkh 1. Redistributions of source code must retain the above copyright notice, 10327Sjkh this list of conditions and the following disclaimer. 11327Sjkh 12327Sjkh 2. Neither the name of the Myricom Inc, nor the names of its 13327Sjkh contributors may be used to endorse or promote products derived from 14327Sjkh this software without specific prior written permission. 15327Sjkh 16327SjkhTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17327SjkhAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18327SjkhIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19327SjkhARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 20327SjkhLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2193520SobrienCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2293520SobrienSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2376392SobrienINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2430221ScharnierCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2512219SjkhARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 2647916SobrienPOSSIBILITY OF SUCH DAMAGE. 27327Sjkh 28327Sjkh$FreeBSD: head/sys/dev/mxge/mxge_mcp.h 258780 2013-11-30 22:17:27Z eadler $ 29327Sjkh***************************************************************************/ 30156497Sphk 31327Sjkh#ifndef _myri10ge_mcp_h 32327Sjkh#define _myri10ge_mcp_h 33152329Skrion 34126465Skensmith#define MXGEFW_VERSION_MAJOR 1 35327Sjkh#define MXGEFW_VERSION_MINOR 4 36327Sjkh 3742740Sbillf#if defined MXGEFW && !defined _stdint_h_ 38154145Sflztypedef signed char int8_t; 39156497Sphktypedef signed short int16_t; 40327Sjkhtypedef signed int int32_t; 41327Sjkhtypedef signed long long int64_t; 42327Sjkhtypedef unsigned char uint8_t; 43327Sjkhtypedef unsigned short uint16_t; 44327Sjkhtypedef unsigned int uint32_t; 45131285Seiktypedef unsigned long long uint64_t; 46327Sjkh#endif 4711780Sjkh 48382Sjkh/* 8 Bytes */ 49327Sjkhstruct mcp_dma_addr { 5085023Sobrien uint32_t high; 5112219Sjkh uint32_t low; 5212219Sjkh}; 5312219Sjkhtypedef struct mcp_dma_addr mcp_dma_addr_t; 5476504Skris 5576504Skris/* 4 Bytes */ 5676504Skrisstruct mcp_slot { 5776504Skris uint16_t checksum; 5876504Skris uint16_t length; 5976504Skris}; 6076504Skristypedef struct mcp_slot mcp_slot_t; 6176504Skris 6276504Skris#ifdef MXGEFW_NDIS 6376504Skris/* 8-byte descriptor, exclusively used by NDIS drivers. */ 64103150Sbmahstruct mcp_slot_8 { 65103155Sbmah /* Place hash value at the top so it gets written before length. 66104658Sbmah * The driver polls length. 67124054Sbmah */ 68124054Sbmah uint32_t hash; 69129054Sbmah uint16_t checksum; 70131285Seik uint16_t length; 71124054Sbmah}; 72124054Sbmahtypedef struct mcp_slot_8 mcp_slot_8_t; 73129054Sbmah 74129054Sbmah/* Two bits of length in mcp_slot are used to indicate hash type. */ 75131285Seik#define MXGEFW_RSS_HASH_NULL (0 << 14) /* bit 15:14 = 00 */ 76147932Skensmith#define MXGEFW_RSS_HASH_IPV4 (1 << 14) /* bit 15:14 = 01 */ 77151754Smurray#define MXGEFW_RSS_HASH_TCP_IPV4 (2 << 14) /* bit 15:14 = 10 */ 7876504Skris#define MXGEFW_RSS_HASH_MASK (3 << 14) /* bit 15:14 = 11 */ 7976504Skris#endif 80136616Sobrien 81147939Skensmith/* 64 Bytes */ 82151754Smurraystruct mcp_cmd { 83147932Skensmith uint32_t cmd; 8476504Skris uint32_t data0; /* will be low portion if data > 32 bits */ 8576504Skris /* 8 */ 8676504Skris uint32_t data1; /* will be high portion if data > 32 bits */ 8776504Skris uint32_t data2; /* currently unused.. */ 8851638Sbillf /* 16 */ 8942740Sbillf struct mcp_dma_addr response_addr; 9042740Sbillf /* 24 */ 9130221Scharnier uint8_t pad[40]; 9230221Scharnier}; 93327Sjkhtypedef struct mcp_cmd mcp_cmd_t; 94327Sjkh 95327Sjkh/* 8 Bytes */ 9676504Skrisstruct mcp_cmd_response { 9712219Sjkh uint32_t data; 9883573Ssobomax uint32_t result; 9953388Scpiazza}; 100131285Seiktypedef struct mcp_cmd_response mcp_cmd_response_t; 10142740Sbillf 102131285Seik 103131285Seik 104131285Seik/* 105131285Seik flags used in mcp_kreq_ether_send_t: 106131285Seik 10712219Sjkh The SMALL flag is only needed in the first segment. It is raised 10824428Simp for packets that are total less or equal 512 bytes. 109327Sjkh 110327Sjkh The CKSUM flag must be set in all segments. 111327Sjkh 112327Sjkh The PADDED flags is set if the packet needs to be padded, and it 113327Sjkh must be set for all segments. 114327Sjkh 115327Sjkh The MXGEFW_FLAGS_ALIGN_ODD must be set if the cumulative 116152329Skrion length of all previous segments was odd. 117327Sjkh*/ 118327Sjkh 119152329Skrion 120152329Skrion#define MXGEFW_FLAGS_SMALL 0x1 121152329Skrion#define MXGEFW_FLAGS_TSO_HDR 0x1 122152329Skrion#define MXGEFW_FLAGS_FIRST 0x2 123152329Skrion#define MXGEFW_FLAGS_ALIGN_ODD 0x4 124327Sjkh#define MXGEFW_FLAGS_CKSUM 0x8 125327Sjkh#define MXGEFW_FLAGS_TSO_LAST 0x8 126327Sjkh#define MXGEFW_FLAGS_NO_TSO 0x10 127327Sjkh#define MXGEFW_FLAGS_TSO_CHOP 0x10 128327Sjkh#define MXGEFW_FLAGS_TSO_PLD 0x20 129327Sjkh 130327Sjkh#define MXGEFW_SEND_SMALL_SIZE 1520 131327Sjkh#define MXGEFW_MAX_MTU 9400 1324996Sjkh 1334996Sjkhunion mcp_pso_or_cumlen { 1344996Sjkh uint16_t pseudo_hdr_offset; 1354996Sjkh uint16_t cum_len; 136156497Sphk}; 137156497Sphktypedef union mcp_pso_or_cumlen mcp_pso_or_cumlen_t; 138156497Sphk 139156497Sphk#define MXGEFW_MAX_SEND_DESC 12 140154145Sflz#define MXGEFW_PAD 2 141154145Sflz 142154145Sflz/* 16 Bytes */ 143154145Sflzstruct mcp_kreq_ether_send { 144327Sjkh uint32_t addr_high; 145327Sjkh uint32_t addr_low; 146327Sjkh uint16_t pseudo_hdr_offset; 147327Sjkh uint16_t length; 14842740Sbillf uint8_t pad; 14942740Sbillf uint8_t rdma_count; 15042740Sbillf uint8_t cksum_offset; /* where to start computing cksum */ 15142740Sbillf uint8_t flags; /* as defined above */ 152382Sjkh}; 15381571Sobrientypedef struct mcp_kreq_ether_send mcp_kreq_ether_send_t; 15476504Skris 155382Sjkh/* 8 Bytes */ 156382Sjkhstruct mcp_kreq_ether_recv { 157382Sjkh uint32_t addr_high; 158382Sjkh uint32_t addr_low; 159382Sjkh}; 160382Sjkhtypedef struct mcp_kreq_ether_recv mcp_kreq_ether_recv_t; 161382Sjkh 162382Sjkh 163382Sjkh/* Commands */ 164382Sjkh 165126465Skensmith#define MXGEFW_BOOT_HANDOFF 0xfc0000 166126465Skensmith#define MXGEFW_BOOT_DUMMY_RDMA 0xfc01c0 167126465Skensmith 168126465Skensmith#define MXGEFW_ETH_CMD 0xf80000 169327Sjkh#define MXGEFW_ETH_SEND_4 0x200000 170327Sjkh#define MXGEFW_ETH_SEND_1 0x240000 171327Sjkh#define MXGEFW_ETH_SEND_2 0x280000 17230221Scharnier#define MXGEFW_ETH_SEND_3 0x2c0000 173327Sjkh#define MXGEFW_ETH_RECV_SMALL 0x300000 174327Sjkh#define MXGEFW_ETH_RECV_BIG 0x340000 17512219Sjkh#define MXGEFW_ETH_SEND_GO 0x380000 1768857Srgrimes#define MXGEFW_ETH_SEND_STOP 0x3C0000 177327Sjkh 178327Sjkh#define MXGEFW_ETH_SEND(n) (0x200000 + (((n) & 0x03) * 0x40000)) 17912219Sjkh#define MXGEFW_ETH_SEND_OFFSET(n) (MXGEFW_ETH_SEND(n) - MXGEFW_ETH_SEND_4) 18076504Skris 18112219Sjkhenum myri10ge_mcp_cmd_type { 182327Sjkh MXGEFW_CMD_NONE = 0, 18312219Sjkh /* Reset the mcp, it is left in a safe state, waiting 18412219Sjkh for the driver to set all its parameters */ 18512219Sjkh MXGEFW_CMD_RESET = 1, 18612219Sjkh 18712219Sjkh /* get the version number of the current firmware.. 18842740Sbillf (may be available in the eeprom strings..? */ 18976504Skris MXGEFW_GET_MCP_VERSION = 2, 19076504Skris 19181571Sobrien 19281571Sobrien /* Parameters which must be set by the driver before it can 19376504Skris issue MXGEFW_CMD_ETHERNET_UP. They persist until the next 19481571Sobrien MXGEFW_CMD_RESET is issued */ 19581571Sobrien 19676504Skris MXGEFW_CMD_SET_INTRQ_DMA = 3, 19776504Skris /* data0 = LSW of the host address 19842786Sbillf * data1 = MSW of the host address 199102383Sobrien * data2 = slice number if multiple slices are used 200102383Sobrien */ 201131285Seik 202131285Seik MXGEFW_CMD_SET_BIG_BUFFER_SIZE = 4, /* in bytes, power of 2 */ 203131285Seik MXGEFW_CMD_SET_SMALL_BUFFER_SIZE = 5, /* in bytes */ 204131285Seik 205131285Seik 206131285Seik /* Parameters which refer to lanai SRAM addresses where the 207131285Seik driver must issue PIO writes for various things */ 20876504Skris 20942740Sbillf MXGEFW_CMD_GET_SEND_OFFSET = 6, 21014582Sjkh MXGEFW_CMD_GET_SMALL_RX_OFFSET = 7, 211132789Skan MXGEFW_CMD_GET_BIG_RX_OFFSET = 8, 21276504Skris /* data0 = slice number if multiple slices are used */ 21381571Sobrien 21481571Sobrien MXGEFW_CMD_GET_IRQ_ACK_OFFSET = 9, 21576504Skris MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET = 10, 21676504Skris 21776504Skris /* Parameters which refer to rings stored on the MCP, 21876504Skris and whose size is controlled by the mcp */ 21981571Sobrien 22081571Sobrien MXGEFW_CMD_GET_SEND_RING_SIZE = 11, /* in bytes */ 22176504Skris MXGEFW_CMD_GET_RX_RING_SIZE = 12, /* in bytes */ 22276504Skris 22376504Skris /* Parameters which refer to rings stored in the host, 22412219Sjkh and whose size is controlled by the host. Note that 22512219Sjkh all must be physically contiguous and must contain 22612219Sjkh a power of 2 number of entries. */ 22779916Skris 22879916Skris MXGEFW_CMD_SET_INTRQ_SIZE = 13, /* in bytes */ 22981571Sobrien#define MXGEFW_CMD_SET_INTRQ_SIZE_FLAG_NO_STRICT_SIZE_CHECK (1U << 31) 23081571Sobrien 23179916Skris /* command to bring ethernet interface up. Above parameters 23279916Skris (plus mtu & mac address) must have been exchanged prior 23379916Skris to issuing this command */ 23481571Sobrien MXGEFW_CMD_ETHERNET_UP = 14, 23581571Sobrien 23676504Skris /* command to bring ethernet interface down. No further sends 23776504Skris or receives may be processed until an MXGEFW_CMD_ETHERNET_UP 23876504Skris is issued, and all interrupt queues must be flushed prior 23912219Sjkh to ack'ing this command */ 24012219Sjkh 24183573Ssobomax MXGEFW_CMD_ETHERNET_DOWN = 15, 24283573Ssobomax 24312219Sjkh /* commands the driver may issue live, without resetting 24412219Sjkh the nic. Note that increasing the mtu "live" should 245327Sjkh only be done if the driver has already supplied buffers 24638942Sjkh sufficiently large to handle the new mtu. Decreasing 24738942Sjkh the mtu live is safe */ 24830221Scharnier 24938942Sjkh MXGEFW_CMD_SET_MTU = 16, 25038942Sjkh MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET = 17, /* in microseconds */ 25138942Sjkh MXGEFW_CMD_SET_STATS_INTERVAL = 18, /* in microseconds */ 25238942Sjkh MXGEFW_CMD_SET_STATS_DMA_OBSOLETE = 19, /* replaced by SET_STATS_DMA_V2 */ 25338942Sjkh 254126465Skensmith MXGEFW_ENABLE_PROMISC = 20, 255126465Skensmith MXGEFW_DISABLE_PROMISC = 21, 256126465Skensmith MXGEFW_SET_MAC_ADDRESS = 22, 257126465Skensmith 258126465Skensmith MXGEFW_ENABLE_FLOW_CONTROL = 23, 25938942Sjkh MXGEFW_DISABLE_FLOW_CONTROL = 24, 26076015Sache 261143849Smarcus /* do a DMA test 26276015Sache data0,data1 = DMA address 26339185Sjkh data2 = RDMA length (MSH), WDMA length (LSH) 26439185Sjkh command return data = repetitions (MSH), 0.5-ms ticks (LSH) 26539185Sjkh */ 26639185Sjkh MXGEFW_DMA_TEST = 25, 26776504Skris 268327Sjkh MXGEFW_ENABLE_ALLMULTI = 26, 26976504Skris MXGEFW_DISABLE_ALLMULTI = 27, 27076504Skris 271327Sjkh /* returns MXGEFW_CMD_ERROR_MULTICAST 272327Sjkh if there is no room in the cache 273327Sjkh data0,MSH(data1) = multicast group address */ 274327Sjkh MXGEFW_JOIN_MULTICAST_GROUP = 28, 275327Sjkh /* returns MXGEFW_CMD_ERROR_MULTICAST 27642786Sbillf if the address is not in the cache, 27751638Sbillf or is equal to FF-FF-FF-FF-FF-FF 27842740Sbillf data0,MSH(data1) = multicast group address */ 27976504Skris MXGEFW_LEAVE_MULTICAST_GROUP = 29, 28047916Sobrien MXGEFW_LEAVE_ALL_MULTICAST_GROUPS = 30, 28147916Sobrien 28242740Sbillf MXGEFW_CMD_SET_STATS_DMA_V2 = 31, 28372430Sobrien /* data0, data1 = bus addr, 28481571Sobrien * data2 = sizeof(struct mcp_irq_data) from driver point of view, allows 28581571Sobrien * adding new stuff to mcp_irq_data without changing the ABI 28676504Skris * 28772430Sobrien * If multiple slices are used, data2 contains both the size of the 28872430Sobrien * structure (in the lower 16 bits) and the slice number 28942740Sbillf * (in the upper 16 bits). 29076504Skris */ 29181571Sobrien 29281571Sobrien MXGEFW_CMD_UNALIGNED_TEST = 32, 29376504Skris /* same than DMA_TEST (same args) but abort with UNALIGNED on unaligned 29476504Skris chipset */ 29581571Sobrien 29681571Sobrien MXGEFW_CMD_UNALIGNED_STATUS = 33, 29776504Skris /* return data = boolean, true if the chipset is known to be unaligned */ 29876504Skris 29972430Sobrien MXGEFW_CMD_ALWAYS_USE_N_BIG_BUFFERS = 34, 30081571Sobrien /* data0 = number of big buffers to use. It must be 0 or a power of 2. 30181571Sobrien * 0 indicates that the NIC consumes as many buffers as they are required 30276504Skris * for packet. This is the default behavior. 30372430Sobrien * A power of 2 number indicates that the NIC always uses the specified 30447916Sobrien * number of buffers for each big receive packet. 30581571Sobrien * It is up to the driver to ensure that this value is big enough for 30676504Skris * the NIC to be able to receive maximum-sized packets. 30747916Sobrien */ 30872430Sobrien 30976504Skris MXGEFW_CMD_GET_MAX_RSS_QUEUES = 35, 31076504Skris MXGEFW_CMD_ENABLE_RSS_QUEUES = 36, 31181571Sobrien /* data0 = number of slices n (0, 1, ..., n-1) to enable 31281571Sobrien * data1 = interrupt mode | use of multiple transmit queues. 31376504Skris * 0=share one INTx/MSI. 31480409Skris * 1=use one MSI-X per queue. 31576504Skris * If all queues share one interrupt, the driver must have set 31676504Skris * RSS_SHARED_INTERRUPT_DMA before enabling queues. 31742740Sbillf * 2=enable both receive and send queues. 31881571Sobrien * Without this bit set, only one send queue (slice 0's send queue) 31976504Skris * is enabled. The receive queues are always enabled. 32072430Sobrien */ 32147916Sobrien#define MXGEFW_SLICE_INTR_MODE_SHARED 0x0 32242740Sbillf#define MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE 0x1 32342740Sbillf#define MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES 0x2 32442786Sbillf 32530221Scharnier MXGEFW_CMD_GET_RSS_SHARED_INTERRUPT_MASK_OFFSET = 37, 32630221Scharnier MXGEFW_CMD_SET_RSS_SHARED_INTERRUPT_DMA = 38, 327327Sjkh /* data0, data1 = bus address lsw, msw */ 32830221Scharnier MXGEFW_CMD_GET_RSS_TABLE_OFFSET = 39, 329154145Sflz /* get the offset of the indirection table */ 330126465Skensmith MXGEFW_CMD_SET_RSS_TABLE_SIZE = 40, 331327Sjkh /* set the size of the indirection table */ 332327Sjkh MXGEFW_CMD_GET_RSS_KEY_OFFSET = 41, 333 /* get the offset of the secret key */ 334 MXGEFW_CMD_RSS_KEY_UPDATED = 42, 335 /* tell nic that the secret key's been updated */ 336 MXGEFW_CMD_SET_RSS_ENABLE = 43, 337 /* data0 = enable/disable rss 338 * 0: disable rss. nic does not distribute receive packets. 339 * 1: enable rss. nic distributes receive packets among queues. 340 * data1 = hash type 341 * 1: IPV4 (required by RSS) 342 * 2: TCP_IPV4 (required by RSS) 343 * 3: IPV4 | TCP_IPV4 (required by RSS) 344 * 4: source port 345 * 5: source port + destination port 346 */ 347#define MXGEFW_RSS_HASH_TYPE_IPV4 0x1 348#define MXGEFW_RSS_HASH_TYPE_TCP_IPV4 0x2 349#define MXGEFW_RSS_HASH_TYPE_SRC_PORT 0x4 350#define MXGEFW_RSS_HASH_TYPE_SRC_DST_PORT 0x5 351#define MXGEFW_RSS_HASH_TYPE_MAX 0x5 352 353 MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE = 44, 354 /* Return data = the max. size of the entire headers of a IPv6 TSO packet. 355 * If the header size of a IPv6 TSO packet is larger than the specified 356 * value, then the driver must not use TSO. 357 * This size restriction only applies to IPv6 TSO. 358 * For IPv4 TSO, the maximum size of the headers is fixed, and the NIC 359 * always has enough header buffer to store maximum-sized headers. 360 */ 361 362 MXGEFW_CMD_SET_TSO_MODE = 45, 363 /* data0 = TSO mode. 364 * 0: Linux/FreeBSD style (NIC default) 365 * 1: NDIS/NetBSD style 366 */ 367#define MXGEFW_TSO_MODE_LINUX 0 368#define MXGEFW_TSO_MODE_NDIS 1 369 370 MXGEFW_CMD_MDIO_READ = 46, 371 /* data0 = dev_addr (PMA/PMD or PCS ...), data1 = register/addr */ 372 MXGEFW_CMD_MDIO_WRITE = 47, 373 /* data0 = dev_addr, data1 = register/addr, data2 = value */ 374 375 MXGEFW_CMD_I2C_READ = 48, 376 /* Starts to get a fresh copy of one byte or of the module i2c table, the 377 * obtained data is cached inside the xaui-xfi chip : 378 * data0 : 0 => get one byte, 1=> get 256 bytes 379 * data1 : If data0 == 0: location to refresh 380 * bit 7:0 register location 381 * bit 8:15 is the i2c slave addr (0 is interpreted as 0xA1) 382 * bit 23:16 is the i2c bus number (for multi-port NICs) 383 * If data0 == 1: unused 384 * The operation might take ~1ms for a single byte or ~65ms when refreshing all 256 bytes 385 * During the i2c operation, MXGEFW_CMD_I2C_READ or MXGEFW_CMD_I2C_BYTE attempts 386 * will return MXGEFW_CMD_ERROR_BUSY 387 */ 388 MXGEFW_CMD_I2C_BYTE = 49, 389 /* Return the last obtained copy of a given byte in the xfp i2c table 390 * (copy cached during the last relevant MXGEFW_CMD_I2C_READ) 391 * data0 : index of the desired table entry 392 * Return data = the byte stored at the requested index in the table 393 */ 394 395 MXGEFW_CMD_GET_VPUMP_OFFSET = 50, 396 /* Return data = NIC memory offset of mcp_vpump_public_global */ 397 MXGEFW_CMD_RESET_VPUMP = 51, 398 /* Resets the VPUMP state */ 399 400 MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE = 52, 401 /* data0 = mcp_slot type to use. 402 * 0 = the default 4B mcp_slot 403 * 1 = 8B mcp_slot_8 404 */ 405#define MXGEFW_RSS_MCP_SLOT_TYPE_MIN 0 406#define MXGEFW_RSS_MCP_SLOT_TYPE_WITH_HASH 1 407 408 MXGEFW_CMD_SET_THROTTLE_FACTOR = 53, 409 /* set the throttle factor for ethp_z8e 410 data0 = throttle_factor 411 throttle_factor = 256 * pcie-raw-speed / tx_speed 412 tx_speed = 256 * pcie-raw-speed / throttle_factor 413 414 For PCI-E x8: pcie-raw-speed == 16Gb/s 415 For PCI-E x4: pcie-raw-speed == 8Gb/s 416 417 ex1: throttle_factor == 0x1a0 (416), tx_speed == 1.23GB/s == 9.846 Gb/s 418 ex2: throttle_factor == 0x200 (512), tx_speed == 1.0GB/s == 8 Gb/s 419 420 with tx_boundary == 2048, max-throttle-factor == 8191 => min-speed == 500Mb/s 421 with tx_boundary == 4096, max-throttle-factor == 4095 => min-speed == 1Gb/s 422 */ 423 424 MXGEFW_CMD_VPUMP_UP = 54, 425 /* Allocates VPump Connection, Send Request and Zero copy buffer address tables */ 426 MXGEFW_CMD_GET_VPUMP_CLK = 55, 427 /* Get the lanai clock */ 428 429 MXGEFW_CMD_GET_DCA_OFFSET = 56, 430 /* offset of dca control for WDMAs */ 431 432 /* VMWare NetQueue commands */ 433 MXGEFW_CMD_NETQ_GET_FILTERS_PER_QUEUE = 57, 434 MXGEFW_CMD_NETQ_ADD_FILTER = 58, 435 /* data0 = filter_id << 16 | queue << 8 | type */ 436 /* data1 = MS4 of MAC Addr */ 437 /* data2 = LS2_MAC << 16 | VLAN_tag */ 438 MXGEFW_CMD_NETQ_DEL_FILTER = 59, 439 /* data0 = filter_id */ 440 MXGEFW_CMD_NETQ_QUERY1 = 60, 441 MXGEFW_CMD_NETQ_QUERY2 = 61, 442 MXGEFW_CMD_NETQ_QUERY3 = 62, 443 MXGEFW_CMD_NETQ_QUERY4 = 63, 444 445 MXGEFW_CMD_RELAX_RXBUFFER_ALIGNMENT = 64, 446 /* When set, small receive buffers can cross page boundaries. 447 * Both small and big receive buffers may start at any address. 448 * This option has performance implications, so use with caution. 449 */ 450}; 451typedef enum myri10ge_mcp_cmd_type myri10ge_mcp_cmd_type_t; 452 453 454enum myri10ge_mcp_cmd_status { 455 MXGEFW_CMD_OK = 0, 456 MXGEFW_CMD_UNKNOWN = 1, 457 MXGEFW_CMD_ERROR_RANGE = 2, 458 MXGEFW_CMD_ERROR_BUSY = 3, 459 MXGEFW_CMD_ERROR_EMPTY = 4, 460 MXGEFW_CMD_ERROR_CLOSED = 5, 461 MXGEFW_CMD_ERROR_HASH_ERROR = 6, 462 MXGEFW_CMD_ERROR_BAD_PORT = 7, 463 MXGEFW_CMD_ERROR_RESOURCES = 8, 464 MXGEFW_CMD_ERROR_MULTICAST = 9, 465 MXGEFW_CMD_ERROR_UNALIGNED = 10, 466 MXGEFW_CMD_ERROR_NO_MDIO = 11, 467 MXGEFW_CMD_ERROR_I2C_FAILURE = 12, 468 MXGEFW_CMD_ERROR_I2C_ABSENT = 13, 469 MXGEFW_CMD_ERROR_BAD_PCIE_LINK = 14 470}; 471typedef enum myri10ge_mcp_cmd_status myri10ge_mcp_cmd_status_t; 472 473 474#define MXGEFW_OLD_IRQ_DATA_LEN 40 475 476struct mcp_irq_data { 477 /* add new counters at the beginning */ 478 uint32_t future_use[1]; 479 uint32_t dropped_pause; 480 uint32_t dropped_unicast_filtered; 481 uint32_t dropped_bad_crc32; 482 uint32_t dropped_bad_phy; 483 uint32_t dropped_multicast_filtered; 484/* 40 Bytes */ 485 uint32_t send_done_count; 486 487#define MXGEFW_LINK_DOWN 0 488#define MXGEFW_LINK_UP 1 489#define MXGEFW_LINK_MYRINET 2 490#define MXGEFW_LINK_UNKNOWN 3 491 uint32_t link_up; 492 uint32_t dropped_link_overflow; 493 uint32_t dropped_link_error_or_filtered; 494 uint32_t dropped_runt; 495 uint32_t dropped_overrun; 496 uint32_t dropped_no_small_buffer; 497 uint32_t dropped_no_big_buffer; 498 uint32_t rdma_tags_available; 499 500 uint8_t tx_stopped; 501 uint8_t link_down; 502 uint8_t stats_updated; 503 uint8_t valid; 504}; 505typedef struct mcp_irq_data mcp_irq_data_t; 506 507#ifdef MXGEFW_NDIS 508/* Exclusively used by NDIS drivers */ 509struct mcp_rss_shared_interrupt { 510 uint8_t pad[2]; 511 uint8_t queue; 512 uint8_t valid; 513}; 514#endif 515 516/* definitions for NETQ filter type */ 517#define MXGEFW_NETQ_FILTERTYPE_NONE 0 518#define MXGEFW_NETQ_FILTERTYPE_MACADDR 1 519#define MXGEFW_NETQ_FILTERTYPE_VLAN 2 520#define MXGEFW_NETQ_FILTERTYPE_VLANMACADDR 3 521 522#endif /* _myri10ge_mcp_h */ 523