1/******************************************************************************* 2 3Copyright (c) 2006-2009, Myricom Inc. 4All rights reserved. 5 6Redistribution and use in source and binary forms, with or without 7modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Neither the name of the Myricom Inc, nor the names of its 13 contributors may be used to endorse or promote products derived from 14 this software without specific prior written permission. 15 16THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 20LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26POSSIBILITY OF SUCH DAMAGE. 27 28$FreeBSD$ 29***************************************************************************/ 30 31#ifndef _myri10ge_mcp_h 32#define _myri10ge_mcp_h 33 34#define MXGEFW_VERSION_MAJOR 1 35#define MXGEFW_VERSION_MINOR 4 36 37#if defined MXGEFW && !defined _stdint_h_ 38typedef signed char int8_t; 39typedef signed short int16_t; 40typedef signed int int32_t; 41typedef signed long long int64_t; 42typedef unsigned char uint8_t; 43typedef unsigned short uint16_t; 44typedef unsigned int uint32_t; 45typedef unsigned long long uint64_t; 46#endif 47 48/* 8 Bytes */ 49struct mcp_dma_addr { 50 uint32_t high; 51 uint32_t low; 52}; 53typedef struct mcp_dma_addr mcp_dma_addr_t; 54 55/* 4 Bytes */ 56struct mcp_slot { 57 uint16_t checksum; 58 uint16_t length; 59}; 60typedef struct mcp_slot mcp_slot_t; 61 62#ifdef MXGEFW_NDIS 63/* 8-byte descriptor, exclusively used by NDIS drivers. */ 64struct mcp_slot_8 { 65 /* Place hash value at the top so it gets written before length. 66 * The driver polls length. 67 */ 68 uint32_t hash; 69 uint16_t checksum; 70 uint16_t length; 71}; 72typedef struct mcp_slot_8 mcp_slot_8_t; 73 74/* Two bits of length in mcp_slot are used to indicate hash type. */ 75#define MXGEFW_RSS_HASH_NULL (0 << 14) /* bit 15:14 = 00 */ 76#define MXGEFW_RSS_HASH_IPV4 (1 << 14) /* bit 15:14 = 01 */ 77#define MXGEFW_RSS_HASH_TCP_IPV4 (2 << 14) /* bit 15:14 = 10 */ 78#define MXGEFW_RSS_HASH_MASK (3 << 14) /* bit 15:14 = 11 */ 79#endif 80 81/* 64 Bytes */ 82struct mcp_cmd { 83 uint32_t cmd; 84 uint32_t data0; /* will be low portion if data > 32 bits */ 85 /* 8 */ 86 uint32_t data1; /* will be high portion if data > 32 bits */ 87 uint32_t data2; /* currently unused.. */ 88 /* 16 */ 89 struct mcp_dma_addr response_addr; 90 /* 24 */ 91 uint8_t pad[40]; 92}; 93typedef struct mcp_cmd mcp_cmd_t; 94 95/* 8 Bytes */ 96struct mcp_cmd_response { 97 uint32_t data; 98 uint32_t result; 99}; 100typedef struct mcp_cmd_response mcp_cmd_response_t; 101 102 103 104/* 105 flags used in mcp_kreq_ether_send_t: 106 107 The SMALL flag is only needed in the first segment. It is raised 108 for packets that are total less or equal 512 bytes. 109 110 The CKSUM flag must be set in all segments. 111 112 The PADDED flags is set if the packet needs to be padded, and it 113 must be set for all segments. 114 115 The MXGEFW_FLAGS_ALIGN_ODD must be set if the cumulative 116 length of all previous segments was odd. 117*/ 118 119 120#define MXGEFW_FLAGS_SMALL 0x1 121#define MXGEFW_FLAGS_TSO_HDR 0x1 122#define MXGEFW_FLAGS_FIRST 0x2 123#define MXGEFW_FLAGS_ALIGN_ODD 0x4 124#define MXGEFW_FLAGS_CKSUM 0x8 125#define MXGEFW_FLAGS_TSO_LAST 0x8 126#define MXGEFW_FLAGS_NO_TSO 0x10 127#define MXGEFW_FLAGS_TSO_CHOP 0x10 128#define MXGEFW_FLAGS_TSO_PLD 0x20 129 130#define MXGEFW_SEND_SMALL_SIZE 1520 131#define MXGEFW_MAX_MTU 9400 132 133union mcp_pso_or_cumlen { 134 uint16_t pseudo_hdr_offset; 135 uint16_t cum_len; 136}; 137typedef union mcp_pso_or_cumlen mcp_pso_or_cumlen_t; 138 139#define MXGEFW_MAX_SEND_DESC 12 140#define MXGEFW_PAD 2 141 142/* 16 Bytes */ 143struct mcp_kreq_ether_send { 144 uint32_t addr_high; 145 uint32_t addr_low; 146 uint16_t pseudo_hdr_offset; 147 uint16_t length; 148 uint8_t pad; 149 uint8_t rdma_count; 150 uint8_t cksum_offset; /* where to start computing cksum */ 151 uint8_t flags; /* as defined above */ 152}; 153typedef struct mcp_kreq_ether_send mcp_kreq_ether_send_t; 154 155/* 8 Bytes */ 156struct mcp_kreq_ether_recv { 157 uint32_t addr_high; 158 uint32_t addr_low; 159}; 160typedef struct mcp_kreq_ether_recv mcp_kreq_ether_recv_t; 161 162 163/* Commands */ 164 165#define MXGEFW_BOOT_HANDOFF 0xfc0000 166#define MXGEFW_BOOT_DUMMY_RDMA 0xfc01c0 167 168#define MXGEFW_ETH_CMD 0xf80000 169#define MXGEFW_ETH_SEND_4 0x200000 170#define MXGEFW_ETH_SEND_1 0x240000 171#define MXGEFW_ETH_SEND_2 0x280000 172#define MXGEFW_ETH_SEND_3 0x2c0000 173#define MXGEFW_ETH_RECV_SMALL 0x300000 174#define MXGEFW_ETH_RECV_BIG 0x340000 175#define MXGEFW_ETH_SEND_GO 0x380000 176#define MXGEFW_ETH_SEND_STOP 0x3C0000 177 178#define MXGEFW_ETH_SEND(n) (0x200000 + (((n) & 0x03) * 0x40000)) 179#define MXGEFW_ETH_SEND_OFFSET(n) (MXGEFW_ETH_SEND(n) - MXGEFW_ETH_SEND_4) 180 181enum myri10ge_mcp_cmd_type { 182 MXGEFW_CMD_NONE = 0, 183 /* Reset the mcp, it is left in a safe state, waiting 184 for the driver to set all its parameters */ 185 MXGEFW_CMD_RESET = 1, 186 187 /* get the version number of the current firmware.. 188 (may be available in the eeprom strings..? */ 189 MXGEFW_GET_MCP_VERSION = 2, 190 191 192 /* Parameters which must be set by the driver before it can 193 issue MXGEFW_CMD_ETHERNET_UP. They persist until the next 194 MXGEFW_CMD_RESET is issued */ 195 196 MXGEFW_CMD_SET_INTRQ_DMA = 3, 197 /* data0 = LSW of the host address 198 * data1 = MSW of the host address 199 * data2 = slice number if multiple slices are used 200 */ 201 202 MXGEFW_CMD_SET_BIG_BUFFER_SIZE = 4, /* in bytes, power of 2 */ 203 MXGEFW_CMD_SET_SMALL_BUFFER_SIZE = 5, /* in bytes */ 204 205 206 /* Parameters which refer to lanai SRAM addresses where the 207 driver must issue PIO writes for various things */ 208 209 MXGEFW_CMD_GET_SEND_OFFSET = 6, 210 MXGEFW_CMD_GET_SMALL_RX_OFFSET = 7, 211 MXGEFW_CMD_GET_BIG_RX_OFFSET = 8, 212 /* data0 = slice number if multiple slices are used */ 213 214 MXGEFW_CMD_GET_IRQ_ACK_OFFSET = 9, 215 MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET = 10, 216 217 /* Parameters which refer to rings stored on the MCP, 218 and whose size is controlled by the mcp */ 219 220 MXGEFW_CMD_GET_SEND_RING_SIZE = 11, /* in bytes */ 221 MXGEFW_CMD_GET_RX_RING_SIZE = 12, /* in bytes */ 222 223 /* Parameters which refer to rings stored in the host, 224 and whose size is controlled by the host. Note that 225 all must be physically contiguous and must contain 226 a power of 2 number of entries. */ 227 228 MXGEFW_CMD_SET_INTRQ_SIZE = 13, /* in bytes */ 229#define MXGEFW_CMD_SET_INTRQ_SIZE_FLAG_NO_STRICT_SIZE_CHECK (1U << 31) 230 231 /* command to bring ethernet interface up. Above parameters 232 (plus mtu & mac address) must have been exchanged prior 233 to issuing this command */ 234 MXGEFW_CMD_ETHERNET_UP = 14, 235 236 /* command to bring ethernet interface down. No further sends 237 or receives may be processed until an MXGEFW_CMD_ETHERNET_UP 238 is issued, and all interrupt queues must be flushed prior 239 to ack'ing this command */ 240 241 MXGEFW_CMD_ETHERNET_DOWN = 15, 242 243 /* commands the driver may issue live, without resetting 244 the nic. Note that increasing the mtu "live" should 245 only be done if the driver has already supplied buffers 246 sufficiently large to handle the new mtu. Decreasing 247 the mtu live is safe */ 248 249 MXGEFW_CMD_SET_MTU = 16, 250 MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET = 17, /* in microseconds */ 251 MXGEFW_CMD_SET_STATS_INTERVAL = 18, /* in microseconds */ 252 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE = 19, /* replaced by SET_STATS_DMA_V2 */ 253 254 MXGEFW_ENABLE_PROMISC = 20, 255 MXGEFW_DISABLE_PROMISC = 21, 256 MXGEFW_SET_MAC_ADDRESS = 22, 257 258 MXGEFW_ENABLE_FLOW_CONTROL = 23, 259 MXGEFW_DISABLE_FLOW_CONTROL = 24, 260 261 /* do a DMA test 262 data0,data1 = DMA address 263 data2 = RDMA length (MSH), WDMA length (LSH) 264 command return data = repetitions (MSH), 0.5-ms ticks (LSH) 265 */ 266 MXGEFW_DMA_TEST = 25, 267 268 MXGEFW_ENABLE_ALLMULTI = 26, 269 MXGEFW_DISABLE_ALLMULTI = 27, 270 271 /* returns MXGEFW_CMD_ERROR_MULTICAST 272 if there is no room in the cache 273 data0,MSH(data1) = multicast group address */ 274 MXGEFW_JOIN_MULTICAST_GROUP = 28, 275 /* returns MXGEFW_CMD_ERROR_MULTICAST 276 if the address is not in the cache, 277 or is equal to FF-FF-FF-FF-FF-FF 278 data0,MSH(data1) = multicast group address */ 279 MXGEFW_LEAVE_MULTICAST_GROUP = 29, 280 MXGEFW_LEAVE_ALL_MULTICAST_GROUPS = 30, 281 282 MXGEFW_CMD_SET_STATS_DMA_V2 = 31, 283 /* data0, data1 = bus addr, 284 * data2 = sizeof(struct mcp_irq_data) from driver point of view, allows 285 * adding new stuff to mcp_irq_data without changing the ABI 286 * 287 * If multiple slices are used, data2 contains both the size of the 288 * structure (in the lower 16 bits) and the slice number 289 * (in the upper 16 bits). 290 */ 291 292 MXGEFW_CMD_UNALIGNED_TEST = 32, 293 /* same than DMA_TEST (same args) but abort with UNALIGNED on unaligned 294 chipset */ 295 296 MXGEFW_CMD_UNALIGNED_STATUS = 33, 297 /* return data = boolean, true if the chipset is known to be unaligned */ 298 299 MXGEFW_CMD_ALWAYS_USE_N_BIG_BUFFERS = 34, 300 /* data0 = number of big buffers to use. It must be 0 or a power of 2. 301 * 0 indicates that the NIC consumes as many buffers as they are required 302 * for packet. This is the default behavior. 303 * A power of 2 number indicates that the NIC always uses the specified 304 * number of buffers for each big receive packet. 305 * It is up to the driver to ensure that this value is big enough for 306 * the NIC to be able to receive maximum-sized packets. 307 */ 308 309 MXGEFW_CMD_GET_MAX_RSS_QUEUES = 35, 310 MXGEFW_CMD_ENABLE_RSS_QUEUES = 36, 311 /* data0 = number of slices n (0, 1, ..., n-1) to enable 312 * data1 = interrupt mode | use of multiple transmit queues. 313 * 0=share one INTx/MSI. 314 * 1=use one MSI-X per queue. 315 * If all queues share one interrupt, the driver must have set 316 * RSS_SHARED_INTERRUPT_DMA before enabling queues. 317 * 2=enable both receive and send queues. 318 * Without this bit set, only one send queue (slice 0's send queue) 319 * is enabled. The receive queues are always enabled. 320 */ 321#define MXGEFW_SLICE_INTR_MODE_SHARED 0x0 322#define MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE 0x1 323#define MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES 0x2 324 325 MXGEFW_CMD_GET_RSS_SHARED_INTERRUPT_MASK_OFFSET = 37, 326 MXGEFW_CMD_SET_RSS_SHARED_INTERRUPT_DMA = 38, 327 /* data0, data1 = bus address lsw, msw */ 328 MXGEFW_CMD_GET_RSS_TABLE_OFFSET = 39, 329 /* get the offset of the indirection table */ 330 MXGEFW_CMD_SET_RSS_TABLE_SIZE = 40, 331 /* set the size of the indirection table */ 332 MXGEFW_CMD_GET_RSS_KEY_OFFSET = 41, 333 /* get the offset of the secret key */ 334 MXGEFW_CMD_RSS_KEY_UPDATED = 42, 335 /* tell nic that the secret key's been updated */ 336 MXGEFW_CMD_SET_RSS_ENABLE = 43, 337 /* data0 = enable/disable rss 338 * 0: disable rss. nic does not distribute receive packets. 339 * 1: enable rss. nic distributes receive packets among queues. 340 * data1 = hash type 341 * 1: IPV4 (required by RSS) 342 * 2: TCP_IPV4 (required by RSS) 343 * 3: IPV4 | TCP_IPV4 (required by RSS) 344 * 4: source port 345 * 5: source port + destination port 346 */ 347#define MXGEFW_RSS_HASH_TYPE_IPV4 0x1 348#define MXGEFW_RSS_HASH_TYPE_TCP_IPV4 0x2 349#define MXGEFW_RSS_HASH_TYPE_SRC_PORT 0x4 350#define MXGEFW_RSS_HASH_TYPE_SRC_DST_PORT 0x5 351#define MXGEFW_RSS_HASH_TYPE_MAX 0x5 352 353 MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE = 44, 354 /* Return data = the max. size of the entire headers of a IPv6 TSO packet. 355 * If the header size of a IPv6 TSO packet is larger than the specified 356 * value, then the driver must not use TSO. 357 * This size restriction only applies to IPv6 TSO. 358 * For IPv4 TSO, the maximum size of the headers is fixed, and the NIC 359 * always has enough header buffer to store maximum-sized headers. 360 */ 361 362 MXGEFW_CMD_SET_TSO_MODE = 45, 363 /* data0 = TSO mode. 364 * 0: Linux/FreeBSD style (NIC default) 365 * 1: NDIS/NetBSD style 366 */ 367#define MXGEFW_TSO_MODE_LINUX 0 368#define MXGEFW_TSO_MODE_NDIS 1 369 370 MXGEFW_CMD_MDIO_READ = 46, 371 /* data0 = dev_addr (PMA/PMD or PCS ...), data1 = register/addr */ 372 MXGEFW_CMD_MDIO_WRITE = 47, 373 /* data0 = dev_addr, data1 = register/addr, data2 = value */ 374 375 MXGEFW_CMD_I2C_READ = 48, 376 /* Starts to get a fresh copy of one byte or of the module i2c table, the 377 * obtained data is cached inside the xaui-xfi chip : 378 * data0 : 0 => get one byte, 1=> get 256 bytes 379 * data1 : If data0 == 0: location to refresh 380 * bit 7:0 register location 381 * bit 8:15 is the i2c slave addr (0 is interpreted as 0xA1) 382 * bit 23:16 is the i2c bus number (for multi-port NICs) 383 * If data0 == 1: unused 384 * The operation might take ~1ms for a single byte or ~65ms when refreshing all 256 bytes 385 * During the i2c operation, MXGEFW_CMD_I2C_READ or MXGEFW_CMD_I2C_BYTE attempts 386 * will return MXGEFW_CMD_ERROR_BUSY 387 */ 388 MXGEFW_CMD_I2C_BYTE = 49, 389 /* Return the last obtained copy of a given byte in the xfp i2c table 390 * (copy cached during the last relevant MXGEFW_CMD_I2C_READ) 391 * data0 : index of the desired table entry 392 * Return data = the byte stored at the requested index in the table 393 */ 394 395 MXGEFW_CMD_GET_VPUMP_OFFSET = 50, 396 /* Return data = NIC memory offset of mcp_vpump_public_global */ 397 MXGEFW_CMD_RESET_VPUMP = 51, 398 /* Resets the VPUMP state */ 399 400 MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE = 52, 401 /* data0 = mcp_slot type to use. 402 * 0 = the default 4B mcp_slot 403 * 1 = 8B mcp_slot_8 404 */ 405#define MXGEFW_RSS_MCP_SLOT_TYPE_MIN 0 406#define MXGEFW_RSS_MCP_SLOT_TYPE_WITH_HASH 1 407 408 MXGEFW_CMD_SET_THROTTLE_FACTOR = 53, 409 /* set the throttle factor for ethp_z8e 410 data0 = throttle_factor 411 throttle_factor = 256 * pcie-raw-speed / tx_speed 412 tx_speed = 256 * pcie-raw-speed / throttle_factor 413 414 For PCI-E x8: pcie-raw-speed == 16Gb/s 415 For PCI-E x4: pcie-raw-speed == 8Gb/s 416 417 ex1: throttle_factor == 0x1a0 (416), tx_speed == 1.23GB/s == 9.846 Gb/s 418 ex2: throttle_factor == 0x200 (512), tx_speed == 1.0GB/s == 8 Gb/s 419 420 with tx_boundary == 2048, max-throttle-factor == 8191 => min-speed == 500Mb/s 421 with tx_boundary == 4096, max-throttle-factor == 4095 => min-speed == 1Gb/s 422 */ 423 424 MXGEFW_CMD_VPUMP_UP = 54, 425 /* Allocates VPump Connection, Send Request and Zero copy buffer address tables */ 426 MXGEFW_CMD_GET_VPUMP_CLK = 55, 427 /* Get the lanai clock */ 428 429 MXGEFW_CMD_GET_DCA_OFFSET = 56, 430 /* offset of dca control for WDMAs */ 431 432 /* VMWare NetQueue commands */ 433 MXGEFW_CMD_NETQ_GET_FILTERS_PER_QUEUE = 57, 434 MXGEFW_CMD_NETQ_ADD_FILTER = 58, 435 /* data0 = filter_id << 16 | queue << 8 | type */ 436 /* data1 = MS4 of MAC Addr */ 437 /* data2 = LS2_MAC << 16 | VLAN_tag */ 438 MXGEFW_CMD_NETQ_DEL_FILTER = 59, 439 /* data0 = filter_id */ 440 MXGEFW_CMD_NETQ_QUERY1 = 60, 441 MXGEFW_CMD_NETQ_QUERY2 = 61, 442 MXGEFW_CMD_NETQ_QUERY3 = 62, 443 MXGEFW_CMD_NETQ_QUERY4 = 63, 444 445 MXGEFW_CMD_RELAX_RXBUFFER_ALIGNMENT = 64, 446 /* When set, small receive buffers can cross page boundaries. 447 * Both small and big receive buffers may start at any address. 448 * This option has performance implications, so use with caution. 449 */ 450}; 451typedef enum myri10ge_mcp_cmd_type myri10ge_mcp_cmd_type_t; 452 453 454enum myri10ge_mcp_cmd_status { 455 MXGEFW_CMD_OK = 0, 456 MXGEFW_CMD_UNKNOWN = 1, 457 MXGEFW_CMD_ERROR_RANGE = 2, 458 MXGEFW_CMD_ERROR_BUSY = 3, 459 MXGEFW_CMD_ERROR_EMPTY = 4, 460 MXGEFW_CMD_ERROR_CLOSED = 5, 461 MXGEFW_CMD_ERROR_HASH_ERROR = 6, 462 MXGEFW_CMD_ERROR_BAD_PORT = 7, 463 MXGEFW_CMD_ERROR_RESOURCES = 8, 464 MXGEFW_CMD_ERROR_MULTICAST = 9, 465 MXGEFW_CMD_ERROR_UNALIGNED = 10, 466 MXGEFW_CMD_ERROR_NO_MDIO = 11, 467 MXGEFW_CMD_ERROR_I2C_FAILURE = 12, 468 MXGEFW_CMD_ERROR_I2C_ABSENT = 13, 469 MXGEFW_CMD_ERROR_BAD_PCIE_LINK = 14 470}; 471typedef enum myri10ge_mcp_cmd_status myri10ge_mcp_cmd_status_t; 472 473 474#define MXGEFW_OLD_IRQ_DATA_LEN 40 475 476struct mcp_irq_data { 477 /* add new counters at the beginning */ 478 uint32_t future_use[1]; 479 uint32_t dropped_pause; 480 uint32_t dropped_unicast_filtered; 481 uint32_t dropped_bad_crc32; 482 uint32_t dropped_bad_phy; 483 uint32_t dropped_multicast_filtered; 484/* 40 Bytes */ 485 uint32_t send_done_count; 486 487#define MXGEFW_LINK_DOWN 0 488#define MXGEFW_LINK_UP 1 489#define MXGEFW_LINK_MYRINET 2 490#define MXGEFW_LINK_UNKNOWN 3 491 uint32_t link_up; 492 uint32_t dropped_link_overflow; 493 uint32_t dropped_link_error_or_filtered; 494 uint32_t dropped_runt; 495 uint32_t dropped_overrun; 496 uint32_t dropped_no_small_buffer; 497 uint32_t dropped_no_big_buffer; 498 uint32_t rdma_tags_available; 499 500 uint8_t tx_stopped; 501 uint8_t link_down; 502 uint8_t stats_updated; 503 uint8_t valid; 504}; 505typedef struct mcp_irq_data mcp_irq_data_t; 506 507#ifdef MXGEFW_NDIS 508/* Exclusively used by NDIS drivers */ 509struct mcp_rss_shared_interrupt { 510 uint8_t pad[2]; 511 uint8_t queue; 512 uint8_t valid; 513}; 514#endif 515 516/* definitions for NETQ filter type */ 517#define MXGEFW_NETQ_FILTERTYPE_NONE 0 518#define MXGEFW_NETQ_FILTERTYPE_MACADDR 1 519#define MXGEFW_NETQ_FILTERTYPE_VLAN 2 520#define MXGEFW_NETQ_FILTERTYPE_VLANMACADDR 3 521 522#endif /* _myri10ge_mcp_h */ 523