mxge_mcp.h revision 183515
1117632Sharti/******************************************************************************* 2117632Sharti 3117632ShartiCopyright (c) 2006-2008, Myricom Inc. 4117632ShartiAll rights reserved. 5117632Sharti 6117632ShartiRedistribution and use in source and binary forms, with or without 7117632Shartimodification, are permitted provided that the following conditions are met: 8117632Sharti 9117632Sharti 1. Redistributions of source code must retain the above copyright notice, 10117632Sharti this list of conditions and the following disclaimer. 11117632Sharti 12117632Sharti 2. Neither the name of the Myricom Inc, nor the names of its 13117632Sharti contributors may be used to endorse or promote products derived from 14117632Sharti this software without specific prior written permission. 15117632Sharti 16117632ShartiTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17117632ShartiAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18117632ShartiIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19117632ShartiARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 20117632ShartiLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21117632ShartiCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22117632ShartiSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23117632ShartiINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24117632ShartiCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25117632ShartiARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26117632ShartiPOSSIBILITY OF SUCH DAMAGE. 27117632Sharti 28117632Sharti$FreeBSD: head/sys/dev/mxge/mxge_mcp.h 183515 2008-10-01 16:23:35Z gallatin $ 29117632Sharti***************************************************************************/ 30117632Sharti 31117632Sharti#ifndef _myri10ge_mcp_h 32117632Sharti#define _myri10ge_mcp_h 33117632Sharti 34117632Sharti#define MXGEFW_VERSION_MAJOR 1 35117632Sharti#define MXGEFW_VERSION_MINOR 4 36117632Sharti 37117632Sharti#ifdef MXGEFW 38117632Shartitypedef signed char int8_t; 39117632Shartitypedef signed short int16_t; 40117632Shartitypedef signed int int32_t; 41117632Shartitypedef signed long long int64_t; 42117632Shartitypedef unsigned char uint8_t; 43117632Shartitypedef unsigned short uint16_t; 44117632Shartitypedef unsigned int uint32_t; 45117632Shartitypedef unsigned long long uint64_t; 46117632Sharti#endif 47117632Sharti 48117632Sharti/* 8 Bytes */ 49117632Shartistruct mcp_dma_addr { 50117632Sharti uint32_t high; 51117632Sharti uint32_t low; 52117632Sharti}; 53117632Shartitypedef struct mcp_dma_addr mcp_dma_addr_t; 54117632Sharti 55117632Sharti/* 4 Bytes */ 56117632Shartistruct mcp_slot { 57117632Sharti uint16_t checksum; 58117632Sharti uint16_t length; 59117632Sharti}; 60117632Shartitypedef struct mcp_slot mcp_slot_t; 61117632Sharti 62117632Sharti#ifdef MXGEFW_NDIS 63117632Sharti/* 8-byte descriptor, exclusively used by NDIS drivers. */ 64117632Shartistruct mcp_slot_8 { 65117632Sharti /* Place hash value at the top so it gets written before length. 66117632Sharti * The driver polls length. 67117632Sharti */ 68117632Sharti uint32_t hash; 69117632Sharti uint16_t checksum; 70117632Sharti uint16_t length; 71117632Sharti}; 72117632Shartitypedef struct mcp_slot_8 mcp_slot_8_t; 73117632Sharti 74117632Sharti/* Two bits of length in mcp_slot are used to indicate hash type. */ 75117632Sharti#define MXGEFW_RSS_HASH_NULL (0 << 14) /* bit 15:14 = 00 */ 76117632Sharti#define MXGEFW_RSS_HASH_IPV4 (1 << 14) /* bit 15:14 = 01 */ 77117632Sharti#define MXGEFW_RSS_HASH_TCP_IPV4 (2 << 14) /* bit 15:14 = 10 */ 78117632Sharti#define MXGEFW_RSS_HASH_MASK (3 << 14) /* bit 15:14 = 11 */ 79117632Sharti#endif 80117632Sharti 81117632Sharti/* 64 Bytes */ 82117632Shartistruct mcp_cmd { 83117632Sharti uint32_t cmd; 84117632Sharti uint32_t data0; /* will be low portion if data > 32 bits */ 85117632Sharti /* 8 */ 86117632Sharti uint32_t data1; /* will be high portion if data > 32 bits */ 87117632Sharti uint32_t data2; /* currently unused.. */ 88117632Sharti /* 16 */ 89117632Sharti struct mcp_dma_addr response_addr; 90117632Sharti /* 24 */ 91117632Sharti uint8_t pad[40]; 92117632Sharti}; 93117632Shartitypedef struct mcp_cmd mcp_cmd_t; 94117632Sharti 95117632Sharti/* 8 Bytes */ 96117632Shartistruct mcp_cmd_response { 97117632Sharti uint32_t data; 98117632Sharti uint32_t result; 99117632Sharti}; 100117632Shartitypedef struct mcp_cmd_response mcp_cmd_response_t; 101117632Sharti 102117632Sharti 103117632Sharti 104117632Sharti/* 105117632Sharti flags used in mcp_kreq_ether_send_t: 106117632Sharti 107117632Sharti The SMALL flag is only needed in the first segment. It is raised 108117632Sharti for packets that are total less or equal 512 bytes. 109117632Sharti 110117632Sharti The CKSUM flag must be set in all segments. 111117632Sharti 112117632Sharti The PADDED flags is set if the packet needs to be padded, and it 113117632Sharti must be set for all segments. 114117632Sharti 115117632Sharti The MXGEFW_FLAGS_ALIGN_ODD must be set if the cumulative 116117632Sharti length of all previous segments was odd. 117117632Sharti*/ 118117632Sharti 119117632Sharti 120117632Sharti#define MXGEFW_FLAGS_SMALL 0x1 121117632Sharti#define MXGEFW_FLAGS_TSO_HDR 0x1 122117632Sharti#define MXGEFW_FLAGS_FIRST 0x2 123117632Sharti#define MXGEFW_FLAGS_ALIGN_ODD 0x4 124117632Sharti#define MXGEFW_FLAGS_CKSUM 0x8 125117632Sharti#define MXGEFW_FLAGS_TSO_LAST 0x8 126117632Sharti#define MXGEFW_FLAGS_NO_TSO 0x10 127117632Sharti#define MXGEFW_FLAGS_TSO_CHOP 0x10 128117632Sharti#define MXGEFW_FLAGS_TSO_PLD 0x20 129117632Sharti 130117632Sharti#define MXGEFW_SEND_SMALL_SIZE 1520 131117632Sharti#define MXGEFW_MAX_MTU 9400 132117632Sharti 133117632Shartiunion mcp_pso_or_cumlen { 134117632Sharti uint16_t pseudo_hdr_offset; 135117632Sharti uint16_t cum_len; 136117632Sharti}; 137117632Shartitypedef union mcp_pso_or_cumlen mcp_pso_or_cumlen_t; 138117632Sharti 139117632Sharti#define MXGEFW_MAX_SEND_DESC 12 140117632Sharti#define MXGEFW_PAD 2 141117632Sharti 142117632Sharti/* 16 Bytes */ 143117632Shartistruct mcp_kreq_ether_send { 144117632Sharti uint32_t addr_high; 145117632Sharti uint32_t addr_low; 146117632Sharti uint16_t pseudo_hdr_offset; 147117632Sharti uint16_t length; 148117632Sharti uint8_t pad; 149117632Sharti uint8_t rdma_count; 150117632Sharti uint8_t cksum_offset; /* where to start computing cksum */ 151117632Sharti uint8_t flags; /* as defined above */ 152117632Sharti}; 153117632Shartitypedef struct mcp_kreq_ether_send mcp_kreq_ether_send_t; 154117632Sharti 155117632Sharti/* 8 Bytes */ 156117632Shartistruct mcp_kreq_ether_recv { 157117632Sharti uint32_t addr_high; 158117632Sharti uint32_t addr_low; 159117632Sharti}; 160117632Shartitypedef struct mcp_kreq_ether_recv mcp_kreq_ether_recv_t; 161117632Sharti 162117632Sharti 163117632Sharti/* Commands */ 164117632Sharti 165117632Sharti#define MXGEFW_BOOT_HANDOFF 0xfc0000 166117632Sharti#define MXGEFW_BOOT_DUMMY_RDMA 0xfc01c0 167117632Sharti 168117632Sharti#define MXGEFW_ETH_CMD 0xf80000 169117632Sharti#define MXGEFW_ETH_SEND_4 0x200000 170117632Sharti#define MXGEFW_ETH_SEND_1 0x240000 171117632Sharti#define MXGEFW_ETH_SEND_2 0x280000 172117632Sharti#define MXGEFW_ETH_SEND_3 0x2c0000 173117632Sharti#define MXGEFW_ETH_RECV_SMALL 0x300000 174117632Sharti#define MXGEFW_ETH_RECV_BIG 0x340000 175117632Sharti#define MXGEFW_ETH_SEND_GO 0x380000 176117632Sharti#define MXGEFW_ETH_SEND_STOP 0x3C0000 177117632Sharti 178117632Sharti#define MXGEFW_ETH_SEND(n) (0x200000 + (((n) & 0x03) * 0x40000)) 179117632Sharti#define MXGEFW_ETH_SEND_OFFSET(n) (MXGEFW_ETH_SEND(n) - MXGEFW_ETH_SEND_4) 180117632Sharti 181117632Shartienum myri10ge_mcp_cmd_type { 182117632Sharti MXGEFW_CMD_NONE = 0, 183117632Sharti /* Reset the mcp, it is left in a safe state, waiting 184117632Sharti for the driver to set all its parameters */ 185117632Sharti MXGEFW_CMD_RESET, 186117632Sharti 187117632Sharti /* get the version number of the current firmware.. 188117632Sharti (may be available in the eeprom strings..? */ 189117632Sharti MXGEFW_GET_MCP_VERSION, 190117632Sharti 191117632Sharti 192117632Sharti /* Parameters which must be set by the driver before it can 193117632Sharti issue MXGEFW_CMD_ETHERNET_UP. They persist until the next 194117632Sharti MXGEFW_CMD_RESET is issued */ 195117632Sharti 196117632Sharti MXGEFW_CMD_SET_INTRQ_DMA, 197117632Sharti /* data0 = LSW of the host address 198117632Sharti * data1 = MSW of the host address 199117632Sharti * data2 = slice number if multiple slices are used 200117632Sharti */ 201117632Sharti 202117632Sharti MXGEFW_CMD_SET_BIG_BUFFER_SIZE, /* in bytes, power of 2 */ 203117632Sharti MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, /* in bytes */ 204117632Sharti 205117632Sharti 206117632Sharti /* Parameters which refer to lanai SRAM addresses where the 207117632Sharti driver must issue PIO writes for various things */ 208117632Sharti 209117632Sharti MXGEFW_CMD_GET_SEND_OFFSET, 210117632Sharti MXGEFW_CMD_GET_SMALL_RX_OFFSET, 211117632Sharti MXGEFW_CMD_GET_BIG_RX_OFFSET, 212117632Sharti /* data0 = slice number if multiple slices are used */ 213117632Sharti 214117632Sharti MXGEFW_CMD_GET_IRQ_ACK_OFFSET, 215117632Sharti MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET, 216117632Sharti 217117632Sharti /* Parameters which refer to rings stored on the MCP, 218117632Sharti and whose size is controlled by the mcp */ 219117632Sharti 220117632Sharti MXGEFW_CMD_GET_SEND_RING_SIZE, /* in bytes */ 221117632Sharti MXGEFW_CMD_GET_RX_RING_SIZE, /* in bytes */ 222117632Sharti 223117632Sharti /* Parameters which refer to rings stored in the host, 224117632Sharti and whose size is controlled by the host. Note that 225117632Sharti all must be physically contiguous and must contain 226117632Sharti a power of 2 number of entries. */ 227117632Sharti 228117632Sharti MXGEFW_CMD_SET_INTRQ_SIZE, /* in bytes */ 229117632Sharti#define MXGEFW_CMD_SET_INTRQ_SIZE_FLAG_NO_STRICT_SIZE_CHECK (1 << 31) 230117632Sharti 231117632Sharti /* command to bring ethernet interface up. Above parameters 232117632Sharti (plus mtu & mac address) must have been exchanged prior 233117632Sharti to issuing this command */ 234117632Sharti MXGEFW_CMD_ETHERNET_UP, 235117632Sharti 236117632Sharti /* command to bring ethernet interface down. No further sends 237117632Sharti or receives may be processed until an MXGEFW_CMD_ETHERNET_UP 238117632Sharti is issued, and all interrupt queues must be flushed prior 239117632Sharti to ack'ing this command */ 240117632Sharti 241117632Sharti MXGEFW_CMD_ETHERNET_DOWN, 242117632Sharti 243117632Sharti /* commands the driver may issue live, without resetting 244117632Sharti the nic. Note that increasing the mtu "live" should 245117632Sharti only be done if the driver has already supplied buffers 246117632Sharti sufficiently large to handle the new mtu. Decreasing 247117632Sharti the mtu live is safe */ 248117632Sharti 249117632Sharti MXGEFW_CMD_SET_MTU, 250117632Sharti MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, /* in microseconds */ 251117632Sharti MXGEFW_CMD_SET_STATS_INTERVAL, /* in microseconds */ 252117632Sharti MXGEFW_CMD_SET_STATS_DMA_OBSOLETE, /* replaced by SET_STATS_DMA_V2 */ 253117632Sharti 254117632Sharti MXGEFW_ENABLE_PROMISC, 255117632Sharti MXGEFW_DISABLE_PROMISC, 256117632Sharti MXGEFW_SET_MAC_ADDRESS, 257117632Sharti 258117632Sharti MXGEFW_ENABLE_FLOW_CONTROL, 259117632Sharti MXGEFW_DISABLE_FLOW_CONTROL, 260117632Sharti 261117632Sharti /* do a DMA test 262117632Sharti data0,data1 = DMA address 263117632Sharti data2 = RDMA length (MSH), WDMA length (LSH) 264117632Sharti command return data = repetitions (MSH), 0.5-ms ticks (LSH) 265117632Sharti */ 266117632Sharti MXGEFW_DMA_TEST, 267117632Sharti 268117632Sharti MXGEFW_ENABLE_ALLMULTI, 269117632Sharti MXGEFW_DISABLE_ALLMULTI, 270117632Sharti 271117632Sharti /* returns MXGEFW_CMD_ERROR_MULTICAST 272117632Sharti if there is no room in the cache 273117632Sharti data0,MSH(data1) = multicast group address */ 274117632Sharti MXGEFW_JOIN_MULTICAST_GROUP, 275117632Sharti /* returns MXGEFW_CMD_ERROR_MULTICAST 276117632Sharti if the address is not in the cache, 277117632Sharti or is equal to FF-FF-FF-FF-FF-FF 278117632Sharti data0,MSH(data1) = multicast group address */ 279117632Sharti MXGEFW_LEAVE_MULTICAST_GROUP, 280117632Sharti MXGEFW_LEAVE_ALL_MULTICAST_GROUPS, 281117632Sharti 282117632Sharti MXGEFW_CMD_SET_STATS_DMA_V2, 283117632Sharti /* data0, data1 = bus addr, 284117632Sharti * data2 = sizeof(struct mcp_irq_data) from driver point of view, allows 285117632Sharti * adding new stuff to mcp_irq_data without changing the ABI 286117632Sharti * 287117632Sharti * If multiple slices are used, data2 contains both the size of the 288117632Sharti * structure (in the lower 16 bits) and the slice number 289117632Sharti * (in the upper 16 bits). 290117632Sharti */ 291117632Sharti 292117632Sharti MXGEFW_CMD_UNALIGNED_TEST, 293117632Sharti /* same than DMA_TEST (same args) but abort with UNALIGNED on unaligned 294117632Sharti chipset */ 295117632Sharti 296117632Sharti MXGEFW_CMD_UNALIGNED_STATUS, 297117632Sharti /* return data = boolean, true if the chipset is known to be unaligned */ 298117632Sharti 299117632Sharti MXGEFW_CMD_ALWAYS_USE_N_BIG_BUFFERS, 300117632Sharti /* data0 = number of big buffers to use. It must be 0 or a power of 2. 301117632Sharti * 0 indicates that the NIC consumes as many buffers as they are required 302117632Sharti * for packet. This is the default behavior. 303117632Sharti * A power of 2 number indicates that the NIC always uses the specified 304117632Sharti * number of buffers for each big receive packet. 305117632Sharti * It is up to the driver to ensure that this value is big enough for 306117632Sharti * the NIC to be able to receive maximum-sized packets. 307117632Sharti */ 308117632Sharti 309117632Sharti MXGEFW_CMD_GET_MAX_RSS_QUEUES, 310117632Sharti MXGEFW_CMD_ENABLE_RSS_QUEUES, 311117632Sharti /* data0 = number of slices n (0, 1, ..., n-1) to enable 312117632Sharti * data1 = interrupt mode | use of multiple transmit queues. 313117632Sharti * 0=share one INTx/MSI. 314117632Sharti * 1=use one MSI-X per queue. 315117632Sharti * If all queues share one interrupt, the driver must have set 316117632Sharti * RSS_SHARED_INTERRUPT_DMA before enabling queues. 317117632Sharti * 2=enable both receive and send queues. 318117632Sharti * Without this bit set, only one send queue (slice 0's send queue) 319117632Sharti * is enabled. The receive queues are always enabled. 320117632Sharti */ 321117632Sharti#define MXGEFW_SLICE_INTR_MODE_SHARED 0x0 322117632Sharti#define MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE 0x1 323117632Sharti#define MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES 0x2 324117632Sharti 325117632Sharti MXGEFW_CMD_GET_RSS_SHARED_INTERRUPT_MASK_OFFSET, 326117632Sharti MXGEFW_CMD_SET_RSS_SHARED_INTERRUPT_DMA, 327117632Sharti /* data0, data1 = bus address lsw, msw */ 328117632Sharti MXGEFW_CMD_GET_RSS_TABLE_OFFSET, 329117632Sharti /* get the offset of the indirection table */ 330117632Sharti MXGEFW_CMD_SET_RSS_TABLE_SIZE, 331117632Sharti /* set the size of the indirection table */ 332117632Sharti MXGEFW_CMD_GET_RSS_KEY_OFFSET, 333117632Sharti /* get the offset of the secret key */ 334117632Sharti MXGEFW_CMD_RSS_KEY_UPDATED, 335117632Sharti /* tell nic that the secret key's been updated */ 336117632Sharti MXGEFW_CMD_SET_RSS_ENABLE, 337117632Sharti /* data0 = enable/disable rss 338117632Sharti * 0: disable rss. nic does not distribute receive packets. 339117632Sharti * 1: enable rss. nic distributes receive packets among queues. 340117632Sharti * data1 = hash type 341117632Sharti * 1: IPV4 (required by RSS) 342117632Sharti * 2: TCP_IPV4 (required by RSS) 343117632Sharti * 3: IPV4 | TCP_IPV4 (required by RSS) 344117632Sharti * 4: source port 345117632Sharti * 5: source port + destination port 346117632Sharti */ 347117632Sharti#define MXGEFW_RSS_HASH_TYPE_IPV4 0x1 348117632Sharti#define MXGEFW_RSS_HASH_TYPE_TCP_IPV4 0x2 349117632Sharti#define MXGEFW_RSS_HASH_TYPE_SRC_PORT 0x4 350117632Sharti#define MXGEFW_RSS_HASH_TYPE_SRC_DST_PORT 0x5 351117632Sharti#define MXGEFW_RSS_HASH_TYPE_MAX 0x5 352117632Sharti 353117632Sharti MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE, 354117632Sharti /* Return data = the max. size of the entire headers of a IPv6 TSO packet. 355117632Sharti * If the header size of a IPv6 TSO packet is larger than the specified 356117632Sharti * value, then the driver must not use TSO. 357117632Sharti * This size restriction only applies to IPv6 TSO. 358117632Sharti * For IPv4 TSO, the maximum size of the headers is fixed, and the NIC 359117632Sharti * always has enough header buffer to store maximum-sized headers. 360117632Sharti */ 361117632Sharti 362117632Sharti MXGEFW_CMD_SET_TSO_MODE, 363117632Sharti /* data0 = TSO mode. 364117632Sharti * 0: Linux/FreeBSD style (NIC default) 365117632Sharti * 1: NDIS/NetBSD style 366117632Sharti */ 367117632Sharti#define MXGEFW_TSO_MODE_LINUX 0 368117632Sharti#define MXGEFW_TSO_MODE_NDIS 1 369117632Sharti 370117632Sharti MXGEFW_CMD_MDIO_READ, 371117632Sharti /* data0 = dev_addr (PMA/PMD or PCS ...), data1 = register/addr */ 372117632Sharti MXGEFW_CMD_MDIO_WRITE, 373117632Sharti /* data0 = dev_addr, data1 = register/addr, data2 = value */ 374117632Sharti 375117632Sharti MXGEFW_CMD_XFP_I2C_READ, 376117632Sharti /* Starts to get a fresh copy of one byte or of the whole xfp i2c table, the 377117632Sharti * obtained data is cached inside the xaui-xfi chip : 378117632Sharti * data0 : "all" flag : 0 => get one byte, 1=> get 256 bytes, 379117632Sharti * data1 : if (data0 == 0): index of byte to refresh [ not used otherwise ] 380117632Sharti * The operation might take ~1ms for a single byte or ~65ms when refreshing all 256 bytes 381117632Sharti * During the i2c operation, MXGEFW_CMD_XFP_I2C_READ or MXGEFW_CMD_XFP_BYTE attempts 382117632Sharti * will return MXGEFW_CMD_ERROR_BUSY 383117632Sharti */ 384117632Sharti MXGEFW_CMD_XFP_BYTE, 385117632Sharti /* Return the last obtained copy of a given byte in the xfp i2c table 386117632Sharti * (copy cached during the last relevant MXGEFW_CMD_XFP_I2C_READ) 387117632Sharti * data0 : index of the desired table entry 388117632Sharti * Return data = the byte stored at the requested index in the table 389117632Sharti */ 390117632Sharti 391117632Sharti MXGEFW_CMD_GET_VPUMP_OFFSET, 392117632Sharti /* Return data = NIC memory offset of mcp_vpump_public_global */ 393117632Sharti MXGEFW_CMD_RESET_VPUMP, 394117632Sharti /* Resets the VPUMP state */ 395117632Sharti 396117632Sharti MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE, 397117632Sharti /* data0 = mcp_slot type to use. 398117632Sharti * 0 = the default 4B mcp_slot 399117632Sharti * 1 = 8B mcp_slot_8 400117632Sharti */ 401117632Sharti#define MXGEFW_RSS_MCP_SLOT_TYPE_MIN 0 402117632Sharti#define MXGEFW_RSS_MCP_SLOT_TYPE_WITH_HASH 1 403117632Sharti 404117632Sharti MXGEFW_CMD_SET_THROTTLE_FACTOR, 405117632Sharti /* set the throttle factor for ethp_z8e 406117632Sharti data0 = throttle_factor 407117632Sharti throttle_factor = 256 * pcie-raw-speed / tx_speed 408117632Sharti tx_speed = 256 * pcie-raw-speed / throttle_factor 409117632Sharti 410117632Sharti For PCI-E x8: pcie-raw-speed == 16Gb/s 411117632Sharti For PCI-E x4: pcie-raw-speed == 8Gb/s 412117632Sharti 413117632Sharti ex1: throttle_factor == 0x1a0 (416), tx_speed == 1.23GB/s == 9.846 Gb/s 414117632Sharti ex2: throttle_factor == 0x200 (512), tx_speed == 1.0GB/s == 8 Gb/s 415117632Sharti 416117632Sharti with tx_boundary == 2048, max-throttle-factor == 8191 => min-speed == 500Mb/s 417117632Sharti with tx_boundary == 4096, max-throttle-factor == 4095 => min-speed == 1Gb/s 418117632Sharti */ 419117632Sharti 420117632Sharti MXGEFW_CMD_VPUMP_UP, 421117632Sharti /* Allocates VPump Connection, Send Request and Zero copy buffer address tables */ 422117632Sharti MXGEFW_CMD_GET_VPUMP_CLK, 423117632Sharti /* Get the lanai clock */ 424117872Sharti 425117632Sharti MXGEFW_CMD_GET_DCA_OFFSET, 426117632Sharti /* offset of dca control for WDMAs */ 427117632Sharti 428117632Sharti /* VMWare NetQueue commands */ 429117632Sharti MXGEFW_CMD_NETQ_GET_FILTERS_PER_QUEUE, 430117632Sharti MXGEFW_CMD_NETQ_ADD_FILTER, 431117632Sharti /* data0 = filter_id << 16 | queue << 8 | type */ 432117632Sharti /* data1 = MS4 of MAC Addr */ 433117632Sharti /* data2 = LS2_MAC << 16 | VLAN_tag */ 434117632Sharti MXGEFW_CMD_NETQ_DEL_FILTER, 435117632Sharti /* data0 = filter_id */ 436117632Sharti MXGEFW_CMD_NETQ_QUERY1, 437117632Sharti MXGEFW_CMD_NETQ_QUERY2, 438117632Sharti MXGEFW_CMD_NETQ_QUERY3, 439117632Sharti MXGEFW_CMD_NETQ_QUERY4, 440117632Sharti 441117632Sharti}; 442117632Shartitypedef enum myri10ge_mcp_cmd_type myri10ge_mcp_cmd_type_t; 443117632Sharti 444117632Sharti 445117632Shartienum myri10ge_mcp_cmd_status { 446117632Sharti MXGEFW_CMD_OK = 0, 447117632Sharti MXGEFW_CMD_UNKNOWN, 448117632Sharti MXGEFW_CMD_ERROR_RANGE, 449117632Sharti MXGEFW_CMD_ERROR_BUSY, 450117632Sharti MXGEFW_CMD_ERROR_EMPTY, 451117632Sharti MXGEFW_CMD_ERROR_CLOSED, 452117632Sharti MXGEFW_CMD_ERROR_HASH_ERROR, 453117632Sharti MXGEFW_CMD_ERROR_BAD_PORT, 454117632Sharti MXGEFW_CMD_ERROR_RESOURCES, 455117632Sharti MXGEFW_CMD_ERROR_MULTICAST, 456117632Sharti MXGEFW_CMD_ERROR_UNALIGNED, 457117632Sharti MXGEFW_CMD_ERROR_NO_MDIO, 458117632Sharti MXGEFW_CMD_ERROR_XFP_FAILURE, 459117632Sharti MXGEFW_CMD_ERROR_XFP_ABSENT, 460117632Sharti MXGEFW_CMD_ERROR_BAD_PCIE_LINK 461117632Sharti}; 462117632Shartitypedef enum myri10ge_mcp_cmd_status myri10ge_mcp_cmd_status_t; 463117632Sharti 464117632Sharti 465117632Sharti#define MXGEFW_OLD_IRQ_DATA_LEN 40 466117632Sharti 467117632Shartistruct mcp_irq_data { 468117632Sharti /* add new counters at the beginning */ 469117632Sharti uint32_t future_use[1]; 470117632Sharti uint32_t dropped_pause; 471117632Sharti uint32_t dropped_unicast_filtered; 472117632Sharti uint32_t dropped_bad_crc32; 473117632Sharti uint32_t dropped_bad_phy; 474117632Sharti uint32_t dropped_multicast_filtered; 475117632Sharti/* 40 Bytes */ 476117632Sharti uint32_t send_done_count; 477117632Sharti 478117632Sharti#define MXGEFW_LINK_DOWN 0 479117632Sharti#define MXGEFW_LINK_UP 1 480117632Sharti#define MXGEFW_LINK_MYRINET 2 481117632Sharti#define MXGEFW_LINK_UNKNOWN 3 482117632Sharti uint32_t link_up; 483117632Sharti uint32_t dropped_link_overflow; 484117632Sharti uint32_t dropped_link_error_or_filtered; 485117632Sharti uint32_t dropped_runt; 486117632Sharti uint32_t dropped_overrun; 487117632Sharti uint32_t dropped_no_small_buffer; 488117632Sharti uint32_t dropped_no_big_buffer; 489117632Sharti uint32_t rdma_tags_available; 490117632Sharti 491117632Sharti uint8_t tx_stopped; 492117632Sharti uint8_t link_down; 493117632Sharti uint8_t stats_updated; 494117632Sharti uint8_t valid; 495117632Sharti}; 496117632Shartitypedef struct mcp_irq_data mcp_irq_data_t; 497117632Sharti 498117632Sharti#ifdef MXGEFW_NDIS 499117632Sharti/* Exclusively used by NDIS drivers */ 500117632Shartistruct mcp_rss_shared_interrupt { 501117632Sharti uint8_t pad[2]; 502117632Sharti uint8_t queue; 503117632Sharti uint8_t valid; 504117632Sharti}; 505117632Sharti#endif 506117632Sharti 507117632Sharti/* definitions for NETQ filter type */ 508117632Sharti#define MXGEFW_NETQ_FILTERTYPE_NONE 0 509117632Sharti#define MXGEFW_NETQ_FILTERTYPE_MACADDR 1 510117632Sharti#define MXGEFW_NETQ_FILTERTYPE_VLAN 2 511117632Sharti#define MXGEFW_NETQ_FILTERTYPE_VLANMACADDR 3 512117632Sharti 513117632Sharti#endif /* _myri10ge_mcp_h */ 514117632Sharti