mxge_mcp.h revision 175365
1155852Sgallatin/******************************************************************************* 2155852Sgallatin 3175365SgallatinCopyright (c) 2006-2008, Myricom Inc. 4155852SgallatinAll rights reserved. 5155852Sgallatin 6155852SgallatinRedistribution and use in source and binary forms, with or without 7155852Sgallatinmodification, are permitted provided that the following conditions are met: 8155852Sgallatin 9155852Sgallatin 1. Redistributions of source code must retain the above copyright notice, 10155852Sgallatin this list of conditions and the following disclaimer. 11155852Sgallatin 12171405Sgallatin 2. Neither the name of the Myricom Inc, nor the names of its 13155852Sgallatin contributors may be used to endorse or promote products derived from 14155852Sgallatin this software without specific prior written permission. 15155852Sgallatin 16155852SgallatinTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17155852SgallatinAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18155852SgallatinIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19155852SgallatinARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 20155852SgallatinLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21155852SgallatinCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22155852SgallatinSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23155852SgallatinINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24155852SgallatinCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25155852SgallatinARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26155852SgallatinPOSSIBILITY OF SUCH DAMAGE. 27155852Sgallatin 28155852Sgallatin$FreeBSD: head/sys/dev/mxge/mxge_mcp.h 175365 2008-01-15 20:34:49Z gallatin $ 29155852Sgallatin***************************************************************************/ 30155852Sgallatin 31159612Sgallatin#ifndef _myri10ge_mcp_h 32159612Sgallatin#define _myri10ge_mcp_h 33155852Sgallatin 34159612Sgallatin#define MXGEFW_VERSION_MAJOR 1 35159612Sgallatin#define MXGEFW_VERSION_MINOR 4 36159612Sgallatin 37159612Sgallatin#ifdef MXGEFW 38155852Sgallatintypedef signed char int8_t; 39155852Sgallatintypedef signed short int16_t; 40155852Sgallatintypedef signed int int32_t; 41155852Sgallatintypedef signed long long int64_t; 42155852Sgallatintypedef unsigned char uint8_t; 43155852Sgallatintypedef unsigned short uint16_t; 44155852Sgallatintypedef unsigned int uint32_t; 45155852Sgallatintypedef unsigned long long uint64_t; 46155852Sgallatin#endif 47155852Sgallatin 48155852Sgallatin/* 8 Bytes */ 49159612Sgallatinstruct mcp_dma_addr { 50155852Sgallatin uint32_t high; 51155852Sgallatin uint32_t low; 52159612Sgallatin}; 53159612Sgallatintypedef struct mcp_dma_addr mcp_dma_addr_t; 54155852Sgallatin 55175365Sgallatin/* 4 Bytes */ 56159612Sgallatinstruct mcp_slot { 57175365Sgallatin uint16_t checksum; 58175365Sgallatin uint16_t length; 59175365Sgallatin}; 60175365Sgallatintypedef struct mcp_slot mcp_slot_t; 61175365Sgallatin 62171917Sgallatin#ifdef MXGEFW_NDIS 63175365Sgallatin/* 8-byte descriptor, exclusively used by NDIS drivers. */ 64175365Sgallatinstruct mcp_slot_8 { 65175365Sgallatin /* Place hash value at the top so it gets written before length. 66171917Sgallatin * The driver polls length. 67171917Sgallatin */ 68171917Sgallatin uint32_t hash; 69159612Sgallatin uint16_t checksum; 70159612Sgallatin uint16_t length; 71159612Sgallatin}; 72175365Sgallatintypedef struct mcp_slot_8 mcp_slot_8_t; 73155852Sgallatin 74171917Sgallatin/* Two bits of length in mcp_slot are used to indicate hash type. */ 75171917Sgallatin#define MXGEFW_RSS_HASH_NULL (0 << 14) /* bit 15:14 = 00 */ 76171917Sgallatin#define MXGEFW_RSS_HASH_IPV4 (1 << 14) /* bit 15:14 = 01 */ 77171917Sgallatin#define MXGEFW_RSS_HASH_TCP_IPV4 (2 << 14) /* bit 15:14 = 10 */ 78171917Sgallatin#define MXGEFW_RSS_HASH_MASK (3 << 14) /* bit 15:14 = 11 */ 79171917Sgallatin#endif 80171917Sgallatin 81155852Sgallatin/* 64 Bytes */ 82159612Sgallatinstruct mcp_cmd { 83155852Sgallatin uint32_t cmd; 84155852Sgallatin uint32_t data0; /* will be low portion if data > 32 bits */ 85155852Sgallatin /* 8 */ 86155852Sgallatin uint32_t data1; /* will be high portion if data > 32 bits */ 87155852Sgallatin uint32_t data2; /* currently unused.. */ 88155852Sgallatin /* 16 */ 89159612Sgallatin struct mcp_dma_addr response_addr; 90155852Sgallatin /* 24 */ 91155852Sgallatin uint8_t pad[40]; 92159612Sgallatin}; 93159612Sgallatintypedef struct mcp_cmd mcp_cmd_t; 94155852Sgallatin 95155852Sgallatin/* 8 Bytes */ 96159612Sgallatinstruct mcp_cmd_response { 97155852Sgallatin uint32_t data; 98155852Sgallatin uint32_t result; 99159612Sgallatin}; 100159612Sgallatintypedef struct mcp_cmd_response mcp_cmd_response_t; 101155852Sgallatin 102155852Sgallatin 103155852Sgallatin 104155852Sgallatin/* 105155852Sgallatin flags used in mcp_kreq_ether_send_t: 106155852Sgallatin 107155852Sgallatin The SMALL flag is only needed in the first segment. It is raised 108155852Sgallatin for packets that are total less or equal 512 bytes. 109155852Sgallatin 110155852Sgallatin The CKSUM flag must be set in all segments. 111155852Sgallatin 112155852Sgallatin The PADDED flags is set if the packet needs to be padded, and it 113155852Sgallatin must be set for all segments. 114155852Sgallatin 115159612Sgallatin The MXGEFW_FLAGS_ALIGN_ODD must be set if the cumulative 116155852Sgallatin length of all previous segments was odd. 117155852Sgallatin*/ 118155852Sgallatin 119155852Sgallatin 120159612Sgallatin#define MXGEFW_FLAGS_SMALL 0x1 121159612Sgallatin#define MXGEFW_FLAGS_TSO_HDR 0x1 122159612Sgallatin#define MXGEFW_FLAGS_FIRST 0x2 123159612Sgallatin#define MXGEFW_FLAGS_ALIGN_ODD 0x4 124159612Sgallatin#define MXGEFW_FLAGS_CKSUM 0x8 125159612Sgallatin#define MXGEFW_FLAGS_TSO_LAST 0x8 126159612Sgallatin#define MXGEFW_FLAGS_NO_TSO 0x10 127159612Sgallatin#define MXGEFW_FLAGS_TSO_CHOP 0x10 128159612Sgallatin#define MXGEFW_FLAGS_TSO_PLD 0x20 129155852Sgallatin 130159612Sgallatin#define MXGEFW_SEND_SMALL_SIZE 1520 131159612Sgallatin#define MXGEFW_MAX_MTU 9400 132155852Sgallatin 133159612Sgallatinunion mcp_pso_or_cumlen { 134155852Sgallatin uint16_t pseudo_hdr_offset; 135155852Sgallatin uint16_t cum_len; 136159612Sgallatin}; 137159612Sgallatintypedef union mcp_pso_or_cumlen mcp_pso_or_cumlen_t; 138155852Sgallatin 139159612Sgallatin#define MXGEFW_MAX_SEND_DESC 12 140159612Sgallatin#define MXGEFW_PAD 2 141155852Sgallatin 142155852Sgallatin/* 16 Bytes */ 143159612Sgallatinstruct mcp_kreq_ether_send { 144155852Sgallatin uint32_t addr_high; 145155852Sgallatin uint32_t addr_low; 146159612Sgallatin uint16_t pseudo_hdr_offset; 147155852Sgallatin uint16_t length; 148159612Sgallatin uint8_t pad; 149159612Sgallatin uint8_t rdma_count; 150155852Sgallatin uint8_t cksum_offset; /* where to start computing cksum */ 151159612Sgallatin uint8_t flags; /* as defined above */ 152159612Sgallatin}; 153159612Sgallatintypedef struct mcp_kreq_ether_send mcp_kreq_ether_send_t; 154155852Sgallatin 155155852Sgallatin/* 8 Bytes */ 156159612Sgallatinstruct mcp_kreq_ether_recv { 157155852Sgallatin uint32_t addr_high; 158155852Sgallatin uint32_t addr_low; 159159612Sgallatin}; 160159612Sgallatintypedef struct mcp_kreq_ether_recv mcp_kreq_ether_recv_t; 161155852Sgallatin 162155852Sgallatin 163155852Sgallatin/* Commands */ 164155852Sgallatin 165162328Sgallatin#define MXGEFW_BOOT_HANDOFF 0xfc0000 166162328Sgallatin#define MXGEFW_BOOT_DUMMY_RDMA 0xfc01c0 167155852Sgallatin 168162328Sgallatin#define MXGEFW_ETH_CMD 0xf80000 169162328Sgallatin#define MXGEFW_ETH_SEND_4 0x200000 170162328Sgallatin#define MXGEFW_ETH_SEND_1 0x240000 171162328Sgallatin#define MXGEFW_ETH_SEND_2 0x280000 172162328Sgallatin#define MXGEFW_ETH_SEND_3 0x2c0000 173162328Sgallatin#define MXGEFW_ETH_RECV_SMALL 0x300000 174162328Sgallatin#define MXGEFW_ETH_RECV_BIG 0x340000 175162328Sgallatin 176162328Sgallatin#define MXGEFW_ETH_SEND(n) (0x200000 + (((n) & 0x03) * 0x40000)) 177162328Sgallatin#define MXGEFW_ETH_SEND_OFFSET(n) (MXGEFW_ETH_SEND(n) - MXGEFW_ETH_SEND_4) 178162328Sgallatin 179159612Sgallatinenum myri10ge_mcp_cmd_type { 180159612Sgallatin MXGEFW_CMD_NONE = 0, 181155852Sgallatin /* Reset the mcp, it is left in a safe state, waiting 182155852Sgallatin for the driver to set all its parameters */ 183159612Sgallatin MXGEFW_CMD_RESET, 184155852Sgallatin 185155852Sgallatin /* get the version number of the current firmware.. 186155852Sgallatin (may be available in the eeprom strings..? */ 187159612Sgallatin MXGEFW_GET_MCP_VERSION, 188155852Sgallatin 189155852Sgallatin 190155852Sgallatin /* Parameters which must be set by the driver before it can 191159612Sgallatin issue MXGEFW_CMD_ETHERNET_UP. They persist until the next 192159612Sgallatin MXGEFW_CMD_RESET is issued */ 193155852Sgallatin 194159612Sgallatin MXGEFW_CMD_SET_INTRQ_DMA, 195159612Sgallatin MXGEFW_CMD_SET_BIG_BUFFER_SIZE, /* in bytes, power of 2 */ 196159612Sgallatin MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, /* in bytes */ 197155852Sgallatin 198155852Sgallatin 199155852Sgallatin /* Parameters which refer to lanai SRAM addresses where the 200155852Sgallatin driver must issue PIO writes for various things */ 201155852Sgallatin 202159612Sgallatin MXGEFW_CMD_GET_SEND_OFFSET, 203159612Sgallatin MXGEFW_CMD_GET_SMALL_RX_OFFSET, 204159612Sgallatin MXGEFW_CMD_GET_BIG_RX_OFFSET, 205159612Sgallatin MXGEFW_CMD_GET_IRQ_ACK_OFFSET, 206159612Sgallatin MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET, 207155852Sgallatin 208155852Sgallatin /* Parameters which refer to rings stored on the MCP, 209155852Sgallatin and whose size is controlled by the mcp */ 210155852Sgallatin 211159612Sgallatin MXGEFW_CMD_GET_SEND_RING_SIZE, /* in bytes */ 212159612Sgallatin MXGEFW_CMD_GET_RX_RING_SIZE, /* in bytes */ 213155852Sgallatin 214155852Sgallatin /* Parameters which refer to rings stored in the host, 215155852Sgallatin and whose size is controlled by the host. Note that 216155852Sgallatin all must be physically contiguous and must contain 217155852Sgallatin a power of 2 number of entries. */ 218155852Sgallatin 219159612Sgallatin MXGEFW_CMD_SET_INTRQ_SIZE, /* in bytes */ 220155852Sgallatin 221155852Sgallatin /* command to bring ethernet interface up. Above parameters 222155852Sgallatin (plus mtu & mac address) must have been exchanged prior 223155852Sgallatin to issuing this command */ 224159612Sgallatin MXGEFW_CMD_ETHERNET_UP, 225155852Sgallatin 226155852Sgallatin /* command to bring ethernet interface down. No further sends 227159612Sgallatin or receives may be processed until an MXGEFW_CMD_ETHERNET_UP 228155852Sgallatin is issued, and all interrupt queues must be flushed prior 229155852Sgallatin to ack'ing this command */ 230155852Sgallatin 231159612Sgallatin MXGEFW_CMD_ETHERNET_DOWN, 232155852Sgallatin 233155852Sgallatin /* commands the driver may issue live, without resetting 234155852Sgallatin the nic. Note that increasing the mtu "live" should 235155852Sgallatin only be done if the driver has already supplied buffers 236155852Sgallatin sufficiently large to handle the new mtu. Decreasing 237155852Sgallatin the mtu live is safe */ 238155852Sgallatin 239159612Sgallatin MXGEFW_CMD_SET_MTU, 240159612Sgallatin MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, /* in microseconds */ 241159612Sgallatin MXGEFW_CMD_SET_STATS_INTERVAL, /* in microseconds */ 242162328Sgallatin MXGEFW_CMD_SET_STATS_DMA_OBSOLETE, /* replaced by SET_STATS_DMA_V2 */ 243155852Sgallatin 244159612Sgallatin MXGEFW_ENABLE_PROMISC, 245159612Sgallatin MXGEFW_DISABLE_PROMISC, 246159612Sgallatin MXGEFW_SET_MAC_ADDRESS, 247155852Sgallatin 248159612Sgallatin MXGEFW_ENABLE_FLOW_CONTROL, 249159612Sgallatin MXGEFW_DISABLE_FLOW_CONTROL, 250155852Sgallatin 251159612Sgallatin /* do a DMA test 252159612Sgallatin data0,data1 = DMA address 253159612Sgallatin data2 = RDMA length (MSH), WDMA length (LSH) 254159612Sgallatin command return data = repetitions (MSH), 0.5-ms ticks (LSH) 255159612Sgallatin */ 256162328Sgallatin MXGEFW_DMA_TEST, 257162328Sgallatin 258162328Sgallatin MXGEFW_ENABLE_ALLMULTI, 259162328Sgallatin MXGEFW_DISABLE_ALLMULTI, 260162328Sgallatin 261162328Sgallatin /* returns MXGEFW_CMD_ERROR_MULTICAST 262162328Sgallatin if there is no room in the cache 263162328Sgallatin data0,MSH(data1) = multicast group address */ 264162328Sgallatin MXGEFW_JOIN_MULTICAST_GROUP, 265162328Sgallatin /* returns MXGEFW_CMD_ERROR_MULTICAST 266162328Sgallatin if the address is not in the cache, 267162328Sgallatin or is equal to FF-FF-FF-FF-FF-FF 268162328Sgallatin data0,MSH(data1) = multicast group address */ 269162328Sgallatin MXGEFW_LEAVE_MULTICAST_GROUP, 270162328Sgallatin MXGEFW_LEAVE_ALL_MULTICAST_GROUPS, 271162328Sgallatin 272162328Sgallatin MXGEFW_CMD_SET_STATS_DMA_V2, 273162328Sgallatin /* data0, data1 = bus addr, 274162328Sgallatin data2 = sizeof(struct mcp_irq_data) from driver point of view, allows 275162328Sgallatin adding new stuff to mcp_irq_data without changing the ABI */ 276169376Sgallatin 277169376Sgallatin MXGEFW_CMD_UNALIGNED_TEST, 278169376Sgallatin /* same than DMA_TEST (same args) but abort with UNALIGNED on unaligned 279169376Sgallatin chipset */ 280169376Sgallatin 281169840Sgallatin MXGEFW_CMD_UNALIGNED_STATUS, 282169376Sgallatin /* return data = boolean, true if the chipset is known to be unaligned */ 283171917Sgallatin 284169840Sgallatin MXGEFW_CMD_ALWAYS_USE_N_BIG_BUFFERS, 285169840Sgallatin /* data0 = number of big buffers to use. It must be 0 or a power of 2. 286169840Sgallatin * 0 indicates that the NIC consumes as many buffers as they are required 287169840Sgallatin * for packet. This is the default behavior. 288169840Sgallatin * A power of 2 number indicates that the NIC always uses the specified 289169840Sgallatin * number of buffers for each big receive packet. 290169840Sgallatin * It is up to the driver to ensure that this value is big enough for 291169840Sgallatin * the NIC to be able to receive maximum-sized packets. 292169840Sgallatin */ 293171917Sgallatin 294171917Sgallatin MXGEFW_CMD_GET_MAX_RSS_QUEUES, 295171917Sgallatin MXGEFW_CMD_ENABLE_RSS_QUEUES, 296171917Sgallatin /* data0 = number of slices n (0, 1, ..., n-1) to enable 297175365Sgallatin * data1 = interrupt mode. 298175365Sgallatin * 0=share one INTx/MSI, 1=use one MSI-X per queue. 299171917Sgallatin * If all queues share one interrupt, the driver must have set 300171917Sgallatin * RSS_SHARED_INTERRUPT_DMA before enabling queues. 301171917Sgallatin */ 302175365Sgallatin#define MXGEFW_SLICE_INTR_MODE_SHARED 0 303175365Sgallatin#define MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE 1 304175365Sgallatin 305171917Sgallatin MXGEFW_CMD_GET_RSS_SHARED_INTERRUPT_MASK_OFFSET, 306171917Sgallatin MXGEFW_CMD_SET_RSS_SHARED_INTERRUPT_DMA, 307171917Sgallatin /* data0, data1 = bus address lsw, msw */ 308171917Sgallatin MXGEFW_CMD_GET_RSS_TABLE_OFFSET, 309171917Sgallatin /* get the offset of the indirection table */ 310171917Sgallatin MXGEFW_CMD_SET_RSS_TABLE_SIZE, 311171917Sgallatin /* set the size of the indirection table */ 312171917Sgallatin MXGEFW_CMD_GET_RSS_KEY_OFFSET, 313171917Sgallatin /* get the offset of the secret key */ 314171917Sgallatin MXGEFW_CMD_RSS_KEY_UPDATED, 315171917Sgallatin /* tell nic that the secret key's been updated */ 316171917Sgallatin MXGEFW_CMD_SET_RSS_ENABLE, 317171917Sgallatin /* data0 = enable/disable rss 318171917Sgallatin * 0: disable rss. nic does not distribute receive packets. 319171917Sgallatin * 1: enable rss. nic distributes receive packets among queues. 320171917Sgallatin * data1 = hash type 321175365Sgallatin * 1: IPV4 (required by RSS) 322175365Sgallatin * 2: TCP_IPV4 (required by RSS) 323175365Sgallatin * 3: IPV4 | TCP_IPV4 (required by RSS) 324175365Sgallatin * 4: source port 325171917Sgallatin */ 326175365Sgallatin#define MXGEFW_RSS_HASH_TYPE_IPV4 0x1 327175365Sgallatin#define MXGEFW_RSS_HASH_TYPE_TCP_IPV4 0x2 328175365Sgallatin#define MXGEFW_RSS_HASH_TYPE_SRC_PORT 0x4 329175365Sgallatin 330171917Sgallatin MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE, 331171917Sgallatin /* Return data = the max. size of the entire headers of a IPv6 TSO packet. 332171917Sgallatin * If the header size of a IPv6 TSO packet is larger than the specified 333171917Sgallatin * value, then the driver must not use TSO. 334171917Sgallatin * This size restriction only applies to IPv6 TSO. 335171917Sgallatin * For IPv4 TSO, the maximum size of the headers is fixed, and the NIC 336171917Sgallatin * always has enough header buffer to store maximum-sized headers. 337171917Sgallatin */ 338171917Sgallatin 339171917Sgallatin MXGEFW_CMD_SET_TSO_MODE, 340171917Sgallatin /* data0 = TSO mode. 341171917Sgallatin * 0: Linux/FreeBSD style (NIC default) 342171917Sgallatin * 1: NDIS/NetBSD style 343171917Sgallatin */ 344175365Sgallatin#define MXGEFW_TSO_MODE_LINUX 0 345175365Sgallatin#define MXGEFW_TSO_MODE_NDIS 1 346171917Sgallatin 347171917Sgallatin MXGEFW_CMD_MDIO_READ, 348171917Sgallatin /* data0 = dev_addr (PMA/PMD or PCS ...), data1 = register/addr */ 349171917Sgallatin MXGEFW_CMD_MDIO_WRITE, 350171917Sgallatin /* data0 = dev_addr, data1 = register/addr, data2 = value */ 351171917Sgallatin 352171917Sgallatin MXGEFW_CMD_XFP_I2C_READ, 353171917Sgallatin /* Starts to get a fresh copy of one byte or of the whole xfp i2c table, the 354171917Sgallatin * obtained data is cached inside the xaui-xfi chip : 355171917Sgallatin * data0 : "all" flag : 0 => get one byte, 1=> get 256 bytes, 356171917Sgallatin * data1 : if (data0 == 0): index of byte to refresh [ not used otherwise ] 357171917Sgallatin * The operation might take ~1ms for a single byte or ~65ms when refreshing all 256 bytes 358171917Sgallatin * During the i2c operation, MXGEFW_CMD_XFP_I2C_READ or MXGEFW_CMD_XFP_BYTE attempts 359171917Sgallatin * will return MXGEFW_CMD_ERROR_BUSY 360171917Sgallatin */ 361175365Sgallatin MXGEFW_CMD_XFP_BYTE, 362171917Sgallatin /* Return the last obtained copy of a given byte in the xfp i2c table 363171917Sgallatin * (copy cached during the last relevant MXGEFW_CMD_XFP_I2C_READ) 364171917Sgallatin * data0 : index of the desired table entry 365171917Sgallatin * Return data = the byte stored at the requested index in the table 366171917Sgallatin */ 367175365Sgallatin 368175365Sgallatin MXGEFW_CMD_GET_VPUMP_OFFSET, 369175365Sgallatin /* Return data = NIC memory offset of mcp_vpump_public_global */ 370175365Sgallatin MXGEFW_CMD_RESET_VPUMP, 371175365Sgallatin /* Resets the VPUMP state */ 372175365Sgallatin 373175365Sgallatin MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE, 374175365Sgallatin /* data0 = mcp_slot type to use. 375175365Sgallatin * 0 = the default 4B mcp_slot 376175365Sgallatin * 1 = 8B mcp_slot_8 377175365Sgallatin */ 378175365Sgallatin#define MXGEFW_RSS_MCP_SLOT_TYPE_MIN 0 379175365Sgallatin#define MXGEFW_RSS_MCP_SLOT_TYPE_WITH_HASH 1 380175365Sgallatin 381175365Sgallatin MXGEFW_CMD_SET_THROTTLE_FACTOR, 382175365Sgallatin /* set the throttle factor for ethp_z8e 383175365Sgallatin data0 = throttle_factor 384175365Sgallatin throttle_factor = 256 * pcie-raw-speed / tx_speed 385175365Sgallatin tx_speed = 256 * pcie-raw-speed / throttle_factor 386175365Sgallatin 387175365Sgallatin For PCI-E x8: pcie-raw-speed == 16Gb/s 388175365Sgallatin For PCI-E x4: pcie-raw-speed == 8Gb/s 389175365Sgallatin 390175365Sgallatin ex1: throttle_factor == 0x1a0 (416), tx_speed == 1.23GB/s == 9.846 Gb/s 391175365Sgallatin ex2: throttle_factor == 0x200 (512), tx_speed == 1.0GB/s == 8 Gb/s 392175365Sgallatin 393175365Sgallatin with tx_boundary == 2048, max-throttle-factor == 8191 => min-speed == 500Mb/s 394175365Sgallatin with tx_boundary == 4096, max-throttle-factor == 4095 => min-speed == 1Gb/s 395175365Sgallatin */ 396175365Sgallatin 397175365Sgallatin MXGEFW_CMD_VPUMP_UP 398175365Sgallatin /* Allocates VPump Connection, Send Request and Zero copy buffer address tables */ 399175365Sgallatin 400159612Sgallatin}; 401159612Sgallatintypedef enum myri10ge_mcp_cmd_type myri10ge_mcp_cmd_type_t; 402155852Sgallatin 403155852Sgallatin 404159612Sgallatinenum myri10ge_mcp_cmd_status { 405159612Sgallatin MXGEFW_CMD_OK = 0, 406159612Sgallatin MXGEFW_CMD_UNKNOWN, 407159612Sgallatin MXGEFW_CMD_ERROR_RANGE, 408159612Sgallatin MXGEFW_CMD_ERROR_BUSY, 409159612Sgallatin MXGEFW_CMD_ERROR_EMPTY, 410159612Sgallatin MXGEFW_CMD_ERROR_CLOSED, 411159612Sgallatin MXGEFW_CMD_ERROR_HASH_ERROR, 412159612Sgallatin MXGEFW_CMD_ERROR_BAD_PORT, 413162328Sgallatin MXGEFW_CMD_ERROR_RESOURCES, 414169376Sgallatin MXGEFW_CMD_ERROR_MULTICAST, 415171917Sgallatin MXGEFW_CMD_ERROR_UNALIGNED, 416171917Sgallatin MXGEFW_CMD_ERROR_NO_MDIO, 417171917Sgallatin MXGEFW_CMD_ERROR_XFP_FAILURE, 418171917Sgallatin MXGEFW_CMD_ERROR_XFP_ABSENT 419159612Sgallatin}; 420159612Sgallatintypedef enum myri10ge_mcp_cmd_status myri10ge_mcp_cmd_status_t; 421155852Sgallatin 422155852Sgallatin 423162328Sgallatin#define MXGEFW_OLD_IRQ_DATA_LEN 40 424162328Sgallatin 425162328Sgallatinstruct mcp_irq_data { 426162328Sgallatin /* add new counters at the beginning */ 427169376Sgallatin uint32_t future_use[1]; 428169376Sgallatin uint32_t dropped_pause; 429169376Sgallatin uint32_t dropped_unicast_filtered; 430169376Sgallatin uint32_t dropped_bad_crc32; 431169376Sgallatin uint32_t dropped_bad_phy; 432162328Sgallatin uint32_t dropped_multicast_filtered; 433159612Sgallatin/* 40 Bytes */ 434159612Sgallatin uint32_t send_done_count; 435159612Sgallatin 436169376Sgallatin#define MXGEFW_LINK_DOWN 0 437169376Sgallatin#define MXGEFW_LINK_UP 1 438169376Sgallatin#define MXGEFW_LINK_MYRINET 2 439169376Sgallatin#define MXGEFW_LINK_UNKNOWN 3 440155852Sgallatin uint32_t link_up; 441155852Sgallatin uint32_t dropped_link_overflow; 442155852Sgallatin uint32_t dropped_link_error_or_filtered; 443155852Sgallatin uint32_t dropped_runt; 444155852Sgallatin uint32_t dropped_overrun; 445155852Sgallatin uint32_t dropped_no_small_buffer; 446155852Sgallatin uint32_t dropped_no_big_buffer; 447155852Sgallatin uint32_t rdma_tags_available; 448155852Sgallatin 449159612Sgallatin uint8_t tx_stopped; 450159612Sgallatin uint8_t link_down; 451159612Sgallatin uint8_t stats_updated; 452159612Sgallatin uint8_t valid; 453159612Sgallatin}; 454159612Sgallatintypedef struct mcp_irq_data mcp_irq_data_t; 455155852Sgallatin 456171917Sgallatin#ifdef MXGEFW_NDIS 457175365Sgallatin/* Exclusively used by NDIS drivers */ 458171917Sgallatinstruct mcp_rss_shared_interrupt { 459171917Sgallatin uint8_t pad[2]; 460171917Sgallatin uint8_t queue; 461171917Sgallatin uint8_t valid; 462171917Sgallatin}; 463171917Sgallatin#endif 464159612Sgallatin 465159612Sgallatin#endif /* _myri10ge_mcp_h */ 466