1155852Sgallatin/******************************************************************************* 2155852Sgallatin 3188736SgallatinCopyright (c) 2006-2009, Myricom Inc. 4155852SgallatinAll rights reserved. 5155852Sgallatin 6155852SgallatinRedistribution and use in source and binary forms, with or without 7155852Sgallatinmodification, are permitted provided that the following conditions are met: 8155852Sgallatin 9155852Sgallatin 1. Redistributions of source code must retain the above copyright notice, 10155852Sgallatin this list of conditions and the following disclaimer. 11155852Sgallatin 12171405Sgallatin 2. Neither the name of the Myricom Inc, nor the names of its 13155852Sgallatin contributors may be used to endorse or promote products derived from 14155852Sgallatin this software without specific prior written permission. 15155852Sgallatin 16155852SgallatinTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17155852SgallatinAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18155852SgallatinIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19155852SgallatinARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 20155852SgallatinLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21155852SgallatinCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22155852SgallatinSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23155852SgallatinINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24155852SgallatinCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25155852SgallatinARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26155852SgallatinPOSSIBILITY OF SUCH DAMAGE. 27155852Sgallatin 28155852Sgallatin$FreeBSD$ 29155852Sgallatin***************************************************************************/ 30155852Sgallatin 31159612Sgallatin#ifndef _myri10ge_mcp_h 32159612Sgallatin#define _myri10ge_mcp_h 33155852Sgallatin 34159612Sgallatin#define MXGEFW_VERSION_MAJOR 1 35159612Sgallatin#define MXGEFW_VERSION_MINOR 4 36159612Sgallatin 37188736Sgallatin#if defined MXGEFW && !defined _stdint_h_ 38155852Sgallatintypedef signed char int8_t; 39155852Sgallatintypedef signed short int16_t; 40155852Sgallatintypedef signed int int32_t; 41155852Sgallatintypedef signed long long int64_t; 42155852Sgallatintypedef unsigned char uint8_t; 43155852Sgallatintypedef unsigned short uint16_t; 44155852Sgallatintypedef unsigned int uint32_t; 45155852Sgallatintypedef unsigned long long uint64_t; 46155852Sgallatin#endif 47155852Sgallatin 48155852Sgallatin/* 8 Bytes */ 49159612Sgallatinstruct mcp_dma_addr { 50155852Sgallatin uint32_t high; 51155852Sgallatin uint32_t low; 52159612Sgallatin}; 53159612Sgallatintypedef struct mcp_dma_addr mcp_dma_addr_t; 54155852Sgallatin 55175365Sgallatin/* 4 Bytes */ 56159612Sgallatinstruct mcp_slot { 57175365Sgallatin uint16_t checksum; 58175365Sgallatin uint16_t length; 59175365Sgallatin}; 60175365Sgallatintypedef struct mcp_slot mcp_slot_t; 61175365Sgallatin 62171917Sgallatin#ifdef MXGEFW_NDIS 63175365Sgallatin/* 8-byte descriptor, exclusively used by NDIS drivers. */ 64175365Sgallatinstruct mcp_slot_8 { 65175365Sgallatin /* Place hash value at the top so it gets written before length. 66171917Sgallatin * The driver polls length. 67171917Sgallatin */ 68171917Sgallatin uint32_t hash; 69159612Sgallatin uint16_t checksum; 70159612Sgallatin uint16_t length; 71159612Sgallatin}; 72175365Sgallatintypedef struct mcp_slot_8 mcp_slot_8_t; 73155852Sgallatin 74171917Sgallatin/* Two bits of length in mcp_slot are used to indicate hash type. */ 75171917Sgallatin#define MXGEFW_RSS_HASH_NULL (0 << 14) /* bit 15:14 = 00 */ 76171917Sgallatin#define MXGEFW_RSS_HASH_IPV4 (1 << 14) /* bit 15:14 = 01 */ 77171917Sgallatin#define MXGEFW_RSS_HASH_TCP_IPV4 (2 << 14) /* bit 15:14 = 10 */ 78171917Sgallatin#define MXGEFW_RSS_HASH_MASK (3 << 14) /* bit 15:14 = 11 */ 79171917Sgallatin#endif 80171917Sgallatin 81155852Sgallatin/* 64 Bytes */ 82159612Sgallatinstruct mcp_cmd { 83155852Sgallatin uint32_t cmd; 84155852Sgallatin uint32_t data0; /* will be low portion if data > 32 bits */ 85155852Sgallatin /* 8 */ 86155852Sgallatin uint32_t data1; /* will be high portion if data > 32 bits */ 87155852Sgallatin uint32_t data2; /* currently unused.. */ 88155852Sgallatin /* 16 */ 89159612Sgallatin struct mcp_dma_addr response_addr; 90155852Sgallatin /* 24 */ 91155852Sgallatin uint8_t pad[40]; 92159612Sgallatin}; 93159612Sgallatintypedef struct mcp_cmd mcp_cmd_t; 94155852Sgallatin 95155852Sgallatin/* 8 Bytes */ 96159612Sgallatinstruct mcp_cmd_response { 97155852Sgallatin uint32_t data; 98155852Sgallatin uint32_t result; 99159612Sgallatin}; 100159612Sgallatintypedef struct mcp_cmd_response mcp_cmd_response_t; 101155852Sgallatin 102155852Sgallatin 103155852Sgallatin 104155852Sgallatin/* 105155852Sgallatin flags used in mcp_kreq_ether_send_t: 106155852Sgallatin 107155852Sgallatin The SMALL flag is only needed in the first segment. It is raised 108155852Sgallatin for packets that are total less or equal 512 bytes. 109155852Sgallatin 110155852Sgallatin The CKSUM flag must be set in all segments. 111155852Sgallatin 112155852Sgallatin The PADDED flags is set if the packet needs to be padded, and it 113155852Sgallatin must be set for all segments. 114155852Sgallatin 115159612Sgallatin The MXGEFW_FLAGS_ALIGN_ODD must be set if the cumulative 116155852Sgallatin length of all previous segments was odd. 117155852Sgallatin*/ 118155852Sgallatin 119155852Sgallatin 120159612Sgallatin#define MXGEFW_FLAGS_SMALL 0x1 121159612Sgallatin#define MXGEFW_FLAGS_TSO_HDR 0x1 122159612Sgallatin#define MXGEFW_FLAGS_FIRST 0x2 123159612Sgallatin#define MXGEFW_FLAGS_ALIGN_ODD 0x4 124159612Sgallatin#define MXGEFW_FLAGS_CKSUM 0x8 125159612Sgallatin#define MXGEFW_FLAGS_TSO_LAST 0x8 126159612Sgallatin#define MXGEFW_FLAGS_NO_TSO 0x10 127159612Sgallatin#define MXGEFW_FLAGS_TSO_CHOP 0x10 128159612Sgallatin#define MXGEFW_FLAGS_TSO_PLD 0x20 129155852Sgallatin 130159612Sgallatin#define MXGEFW_SEND_SMALL_SIZE 1520 131159612Sgallatin#define MXGEFW_MAX_MTU 9400 132155852Sgallatin 133159612Sgallatinunion mcp_pso_or_cumlen { 134155852Sgallatin uint16_t pseudo_hdr_offset; 135155852Sgallatin uint16_t cum_len; 136159612Sgallatin}; 137159612Sgallatintypedef union mcp_pso_or_cumlen mcp_pso_or_cumlen_t; 138155852Sgallatin 139159612Sgallatin#define MXGEFW_MAX_SEND_DESC 12 140159612Sgallatin#define MXGEFW_PAD 2 141155852Sgallatin 142155852Sgallatin/* 16 Bytes */ 143159612Sgallatinstruct mcp_kreq_ether_send { 144155852Sgallatin uint32_t addr_high; 145155852Sgallatin uint32_t addr_low; 146159612Sgallatin uint16_t pseudo_hdr_offset; 147155852Sgallatin uint16_t length; 148159612Sgallatin uint8_t pad; 149159612Sgallatin uint8_t rdma_count; 150155852Sgallatin uint8_t cksum_offset; /* where to start computing cksum */ 151159612Sgallatin uint8_t flags; /* as defined above */ 152159612Sgallatin}; 153159612Sgallatintypedef struct mcp_kreq_ether_send mcp_kreq_ether_send_t; 154155852Sgallatin 155155852Sgallatin/* 8 Bytes */ 156159612Sgallatinstruct mcp_kreq_ether_recv { 157155852Sgallatin uint32_t addr_high; 158155852Sgallatin uint32_t addr_low; 159159612Sgallatin}; 160159612Sgallatintypedef struct mcp_kreq_ether_recv mcp_kreq_ether_recv_t; 161155852Sgallatin 162155852Sgallatin 163155852Sgallatin/* Commands */ 164155852Sgallatin 165162328Sgallatin#define MXGEFW_BOOT_HANDOFF 0xfc0000 166162328Sgallatin#define MXGEFW_BOOT_DUMMY_RDMA 0xfc01c0 167155852Sgallatin 168162328Sgallatin#define MXGEFW_ETH_CMD 0xf80000 169162328Sgallatin#define MXGEFW_ETH_SEND_4 0x200000 170162328Sgallatin#define MXGEFW_ETH_SEND_1 0x240000 171162328Sgallatin#define MXGEFW_ETH_SEND_2 0x280000 172162328Sgallatin#define MXGEFW_ETH_SEND_3 0x2c0000 173162328Sgallatin#define MXGEFW_ETH_RECV_SMALL 0x300000 174162328Sgallatin#define MXGEFW_ETH_RECV_BIG 0x340000 175183515Sgallatin#define MXGEFW_ETH_SEND_GO 0x380000 176183515Sgallatin#define MXGEFW_ETH_SEND_STOP 0x3C0000 177162328Sgallatin 178162328Sgallatin#define MXGEFW_ETH_SEND(n) (0x200000 + (((n) & 0x03) * 0x40000)) 179162328Sgallatin#define MXGEFW_ETH_SEND_OFFSET(n) (MXGEFW_ETH_SEND(n) - MXGEFW_ETH_SEND_4) 180162328Sgallatin 181159612Sgallatinenum myri10ge_mcp_cmd_type { 182159612Sgallatin MXGEFW_CMD_NONE = 0, 183155852Sgallatin /* Reset the mcp, it is left in a safe state, waiting 184155852Sgallatin for the driver to set all its parameters */ 185188736Sgallatin MXGEFW_CMD_RESET = 1, 186155852Sgallatin 187155852Sgallatin /* get the version number of the current firmware.. 188155852Sgallatin (may be available in the eeprom strings..? */ 189188736Sgallatin MXGEFW_GET_MCP_VERSION = 2, 190155852Sgallatin 191155852Sgallatin 192155852Sgallatin /* Parameters which must be set by the driver before it can 193159612Sgallatin issue MXGEFW_CMD_ETHERNET_UP. They persist until the next 194159612Sgallatin MXGEFW_CMD_RESET is issued */ 195155852Sgallatin 196188736Sgallatin MXGEFW_CMD_SET_INTRQ_DMA = 3, 197183515Sgallatin /* data0 = LSW of the host address 198183515Sgallatin * data1 = MSW of the host address 199183515Sgallatin * data2 = slice number if multiple slices are used 200183515Sgallatin */ 201183515Sgallatin 202188736Sgallatin MXGEFW_CMD_SET_BIG_BUFFER_SIZE = 4, /* in bytes, power of 2 */ 203188736Sgallatin MXGEFW_CMD_SET_SMALL_BUFFER_SIZE = 5, /* in bytes */ 204155852Sgallatin 205155852Sgallatin 206155852Sgallatin /* Parameters which refer to lanai SRAM addresses where the 207155852Sgallatin driver must issue PIO writes for various things */ 208155852Sgallatin 209188736Sgallatin MXGEFW_CMD_GET_SEND_OFFSET = 6, 210188736Sgallatin MXGEFW_CMD_GET_SMALL_RX_OFFSET = 7, 211188736Sgallatin MXGEFW_CMD_GET_BIG_RX_OFFSET = 8, 212183515Sgallatin /* data0 = slice number if multiple slices are used */ 213183515Sgallatin 214188736Sgallatin MXGEFW_CMD_GET_IRQ_ACK_OFFSET = 9, 215188736Sgallatin MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET = 10, 216155852Sgallatin 217155852Sgallatin /* Parameters which refer to rings stored on the MCP, 218155852Sgallatin and whose size is controlled by the mcp */ 219155852Sgallatin 220188736Sgallatin MXGEFW_CMD_GET_SEND_RING_SIZE = 11, /* in bytes */ 221188736Sgallatin MXGEFW_CMD_GET_RX_RING_SIZE = 12, /* in bytes */ 222155852Sgallatin 223155852Sgallatin /* Parameters which refer to rings stored in the host, 224155852Sgallatin and whose size is controlled by the host. Note that 225155852Sgallatin all must be physically contiguous and must contain 226155852Sgallatin a power of 2 number of entries. */ 227155852Sgallatin 228188736Sgallatin MXGEFW_CMD_SET_INTRQ_SIZE = 13, /* in bytes */ 229258780Seadler#define MXGEFW_CMD_SET_INTRQ_SIZE_FLAG_NO_STRICT_SIZE_CHECK (1U << 31) 230155852Sgallatin 231155852Sgallatin /* command to bring ethernet interface up. Above parameters 232155852Sgallatin (plus mtu & mac address) must have been exchanged prior 233155852Sgallatin to issuing this command */ 234188736Sgallatin MXGEFW_CMD_ETHERNET_UP = 14, 235155852Sgallatin 236155852Sgallatin /* command to bring ethernet interface down. No further sends 237159612Sgallatin or receives may be processed until an MXGEFW_CMD_ETHERNET_UP 238155852Sgallatin is issued, and all interrupt queues must be flushed prior 239155852Sgallatin to ack'ing this command */ 240155852Sgallatin 241188736Sgallatin MXGEFW_CMD_ETHERNET_DOWN = 15, 242155852Sgallatin 243155852Sgallatin /* commands the driver may issue live, without resetting 244155852Sgallatin the nic. Note that increasing the mtu "live" should 245155852Sgallatin only be done if the driver has already supplied buffers 246155852Sgallatin sufficiently large to handle the new mtu. Decreasing 247155852Sgallatin the mtu live is safe */ 248155852Sgallatin 249188736Sgallatin MXGEFW_CMD_SET_MTU = 16, 250188736Sgallatin MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET = 17, /* in microseconds */ 251188736Sgallatin MXGEFW_CMD_SET_STATS_INTERVAL = 18, /* in microseconds */ 252188736Sgallatin MXGEFW_CMD_SET_STATS_DMA_OBSOLETE = 19, /* replaced by SET_STATS_DMA_V2 */ 253155852Sgallatin 254188736Sgallatin MXGEFW_ENABLE_PROMISC = 20, 255188736Sgallatin MXGEFW_DISABLE_PROMISC = 21, 256188736Sgallatin MXGEFW_SET_MAC_ADDRESS = 22, 257155852Sgallatin 258188736Sgallatin MXGEFW_ENABLE_FLOW_CONTROL = 23, 259188736Sgallatin MXGEFW_DISABLE_FLOW_CONTROL = 24, 260155852Sgallatin 261159612Sgallatin /* do a DMA test 262159612Sgallatin data0,data1 = DMA address 263159612Sgallatin data2 = RDMA length (MSH), WDMA length (LSH) 264159612Sgallatin command return data = repetitions (MSH), 0.5-ms ticks (LSH) 265159612Sgallatin */ 266188736Sgallatin MXGEFW_DMA_TEST = 25, 267162328Sgallatin 268188736Sgallatin MXGEFW_ENABLE_ALLMULTI = 26, 269188736Sgallatin MXGEFW_DISABLE_ALLMULTI = 27, 270162328Sgallatin 271162328Sgallatin /* returns MXGEFW_CMD_ERROR_MULTICAST 272162328Sgallatin if there is no room in the cache 273162328Sgallatin data0,MSH(data1) = multicast group address */ 274188736Sgallatin MXGEFW_JOIN_MULTICAST_GROUP = 28, 275162328Sgallatin /* returns MXGEFW_CMD_ERROR_MULTICAST 276162328Sgallatin if the address is not in the cache, 277162328Sgallatin or is equal to FF-FF-FF-FF-FF-FF 278162328Sgallatin data0,MSH(data1) = multicast group address */ 279188736Sgallatin MXGEFW_LEAVE_MULTICAST_GROUP = 29, 280188736Sgallatin MXGEFW_LEAVE_ALL_MULTICAST_GROUPS = 30, 281162328Sgallatin 282188736Sgallatin MXGEFW_CMD_SET_STATS_DMA_V2 = 31, 283162328Sgallatin /* data0, data1 = bus addr, 284183515Sgallatin * data2 = sizeof(struct mcp_irq_data) from driver point of view, allows 285183515Sgallatin * adding new stuff to mcp_irq_data without changing the ABI 286183515Sgallatin * 287183515Sgallatin * If multiple slices are used, data2 contains both the size of the 288183515Sgallatin * structure (in the lower 16 bits) and the slice number 289183515Sgallatin * (in the upper 16 bits). 290183515Sgallatin */ 291169376Sgallatin 292188736Sgallatin MXGEFW_CMD_UNALIGNED_TEST = 32, 293169376Sgallatin /* same than DMA_TEST (same args) but abort with UNALIGNED on unaligned 294169376Sgallatin chipset */ 295169376Sgallatin 296188736Sgallatin MXGEFW_CMD_UNALIGNED_STATUS = 33, 297169376Sgallatin /* return data = boolean, true if the chipset is known to be unaligned */ 298171917Sgallatin 299188736Sgallatin MXGEFW_CMD_ALWAYS_USE_N_BIG_BUFFERS = 34, 300169840Sgallatin /* data0 = number of big buffers to use. It must be 0 or a power of 2. 301169840Sgallatin * 0 indicates that the NIC consumes as many buffers as they are required 302169840Sgallatin * for packet. This is the default behavior. 303169840Sgallatin * A power of 2 number indicates that the NIC always uses the specified 304169840Sgallatin * number of buffers for each big receive packet. 305169840Sgallatin * It is up to the driver to ensure that this value is big enough for 306169840Sgallatin * the NIC to be able to receive maximum-sized packets. 307169840Sgallatin */ 308171917Sgallatin 309188736Sgallatin MXGEFW_CMD_GET_MAX_RSS_QUEUES = 35, 310188736Sgallatin MXGEFW_CMD_ENABLE_RSS_QUEUES = 36, 311171917Sgallatin /* data0 = number of slices n (0, 1, ..., n-1) to enable 312183515Sgallatin * data1 = interrupt mode | use of multiple transmit queues. 313183515Sgallatin * 0=share one INTx/MSI. 314183515Sgallatin * 1=use one MSI-X per queue. 315171917Sgallatin * If all queues share one interrupt, the driver must have set 316171917Sgallatin * RSS_SHARED_INTERRUPT_DMA before enabling queues. 317183515Sgallatin * 2=enable both receive and send queues. 318183515Sgallatin * Without this bit set, only one send queue (slice 0's send queue) 319183515Sgallatin * is enabled. The receive queues are always enabled. 320171917Sgallatin */ 321183515Sgallatin#define MXGEFW_SLICE_INTR_MODE_SHARED 0x0 322183515Sgallatin#define MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE 0x1 323183515Sgallatin#define MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES 0x2 324175365Sgallatin 325188736Sgallatin MXGEFW_CMD_GET_RSS_SHARED_INTERRUPT_MASK_OFFSET = 37, 326188736Sgallatin MXGEFW_CMD_SET_RSS_SHARED_INTERRUPT_DMA = 38, 327171917Sgallatin /* data0, data1 = bus address lsw, msw */ 328188736Sgallatin MXGEFW_CMD_GET_RSS_TABLE_OFFSET = 39, 329171917Sgallatin /* get the offset of the indirection table */ 330188736Sgallatin MXGEFW_CMD_SET_RSS_TABLE_SIZE = 40, 331171917Sgallatin /* set the size of the indirection table */ 332188736Sgallatin MXGEFW_CMD_GET_RSS_KEY_OFFSET = 41, 333171917Sgallatin /* get the offset of the secret key */ 334188736Sgallatin MXGEFW_CMD_RSS_KEY_UPDATED = 42, 335171917Sgallatin /* tell nic that the secret key's been updated */ 336188736Sgallatin MXGEFW_CMD_SET_RSS_ENABLE = 43, 337171917Sgallatin /* data0 = enable/disable rss 338171917Sgallatin * 0: disable rss. nic does not distribute receive packets. 339171917Sgallatin * 1: enable rss. nic distributes receive packets among queues. 340171917Sgallatin * data1 = hash type 341175365Sgallatin * 1: IPV4 (required by RSS) 342175365Sgallatin * 2: TCP_IPV4 (required by RSS) 343175365Sgallatin * 3: IPV4 | TCP_IPV4 (required by RSS) 344175365Sgallatin * 4: source port 345183515Sgallatin * 5: source port + destination port 346171917Sgallatin */ 347175365Sgallatin#define MXGEFW_RSS_HASH_TYPE_IPV4 0x1 348175365Sgallatin#define MXGEFW_RSS_HASH_TYPE_TCP_IPV4 0x2 349175365Sgallatin#define MXGEFW_RSS_HASH_TYPE_SRC_PORT 0x4 350183515Sgallatin#define MXGEFW_RSS_HASH_TYPE_SRC_DST_PORT 0x5 351183515Sgallatin#define MXGEFW_RSS_HASH_TYPE_MAX 0x5 352175365Sgallatin 353188736Sgallatin MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE = 44, 354171917Sgallatin /* Return data = the max. size of the entire headers of a IPv6 TSO packet. 355171917Sgallatin * If the header size of a IPv6 TSO packet is larger than the specified 356171917Sgallatin * value, then the driver must not use TSO. 357171917Sgallatin * This size restriction only applies to IPv6 TSO. 358171917Sgallatin * For IPv4 TSO, the maximum size of the headers is fixed, and the NIC 359171917Sgallatin * always has enough header buffer to store maximum-sized headers. 360171917Sgallatin */ 361171917Sgallatin 362188736Sgallatin MXGEFW_CMD_SET_TSO_MODE = 45, 363171917Sgallatin /* data0 = TSO mode. 364171917Sgallatin * 0: Linux/FreeBSD style (NIC default) 365171917Sgallatin * 1: NDIS/NetBSD style 366171917Sgallatin */ 367175365Sgallatin#define MXGEFW_TSO_MODE_LINUX 0 368175365Sgallatin#define MXGEFW_TSO_MODE_NDIS 1 369171917Sgallatin 370188736Sgallatin MXGEFW_CMD_MDIO_READ = 46, 371171917Sgallatin /* data0 = dev_addr (PMA/PMD or PCS ...), data1 = register/addr */ 372188736Sgallatin MXGEFW_CMD_MDIO_WRITE = 47, 373171917Sgallatin /* data0 = dev_addr, data1 = register/addr, data2 = value */ 374171917Sgallatin 375188736Sgallatin MXGEFW_CMD_I2C_READ = 48, 376188736Sgallatin /* Starts to get a fresh copy of one byte or of the module i2c table, the 377171917Sgallatin * obtained data is cached inside the xaui-xfi chip : 378188736Sgallatin * data0 : 0 => get one byte, 1=> get 256 bytes 379188736Sgallatin * data1 : If data0 == 0: location to refresh 380188736Sgallatin * bit 7:0 register location 381188736Sgallatin * bit 8:15 is the i2c slave addr (0 is interpreted as 0xA1) 382188736Sgallatin * bit 23:16 is the i2c bus number (for multi-port NICs) 383188736Sgallatin * If data0 == 1: unused 384171917Sgallatin * The operation might take ~1ms for a single byte or ~65ms when refreshing all 256 bytes 385188736Sgallatin * During the i2c operation, MXGEFW_CMD_I2C_READ or MXGEFW_CMD_I2C_BYTE attempts 386171917Sgallatin * will return MXGEFW_CMD_ERROR_BUSY 387171917Sgallatin */ 388188736Sgallatin MXGEFW_CMD_I2C_BYTE = 49, 389171917Sgallatin /* Return the last obtained copy of a given byte in the xfp i2c table 390188736Sgallatin * (copy cached during the last relevant MXGEFW_CMD_I2C_READ) 391171917Sgallatin * data0 : index of the desired table entry 392171917Sgallatin * Return data = the byte stored at the requested index in the table 393171917Sgallatin */ 394175365Sgallatin 395188736Sgallatin MXGEFW_CMD_GET_VPUMP_OFFSET = 50, 396175365Sgallatin /* Return data = NIC memory offset of mcp_vpump_public_global */ 397188736Sgallatin MXGEFW_CMD_RESET_VPUMP = 51, 398175365Sgallatin /* Resets the VPUMP state */ 399175365Sgallatin 400188736Sgallatin MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE = 52, 401175365Sgallatin /* data0 = mcp_slot type to use. 402175365Sgallatin * 0 = the default 4B mcp_slot 403175365Sgallatin * 1 = 8B mcp_slot_8 404175365Sgallatin */ 405175365Sgallatin#define MXGEFW_RSS_MCP_SLOT_TYPE_MIN 0 406175365Sgallatin#define MXGEFW_RSS_MCP_SLOT_TYPE_WITH_HASH 1 407175365Sgallatin 408188736Sgallatin MXGEFW_CMD_SET_THROTTLE_FACTOR = 53, 409175365Sgallatin /* set the throttle factor for ethp_z8e 410175365Sgallatin data0 = throttle_factor 411175365Sgallatin throttle_factor = 256 * pcie-raw-speed / tx_speed 412175365Sgallatin tx_speed = 256 * pcie-raw-speed / throttle_factor 413175365Sgallatin 414175365Sgallatin For PCI-E x8: pcie-raw-speed == 16Gb/s 415175365Sgallatin For PCI-E x4: pcie-raw-speed == 8Gb/s 416175365Sgallatin 417175365Sgallatin ex1: throttle_factor == 0x1a0 (416), tx_speed == 1.23GB/s == 9.846 Gb/s 418175365Sgallatin ex2: throttle_factor == 0x200 (512), tx_speed == 1.0GB/s == 8 Gb/s 419175365Sgallatin 420175365Sgallatin with tx_boundary == 2048, max-throttle-factor == 8191 => min-speed == 500Mb/s 421175365Sgallatin with tx_boundary == 4096, max-throttle-factor == 4095 => min-speed == 1Gb/s 422175365Sgallatin */ 423183515Sgallatin 424188736Sgallatin MXGEFW_CMD_VPUMP_UP = 54, 425175365Sgallatin /* Allocates VPump Connection, Send Request and Zero copy buffer address tables */ 426188736Sgallatin MXGEFW_CMD_GET_VPUMP_CLK = 55, 427183515Sgallatin /* Get the lanai clock */ 428175365Sgallatin 429188736Sgallatin MXGEFW_CMD_GET_DCA_OFFSET = 56, 430183515Sgallatin /* offset of dca control for WDMAs */ 431183515Sgallatin 432183515Sgallatin /* VMWare NetQueue commands */ 433188736Sgallatin MXGEFW_CMD_NETQ_GET_FILTERS_PER_QUEUE = 57, 434188736Sgallatin MXGEFW_CMD_NETQ_ADD_FILTER = 58, 435183515Sgallatin /* data0 = filter_id << 16 | queue << 8 | type */ 436183515Sgallatin /* data1 = MS4 of MAC Addr */ 437183515Sgallatin /* data2 = LS2_MAC << 16 | VLAN_tag */ 438188736Sgallatin MXGEFW_CMD_NETQ_DEL_FILTER = 59, 439183515Sgallatin /* data0 = filter_id */ 440188736Sgallatin MXGEFW_CMD_NETQ_QUERY1 = 60, 441188736Sgallatin MXGEFW_CMD_NETQ_QUERY2 = 61, 442188736Sgallatin MXGEFW_CMD_NETQ_QUERY3 = 62, 443188736Sgallatin MXGEFW_CMD_NETQ_QUERY4 = 63, 444183515Sgallatin 445188736Sgallatin MXGEFW_CMD_RELAX_RXBUFFER_ALIGNMENT = 64, 446188736Sgallatin /* When set, small receive buffers can cross page boundaries. 447188736Sgallatin * Both small and big receive buffers may start at any address. 448188736Sgallatin * This option has performance implications, so use with caution. 449188736Sgallatin */ 450159612Sgallatin}; 451159612Sgallatintypedef enum myri10ge_mcp_cmd_type myri10ge_mcp_cmd_type_t; 452155852Sgallatin 453155852Sgallatin 454159612Sgallatinenum myri10ge_mcp_cmd_status { 455159612Sgallatin MXGEFW_CMD_OK = 0, 456188736Sgallatin MXGEFW_CMD_UNKNOWN = 1, 457188736Sgallatin MXGEFW_CMD_ERROR_RANGE = 2, 458188736Sgallatin MXGEFW_CMD_ERROR_BUSY = 3, 459188736Sgallatin MXGEFW_CMD_ERROR_EMPTY = 4, 460188736Sgallatin MXGEFW_CMD_ERROR_CLOSED = 5, 461188736Sgallatin MXGEFW_CMD_ERROR_HASH_ERROR = 6, 462188736Sgallatin MXGEFW_CMD_ERROR_BAD_PORT = 7, 463188736Sgallatin MXGEFW_CMD_ERROR_RESOURCES = 8, 464188736Sgallatin MXGEFW_CMD_ERROR_MULTICAST = 9, 465188736Sgallatin MXGEFW_CMD_ERROR_UNALIGNED = 10, 466188736Sgallatin MXGEFW_CMD_ERROR_NO_MDIO = 11, 467188736Sgallatin MXGEFW_CMD_ERROR_I2C_FAILURE = 12, 468188736Sgallatin MXGEFW_CMD_ERROR_I2C_ABSENT = 13, 469188736Sgallatin MXGEFW_CMD_ERROR_BAD_PCIE_LINK = 14 470159612Sgallatin}; 471159612Sgallatintypedef enum myri10ge_mcp_cmd_status myri10ge_mcp_cmd_status_t; 472155852Sgallatin 473155852Sgallatin 474162328Sgallatin#define MXGEFW_OLD_IRQ_DATA_LEN 40 475162328Sgallatin 476162328Sgallatinstruct mcp_irq_data { 477162328Sgallatin /* add new counters at the beginning */ 478169376Sgallatin uint32_t future_use[1]; 479169376Sgallatin uint32_t dropped_pause; 480169376Sgallatin uint32_t dropped_unicast_filtered; 481169376Sgallatin uint32_t dropped_bad_crc32; 482169376Sgallatin uint32_t dropped_bad_phy; 483162328Sgallatin uint32_t dropped_multicast_filtered; 484159612Sgallatin/* 40 Bytes */ 485159612Sgallatin uint32_t send_done_count; 486159612Sgallatin 487169376Sgallatin#define MXGEFW_LINK_DOWN 0 488169376Sgallatin#define MXGEFW_LINK_UP 1 489169376Sgallatin#define MXGEFW_LINK_MYRINET 2 490169376Sgallatin#define MXGEFW_LINK_UNKNOWN 3 491155852Sgallatin uint32_t link_up; 492155852Sgallatin uint32_t dropped_link_overflow; 493155852Sgallatin uint32_t dropped_link_error_or_filtered; 494155852Sgallatin uint32_t dropped_runt; 495155852Sgallatin uint32_t dropped_overrun; 496155852Sgallatin uint32_t dropped_no_small_buffer; 497155852Sgallatin uint32_t dropped_no_big_buffer; 498155852Sgallatin uint32_t rdma_tags_available; 499155852Sgallatin 500159612Sgallatin uint8_t tx_stopped; 501159612Sgallatin uint8_t link_down; 502159612Sgallatin uint8_t stats_updated; 503159612Sgallatin uint8_t valid; 504159612Sgallatin}; 505159612Sgallatintypedef struct mcp_irq_data mcp_irq_data_t; 506155852Sgallatin 507171917Sgallatin#ifdef MXGEFW_NDIS 508175365Sgallatin/* Exclusively used by NDIS drivers */ 509171917Sgallatinstruct mcp_rss_shared_interrupt { 510171917Sgallatin uint8_t pad[2]; 511171917Sgallatin uint8_t queue; 512171917Sgallatin uint8_t valid; 513171917Sgallatin}; 514171917Sgallatin#endif 515159612Sgallatin 516183515Sgallatin/* definitions for NETQ filter type */ 517183515Sgallatin#define MXGEFW_NETQ_FILTERTYPE_NONE 0 518183515Sgallatin#define MXGEFW_NETQ_FILTERTYPE_MACADDR 1 519183515Sgallatin#define MXGEFW_NETQ_FILTERTYPE_VLAN 2 520183515Sgallatin#define MXGEFW_NETQ_FILTERTYPE_VLANMACADDR 3 521183515Sgallatin 522159612Sgallatin#endif /* _myri10ge_mcp_h */ 523