1/*- 2 * Copyright (c) 2007-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2007-2009 Marvell Semiconductor, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer, 11 * without modification. 12 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 13 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 14 * redistribution must be conditioned upon including a substantially 15 * similar Disclaimer requirement for further binary redistribution. 16 * 17 * NO WARRANTY 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 21 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 22 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 23 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 26 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 28 * THE POSSIBILITY OF SUCH DAMAGES. 29 * 30 * $FreeBSD$ 31 */ 32 33/* 34 * Definitions for the Marvell Wireless LAN controller Hardware Access Layer. 35 */ 36#ifndef _MWL_HALREG_H_ 37#define _MWL_HALREG_H_ 38 39#define MWL_ANT_INFO_SUPPORT /* per-antenna data in rx descriptor */ 40 41#define MACREG_REG_TSF_LOW 0xa600 /* TSF lo */ 42#define MACREG_REG_TSF_HIGH 0xa604 /* TSF hi */ 43#define MACREG_REG_CHIP_REV 0xa814 /* chip rev */ 44 45// Map to 0x80000000 (Bus control) on BAR0 46#define MACREG_REG_H2A_INTERRUPT_EVENTS 0x00000C18 // (From host to ARM) 47#define MACREG_REG_H2A_INTERRUPT_CAUSE 0x00000C1C // (From host to ARM) 48#define MACREG_REG_H2A_INTERRUPT_MASK 0x00000C20 // (From host to ARM) 49#define MACREG_REG_H2A_INTERRUPT_CLEAR_SEL 0x00000C24 // (From host to ARM) 50#define MACREG_REG_H2A_INTERRUPT_STATUS_MASK 0x00000C28 // (From host to ARM) 51 52#define MACREG_REG_A2H_INTERRUPT_EVENTS 0x00000C2C // (From ARM to host) 53#define MACREG_REG_A2H_INTERRUPT_CAUSE 0x00000C30 // (From ARM to host) 54#define MACREG_REG_A2H_INTERRUPT_MASK 0x00000C34 // (From ARM to host) 55#define MACREG_REG_A2H_INTERRUPT_CLEAR_SEL 0x00000C38 // (From ARM to host) 56#define MACREG_REG_A2H_INTERRUPT_STATUS_MASK 0x00000C3C // (From ARM to host) 57 58 59// Map to 0x80000000 on BAR1 60#define MACREG_REG_GEN_PTR 0x00000C10 61#define MACREG_REG_INT_CODE 0x00000C14 62#define MACREG_REG_SCRATCH 0x00000C40 63#define MACREG_REG_FW_PRESENT 0x0000BFFC 64 65#define MACREG_REG_PROMISCUOUS 0xA300 66 67// Bit definitio for MACREG_REG_A2H_INTERRUPT_CAUSE (A2HRIC) 68#define MACREG_A2HRIC_BIT_TX_DONE 0x00000001 // bit 0 69#define MACREG_A2HRIC_BIT_RX_RDY 0x00000002 // bit 1 70#define MACREG_A2HRIC_BIT_OPC_DONE 0x00000004 // bit 2 71#define MACREG_A2HRIC_BIT_MAC_EVENT 0x00000008 // bit 3 72#define MACREG_A2HRIC_BIT_RX_PROBLEM 0x00000010 // bit 4 73 74#define MACREG_A2HRIC_BIT_RADIO_OFF 0x00000020 // bit 5 75#define MACREG_A2HRIC_BIT_RADIO_ON 0x00000040 // bit 6 76 77#define MACREG_A2HRIC_BIT_RADAR_DETECT 0x00000080 // bit 7 78 79#define MACREG_A2HRIC_BIT_ICV_ERROR 0x00000100 // bit 8 80#define MACREG_A2HRIC_BIT_MIC_ERROR 0x00000200 // bit 9 81#define MACREG_A2HRIC_BIT_QUEUE_EMPTY 0x00004000 82#define MACREG_A2HRIC_BIT_QUEUE_FULL 0x00000800 83#define MACREG_A2HRIC_BIT_CHAN_SWITCH 0x00001000 84#define MACREG_A2HRIC_BIT_TX_WATCHDOG 0x00002000 85#define MACREG_A2HRIC_BIT_BA_WATCHDOG 0x00000400 86#define MACREQ_A2HRIC_BIT_TX_ACK 0x00008000 87#define ISR_SRC_BITS ((MACREG_A2HRIC_BIT_RX_RDY) | \ 88 (MACREG_A2HRIC_BIT_TX_DONE) | \ 89 (MACREG_A2HRIC_BIT_OPC_DONE) | \ 90 (MACREG_A2HRIC_BIT_MAC_EVENT)| \ 91 (MACREG_A2HRIC_BIT_MIC_ERROR)| \ 92 (MACREG_A2HRIC_BIT_ICV_ERROR)| \ 93 (MACREG_A2HRIC_BIT_RADAR_DETECT)| \ 94 (MACREG_A2HRIC_BIT_CHAN_SWITCH)| \ 95 (MACREG_A2HRIC_BIT_TX_WATCHDOG)| \ 96 (MACREG_A2HRIC_BIT_QUEUE_EMPTY)| \ 97 (MACREG_A2HRIC_BIT_BA_WATCHDOG)| \ 98 (MACREQ_A2HRIC_BIT_TX_ACK)) 99 100#define MACREG_A2HRIC_BIT_MASK ISR_SRC_BITS 101 102 103// Bit definitio for MACREG_REG_H2A_INTERRUPT_CAUSE (H2ARIC) 104#define MACREG_H2ARIC_BIT_PPA_READY 0x00000001 // bit 0 105#define MACREG_H2ARIC_BIT_DOOR_BELL 0x00000002 // bit 1 106#define ISR_RESET (1<<15) 107 108// INT code register event definition 109#define MACREG_INT_CODE_CMD_FINISHED 0x00000005 110 111/* 112 * Host/Firmware Interface definitions. 113 */ 114 115/** 116 * Define total number of TX queues in the shared memory. 117 * This count includes the EDCA queues, Block Ack queues, and HCCA queues 118 * In addition to this, there could be a management packet queue some 119 * time in the future 120 */ 121#define NUM_EDCA_QUEUES 4 122#define NUM_HCCA_QUEUES 0 123#define NUM_BA_QUEUES 0 124#define NUM_MGMT_QUEUES 0 125#define NUM_ACK_EVENT_QUEUE 1 126#define TOTAL_TX_QUEUES \ 127 (NUM_EDCA_QUEUES + NUM_HCCA_QUEUES + NUM_BA_QUEUES + NUM_MGMT_QUEUES + NUM_ACK_EVENT_QUEUE) 128#define MAX_TXWCB_QUEUES TOTAL_TX_QUEUES - NUM_ACK_EVENT_QUEUE 129#define MAX_RXWCB_QUEUES 1 130 131//============================================================================= 132// PUBLIC DEFINITIONS 133//============================================================================= 134 135#define RATE_INDEX_MAX_ARRAY 14 136#define WOW_MAX_STATION 32 137 138/* 139 * Hardware tx/rx descriptors. 140 * 141 * NB: tx descriptor size must match f/w expected size 142 * because f/w prefetch's the next descriptor linearly 143 * and doesn't chase the next pointer. 144 */ 145struct mwl_txdesc { 146 uint32_t Status; 147#define EAGLE_TXD_STATUS_IDLE 0x00000000 148#define EAGLE_TXD_STATUS_USED 0x00000001 149#define EAGLE_TXD_STATUS_OK 0x00000001 150#define EAGLE_TXD_STATUS_OK_RETRY 0x00000002 151#define EAGLE_TXD_STATUS_OK_MORE_RETRY 0x00000004 152#define EAGLE_TXD_STATUS_MULTICAST_TX 0x00000008 153#define EAGLE_TXD_STATUS_BROADCAST_TX 0x00000010 154#define EAGLE_TXD_STATUS_FAILED_LINK_ERROR 0x00000020 155#define EAGLE_TXD_STATUS_FAILED_EXCEED_LIMIT 0x00000040 156#define EAGLE_TXD_STATUS_FAILED_XRETRY EAGLE_TXD_STATUS_FAILED_EXCEED_LIMIT 157#define EAGLE_TXD_STATUS_FAILED_AGING 0x00000080 158#define EAGLE_TXD_STATUS_FW_OWNED 0x80000000 159 uint8_t DataRate; 160 uint8_t TxPriority; 161 uint16_t QosCtrl; 162 uint32_t PktPtr; 163 uint16_t PktLen; 164 uint8_t DestAddr[6]; 165 uint32_t pPhysNext; 166 uint32_t SapPktInfo; 167#define EAGLE_TXD_MODE_BONLY 1 168#define EAGLE_TXD_MODE_GONLY 2 169#define EAGLE_TXD_MODE_BG 3 170#define EAGLE_TXD_MODE_NONLY 4 171#define EAGLE_TXD_MODE_BN 5 172#define EAGLE_TXD_MODE_GN 6 173#define EAGLE_TXD_MODE_BGN 7 174#define EAGLE_TXD_MODE_AONLY 8 175#define EAGLE_TXD_MODE_AG 10 176#define EAGLE_TXD_MODE_AN 12 177 uint16_t Format; 178#define EAGLE_TXD_FORMAT 0x0001 /* frame format/rate */ 179#define EAGLE_TXD_FORMAT_LEGACY 0x0000 /* legacy rate frame */ 180#define EAGLE_TXD_FORMAT_HT 0x0001 /* HT rate frame */ 181#define EAGLE_TXD_GI 0x0002 /* guard interval */ 182#define EAGLE_TXD_GI_SHORT 0x0002 /* short guard interval */ 183#define EAGLE_TXD_GI_LONG 0x0000 /* long guard interval */ 184#define EAGLE_TXD_CHW 0x0004 /* channel width */ 185#define EAGLE_TXD_CHW_20 0x0000 /* 20MHz channel width */ 186#define EAGLE_TXD_CHW_40 0x0004 /* 40MHz channel width */ 187#define EAGLE_TXD_RATE 0x01f8 /* tx rate (legacy)/ MCS */ 188#define EAGLE_TXD_RATE_S 3 189#define EAGLE_TXD_ADV 0x0600 /* advanced coding */ 190#define EAGLE_TXD_ADV_S 9 191#define EAGLE_TXD_ADV_NONE 0x0000 192#define EAGLE_TXD_ADV_LDPC 0x0200 193#define EAGLE_TXD_ADV_RS 0x0400 194/* NB: 3 is reserved */ 195#define EAGLE_TXD_ANTENNA 0x1800 /* antenna select */ 196#define EAGLE_TXD_ANTENNA_S 11 197#define EAGLE_TXD_EXTCHAN 0x6000 /* extension channel */ 198#define EAGLE_TXD_EXTCHAN_S 13 199#define EAGLE_TXD_EXTCHAN_HI 0x0000 /* above */ 200#define EAGLE_TXD_EXTCHAN_LO 0x2000 /* below */ 201#define EAGLE_TXD_PREAMBLE 0x8000 202#define EAGLE_TXD_PREAMBLE_SHORT 0x8000 /* short preamble */ 203#define EAGLE_TXD_PREAMBLE_LONG 0x0000 /* long preamble */ 204 uint16_t pad; /* align to 4-byte boundary */ 205#define EAGLE_TXD_FIXED_RATE 0x0100 /* get tx rate from Format */ 206#define EAGLE_TXD_DONT_AGGR 0x0200 /* don't aggregate frame */ 207 uint32_t ack_wcb_addr; 208} __packed; 209 210struct mwl_ant_info { 211 uint8_t rssi_a; /* RSSI for antenna A */ 212 uint8_t rssi_b; /* RSSI for antenna B */ 213 uint8_t rssi_c; /* RSSI for antenna C */ 214 uint8_t rsvd1; /* Reserved */ 215 uint8_t nf_a; /* Noise floor for antenna A */ 216 uint8_t nf_b; /* Noise floor for antenna B */ 217 uint8_t nf_c; /* Noise floor for antenna C */ 218 uint8_t rsvd2; /* Reserved */ 219 uint8_t nf; /* Noise floor */ 220 uint8_t rsvd3[3]; /* Reserved - To make word aligned */ 221} __packed; 222 223struct mwl_rxdesc { 224 uint8_t RxControl; /* control element */ 225#define EAGLE_RXD_CTRL_DRIVER_OWN 0x00 226#define EAGLE_RXD_CTRL_OS_OWN 0x04 227#define EAGLE_RXD_CTRL_DMA_OWN 0x80 228 uint8_t RSSI; /* received signal strengt indication */ 229 uint8_t Status; /* status field w/ USED bit */ 230#define EAGLE_RXD_STATUS_IDLE 0x00 231#define EAGLE_RXD_STATUS_OK 0x01 232#define EAGLE_RXD_STATUS_MULTICAST_RX 0x02 233#define EAGLE_RXD_STATUS_BROADCAST_RX 0x04 234#define EAGLE_RXD_STATUS_FRAGMENT_RX 0x08 235#define EAGLE_RXD_STATUS_GENERAL_DECRYPT_ERR 0xff 236#define EAGLE_RXD_STATUS_DECRYPT_ERR_MASK 0x80 237#define EAGLE_RXD_STATUS_TKIP_MIC_DECRYPT_ERR 0x02 238#define EAGLE_RXD_STATUS_WEP_ICV_DECRYPT_ERR 0x04 239#define EAGLE_RXD_STATUS_TKIP_ICV_DECRYPT_ERR 0x08 240 uint8_t Channel; /* channel # pkt received on */ 241 uint16_t PktLen; /* total length of received data */ 242 uint8_t SQ2; /* not used */ 243 uint8_t Rate; /* received data rate */ 244 uint32_t pPhysBuffData; /* physical address of payload data */ 245 uint32_t pPhysNext; /* physical address of next RX desc */ 246 uint16_t QosCtrl; /* received QosCtrl field variable */ 247 uint16_t HtSig2; /* like name states */ 248#ifdef MWL_ANT_INFO_SUPPORT 249 struct mwl_ant_info ai; /* antenna info */ 250#endif 251} __packed; 252 253/* 254// Define OpMode for SoftAP/Station mode 255// 256// The following mode signature has to be written to PCI scratch register#0 257// right after successfully downloading the last block of firmware and 258// before waiting for firmware ready signature 259 */ 260#define HostCmd_STA_MODE 0x5A 261#define HostCmd_SOFTAP_MODE 0xA5 262 263#define HostCmd_STA_FWRDY_SIGNATURE 0xF0F1F2F4 264#define HostCmd_SOFTAP_FWRDY_SIGNATURE 0xF1F2F4A5 265 266//*************************************************************************** 267//*************************************************************************** 268 269//*************************************************************************** 270 271#define HostCmd_CMD_CODE_DNLD 0x0001 272#define HostCmd_CMD_GET_HW_SPEC 0x0003 273#define HostCmd_CMD_SET_HW_SPEC 0x0004 274#define HostCmd_CMD_MAC_MULTICAST_ADR 0x0010 275#define HostCmd_CMD_802_11_GET_STAT 0x0014 276#define HostCmd_CMD_MAC_REG_ACCESS 0x0019 277#define HostCmd_CMD_BBP_REG_ACCESS 0x001a 278#define HostCmd_CMD_RF_REG_ACCESS 0x001b 279#define HostCmd_CMD_802_11_RADIO_CONTROL 0x001c 280#define HostCmd_CMD_802_11_RF_TX_POWER 0x001e 281#define HostCmd_CMD_802_11_RF_ANTENNA 0x0020 282#define HostCmd_CMD_SET_BEACON 0x0100 283#define HostCmd_CMD_SET_AID 0x010d 284#define HostCmd_CMD_SET_RF_CHANNEL 0x010a 285#define HostCmd_CMD_SET_INFRA_MODE 0x010e 286#define HostCmd_CMD_SET_G_PROTECT_FLAG 0x010f 287#define HostCmd_CMD_802_11_RTS_THSD 0x0113 288#define HostCmd_CMD_802_11_SET_SLOT 0x0114 289 290#define HostCmd_CMD_802_11H_DETECT_RADAR 0x0120 291#define HostCmd_CMD_SET_WMM_MODE 0x0123 292#define HostCmd_CMD_HT_GUARD_INTERVAL 0x0124 293#define HostCmd_CMD_SET_FIXED_RATE 0x0126 294#define HostCmd_CMD_SET_LINKADAPT_CS_MODE 0x0129 295#define HostCmd_CMD_SET_MAC_ADDR 0x0202 296#define HostCmd_CMD_SET_RATE_ADAPT_MODE 0x0203 297#define HostCmd_CMD_GET_WATCHDOG_BITMAP 0x0205 298 299//SoftAP command code 300#define HostCmd_CMD_BSS_START 0x1100 301#define HostCmd_CMD_SET_NEW_STN 0x1111 302#define HostCmd_CMD_SET_KEEP_ALIVE 0x1112 303#define HostCmd_CMD_SET_APMODE 0x1114 304#define HostCmd_CMD_SET_SWITCH_CHANNEL 0x1121 305 306/* 307 @HWENCR@ 308 Command to update firmware encryption keys. 309*/ 310#define HostCmd_CMD_UPDATE_ENCRYPTION 0x1122 311/* 312 @11E-BA@ 313 Command to create/destroy block ACK 314*/ 315#define HostCmd_CMD_BASTREAM 0x1125 316#define HostCmd_CMD_SET_RIFS 0x1126 317#define HostCmd_CMD_SET_N_PROTECT_FLAG 0x1131 318#define HostCmd_CMD_SET_N_PROTECT_OPMODE 0x1132 319#define HostCmd_CMD_SET_OPTIMIZATION_LEVEL 0x1133 320#define HostCmd_CMD_GET_CALTABLE 0x1134 321#define HostCmd_CMD_SET_MIMOPSHT 0x1135 322#define HostCmd_CMD_GET_BEACON 0x1138 323#define HostCmd_CMD_SET_REGION_CODE 0x1139 324#define HostCmd_CMD_SET_POWERSAVESTATION 0x1140 325#define HostCmd_CMD_SET_TIM 0x1141 326#define HostCmd_CMD_GET_TIM 0x1142 327#define HostCmd_CMD_GET_SEQNO 0x1143 328#define HostCmd_CMD_DWDS_ENABLE 0x1144 329#define HostCmd_CMD_AMPDU_RETRY_RATEDROP_MODE 0x1145 330#define HostCmd_CMD_CFEND_ENABLE 0x1146 331 332/* 333// Define general result code for each command 334 */ 335#define HostCmd_RESULT_OK 0x0000 // OK 336#define HostCmd_RESULT_ERROR 0x0001 // Genenral error 337#define HostCmd_RESULT_NOT_SUPPORT 0x0002 // Command is not valid 338#define HostCmd_RESULT_PENDING 0x0003 // Command is pending (will be processed) 339#define HostCmd_RESULT_BUSY 0x0004 // System is busy (command ignored) 340#define HostCmd_RESULT_PARTIAL_DATA 0x0005 // Data buffer is not big enough 341 342 343/* 344// Definition of action or option for each command 345// 346// Define general purpose action 347 */ 348#define HostCmd_ACT_GEN_READ 0x0000 349#define HostCmd_ACT_GEN_WRITE 0x0001 350#define HostCmd_ACT_GEN_GET 0x0000 351#define HostCmd_ACT_GEN_SET 0x0001 352#define HostCmd_ACT_GEN_OFF 0x0000 353#define HostCmd_ACT_GEN_ON 0x0001 354 355#define HostCmd_ACT_DIFF_CHANNEL 0x0002 356#define HostCmd_ACT_GEN_SET_LIST 0x0002 357 358// Define action or option for HostCmd_FW_USE_FIXED_RATE 359#define HostCmd_ACT_USE_FIXED_RATE 0x0001 360#define HostCmd_ACT_NOT_USE_FIXED_RATE 0x0002 361 362// Define action or option for HostCmd_CMD_802_11_SET_WEP 363//#define HostCmd_ACT_ENABLE 0x0001 // Use MAC control for WEP on/off 364//#define HostCmd_ACT_DISABLE 0x0000 365#define HostCmd_ACT_ADD 0x0002 366#define HostCmd_ACT_REMOVE 0x0004 367#define HostCmd_ACT_USE_DEFAULT 0x0008 368 369#define HostCmd_TYPE_WEP_40_BIT 0x0001 // 40 bit 370#define HostCmd_TYPE_WEP_104_BIT 0x0002 // 104 bit 371#define HostCmd_TYPE_WEP_128_BIT 0x0003 // 128 bit 372#define HostCmd_TYPE_WEP_TX_KEY 0x0004 // TX WEP 373 374#define HostCmd_NUM_OF_WEP_KEYS 4 375 376#define HostCmd_WEP_KEY_INDEX_MASK 0x3fffffff 377 378 379// Define action or option for HostCmd_CMD_802_11_RESET 380#define HostCmd_ACT_HALT 0x0001 381#define HostCmd_ACT_RESTART 0x0002 382 383// Define action or option for HostCmd_CMD_802_11_RADIO_CONTROL 384#define HostCmd_TYPE_AUTO_PREAMBLE 0x0001 385#define HostCmd_TYPE_SHORT_PREAMBLE 0x0002 386#define HostCmd_TYPE_LONG_PREAMBLE 0x0003 387 388// Define action or option for CMD_802_11_RF_CHANNEL 389#define HostCmd_TYPE_802_11A 0x0001 390#define HostCmd_TYPE_802_11B 0x0002 391 392// Define action or option for HostCmd_CMD_802_11_RF_TX_POWER 393#define HostCmd_ACT_TX_POWER_OPT_SET_HIGH 0x0003 394#define HostCmd_ACT_TX_POWER_OPT_SET_MID 0x0002 395#define HostCmd_ACT_TX_POWER_OPT_SET_LOW 0x0001 396#define HostCmd_ACT_TX_POWER_OPT_SET_AUTO 0x0000 397 398#define HostCmd_ACT_TX_POWER_LEVEL_MIN 0x000e // in dbm 399#define HostCmd_ACT_TX_POWER_LEVEL_GAP 0x0001 // in dbm 400// Define action or option for HostCmd_CMD_802_11_DATA_RATE 401#define HostCmd_ACT_SET_TX_AUTO 0x0000 402#define HostCmd_ACT_SET_TX_FIX_RATE 0x0001 403#define HostCmd_ACT_GET_TX_RATE 0x0002 404 405#define HostCmd_ACT_SET_RX 0x0001 406#define HostCmd_ACT_SET_TX 0x0002 407#define HostCmd_ACT_SET_BOTH 0x0003 408#define HostCmd_ACT_GET_RX 0x0004 409#define HostCmd_ACT_GET_TX 0x0008 410#define HostCmd_ACT_GET_BOTH 0x000c 411 412#define TYPE_ANTENNA_DIVERSITY 0xffff 413 414// Define action or option for HostCmd_CMD_802_11_PS_MODE 415#define HostCmd_TYPE_CAM 0x0000 416#define HostCmd_TYPE_MAX_PSP 0x0001 417#define HostCmd_TYPE_FAST_PSP 0x0002 418 419#define HostCmd_CMD_SET_EDCA_PARAMS 0x0115 420 421//============================================================================= 422// HOST COMMAND DEFINITIONS 423//============================================================================= 424 425// 426// Definition of data structure for each command 427// 428// Define general data structure 429typedef struct { 430 uint16_t Cmd; 431 uint16_t Length; 432#ifdef MWL_MBSS_SUPPORT 433 uint8_t SeqNum; 434 uint8_t MacId; 435#else 436 uint16_t SeqNum; 437#endif 438 uint16_t Result; 439} __packed FWCmdHdr; 440 441typedef struct { 442 FWCmdHdr CmdHdr; 443 uint8_t Version; // HW revision 444 uint8_t HostIf; // Host interface 445 uint16_t NumOfMCastAdr; // Max. number of Multicast address FW can handle 446 uint8_t PermanentAddr[6]; // MAC address 447 uint16_t RegionCode; // Region Code 448 uint32_t FWReleaseNumber; // 4 byte of FW release number 449 uint32_t ulFwAwakeCookie; // Firmware awake cookie 450 uint32_t DeviceCaps; // Device capabilities (see above) 451 uint32_t RxPdWrPtr; // Rx shared memory queue 452 uint32_t NumTxQueues; // # TX queues in WcbBase array 453 uint32_t WcbBase[MAX_TXWCB_QUEUES]; // TX WCB Rings 454 uint32_t Flags; 455#define SET_HW_SPEC_DISABLEMBSS 0x08 456#define SET_HW_SPEC_HOSTFORM_BEACON 0x10 457#define SET_HW_SPEC_HOSTFORM_PROBERESP 0x20 458#define SET_HW_SPEC_HOST_POWERSAVE 0x40 459#define SET_HW_SPEC_HOSTENCRDECR_MGMT 0x80 460 uint32_t TxWcbNumPerQueue; 461 uint32_t TotalRxWcb; 462} __packed HostCmd_DS_SET_HW_SPEC; 463 464typedef struct { 465 FWCmdHdr CmdHdr; 466 u_int8_t Version; /* version of the HW */ 467 u_int8_t HostIf; /* host interface */ 468 u_int16_t NumOfWCB; /* Max. number of WCB FW can handle */ 469 u_int16_t NumOfMCastAddr; /* MaxNbr of MC addresses FW can handle */ 470 u_int8_t PermanentAddr[6]; /* MAC address programmed in HW */ 471 u_int16_t RegionCode; 472 u_int16_t NumberOfAntenna; /* Number of antenna used */ 473 u_int32_t FWReleaseNumber; /* 4 byte of FW release number */ 474 u_int32_t WcbBase0; 475 u_int32_t RxPdWrPtr; 476 u_int32_t RxPdRdPtr; 477 u_int32_t ulFwAwakeCookie; 478 u_int32_t WcbBase1[TOTAL_TX_QUEUES-1]; 479} __packed HostCmd_DS_GET_HW_SPEC; 480 481typedef struct { 482 FWCmdHdr CmdHdr; 483 u_int32_t Enable; /* FALSE: Disable or TRUE: Enable */ 484} __packed HostCmd_DS_BSS_START; 485 486 487typedef struct { 488 u_int8_t ElemId; 489 u_int8_t Len; 490 u_int8_t OuiType[4]; /* 00:50:f2:01 */ 491 u_int8_t Ver[2]; 492 u_int8_t GrpKeyCipher[4]; 493 u_int8_t PwsKeyCnt[2]; 494 u_int8_t PwsKeyCipherList[4]; 495 u_int8_t AuthKeyCnt[2]; 496 u_int8_t AuthKeyList[4]; 497} __packed RsnIE_t; 498 499typedef struct { 500 u_int8_t ElemId; 501 u_int8_t Len; 502 u_int8_t Ver[2]; 503 u_int8_t GrpKeyCipher[4]; 504 u_int8_t PwsKeyCnt[2]; 505 u_int8_t PwsKeyCipherList[4]; 506 u_int8_t AuthKeyCnt[2]; 507 u_int8_t AuthKeyList[4]; 508 u_int8_t RsnCap[2]; 509} __packed Rsn48IE_t; 510 511typedef struct { 512 u_int8_t ElementId; 513 u_int8_t Len; 514 u_int8_t CfpCnt; 515 u_int8_t CfpPeriod; 516 u_int16_t CfpMaxDuration; 517 u_int16_t CfpDurationRemaining; 518} __packed CfParams_t; 519 520typedef struct { 521 u_int8_t ElementId; 522 u_int8_t Len; 523 u_int16_t AtimWindow; 524} __packed IbssParams_t; 525 526typedef union { 527 CfParams_t CfParamSet; 528 IbssParams_t IbssParamSet; 529} __packed SsParams_t; 530 531typedef struct { 532 u_int8_t ElementId; 533 u_int8_t Len; 534 u_int16_t DwellTime; 535 u_int8_t HopSet; 536 u_int8_t HopPattern; 537 u_int8_t HopIndex; 538} __packed FhParams_t; 539 540typedef struct { 541 u_int8_t ElementId; 542 u_int8_t Len; 543 u_int8_t CurrentChan; 544} __packed DsParams_t; 545 546typedef union { 547 FhParams_t FhParamSet; 548 DsParams_t DsParamSet; 549} __packed PhyParams_t; 550 551typedef struct { 552 u_int8_t FirstChannelNum; 553 u_int8_t NumOfChannels; 554 u_int8_t MaxTxPwrLevel; 555} __packed ChannelInfo_t; 556 557typedef struct { 558 u_int8_t ElementId; 559 u_int8_t Len; 560 u_int8_t CountryStr[3]; 561 ChannelInfo_t ChannelInfo[40]; 562} __packed Country_t; 563 564typedef struct { 565 u_int8_t AIFSN : 4; 566 u_int8_t ACM : 1; 567 u_int8_t ACI : 2; 568 u_int8_t rsvd : 1; 569 570}__packed ACIAIFSN_field_t; 571 572typedef struct { 573 u_int8_t ECW_min : 4; 574 u_int8_t ECW_max : 4; 575}__packed ECWmin_max_field_t; 576 577typedef struct { 578 ACIAIFSN_field_t ACI_AIFSN; 579 ECWmin_max_field_t ECW_min_max; 580 u_int16_t TXOP_lim; 581}__packed ACparam_rcd_t; 582 583typedef struct { 584 u_int8_t ElementId; 585 u_int8_t Len; 586 u_int8_t OUI[3]; 587 u_int8_t Type; 588 u_int8_t Subtype; 589 u_int8_t version; 590 u_int8_t rsvd; 591 ACparam_rcd_t AC_BE; 592 ACparam_rcd_t AC_BK; 593 ACparam_rcd_t AC_VI; 594 ACparam_rcd_t AC_VO; 595} __packed WMM_param_elem_t ; 596 597typedef struct { 598#ifdef MWL_MBSS_SUPPORT 599 u_int8_t StaMacAddr[6]; 600#endif 601 u_int8_t SsId[32]; 602 u_int8_t BssType; 603 u_int16_t BcnPeriod; 604 u_int8_t DtimPeriod; 605 SsParams_t SsParamSet; 606 PhyParams_t PhyParamSet; 607 u_int16_t ProbeDelay; 608 u_int16_t CapInfo; /* see below */ 609 u_int8_t BssBasicRateSet[14]; 610 u_int8_t OpRateSet[14]; 611 RsnIE_t RsnIE; 612 Rsn48IE_t Rsn48IE; 613 WMM_param_elem_t WMMParam; 614 Country_t Country; 615 u_int32_t ApRFType; /* 0->B, 1->G, 2->Mixed, 3->A, 4->11J */ 616} __packed StartCmd_t; 617 618#define HostCmd_CAPINFO_DEFAULT 0x0000 619#define HostCmd_CAPINFO_ESS 0x0001 620#define HostCmd_CAPINFO_IBSS 0x0002 621#define HostCmd_CAPINFO_CF_POLLABLE 0x0004 622#define HostCmd_CAPINFO_CF_REQUEST 0x0008 623#define HostCmd_CAPINFO_PRIVACY 0x0010 624#define HostCmd_CAPINFO_SHORT_PREAMBLE 0x0020 625#define HostCmd_CAPINFO_PBCC 0x0040 626#define HostCmd_CAPINFO_CHANNEL_AGILITY 0x0080 627#define HostCmd_CAPINFO_SHORT_SLOT 0x0400 628#define HostCmd_CAPINFO_DSSS_OFDM 0x2000 629 630typedef struct { 631 FWCmdHdr CmdHdr; 632 StartCmd_t StartCmd; 633} __packed HostCmd_DS_AP_BEACON; 634 635typedef struct { 636 FWCmdHdr CmdHdr; 637 uint16_t FrmBodyLen; 638 uint8_t FrmBody[1]; /* NB: variable length */ 639} __packed HostCmd_DS_SET_BEACON; 640 641// Define data structure for HostCmd_CMD_MAC_MULTICAST_ADR 642typedef struct { 643 FWCmdHdr CmdHdr; 644 uint16_t Action; 645 uint16_t NumOfAdrs; 646#define MWL_HAL_MCAST_MAX 32 647 uint8_t MACList[6*32]; 648} __packed HostCmd_DS_MAC_MULTICAST_ADR; 649 650// Indicate to FW the current state of AP ERP info 651typedef struct { 652 FWCmdHdr CmdHdr; 653 uint32_t GProtectFlag; 654} __packed HostCmd_FW_SET_G_PROTECT_FLAG; 655 656typedef struct { 657 FWCmdHdr CmdHdr; 658} __packed HostCmd_FW_SET_INFRA_MODE; 659 660// Define data structure for HostCmd_CMD_802_11_RF_CHANNEL 661typedef struct { 662 FWCmdHdr CmdHdr; 663 uint16_t Action; 664 uint8_t CurrentChannel; /* channel # */ 665 uint32_t ChannelFlags; /* see below */ 666} __packed HostCmd_FW_SET_RF_CHANNEL; 667 668/* bits 0-5 specify frequency band */ 669#define FREQ_BAND_2DOT4GHZ 0x0001 670#define FREQ_BAND_4DOT9GHZ 0x0002 /* XXX not implemented */ 671#define FREQ_BAND_5GHZ 0x0004 672#define FREQ_BAND_5DOT2GHZ 0x0008 /* XXX not implemented */ 673/* bits 6-10 specify channel width */ 674#define CH_AUTO_WIDTH 0x0000 /* XXX not used? */ 675#define CH_10_MHz_WIDTH 0x0040 676#define CH_20_MHz_WIDTH 0x0080 677#define CH_40_MHz_WIDTH 0x0100 678/* bits 11-12 specify extension channel */ 679#define EXT_CH_NONE 0x0000 /* no extension channel */ 680#define EXT_CH_ABOVE_CTRL_CH 0x0800 /* extension channel above */ 681#define EXT_CH_AUTO 0x1000 /* XXX not used? */ 682#define EXT_CH_BELOW_CTRL_CH 0x1800 /* extension channel below */ 683/* bits 13-31 are reserved */ 684 685#define FIXED_RATE_WITH_AUTO_RATE_DROP 0 686#define FIXED_RATE_WITHOUT_AUTORATE_DROP 1 687 688#define LEGACY_RATE_TYPE 0 689#define HT_RATE_TYPE 1 690 691#define RETRY_COUNT_VALID 0 692#define RETRY_COUNT_INVALID 1 693 694typedef struct { 695 // lower rate after the retry count 696 uint32_t FixRateType; //0: legacy, 1: HT 697 uint32_t RetryCountValid; //0: retry count is not valid, 1: use retry count specified 698} __packed FIX_RATE_FLAG; 699 700typedef struct { 701 FIX_RATE_FLAG FixRateTypeFlags; 702 uint32_t FixedRate; // legacy rate(not index) or an MCS code. 703 uint32_t RetryCount; 704} __packed FIXED_RATE_ENTRY; 705 706typedef struct { 707 FWCmdHdr CmdHdr; 708 uint32_t Action; //HostCmd_ACT_GEN_GET 0x0000 709 //HostCmd_ACT_GEN_SET 0x0001 710 //HostCmd_ACT_NOT_USE_FIXED_RATE 0x0002 711 uint32_t AllowRateDrop; // use fixed rate specified but firmware can drop to 712 uint32_t EntryCount; 713 FIXED_RATE_ENTRY FixedRateTable[4]; 714 uint8_t MulticastRate; 715 uint8_t MultiRateTxType; 716 uint8_t ManagementRate; 717} __packed HostCmd_FW_USE_FIXED_RATE; 718 719typedef struct { 720 uint32_t AllowRateDrop; 721 uint32_t EntryCount; 722 FIXED_RATE_ENTRY FixedRateTable[4]; 723} __packed USE_FIXED_RATE_INFO; 724 725typedef struct { 726 FWCmdHdr CmdHdr; 727 uint32_t Action; 728 uint32_t GIType; 729#define GI_TYPE_LONG 0x0001 730#define GI_TYPE_SHORT 0x0002 731} __packed HostCmd_FW_HT_GUARD_INTERVAL; 732 733typedef struct { 734 FWCmdHdr CmdHdr; 735 uint32_t Action; 736 uint8_t RxAntennaMap; 737 uint8_t TxAntennaMap; 738} __packed HostCmd_FW_HT_MIMO_CONFIG; 739 740typedef struct { 741 FWCmdHdr CmdHdr; 742 uint16_t Action; 743 uint8_t Slot; // Slot=0 if regular, Slot=1 if short. 744} __packed HostCmd_FW_SET_SLOT; 745 746 747// Define data structure for HostCmd_CMD_802_11_GET_STAT 748typedef struct { 749 FWCmdHdr CmdHdr; 750 uint32_t TxRetrySuccesses; 751 uint32_t TxMultipleRetrySuccesses; 752 uint32_t TxFailures; 753 uint32_t RTSSuccesses; 754 uint32_t RTSFailures; 755 uint32_t AckFailures; 756 uint32_t RxDuplicateFrames; 757 uint32_t FCSErrorCount; 758 uint32_t TxWatchDogTimeouts; 759 uint32_t RxOverflows; //used 760 uint32_t RxFragErrors; //used 761 uint32_t RxMemErrors; //used 762 uint32_t PointerErrors; //used 763 uint32_t TxUnderflows; //used 764 uint32_t TxDone; 765 uint32_t TxDoneBufTryPut; 766 uint32_t TxDoneBufPut; 767 uint32_t Wait4TxBuf; // Put size of requested buffer in here 768 uint32_t TxAttempts; 769 uint32_t TxSuccesses; 770 uint32_t TxFragments; 771 uint32_t TxMulticasts; 772 uint32_t RxNonCtlPkts; 773 uint32_t RxMulticasts; 774 uint32_t RxUndecryptableFrames; 775 uint32_t RxICVErrors; 776 uint32_t RxExcludedFrames; 777} __packed HostCmd_DS_802_11_GET_STAT; 778 779 780// Define data structure for HostCmd_CMD_MAC_REG_ACCESS 781typedef struct { 782 FWCmdHdr CmdHdr; 783 uint16_t Action; 784 uint16_t Offset; 785 uint32_t Value; 786 uint16_t Reserved; 787} __packed HostCmd_DS_MAC_REG_ACCESS; 788 789// Define data structure for HostCmd_CMD_BBP_REG_ACCESS 790typedef struct { 791 FWCmdHdr CmdHdr; 792 uint16_t Action; 793 uint16_t Offset; 794 uint8_t Value; 795 uint8_t Reserverd[3]; 796} __packed HostCmd_DS_BBP_REG_ACCESS; 797 798// Define data structure for HostCmd_CMD_RF_REG_ACCESS 799typedef struct { 800 FWCmdHdr CmdHdr; 801 uint16_t Action; 802 uint16_t Offset; 803 uint8_t Value; 804 uint8_t Reserverd[3]; 805} __packed HostCmd_DS_RF_REG_ACCESS; 806 807 808// Define data structure for HostCmd_CMD_802_11_RADIO_CONTROL 809typedef struct { 810 FWCmdHdr CmdHdr; 811 uint16_t Action; 812 uint16_t Control; // @bit0: 1/0,on/off, @bit1: 1/0, long/short @bit2: 1/0,auto/fix 813 uint16_t RadioOn; 814} __packed HostCmd_DS_802_11_RADIO_CONTROL; 815 816 817#define TX_POWER_LEVEL_TOTAL 8 818// Define data structure for HostCmd_CMD_802_11_RF_TX_POWER 819typedef struct { 820 FWCmdHdr CmdHdr; 821 uint16_t Action; 822 uint16_t SupportTxPowerLevel; 823 uint16_t CurrentTxPowerLevel; 824 uint16_t Reserved; 825 uint16_t PowerLevelList[TX_POWER_LEVEL_TOTAL]; 826} __packed HostCmd_DS_802_11_RF_TX_POWER; 827 828// Define data structure for HostCmd_CMD_802_11_RF_ANTENNA 829typedef struct _HostCmd_DS_802_11_RF_ANTENNA { 830 FWCmdHdr CmdHdr; 831 uint16_t Action; 832 uint16_t AntennaMode; // Number of antennas or 0xffff(diversity) 833} __packed HostCmd_DS_802_11_RF_ANTENNA; 834 835// Define data structure for HostCmd_CMD_802_11_PS_MODE 836typedef struct { 837 FWCmdHdr CmdHdr; 838 uint16_t Action; 839 uint16_t PowerMode; // CAM, Max.PSP or Fast PSP 840} __packed HostCmd_DS_802_11_PS_MODE; 841 842typedef struct { 843 FWCmdHdr CmdHdr; 844 uint16_t Action; 845 uint16_t Threshold; 846} __packed HostCmd_DS_802_11_RTS_THSD; 847 848// used for stand alone bssid sets/clears 849typedef struct { 850 FWCmdHdr CmdHdr; 851#ifdef MWL_MBSS_SUPPORT 852 uint16_t MacType; 853#define WL_MAC_TYPE_PRIMARY_CLIENT 0 854#define WL_MAC_TYPE_SECONDARY_CLIENT 1 855#define WL_MAC_TYPE_PRIMARY_AP 2 856#define WL_MAC_TYPE_SECONDARY_AP 3 857#endif 858 uint8_t MacAddr[6]; 859} __packed HostCmd_DS_SET_MAC, 860 HostCmd_FW_SET_BSSID, 861 HostCmd_FW_SET_MAC; 862 863// Indicate to FW to send out PS Poll 864typedef struct { 865 FWCmdHdr CmdHdr; 866 uint32_t PSPoll; 867} __packed HostCmd_FW_TX_POLL; 868 869// used for AID sets/clears 870typedef struct { 871 FWCmdHdr CmdHdr; 872 uint16_t AssocID; 873 uint8_t MacAddr[6]; //AP's Mac Address(BSSID) 874 uint32_t GProtection; 875 uint8_t ApRates[ RATE_INDEX_MAX_ARRAY]; 876} __packed HostCmd_FW_SET_AID; 877 878typedef struct { 879 uint32_t LegacyRateBitMap; 880 uint32_t HTRateBitMap; 881 uint16_t CapInfo; 882 uint16_t HTCapabilitiesInfo; 883 uint8_t MacHTParamInfo; 884 uint8_t Rev; 885 struct { 886 uint8_t ControlChan; 887 uint8_t AddChan; 888 uint16_t OpMode; 889 uint16_t stbc; 890 } __packed AddHtInfo; 891} __packed PeerInfo_t; 892 893typedef struct { 894 FWCmdHdr CmdHdr; 895 uint16_t AID; 896 uint8_t MacAddr[6]; 897 uint16_t StnId; 898 uint16_t Action; 899 uint16_t Reserved; 900 PeerInfo_t PeerInfo; 901 uint8_t Qosinfo; 902 uint8_t isQosSta; 903 uint32_t FwStaPtr; 904} __packed HostCmd_FW_SET_NEW_STN; 905 906typedef struct { 907 FWCmdHdr CmdHdr; 908 uint8_t tick; 909} __packed HostCmd_FW_SET_KEEP_ALIVE_TICK; 910 911typedef struct { 912 FWCmdHdr CmdHdr; 913 uint8_t QNum; 914} __packed HostCmd_FW_SET_RIFS; 915 916typedef struct { 917 FWCmdHdr CmdHdr; 918 uint8_t ApMode; 919} __packed HostCmd_FW_SET_APMODE; 920 921typedef struct { 922 FWCmdHdr CmdHdr; 923 uint16_t Action; // see following 924 uint16_t RadarTypeCode; 925} __packed HostCmd_802_11h_Detect_Radar; 926 927#define DR_DFS_DISABLE 0 928#define DR_CHK_CHANNEL_AVAILABLE_START 1 929#define DR_CHK_CHANNEL_AVAILABLE_STOP 2 930#define DR_IN_SERVICE_MONITOR_START 3 931 932//New Structure for Update Tim 30/9/2003 933typedef struct { 934 FWCmdHdr CmdHdr; 935 uint16_t Aid; 936 uint32_t Set; 937} __packed HostCmd_UpdateTIM; 938 939typedef struct { 940 FWCmdHdr CmdHdr; 941 uint32_t SsidBroadcastEnable; 942} __packed HostCmd_SSID_BROADCAST; 943 944typedef struct { 945 FWCmdHdr CmdHdr; 946 uint32_t WdsEnable; 947} __packed HostCmd_WDS; 948 949typedef struct { 950 FWCmdHdr CmdHdr; 951 uint32_t Next11hChannel; 952 uint32_t Mode; 953 uint32_t InitialCount; 954 uint32_t ChannelFlags ; 955} __packed HostCmd_SET_SWITCH_CHANNEL; 956 957typedef struct { 958 FWCmdHdr CmdHdr; 959 uint32_t SpectrumMgmt; 960} __packed HostCmd_SET_SPECTRUM_MGMT; 961 962typedef struct { 963 FWCmdHdr CmdHdr; 964 int32_t PowerConstraint; 965} __packed HostCmd_SET_POWER_CONSTRAINT; 966 967typedef struct { 968 uint8_t FirstChannelNo; 969 uint8_t NoofChannel; 970 uint8_t MaxTransmitPw; 971} __packed DomainChannelEntry; 972 973typedef struct { 974 uint8_t CountryString[3]; 975 uint8_t GChannelLen; 976 DomainChannelEntry DomainEntryG[1]; /** Assume only 1 G zone **/ 977 uint8_t AChannelLen; 978 DomainChannelEntry DomainEntryA[20]; /** Assume max of 5 A zone **/ 979} __packed DomainCountryInfo; 980 981typedef struct { 982 FWCmdHdr CmdHdr; 983 uint32_t Action ; // 0 -> unset, 1 ->set 984 DomainCountryInfo DomainInfo ; 985} __packed HostCmd_SET_COUNTRY_INFO; 986 987typedef struct { 988 FWCmdHdr CmdHdr; 989 uint16_t regionCode ; 990} __packed HostCmd_SET_REGIONCODE_INFO; 991 992// for HostCmd_CMD_SET_WMM_MODE 993typedef struct { 994 FWCmdHdr CmdHdr; 995 uint16_t Action; // 0->unset, 1->set 996} __packed HostCmd_FW_SetWMMMode; 997 998typedef struct { 999 FWCmdHdr CmdHdr; 1000 uint16_t Action; // 0->unset, 1->set 1001 uint16_t IeListLen; 1002 uint8_t IeList[200]; 1003} __packed HostCmd_FW_SetIEs; 1004 1005#define EDCA_PARAM_SIZE 18 1006#define BA_PARAM_SIZE 2 1007 1008typedef struct { 1009 FWCmdHdr CmdHdr; 1010 uint16_t Action; //0 = get all, 0x1 =set CWMin/Max, 0x2 = set TXOP , 0x4 =set AIFSN 1011 uint16_t TxOP; // in unit of 32 us 1012 uint32_t CWMax; // 0~15 1013 uint32_t CWMin; // 0~15 1014 uint8_t AIFSN; 1015 uint8_t TxQNum; // Tx Queue number. 1016} __packed HostCmd_FW_SET_EDCA_PARAMS; 1017 1018/****************************************************************************** 1019 @HWENCR@ 1020 Hardware Encryption related data structures and constant definitions. 1021 Note that all related changes are marked with the @HWENCR@ tag. 1022*******************************************************************************/ 1023 1024#define MAX_ENCR_KEY_LENGTH 16 /* max 128 bits - depends on type */ 1025#define MIC_KEY_LENGTH 8 /* size of Tx/Rx MIC key - 8 bytes*/ 1026 1027#define ENCR_KEY_TYPE_ID_WEP 0x00 /* Key type is WEP */ 1028#define ENCR_KEY_TYPE_ID_TKIP 0x01 /* Key type is TKIP */ 1029#define ENCR_KEY_TYPE_ID_AES 0x02 /* Key type is AES-CCMP */ 1030 1031/* flags used in structure - same as driver EKF_XXX flags */ 1032#define ENCR_KEY_FLAG_INUSE 0x00000001 /* indicate key is in use */ 1033#define ENCR_KEY_FLAG_RXGROUPKEY 0x00000002 /* Group key for RX only */ 1034#define ENCR_KEY_FLAG_TXGROUPKEY 0x00000004 /* Group key for TX */ 1035#define ENCR_KEY_FLAG_PAIRWISE 0x00000008 /* pairwise */ 1036#define ENCR_KEY_FLAG_RXONLY 0x00000010 /* only used for RX */ 1037// These flags are new additions - for hardware encryption commands only. 1038#define ENCR_KEY_FLAG_AUTHENTICATOR 0x00000020 /* Key is for Authenticator */ 1039#define ENCR_KEY_FLAG_TSC_VALID 0x00000040 /* Sequence counters valid */ 1040#define ENCR_KEY_FLAG_WEP_TXKEY 0x01000000 /* Tx key for WEP */ 1041#define ENCR_KEY_FLAG_MICKEY_VALID 0x02000000 /* Tx/Rx MIC keys are valid */ 1042 1043/* 1044 UPDATE_ENCRYPTION command action type. 1045*/ 1046typedef enum { 1047 // request to enable/disable HW encryption 1048 EncrActionEnableHWEncryption, 1049 // request to set encryption key 1050 EncrActionTypeSetKey, 1051 // request to remove one or more keys 1052 EncrActionTypeRemoveKey, 1053 EncrActionTypeSetGroupKey 1054} ENCR_ACTION_TYPE; 1055 1056/* 1057 Key material definitions (for WEP, TKIP, & AES-CCMP) 1058*/ 1059 1060/* 1061 WEP Key material definition 1062 ---------------------------- 1063 WEPKey --> An array of 'MAX_ENCR_KEY_LENGTH' bytes. 1064 Note that we do not support 152bit WEP keys 1065*/ 1066typedef struct { 1067 // WEP key material (max 128bit) 1068 uint8_t KeyMaterial[ MAX_ENCR_KEY_LENGTH ]; 1069} __packed WEP_TYPE_KEY; 1070 1071/* 1072 TKIP Key material definition 1073 ---------------------------- 1074 This structure defines TKIP key material. Note that 1075 the TxMicKey and RxMicKey may or may not be valid. 1076*/ 1077/* TKIP Sequence counter - 24 bits */ 1078/* Incremented on each fragment MPDU */ 1079typedef struct { 1080 uint16_t low; 1081 uint32_t high; 1082} __packed ENCR_TKIPSEQCNT; 1083 1084typedef struct { 1085 // TKIP Key material. Key type (group or pairwise key) is 1086 // determined by flags in KEY_PARAM_SET structure. 1087 uint8_t KeyMaterial[ MAX_ENCR_KEY_LENGTH ]; 1088 uint8_t TkipTxMicKey[ MIC_KEY_LENGTH ]; 1089 uint8_t TkipRxMicKey[ MIC_KEY_LENGTH ]; 1090 ENCR_TKIPSEQCNT TkipRsc; 1091 ENCR_TKIPSEQCNT TkipTsc; 1092} __packed TKIP_TYPE_KEY; 1093 1094/* 1095 AES-CCMP Key material definition 1096 -------------------------------- 1097 This structure defines AES-CCMP key material. 1098*/ 1099typedef struct { 1100 // AES Key material 1101 uint8_t KeyMaterial[ MAX_ENCR_KEY_LENGTH ]; 1102} __packed AES_TYPE_KEY; 1103 1104/* 1105 Encryption key definition. 1106 -------------------------- 1107 This structure provides all required/essential 1108 information about the key being set/removed. 1109*/ 1110typedef struct { 1111 uint16_t Length; // Total length of this structure 1112 uint16_t KeyTypeId; // Key type - WEP, TKIP or AES-CCMP. 1113 uint32_t KeyInfo; // key flags (ENCR_KEY_FLAG_XXX_ 1114 uint32_t KeyIndex; // For WEP only - actual key index 1115 uint16_t KeyLen; // Size of the key 1116 union { // Key material (variable size array) 1117 WEP_TYPE_KEY WepKey; 1118 TKIP_TYPE_KEY TkipKey; 1119 AES_TYPE_KEY AesKey; 1120 }__packed Key; 1121#ifdef MWL_MBSS_SUPPORT 1122 uint8_t Macaddr[6]; 1123#endif 1124} __packed KEY_PARAM_SET; 1125 1126/* 1127 HostCmd_FW_UPDATE_ENCRYPTION 1128 ---------------------------- 1129 Define data structure for updating firmware encryption keys. 1130 1131*/ 1132typedef struct { 1133 FWCmdHdr CmdHdr; 1134 uint32_t ActionType; // ENCR_ACTION_TYPE 1135 uint32_t DataLength; // size of the data buffer attached. 1136#ifdef MWL_MBSS_SUPPORT 1137 uint8_t macaddr[6]; 1138#endif 1139 uint8_t ActionData[1]; 1140} __packed HostCmd_FW_UPDATE_ENCRYPTION; 1141 1142 1143typedef struct { 1144 FWCmdHdr CmdHdr; 1145 uint32_t ActionType; // ENCR_ACTION_TYPE 1146 uint32_t DataLength; // size of the data buffer attached. 1147 KEY_PARAM_SET KeyParam; 1148#ifndef MWL_MBSS_SUPPORT 1149 uint8_t Macaddr[8]; /* XXX? */ 1150#endif 1151} __packed HostCmd_FW_UPDATE_ENCRYPTION_SET_KEY; 1152 1153typedef struct { 1154 // Rate flags - see above. 1155 uint32_t Flags; 1156 // Rate in 500Kbps units. 1157 uint8_t RateKbps; 1158 // 802.11 rate to conversion table index value. 1159 // This is the value required by the firmware/hardware. 1160 uint16_t RateCodeToIndex; 1161}__packed RATE_INFO; 1162 1163/* 1164 UPDATE_STADB command action type. 1165*/ 1166typedef enum { 1167 // request to add entry to stainfo db 1168 StaInfoDbActionAddEntry, 1169 // request to modify peer entry 1170 StaInfoDbActionModifyEntry, 1171 // request to remove peer from stainfo db 1172 StaInfoDbActionRemoveEntry 1173}__packed STADB_ACTION_TYPE; 1174 1175/* 1176 @11E-BA@ 1177 802.11e/WMM Related command(s)/data structures 1178*/ 1179 1180// Flag to indicate if the stream is an immediate block ack stream. 1181// if this bit is not set, the stream is delayed block ack stream. 1182#define BASTREAM_FLAG_DELAYED_TYPE 0x00 1183#define BASTREAM_FLAG_IMMEDIATE_TYPE 0x01 1184 1185// Flag to indicate the direction of the stream (upstream/downstream). 1186// If this bit is not set, the direction is downstream. 1187#define BASTREAM_FLAG_DIRECTION_UPSTREAM 0x00 1188#define BASTREAM_FLAG_DIRECTION_DOWNSTREAM 0x02 1189#define BASTREAM_FLAG_DIRECTION_DLP 0x04 1190#define BASTREAM_FLAG_DIRECTION_BOTH 0x06 1191 1192typedef enum { 1193 BaCreateStream, 1194 BaUpdateStream, 1195 BaDestroyStream, 1196 BaFlushStream, 1197 BaCheckCreateStream 1198} BASTREAM_ACTION_TYPE; 1199 1200typedef struct { 1201 uint32_t Context; 1202} __packed BASTREAM_CONTEXT; 1203 1204// parameters for block ack creation 1205typedef struct { 1206 // BA Creation flags - see above 1207 uint32_t Flags; 1208 // idle threshold 1209 uint32_t IdleThrs; 1210 // block ack transmit threshold (after how many pkts should we send BAR?) 1211 uint32_t BarThrs; 1212 // receiver window size 1213 uint32_t WindowSize; 1214 // MAC Address of the BA partner 1215 uint8_t PeerMacAddr[6]; 1216 // Dialog Token 1217 uint8_t DialogToken; 1218 //TID for the traffic stream in this BA 1219 uint8_t Tid; 1220 // shared memory queue ID (not sure if this is required) 1221 uint8_t QueueId; 1222 uint8_t ParamInfo; 1223 // returned by firmware - firmware context pointer. 1224 // this context pointer will be passed to firmware for all future commands. 1225 BASTREAM_CONTEXT FwBaContext; 1226 uint8_t ResetSeqNo; /** 0 or 1**/ 1227 uint16_t StartSeqNo; 1228 1229 // proxy sta MAC Address 1230 uint8_t StaSrcMacAddr[6]; 1231}__packed BASTREAM_CREATE_STREAM; 1232 1233// new transmit sequence number information 1234typedef struct { 1235 // BA flags - see above 1236 uint32_t Flags; 1237 // returned by firmware in the create ba stream response 1238 BASTREAM_CONTEXT FwBaContext; 1239 // new sequence number for this block ack stream 1240 uint16_t BaSeqNum; 1241}__packed BASTREAM_UPDATE_STREAM; 1242 1243typedef struct { 1244 // BA Stream flags 1245 uint32_t Flags; 1246 // returned by firmware in the create ba stream response 1247 BASTREAM_CONTEXT FwBaContext; 1248}__packed BASTREAM_STREAM_INFO; 1249 1250//Command to create/destroy block ACK 1251typedef struct { 1252 FWCmdHdr CmdHdr; 1253 uint32_t ActionType; 1254 union 1255 { 1256 // information required to create BA Stream... 1257 BASTREAM_CREATE_STREAM CreateParams; 1258 // update starting/new sequence number etc. 1259 BASTREAM_UPDATE_STREAM UpdtSeqNum; 1260 // destroy an existing stream... 1261 BASTREAM_STREAM_INFO DestroyParams; 1262 // destroy an existing stream... 1263 BASTREAM_STREAM_INFO FlushParams; 1264 }__packed BaInfo; 1265}__packed HostCmd_FW_BASTREAM; 1266 1267// Define data structure for HostCmd_CMD_GET_WATCHDOG_BITMAP 1268typedef struct { 1269 FWCmdHdr CmdHdr; 1270 uint8_t Watchdogbitmap; // for SW/BA 1271} __packed HostCmd_FW_GET_WATCHDOG_BITMAP; 1272 1273 1274 1275// Define data structure for HostCmd_CMD_SET_REGION_POWER 1276typedef struct { 1277 FWCmdHdr CmdHdr; 1278 uint16_t MaxPowerLevel; 1279 uint16_t Reserved; 1280} __packed HostCmd_DS_SET_REGION_POWER; 1281 1282// Define data structure for HostCmd_CMD_SET_RATE_ADAPT_MODE 1283typedef struct { 1284 FWCmdHdr CmdHdr; 1285 uint16_t Action; 1286 uint16_t RateAdaptMode; 1287} __packed HostCmd_DS_SET_RATE_ADAPT_MODE; 1288 1289// Define data structure for HostCmd_CMD_SET_LINKADAPT_CS_MODE 1290typedef struct { 1291 FWCmdHdr CmdHdr; 1292 uint16_t Action; 1293 uint16_t CSMode; 1294} __packed HostCmd_DS_SET_LINKADAPT_CS_MODE; 1295 1296typedef struct { 1297 FWCmdHdr CmdHdr; 1298 uint32_t NProtectFlag; 1299} __packed HostCmd_FW_SET_N_PROTECT_FLAG; 1300 1301typedef struct { 1302 FWCmdHdr CmdHdr; 1303 uint8_t NProtectOpMode; 1304} __packed HostCmd_FW_SET_N_PROTECT_OPMODE; 1305 1306typedef struct { 1307 FWCmdHdr CmdHdr; 1308 uint8_t OptLevel; 1309} __packed HostCmd_FW_SET_OPTIMIZATION_LEVEL; 1310 1311typedef struct { 1312 FWCmdHdr CmdHdr; 1313 uint8_t annex; 1314 uint8_t index; 1315 uint8_t len; 1316 uint8_t Reserverd; 1317#define CAL_TBL_SIZE 160 1318 uint8_t calTbl[CAL_TBL_SIZE]; 1319} __packed HostCmd_FW_GET_CALTABLE; 1320 1321typedef struct { 1322 FWCmdHdr CmdHdr; 1323 uint8_t Addr[6]; 1324 uint8_t Enable; 1325 uint8_t Mode; 1326} __packed HostCmd_FW_SET_MIMOPSHT; 1327 1328#define MAX_BEACON_SIZE 1024 1329typedef struct { 1330 FWCmdHdr CmdHdr; 1331 uint16_t Bcnlen; 1332 uint8_t Reserverd[2]; 1333 uint8_t Bcn[MAX_BEACON_SIZE]; 1334} __packed HostCmd_FW_GET_BEACON; 1335 1336typedef struct { 1337 FWCmdHdr CmdHdr; 1338 uint8_t NumberOfPowersave; 1339 uint8_t reserved; 1340} __packed HostCmd_SET_POWERSAVESTATION; 1341 1342typedef struct { 1343 FWCmdHdr CmdHdr; 1344 uint16_t Aid; 1345 uint32_t Set; 1346 uint8_t reserved; 1347} __packed HostCmd_SET_TIM; 1348 1349typedef struct { 1350 FWCmdHdr CmdHdr; 1351 uint8_t TrafficMap[251]; 1352 uint8_t reserved; 1353} __packed HostCmd_GET_TIM; 1354 1355typedef struct { 1356 FWCmdHdr CmdHdr; 1357 uint8_t MacAddr[6]; 1358 uint8_t TID; 1359 uint16_t SeqNo; 1360 uint8_t reserved; 1361} __packed HostCmd_GET_SEQNO; 1362 1363typedef struct { 1364 FWCmdHdr CmdHdr; 1365 uint32_t Enable; //0 -- Disbale. or 1 -- Enable. 1366} __packed HostCmd_DWDS_ENABLE; 1367 1368typedef struct { 1369 FWCmdHdr CmdHdr; 1370 uint16_t Action; /* 0: Get. 1:Set */ 1371 uint32_t Option; /* 0: default. 1:Aggressive */ 1372 uint32_t Threshold; /* Range 0-200, default 8 */ 1373}__packed HostCmd_FW_AMPDU_RETRY_RATEDROP_MODE; 1374 1375typedef struct { 1376 FWCmdHdr CmdHdr; 1377 uint32_t Enable; /* 0 -- Disable. or 1 -- Enable */ 1378}__packed HostCmd_CFEND_ENABLE; 1379#endif /* _MWL_HALREG_H_ */ 1380