if_mwl.c revision 287197
1193240Ssam/*- 2193240Ssam * Copyright (c) 2007-2009 Sam Leffler, Errno Consulting 3193240Ssam * Copyright (c) 2007-2008 Marvell Semiconductor, Inc. 4193240Ssam * All rights reserved. 5193240Ssam * 6193240Ssam * Redistribution and use in source and binary forms, with or without 7193240Ssam * modification, are permitted provided that the following conditions 8193240Ssam * are met: 9193240Ssam * 1. Redistributions of source code must retain the above copyright 10193240Ssam * notice, this list of conditions and the following disclaimer, 11193240Ssam * without modification. 12193240Ssam * 2. Redistributions in binary form must reproduce at minimum a disclaimer 13193240Ssam * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 14193240Ssam * redistribution must be conditioned upon including a substantially 15193240Ssam * similar Disclaimer requirement for further binary redistribution. 16193240Ssam * 17193240Ssam * NO WARRANTY 18193240Ssam * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19193240Ssam * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20193240Ssam * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 21193240Ssam * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 22193240Ssam * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 23193240Ssam * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24193240Ssam * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25193240Ssam * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 26193240Ssam * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27193240Ssam * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 28193240Ssam * THE POSSIBILITY OF SUCH DAMAGES. 29193240Ssam */ 30193240Ssam 31193240Ssam#include <sys/cdefs.h> 32193240Ssam__FBSDID("$FreeBSD: head/sys/dev/mwl/if_mwl.c 287197 2015-08-27 08:56:39Z glebius $"); 33193240Ssam 34193240Ssam/* 35193240Ssam * Driver for the Marvell 88W8363 Wireless LAN controller. 36193240Ssam */ 37193240Ssam 38193240Ssam#include "opt_inet.h" 39193240Ssam#include "opt_mwl.h" 40234367Sadrian#include "opt_wlan.h" 41193240Ssam 42193240Ssam#include <sys/param.h> 43193240Ssam#include <sys/systm.h> 44193240Ssam#include <sys/sysctl.h> 45193240Ssam#include <sys/mbuf.h> 46193240Ssam#include <sys/malloc.h> 47193240Ssam#include <sys/lock.h> 48193240Ssam#include <sys/mutex.h> 49193240Ssam#include <sys/kernel.h> 50193240Ssam#include <sys/socket.h> 51193240Ssam#include <sys/sockio.h> 52193240Ssam#include <sys/errno.h> 53193240Ssam#include <sys/callout.h> 54193240Ssam#include <sys/bus.h> 55193240Ssam#include <sys/endian.h> 56193240Ssam#include <sys/kthread.h> 57193240Ssam#include <sys/taskqueue.h> 58193240Ssam 59193240Ssam#include <machine/bus.h> 60193240Ssam 61193240Ssam#include <net/if.h> 62257176Sglebius#include <net/if_var.h> 63193240Ssam#include <net/if_dl.h> 64193240Ssam#include <net/if_media.h> 65193240Ssam#include <net/if_types.h> 66193240Ssam#include <net/if_arp.h> 67193240Ssam#include <net/ethernet.h> 68193240Ssam#include <net/if_llc.h> 69193240Ssam 70193240Ssam#include <net/bpf.h> 71193240Ssam 72193240Ssam#include <net80211/ieee80211_var.h> 73193240Ssam#include <net80211/ieee80211_regdomain.h> 74193240Ssam 75193240Ssam#ifdef INET 76193240Ssam#include <netinet/in.h> 77193240Ssam#include <netinet/if_ether.h> 78193240Ssam#endif /* INET */ 79193240Ssam 80193240Ssam#include <dev/mwl/if_mwlvar.h> 81193240Ssam#include <dev/mwl/mwldiag.h> 82193240Ssam 83193240Ssam/* idiomatic shorthands: MS = mask+shift, SM = shift+mask */ 84193240Ssam#define MS(v,x) (((v) & x) >> x##_S) 85193240Ssam#define SM(v,x) (((v) << x##_S) & x) 86193240Ssam 87193240Ssamstatic struct ieee80211vap *mwl_vap_create(struct ieee80211com *, 88228621Sbschmidt const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 89228621Sbschmidt const uint8_t [IEEE80211_ADDR_LEN], 90228621Sbschmidt const uint8_t [IEEE80211_ADDR_LEN]); 91193240Ssamstatic void mwl_vap_delete(struct ieee80211vap *); 92193240Ssamstatic int mwl_setupdma(struct mwl_softc *); 93193240Ssamstatic int mwl_hal_reset(struct mwl_softc *sc); 94287197Sglebiusstatic int mwl_init(struct mwl_softc *); 95287197Sglebiusstatic void mwl_parent(struct ieee80211com *); 96193240Ssamstatic int mwl_reset(struct ieee80211vap *, u_long); 97287197Sglebiusstatic void mwl_stop(struct mwl_softc *); 98287197Sglebiusstatic void mwl_start(struct mwl_softc *); 99287197Sglebiusstatic int mwl_transmit(struct ieee80211com *, struct mbuf *); 100193240Ssamstatic int mwl_raw_xmit(struct ieee80211_node *, struct mbuf *, 101193240Ssam const struct ieee80211_bpf_params *); 102193240Ssamstatic int mwl_media_change(struct ifnet *); 103199559Sjhbstatic void mwl_watchdog(void *); 104287197Sglebiusstatic int mwl_ioctl(struct ieee80211com *, u_long, void *); 105193240Ssamstatic void mwl_radar_proc(void *, int); 106193240Ssamstatic void mwl_chanswitch_proc(void *, int); 107193240Ssamstatic void mwl_bawatchdog_proc(void *, int); 108193240Ssamstatic int mwl_key_alloc(struct ieee80211vap *, 109193240Ssam struct ieee80211_key *, 110193240Ssam ieee80211_keyix *, ieee80211_keyix *); 111193240Ssamstatic int mwl_key_delete(struct ieee80211vap *, 112193240Ssam const struct ieee80211_key *); 113193240Ssamstatic int mwl_key_set(struct ieee80211vap *, const struct ieee80211_key *, 114193240Ssam const uint8_t mac[IEEE80211_ADDR_LEN]); 115193240Ssamstatic int mwl_mode_init(struct mwl_softc *); 116283540Sglebiusstatic void mwl_update_mcast(struct ieee80211com *); 117283540Sglebiusstatic void mwl_update_promisc(struct ieee80211com *); 118283540Sglebiusstatic void mwl_updateslot(struct ieee80211com *); 119193240Ssamstatic int mwl_beacon_setup(struct ieee80211vap *); 120193240Ssamstatic void mwl_beacon_update(struct ieee80211vap *, int); 121193240Ssam#ifdef MWL_HOST_PS_SUPPORT 122193240Ssamstatic void mwl_update_ps(struct ieee80211vap *, int); 123193240Ssamstatic int mwl_set_tim(struct ieee80211_node *, int); 124193240Ssam#endif 125193240Ssamstatic int mwl_dma_setup(struct mwl_softc *); 126193240Ssamstatic void mwl_dma_cleanup(struct mwl_softc *); 127193240Ssamstatic struct ieee80211_node *mwl_node_alloc(struct ieee80211vap *, 128193240Ssam const uint8_t [IEEE80211_ADDR_LEN]); 129193240Ssamstatic void mwl_node_cleanup(struct ieee80211_node *); 130193240Ssamstatic void mwl_node_drain(struct ieee80211_node *); 131193240Ssamstatic void mwl_node_getsignal(const struct ieee80211_node *, 132193240Ssam int8_t *, int8_t *); 133193240Ssamstatic void mwl_node_getmimoinfo(const struct ieee80211_node *, 134193240Ssam struct ieee80211_mimo_info *); 135193240Ssamstatic int mwl_rxbuf_init(struct mwl_softc *, struct mwl_rxbuf *); 136193240Ssamstatic void mwl_rx_proc(void *, int); 137193240Ssamstatic void mwl_txq_init(struct mwl_softc *sc, struct mwl_txq *, int); 138193240Ssamstatic int mwl_tx_setup(struct mwl_softc *, int, int); 139193240Ssamstatic int mwl_wme_update(struct ieee80211com *); 140193240Ssamstatic void mwl_tx_cleanupq(struct mwl_softc *, struct mwl_txq *); 141193240Ssamstatic void mwl_tx_cleanup(struct mwl_softc *); 142193240Ssamstatic uint16_t mwl_calcformat(uint8_t rate, const struct ieee80211_node *); 143193240Ssamstatic int mwl_tx_start(struct mwl_softc *, struct ieee80211_node *, 144193240Ssam struct mwl_txbuf *, struct mbuf *); 145193240Ssamstatic void mwl_tx_proc(void *, int); 146193240Ssamstatic int mwl_chan_set(struct mwl_softc *, struct ieee80211_channel *); 147193240Ssamstatic void mwl_draintxq(struct mwl_softc *); 148193240Ssamstatic void mwl_cleartxq(struct mwl_softc *, struct ieee80211vap *); 149195377Ssamstatic int mwl_recv_action(struct ieee80211_node *, 150195377Ssam const struct ieee80211_frame *, 151193240Ssam const uint8_t *, const uint8_t *); 152193240Ssamstatic int mwl_addba_request(struct ieee80211_node *, 153193240Ssam struct ieee80211_tx_ampdu *, int dialogtoken, 154193240Ssam int baparamset, int batimeout); 155193240Ssamstatic int mwl_addba_response(struct ieee80211_node *, 156193240Ssam struct ieee80211_tx_ampdu *, int status, 157193240Ssam int baparamset, int batimeout); 158193240Ssamstatic void mwl_addba_stop(struct ieee80211_node *, 159193240Ssam struct ieee80211_tx_ampdu *); 160193240Ssamstatic int mwl_startrecv(struct mwl_softc *); 161193240Ssamstatic MWL_HAL_APMODE mwl_getapmode(const struct ieee80211vap *, 162193240Ssam struct ieee80211_channel *); 163193240Ssamstatic int mwl_setapmode(struct ieee80211vap *, struct ieee80211_channel*); 164193240Ssamstatic void mwl_scan_start(struct ieee80211com *); 165193240Ssamstatic void mwl_scan_end(struct ieee80211com *); 166193240Ssamstatic void mwl_set_channel(struct ieee80211com *); 167193240Ssamstatic int mwl_peerstadb(struct ieee80211_node *, 168193240Ssam int aid, int staid, MWL_HAL_PEERINFO *pi); 169193240Ssamstatic int mwl_localstadb(struct ieee80211vap *); 170193240Ssamstatic int mwl_newstate(struct ieee80211vap *, enum ieee80211_state, int); 171193240Ssamstatic int allocstaid(struct mwl_softc *sc, int aid); 172193240Ssamstatic void delstaid(struct mwl_softc *sc, int staid); 173193240Ssamstatic void mwl_newassoc(struct ieee80211_node *, int); 174193240Ssamstatic void mwl_agestations(void *); 175193240Ssamstatic int mwl_setregdomain(struct ieee80211com *, 176193240Ssam struct ieee80211_regdomain *, int, 177193240Ssam struct ieee80211_channel []); 178193240Ssamstatic void mwl_getradiocaps(struct ieee80211com *, int, int *, 179193240Ssam struct ieee80211_channel []); 180193240Ssamstatic int mwl_getchannels(struct mwl_softc *); 181193240Ssam 182193240Ssamstatic void mwl_sysctlattach(struct mwl_softc *); 183193240Ssamstatic void mwl_announce(struct mwl_softc *); 184193240Ssam 185193240SsamSYSCTL_NODE(_hw, OID_AUTO, mwl, CTLFLAG_RD, 0, "Marvell driver parameters"); 186193240Ssam 187193240Ssamstatic int mwl_rxdesc = MWL_RXDESC; /* # rx desc's to allocate */ 188193240SsamSYSCTL_INT(_hw_mwl, OID_AUTO, rxdesc, CTLFLAG_RW, &mwl_rxdesc, 189193240Ssam 0, "rx descriptors allocated"); 190193240Ssamstatic int mwl_rxbuf = MWL_RXBUF; /* # rx buffers to allocate */ 191267992ShselaskySYSCTL_INT(_hw_mwl, OID_AUTO, rxbuf, CTLFLAG_RWTUN, &mwl_rxbuf, 192193240Ssam 0, "rx buffers allocated"); 193193240Ssamstatic int mwl_txbuf = MWL_TXBUF; /* # tx buffers to allocate */ 194267992ShselaskySYSCTL_INT(_hw_mwl, OID_AUTO, txbuf, CTLFLAG_RWTUN, &mwl_txbuf, 195193240Ssam 0, "tx buffers allocated"); 196193240Ssamstatic int mwl_txcoalesce = 8; /* # tx packets to q before poking f/w*/ 197267992ShselaskySYSCTL_INT(_hw_mwl, OID_AUTO, txcoalesce, CTLFLAG_RWTUN, &mwl_txcoalesce, 198193240Ssam 0, "tx buffers to send at once"); 199193240Ssamstatic int mwl_rxquota = MWL_RXBUF; /* # max buffers to process */ 200267992ShselaskySYSCTL_INT(_hw_mwl, OID_AUTO, rxquota, CTLFLAG_RWTUN, &mwl_rxquota, 201193240Ssam 0, "max rx buffers to process per interrupt"); 202193240Ssamstatic int mwl_rxdmalow = 3; /* # min buffers for wakeup */ 203267992ShselaskySYSCTL_INT(_hw_mwl, OID_AUTO, rxdmalow, CTLFLAG_RWTUN, &mwl_rxdmalow, 204193240Ssam 0, "min free rx buffers before restarting traffic"); 205193240Ssam 206193240Ssam#ifdef MWL_DEBUG 207193240Ssamstatic int mwl_debug = 0; 208267992ShselaskySYSCTL_INT(_hw_mwl, OID_AUTO, debug, CTLFLAG_RWTUN, &mwl_debug, 209193240Ssam 0, "control debugging printfs"); 210193240Ssamenum { 211193240Ssam MWL_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 212193240Ssam MWL_DEBUG_XMIT_DESC = 0x00000002, /* xmit descriptors */ 213193240Ssam MWL_DEBUG_RECV = 0x00000004, /* basic recv operation */ 214193240Ssam MWL_DEBUG_RECV_DESC = 0x00000008, /* recv descriptors */ 215193240Ssam MWL_DEBUG_RESET = 0x00000010, /* reset processing */ 216193240Ssam MWL_DEBUG_BEACON = 0x00000020, /* beacon handling */ 217193240Ssam MWL_DEBUG_INTR = 0x00000040, /* ISR */ 218193240Ssam MWL_DEBUG_TX_PROC = 0x00000080, /* tx ISR proc */ 219193240Ssam MWL_DEBUG_RX_PROC = 0x00000100, /* rx ISR proc */ 220193240Ssam MWL_DEBUG_KEYCACHE = 0x00000200, /* key cache management */ 221193240Ssam MWL_DEBUG_STATE = 0x00000400, /* 802.11 state transitions */ 222193240Ssam MWL_DEBUG_NODE = 0x00000800, /* node management */ 223193240Ssam MWL_DEBUG_RECV_ALL = 0x00001000, /* trace all frames (beacons) */ 224193240Ssam MWL_DEBUG_TSO = 0x00002000, /* TSO processing */ 225193240Ssam MWL_DEBUG_AMPDU = 0x00004000, /* BA stream handling */ 226193240Ssam MWL_DEBUG_ANY = 0xffffffff 227193240Ssam}; 228193240Ssam#define IS_BEACON(wh) \ 229193240Ssam ((wh->i_fc[0] & (IEEE80211_FC0_TYPE_MASK|IEEE80211_FC0_SUBTYPE_MASK)) == \ 230193240Ssam (IEEE80211_FC0_TYPE_MGT|IEEE80211_FC0_SUBTYPE_BEACON)) 231193240Ssam#define IFF_DUMPPKTS_RECV(sc, wh) \ 232287197Sglebius ((sc->sc_debug & MWL_DEBUG_RECV) && \ 233287197Sglebius ((sc->sc_debug & MWL_DEBUG_RECV_ALL) || !IS_BEACON(wh))) 234193240Ssam#define IFF_DUMPPKTS_XMIT(sc) \ 235287197Sglebius (sc->sc_debug & MWL_DEBUG_XMIT) 236287197Sglebius 237193240Ssam#define DPRINTF(sc, m, fmt, ...) do { \ 238193240Ssam if (sc->sc_debug & (m)) \ 239193240Ssam printf(fmt, __VA_ARGS__); \ 240193240Ssam} while (0) 241193240Ssam#define KEYPRINTF(sc, hk, mac) do { \ 242193240Ssam if (sc->sc_debug & MWL_DEBUG_KEYCACHE) \ 243193240Ssam mwl_keyprint(sc, __func__, hk, mac); \ 244193240Ssam} while (0) 245193240Ssamstatic void mwl_printrxbuf(const struct mwl_rxbuf *bf, u_int ix); 246193240Ssamstatic void mwl_printtxbuf(const struct mwl_txbuf *bf, u_int qnum, u_int ix); 247193240Ssam#else 248287197Sglebius#define IFF_DUMPPKTS_RECV(sc, wh) 0 249287197Sglebius#define IFF_DUMPPKTS_XMIT(sc) 0 250287197Sglebius#define DPRINTF(sc, m, fmt, ...) do { (void )sc; } while (0) 251287197Sglebius#define KEYPRINTF(sc, k, mac) do { (void )sc; } while (0) 252193240Ssam#endif 253193240Ssam 254227293Sedstatic MALLOC_DEFINE(M_MWLDEV, "mwldev", "mwl driver dma buffers"); 255193240Ssam 256193240Ssam/* 257193240Ssam * Each packet has fixed front matter: a 2-byte length 258193240Ssam * of the payload, followed by a 4-address 802.11 header 259193240Ssam * (regardless of the actual header and always w/o any 260193240Ssam * QoS header). The payload then follows. 261193240Ssam */ 262193240Ssamstruct mwltxrec { 263193240Ssam uint16_t fwlen; 264193240Ssam struct ieee80211_frame_addr4 wh; 265193240Ssam} __packed; 266193240Ssam 267193240Ssam/* 268193240Ssam * Read/Write shorthands for accesses to BAR 0. Note 269193240Ssam * that all BAR 1 operations are done in the "hal" and 270193240Ssam * there should be no reference to them here. 271193240Ssam */ 272259869Sdim#ifdef MWL_DEBUG 273193240Ssamstatic __inline uint32_t 274193240SsamRD4(struct mwl_softc *sc, bus_size_t off) 275193240Ssam{ 276193240Ssam return bus_space_read_4(sc->sc_io0t, sc->sc_io0h, off); 277193240Ssam} 278259869Sdim#endif 279193240Ssam 280193240Ssamstatic __inline void 281193240SsamWR4(struct mwl_softc *sc, bus_size_t off, uint32_t val) 282193240Ssam{ 283193240Ssam bus_space_write_4(sc->sc_io0t, sc->sc_io0h, off, val); 284193240Ssam} 285193240Ssam 286193240Ssamint 287193240Ssammwl_attach(uint16_t devid, struct mwl_softc *sc) 288193240Ssam{ 289287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 290193240Ssam struct mwl_hal *mh; 291193240Ssam int error = 0; 292193240Ssam 293193240Ssam DPRINTF(sc, MWL_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid); 294193240Ssam 295234368Sadrian /* 296234368Sadrian * Setup the RX free list lock early, so it can be consistently 297234368Sadrian * removed. 298234368Sadrian */ 299234368Sadrian MWL_RXFREE_INIT(sc); 300234368Sadrian 301193240Ssam mh = mwl_hal_attach(sc->sc_dev, devid, 302193240Ssam sc->sc_io1h, sc->sc_io1t, sc->sc_dmat); 303193240Ssam if (mh == NULL) { 304287197Sglebius device_printf(sc->sc_dev, "unable to attach HAL\n"); 305193240Ssam error = EIO; 306193240Ssam goto bad; 307193240Ssam } 308193240Ssam sc->sc_mh = mh; 309193240Ssam /* 310193240Ssam * Load firmware so we can get setup. We arbitrarily 311193240Ssam * pick station firmware; we'll re-load firmware as 312193240Ssam * needed so setting up the wrong mode isn't a big deal. 313193240Ssam */ 314193240Ssam if (mwl_hal_fwload(mh, NULL) != 0) { 315287197Sglebius device_printf(sc->sc_dev, "unable to setup builtin firmware\n"); 316193240Ssam error = EIO; 317193240Ssam goto bad1; 318193240Ssam } 319193240Ssam if (mwl_hal_gethwspecs(mh, &sc->sc_hwspecs) != 0) { 320287197Sglebius device_printf(sc->sc_dev, "unable to fetch h/w specs\n"); 321193240Ssam error = EIO; 322193240Ssam goto bad1; 323193240Ssam } 324193240Ssam error = mwl_getchannels(sc); 325193240Ssam if (error != 0) 326193240Ssam goto bad1; 327193240Ssam 328193240Ssam sc->sc_txantenna = 0; /* h/w default */ 329193240Ssam sc->sc_rxantenna = 0; /* h/w default */ 330193240Ssam sc->sc_invalid = 0; /* ready to go, enable int handling */ 331193240Ssam sc->sc_ageinterval = MWL_AGEINTERVAL; 332193240Ssam 333193240Ssam /* 334193240Ssam * Allocate tx+rx descriptors and populate the lists. 335193240Ssam * We immediately push the information to the firmware 336193240Ssam * as otherwise it gets upset. 337193240Ssam */ 338193240Ssam error = mwl_dma_setup(sc); 339193240Ssam if (error != 0) { 340287197Sglebius device_printf(sc->sc_dev, "failed to setup descriptors: %d\n", 341287197Sglebius error); 342193240Ssam goto bad1; 343193240Ssam } 344193240Ssam error = mwl_setupdma(sc); /* push to firmware */ 345193240Ssam if (error != 0) /* NB: mwl_setupdma prints msg */ 346193240Ssam goto bad1; 347193240Ssam 348283291Sjkim callout_init(&sc->sc_timer, 1); 349199559Sjhb callout_init_mtx(&sc->sc_watchdog, &sc->sc_mtx, 0); 350287197Sglebius mbufq_init(&sc->sc_snd, ifqmaxlen); 351193240Ssam 352193240Ssam sc->sc_tq = taskqueue_create("mwl_taskq", M_NOWAIT, 353193240Ssam taskqueue_thread_enqueue, &sc->sc_tq); 354193240Ssam taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, 355287197Sglebius "%s taskq", device_get_nameunit(sc->sc_dev)); 356193240Ssam 357193240Ssam TASK_INIT(&sc->sc_rxtask, 0, mwl_rx_proc, sc); 358193240Ssam TASK_INIT(&sc->sc_radartask, 0, mwl_radar_proc, sc); 359193240Ssam TASK_INIT(&sc->sc_chanswitchtask, 0, mwl_chanswitch_proc, sc); 360193240Ssam TASK_INIT(&sc->sc_bawatchdogtask, 0, mwl_bawatchdog_proc, sc); 361193240Ssam 362193240Ssam /* NB: insure BK queue is the lowest priority h/w queue */ 363193240Ssam if (!mwl_tx_setup(sc, WME_AC_BK, MWL_WME_AC_BK)) { 364287197Sglebius device_printf(sc->sc_dev, 365287197Sglebius "unable to setup xmit queue for %s traffic!\n", 366287197Sglebius ieee80211_wme_acnames[WME_AC_BK]); 367193240Ssam error = EIO; 368193240Ssam goto bad2; 369193240Ssam } 370193240Ssam if (!mwl_tx_setup(sc, WME_AC_BE, MWL_WME_AC_BE) || 371193240Ssam !mwl_tx_setup(sc, WME_AC_VI, MWL_WME_AC_VI) || 372193240Ssam !mwl_tx_setup(sc, WME_AC_VO, MWL_WME_AC_VO)) { 373193240Ssam /* 374193240Ssam * Not enough hardware tx queues to properly do WME; 375193240Ssam * just punt and assign them all to the same h/w queue. 376193240Ssam * We could do a better job of this if, for example, 377193240Ssam * we allocate queues when we switch from station to 378193240Ssam * AP mode. 379193240Ssam */ 380193240Ssam if (sc->sc_ac2q[WME_AC_VI] != NULL) 381193240Ssam mwl_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]); 382193240Ssam if (sc->sc_ac2q[WME_AC_BE] != NULL) 383193240Ssam mwl_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]); 384193240Ssam sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK]; 385193240Ssam sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK]; 386193240Ssam sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK]; 387193240Ssam } 388193240Ssam TASK_INIT(&sc->sc_txtask, 0, mwl_tx_proc, sc); 389193240Ssam 390283537Sglebius ic->ic_softc = sc; 391283527Sglebius ic->ic_name = device_get_nameunit(sc->sc_dev); 392193240Ssam /* XXX not right but it's not used anywhere important */ 393193240Ssam ic->ic_phytype = IEEE80211_T_OFDM; 394193240Ssam ic->ic_opmode = IEEE80211_M_STA; 395193240Ssam ic->ic_caps = 396193240Ssam IEEE80211_C_STA /* station mode supported */ 397193240Ssam | IEEE80211_C_HOSTAP /* hostap mode */ 398193240Ssam | IEEE80211_C_MONITOR /* monitor mode */ 399193240Ssam#if 0 400193240Ssam | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 401193240Ssam | IEEE80211_C_AHDEMO /* adhoc demo mode */ 402193240Ssam#endif 403195618Srpaulo | IEEE80211_C_MBSS /* mesh point link mode */ 404193240Ssam | IEEE80211_C_WDS /* WDS supported */ 405193240Ssam | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 406193240Ssam | IEEE80211_C_SHSLOT /* short slot time supported */ 407193240Ssam | IEEE80211_C_WME /* WME/WMM supported */ 408193240Ssam | IEEE80211_C_BURST /* xmit bursting supported */ 409193240Ssam | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 410193240Ssam | IEEE80211_C_BGSCAN /* capable of bg scanning */ 411193240Ssam | IEEE80211_C_TXFRAG /* handle tx frags */ 412193240Ssam | IEEE80211_C_TXPMGT /* capable of txpow mgt */ 413193240Ssam | IEEE80211_C_DFS /* DFS supported */ 414193240Ssam ; 415193240Ssam 416193240Ssam ic->ic_htcaps = 417193240Ssam IEEE80211_HTCAP_SMPS_ENA /* SM PS mode enabled */ 418193240Ssam | IEEE80211_HTCAP_CHWIDTH40 /* 40MHz channel width */ 419193240Ssam | IEEE80211_HTCAP_SHORTGI20 /* short GI in 20MHz */ 420193240Ssam | IEEE80211_HTCAP_SHORTGI40 /* short GI in 40MHz */ 421193240Ssam | IEEE80211_HTCAP_RXSTBC_2STREAM/* 1-2 spatial streams */ 422193240Ssam#if MWL_AGGR_SIZE == 7935 423193240Ssam | IEEE80211_HTCAP_MAXAMSDU_7935 /* max A-MSDU length */ 424193240Ssam#else 425193240Ssam | IEEE80211_HTCAP_MAXAMSDU_3839 /* max A-MSDU length */ 426193240Ssam#endif 427193240Ssam#if 0 428193240Ssam | IEEE80211_HTCAP_PSMP /* PSMP supported */ 429193240Ssam | IEEE80211_HTCAP_40INTOLERANT /* 40MHz intolerant */ 430193240Ssam#endif 431193240Ssam /* s/w capabilities */ 432193240Ssam | IEEE80211_HTC_HT /* HT operation */ 433193240Ssam | IEEE80211_HTC_AMPDU /* tx A-MPDU */ 434193240Ssam | IEEE80211_HTC_AMSDU /* tx A-MSDU */ 435193240Ssam | IEEE80211_HTC_SMPS /* SMPS available */ 436193240Ssam ; 437193240Ssam 438193240Ssam /* 439193240Ssam * Mark h/w crypto support. 440193240Ssam * XXX no way to query h/w support. 441193240Ssam */ 442193240Ssam ic->ic_cryptocaps |= IEEE80211_CRYPTO_WEP 443193240Ssam | IEEE80211_CRYPTO_AES_CCM 444193240Ssam | IEEE80211_CRYPTO_TKIP 445193240Ssam | IEEE80211_CRYPTO_TKIPMIC 446193240Ssam ; 447193240Ssam /* 448193240Ssam * Transmit requires space in the packet for a special 449193240Ssam * format transmit record and optional padding between 450193240Ssam * this record and the payload. Ask the net80211 layer 451193240Ssam * to arrange this when encapsulating packets so we can 452193240Ssam * add it efficiently. 453193240Ssam */ 454193240Ssam ic->ic_headroom = sizeof(struct mwltxrec) - 455193240Ssam sizeof(struct ieee80211_frame); 456193240Ssam 457287197Sglebius IEEE80211_ADDR_COPY(ic->ic_macaddr, sc->sc_hwspecs.macAddr); 458287197Sglebius 459193240Ssam /* call MI attach routine. */ 460287197Sglebius ieee80211_ifattach(ic); 461193240Ssam ic->ic_setregdomain = mwl_setregdomain; 462193240Ssam ic->ic_getradiocaps = mwl_getradiocaps; 463193240Ssam /* override default methods */ 464193240Ssam ic->ic_raw_xmit = mwl_raw_xmit; 465193240Ssam ic->ic_newassoc = mwl_newassoc; 466193240Ssam ic->ic_updateslot = mwl_updateslot; 467193240Ssam ic->ic_update_mcast = mwl_update_mcast; 468193240Ssam ic->ic_update_promisc = mwl_update_promisc; 469193240Ssam ic->ic_wme.wme_update = mwl_wme_update; 470287197Sglebius ic->ic_transmit = mwl_transmit; 471287197Sglebius ic->ic_ioctl = mwl_ioctl; 472287197Sglebius ic->ic_parent = mwl_parent; 473193240Ssam 474193240Ssam ic->ic_node_alloc = mwl_node_alloc; 475193240Ssam sc->sc_node_cleanup = ic->ic_node_cleanup; 476193240Ssam ic->ic_node_cleanup = mwl_node_cleanup; 477193240Ssam sc->sc_node_drain = ic->ic_node_drain; 478193240Ssam ic->ic_node_drain = mwl_node_drain; 479193240Ssam ic->ic_node_getsignal = mwl_node_getsignal; 480193240Ssam ic->ic_node_getmimoinfo = mwl_node_getmimoinfo; 481193240Ssam 482193240Ssam ic->ic_scan_start = mwl_scan_start; 483193240Ssam ic->ic_scan_end = mwl_scan_end; 484193240Ssam ic->ic_set_channel = mwl_set_channel; 485193240Ssam 486193240Ssam sc->sc_recv_action = ic->ic_recv_action; 487193240Ssam ic->ic_recv_action = mwl_recv_action; 488193240Ssam sc->sc_addba_request = ic->ic_addba_request; 489193240Ssam ic->ic_addba_request = mwl_addba_request; 490193240Ssam sc->sc_addba_response = ic->ic_addba_response; 491193240Ssam ic->ic_addba_response = mwl_addba_response; 492193240Ssam sc->sc_addba_stop = ic->ic_addba_stop; 493193240Ssam ic->ic_addba_stop = mwl_addba_stop; 494193240Ssam 495193240Ssam ic->ic_vap_create = mwl_vap_create; 496193240Ssam ic->ic_vap_delete = mwl_vap_delete; 497193240Ssam 498193240Ssam ieee80211_radiotap_attach(ic, 499193240Ssam &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th), 500193240Ssam MWL_TX_RADIOTAP_PRESENT, 501193240Ssam &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th), 502193240Ssam MWL_RX_RADIOTAP_PRESENT); 503193240Ssam /* 504193240Ssam * Setup dynamic sysctl's now that country code and 505193240Ssam * regdomain are available from the hal. 506193240Ssam */ 507193240Ssam mwl_sysctlattach(sc); 508193240Ssam 509193240Ssam if (bootverbose) 510193240Ssam ieee80211_announce(ic); 511193240Ssam mwl_announce(sc); 512193240Ssam return 0; 513193240Ssambad2: 514193240Ssam mwl_dma_cleanup(sc); 515193240Ssambad1: 516193240Ssam mwl_hal_detach(mh); 517193240Ssambad: 518234368Sadrian MWL_RXFREE_DESTROY(sc); 519193240Ssam sc->sc_invalid = 1; 520193240Ssam return error; 521193240Ssam} 522193240Ssam 523193240Ssamint 524193240Ssammwl_detach(struct mwl_softc *sc) 525193240Ssam{ 526287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 527193240Ssam 528287197Sglebius MWL_LOCK(sc); 529287197Sglebius mwl_stop(sc); 530287197Sglebius MWL_UNLOCK(sc); 531193240Ssam /* 532193240Ssam * NB: the order of these is important: 533193240Ssam * o call the 802.11 layer before detaching the hal to 534193240Ssam * insure callbacks into the driver to delete global 535193240Ssam * key cache entries can be handled 536193240Ssam * o reclaim the tx queue data structures after calling 537193240Ssam * the 802.11 layer as we'll get called back to reclaim 538193240Ssam * node state and potentially want to use them 539193240Ssam * o to cleanup the tx queues the hal is called, so detach 540193240Ssam * it last 541193240Ssam * Other than that, it's straightforward... 542193240Ssam */ 543193240Ssam ieee80211_ifdetach(ic); 544199559Sjhb callout_drain(&sc->sc_watchdog); 545193240Ssam mwl_dma_cleanup(sc); 546234368Sadrian MWL_RXFREE_DESTROY(sc); 547193240Ssam mwl_tx_cleanup(sc); 548193240Ssam mwl_hal_detach(sc->sc_mh); 549287197Sglebius mbufq_drain(&sc->sc_snd); 550193240Ssam 551193240Ssam return 0; 552193240Ssam} 553193240Ssam 554193240Ssam/* 555193240Ssam * MAC address handling for multiple BSS on the same radio. 556193240Ssam * The first vap uses the MAC address from the EEPROM. For 557193240Ssam * subsequent vap's we set the U/L bit (bit 1) in the MAC 558193240Ssam * address and use the next six bits as an index. 559193240Ssam */ 560193240Ssamstatic void 561193240Ssamassign_address(struct mwl_softc *sc, uint8_t mac[IEEE80211_ADDR_LEN], int clone) 562193240Ssam{ 563193240Ssam int i; 564193240Ssam 565193240Ssam if (clone && mwl_hal_ismbsscapable(sc->sc_mh)) { 566193240Ssam /* NB: we only do this if h/w supports multiple bssid */ 567193240Ssam for (i = 0; i < 32; i++) 568193240Ssam if ((sc->sc_bssidmask & (1<<i)) == 0) 569193240Ssam break; 570193240Ssam if (i != 0) 571193240Ssam mac[0] |= (i << 2)|0x2; 572193240Ssam } else 573193240Ssam i = 0; 574193240Ssam sc->sc_bssidmask |= 1<<i; 575193240Ssam if (i == 0) 576193240Ssam sc->sc_nbssid0++; 577193240Ssam} 578193240Ssam 579193240Ssamstatic void 580287197Sglebiusreclaim_address(struct mwl_softc *sc, const uint8_t mac[IEEE80211_ADDR_LEN]) 581193240Ssam{ 582193240Ssam int i = mac[0] >> 2; 583193240Ssam if (i != 0 || --sc->sc_nbssid0 == 0) 584193240Ssam sc->sc_bssidmask &= ~(1<<i); 585193240Ssam} 586193240Ssam 587193240Ssamstatic struct ieee80211vap * 588228621Sbschmidtmwl_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 589228621Sbschmidt enum ieee80211_opmode opmode, int flags, 590228621Sbschmidt const uint8_t bssid[IEEE80211_ADDR_LEN], 591228621Sbschmidt const uint8_t mac0[IEEE80211_ADDR_LEN]) 592193240Ssam{ 593287197Sglebius struct mwl_softc *sc = ic->ic_softc; 594193240Ssam struct mwl_hal *mh = sc->sc_mh; 595193240Ssam struct ieee80211vap *vap, *apvap; 596193240Ssam struct mwl_hal_vap *hvap; 597193240Ssam struct mwl_vap *mvp; 598193240Ssam uint8_t mac[IEEE80211_ADDR_LEN]; 599193240Ssam 600193240Ssam IEEE80211_ADDR_COPY(mac, mac0); 601193240Ssam switch (opmode) { 602193240Ssam case IEEE80211_M_HOSTAP: 603195618Srpaulo case IEEE80211_M_MBSS: 604193240Ssam if ((flags & IEEE80211_CLONE_MACADDR) == 0) 605193240Ssam assign_address(sc, mac, flags & IEEE80211_CLONE_BSSID); 606193240Ssam hvap = mwl_hal_newvap(mh, MWL_HAL_AP, mac); 607193240Ssam if (hvap == NULL) { 608193240Ssam if ((flags & IEEE80211_CLONE_MACADDR) == 0) 609193240Ssam reclaim_address(sc, mac); 610193240Ssam return NULL; 611193240Ssam } 612193240Ssam break; 613193240Ssam case IEEE80211_M_STA: 614193240Ssam if ((flags & IEEE80211_CLONE_MACADDR) == 0) 615193240Ssam assign_address(sc, mac, flags & IEEE80211_CLONE_BSSID); 616193240Ssam hvap = mwl_hal_newvap(mh, MWL_HAL_STA, mac); 617193240Ssam if (hvap == NULL) { 618193240Ssam if ((flags & IEEE80211_CLONE_MACADDR) == 0) 619193240Ssam reclaim_address(sc, mac); 620193240Ssam return NULL; 621193240Ssam } 622193240Ssam /* no h/w beacon miss support; always use s/w */ 623193240Ssam flags |= IEEE80211_CLONE_NOBEACONS; 624193240Ssam break; 625193240Ssam case IEEE80211_M_WDS: 626193240Ssam hvap = NULL; /* NB: we use associated AP vap */ 627193240Ssam if (sc->sc_napvaps == 0) 628193240Ssam return NULL; /* no existing AP vap */ 629193240Ssam break; 630193240Ssam case IEEE80211_M_MONITOR: 631193240Ssam hvap = NULL; 632193240Ssam break; 633193240Ssam case IEEE80211_M_IBSS: 634193240Ssam case IEEE80211_M_AHDEMO: 635193240Ssam default: 636193240Ssam return NULL; 637193240Ssam } 638193240Ssam 639287197Sglebius mvp = malloc(sizeof(struct mwl_vap), M_80211_VAP, M_WAITOK | M_ZERO); 640193240Ssam mvp->mv_hvap = hvap; 641193240Ssam if (opmode == IEEE80211_M_WDS) { 642193240Ssam /* 643193240Ssam * WDS vaps must have an associated AP vap; find one. 644193240Ssam * XXX not right. 645193240Ssam */ 646193240Ssam TAILQ_FOREACH(apvap, &ic->ic_vaps, iv_next) 647193240Ssam if (apvap->iv_opmode == IEEE80211_M_HOSTAP) { 648193240Ssam mvp->mv_ap_hvap = MWL_VAP(apvap)->mv_hvap; 649193240Ssam break; 650193240Ssam } 651193240Ssam KASSERT(mvp->mv_ap_hvap != NULL, ("no ap vap")); 652193240Ssam } 653193240Ssam vap = &mvp->mv_vap; 654287197Sglebius ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid); 655193240Ssam /* override with driver methods */ 656193240Ssam mvp->mv_newstate = vap->iv_newstate; 657193240Ssam vap->iv_newstate = mwl_newstate; 658193240Ssam vap->iv_max_keyix = 0; /* XXX */ 659193240Ssam vap->iv_key_alloc = mwl_key_alloc; 660193240Ssam vap->iv_key_delete = mwl_key_delete; 661193240Ssam vap->iv_key_set = mwl_key_set; 662193240Ssam#ifdef MWL_HOST_PS_SUPPORT 663195618Srpaulo if (opmode == IEEE80211_M_HOSTAP || opmode == IEEE80211_M_MBSS) { 664193240Ssam vap->iv_update_ps = mwl_update_ps; 665193240Ssam mvp->mv_set_tim = vap->iv_set_tim; 666193240Ssam vap->iv_set_tim = mwl_set_tim; 667193240Ssam } 668193240Ssam#endif 669193240Ssam vap->iv_reset = mwl_reset; 670193240Ssam vap->iv_update_beacon = mwl_beacon_update; 671193240Ssam 672193240Ssam /* override max aid so sta's cannot assoc when we're out of sta id's */ 673193240Ssam vap->iv_max_aid = MWL_MAXSTAID; 674193240Ssam /* override default A-MPDU rx parameters */ 675193240Ssam vap->iv_ampdu_rxmax = IEEE80211_HTCAP_MAXRXAMPDU_64K; 676193240Ssam vap->iv_ampdu_density = IEEE80211_HTCAP_MPDUDENSITY_4; 677193240Ssam 678193240Ssam /* complete setup */ 679287197Sglebius ieee80211_vap_attach(vap, mwl_media_change, ieee80211_media_status, 680287197Sglebius mac); 681193240Ssam 682193240Ssam switch (vap->iv_opmode) { 683193240Ssam case IEEE80211_M_HOSTAP: 684195618Srpaulo case IEEE80211_M_MBSS: 685193240Ssam case IEEE80211_M_STA: 686193240Ssam /* 687193240Ssam * Setup sta db entry for local address. 688193240Ssam */ 689193240Ssam mwl_localstadb(vap); 690195618Srpaulo if (vap->iv_opmode == IEEE80211_M_HOSTAP || 691195618Srpaulo vap->iv_opmode == IEEE80211_M_MBSS) 692193240Ssam sc->sc_napvaps++; 693193240Ssam else 694193240Ssam sc->sc_nstavaps++; 695193240Ssam break; 696193240Ssam case IEEE80211_M_WDS: 697193240Ssam sc->sc_nwdsvaps++; 698193240Ssam break; 699193240Ssam default: 700193240Ssam break; 701193240Ssam } 702193240Ssam /* 703193240Ssam * Setup overall operating mode. 704193240Ssam */ 705193240Ssam if (sc->sc_napvaps) 706193240Ssam ic->ic_opmode = IEEE80211_M_HOSTAP; 707193240Ssam else if (sc->sc_nstavaps) 708193240Ssam ic->ic_opmode = IEEE80211_M_STA; 709193240Ssam else 710193240Ssam ic->ic_opmode = opmode; 711193240Ssam 712193240Ssam return vap; 713193240Ssam} 714193240Ssam 715193240Ssamstatic void 716193240Ssammwl_vap_delete(struct ieee80211vap *vap) 717193240Ssam{ 718193240Ssam struct mwl_vap *mvp = MWL_VAP(vap); 719287197Sglebius struct mwl_softc *sc = vap->iv_ic->ic_softc; 720193240Ssam struct mwl_hal *mh = sc->sc_mh; 721193240Ssam struct mwl_hal_vap *hvap = mvp->mv_hvap; 722193240Ssam enum ieee80211_opmode opmode = vap->iv_opmode; 723193240Ssam 724193240Ssam /* XXX disallow ap vap delete if WDS still present */ 725287197Sglebius if (sc->sc_running) { 726193240Ssam /* quiesce h/w while we remove the vap */ 727193240Ssam mwl_hal_intrset(mh, 0); /* disable interrupts */ 728193240Ssam } 729193240Ssam ieee80211_vap_detach(vap); 730193240Ssam switch (opmode) { 731193240Ssam case IEEE80211_M_HOSTAP: 732195618Srpaulo case IEEE80211_M_MBSS: 733193240Ssam case IEEE80211_M_STA: 734193240Ssam KASSERT(hvap != NULL, ("no hal vap handle")); 735193240Ssam (void) mwl_hal_delstation(hvap, vap->iv_myaddr); 736193240Ssam mwl_hal_delvap(hvap); 737195618Srpaulo if (opmode == IEEE80211_M_HOSTAP || opmode == IEEE80211_M_MBSS) 738193240Ssam sc->sc_napvaps--; 739193240Ssam else 740193240Ssam sc->sc_nstavaps--; 741193240Ssam /* XXX don't do it for IEEE80211_CLONE_MACADDR */ 742193240Ssam reclaim_address(sc, vap->iv_myaddr); 743193240Ssam break; 744193240Ssam case IEEE80211_M_WDS: 745193240Ssam sc->sc_nwdsvaps--; 746193240Ssam break; 747193240Ssam default: 748193240Ssam break; 749193240Ssam } 750193240Ssam mwl_cleartxq(sc, vap); 751193240Ssam free(mvp, M_80211_VAP); 752287197Sglebius if (sc->sc_running) 753193240Ssam mwl_hal_intrset(mh, sc->sc_imask); 754193240Ssam} 755193240Ssam 756193240Ssamvoid 757193240Ssammwl_suspend(struct mwl_softc *sc) 758193240Ssam{ 759193240Ssam 760287197Sglebius MWL_LOCK(sc); 761287197Sglebius mwl_stop(sc); 762287197Sglebius MWL_UNLOCK(sc); 763193240Ssam} 764193240Ssam 765193240Ssamvoid 766193240Ssammwl_resume(struct mwl_softc *sc) 767193240Ssam{ 768287197Sglebius int error = EDOOFUS; 769193240Ssam 770287197Sglebius MWL_LOCK(sc); 771287197Sglebius if (sc->sc_ic.ic_nrunning > 0) 772287197Sglebius error = mwl_init(sc); 773287197Sglebius MWL_UNLOCK(sc); 774193240Ssam 775287197Sglebius if (error == 0) 776287197Sglebius ieee80211_start_all(&sc->sc_ic); /* start all vap's */ 777193240Ssam} 778193240Ssam 779193240Ssamvoid 780193240Ssammwl_shutdown(void *arg) 781193240Ssam{ 782193240Ssam struct mwl_softc *sc = arg; 783193240Ssam 784287197Sglebius MWL_LOCK(sc); 785287197Sglebius mwl_stop(sc); 786287197Sglebius MWL_UNLOCK(sc); 787193240Ssam} 788193240Ssam 789193240Ssam/* 790193240Ssam * Interrupt handler. Most of the actual processing is deferred. 791193240Ssam */ 792193240Ssamvoid 793193240Ssammwl_intr(void *arg) 794193240Ssam{ 795193240Ssam struct mwl_softc *sc = arg; 796193240Ssam struct mwl_hal *mh = sc->sc_mh; 797193240Ssam uint32_t status; 798193240Ssam 799193240Ssam if (sc->sc_invalid) { 800193240Ssam /* 801193240Ssam * The hardware is not ready/present, don't touch anything. 802193240Ssam * Note this can happen early on if the IRQ is shared. 803193240Ssam */ 804193240Ssam DPRINTF(sc, MWL_DEBUG_ANY, "%s: invalid; ignored\n", __func__); 805193240Ssam return; 806193240Ssam } 807193240Ssam /* 808193240Ssam * Figure out the reason(s) for the interrupt. 809193240Ssam */ 810193240Ssam mwl_hal_getisr(mh, &status); /* NB: clears ISR too */ 811193240Ssam if (status == 0) /* must be a shared irq */ 812193240Ssam return; 813193240Ssam 814193240Ssam DPRINTF(sc, MWL_DEBUG_INTR, "%s: status 0x%x imask 0x%x\n", 815193240Ssam __func__, status, sc->sc_imask); 816193240Ssam if (status & MACREG_A2HRIC_BIT_RX_RDY) 817193240Ssam taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 818193240Ssam if (status & MACREG_A2HRIC_BIT_TX_DONE) 819193240Ssam taskqueue_enqueue(sc->sc_tq, &sc->sc_txtask); 820193240Ssam if (status & MACREG_A2HRIC_BIT_BA_WATCHDOG) 821193240Ssam taskqueue_enqueue(sc->sc_tq, &sc->sc_bawatchdogtask); 822193240Ssam if (status & MACREG_A2HRIC_BIT_OPC_DONE) 823193240Ssam mwl_hal_cmddone(mh); 824193240Ssam if (status & MACREG_A2HRIC_BIT_MAC_EVENT) { 825193240Ssam ; 826193240Ssam } 827193240Ssam if (status & MACREG_A2HRIC_BIT_ICV_ERROR) { 828193240Ssam /* TKIP ICV error */ 829193240Ssam sc->sc_stats.mst_rx_badtkipicv++; 830193240Ssam } 831193240Ssam if (status & MACREG_A2HRIC_BIT_QUEUE_EMPTY) { 832193240Ssam /* 11n aggregation queue is empty, re-fill */ 833193240Ssam ; 834193240Ssam } 835193240Ssam if (status & MACREG_A2HRIC_BIT_QUEUE_FULL) { 836193240Ssam ; 837193240Ssam } 838193240Ssam if (status & MACREG_A2HRIC_BIT_RADAR_DETECT) { 839193240Ssam /* radar detected, process event */ 840193240Ssam taskqueue_enqueue(sc->sc_tq, &sc->sc_radartask); 841193240Ssam } 842193240Ssam if (status & MACREG_A2HRIC_BIT_CHAN_SWITCH) { 843193240Ssam /* DFS channel switch */ 844193240Ssam taskqueue_enqueue(sc->sc_tq, &sc->sc_chanswitchtask); 845193240Ssam } 846193240Ssam} 847193240Ssam 848193240Ssamstatic void 849193240Ssammwl_radar_proc(void *arg, int pending) 850193240Ssam{ 851193240Ssam struct mwl_softc *sc = arg; 852287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 853193240Ssam 854193240Ssam DPRINTF(sc, MWL_DEBUG_ANY, "%s: radar detected, pending %u\n", 855193240Ssam __func__, pending); 856193240Ssam 857193240Ssam sc->sc_stats.mst_radardetect++; 858195171Ssam /* XXX stop h/w BA streams? */ 859193240Ssam 860193240Ssam IEEE80211_LOCK(ic); 861193240Ssam ieee80211_dfs_notify_radar(ic, ic->ic_curchan); 862193240Ssam IEEE80211_UNLOCK(ic); 863193240Ssam} 864193240Ssam 865193240Ssamstatic void 866193240Ssammwl_chanswitch_proc(void *arg, int pending) 867193240Ssam{ 868193240Ssam struct mwl_softc *sc = arg; 869287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 870193240Ssam 871193240Ssam DPRINTF(sc, MWL_DEBUG_ANY, "%s: channel switch notice, pending %u\n", 872193240Ssam __func__, pending); 873193240Ssam 874193240Ssam IEEE80211_LOCK(ic); 875193240Ssam sc->sc_csapending = 0; 876193240Ssam ieee80211_csa_completeswitch(ic); 877193240Ssam IEEE80211_UNLOCK(ic); 878193240Ssam} 879193240Ssam 880193240Ssamstatic void 881193240Ssammwl_bawatchdog(const MWL_HAL_BASTREAM *sp) 882193240Ssam{ 883193240Ssam struct ieee80211_node *ni = sp->data[0]; 884193240Ssam 885193240Ssam /* send DELBA and drop the stream */ 886193240Ssam ieee80211_ampdu_stop(ni, sp->data[1], IEEE80211_REASON_UNSPECIFIED); 887193240Ssam} 888193240Ssam 889193240Ssamstatic void 890193240Ssammwl_bawatchdog_proc(void *arg, int pending) 891193240Ssam{ 892193240Ssam struct mwl_softc *sc = arg; 893193240Ssam struct mwl_hal *mh = sc->sc_mh; 894193240Ssam const MWL_HAL_BASTREAM *sp; 895193240Ssam uint8_t bitmap, n; 896193240Ssam 897193240Ssam sc->sc_stats.mst_bawatchdog++; 898193240Ssam 899193240Ssam if (mwl_hal_getwatchdogbitmap(mh, &bitmap) != 0) { 900193240Ssam DPRINTF(sc, MWL_DEBUG_AMPDU, 901193240Ssam "%s: could not get bitmap\n", __func__); 902193240Ssam sc->sc_stats.mst_bawatchdog_failed++; 903193240Ssam return; 904193240Ssam } 905193240Ssam DPRINTF(sc, MWL_DEBUG_AMPDU, "%s: bitmap 0x%x\n", __func__, bitmap); 906193240Ssam if (bitmap == 0xff) { 907193240Ssam n = 0; 908193240Ssam /* disable all ba streams */ 909193240Ssam for (bitmap = 0; bitmap < 8; bitmap++) { 910193240Ssam sp = mwl_hal_bastream_lookup(mh, bitmap); 911193240Ssam if (sp != NULL) { 912193240Ssam mwl_bawatchdog(sp); 913193240Ssam n++; 914193240Ssam } 915193240Ssam } 916193240Ssam if (n == 0) { 917193240Ssam DPRINTF(sc, MWL_DEBUG_AMPDU, 918193240Ssam "%s: no BA streams found\n", __func__); 919193240Ssam sc->sc_stats.mst_bawatchdog_empty++; 920193240Ssam } 921193240Ssam } else if (bitmap != 0xaa) { 922193240Ssam /* disable a single ba stream */ 923193240Ssam sp = mwl_hal_bastream_lookup(mh, bitmap); 924193240Ssam if (sp != NULL) { 925193240Ssam mwl_bawatchdog(sp); 926193240Ssam } else { 927193240Ssam DPRINTF(sc, MWL_DEBUG_AMPDU, 928193240Ssam "%s: no BA stream %d\n", __func__, bitmap); 929193240Ssam sc->sc_stats.mst_bawatchdog_notfound++; 930193240Ssam } 931193240Ssam } 932193240Ssam} 933193240Ssam 934193240Ssam/* 935193240Ssam * Convert net80211 channel to a HAL channel. 936193240Ssam */ 937193240Ssamstatic void 938193240Ssammwl_mapchan(MWL_HAL_CHANNEL *hc, const struct ieee80211_channel *chan) 939193240Ssam{ 940193240Ssam hc->channel = chan->ic_ieee; 941193240Ssam 942193240Ssam *(uint32_t *)&hc->channelFlags = 0; 943193240Ssam if (IEEE80211_IS_CHAN_2GHZ(chan)) 944193240Ssam hc->channelFlags.FreqBand = MWL_FREQ_BAND_2DOT4GHZ; 945193240Ssam else if (IEEE80211_IS_CHAN_5GHZ(chan)) 946193240Ssam hc->channelFlags.FreqBand = MWL_FREQ_BAND_5GHZ; 947193240Ssam if (IEEE80211_IS_CHAN_HT40(chan)) { 948193240Ssam hc->channelFlags.ChnlWidth = MWL_CH_40_MHz_WIDTH; 949193240Ssam if (IEEE80211_IS_CHAN_HT40U(chan)) 950193240Ssam hc->channelFlags.ExtChnlOffset = MWL_EXT_CH_ABOVE_CTRL_CH; 951193240Ssam else 952193240Ssam hc->channelFlags.ExtChnlOffset = MWL_EXT_CH_BELOW_CTRL_CH; 953193240Ssam } else 954193240Ssam hc->channelFlags.ChnlWidth = MWL_CH_20_MHz_WIDTH; 955193240Ssam /* XXX 10MHz channels */ 956193240Ssam} 957193240Ssam 958193240Ssam/* 959193240Ssam * Inform firmware of our tx/rx dma setup. The BAR 0 960193240Ssam * writes below are for compatibility with older firmware. 961193240Ssam * For current firmware we send this information with a 962193240Ssam * cmd block via mwl_hal_sethwdma. 963193240Ssam */ 964193240Ssamstatic int 965193240Ssammwl_setupdma(struct mwl_softc *sc) 966193240Ssam{ 967193240Ssam int error, i; 968193240Ssam 969193240Ssam sc->sc_hwdma.rxDescRead = sc->sc_rxdma.dd_desc_paddr; 970193240Ssam WR4(sc, sc->sc_hwspecs.rxDescRead, sc->sc_hwdma.rxDescRead); 971193240Ssam WR4(sc, sc->sc_hwspecs.rxDescWrite, sc->sc_hwdma.rxDescRead); 972193240Ssam 973195171Ssam for (i = 0; i < MWL_NUM_TX_QUEUES-MWL_NUM_ACK_QUEUES; i++) { 974193240Ssam struct mwl_txq *txq = &sc->sc_txq[i]; 975193240Ssam sc->sc_hwdma.wcbBase[i] = txq->dma.dd_desc_paddr; 976193240Ssam WR4(sc, sc->sc_hwspecs.wcbBase[i], sc->sc_hwdma.wcbBase[i]); 977193240Ssam } 978193240Ssam sc->sc_hwdma.maxNumTxWcb = mwl_txbuf; 979195171Ssam sc->sc_hwdma.maxNumWCB = MWL_NUM_TX_QUEUES-MWL_NUM_ACK_QUEUES; 980193240Ssam 981193240Ssam error = mwl_hal_sethwdma(sc->sc_mh, &sc->sc_hwdma); 982193240Ssam if (error != 0) { 983193240Ssam device_printf(sc->sc_dev, 984193240Ssam "unable to setup tx/rx dma; hal status %u\n", error); 985193240Ssam /* XXX */ 986193240Ssam } 987193240Ssam return error; 988193240Ssam} 989193240Ssam 990193240Ssam/* 991193240Ssam * Inform firmware of tx rate parameters. 992193240Ssam * Called after a channel change. 993193240Ssam */ 994193240Ssamstatic int 995193240Ssammwl_setcurchanrates(struct mwl_softc *sc) 996193240Ssam{ 997287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 998193240Ssam const struct ieee80211_rateset *rs; 999193240Ssam MWL_HAL_TXRATE rates; 1000193240Ssam 1001193240Ssam memset(&rates, 0, sizeof(rates)); 1002193240Ssam rs = ieee80211_get_suprates(ic, ic->ic_curchan); 1003193240Ssam /* rate used to send management frames */ 1004193240Ssam rates.MgtRate = rs->rs_rates[0] & IEEE80211_RATE_VAL; 1005193240Ssam /* rate used to send multicast frames */ 1006193240Ssam rates.McastRate = rates.MgtRate; 1007193240Ssam 1008193240Ssam return mwl_hal_settxrate_auto(sc->sc_mh, &rates); 1009193240Ssam} 1010193240Ssam 1011193240Ssam/* 1012193240Ssam * Inform firmware of tx rate parameters. Called whenever 1013193240Ssam * user-settable params change and after a channel change. 1014193240Ssam */ 1015193240Ssamstatic int 1016193240Ssammwl_setrates(struct ieee80211vap *vap) 1017193240Ssam{ 1018193240Ssam struct mwl_vap *mvp = MWL_VAP(vap); 1019193240Ssam struct ieee80211_node *ni = vap->iv_bss; 1020193240Ssam const struct ieee80211_txparam *tp = ni->ni_txparms; 1021193240Ssam MWL_HAL_TXRATE rates; 1022193240Ssam 1023193240Ssam KASSERT(vap->iv_state == IEEE80211_S_RUN, ("state %d", vap->iv_state)); 1024193240Ssam 1025193240Ssam /* 1026193240Ssam * Update the h/w rate map. 1027193240Ssam * NB: 0x80 for MCS is passed through unchanged 1028193240Ssam */ 1029193240Ssam memset(&rates, 0, sizeof(rates)); 1030193240Ssam /* rate used to send management frames */ 1031193240Ssam rates.MgtRate = tp->mgmtrate; 1032193240Ssam /* rate used to send multicast frames */ 1033193240Ssam rates.McastRate = tp->mcastrate; 1034193240Ssam 1035193240Ssam /* while here calculate EAPOL fixed rate cookie */ 1036193240Ssam mvp->mv_eapolformat = htole16(mwl_calcformat(rates.MgtRate, ni)); 1037193240Ssam 1038195171Ssam return mwl_hal_settxrate(mvp->mv_hvap, 1039195171Ssam tp->ucastrate != IEEE80211_FIXED_RATE_NONE ? 1040195171Ssam RATE_FIXED : RATE_AUTO, &rates); 1041193240Ssam} 1042193240Ssam 1043193240Ssam/* 1044193240Ssam * Setup a fixed xmit rate cookie for EAPOL frames. 1045193240Ssam */ 1046193240Ssamstatic void 1047193240Ssammwl_seteapolformat(struct ieee80211vap *vap) 1048193240Ssam{ 1049193240Ssam struct mwl_vap *mvp = MWL_VAP(vap); 1050193240Ssam struct ieee80211_node *ni = vap->iv_bss; 1051193240Ssam enum ieee80211_phymode mode; 1052193240Ssam uint8_t rate; 1053193240Ssam 1054193240Ssam KASSERT(vap->iv_state == IEEE80211_S_RUN, ("state %d", vap->iv_state)); 1055193240Ssam 1056193240Ssam mode = ieee80211_chan2mode(ni->ni_chan); 1057193240Ssam /* 1058193240Ssam * Use legacy rates when operating a mixed HT+non-HT bss. 1059193240Ssam * NB: this may violate POLA for sta and wds vap's. 1060193240Ssam */ 1061193240Ssam if (mode == IEEE80211_MODE_11NA && 1062193656Ssam (vap->iv_flags_ht & IEEE80211_FHT_PUREN) == 0) 1063193240Ssam rate = vap->iv_txparms[IEEE80211_MODE_11A].mgmtrate; 1064193240Ssam else if (mode == IEEE80211_MODE_11NG && 1065193656Ssam (vap->iv_flags_ht & IEEE80211_FHT_PUREN) == 0) 1066193240Ssam rate = vap->iv_txparms[IEEE80211_MODE_11G].mgmtrate; 1067193240Ssam else 1068193240Ssam rate = vap->iv_txparms[mode].mgmtrate; 1069193240Ssam 1070193240Ssam mvp->mv_eapolformat = htole16(mwl_calcformat(rate, ni)); 1071193240Ssam} 1072193240Ssam 1073193240Ssam/* 1074193240Ssam * Map SKU+country code to region code for radar bin'ing. 1075193240Ssam */ 1076193240Ssamstatic int 1077193240Ssammwl_map2regioncode(const struct ieee80211_regdomain *rd) 1078193240Ssam{ 1079193240Ssam switch (rd->regdomain) { 1080193240Ssam case SKU_FCC: 1081193240Ssam case SKU_FCC3: 1082193240Ssam return DOMAIN_CODE_FCC; 1083193240Ssam case SKU_CA: 1084193240Ssam return DOMAIN_CODE_IC; 1085193240Ssam case SKU_ETSI: 1086193240Ssam case SKU_ETSI2: 1087193240Ssam case SKU_ETSI3: 1088193240Ssam if (rd->country == CTRY_SPAIN) 1089193240Ssam return DOMAIN_CODE_SPAIN; 1090193240Ssam if (rd->country == CTRY_FRANCE || rd->country == CTRY_FRANCE2) 1091193240Ssam return DOMAIN_CODE_FRANCE; 1092193240Ssam /* XXX force 1.3.1 radar type */ 1093193240Ssam return DOMAIN_CODE_ETSI_131; 1094193240Ssam case SKU_JAPAN: 1095193240Ssam return DOMAIN_CODE_MKK; 1096193240Ssam case SKU_ROW: 1097193240Ssam return DOMAIN_CODE_DGT; /* Taiwan */ 1098193240Ssam case SKU_APAC: 1099193240Ssam case SKU_APAC2: 1100193240Ssam case SKU_APAC3: 1101193240Ssam return DOMAIN_CODE_AUS; /* Australia */ 1102193240Ssam } 1103193240Ssam /* XXX KOREA? */ 1104193240Ssam return DOMAIN_CODE_FCC; /* XXX? */ 1105193240Ssam} 1106193240Ssam 1107193240Ssamstatic int 1108193240Ssammwl_hal_reset(struct mwl_softc *sc) 1109193240Ssam{ 1110287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 1111193240Ssam struct mwl_hal *mh = sc->sc_mh; 1112193240Ssam 1113193240Ssam mwl_hal_setantenna(mh, WL_ANTENNATYPE_RX, sc->sc_rxantenna); 1114193240Ssam mwl_hal_setantenna(mh, WL_ANTENNATYPE_TX, sc->sc_txantenna); 1115193240Ssam mwl_hal_setradio(mh, 1, WL_AUTO_PREAMBLE); 1116193240Ssam mwl_hal_setwmm(sc->sc_mh, (ic->ic_flags & IEEE80211_F_WME) != 0); 1117193240Ssam mwl_chan_set(sc, ic->ic_curchan); 1118195171Ssam /* NB: RF/RA performance tuned for indoor mode */ 1119195171Ssam mwl_hal_setrateadaptmode(mh, 0); 1120193240Ssam mwl_hal_setoptimizationlevel(mh, 1121193240Ssam (ic->ic_flags & IEEE80211_F_BURST) != 0); 1122193240Ssam 1123193240Ssam mwl_hal_setregioncode(mh, mwl_map2regioncode(&ic->ic_regdomain)); 1124193240Ssam 1125195171Ssam mwl_hal_setaggampduratemode(mh, 1, 80); /* XXX */ 1126195171Ssam mwl_hal_setcfend(mh, 0); /* XXX */ 1127195171Ssam 1128193240Ssam return 1; 1129193240Ssam} 1130193240Ssam 1131193240Ssamstatic int 1132287197Sglebiusmwl_init(struct mwl_softc *sc) 1133193240Ssam{ 1134193240Ssam struct mwl_hal *mh = sc->sc_mh; 1135193240Ssam int error = 0; 1136193240Ssam 1137193240Ssam MWL_LOCK_ASSERT(sc); 1138193240Ssam 1139193240Ssam /* 1140193240Ssam * Stop anything previously setup. This is safe 1141193240Ssam * whether this is the first time through or not. 1142193240Ssam */ 1143287197Sglebius mwl_stop(sc); 1144193240Ssam 1145193240Ssam /* 1146193240Ssam * Push vap-independent state to the firmware. 1147193240Ssam */ 1148193240Ssam if (!mwl_hal_reset(sc)) { 1149287197Sglebius device_printf(sc->sc_dev, "unable to reset hardware\n"); 1150193240Ssam return EIO; 1151193240Ssam } 1152193240Ssam 1153193240Ssam /* 1154193240Ssam * Setup recv (once); transmit is already good to go. 1155193240Ssam */ 1156193240Ssam error = mwl_startrecv(sc); 1157193240Ssam if (error != 0) { 1158287197Sglebius device_printf(sc->sc_dev, "unable to start recv logic\n"); 1159193240Ssam return error; 1160193240Ssam } 1161193240Ssam 1162193240Ssam /* 1163193240Ssam * Enable interrupts. 1164193240Ssam */ 1165193240Ssam sc->sc_imask = MACREG_A2HRIC_BIT_RX_RDY 1166193240Ssam | MACREG_A2HRIC_BIT_TX_DONE 1167193240Ssam | MACREG_A2HRIC_BIT_OPC_DONE 1168193240Ssam#if 0 1169193240Ssam | MACREG_A2HRIC_BIT_MAC_EVENT 1170193240Ssam#endif 1171193240Ssam | MACREG_A2HRIC_BIT_ICV_ERROR 1172193240Ssam | MACREG_A2HRIC_BIT_RADAR_DETECT 1173193240Ssam | MACREG_A2HRIC_BIT_CHAN_SWITCH 1174193240Ssam#if 0 1175193240Ssam | MACREG_A2HRIC_BIT_QUEUE_EMPTY 1176193240Ssam#endif 1177193240Ssam | MACREG_A2HRIC_BIT_BA_WATCHDOG 1178195171Ssam | MACREQ_A2HRIC_BIT_TX_ACK 1179193240Ssam ; 1180193240Ssam 1181287197Sglebius sc->sc_running = 1; 1182193240Ssam mwl_hal_intrset(mh, sc->sc_imask); 1183199559Sjhb callout_reset(&sc->sc_watchdog, hz, mwl_watchdog, sc); 1184193240Ssam 1185193240Ssam return 0; 1186193240Ssam} 1187193240Ssam 1188193240Ssamstatic void 1189287197Sglebiusmwl_stop(struct mwl_softc *sc) 1190193240Ssam{ 1191193240Ssam 1192193240Ssam MWL_LOCK_ASSERT(sc); 1193287197Sglebius if (sc->sc_running) { 1194193240Ssam /* 1195193240Ssam * Shutdown the hardware and driver. 1196193240Ssam */ 1197287197Sglebius sc->sc_running = 0; 1198199559Sjhb callout_stop(&sc->sc_watchdog); 1199199559Sjhb sc->sc_tx_timer = 0; 1200193240Ssam mwl_draintxq(sc); 1201193240Ssam } 1202193240Ssam} 1203193240Ssam 1204193240Ssamstatic int 1205193240Ssammwl_reset_vap(struct ieee80211vap *vap, int state) 1206193240Ssam{ 1207193240Ssam struct mwl_hal_vap *hvap = MWL_VAP(vap)->mv_hvap; 1208193240Ssam struct ieee80211com *ic = vap->iv_ic; 1209193240Ssam 1210193240Ssam if (state == IEEE80211_S_RUN) 1211193240Ssam mwl_setrates(vap); 1212193240Ssam /* XXX off by 1? */ 1213193240Ssam mwl_hal_setrtsthreshold(hvap, vap->iv_rtsthreshold); 1214193240Ssam /* XXX auto? 20/40 split? */ 1215193656Ssam mwl_hal_sethtgi(hvap, (vap->iv_flags_ht & 1216193656Ssam (IEEE80211_FHT_SHORTGI20|IEEE80211_FHT_SHORTGI40)) ? 1 : 0); 1217193240Ssam mwl_hal_setnprot(hvap, ic->ic_htprotmode == IEEE80211_PROT_NONE ? 1218193240Ssam HTPROTECT_NONE : HTPROTECT_AUTO); 1219193240Ssam /* XXX txpower cap */ 1220193240Ssam 1221193240Ssam /* re-setup beacons */ 1222193240Ssam if (state == IEEE80211_S_RUN && 1223193240Ssam (vap->iv_opmode == IEEE80211_M_HOSTAP || 1224195618Srpaulo vap->iv_opmode == IEEE80211_M_MBSS || 1225193240Ssam vap->iv_opmode == IEEE80211_M_IBSS)) { 1226193240Ssam mwl_setapmode(vap, vap->iv_bss->ni_chan); 1227193240Ssam mwl_hal_setnprotmode(hvap, 1228193240Ssam MS(ic->ic_curhtprotmode, IEEE80211_HTINFO_OPMODE)); 1229193240Ssam return mwl_beacon_setup(vap); 1230193240Ssam } 1231193240Ssam return 0; 1232193240Ssam} 1233193240Ssam 1234193240Ssam/* 1235193240Ssam * Reset the hardware w/o losing operational state. 1236193240Ssam * Used to to reset or reload hardware state for a vap. 1237193240Ssam */ 1238193240Ssamstatic int 1239193240Ssammwl_reset(struct ieee80211vap *vap, u_long cmd) 1240193240Ssam{ 1241193240Ssam struct mwl_hal_vap *hvap = MWL_VAP(vap)->mv_hvap; 1242193240Ssam int error = 0; 1243193240Ssam 1244193240Ssam if (hvap != NULL) { /* WDS, MONITOR, etc. */ 1245193240Ssam struct ieee80211com *ic = vap->iv_ic; 1246287197Sglebius struct mwl_softc *sc = ic->ic_softc; 1247193240Ssam struct mwl_hal *mh = sc->sc_mh; 1248193240Ssam 1249195171Ssam /* XXX handle DWDS sta vap change */ 1250193240Ssam /* XXX do we need to disable interrupts? */ 1251193240Ssam mwl_hal_intrset(mh, 0); /* disable interrupts */ 1252193240Ssam error = mwl_reset_vap(vap, vap->iv_state); 1253193240Ssam mwl_hal_intrset(mh, sc->sc_imask); 1254193240Ssam } 1255193240Ssam return error; 1256193240Ssam} 1257193240Ssam 1258193240Ssam/* 1259193240Ssam * Allocate a tx buffer for sending a frame. The 1260193240Ssam * packet is assumed to have the WME AC stored so 1261193240Ssam * we can use it to select the appropriate h/w queue. 1262193240Ssam */ 1263193240Ssamstatic struct mwl_txbuf * 1264193240Ssammwl_gettxbuf(struct mwl_softc *sc, struct mwl_txq *txq) 1265193240Ssam{ 1266193240Ssam struct mwl_txbuf *bf; 1267193240Ssam 1268193240Ssam /* 1269193240Ssam * Grab a TX buffer and associated resources. 1270193240Ssam */ 1271193240Ssam MWL_TXQ_LOCK(txq); 1272193240Ssam bf = STAILQ_FIRST(&txq->free); 1273193240Ssam if (bf != NULL) { 1274193240Ssam STAILQ_REMOVE_HEAD(&txq->free, bf_list); 1275193240Ssam txq->nfree--; 1276193240Ssam } 1277193240Ssam MWL_TXQ_UNLOCK(txq); 1278193240Ssam if (bf == NULL) 1279193240Ssam DPRINTF(sc, MWL_DEBUG_XMIT, 1280193240Ssam "%s: out of xmit buffers on q %d\n", __func__, txq->qnum); 1281193240Ssam return bf; 1282193240Ssam} 1283193240Ssam 1284193240Ssam/* 1285193240Ssam * Return a tx buffer to the queue it came from. Note there 1286193240Ssam * are two cases because we must preserve the order of buffers 1287193240Ssam * as it reflects the fixed order of descriptors in memory 1288193240Ssam * (the firmware pre-fetches descriptors so we cannot reorder). 1289193240Ssam */ 1290193240Ssamstatic void 1291193240Ssammwl_puttxbuf_head(struct mwl_txq *txq, struct mwl_txbuf *bf) 1292193240Ssam{ 1293193240Ssam bf->bf_m = NULL; 1294193240Ssam bf->bf_node = NULL; 1295193240Ssam MWL_TXQ_LOCK(txq); 1296193240Ssam STAILQ_INSERT_HEAD(&txq->free, bf, bf_list); 1297193240Ssam txq->nfree++; 1298193240Ssam MWL_TXQ_UNLOCK(txq); 1299193240Ssam} 1300193240Ssam 1301193240Ssamstatic void 1302193240Ssammwl_puttxbuf_tail(struct mwl_txq *txq, struct mwl_txbuf *bf) 1303193240Ssam{ 1304193240Ssam bf->bf_m = NULL; 1305193240Ssam bf->bf_node = NULL; 1306193240Ssam MWL_TXQ_LOCK(txq); 1307193240Ssam STAILQ_INSERT_TAIL(&txq->free, bf, bf_list); 1308193240Ssam txq->nfree++; 1309193240Ssam MWL_TXQ_UNLOCK(txq); 1310193240Ssam} 1311193240Ssam 1312287197Sglebiusstatic int 1313287197Sglebiusmwl_transmit(struct ieee80211com *ic, struct mbuf *m) 1314287197Sglebius{ 1315287197Sglebius struct mwl_softc *sc = ic->ic_softc; 1316287197Sglebius int error; 1317287197Sglebius 1318287197Sglebius MWL_LOCK(sc); 1319287197Sglebius if (!sc->sc_running) { 1320287197Sglebius MWL_UNLOCK(sc); 1321287197Sglebius return (ENXIO); 1322287197Sglebius } 1323287197Sglebius error = mbufq_enqueue(&sc->sc_snd, m); 1324287197Sglebius if (error) { 1325287197Sglebius MWL_UNLOCK(sc); 1326287197Sglebius return (error); 1327287197Sglebius } 1328287197Sglebius mwl_start(sc); 1329287197Sglebius MWL_UNLOCK(sc); 1330287197Sglebius return (0); 1331287197Sglebius} 1332287197Sglebius 1333193240Ssamstatic void 1334287197Sglebiusmwl_start(struct mwl_softc *sc) 1335193240Ssam{ 1336193240Ssam struct ieee80211_node *ni; 1337193240Ssam struct mwl_txbuf *bf; 1338193240Ssam struct mbuf *m; 1339193240Ssam struct mwl_txq *txq = NULL; /* XXX silence gcc */ 1340193240Ssam int nqueued; 1341193240Ssam 1342287197Sglebius MWL_LOCK_ASSERT(sc); 1343287197Sglebius if (!sc->sc_running || sc->sc_invalid) 1344193240Ssam return; 1345193240Ssam nqueued = 0; 1346287197Sglebius while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 1347193240Ssam /* 1348193240Ssam * Grab the node for the destination. 1349193240Ssam */ 1350193240Ssam ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1351193240Ssam KASSERT(ni != NULL, ("no node")); 1352193240Ssam m->m_pkthdr.rcvif = NULL; /* committed, clear ref */ 1353193240Ssam /* 1354193240Ssam * Grab a TX buffer and associated resources. 1355193240Ssam * We honor the classification by the 802.11 layer. 1356193240Ssam */ 1357193240Ssam txq = sc->sc_ac2q[M_WME_GETAC(m)]; 1358193240Ssam bf = mwl_gettxbuf(sc, txq); 1359193240Ssam if (bf == NULL) { 1360193240Ssam m_freem(m); 1361193240Ssam ieee80211_free_node(ni); 1362193240Ssam#ifdef MWL_TX_NODROP 1363193240Ssam sc->sc_stats.mst_tx_qstop++; 1364193240Ssam break; 1365193240Ssam#else 1366193240Ssam DPRINTF(sc, MWL_DEBUG_XMIT, 1367193240Ssam "%s: tail drop on q %d\n", __func__, txq->qnum); 1368193240Ssam sc->sc_stats.mst_tx_qdrop++; 1369193240Ssam continue; 1370193240Ssam#endif /* MWL_TX_NODROP */ 1371193240Ssam } 1372193240Ssam 1373193240Ssam /* 1374193240Ssam * Pass the frame to the h/w for transmission. 1375193240Ssam */ 1376193240Ssam if (mwl_tx_start(sc, ni, bf, m)) { 1377287197Sglebius if_inc_counter(ni->ni_vap->iv_ifp, 1378287197Sglebius IFCOUNTER_OERRORS, 1); 1379193240Ssam mwl_puttxbuf_head(txq, bf); 1380193240Ssam ieee80211_free_node(ni); 1381193240Ssam continue; 1382193240Ssam } 1383193240Ssam nqueued++; 1384193240Ssam if (nqueued >= mwl_txcoalesce) { 1385193240Ssam /* 1386193240Ssam * Poke the firmware to process queued frames; 1387193240Ssam * see below about (lack of) locking. 1388193240Ssam */ 1389193240Ssam nqueued = 0; 1390193240Ssam mwl_hal_txstart(sc->sc_mh, 0/*XXX*/); 1391193240Ssam } 1392193240Ssam } 1393193240Ssam if (nqueued) { 1394193240Ssam /* 1395193240Ssam * NB: We don't need to lock against tx done because 1396193240Ssam * this just prods the firmware to check the transmit 1397193240Ssam * descriptors. The firmware will also start fetching 1398193240Ssam * descriptors by itself if it notices new ones are 1399193240Ssam * present when it goes to deliver a tx done interrupt 1400193240Ssam * to the host. So if we race with tx done processing 1401193240Ssam * it's ok. Delivering the kick here rather than in 1402193240Ssam * mwl_tx_start is an optimization to avoid poking the 1403193240Ssam * firmware for each packet. 1404193240Ssam * 1405193240Ssam * NB: the queue id isn't used so 0 is ok. 1406193240Ssam */ 1407193240Ssam mwl_hal_txstart(sc->sc_mh, 0/*XXX*/); 1408193240Ssam } 1409193240Ssam} 1410193240Ssam 1411193240Ssamstatic int 1412193240Ssammwl_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1413193240Ssam const struct ieee80211_bpf_params *params) 1414193240Ssam{ 1415193240Ssam struct ieee80211com *ic = ni->ni_ic; 1416287197Sglebius struct mwl_softc *sc = ic->ic_softc; 1417193240Ssam struct mwl_txbuf *bf; 1418193240Ssam struct mwl_txq *txq; 1419193240Ssam 1420287197Sglebius if (!sc->sc_running || sc->sc_invalid) { 1421193240Ssam ieee80211_free_node(ni); 1422193240Ssam m_freem(m); 1423193240Ssam return ENETDOWN; 1424193240Ssam } 1425193240Ssam /* 1426193240Ssam * Grab a TX buffer and associated resources. 1427193240Ssam * Note that we depend on the classification 1428193240Ssam * by the 802.11 layer to get to the right h/w 1429193240Ssam * queue. Management frames must ALWAYS go on 1430193240Ssam * queue 1 but we cannot just force that here 1431193240Ssam * because we may receive non-mgt frames. 1432193240Ssam */ 1433193240Ssam txq = sc->sc_ac2q[M_WME_GETAC(m)]; 1434193240Ssam bf = mwl_gettxbuf(sc, txq); 1435193240Ssam if (bf == NULL) { 1436193240Ssam sc->sc_stats.mst_tx_qstop++; 1437193240Ssam ieee80211_free_node(ni); 1438193240Ssam m_freem(m); 1439193240Ssam return ENOBUFS; 1440193240Ssam } 1441193240Ssam /* 1442193240Ssam * Pass the frame to the h/w for transmission. 1443193240Ssam */ 1444193240Ssam if (mwl_tx_start(sc, ni, bf, m)) { 1445193240Ssam mwl_puttxbuf_head(txq, bf); 1446193240Ssam 1447193240Ssam ieee80211_free_node(ni); 1448193240Ssam return EIO; /* XXX */ 1449193240Ssam } 1450193240Ssam /* 1451193240Ssam * NB: We don't need to lock against tx done because 1452193240Ssam * this just prods the firmware to check the transmit 1453193240Ssam * descriptors. The firmware will also start fetching 1454193240Ssam * descriptors by itself if it notices new ones are 1455193240Ssam * present when it goes to deliver a tx done interrupt 1456193240Ssam * to the host. So if we race with tx done processing 1457193240Ssam * it's ok. Delivering the kick here rather than in 1458193240Ssam * mwl_tx_start is an optimization to avoid poking the 1459193240Ssam * firmware for each packet. 1460193240Ssam * 1461193240Ssam * NB: the queue id isn't used so 0 is ok. 1462193240Ssam */ 1463193240Ssam mwl_hal_txstart(sc->sc_mh, 0/*XXX*/); 1464193240Ssam return 0; 1465193240Ssam} 1466193240Ssam 1467193240Ssamstatic int 1468193240Ssammwl_media_change(struct ifnet *ifp) 1469193240Ssam{ 1470193240Ssam struct ieee80211vap *vap = ifp->if_softc; 1471193240Ssam int error; 1472193240Ssam 1473193240Ssam error = ieee80211_media_change(ifp); 1474193240Ssam /* NB: only the fixed rate can change and that doesn't need a reset */ 1475193240Ssam if (error == ENETRESET) { 1476193240Ssam mwl_setrates(vap); 1477193240Ssam error = 0; 1478193240Ssam } 1479193240Ssam return error; 1480193240Ssam} 1481193240Ssam 1482193240Ssam#ifdef MWL_DEBUG 1483193240Ssamstatic void 1484193240Ssammwl_keyprint(struct mwl_softc *sc, const char *tag, 1485193240Ssam const MWL_HAL_KEYVAL *hk, const uint8_t mac[IEEE80211_ADDR_LEN]) 1486193240Ssam{ 1487193240Ssam static const char *ciphers[] = { 1488193240Ssam "WEP", 1489193240Ssam "TKIP", 1490193240Ssam "AES-CCM", 1491193240Ssam }; 1492193240Ssam int i, n; 1493193240Ssam 1494193240Ssam printf("%s: [%u] %-7s", tag, hk->keyIndex, ciphers[hk->keyTypeId]); 1495193240Ssam for (i = 0, n = hk->keyLen; i < n; i++) 1496193240Ssam printf(" %02x", hk->key.aes[i]); 1497193240Ssam printf(" mac %s", ether_sprintf(mac)); 1498193240Ssam if (hk->keyTypeId == KEY_TYPE_ID_TKIP) { 1499193240Ssam printf(" %s", "rxmic"); 1500193240Ssam for (i = 0; i < sizeof(hk->key.tkip.rxMic); i++) 1501193240Ssam printf(" %02x", hk->key.tkip.rxMic[i]); 1502193240Ssam printf(" txmic"); 1503193240Ssam for (i = 0; i < sizeof(hk->key.tkip.txMic); i++) 1504193240Ssam printf(" %02x", hk->key.tkip.txMic[i]); 1505193240Ssam } 1506193240Ssam printf(" flags 0x%x\n", hk->keyFlags); 1507193240Ssam} 1508193240Ssam#endif 1509193240Ssam 1510193240Ssam/* 1511193240Ssam * Allocate a key cache slot for a unicast key. The 1512193240Ssam * firmware handles key allocation and every station is 1513193240Ssam * guaranteed key space so we are always successful. 1514193240Ssam */ 1515193240Ssamstatic int 1516193240Ssammwl_key_alloc(struct ieee80211vap *vap, struct ieee80211_key *k, 1517193240Ssam ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix) 1518193240Ssam{ 1519287197Sglebius struct mwl_softc *sc = vap->iv_ic->ic_softc; 1520193240Ssam 1521193240Ssam if (k->wk_keyix != IEEE80211_KEYIX_NONE || 1522193240Ssam (k->wk_flags & IEEE80211_KEY_GROUP)) { 1523193240Ssam if (!(&vap->iv_nw_keys[0] <= k && 1524193240Ssam k < &vap->iv_nw_keys[IEEE80211_WEP_NKID])) { 1525193240Ssam /* should not happen */ 1526193240Ssam DPRINTF(sc, MWL_DEBUG_KEYCACHE, 1527193240Ssam "%s: bogus group key\n", __func__); 1528193240Ssam return 0; 1529193240Ssam } 1530193240Ssam /* give the caller what they requested */ 1531193240Ssam *keyix = *rxkeyix = k - vap->iv_nw_keys; 1532193240Ssam } else { 1533193240Ssam /* 1534193240Ssam * Firmware handles key allocation. 1535193240Ssam */ 1536193240Ssam *keyix = *rxkeyix = 0; 1537193240Ssam } 1538193240Ssam return 1; 1539193240Ssam} 1540193240Ssam 1541193240Ssam/* 1542193240Ssam * Delete a key entry allocated by mwl_key_alloc. 1543193240Ssam */ 1544193240Ssamstatic int 1545193240Ssammwl_key_delete(struct ieee80211vap *vap, const struct ieee80211_key *k) 1546193240Ssam{ 1547287197Sglebius struct mwl_softc *sc = vap->iv_ic->ic_softc; 1548193240Ssam struct mwl_hal_vap *hvap = MWL_VAP(vap)->mv_hvap; 1549193240Ssam MWL_HAL_KEYVAL hk; 1550193240Ssam const uint8_t bcastaddr[IEEE80211_ADDR_LEN] = 1551193240Ssam { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 1552193240Ssam 1553193240Ssam if (hvap == NULL) { 1554193240Ssam if (vap->iv_opmode != IEEE80211_M_WDS) { 1555193240Ssam /* XXX monitor mode? */ 1556193240Ssam DPRINTF(sc, MWL_DEBUG_KEYCACHE, 1557193240Ssam "%s: no hvap for opmode %d\n", __func__, 1558193240Ssam vap->iv_opmode); 1559193240Ssam return 0; 1560193240Ssam } 1561193240Ssam hvap = MWL_VAP(vap)->mv_ap_hvap; 1562193240Ssam } 1563193240Ssam 1564193240Ssam DPRINTF(sc, MWL_DEBUG_KEYCACHE, "%s: delete key %u\n", 1565193240Ssam __func__, k->wk_keyix); 1566193240Ssam 1567193240Ssam memset(&hk, 0, sizeof(hk)); 1568193240Ssam hk.keyIndex = k->wk_keyix; 1569193240Ssam switch (k->wk_cipher->ic_cipher) { 1570193240Ssam case IEEE80211_CIPHER_WEP: 1571193240Ssam hk.keyTypeId = KEY_TYPE_ID_WEP; 1572193240Ssam break; 1573193240Ssam case IEEE80211_CIPHER_TKIP: 1574193240Ssam hk.keyTypeId = KEY_TYPE_ID_TKIP; 1575193240Ssam break; 1576193240Ssam case IEEE80211_CIPHER_AES_CCM: 1577193240Ssam hk.keyTypeId = KEY_TYPE_ID_AES; 1578193240Ssam break; 1579193240Ssam default: 1580193240Ssam /* XXX should not happen */ 1581193240Ssam DPRINTF(sc, MWL_DEBUG_KEYCACHE, "%s: unknown cipher %d\n", 1582193240Ssam __func__, k->wk_cipher->ic_cipher); 1583193240Ssam return 0; 1584193240Ssam } 1585193240Ssam return (mwl_hal_keyreset(hvap, &hk, bcastaddr) == 0); /*XXX*/ 1586193240Ssam} 1587193240Ssam 1588193240Ssamstatic __inline int 1589193240Ssamaddgroupflags(MWL_HAL_KEYVAL *hk, const struct ieee80211_key *k) 1590193240Ssam{ 1591193240Ssam if (k->wk_flags & IEEE80211_KEY_GROUP) { 1592193240Ssam if (k->wk_flags & IEEE80211_KEY_XMIT) 1593193240Ssam hk->keyFlags |= KEY_FLAG_TXGROUPKEY; 1594193240Ssam if (k->wk_flags & IEEE80211_KEY_RECV) 1595193240Ssam hk->keyFlags |= KEY_FLAG_RXGROUPKEY; 1596193240Ssam return 1; 1597193240Ssam } else 1598193240Ssam return 0; 1599193240Ssam} 1600193240Ssam 1601193240Ssam/* 1602193240Ssam * Set the key cache contents for the specified key. Key cache 1603193240Ssam * slot(s) must already have been allocated by mwl_key_alloc. 1604193240Ssam */ 1605193240Ssamstatic int 1606193240Ssammwl_key_set(struct ieee80211vap *vap, const struct ieee80211_key *k, 1607193240Ssam const uint8_t mac[IEEE80211_ADDR_LEN]) 1608193240Ssam{ 1609193240Ssam#define GRPXMIT (IEEE80211_KEY_XMIT | IEEE80211_KEY_GROUP) 1610193240Ssam/* NB: static wep keys are marked GROUP+tx/rx; GTK will be tx or rx */ 1611193240Ssam#define IEEE80211_IS_STATICKEY(k) \ 1612193240Ssam (((k)->wk_flags & (GRPXMIT|IEEE80211_KEY_RECV)) == \ 1613193240Ssam (GRPXMIT|IEEE80211_KEY_RECV)) 1614287197Sglebius struct mwl_softc *sc = vap->iv_ic->ic_softc; 1615193240Ssam struct mwl_hal_vap *hvap = MWL_VAP(vap)->mv_hvap; 1616193240Ssam const struct ieee80211_cipher *cip = k->wk_cipher; 1617193240Ssam const uint8_t *macaddr; 1618193240Ssam MWL_HAL_KEYVAL hk; 1619193240Ssam 1620193240Ssam KASSERT((k->wk_flags & IEEE80211_KEY_SWCRYPT) == 0, 1621193240Ssam ("s/w crypto set?")); 1622193240Ssam 1623193240Ssam if (hvap == NULL) { 1624193240Ssam if (vap->iv_opmode != IEEE80211_M_WDS) { 1625193240Ssam /* XXX monitor mode? */ 1626193240Ssam DPRINTF(sc, MWL_DEBUG_KEYCACHE, 1627193240Ssam "%s: no hvap for opmode %d\n", __func__, 1628193240Ssam vap->iv_opmode); 1629193240Ssam return 0; 1630193240Ssam } 1631193240Ssam hvap = MWL_VAP(vap)->mv_ap_hvap; 1632193240Ssam } 1633193240Ssam memset(&hk, 0, sizeof(hk)); 1634193240Ssam hk.keyIndex = k->wk_keyix; 1635193240Ssam switch (cip->ic_cipher) { 1636193240Ssam case IEEE80211_CIPHER_WEP: 1637193240Ssam hk.keyTypeId = KEY_TYPE_ID_WEP; 1638193240Ssam hk.keyLen = k->wk_keylen; 1639193240Ssam if (k->wk_keyix == vap->iv_def_txkey) 1640193240Ssam hk.keyFlags = KEY_FLAG_WEP_TXKEY; 1641193240Ssam if (!IEEE80211_IS_STATICKEY(k)) { 1642193240Ssam /* NB: WEP is never used for the PTK */ 1643193240Ssam (void) addgroupflags(&hk, k); 1644193240Ssam } 1645193240Ssam break; 1646193240Ssam case IEEE80211_CIPHER_TKIP: 1647193240Ssam hk.keyTypeId = KEY_TYPE_ID_TKIP; 1648193240Ssam hk.key.tkip.tsc.high = (uint32_t)(k->wk_keytsc >> 16); 1649193240Ssam hk.key.tkip.tsc.low = (uint16_t)k->wk_keytsc; 1650193240Ssam hk.keyFlags = KEY_FLAG_TSC_VALID | KEY_FLAG_MICKEY_VALID; 1651193240Ssam hk.keyLen = k->wk_keylen + IEEE80211_MICBUF_SIZE; 1652193240Ssam if (!addgroupflags(&hk, k)) 1653193240Ssam hk.keyFlags |= KEY_FLAG_PAIRWISE; 1654193240Ssam break; 1655193240Ssam case IEEE80211_CIPHER_AES_CCM: 1656193240Ssam hk.keyTypeId = KEY_TYPE_ID_AES; 1657193240Ssam hk.keyLen = k->wk_keylen; 1658193240Ssam if (!addgroupflags(&hk, k)) 1659193240Ssam hk.keyFlags |= KEY_FLAG_PAIRWISE; 1660193240Ssam break; 1661193240Ssam default: 1662193240Ssam /* XXX should not happen */ 1663193240Ssam DPRINTF(sc, MWL_DEBUG_KEYCACHE, "%s: unknown cipher %d\n", 1664193240Ssam __func__, k->wk_cipher->ic_cipher); 1665193240Ssam return 0; 1666193240Ssam } 1667193240Ssam /* 1668193240Ssam * NB: tkip mic keys get copied here too; the layout 1669193240Ssam * just happens to match that in ieee80211_key. 1670193240Ssam */ 1671193240Ssam memcpy(hk.key.aes, k->wk_key, hk.keyLen); 1672193240Ssam 1673193240Ssam /* 1674193240Ssam * Locate address of sta db entry for writing key; 1675193240Ssam * the convention unfortunately is somewhat different 1676193240Ssam * than how net80211, hostapd, and wpa_supplicant think. 1677193240Ssam */ 1678193240Ssam if (vap->iv_opmode == IEEE80211_M_STA) { 1679193240Ssam /* 1680193240Ssam * NB: keys plumbed before the sta reaches AUTH state 1681193240Ssam * will be discarded or written to the wrong sta db 1682193240Ssam * entry because iv_bss is meaningless. This is ok 1683193240Ssam * (right now) because we handle deferred plumbing of 1684193240Ssam * WEP keys when the sta reaches AUTH state. 1685193240Ssam */ 1686193240Ssam macaddr = vap->iv_bss->ni_bssid; 1687196842Ssam if ((k->wk_flags & IEEE80211_KEY_GROUP) == 0) { 1688196842Ssam /* XXX plumb to local sta db too for static key wep */ 1689196842Ssam mwl_hal_keyset(hvap, &hk, vap->iv_myaddr); 1690196842Ssam } 1691193240Ssam } else if (vap->iv_opmode == IEEE80211_M_WDS && 1692193240Ssam vap->iv_state != IEEE80211_S_RUN) { 1693193240Ssam /* 1694193240Ssam * Prior to RUN state a WDS vap will not it's BSS node 1695193240Ssam * setup so we will plumb the key to the wrong mac 1696193240Ssam * address (it'll be our local address). Workaround 1697193240Ssam * this for the moment by grabbing the correct address. 1698193240Ssam */ 1699193240Ssam macaddr = vap->iv_des_bssid; 1700193240Ssam } else if ((k->wk_flags & GRPXMIT) == GRPXMIT) 1701193240Ssam macaddr = vap->iv_myaddr; 1702193240Ssam else 1703193240Ssam macaddr = mac; 1704193240Ssam KEYPRINTF(sc, &hk, macaddr); 1705193240Ssam return (mwl_hal_keyset(hvap, &hk, macaddr) == 0); 1706193240Ssam#undef IEEE80211_IS_STATICKEY 1707193240Ssam#undef GRPXMIT 1708193240Ssam} 1709193240Ssam 1710193240Ssam/* unaligned little endian access */ 1711193240Ssam#define LE_READ_2(p) \ 1712193240Ssam ((uint16_t) \ 1713193240Ssam ((((const uint8_t *)(p))[0] ) | \ 1714193240Ssam (((const uint8_t *)(p))[1] << 8))) 1715193240Ssam#define LE_READ_4(p) \ 1716193240Ssam ((uint32_t) \ 1717193240Ssam ((((const uint8_t *)(p))[0] ) | \ 1718193240Ssam (((const uint8_t *)(p))[1] << 8) | \ 1719193240Ssam (((const uint8_t *)(p))[2] << 16) | \ 1720193240Ssam (((const uint8_t *)(p))[3] << 24))) 1721193240Ssam 1722193240Ssam/* 1723193240Ssam * Set the multicast filter contents into the hardware. 1724193240Ssam * XXX f/w has no support; just defer to the os. 1725193240Ssam */ 1726193240Ssamstatic void 1727193240Ssammwl_setmcastfilter(struct mwl_softc *sc) 1728193240Ssam{ 1729193240Ssam#if 0 1730193240Ssam struct ether_multi *enm; 1731193240Ssam struct ether_multistep estep; 1732193240Ssam uint8_t macs[IEEE80211_ADDR_LEN*MWL_HAL_MCAST_MAX];/* XXX stack use */ 1733193240Ssam uint8_t *mp; 1734193240Ssam int nmc; 1735193240Ssam 1736193240Ssam mp = macs; 1737193240Ssam nmc = 0; 1738193240Ssam ETHER_FIRST_MULTI(estep, &sc->sc_ec, enm); 1739193240Ssam while (enm != NULL) { 1740193240Ssam /* XXX Punt on ranges. */ 1741193240Ssam if (nmc == MWL_HAL_MCAST_MAX || 1742193240Ssam !IEEE80211_ADDR_EQ(enm->enm_addrlo, enm->enm_addrhi)) { 1743193240Ssam ifp->if_flags |= IFF_ALLMULTI; 1744193240Ssam return; 1745193240Ssam } 1746193240Ssam IEEE80211_ADDR_COPY(mp, enm->enm_addrlo); 1747193240Ssam mp += IEEE80211_ADDR_LEN, nmc++; 1748193240Ssam ETHER_NEXT_MULTI(estep, enm); 1749193240Ssam } 1750193240Ssam ifp->if_flags &= ~IFF_ALLMULTI; 1751193240Ssam mwl_hal_setmcast(sc->sc_mh, nmc, macs); 1752193240Ssam#endif 1753193240Ssam} 1754193240Ssam 1755193240Ssamstatic int 1756193240Ssammwl_mode_init(struct mwl_softc *sc) 1757193240Ssam{ 1758287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 1759193240Ssam struct mwl_hal *mh = sc->sc_mh; 1760193240Ssam 1761193240Ssam /* 1762193240Ssam * NB: Ignore promisc in hostap mode; it's set by the 1763193240Ssam * bridge. This is wrong but we have no way to 1764193240Ssam * identify internal requests (from the bridge) 1765193240Ssam * versus external requests such as for tcpdump. 1766193240Ssam */ 1767287197Sglebius mwl_hal_setpromisc(mh, ic->ic_promisc > 0 && 1768193240Ssam ic->ic_opmode != IEEE80211_M_HOSTAP); 1769193240Ssam mwl_setmcastfilter(sc); 1770193240Ssam 1771193240Ssam return 0; 1772193240Ssam} 1773193240Ssam 1774193240Ssam/* 1775193240Ssam * Callback from the 802.11 layer after a multicast state change. 1776193240Ssam */ 1777193240Ssamstatic void 1778283540Sglebiusmwl_update_mcast(struct ieee80211com *ic) 1779193240Ssam{ 1780283540Sglebius struct mwl_softc *sc = ic->ic_softc; 1781193240Ssam 1782193240Ssam mwl_setmcastfilter(sc); 1783193240Ssam} 1784193240Ssam 1785193240Ssam/* 1786193240Ssam * Callback from the 802.11 layer after a promiscuous mode change. 1787193240Ssam * Note this interface does not check the operating mode as this 1788193240Ssam * is an internal callback and we are expected to honor the current 1789193240Ssam * state (e.g. this is used for setting the interface in promiscuous 1790193240Ssam * mode when operating in hostap mode to do ACS). 1791193240Ssam */ 1792193240Ssamstatic void 1793283540Sglebiusmwl_update_promisc(struct ieee80211com *ic) 1794193240Ssam{ 1795283540Sglebius struct mwl_softc *sc = ic->ic_softc; 1796193240Ssam 1797287197Sglebius mwl_hal_setpromisc(sc->sc_mh, ic->ic_promisc > 0); 1798193240Ssam} 1799193240Ssam 1800193240Ssam/* 1801193240Ssam * Callback from the 802.11 layer to update the slot time 1802193240Ssam * based on the current setting. We use it to notify the 1803193240Ssam * firmware of ERP changes and the f/w takes care of things 1804193240Ssam * like slot time and preamble. 1805193240Ssam */ 1806193240Ssamstatic void 1807283540Sglebiusmwl_updateslot(struct ieee80211com *ic) 1808193240Ssam{ 1809283540Sglebius struct mwl_softc *sc = ic->ic_softc; 1810193240Ssam struct mwl_hal *mh = sc->sc_mh; 1811193240Ssam int prot; 1812193240Ssam 1813193240Ssam /* NB: can be called early; suppress needless cmds */ 1814287197Sglebius if (!sc->sc_running) 1815193240Ssam return; 1816193240Ssam 1817193240Ssam /* 1818193240Ssam * Calculate the ERP flags. The firwmare will use 1819193240Ssam * this to carry out the appropriate measures. 1820193240Ssam */ 1821193240Ssam prot = 0; 1822193240Ssam if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) { 1823193240Ssam if ((ic->ic_flags & IEEE80211_F_SHSLOT) == 0) 1824193240Ssam prot |= IEEE80211_ERP_NON_ERP_PRESENT; 1825193240Ssam if (ic->ic_flags & IEEE80211_F_USEPROT) 1826193240Ssam prot |= IEEE80211_ERP_USE_PROTECTION; 1827193240Ssam if (ic->ic_flags & IEEE80211_F_USEBARKER) 1828193240Ssam prot |= IEEE80211_ERP_LONG_PREAMBLE; 1829193240Ssam } 1830193240Ssam 1831193240Ssam DPRINTF(sc, MWL_DEBUG_RESET, 1832193240Ssam "%s: chan %u MHz/flags 0x%x %s slot, (prot 0x%x ic_flags 0x%x)\n", 1833193240Ssam __func__, ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags, 1834193240Ssam ic->ic_flags & IEEE80211_F_SHSLOT ? "short" : "long", prot, 1835193240Ssam ic->ic_flags); 1836193240Ssam 1837193240Ssam mwl_hal_setgprot(mh, prot); 1838193240Ssam} 1839193240Ssam 1840193240Ssam/* 1841193240Ssam * Setup the beacon frame. 1842193240Ssam */ 1843193240Ssamstatic int 1844193240Ssammwl_beacon_setup(struct ieee80211vap *vap) 1845193240Ssam{ 1846193240Ssam struct mwl_hal_vap *hvap = MWL_VAP(vap)->mv_hvap; 1847193240Ssam struct ieee80211_node *ni = vap->iv_bss; 1848193240Ssam struct ieee80211_beacon_offsets bo; 1849193240Ssam struct mbuf *m; 1850193240Ssam 1851193240Ssam m = ieee80211_beacon_alloc(ni, &bo); 1852193240Ssam if (m == NULL) 1853193240Ssam return ENOBUFS; 1854193240Ssam mwl_hal_setbeacon(hvap, mtod(m, const void *), m->m_len); 1855193240Ssam m_free(m); 1856193240Ssam 1857193240Ssam return 0; 1858193240Ssam} 1859193240Ssam 1860193240Ssam/* 1861193240Ssam * Update the beacon frame in response to a change. 1862193240Ssam */ 1863193240Ssamstatic void 1864193240Ssammwl_beacon_update(struct ieee80211vap *vap, int item) 1865193240Ssam{ 1866193240Ssam struct mwl_hal_vap *hvap = MWL_VAP(vap)->mv_hvap; 1867193240Ssam struct ieee80211com *ic = vap->iv_ic; 1868193240Ssam 1869193240Ssam KASSERT(hvap != NULL, ("no beacon")); 1870193240Ssam switch (item) { 1871193240Ssam case IEEE80211_BEACON_ERP: 1872283540Sglebius mwl_updateslot(ic); 1873193240Ssam break; 1874193240Ssam case IEEE80211_BEACON_HTINFO: 1875193240Ssam mwl_hal_setnprotmode(hvap, 1876193240Ssam MS(ic->ic_curhtprotmode, IEEE80211_HTINFO_OPMODE)); 1877193240Ssam break; 1878193240Ssam case IEEE80211_BEACON_CAPS: 1879193240Ssam case IEEE80211_BEACON_WME: 1880193240Ssam case IEEE80211_BEACON_APPIE: 1881193240Ssam case IEEE80211_BEACON_CSA: 1882193240Ssam break; 1883193240Ssam case IEEE80211_BEACON_TIM: 1884193240Ssam /* NB: firmware always forms TIM */ 1885193240Ssam return; 1886193240Ssam } 1887193240Ssam /* XXX retain beacon frame and update */ 1888193240Ssam mwl_beacon_setup(vap); 1889193240Ssam} 1890193240Ssam 1891193240Ssamstatic void 1892193240Ssammwl_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1893193240Ssam{ 1894193240Ssam bus_addr_t *paddr = (bus_addr_t*) arg; 1895193240Ssam KASSERT(error == 0, ("error %u on bus_dma callback", error)); 1896193240Ssam *paddr = segs->ds_addr; 1897193240Ssam} 1898193240Ssam 1899193240Ssam#ifdef MWL_HOST_PS_SUPPORT 1900193240Ssam/* 1901193240Ssam * Handle power save station occupancy changes. 1902193240Ssam */ 1903193240Ssamstatic void 1904193240Ssammwl_update_ps(struct ieee80211vap *vap, int nsta) 1905193240Ssam{ 1906193240Ssam struct mwl_vap *mvp = MWL_VAP(vap); 1907193240Ssam 1908193240Ssam if (nsta == 0 || mvp->mv_last_ps_sta == 0) 1909193240Ssam mwl_hal_setpowersave_bss(mvp->mv_hvap, nsta); 1910193240Ssam mvp->mv_last_ps_sta = nsta; 1911193240Ssam} 1912193240Ssam 1913193240Ssam/* 1914193240Ssam * Handle associated station power save state changes. 1915193240Ssam */ 1916193240Ssamstatic int 1917193240Ssammwl_set_tim(struct ieee80211_node *ni, int set) 1918193240Ssam{ 1919193240Ssam struct ieee80211vap *vap = ni->ni_vap; 1920193240Ssam struct mwl_vap *mvp = MWL_VAP(vap); 1921193240Ssam 1922193240Ssam if (mvp->mv_set_tim(ni, set)) { /* NB: state change */ 1923193240Ssam mwl_hal_setpowersave_sta(mvp->mv_hvap, 1924193240Ssam IEEE80211_AID(ni->ni_associd), set); 1925193240Ssam return 1; 1926193240Ssam } else 1927193240Ssam return 0; 1928193240Ssam} 1929193240Ssam#endif /* MWL_HOST_PS_SUPPORT */ 1930193240Ssam 1931193240Ssamstatic int 1932193240Ssammwl_desc_setup(struct mwl_softc *sc, const char *name, 1933193240Ssam struct mwl_descdma *dd, 1934193240Ssam int nbuf, size_t bufsize, int ndesc, size_t descsize) 1935193240Ssam{ 1936193240Ssam uint8_t *ds; 1937193240Ssam int error; 1938193240Ssam 1939193240Ssam DPRINTF(sc, MWL_DEBUG_RESET, 1940193240Ssam "%s: %s DMA: %u bufs (%ju) %u desc/buf (%ju)\n", 1941193240Ssam __func__, name, nbuf, (uintmax_t) bufsize, 1942193240Ssam ndesc, (uintmax_t) descsize); 1943193240Ssam 1944193240Ssam dd->dd_name = name; 1945193240Ssam dd->dd_desc_len = nbuf * ndesc * descsize; 1946193240Ssam 1947193240Ssam /* 1948193240Ssam * Setup DMA descriptor area. 1949193240Ssam */ 1950193240Ssam error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */ 1951193240Ssam PAGE_SIZE, 0, /* alignment, bounds */ 1952193240Ssam BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1953193240Ssam BUS_SPACE_MAXADDR, /* highaddr */ 1954193240Ssam NULL, NULL, /* filter, filterarg */ 1955193240Ssam dd->dd_desc_len, /* maxsize */ 1956193240Ssam 1, /* nsegments */ 1957193240Ssam dd->dd_desc_len, /* maxsegsize */ 1958193240Ssam BUS_DMA_ALLOCNOW, /* flags */ 1959193240Ssam NULL, /* lockfunc */ 1960193240Ssam NULL, /* lockarg */ 1961193240Ssam &dd->dd_dmat); 1962193240Ssam if (error != 0) { 1963287197Sglebius device_printf(sc->sc_dev, "cannot allocate %s DMA tag\n", dd->dd_name); 1964193240Ssam return error; 1965193240Ssam } 1966193240Ssam 1967193240Ssam /* allocate descriptors */ 1968193240Ssam error = bus_dmamem_alloc(dd->dd_dmat, (void**) &dd->dd_desc, 1969193240Ssam BUS_DMA_NOWAIT | BUS_DMA_COHERENT, 1970193240Ssam &dd->dd_dmamap); 1971193240Ssam if (error != 0) { 1972287197Sglebius device_printf(sc->sc_dev, "unable to alloc memory for %u %s descriptors, " 1973193240Ssam "error %u\n", nbuf * ndesc, dd->dd_name, error); 1974193240Ssam goto fail1; 1975193240Ssam } 1976193240Ssam 1977193240Ssam error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap, 1978193240Ssam dd->dd_desc, dd->dd_desc_len, 1979193240Ssam mwl_load_cb, &dd->dd_desc_paddr, 1980193240Ssam BUS_DMA_NOWAIT); 1981193240Ssam if (error != 0) { 1982287197Sglebius device_printf(sc->sc_dev, "unable to map %s descriptors, error %u\n", 1983193240Ssam dd->dd_name, error); 1984193240Ssam goto fail2; 1985193240Ssam } 1986193240Ssam 1987193240Ssam ds = dd->dd_desc; 1988193240Ssam memset(ds, 0, dd->dd_desc_len); 1989278532Smarius DPRINTF(sc, MWL_DEBUG_RESET, 1990278532Smarius "%s: %s DMA map: %p (%lu) -> 0x%jx (%lu)\n", 1991193240Ssam __func__, dd->dd_name, ds, (u_long) dd->dd_desc_len, 1992278532Smarius (uintmax_t) dd->dd_desc_paddr, /*XXX*/ (u_long) dd->dd_desc_len); 1993193240Ssam 1994193240Ssam return 0; 1995193240Ssamfail2: 1996193240Ssam bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap); 1997193240Ssamfail1: 1998193240Ssam bus_dma_tag_destroy(dd->dd_dmat); 1999193240Ssam memset(dd, 0, sizeof(*dd)); 2000193240Ssam return error; 2001193240Ssam#undef DS2PHYS 2002193240Ssam} 2003193240Ssam 2004193240Ssamstatic void 2005193240Ssammwl_desc_cleanup(struct mwl_softc *sc, struct mwl_descdma *dd) 2006193240Ssam{ 2007193240Ssam bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 2008193240Ssam bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap); 2009193240Ssam bus_dma_tag_destroy(dd->dd_dmat); 2010193240Ssam 2011193240Ssam memset(dd, 0, sizeof(*dd)); 2012193240Ssam} 2013193240Ssam 2014193240Ssam/* 2015193240Ssam * Construct a tx q's free list. The order of entries on 2016193240Ssam * the list must reflect the physical layout of tx descriptors 2017193240Ssam * because the firmware pre-fetches descriptors. 2018193240Ssam * 2019193240Ssam * XXX might be better to use indices into the buffer array. 2020193240Ssam */ 2021193240Ssamstatic void 2022193240Ssammwl_txq_reset(struct mwl_softc *sc, struct mwl_txq *txq) 2023193240Ssam{ 2024193240Ssam struct mwl_txbuf *bf; 2025193240Ssam int i; 2026193240Ssam 2027193240Ssam bf = txq->dma.dd_bufptr; 2028193240Ssam STAILQ_INIT(&txq->free); 2029193240Ssam for (i = 0; i < mwl_txbuf; i++, bf++) 2030193240Ssam STAILQ_INSERT_TAIL(&txq->free, bf, bf_list); 2031193240Ssam txq->nfree = i; 2032193240Ssam} 2033193240Ssam 2034193240Ssam#define DS2PHYS(_dd, _ds) \ 2035193240Ssam ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) 2036193240Ssam 2037193240Ssamstatic int 2038193240Ssammwl_txdma_setup(struct mwl_softc *sc, struct mwl_txq *txq) 2039193240Ssam{ 2040193240Ssam int error, bsize, i; 2041193240Ssam struct mwl_txbuf *bf; 2042193240Ssam struct mwl_txdesc *ds; 2043193240Ssam 2044193240Ssam error = mwl_desc_setup(sc, "tx", &txq->dma, 2045193240Ssam mwl_txbuf, sizeof(struct mwl_txbuf), 2046193240Ssam MWL_TXDESC, sizeof(struct mwl_txdesc)); 2047193240Ssam if (error != 0) 2048193240Ssam return error; 2049193240Ssam 2050193240Ssam /* allocate and setup tx buffers */ 2051193240Ssam bsize = mwl_txbuf * sizeof(struct mwl_txbuf); 2052193240Ssam bf = malloc(bsize, M_MWLDEV, M_NOWAIT | M_ZERO); 2053193240Ssam if (bf == NULL) { 2054287197Sglebius device_printf(sc->sc_dev, "malloc of %u tx buffers failed\n", 2055193240Ssam mwl_txbuf); 2056193240Ssam return ENOMEM; 2057193240Ssam } 2058193240Ssam txq->dma.dd_bufptr = bf; 2059193240Ssam 2060193240Ssam ds = txq->dma.dd_desc; 2061193240Ssam for (i = 0; i < mwl_txbuf; i++, bf++, ds += MWL_TXDESC) { 2062193240Ssam bf->bf_desc = ds; 2063193240Ssam bf->bf_daddr = DS2PHYS(&txq->dma, ds); 2064193240Ssam error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, 2065193240Ssam &bf->bf_dmamap); 2066193240Ssam if (error != 0) { 2067287197Sglebius device_printf(sc->sc_dev, "unable to create dmamap for tx " 2068193240Ssam "buffer %u, error %u\n", i, error); 2069193240Ssam return error; 2070193240Ssam } 2071193240Ssam } 2072193240Ssam mwl_txq_reset(sc, txq); 2073193240Ssam return 0; 2074193240Ssam} 2075193240Ssam 2076193240Ssamstatic void 2077193240Ssammwl_txdma_cleanup(struct mwl_softc *sc, struct mwl_txq *txq) 2078193240Ssam{ 2079193240Ssam struct mwl_txbuf *bf; 2080193240Ssam int i; 2081193240Ssam 2082193240Ssam bf = txq->dma.dd_bufptr; 2083193240Ssam for (i = 0; i < mwl_txbuf; i++, bf++) { 2084193240Ssam KASSERT(bf->bf_m == NULL, ("mbuf on free list")); 2085193240Ssam KASSERT(bf->bf_node == NULL, ("node on free list")); 2086193240Ssam if (bf->bf_dmamap != NULL) 2087193240Ssam bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 2088193240Ssam } 2089193240Ssam STAILQ_INIT(&txq->free); 2090193240Ssam txq->nfree = 0; 2091193240Ssam if (txq->dma.dd_bufptr != NULL) { 2092193240Ssam free(txq->dma.dd_bufptr, M_MWLDEV); 2093193240Ssam txq->dma.dd_bufptr = NULL; 2094193240Ssam } 2095193240Ssam if (txq->dma.dd_desc_len != 0) 2096193240Ssam mwl_desc_cleanup(sc, &txq->dma); 2097193240Ssam} 2098193240Ssam 2099193240Ssamstatic int 2100193240Ssammwl_rxdma_setup(struct mwl_softc *sc) 2101193240Ssam{ 2102193240Ssam int error, jumbosize, bsize, i; 2103193240Ssam struct mwl_rxbuf *bf; 2104193240Ssam struct mwl_jumbo *rbuf; 2105193240Ssam struct mwl_rxdesc *ds; 2106193240Ssam caddr_t data; 2107193240Ssam 2108193240Ssam error = mwl_desc_setup(sc, "rx", &sc->sc_rxdma, 2109193240Ssam mwl_rxdesc, sizeof(struct mwl_rxbuf), 2110193240Ssam 1, sizeof(struct mwl_rxdesc)); 2111193240Ssam if (error != 0) 2112193240Ssam return error; 2113193240Ssam 2114193240Ssam /* 2115193240Ssam * Receive is done to a private pool of jumbo buffers. 2116193240Ssam * This allows us to attach to mbuf's and avoid re-mapping 2117193240Ssam * memory on each rx we post. We allocate a large chunk 2118193240Ssam * of memory and manage it in the driver. The mbuf free 2119193240Ssam * callback method is used to reclaim frames after sending 2120193240Ssam * them up the stack. By default we allocate 2x the number of 2121193240Ssam * rx descriptors configured so we have some slop to hold 2122193240Ssam * us while frames are processed. 2123193240Ssam */ 2124193240Ssam if (mwl_rxbuf < 2*mwl_rxdesc) { 2125287197Sglebius device_printf(sc->sc_dev, 2126193240Ssam "too few rx dma buffers (%d); increasing to %d\n", 2127193240Ssam mwl_rxbuf, 2*mwl_rxdesc); 2128193240Ssam mwl_rxbuf = 2*mwl_rxdesc; 2129193240Ssam } 2130193240Ssam jumbosize = roundup(MWL_AGGR_SIZE, PAGE_SIZE); 2131193240Ssam sc->sc_rxmemsize = mwl_rxbuf*jumbosize; 2132193240Ssam 2133193240Ssam error = bus_dma_tag_create(sc->sc_dmat, /* parent */ 2134193240Ssam PAGE_SIZE, 0, /* alignment, bounds */ 2135193240Ssam BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 2136193240Ssam BUS_SPACE_MAXADDR, /* highaddr */ 2137193240Ssam NULL, NULL, /* filter, filterarg */ 2138193240Ssam sc->sc_rxmemsize, /* maxsize */ 2139193240Ssam 1, /* nsegments */ 2140193240Ssam sc->sc_rxmemsize, /* maxsegsize */ 2141193240Ssam BUS_DMA_ALLOCNOW, /* flags */ 2142193240Ssam NULL, /* lockfunc */ 2143193240Ssam NULL, /* lockarg */ 2144193240Ssam &sc->sc_rxdmat); 2145193240Ssam if (error != 0) { 2146287197Sglebius device_printf(sc->sc_dev, "could not create rx DMA tag\n"); 2147193240Ssam return error; 2148193240Ssam } 2149193240Ssam 2150193240Ssam error = bus_dmamem_alloc(sc->sc_rxdmat, (void**) &sc->sc_rxmem, 2151193240Ssam BUS_DMA_NOWAIT | BUS_DMA_COHERENT, 2152193240Ssam &sc->sc_rxmap); 2153193240Ssam if (error != 0) { 2154287197Sglebius device_printf(sc->sc_dev, "could not alloc %ju bytes of rx DMA memory\n", 2155193240Ssam (uintmax_t) sc->sc_rxmemsize); 2156193240Ssam return error; 2157193240Ssam } 2158193240Ssam 2159193240Ssam error = bus_dmamap_load(sc->sc_rxdmat, sc->sc_rxmap, 2160193240Ssam sc->sc_rxmem, sc->sc_rxmemsize, 2161193240Ssam mwl_load_cb, &sc->sc_rxmem_paddr, 2162193240Ssam BUS_DMA_NOWAIT); 2163193240Ssam if (error != 0) { 2164287197Sglebius device_printf(sc->sc_dev, "could not load rx DMA map\n"); 2165193240Ssam return error; 2166193240Ssam } 2167193240Ssam 2168193240Ssam /* 2169193240Ssam * Allocate rx buffers and set them up. 2170193240Ssam */ 2171193240Ssam bsize = mwl_rxdesc * sizeof(struct mwl_rxbuf); 2172193240Ssam bf = malloc(bsize, M_MWLDEV, M_NOWAIT | M_ZERO); 2173193240Ssam if (bf == NULL) { 2174287197Sglebius device_printf(sc->sc_dev, "malloc of %u rx buffers failed\n", bsize); 2175193240Ssam return error; 2176193240Ssam } 2177193240Ssam sc->sc_rxdma.dd_bufptr = bf; 2178193240Ssam 2179193240Ssam STAILQ_INIT(&sc->sc_rxbuf); 2180193240Ssam ds = sc->sc_rxdma.dd_desc; 2181193240Ssam for (i = 0; i < mwl_rxdesc; i++, bf++, ds++) { 2182193240Ssam bf->bf_desc = ds; 2183193240Ssam bf->bf_daddr = DS2PHYS(&sc->sc_rxdma, ds); 2184193240Ssam /* pre-assign dma buffer */ 2185193240Ssam bf->bf_data = ((uint8_t *)sc->sc_rxmem) + (i*jumbosize); 2186193240Ssam /* NB: tail is intentional to preserve descriptor order */ 2187193240Ssam STAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 2188193240Ssam } 2189193240Ssam 2190193240Ssam /* 2191193240Ssam * Place remainder of dma memory buffers on the free list. 2192193240Ssam */ 2193193240Ssam SLIST_INIT(&sc->sc_rxfree); 2194193240Ssam for (; i < mwl_rxbuf; i++) { 2195193240Ssam data = ((uint8_t *)sc->sc_rxmem) + (i*jumbosize); 2196193240Ssam rbuf = MWL_JUMBO_DATA2BUF(data); 2197193240Ssam SLIST_INSERT_HEAD(&sc->sc_rxfree, rbuf, next); 2198193240Ssam sc->sc_nrxfree++; 2199193240Ssam } 2200193240Ssam return 0; 2201193240Ssam} 2202193240Ssam#undef DS2PHYS 2203193240Ssam 2204193240Ssamstatic void 2205193240Ssammwl_rxdma_cleanup(struct mwl_softc *sc) 2206193240Ssam{ 2207267340Sjhb if (sc->sc_rxmem_paddr != 0) { 2208193240Ssam bus_dmamap_unload(sc->sc_rxdmat, sc->sc_rxmap); 2209267340Sjhb sc->sc_rxmem_paddr = 0; 2210267340Sjhb } 2211193240Ssam if (sc->sc_rxmem != NULL) { 2212193240Ssam bus_dmamem_free(sc->sc_rxdmat, sc->sc_rxmem, sc->sc_rxmap); 2213193240Ssam sc->sc_rxmem = NULL; 2214193240Ssam } 2215193240Ssam if (sc->sc_rxdma.dd_bufptr != NULL) { 2216193240Ssam free(sc->sc_rxdma.dd_bufptr, M_MWLDEV); 2217193240Ssam sc->sc_rxdma.dd_bufptr = NULL; 2218193240Ssam } 2219193240Ssam if (sc->sc_rxdma.dd_desc_len != 0) 2220193240Ssam mwl_desc_cleanup(sc, &sc->sc_rxdma); 2221193240Ssam} 2222193240Ssam 2223193240Ssamstatic int 2224193240Ssammwl_dma_setup(struct mwl_softc *sc) 2225193240Ssam{ 2226193240Ssam int error, i; 2227193240Ssam 2228193240Ssam error = mwl_rxdma_setup(sc); 2229197307Srpaulo if (error != 0) { 2230197307Srpaulo mwl_rxdma_cleanup(sc); 2231193240Ssam return error; 2232197307Srpaulo } 2233193240Ssam 2234193240Ssam for (i = 0; i < MWL_NUM_TX_QUEUES; i++) { 2235193240Ssam error = mwl_txdma_setup(sc, &sc->sc_txq[i]); 2236193240Ssam if (error != 0) { 2237193240Ssam mwl_dma_cleanup(sc); 2238193240Ssam return error; 2239193240Ssam } 2240193240Ssam } 2241193240Ssam return 0; 2242193240Ssam} 2243193240Ssam 2244193240Ssamstatic void 2245193240Ssammwl_dma_cleanup(struct mwl_softc *sc) 2246193240Ssam{ 2247193240Ssam int i; 2248193240Ssam 2249193240Ssam for (i = 0; i < MWL_NUM_TX_QUEUES; i++) 2250193240Ssam mwl_txdma_cleanup(sc, &sc->sc_txq[i]); 2251193240Ssam mwl_rxdma_cleanup(sc); 2252193240Ssam} 2253193240Ssam 2254193240Ssamstatic struct ieee80211_node * 2255193240Ssammwl_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN]) 2256193240Ssam{ 2257193240Ssam struct ieee80211com *ic = vap->iv_ic; 2258287197Sglebius struct mwl_softc *sc = ic->ic_softc; 2259193240Ssam const size_t space = sizeof(struct mwl_node); 2260193240Ssam struct mwl_node *mn; 2261193240Ssam 2262193240Ssam mn = malloc(space, M_80211_NODE, M_NOWAIT|M_ZERO); 2263193240Ssam if (mn == NULL) { 2264193240Ssam /* XXX stat+msg */ 2265193240Ssam return NULL; 2266193240Ssam } 2267193240Ssam DPRINTF(sc, MWL_DEBUG_NODE, "%s: mn %p\n", __func__, mn); 2268193240Ssam return &mn->mn_node; 2269193240Ssam} 2270193240Ssam 2271193240Ssamstatic void 2272193240Ssammwl_node_cleanup(struct ieee80211_node *ni) 2273193240Ssam{ 2274193240Ssam struct ieee80211com *ic = ni->ni_ic; 2275287197Sglebius struct mwl_softc *sc = ic->ic_softc; 2276193240Ssam struct mwl_node *mn = MWL_NODE(ni); 2277193240Ssam 2278193240Ssam DPRINTF(sc, MWL_DEBUG_NODE, "%s: ni %p ic %p staid %d\n", 2279193240Ssam __func__, ni, ni->ni_ic, mn->mn_staid); 2280193240Ssam 2281193240Ssam if (mn->mn_staid != 0) { 2282193240Ssam struct ieee80211vap *vap = ni->ni_vap; 2283193240Ssam 2284193240Ssam if (mn->mn_hvap != NULL) { 2285193240Ssam if (vap->iv_opmode == IEEE80211_M_STA) 2286193240Ssam mwl_hal_delstation(mn->mn_hvap, vap->iv_myaddr); 2287193240Ssam else 2288193240Ssam mwl_hal_delstation(mn->mn_hvap, ni->ni_macaddr); 2289193240Ssam } 2290193240Ssam /* 2291193240Ssam * NB: legacy WDS peer sta db entry is installed using 2292193240Ssam * the associate ap's hvap; use it again to delete it. 2293193240Ssam * XXX can vap be NULL? 2294193240Ssam */ 2295193240Ssam else if (vap->iv_opmode == IEEE80211_M_WDS && 2296193240Ssam MWL_VAP(vap)->mv_ap_hvap != NULL) 2297193240Ssam mwl_hal_delstation(MWL_VAP(vap)->mv_ap_hvap, 2298193240Ssam ni->ni_macaddr); 2299193240Ssam delstaid(sc, mn->mn_staid); 2300193240Ssam mn->mn_staid = 0; 2301193240Ssam } 2302193240Ssam sc->sc_node_cleanup(ni); 2303193240Ssam} 2304193240Ssam 2305193240Ssam/* 2306193240Ssam * Reclaim rx dma buffers from packets sitting on the ampdu 2307193240Ssam * reorder queue for a station. We replace buffers with a 2308193240Ssam * system cluster (if available). 2309193240Ssam */ 2310193240Ssamstatic void 2311193240Ssammwl_ampdu_rxdma_reclaim(struct ieee80211_rx_ampdu *rap) 2312193240Ssam{ 2313193240Ssam#if 0 2314193240Ssam int i, n, off; 2315193240Ssam struct mbuf *m; 2316193240Ssam void *cl; 2317193240Ssam 2318193240Ssam n = rap->rxa_qframes; 2319193240Ssam for (i = 0; i < rap->rxa_wnd && n > 0; i++) { 2320193240Ssam m = rap->rxa_m[i]; 2321193240Ssam if (m == NULL) 2322193240Ssam continue; 2323193240Ssam n--; 2324193240Ssam /* our dma buffers have a well-known free routine */ 2325193240Ssam if ((m->m_flags & M_EXT) == 0 || 2326193240Ssam m->m_ext.ext_free != mwl_ext_free) 2327193240Ssam continue; 2328193240Ssam /* 2329193240Ssam * Try to allocate a cluster and move the data. 2330193240Ssam */ 2331193240Ssam off = m->m_data - m->m_ext.ext_buf; 2332193240Ssam if (off + m->m_pkthdr.len > MCLBYTES) { 2333193240Ssam /* XXX no AMSDU for now */ 2334193240Ssam continue; 2335193240Ssam } 2336193240Ssam cl = pool_cache_get_paddr(&mclpool_cache, 0, 2337193240Ssam &m->m_ext.ext_paddr); 2338193240Ssam if (cl != NULL) { 2339193240Ssam /* 2340193240Ssam * Copy the existing data to the cluster, remove 2341193240Ssam * the rx dma buffer, and attach the cluster in 2342193240Ssam * its place. Note we preserve the offset to the 2343193240Ssam * data so frames being bridged can still prepend 2344193240Ssam * their headers without adding another mbuf. 2345193240Ssam */ 2346193240Ssam memcpy((caddr_t) cl + off, m->m_data, m->m_pkthdr.len); 2347193240Ssam MEXTREMOVE(m); 2348193240Ssam MEXTADD(m, cl, MCLBYTES, 0, NULL, &mclpool_cache); 2349193240Ssam /* setup mbuf like _MCLGET does */ 2350193240Ssam m->m_flags |= M_CLUSTER | M_EXT_RW; 2351193240Ssam _MOWNERREF(m, M_EXT | M_CLUSTER); 2352193240Ssam /* NB: m_data is clobbered by MEXTADDR, adjust */ 2353193240Ssam m->m_data += off; 2354193240Ssam } 2355193240Ssam } 2356193240Ssam#endif 2357193240Ssam} 2358193240Ssam 2359193240Ssam/* 2360193240Ssam * Callback to reclaim resources. We first let the 2361193240Ssam * net80211 layer do it's thing, then if we are still 2362193240Ssam * blocked by a lack of rx dma buffers we walk the ampdu 2363193240Ssam * reorder q's to reclaim buffers by copying to a system 2364193240Ssam * cluster. 2365193240Ssam */ 2366193240Ssamstatic void 2367193240Ssammwl_node_drain(struct ieee80211_node *ni) 2368193240Ssam{ 2369193240Ssam struct ieee80211com *ic = ni->ni_ic; 2370287197Sglebius struct mwl_softc *sc = ic->ic_softc; 2371193240Ssam struct mwl_node *mn = MWL_NODE(ni); 2372193240Ssam 2373193240Ssam DPRINTF(sc, MWL_DEBUG_NODE, "%s: ni %p vap %p staid %d\n", 2374193240Ssam __func__, ni, ni->ni_vap, mn->mn_staid); 2375193240Ssam 2376193240Ssam /* NB: call up first to age out ampdu q's */ 2377193240Ssam sc->sc_node_drain(ni); 2378193240Ssam 2379193240Ssam /* XXX better to not check low water mark? */ 2380193240Ssam if (sc->sc_rxblocked && mn->mn_staid != 0 && 2381193240Ssam (ni->ni_flags & IEEE80211_NODE_HT)) { 2382193240Ssam uint8_t tid; 2383193240Ssam /* 2384193240Ssam * Walk the reorder q and reclaim rx dma buffers by copying 2385193240Ssam * the packet contents into clusters. 2386193240Ssam */ 2387193240Ssam for (tid = 0; tid < WME_NUM_TID; tid++) { 2388193240Ssam struct ieee80211_rx_ampdu *rap; 2389193240Ssam 2390193240Ssam rap = &ni->ni_rx_ampdu[tid]; 2391193240Ssam if ((rap->rxa_flags & IEEE80211_AGGR_XCHGPEND) == 0) 2392193240Ssam continue; 2393193240Ssam if (rap->rxa_qframes) 2394193240Ssam mwl_ampdu_rxdma_reclaim(rap); 2395193240Ssam } 2396193240Ssam } 2397193240Ssam} 2398193240Ssam 2399193240Ssamstatic void 2400193240Ssammwl_node_getsignal(const struct ieee80211_node *ni, int8_t *rssi, int8_t *noise) 2401193240Ssam{ 2402193240Ssam *rssi = ni->ni_ic->ic_node_getrssi(ni); 2403193240Ssam#ifdef MWL_ANT_INFO_SUPPORT 2404193240Ssam#if 0 2405193240Ssam /* XXX need to smooth data */ 2406193240Ssam *noise = -MWL_NODE_CONST(ni)->mn_ai.nf; 2407193240Ssam#else 2408193240Ssam *noise = -95; /* XXX */ 2409193240Ssam#endif 2410193240Ssam#else 2411193240Ssam *noise = -95; /* XXX */ 2412193240Ssam#endif 2413193240Ssam} 2414193240Ssam 2415193240Ssam/* 2416193240Ssam * Convert Hardware per-antenna rssi info to common format: 2417193240Ssam * Let a1, a2, a3 represent the amplitudes per chain 2418193240Ssam * Let amax represent max[a1, a2, a3] 2419193240Ssam * Rssi1_dBm = RSSI_dBm + 20*log10(a1/amax) 2420193240Ssam * Rssi1_dBm = RSSI_dBm + 20*log10(a1) - 20*log10(amax) 2421193240Ssam * We store a table that is 4*20*log10(idx) - the extra 4 is to store or 2422193240Ssam * maintain some extra precision. 2423193240Ssam * 2424193240Ssam * Values are stored in .5 db format capped at 127. 2425193240Ssam */ 2426193240Ssamstatic void 2427193240Ssammwl_node_getmimoinfo(const struct ieee80211_node *ni, 2428193240Ssam struct ieee80211_mimo_info *mi) 2429193240Ssam{ 2430193240Ssam#define CVT(_dst, _src) do { \ 2431193240Ssam (_dst) = rssi + ((logdbtbl[_src] - logdbtbl[rssi_max]) >> 2); \ 2432193240Ssam (_dst) = (_dst) > 64 ? 127 : ((_dst) << 1); \ 2433193240Ssam} while (0) 2434193240Ssam static const int8_t logdbtbl[32] = { 2435193240Ssam 0, 0, 24, 38, 48, 56, 62, 68, 2436193240Ssam 72, 76, 80, 83, 86, 89, 92, 94, 2437193240Ssam 96, 98, 100, 102, 104, 106, 107, 109, 2438193240Ssam 110, 112, 113, 115, 116, 117, 118, 119 2439193240Ssam }; 2440193240Ssam const struct mwl_node *mn = MWL_NODE_CONST(ni); 2441193240Ssam uint8_t rssi = mn->mn_ai.rsvd1/2; /* XXX */ 2442193240Ssam uint32_t rssi_max; 2443193240Ssam 2444193240Ssam rssi_max = mn->mn_ai.rssi_a; 2445193240Ssam if (mn->mn_ai.rssi_b > rssi_max) 2446193240Ssam rssi_max = mn->mn_ai.rssi_b; 2447193240Ssam if (mn->mn_ai.rssi_c > rssi_max) 2448193240Ssam rssi_max = mn->mn_ai.rssi_c; 2449193240Ssam 2450220935Sadrian CVT(mi->rssi[0], mn->mn_ai.rssi_a); 2451220935Sadrian CVT(mi->rssi[1], mn->mn_ai.rssi_b); 2452220935Sadrian CVT(mi->rssi[2], mn->mn_ai.rssi_c); 2453193240Ssam 2454220935Sadrian mi->noise[0] = mn->mn_ai.nf_a; 2455220935Sadrian mi->noise[1] = mn->mn_ai.nf_b; 2456220935Sadrian mi->noise[2] = mn->mn_ai.nf_c; 2457193240Ssam#undef CVT 2458193240Ssam} 2459193240Ssam 2460193240Ssamstatic __inline void * 2461193240Ssammwl_getrxdma(struct mwl_softc *sc) 2462193240Ssam{ 2463193240Ssam struct mwl_jumbo *buf; 2464193240Ssam void *data; 2465193240Ssam 2466193240Ssam /* 2467193240Ssam * Allocate from jumbo pool. 2468193240Ssam */ 2469193240Ssam MWL_RXFREE_LOCK(sc); 2470193240Ssam buf = SLIST_FIRST(&sc->sc_rxfree); 2471193240Ssam if (buf == NULL) { 2472193240Ssam DPRINTF(sc, MWL_DEBUG_ANY, 2473193240Ssam "%s: out of rx dma buffers\n", __func__); 2474193240Ssam sc->sc_stats.mst_rx_nodmabuf++; 2475193240Ssam data = NULL; 2476193240Ssam } else { 2477193240Ssam SLIST_REMOVE_HEAD(&sc->sc_rxfree, next); 2478193240Ssam sc->sc_nrxfree--; 2479193240Ssam data = MWL_JUMBO_BUF2DATA(buf); 2480193240Ssam } 2481193240Ssam MWL_RXFREE_UNLOCK(sc); 2482193240Ssam return data; 2483193240Ssam} 2484193240Ssam 2485193240Ssamstatic __inline void 2486193240Ssammwl_putrxdma(struct mwl_softc *sc, void *data) 2487193240Ssam{ 2488193240Ssam struct mwl_jumbo *buf; 2489193240Ssam 2490193240Ssam /* XXX bounds check data */ 2491193240Ssam MWL_RXFREE_LOCK(sc); 2492193240Ssam buf = MWL_JUMBO_DATA2BUF(data); 2493193240Ssam SLIST_INSERT_HEAD(&sc->sc_rxfree, buf, next); 2494193240Ssam sc->sc_nrxfree++; 2495193240Ssam MWL_RXFREE_UNLOCK(sc); 2496193240Ssam} 2497193240Ssam 2498193240Ssamstatic int 2499193240Ssammwl_rxbuf_init(struct mwl_softc *sc, struct mwl_rxbuf *bf) 2500193240Ssam{ 2501193240Ssam struct mwl_rxdesc *ds; 2502193240Ssam 2503193240Ssam ds = bf->bf_desc; 2504193240Ssam if (bf->bf_data == NULL) { 2505193240Ssam bf->bf_data = mwl_getrxdma(sc); 2506193240Ssam if (bf->bf_data == NULL) { 2507193240Ssam /* mark descriptor to be skipped */ 2508193240Ssam ds->RxControl = EAGLE_RXD_CTRL_OS_OWN; 2509193240Ssam /* NB: don't need PREREAD */ 2510193240Ssam MWL_RXDESC_SYNC(sc, ds, BUS_DMASYNC_PREWRITE); 2511193240Ssam sc->sc_stats.mst_rxbuf_failed++; 2512193240Ssam return ENOMEM; 2513193240Ssam } 2514193240Ssam } 2515193240Ssam /* 2516193240Ssam * NB: DMA buffer contents is known to be unmodified 2517193240Ssam * so there's no need to flush the data cache. 2518193240Ssam */ 2519193240Ssam 2520193240Ssam /* 2521193240Ssam * Setup descriptor. 2522193240Ssam */ 2523193240Ssam ds->QosCtrl = 0; 2524193240Ssam ds->RSSI = 0; 2525193240Ssam ds->Status = EAGLE_RXD_STATUS_IDLE; 2526193240Ssam ds->Channel = 0; 2527193240Ssam ds->PktLen = htole16(MWL_AGGR_SIZE); 2528193240Ssam ds->SQ2 = 0; 2529193240Ssam ds->pPhysBuffData = htole32(MWL_JUMBO_DMA_ADDR(sc, bf->bf_data)); 2530193240Ssam /* NB: don't touch pPhysNext, set once */ 2531193240Ssam ds->RxControl = EAGLE_RXD_CTRL_DRIVER_OWN; 2532193240Ssam MWL_RXDESC_SYNC(sc, ds, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2533193240Ssam 2534193240Ssam return 0; 2535193240Ssam} 2536193240Ssam 2537268529Sglebiusstatic void 2538254799Sandremwl_ext_free(struct mbuf *m, void *data, void *arg) 2539193240Ssam{ 2540193240Ssam struct mwl_softc *sc = arg; 2541193240Ssam 2542193240Ssam /* XXX bounds check data */ 2543193240Ssam mwl_putrxdma(sc, data); 2544193240Ssam /* 2545193240Ssam * If we were previously blocked by a lack of rx dma buffers 2546193240Ssam * check if we now have enough to restart rx interrupt handling. 2547193240Ssam * NB: we know we are called at splvm which is above splnet. 2548193240Ssam */ 2549193240Ssam if (sc->sc_rxblocked && sc->sc_nrxfree > mwl_rxdmalow) { 2550193240Ssam sc->sc_rxblocked = 0; 2551193240Ssam mwl_hal_intrset(sc->sc_mh, sc->sc_imask); 2552193240Ssam } 2553193240Ssam} 2554193240Ssam 2555193240Ssamstruct mwl_frame_bar { 2556193240Ssam u_int8_t i_fc[2]; 2557193240Ssam u_int8_t i_dur[2]; 2558193240Ssam u_int8_t i_ra[IEEE80211_ADDR_LEN]; 2559193240Ssam u_int8_t i_ta[IEEE80211_ADDR_LEN]; 2560193240Ssam /* ctl, seq, FCS */ 2561193240Ssam} __packed; 2562193240Ssam 2563193240Ssam/* 2564193240Ssam * Like ieee80211_anyhdrsize, but handles BAR frames 2565193240Ssam * specially so the logic below to piece the 802.11 2566193240Ssam * header together works. 2567193240Ssam */ 2568193240Ssamstatic __inline int 2569193240Ssammwl_anyhdrsize(const void *data) 2570193240Ssam{ 2571193240Ssam const struct ieee80211_frame *wh = data; 2572193240Ssam 2573193240Ssam if ((wh->i_fc[0]&IEEE80211_FC0_TYPE_MASK) == IEEE80211_FC0_TYPE_CTL) { 2574193240Ssam switch (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) { 2575193240Ssam case IEEE80211_FC0_SUBTYPE_CTS: 2576193240Ssam case IEEE80211_FC0_SUBTYPE_ACK: 2577193240Ssam return sizeof(struct ieee80211_frame_ack); 2578193240Ssam case IEEE80211_FC0_SUBTYPE_BAR: 2579193240Ssam return sizeof(struct mwl_frame_bar); 2580193240Ssam } 2581193240Ssam return sizeof(struct ieee80211_frame_min); 2582193240Ssam } else 2583193240Ssam return ieee80211_hdrsize(data); 2584193240Ssam} 2585193240Ssam 2586193240Ssamstatic void 2587193240Ssammwl_handlemicerror(struct ieee80211com *ic, const uint8_t *data) 2588193240Ssam{ 2589193240Ssam const struct ieee80211_frame *wh; 2590193240Ssam struct ieee80211_node *ni; 2591193240Ssam 2592193240Ssam wh = (const struct ieee80211_frame *)(data + sizeof(uint16_t)); 2593193240Ssam ni = ieee80211_find_rxnode(ic, (const struct ieee80211_frame_min *) wh); 2594193240Ssam if (ni != NULL) { 2595193240Ssam ieee80211_notify_michael_failure(ni->ni_vap, wh, 0); 2596193240Ssam ieee80211_free_node(ni); 2597193240Ssam } 2598193240Ssam} 2599193240Ssam 2600193240Ssam/* 2601193240Ssam * Convert hardware signal strength to rssi. The value 2602193240Ssam * provided by the device has the noise floor added in; 2603193240Ssam * we need to compensate for this but we don't have that 2604193240Ssam * so we use a fixed value. 2605193240Ssam * 2606193240Ssam * The offset of 8 is good for both 2.4 and 5GHz. The LNA 2607193240Ssam * offset is already set as part of the initial gain. This 2608193240Ssam * will give at least +/- 3dB for 2.4GHz and +/- 5dB for 5GHz. 2609193240Ssam */ 2610193240Ssamstatic __inline int 2611193240Ssamcvtrssi(uint8_t ssi) 2612193240Ssam{ 2613193240Ssam int rssi = (int) ssi + 8; 2614193240Ssam /* XXX hack guess until we have a real noise floor */ 2615193240Ssam rssi = 2*(87 - rssi); /* NB: .5 dBm units */ 2616193240Ssam return (rssi < 0 ? 0 : rssi > 127 ? 127 : rssi); 2617193240Ssam} 2618193240Ssam 2619193240Ssamstatic void 2620193240Ssammwl_rx_proc(void *arg, int npending) 2621193240Ssam{ 2622193240Ssam#define IEEE80211_DIR_DSTODS(wh) \ 2623193240Ssam ((((const struct ieee80211_frame *)wh)->i_fc[1] & IEEE80211_FC1_DIR_MASK) == IEEE80211_FC1_DIR_DSTODS) 2624193240Ssam struct mwl_softc *sc = arg; 2625287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 2626193240Ssam struct mwl_rxbuf *bf; 2627193240Ssam struct mwl_rxdesc *ds; 2628193240Ssam struct mbuf *m; 2629193240Ssam struct ieee80211_qosframe *wh; 2630193240Ssam struct ieee80211_qosframe_addr4 *wh4; 2631193240Ssam struct ieee80211_node *ni; 2632193240Ssam struct mwl_node *mn; 2633193240Ssam int off, len, hdrlen, pktlen, rssi, ntodo; 2634193240Ssam uint8_t *data, status; 2635193240Ssam void *newdata; 2636193240Ssam int16_t nf; 2637193240Ssam 2638193240Ssam DPRINTF(sc, MWL_DEBUG_RX_PROC, "%s: pending %u rdptr 0x%x wrptr 0x%x\n", 2639193240Ssam __func__, npending, RD4(sc, sc->sc_hwspecs.rxDescRead), 2640193240Ssam RD4(sc, sc->sc_hwspecs.rxDescWrite)); 2641193240Ssam nf = -96; /* XXX */ 2642193240Ssam bf = sc->sc_rxnext; 2643193240Ssam for (ntodo = mwl_rxquota; ntodo > 0; ntodo--) { 2644193240Ssam if (bf == NULL) 2645193240Ssam bf = STAILQ_FIRST(&sc->sc_rxbuf); 2646193240Ssam ds = bf->bf_desc; 2647193240Ssam data = bf->bf_data; 2648193240Ssam if (data == NULL) { 2649193240Ssam /* 2650193240Ssam * If data allocation failed previously there 2651193240Ssam * will be no buffer; try again to re-populate it. 2652193240Ssam * Note the firmware will not advance to the next 2653193240Ssam * descriptor with a dma buffer so we must mimic 2654193240Ssam * this or we'll get out of sync. 2655193240Ssam */ 2656193240Ssam DPRINTF(sc, MWL_DEBUG_ANY, 2657193240Ssam "%s: rx buf w/o dma memory\n", __func__); 2658193240Ssam (void) mwl_rxbuf_init(sc, bf); 2659193240Ssam sc->sc_stats.mst_rx_dmabufmissing++; 2660193240Ssam break; 2661193240Ssam } 2662193240Ssam MWL_RXDESC_SYNC(sc, ds, 2663193240Ssam BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2664193240Ssam if (ds->RxControl != EAGLE_RXD_CTRL_DMA_OWN) 2665193240Ssam break; 2666193240Ssam#ifdef MWL_DEBUG 2667193240Ssam if (sc->sc_debug & MWL_DEBUG_RECV_DESC) 2668193240Ssam mwl_printrxbuf(bf, 0); 2669193240Ssam#endif 2670193240Ssam status = ds->Status; 2671193240Ssam if (status & EAGLE_RXD_STATUS_DECRYPT_ERR_MASK) { 2672287197Sglebius counter_u64_add(ic->ic_ierrors, 1); 2673193240Ssam sc->sc_stats.mst_rx_crypto++; 2674193240Ssam /* 2675193240Ssam * NB: Check EAGLE_RXD_STATUS_GENERAL_DECRYPT_ERR 2676193240Ssam * for backwards compatibility. 2677193240Ssam */ 2678193240Ssam if (status != EAGLE_RXD_STATUS_GENERAL_DECRYPT_ERR && 2679193240Ssam (status & EAGLE_RXD_STATUS_TKIP_MIC_DECRYPT_ERR)) { 2680193240Ssam /* 2681193240Ssam * MIC error, notify upper layers. 2682193240Ssam */ 2683193240Ssam bus_dmamap_sync(sc->sc_rxdmat, sc->sc_rxmap, 2684193240Ssam BUS_DMASYNC_POSTREAD); 2685193240Ssam mwl_handlemicerror(ic, data); 2686193240Ssam sc->sc_stats.mst_rx_tkipmic++; 2687193240Ssam } 2688193240Ssam /* XXX too painful to tap packets */ 2689193240Ssam goto rx_next; 2690193240Ssam } 2691193240Ssam /* 2692193240Ssam * Sync the data buffer. 2693193240Ssam */ 2694193240Ssam len = le16toh(ds->PktLen); 2695193240Ssam bus_dmamap_sync(sc->sc_rxdmat, sc->sc_rxmap, BUS_DMASYNC_POSTREAD); 2696193240Ssam /* 2697193240Ssam * The 802.11 header is provided all or in part at the front; 2698193240Ssam * use it to calculate the true size of the header that we'll 2699193240Ssam * construct below. We use this to figure out where to copy 2700193240Ssam * payload prior to constructing the header. 2701193240Ssam */ 2702193240Ssam hdrlen = mwl_anyhdrsize(data + sizeof(uint16_t)); 2703193240Ssam off = sizeof(uint16_t) + sizeof(struct ieee80211_frame_addr4); 2704193240Ssam 2705193240Ssam /* calculate rssi early so we can re-use for each aggregate */ 2706193240Ssam rssi = cvtrssi(ds->RSSI); 2707193240Ssam 2708193240Ssam pktlen = hdrlen + (len - off); 2709193240Ssam /* 2710193240Ssam * NB: we know our frame is at least as large as 2711193240Ssam * IEEE80211_MIN_LEN because there is a 4-address 2712193240Ssam * frame at the front. Hence there's no need to 2713193240Ssam * vet the packet length. If the frame in fact 2714193240Ssam * is too small it should be discarded at the 2715193240Ssam * net80211 layer. 2716193240Ssam */ 2717193240Ssam 2718193240Ssam /* 2719193240Ssam * Attach dma buffer to an mbuf. We tried 2720193240Ssam * doing this based on the packet size (i.e. 2721193240Ssam * copying small packets) but it turns out to 2722193240Ssam * be a net loss. The tradeoff might be system 2723193240Ssam * dependent (cache architecture is important). 2724193240Ssam */ 2725243857Sglebius MGETHDR(m, M_NOWAIT, MT_DATA); 2726193240Ssam if (m == NULL) { 2727193240Ssam DPRINTF(sc, MWL_DEBUG_ANY, 2728193240Ssam "%s: no rx mbuf\n", __func__); 2729193240Ssam sc->sc_stats.mst_rx_nombuf++; 2730193240Ssam goto rx_next; 2731193240Ssam } 2732193240Ssam /* 2733193240Ssam * Acquire the replacement dma buffer before 2734193240Ssam * processing the frame. If we're out of dma 2735193240Ssam * buffers we disable rx interrupts and wait 2736193240Ssam * for the free pool to reach mlw_rxdmalow buffers 2737193240Ssam * before starting to do work again. If the firmware 2738193240Ssam * runs out of descriptors then it will toss frames 2739193240Ssam * which is better than our doing it as that can 2740193240Ssam * starve our processing. It is also important that 2741193240Ssam * we always process rx'd frames in case they are 2742193240Ssam * A-MPDU as otherwise the host's view of the BA 2743193240Ssam * window may get out of sync with the firmware. 2744193240Ssam */ 2745193240Ssam newdata = mwl_getrxdma(sc); 2746193240Ssam if (newdata == NULL) { 2747193240Ssam /* NB: stat+msg in mwl_getrxdma */ 2748193240Ssam m_free(m); 2749193240Ssam /* disable RX interrupt and mark state */ 2750193240Ssam mwl_hal_intrset(sc->sc_mh, 2751193240Ssam sc->sc_imask &~ MACREG_A2HRIC_BIT_RX_RDY); 2752193240Ssam sc->sc_rxblocked = 1; 2753193240Ssam ieee80211_drain(ic); 2754193240Ssam /* XXX check rxblocked and immediately start again? */ 2755193240Ssam goto rx_stop; 2756193240Ssam } 2757193240Ssam bf->bf_data = newdata; 2758193240Ssam /* 2759193240Ssam * Attach the dma buffer to the mbuf; 2760193240Ssam * mwl_rxbuf_init will re-setup the rx 2761193240Ssam * descriptor using the replacement dma 2762193240Ssam * buffer we just installed above. 2763193240Ssam */ 2764193240Ssam MEXTADD(m, data, MWL_AGGR_SIZE, mwl_ext_free, 2765193240Ssam data, sc, 0, EXT_NET_DRV); 2766193240Ssam m->m_data += off - hdrlen; 2767193240Ssam m->m_pkthdr.len = m->m_len = pktlen; 2768193240Ssam /* NB: dma buffer assumed read-only */ 2769193240Ssam 2770193240Ssam /* 2771193240Ssam * Piece 802.11 header together. 2772193240Ssam */ 2773193240Ssam wh = mtod(m, struct ieee80211_qosframe *); 2774193240Ssam /* NB: don't need to do this sometimes but ... */ 2775193240Ssam /* XXX special case so we can memcpy after m_devget? */ 2776193240Ssam ovbcopy(data + sizeof(uint16_t), wh, hdrlen); 2777193240Ssam if (IEEE80211_QOS_HAS_SEQ(wh)) { 2778193240Ssam if (IEEE80211_DIR_DSTODS(wh)) { 2779193240Ssam wh4 = mtod(m, 2780193240Ssam struct ieee80211_qosframe_addr4*); 2781193240Ssam *(uint16_t *)wh4->i_qos = ds->QosCtrl; 2782193240Ssam } else { 2783193240Ssam *(uint16_t *)wh->i_qos = ds->QosCtrl; 2784193240Ssam } 2785193240Ssam } 2786193240Ssam /* 2787193240Ssam * The f/w strips WEP header but doesn't clear 2788193240Ssam * the WEP bit; mark the packet with M_WEP so 2789193240Ssam * net80211 will treat the data as decrypted. 2790193240Ssam * While here also clear the PWR_MGT bit since 2791193240Ssam * power save is handled by the firmware and 2792193240Ssam * passing this up will potentially cause the 2793193240Ssam * upper layer to put a station in power save 2794193240Ssam * (except when configured with MWL_HOST_PS_SUPPORT). 2795193240Ssam */ 2796260444Skevlo if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) 2797193240Ssam m->m_flags |= M_WEP; 2798193240Ssam#ifdef MWL_HOST_PS_SUPPORT 2799260444Skevlo wh->i_fc[1] &= ~IEEE80211_FC1_PROTECTED; 2800193240Ssam#else 2801260444Skevlo wh->i_fc[1] &= ~(IEEE80211_FC1_PROTECTED | 2802260444Skevlo IEEE80211_FC1_PWR_MGT); 2803193240Ssam#endif 2804193240Ssam 2805193240Ssam if (ieee80211_radiotap_active(ic)) { 2806193240Ssam struct mwl_rx_radiotap_header *tap = &sc->sc_rx_th; 2807193240Ssam 2808193240Ssam tap->wr_flags = 0; 2809193240Ssam tap->wr_rate = ds->Rate; 2810193240Ssam tap->wr_antsignal = rssi + nf; 2811193240Ssam tap->wr_antnoise = nf; 2812193240Ssam } 2813193240Ssam if (IFF_DUMPPKTS_RECV(sc, wh)) { 2814193240Ssam ieee80211_dump_pkt(ic, mtod(m, caddr_t), 2815193240Ssam len, ds->Rate, rssi); 2816193240Ssam } 2817193240Ssam /* dispatch */ 2818193240Ssam ni = ieee80211_find_rxnode(ic, 2819193240Ssam (const struct ieee80211_frame_min *) wh); 2820193240Ssam if (ni != NULL) { 2821193240Ssam mn = MWL_NODE(ni); 2822193240Ssam#ifdef MWL_ANT_INFO_SUPPORT 2823193240Ssam mn->mn_ai.rssi_a = ds->ai.rssi_a; 2824193240Ssam mn->mn_ai.rssi_b = ds->ai.rssi_b; 2825193240Ssam mn->mn_ai.rssi_c = ds->ai.rssi_c; 2826193240Ssam mn->mn_ai.rsvd1 = rssi; 2827193240Ssam#endif 2828193240Ssam /* tag AMPDU aggregates for reorder processing */ 2829193240Ssam if (ni->ni_flags & IEEE80211_NODE_HT) 2830193240Ssam m->m_flags |= M_AMPDU; 2831193240Ssam (void) ieee80211_input(ni, m, rssi, nf); 2832193240Ssam ieee80211_free_node(ni); 2833193240Ssam } else 2834193240Ssam (void) ieee80211_input_all(ic, m, rssi, nf); 2835193240Ssamrx_next: 2836193240Ssam /* NB: ignore ENOMEM so we process more descriptors */ 2837193240Ssam (void) mwl_rxbuf_init(sc, bf); 2838193240Ssam bf = STAILQ_NEXT(bf, bf_list); 2839193240Ssam } 2840193240Ssamrx_stop: 2841193240Ssam sc->sc_rxnext = bf; 2842193240Ssam 2843287197Sglebius if (mbufq_first(&sc->sc_snd) != NULL) { 2844193240Ssam /* NB: kick fw; the tx thread may have been preempted */ 2845193240Ssam mwl_hal_txstart(sc->sc_mh, 0); 2846287197Sglebius mwl_start(sc); 2847193240Ssam } 2848193240Ssam#undef IEEE80211_DIR_DSTODS 2849193240Ssam} 2850193240Ssam 2851193240Ssamstatic void 2852193240Ssammwl_txq_init(struct mwl_softc *sc, struct mwl_txq *txq, int qnum) 2853193240Ssam{ 2854193240Ssam struct mwl_txbuf *bf, *bn; 2855193240Ssam struct mwl_txdesc *ds; 2856193240Ssam 2857193240Ssam MWL_TXQ_LOCK_INIT(sc, txq); 2858193240Ssam txq->qnum = qnum; 2859193240Ssam txq->txpri = 0; /* XXX */ 2860193240Ssam#if 0 2861193240Ssam /* NB: q setup by mwl_txdma_setup XXX */ 2862193240Ssam STAILQ_INIT(&txq->free); 2863193240Ssam#endif 2864193240Ssam STAILQ_FOREACH(bf, &txq->free, bf_list) { 2865193240Ssam bf->bf_txq = txq; 2866193240Ssam 2867193240Ssam ds = bf->bf_desc; 2868193240Ssam bn = STAILQ_NEXT(bf, bf_list); 2869193240Ssam if (bn == NULL) 2870193240Ssam bn = STAILQ_FIRST(&txq->free); 2871193240Ssam ds->pPhysNext = htole32(bn->bf_daddr); 2872193240Ssam } 2873193240Ssam STAILQ_INIT(&txq->active); 2874193240Ssam} 2875193240Ssam 2876193240Ssam/* 2877193240Ssam * Setup a hardware data transmit queue for the specified 2878193240Ssam * access control. We record the mapping from ac's 2879193240Ssam * to h/w queues for use by mwl_tx_start. 2880193240Ssam */ 2881193240Ssamstatic int 2882193240Ssammwl_tx_setup(struct mwl_softc *sc, int ac, int mvtype) 2883193240Ssam{ 2884193240Ssam#define N(a) (sizeof(a)/sizeof(a[0])) 2885193240Ssam struct mwl_txq *txq; 2886193240Ssam 2887193240Ssam if (ac >= N(sc->sc_ac2q)) { 2888193240Ssam device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n", 2889193240Ssam ac, N(sc->sc_ac2q)); 2890193240Ssam return 0; 2891193240Ssam } 2892193240Ssam if (mvtype >= MWL_NUM_TX_QUEUES) { 2893193240Ssam device_printf(sc->sc_dev, "mvtype %u out of range, max %u!\n", 2894193240Ssam mvtype, MWL_NUM_TX_QUEUES); 2895193240Ssam return 0; 2896193240Ssam } 2897193240Ssam txq = &sc->sc_txq[mvtype]; 2898193240Ssam mwl_txq_init(sc, txq, mvtype); 2899193240Ssam sc->sc_ac2q[ac] = txq; 2900193240Ssam return 1; 2901193240Ssam#undef N 2902193240Ssam} 2903193240Ssam 2904193240Ssam/* 2905193240Ssam * Update WME parameters for a transmit queue. 2906193240Ssam */ 2907193240Ssamstatic int 2908193240Ssammwl_txq_update(struct mwl_softc *sc, int ac) 2909193240Ssam{ 2910193240Ssam#define MWL_EXPONENT_TO_VALUE(v) ((1<<v)-1) 2911287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 2912193240Ssam struct mwl_txq *txq = sc->sc_ac2q[ac]; 2913193240Ssam struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 2914193240Ssam struct mwl_hal *mh = sc->sc_mh; 2915193240Ssam int aifs, cwmin, cwmax, txoplim; 2916193240Ssam 2917193240Ssam aifs = wmep->wmep_aifsn; 2918193240Ssam /* XXX in sta mode need to pass log values for cwmin/max */ 2919193240Ssam cwmin = MWL_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 2920193240Ssam cwmax = MWL_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 2921193240Ssam txoplim = wmep->wmep_txopLimit; /* NB: units of 32us */ 2922193240Ssam 2923193240Ssam if (mwl_hal_setedcaparams(mh, txq->qnum, cwmin, cwmax, aifs, txoplim)) { 2924193240Ssam device_printf(sc->sc_dev, "unable to update hardware queue " 2925193240Ssam "parameters for %s traffic!\n", 2926193240Ssam ieee80211_wme_acnames[ac]); 2927193240Ssam return 0; 2928193240Ssam } 2929193240Ssam return 1; 2930193240Ssam#undef MWL_EXPONENT_TO_VALUE 2931193240Ssam} 2932193240Ssam 2933193240Ssam/* 2934193240Ssam * Callback from the 802.11 layer to update WME parameters. 2935193240Ssam */ 2936193240Ssamstatic int 2937193240Ssammwl_wme_update(struct ieee80211com *ic) 2938193240Ssam{ 2939287197Sglebius struct mwl_softc *sc = ic->ic_softc; 2940193240Ssam 2941193240Ssam return !mwl_txq_update(sc, WME_AC_BE) || 2942193240Ssam !mwl_txq_update(sc, WME_AC_BK) || 2943193240Ssam !mwl_txq_update(sc, WME_AC_VI) || 2944193240Ssam !mwl_txq_update(sc, WME_AC_VO) ? EIO : 0; 2945193240Ssam} 2946193240Ssam 2947193240Ssam/* 2948193240Ssam * Reclaim resources for a setup queue. 2949193240Ssam */ 2950193240Ssamstatic void 2951193240Ssammwl_tx_cleanupq(struct mwl_softc *sc, struct mwl_txq *txq) 2952193240Ssam{ 2953193240Ssam /* XXX hal work? */ 2954193240Ssam MWL_TXQ_LOCK_DESTROY(txq); 2955193240Ssam} 2956193240Ssam 2957193240Ssam/* 2958193240Ssam * Reclaim all tx queue resources. 2959193240Ssam */ 2960193240Ssamstatic void 2961193240Ssammwl_tx_cleanup(struct mwl_softc *sc) 2962193240Ssam{ 2963193240Ssam int i; 2964193240Ssam 2965193240Ssam for (i = 0; i < MWL_NUM_TX_QUEUES; i++) 2966193240Ssam mwl_tx_cleanupq(sc, &sc->sc_txq[i]); 2967193240Ssam} 2968193240Ssam 2969193240Ssamstatic int 2970193240Ssammwl_tx_dmasetup(struct mwl_softc *sc, struct mwl_txbuf *bf, struct mbuf *m0) 2971193240Ssam{ 2972193240Ssam struct mbuf *m; 2973193240Ssam int error; 2974193240Ssam 2975193240Ssam /* 2976193240Ssam * Load the DMA map so any coalescing is done. This 2977193240Ssam * also calculates the number of descriptors we need. 2978193240Ssam */ 2979193240Ssam error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0, 2980193240Ssam bf->bf_segs, &bf->bf_nseg, 2981193240Ssam BUS_DMA_NOWAIT); 2982193240Ssam if (error == EFBIG) { 2983193240Ssam /* XXX packet requires too many descriptors */ 2984193240Ssam bf->bf_nseg = MWL_TXDESC+1; 2985193240Ssam } else if (error != 0) { 2986193240Ssam sc->sc_stats.mst_tx_busdma++; 2987193240Ssam m_freem(m0); 2988193240Ssam return error; 2989193240Ssam } 2990193240Ssam /* 2991193240Ssam * Discard null packets and check for packets that 2992193240Ssam * require too many TX descriptors. We try to convert 2993193240Ssam * the latter to a cluster. 2994193240Ssam */ 2995193240Ssam if (error == EFBIG) { /* too many desc's, linearize */ 2996193240Ssam sc->sc_stats.mst_tx_linear++; 2997193240Ssam#if MWL_TXDESC > 1 2998243857Sglebius m = m_collapse(m0, M_NOWAIT, MWL_TXDESC); 2999193240Ssam#else 3000243857Sglebius m = m_defrag(m0, M_NOWAIT); 3001193240Ssam#endif 3002193240Ssam if (m == NULL) { 3003193240Ssam m_freem(m0); 3004193240Ssam sc->sc_stats.mst_tx_nombuf++; 3005193240Ssam return ENOMEM; 3006193240Ssam } 3007193240Ssam m0 = m; 3008193240Ssam error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0, 3009193240Ssam bf->bf_segs, &bf->bf_nseg, 3010193240Ssam BUS_DMA_NOWAIT); 3011193240Ssam if (error != 0) { 3012193240Ssam sc->sc_stats.mst_tx_busdma++; 3013193240Ssam m_freem(m0); 3014193240Ssam return error; 3015193240Ssam } 3016193240Ssam KASSERT(bf->bf_nseg <= MWL_TXDESC, 3017193240Ssam ("too many segments after defrag; nseg %u", bf->bf_nseg)); 3018193240Ssam } else if (bf->bf_nseg == 0) { /* null packet, discard */ 3019193240Ssam sc->sc_stats.mst_tx_nodata++; 3020193240Ssam m_freem(m0); 3021193240Ssam return EIO; 3022193240Ssam } 3023193240Ssam DPRINTF(sc, MWL_DEBUG_XMIT, "%s: m %p len %u\n", 3024193240Ssam __func__, m0, m0->m_pkthdr.len); 3025193240Ssam bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 3026193240Ssam bf->bf_m = m0; 3027193240Ssam 3028193240Ssam return 0; 3029193240Ssam} 3030193240Ssam 3031193240Ssamstatic __inline int 3032193240Ssammwl_cvtlegacyrate(int rate) 3033193240Ssam{ 3034193240Ssam switch (rate) { 3035193240Ssam case 2: return 0; 3036193240Ssam case 4: return 1; 3037193240Ssam case 11: return 2; 3038193240Ssam case 22: return 3; 3039193240Ssam case 44: return 4; 3040193240Ssam case 12: return 5; 3041193240Ssam case 18: return 6; 3042193240Ssam case 24: return 7; 3043193240Ssam case 36: return 8; 3044193240Ssam case 48: return 9; 3045193240Ssam case 72: return 10; 3046193240Ssam case 96: return 11; 3047193240Ssam case 108:return 12; 3048193240Ssam } 3049193240Ssam return 0; 3050193240Ssam} 3051193240Ssam 3052193240Ssam/* 3053193240Ssam * Calculate fixed tx rate information per client state; 3054193240Ssam * this value is suitable for writing to the Format field 3055193240Ssam * of a tx descriptor. 3056193240Ssam */ 3057193240Ssamstatic uint16_t 3058193240Ssammwl_calcformat(uint8_t rate, const struct ieee80211_node *ni) 3059193240Ssam{ 3060193240Ssam uint16_t fmt; 3061193240Ssam 3062193240Ssam fmt = SM(3, EAGLE_TXD_ANTENNA) 3063193240Ssam | (IEEE80211_IS_CHAN_HT40D(ni->ni_chan) ? 3064193240Ssam EAGLE_TXD_EXTCHAN_LO : EAGLE_TXD_EXTCHAN_HI); 3065195171Ssam if (rate & IEEE80211_RATE_MCS) { /* HT MCS */ 3066193240Ssam fmt |= EAGLE_TXD_FORMAT_HT 3067193240Ssam /* NB: 0x80 implicitly stripped from ucastrate */ 3068193240Ssam | SM(rate, EAGLE_TXD_RATE); 3069193240Ssam /* XXX short/long GI may be wrong; re-check */ 3070193240Ssam if (IEEE80211_IS_CHAN_HT40(ni->ni_chan)) { 3071193240Ssam fmt |= EAGLE_TXD_CHW_40 3072193240Ssam | (ni->ni_htcap & IEEE80211_HTCAP_SHORTGI40 ? 3073193240Ssam EAGLE_TXD_GI_SHORT : EAGLE_TXD_GI_LONG); 3074193240Ssam } else { 3075193240Ssam fmt |= EAGLE_TXD_CHW_20 3076193240Ssam | (ni->ni_htcap & IEEE80211_HTCAP_SHORTGI20 ? 3077193240Ssam EAGLE_TXD_GI_SHORT : EAGLE_TXD_GI_LONG); 3078193240Ssam } 3079193240Ssam } else { /* legacy rate */ 3080193240Ssam fmt |= EAGLE_TXD_FORMAT_LEGACY 3081193240Ssam | SM(mwl_cvtlegacyrate(rate), EAGLE_TXD_RATE) 3082193240Ssam | EAGLE_TXD_CHW_20 3083193240Ssam /* XXX iv_flags & IEEE80211_F_SHPREAMBLE? */ 3084193240Ssam | (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE ? 3085193240Ssam EAGLE_TXD_PREAMBLE_SHORT : EAGLE_TXD_PREAMBLE_LONG); 3086193240Ssam } 3087193240Ssam return fmt; 3088193240Ssam} 3089193240Ssam 3090193240Ssamstatic int 3091193240Ssammwl_tx_start(struct mwl_softc *sc, struct ieee80211_node *ni, struct mwl_txbuf *bf, 3092193240Ssam struct mbuf *m0) 3093193240Ssam{ 3094193240Ssam#define IEEE80211_DIR_DSTODS(wh) \ 3095193240Ssam ((wh->i_fc[1] & IEEE80211_FC1_DIR_MASK) == IEEE80211_FC1_DIR_DSTODS) 3096287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 3097193240Ssam struct ieee80211vap *vap = ni->ni_vap; 3098193240Ssam int error, iswep, ismcast; 3099193240Ssam int hdrlen, copyhdrlen, pktlen; 3100193240Ssam struct mwl_txdesc *ds; 3101193240Ssam struct mwl_txq *txq; 3102193240Ssam struct ieee80211_frame *wh; 3103193240Ssam struct mwltxrec *tr; 3104193240Ssam struct mwl_node *mn; 3105193240Ssam uint16_t qos; 3106193240Ssam#if MWL_TXDESC > 1 3107193240Ssam int i; 3108193240Ssam#endif 3109193240Ssam 3110193240Ssam wh = mtod(m0, struct ieee80211_frame *); 3111260444Skevlo iswep = wh->i_fc[1] & IEEE80211_FC1_PROTECTED; 3112193240Ssam ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 3113193240Ssam hdrlen = ieee80211_anyhdrsize(wh); 3114193240Ssam copyhdrlen = hdrlen; 3115193240Ssam pktlen = m0->m_pkthdr.len; 3116193240Ssam if (IEEE80211_QOS_HAS_SEQ(wh)) { 3117193240Ssam if (IEEE80211_DIR_DSTODS(wh)) { 3118193240Ssam qos = *(uint16_t *) 3119193240Ssam (((struct ieee80211_qosframe_addr4 *) wh)->i_qos); 3120193240Ssam copyhdrlen -= sizeof(qos); 3121193240Ssam } else 3122193240Ssam qos = *(uint16_t *) 3123193240Ssam (((struct ieee80211_qosframe *) wh)->i_qos); 3124193240Ssam } else 3125193240Ssam qos = 0; 3126193240Ssam 3127193240Ssam if (iswep) { 3128193240Ssam const struct ieee80211_cipher *cip; 3129193240Ssam struct ieee80211_key *k; 3130193240Ssam 3131193240Ssam /* 3132193240Ssam * Construct the 802.11 header+trailer for an encrypted 3133193240Ssam * frame. The only reason this can fail is because of an 3134193240Ssam * unknown or unsupported cipher/key type. 3135193240Ssam * 3136193240Ssam * NB: we do this even though the firmware will ignore 3137193240Ssam * what we've done for WEP and TKIP as we need the 3138193240Ssam * ExtIV filled in for CCMP and this also adjusts 3139193240Ssam * the headers which simplifies our work below. 3140193240Ssam */ 3141193240Ssam k = ieee80211_crypto_encap(ni, m0); 3142193240Ssam if (k == NULL) { 3143193240Ssam /* 3144193240Ssam * This can happen when the key is yanked after the 3145193240Ssam * frame was queued. Just discard the frame; the 3146193240Ssam * 802.11 layer counts failures and provides 3147193240Ssam * debugging/diagnostics. 3148193240Ssam */ 3149193240Ssam m_freem(m0); 3150193240Ssam return EIO; 3151193240Ssam } 3152193240Ssam /* 3153193240Ssam * Adjust the packet length for the crypto additions 3154193240Ssam * done during encap and any other bits that the f/w 3155193240Ssam * will add later on. 3156193240Ssam */ 3157193240Ssam cip = k->wk_cipher; 3158193240Ssam pktlen += cip->ic_header + cip->ic_miclen + cip->ic_trailer; 3159193240Ssam 3160193240Ssam /* packet header may have moved, reset our local pointer */ 3161193240Ssam wh = mtod(m0, struct ieee80211_frame *); 3162193240Ssam } 3163193240Ssam 3164193240Ssam if (ieee80211_radiotap_active_vap(vap)) { 3165193240Ssam sc->sc_tx_th.wt_flags = 0; /* XXX */ 3166193240Ssam if (iswep) 3167193240Ssam sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3168193240Ssam#if 0 3169193240Ssam sc->sc_tx_th.wt_rate = ds->DataRate; 3170193240Ssam#endif 3171193240Ssam sc->sc_tx_th.wt_txpower = ni->ni_txpower; 3172193240Ssam sc->sc_tx_th.wt_antenna = sc->sc_txantenna; 3173193240Ssam 3174193240Ssam ieee80211_radiotap_tx(vap, m0); 3175193240Ssam } 3176193240Ssam /* 3177193240Ssam * Copy up/down the 802.11 header; the firmware requires 3178193240Ssam * we present a 2-byte payload length followed by a 3179193240Ssam * 4-address header (w/o QoS), followed (optionally) by 3180193240Ssam * any WEP/ExtIV header (but only filled in for CCMP). 3181193240Ssam * We are assured the mbuf has sufficient headroom to 3182193240Ssam * prepend in-place by the setup of ic_headroom in 3183193240Ssam * mwl_attach. 3184193240Ssam */ 3185193240Ssam if (hdrlen < sizeof(struct mwltxrec)) { 3186193240Ssam const int space = sizeof(struct mwltxrec) - hdrlen; 3187193240Ssam if (M_LEADINGSPACE(m0) < space) { 3188193240Ssam /* NB: should never happen */ 3189193240Ssam device_printf(sc->sc_dev, 3190193240Ssam "not enough headroom, need %d found %zd, " 3191193240Ssam "m_flags 0x%x m_len %d\n", 3192193240Ssam space, M_LEADINGSPACE(m0), m0->m_flags, m0->m_len); 3193193240Ssam ieee80211_dump_pkt(ic, 3194193240Ssam mtod(m0, const uint8_t *), m0->m_len, 0, -1); 3195193240Ssam m_freem(m0); 3196193240Ssam sc->sc_stats.mst_tx_noheadroom++; 3197193240Ssam return EIO; 3198193240Ssam } 3199193240Ssam M_PREPEND(m0, space, M_NOWAIT); 3200193240Ssam } 3201193240Ssam tr = mtod(m0, struct mwltxrec *); 3202193240Ssam if (wh != (struct ieee80211_frame *) &tr->wh) 3203193240Ssam ovbcopy(wh, &tr->wh, hdrlen); 3204193240Ssam /* 3205193240Ssam * Note: the "firmware length" is actually the length 3206193240Ssam * of the fully formed "802.11 payload". That is, it's 3207193240Ssam * everything except for the 802.11 header. In particular 3208193240Ssam * this includes all crypto material including the MIC! 3209193240Ssam */ 3210193240Ssam tr->fwlen = htole16(pktlen - hdrlen); 3211193240Ssam 3212193240Ssam /* 3213193240Ssam * Load the DMA map so any coalescing is done. This 3214193240Ssam * also calculates the number of descriptors we need. 3215193240Ssam */ 3216193240Ssam error = mwl_tx_dmasetup(sc, bf, m0); 3217193240Ssam if (error != 0) { 3218193240Ssam /* NB: stat collected in mwl_tx_dmasetup */ 3219193240Ssam DPRINTF(sc, MWL_DEBUG_XMIT, 3220193240Ssam "%s: unable to setup dma\n", __func__); 3221193240Ssam return error; 3222193240Ssam } 3223193240Ssam bf->bf_node = ni; /* NB: held reference */ 3224193240Ssam m0 = bf->bf_m; /* NB: may have changed */ 3225193240Ssam tr = mtod(m0, struct mwltxrec *); 3226193240Ssam wh = (struct ieee80211_frame *)&tr->wh; 3227193240Ssam 3228193240Ssam /* 3229193240Ssam * Formulate tx descriptor. 3230193240Ssam */ 3231193240Ssam ds = bf->bf_desc; 3232193240Ssam txq = bf->bf_txq; 3233193240Ssam 3234193240Ssam ds->QosCtrl = qos; /* NB: already little-endian */ 3235193240Ssam#if MWL_TXDESC == 1 3236193240Ssam /* 3237193240Ssam * NB: multiframes should be zero because the descriptors 3238193240Ssam * are initialized to zero. This should handle the case 3239193240Ssam * where the driver is built with MWL_TXDESC=1 but we are 3240193240Ssam * using firmware with multi-segment support. 3241193240Ssam */ 3242193240Ssam ds->PktPtr = htole32(bf->bf_segs[0].ds_addr); 3243193240Ssam ds->PktLen = htole16(bf->bf_segs[0].ds_len); 3244193240Ssam#else 3245193240Ssam ds->multiframes = htole32(bf->bf_nseg); 3246193240Ssam ds->PktLen = htole16(m0->m_pkthdr.len); 3247193240Ssam for (i = 0; i < bf->bf_nseg; i++) { 3248193240Ssam ds->PktPtrArray[i] = htole32(bf->bf_segs[i].ds_addr); 3249193240Ssam ds->PktLenArray[i] = htole16(bf->bf_segs[i].ds_len); 3250193240Ssam } 3251193240Ssam#endif 3252193240Ssam /* NB: pPhysNext, DataRate, and SapPktInfo setup once, don't touch */ 3253193240Ssam ds->Format = 0; 3254193240Ssam ds->pad = 0; 3255195171Ssam ds->ack_wcb_addr = 0; 3256193240Ssam 3257193240Ssam mn = MWL_NODE(ni); 3258193240Ssam /* 3259193240Ssam * Select transmit rate. 3260193240Ssam */ 3261193240Ssam switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 3262193240Ssam case IEEE80211_FC0_TYPE_MGT: 3263193240Ssam sc->sc_stats.mst_tx_mgmt++; 3264193240Ssam /* fall thru... */ 3265193240Ssam case IEEE80211_FC0_TYPE_CTL: 3266193240Ssam /* NB: assign to BE q to avoid bursting */ 3267193240Ssam ds->TxPriority = MWL_WME_AC_BE; 3268193240Ssam break; 3269193240Ssam case IEEE80211_FC0_TYPE_DATA: 3270193240Ssam if (!ismcast) { 3271193240Ssam const struct ieee80211_txparam *tp = ni->ni_txparms; 3272193240Ssam /* 3273193240Ssam * EAPOL frames get forced to a fixed rate and w/o 3274193240Ssam * aggregation; otherwise check for any fixed rate 3275193240Ssam * for the client (may depend on association state). 3276193240Ssam */ 3277193240Ssam if (m0->m_flags & M_EAPOL) { 3278193240Ssam const struct mwl_vap *mvp = MWL_VAP_CONST(vap); 3279193240Ssam ds->Format = mvp->mv_eapolformat; 3280193240Ssam ds->pad = htole16( 3281193240Ssam EAGLE_TXD_FIXED_RATE | EAGLE_TXD_DONT_AGGR); 3282195171Ssam } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) { 3283193240Ssam /* XXX pre-calculate per node */ 3284193240Ssam ds->Format = htole16( 3285193240Ssam mwl_calcformat(tp->ucastrate, ni)); 3286193240Ssam ds->pad = htole16(EAGLE_TXD_FIXED_RATE); 3287193240Ssam } 3288193240Ssam /* NB: EAPOL frames will never have qos set */ 3289193240Ssam if (qos == 0) 3290193240Ssam ds->TxPriority = txq->qnum; 3291193240Ssam#if MWL_MAXBA > 3 3292193240Ssam else if (mwl_bastream_match(&mn->mn_ba[3], qos)) 3293193240Ssam ds->TxPriority = mn->mn_ba[3].txq; 3294193240Ssam#endif 3295193240Ssam#if MWL_MAXBA > 2 3296193240Ssam else if (mwl_bastream_match(&mn->mn_ba[2], qos)) 3297193240Ssam ds->TxPriority = mn->mn_ba[2].txq; 3298193240Ssam#endif 3299193240Ssam#if MWL_MAXBA > 1 3300193240Ssam else if (mwl_bastream_match(&mn->mn_ba[1], qos)) 3301193240Ssam ds->TxPriority = mn->mn_ba[1].txq; 3302193240Ssam#endif 3303193240Ssam#if MWL_MAXBA > 0 3304193240Ssam else if (mwl_bastream_match(&mn->mn_ba[0], qos)) 3305193240Ssam ds->TxPriority = mn->mn_ba[0].txq; 3306193240Ssam#endif 3307193240Ssam else 3308193240Ssam ds->TxPriority = txq->qnum; 3309193240Ssam } else 3310193240Ssam ds->TxPriority = txq->qnum; 3311193240Ssam break; 3312193240Ssam default: 3313287197Sglebius device_printf(sc->sc_dev, "bogus frame type 0x%x (%s)\n", 3314193240Ssam wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__); 3315193240Ssam sc->sc_stats.mst_tx_badframetype++; 3316193240Ssam m_freem(m0); 3317193240Ssam return EIO; 3318193240Ssam } 3319193240Ssam 3320193240Ssam if (IFF_DUMPPKTS_XMIT(sc)) 3321193240Ssam ieee80211_dump_pkt(ic, 3322193240Ssam mtod(m0, const uint8_t *)+sizeof(uint16_t), 3323193240Ssam m0->m_len - sizeof(uint16_t), ds->DataRate, -1); 3324193240Ssam 3325193240Ssam MWL_TXQ_LOCK(txq); 3326193240Ssam ds->Status = htole32(EAGLE_TXD_STATUS_FW_OWNED); 3327193240Ssam STAILQ_INSERT_TAIL(&txq->active, bf, bf_list); 3328193240Ssam MWL_TXDESC_SYNC(txq, ds, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3329193240Ssam 3330199559Sjhb sc->sc_tx_timer = 5; 3331193240Ssam MWL_TXQ_UNLOCK(txq); 3332193240Ssam 3333193240Ssam return 0; 3334193240Ssam#undef IEEE80211_DIR_DSTODS 3335193240Ssam} 3336193240Ssam 3337193240Ssamstatic __inline int 3338193240Ssammwl_cvtlegacyrix(int rix) 3339193240Ssam{ 3340193240Ssam#define N(x) (sizeof(x)/sizeof(x[0])) 3341193240Ssam static const int ieeerates[] = 3342193240Ssam { 2, 4, 11, 22, 44, 12, 18, 24, 36, 48, 72, 96, 108 }; 3343193240Ssam return (rix < N(ieeerates) ? ieeerates[rix] : 0); 3344193240Ssam#undef N 3345193240Ssam} 3346193240Ssam 3347193240Ssam/* 3348193240Ssam * Process completed xmit descriptors from the specified queue. 3349193240Ssam */ 3350193240Ssamstatic int 3351193240Ssammwl_tx_processq(struct mwl_softc *sc, struct mwl_txq *txq) 3352193240Ssam{ 3353193240Ssam#define EAGLE_TXD_STATUS_MCAST \ 3354193240Ssam (EAGLE_TXD_STATUS_MULTICAST_TX | EAGLE_TXD_STATUS_BROADCAST_TX) 3355287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 3356193240Ssam struct mwl_txbuf *bf; 3357193240Ssam struct mwl_txdesc *ds; 3358193240Ssam struct ieee80211_node *ni; 3359193240Ssam struct mwl_node *an; 3360193240Ssam int nreaped; 3361193240Ssam uint32_t status; 3362193240Ssam 3363193240Ssam DPRINTF(sc, MWL_DEBUG_TX_PROC, "%s: tx queue %u\n", __func__, txq->qnum); 3364193240Ssam for (nreaped = 0;; nreaped++) { 3365193240Ssam MWL_TXQ_LOCK(txq); 3366193240Ssam bf = STAILQ_FIRST(&txq->active); 3367193240Ssam if (bf == NULL) { 3368193240Ssam MWL_TXQ_UNLOCK(txq); 3369193240Ssam break; 3370193240Ssam } 3371193240Ssam ds = bf->bf_desc; 3372193240Ssam MWL_TXDESC_SYNC(txq, ds, 3373193240Ssam BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3374193240Ssam if (ds->Status & htole32(EAGLE_TXD_STATUS_FW_OWNED)) { 3375193240Ssam MWL_TXQ_UNLOCK(txq); 3376193240Ssam break; 3377193240Ssam } 3378193240Ssam STAILQ_REMOVE_HEAD(&txq->active, bf_list); 3379193240Ssam MWL_TXQ_UNLOCK(txq); 3380193240Ssam 3381193240Ssam#ifdef MWL_DEBUG 3382193240Ssam if (sc->sc_debug & MWL_DEBUG_XMIT_DESC) 3383193240Ssam mwl_printtxbuf(bf, txq->qnum, nreaped); 3384193240Ssam#endif 3385193240Ssam ni = bf->bf_node; 3386193240Ssam if (ni != NULL) { 3387193240Ssam an = MWL_NODE(ni); 3388193240Ssam status = le32toh(ds->Status); 3389193240Ssam if (status & EAGLE_TXD_STATUS_OK) { 3390193240Ssam uint16_t Format = le16toh(ds->Format); 3391193240Ssam uint8_t txant = MS(Format, EAGLE_TXD_ANTENNA); 3392193240Ssam 3393193240Ssam sc->sc_stats.mst_ant_tx[txant]++; 3394193240Ssam if (status & EAGLE_TXD_STATUS_OK_RETRY) 3395193240Ssam sc->sc_stats.mst_tx_retries++; 3396193240Ssam if (status & EAGLE_TXD_STATUS_OK_MORE_RETRY) 3397193240Ssam sc->sc_stats.mst_tx_mretries++; 3398193240Ssam if (txq->qnum >= MWL_WME_AC_VO) 3399193240Ssam ic->ic_wme.wme_hipri_traffic++; 3400193240Ssam ni->ni_txrate = MS(Format, EAGLE_TXD_RATE); 3401193240Ssam if ((Format & EAGLE_TXD_FORMAT_HT) == 0) { 3402193240Ssam ni->ni_txrate = mwl_cvtlegacyrix( 3403193240Ssam ni->ni_txrate); 3404193240Ssam } else 3405193240Ssam ni->ni_txrate |= IEEE80211_RATE_MCS; 3406193240Ssam sc->sc_stats.mst_tx_rate = ni->ni_txrate; 3407193240Ssam } else { 3408193240Ssam if (status & EAGLE_TXD_STATUS_FAILED_LINK_ERROR) 3409193240Ssam sc->sc_stats.mst_tx_linkerror++; 3410193240Ssam if (status & EAGLE_TXD_STATUS_FAILED_XRETRY) 3411193240Ssam sc->sc_stats.mst_tx_xretries++; 3412193240Ssam if (status & EAGLE_TXD_STATUS_FAILED_AGING) 3413193240Ssam sc->sc_stats.mst_tx_aging++; 3414193240Ssam if (bf->bf_m->m_flags & M_FF) 3415193240Ssam sc->sc_stats.mst_ff_txerr++; 3416193240Ssam } 3417287197Sglebius if (bf->bf_m->m_flags & M_TXCB) 3418193240Ssam /* XXX strip fw len in case header inspected */ 3419193240Ssam m_adj(bf->bf_m, sizeof(uint16_t)); 3420287197Sglebius ieee80211_tx_complete(ni, bf->bf_m, 3421287197Sglebius (status & EAGLE_TXD_STATUS_OK) == 0); 3422287197Sglebius } else 3423287197Sglebius m_freem(bf->bf_m); 3424193240Ssam ds->Status = htole32(EAGLE_TXD_STATUS_IDLE); 3425193240Ssam 3426193240Ssam bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 3427193240Ssam BUS_DMASYNC_POSTWRITE); 3428193240Ssam bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3429193240Ssam 3430193240Ssam mwl_puttxbuf_tail(txq, bf); 3431193240Ssam } 3432193240Ssam return nreaped; 3433193240Ssam#undef EAGLE_TXD_STATUS_MCAST 3434193240Ssam} 3435193240Ssam 3436193240Ssam/* 3437193240Ssam * Deferred processing of transmit interrupt; special-cased 3438193240Ssam * for four hardware queues, 0-3. 3439193240Ssam */ 3440193240Ssamstatic void 3441193240Ssammwl_tx_proc(void *arg, int npending) 3442193240Ssam{ 3443193240Ssam struct mwl_softc *sc = arg; 3444193240Ssam int nreaped; 3445193240Ssam 3446193240Ssam /* 3447193240Ssam * Process each active queue. 3448193240Ssam */ 3449193240Ssam nreaped = 0; 3450193240Ssam if (!STAILQ_EMPTY(&sc->sc_txq[0].active)) 3451193240Ssam nreaped += mwl_tx_processq(sc, &sc->sc_txq[0]); 3452193240Ssam if (!STAILQ_EMPTY(&sc->sc_txq[1].active)) 3453193240Ssam nreaped += mwl_tx_processq(sc, &sc->sc_txq[1]); 3454193240Ssam if (!STAILQ_EMPTY(&sc->sc_txq[2].active)) 3455193240Ssam nreaped += mwl_tx_processq(sc, &sc->sc_txq[2]); 3456193240Ssam if (!STAILQ_EMPTY(&sc->sc_txq[3].active)) 3457193240Ssam nreaped += mwl_tx_processq(sc, &sc->sc_txq[3]); 3458193240Ssam 3459193240Ssam if (nreaped != 0) { 3460199559Sjhb sc->sc_tx_timer = 0; 3461287197Sglebius if (mbufq_first(&sc->sc_snd) != NULL) { 3462193240Ssam /* NB: kick fw; the tx thread may have been preempted */ 3463193240Ssam mwl_hal_txstart(sc->sc_mh, 0); 3464287197Sglebius mwl_start(sc); 3465193240Ssam } 3466193240Ssam } 3467193240Ssam} 3468193240Ssam 3469193240Ssamstatic void 3470193240Ssammwl_tx_draintxq(struct mwl_softc *sc, struct mwl_txq *txq) 3471193240Ssam{ 3472193240Ssam struct ieee80211_node *ni; 3473193240Ssam struct mwl_txbuf *bf; 3474193240Ssam u_int ix; 3475193240Ssam 3476193240Ssam /* 3477193240Ssam * NB: this assumes output has been stopped and 3478193240Ssam * we do not need to block mwl_tx_tasklet 3479193240Ssam */ 3480193240Ssam for (ix = 0;; ix++) { 3481193240Ssam MWL_TXQ_LOCK(txq); 3482193240Ssam bf = STAILQ_FIRST(&txq->active); 3483193240Ssam if (bf == NULL) { 3484193240Ssam MWL_TXQ_UNLOCK(txq); 3485193240Ssam break; 3486193240Ssam } 3487193240Ssam STAILQ_REMOVE_HEAD(&txq->active, bf_list); 3488193240Ssam MWL_TXQ_UNLOCK(txq); 3489193240Ssam#ifdef MWL_DEBUG 3490193240Ssam if (sc->sc_debug & MWL_DEBUG_RESET) { 3491287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 3492193240Ssam const struct mwltxrec *tr = 3493193240Ssam mtod(bf->bf_m, const struct mwltxrec *); 3494193240Ssam mwl_printtxbuf(bf, txq->qnum, ix); 3495193240Ssam ieee80211_dump_pkt(ic, (const uint8_t *)&tr->wh, 3496193240Ssam bf->bf_m->m_len - sizeof(tr->fwlen), 0, -1); 3497193240Ssam } 3498193240Ssam#endif /* MWL_DEBUG */ 3499193240Ssam bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3500193240Ssam ni = bf->bf_node; 3501193240Ssam if (ni != NULL) { 3502193240Ssam /* 3503193240Ssam * Reclaim node reference. 3504193240Ssam */ 3505193240Ssam ieee80211_free_node(ni); 3506193240Ssam } 3507193240Ssam m_freem(bf->bf_m); 3508193240Ssam 3509193240Ssam mwl_puttxbuf_tail(txq, bf); 3510193240Ssam } 3511193240Ssam} 3512193240Ssam 3513193240Ssam/* 3514193240Ssam * Drain the transmit queues and reclaim resources. 3515193240Ssam */ 3516193240Ssamstatic void 3517193240Ssammwl_draintxq(struct mwl_softc *sc) 3518193240Ssam{ 3519193240Ssam int i; 3520193240Ssam 3521193240Ssam for (i = 0; i < MWL_NUM_TX_QUEUES; i++) 3522193240Ssam mwl_tx_draintxq(sc, &sc->sc_txq[i]); 3523199559Sjhb sc->sc_tx_timer = 0; 3524193240Ssam} 3525193240Ssam 3526193240Ssam#ifdef MWL_DIAGAPI 3527193240Ssam/* 3528193240Ssam * Reset the transmit queues to a pristine state after a fw download. 3529193240Ssam */ 3530193240Ssamstatic void 3531193240Ssammwl_resettxq(struct mwl_softc *sc) 3532193240Ssam{ 3533193240Ssam int i; 3534193240Ssam 3535193240Ssam for (i = 0; i < MWL_NUM_TX_QUEUES; i++) 3536193240Ssam mwl_txq_reset(sc, &sc->sc_txq[i]); 3537193240Ssam} 3538193240Ssam#endif /* MWL_DIAGAPI */ 3539193240Ssam 3540193240Ssam/* 3541193240Ssam * Clear the transmit queues of any frames submitted for the 3542193240Ssam * specified vap. This is done when the vap is deleted so we 3543193240Ssam * don't potentially reference the vap after it is gone. 3544193240Ssam * Note we cannot remove the frames; we only reclaim the node 3545193240Ssam * reference. 3546193240Ssam */ 3547193240Ssamstatic void 3548193240Ssammwl_cleartxq(struct mwl_softc *sc, struct ieee80211vap *vap) 3549193240Ssam{ 3550193240Ssam struct mwl_txq *txq; 3551193240Ssam struct mwl_txbuf *bf; 3552193240Ssam int i; 3553193240Ssam 3554193240Ssam for (i = 0; i < MWL_NUM_TX_QUEUES; i++) { 3555193240Ssam txq = &sc->sc_txq[i]; 3556193240Ssam MWL_TXQ_LOCK(txq); 3557193240Ssam STAILQ_FOREACH(bf, &txq->active, bf_list) { 3558193240Ssam struct ieee80211_node *ni = bf->bf_node; 3559193240Ssam if (ni != NULL && ni->ni_vap == vap) { 3560193240Ssam bf->bf_node = NULL; 3561193240Ssam ieee80211_free_node(ni); 3562193240Ssam } 3563193240Ssam } 3564193240Ssam MWL_TXQ_UNLOCK(txq); 3565193240Ssam } 3566193240Ssam} 3567193240Ssam 3568195377Ssamstatic int 3569195377Ssammwl_recv_action(struct ieee80211_node *ni, const struct ieee80211_frame *wh, 3570195377Ssam const uint8_t *frm, const uint8_t *efrm) 3571193240Ssam{ 3572287197Sglebius struct mwl_softc *sc = ni->ni_ic->ic_softc; 3573193240Ssam const struct ieee80211_action *ia; 3574193240Ssam 3575193240Ssam ia = (const struct ieee80211_action *) frm; 3576193240Ssam if (ia->ia_category == IEEE80211_ACTION_CAT_HT && 3577193240Ssam ia->ia_action == IEEE80211_ACTION_HT_MIMOPWRSAVE) { 3578193240Ssam const struct ieee80211_action_ht_mimopowersave *mps = 3579193240Ssam (const struct ieee80211_action_ht_mimopowersave *) ia; 3580193240Ssam 3581193240Ssam mwl_hal_setmimops(sc->sc_mh, ni->ni_macaddr, 3582193240Ssam mps->am_control & IEEE80211_A_HT_MIMOPWRSAVE_ENA, 3583193240Ssam MS(mps->am_control, IEEE80211_A_HT_MIMOPWRSAVE_MODE)); 3584195377Ssam return 0; 3585193240Ssam } else 3586195377Ssam return sc->sc_recv_action(ni, wh, frm, efrm); 3587193240Ssam} 3588193240Ssam 3589193240Ssamstatic int 3590193240Ssammwl_addba_request(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, 3591193240Ssam int dialogtoken, int baparamset, int batimeout) 3592193240Ssam{ 3593287197Sglebius struct mwl_softc *sc = ni->ni_ic->ic_softc; 3594195171Ssam struct ieee80211vap *vap = ni->ni_vap; 3595193240Ssam struct mwl_node *mn = MWL_NODE(ni); 3596193240Ssam struct mwl_bastate *bas; 3597193240Ssam 3598193240Ssam bas = tap->txa_private; 3599193240Ssam if (bas == NULL) { 3600193240Ssam const MWL_HAL_BASTREAM *sp; 3601193240Ssam /* 3602193240Ssam * Check for a free BA stream slot. 3603193240Ssam */ 3604193240Ssam#if MWL_MAXBA > 3 3605193240Ssam if (mn->mn_ba[3].bastream == NULL) 3606193240Ssam bas = &mn->mn_ba[3]; 3607193240Ssam else 3608193240Ssam#endif 3609193240Ssam#if MWL_MAXBA > 2 3610193240Ssam if (mn->mn_ba[2].bastream == NULL) 3611193240Ssam bas = &mn->mn_ba[2]; 3612193240Ssam else 3613193240Ssam#endif 3614193240Ssam#if MWL_MAXBA > 1 3615193240Ssam if (mn->mn_ba[1].bastream == NULL) 3616193240Ssam bas = &mn->mn_ba[1]; 3617193240Ssam else 3618193240Ssam#endif 3619193240Ssam#if MWL_MAXBA > 0 3620193240Ssam if (mn->mn_ba[0].bastream == NULL) 3621193240Ssam bas = &mn->mn_ba[0]; 3622193240Ssam else 3623193240Ssam#endif 3624193240Ssam { 3625193240Ssam /* sta already has max BA streams */ 3626193240Ssam /* XXX assign BA stream to highest priority tid */ 3627193240Ssam DPRINTF(sc, MWL_DEBUG_AMPDU, 3628193240Ssam "%s: already has max bastreams\n", __func__); 3629193240Ssam sc->sc_stats.mst_ampdu_reject++; 3630193240Ssam return 0; 3631193240Ssam } 3632193240Ssam /* NB: no held reference to ni */ 3633195171Ssam sp = mwl_hal_bastream_alloc(MWL_VAP(vap)->mv_hvap, 3634195171Ssam (baparamset & IEEE80211_BAPS_POLICY_IMMEDIATE) != 0, 3635234324Sadrian ni->ni_macaddr, tap->txa_tid, ni->ni_htparam, 3636195171Ssam ni, tap); 3637193240Ssam if (sp == NULL) { 3638193240Ssam /* 3639193240Ssam * No available stream, return 0 so no 3640193240Ssam * a-mpdu aggregation will be done. 3641193240Ssam */ 3642193240Ssam DPRINTF(sc, MWL_DEBUG_AMPDU, 3643193240Ssam "%s: no bastream available\n", __func__); 3644193240Ssam sc->sc_stats.mst_ampdu_nostream++; 3645193240Ssam return 0; 3646193240Ssam } 3647193240Ssam DPRINTF(sc, MWL_DEBUG_AMPDU, "%s: alloc bastream %p\n", 3648193240Ssam __func__, sp); 3649193240Ssam /* NB: qos is left zero so we won't match in mwl_tx_start */ 3650193240Ssam bas->bastream = sp; 3651193240Ssam tap->txa_private = bas; 3652193240Ssam } 3653193240Ssam /* fetch current seq# from the firmware; if available */ 3654193240Ssam if (mwl_hal_bastream_get_seqno(sc->sc_mh, bas->bastream, 3655195171Ssam vap->iv_opmode == IEEE80211_M_STA ? vap->iv_myaddr : ni->ni_macaddr, 3656193240Ssam &tap->txa_start) != 0) 3657193240Ssam tap->txa_start = 0; 3658193240Ssam return sc->sc_addba_request(ni, tap, dialogtoken, baparamset, batimeout); 3659193240Ssam} 3660193240Ssam 3661193240Ssamstatic int 3662193240Ssammwl_addba_response(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, 3663193240Ssam int code, int baparamset, int batimeout) 3664193240Ssam{ 3665287197Sglebius struct mwl_softc *sc = ni->ni_ic->ic_softc; 3666193240Ssam struct mwl_bastate *bas; 3667193240Ssam 3668193240Ssam bas = tap->txa_private; 3669193240Ssam if (bas == NULL) { 3670193240Ssam /* XXX should not happen */ 3671193240Ssam DPRINTF(sc, MWL_DEBUG_AMPDU, 3672234324Sadrian "%s: no BA stream allocated, TID %d\n", 3673234324Sadrian __func__, tap->txa_tid); 3674193240Ssam sc->sc_stats.mst_addba_nostream++; 3675193240Ssam return 0; 3676193240Ssam } 3677193240Ssam if (code == IEEE80211_STATUS_SUCCESS) { 3678195171Ssam struct ieee80211vap *vap = ni->ni_vap; 3679193240Ssam int bufsiz, error; 3680193240Ssam 3681193240Ssam /* 3682193240Ssam * Tell the firmware to setup the BA stream; 3683193240Ssam * we know resources are available because we 3684193240Ssam * pre-allocated one before forming the request. 3685193240Ssam */ 3686193240Ssam bufsiz = MS(baparamset, IEEE80211_BAPS_BUFSIZ); 3687193240Ssam if (bufsiz == 0) 3688193240Ssam bufsiz = IEEE80211_AGGR_BAWMAX; 3689195171Ssam error = mwl_hal_bastream_create(MWL_VAP(vap)->mv_hvap, 3690195171Ssam bas->bastream, bufsiz, bufsiz, tap->txa_start); 3691193240Ssam if (error != 0) { 3692193240Ssam /* 3693193240Ssam * Setup failed, return immediately so no a-mpdu 3694193240Ssam * aggregation will be done. 3695193240Ssam */ 3696193240Ssam mwl_hal_bastream_destroy(sc->sc_mh, bas->bastream); 3697193240Ssam mwl_bastream_free(bas); 3698193240Ssam tap->txa_private = NULL; 3699193240Ssam 3700193240Ssam DPRINTF(sc, MWL_DEBUG_AMPDU, 3701234324Sadrian "%s: create failed, error %d, bufsiz %d TID %d " 3702193240Ssam "htparam 0x%x\n", __func__, error, bufsiz, 3703234324Sadrian tap->txa_tid, ni->ni_htparam); 3704193240Ssam sc->sc_stats.mst_bacreate_failed++; 3705193240Ssam return 0; 3706193240Ssam } 3707193240Ssam /* NB: cache txq to avoid ptr indirect */ 3708234324Sadrian mwl_bastream_setup(bas, tap->txa_tid, bas->bastream->txq); 3709193240Ssam DPRINTF(sc, MWL_DEBUG_AMPDU, 3710234324Sadrian "%s: bastream %p assigned to txq %d TID %d bufsiz %d " 3711193240Ssam "htparam 0x%x\n", __func__, bas->bastream, 3712234324Sadrian bas->txq, tap->txa_tid, bufsiz, ni->ni_htparam); 3713193240Ssam } else { 3714193240Ssam /* 3715193240Ssam * Other side NAK'd us; return the resources. 3716193240Ssam */ 3717193240Ssam DPRINTF(sc, MWL_DEBUG_AMPDU, 3718193240Ssam "%s: request failed with code %d, destroy bastream %p\n", 3719193240Ssam __func__, code, bas->bastream); 3720193240Ssam mwl_hal_bastream_destroy(sc->sc_mh, bas->bastream); 3721193240Ssam mwl_bastream_free(bas); 3722193240Ssam tap->txa_private = NULL; 3723193240Ssam } 3724193240Ssam /* NB: firmware sends BAR so we don't need to */ 3725193240Ssam return sc->sc_addba_response(ni, tap, code, baparamset, batimeout); 3726193240Ssam} 3727193240Ssam 3728193240Ssamstatic void 3729193240Ssammwl_addba_stop(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap) 3730193240Ssam{ 3731287197Sglebius struct mwl_softc *sc = ni->ni_ic->ic_softc; 3732193240Ssam struct mwl_bastate *bas; 3733193240Ssam 3734193240Ssam bas = tap->txa_private; 3735193240Ssam if (bas != NULL) { 3736193240Ssam DPRINTF(sc, MWL_DEBUG_AMPDU, "%s: destroy bastream %p\n", 3737193240Ssam __func__, bas->bastream); 3738193240Ssam mwl_hal_bastream_destroy(sc->sc_mh, bas->bastream); 3739193240Ssam mwl_bastream_free(bas); 3740193240Ssam tap->txa_private = NULL; 3741193240Ssam } 3742193240Ssam sc->sc_addba_stop(ni, tap); 3743193240Ssam} 3744193240Ssam 3745193240Ssam/* 3746193240Ssam * Setup the rx data structures. This should only be 3747193240Ssam * done once or we may get out of sync with the firmware. 3748193240Ssam */ 3749193240Ssamstatic int 3750193240Ssammwl_startrecv(struct mwl_softc *sc) 3751193240Ssam{ 3752193240Ssam if (!sc->sc_recvsetup) { 3753193240Ssam struct mwl_rxbuf *bf, *prev; 3754193240Ssam struct mwl_rxdesc *ds; 3755193240Ssam 3756193240Ssam prev = NULL; 3757193240Ssam STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 3758193240Ssam int error = mwl_rxbuf_init(sc, bf); 3759193240Ssam if (error != 0) { 3760193240Ssam DPRINTF(sc, MWL_DEBUG_RECV, 3761193240Ssam "%s: mwl_rxbuf_init failed %d\n", 3762193240Ssam __func__, error); 3763193240Ssam return error; 3764193240Ssam } 3765193240Ssam if (prev != NULL) { 3766193240Ssam ds = prev->bf_desc; 3767193240Ssam ds->pPhysNext = htole32(bf->bf_daddr); 3768193240Ssam } 3769193240Ssam prev = bf; 3770193240Ssam } 3771193240Ssam if (prev != NULL) { 3772193240Ssam ds = prev->bf_desc; 3773193240Ssam ds->pPhysNext = 3774193240Ssam htole32(STAILQ_FIRST(&sc->sc_rxbuf)->bf_daddr); 3775193240Ssam } 3776193240Ssam sc->sc_recvsetup = 1; 3777193240Ssam } 3778193240Ssam mwl_mode_init(sc); /* set filters, etc. */ 3779193240Ssam return 0; 3780193240Ssam} 3781193240Ssam 3782193240Ssamstatic MWL_HAL_APMODE 3783193240Ssammwl_getapmode(const struct ieee80211vap *vap, struct ieee80211_channel *chan) 3784193240Ssam{ 3785193240Ssam MWL_HAL_APMODE mode; 3786193240Ssam 3787193240Ssam if (IEEE80211_IS_CHAN_HT(chan)) { 3788193656Ssam if (vap->iv_flags_ht & IEEE80211_FHT_PUREN) 3789193240Ssam mode = AP_MODE_N_ONLY; 3790193240Ssam else if (IEEE80211_IS_CHAN_5GHZ(chan)) 3791193240Ssam mode = AP_MODE_AandN; 3792193240Ssam else if (vap->iv_flags & IEEE80211_F_PUREG) 3793193240Ssam mode = AP_MODE_GandN; 3794193240Ssam else 3795193240Ssam mode = AP_MODE_BandGandN; 3796193240Ssam } else if (IEEE80211_IS_CHAN_ANYG(chan)) { 3797193240Ssam if (vap->iv_flags & IEEE80211_F_PUREG) 3798193240Ssam mode = AP_MODE_G_ONLY; 3799193240Ssam else 3800193240Ssam mode = AP_MODE_MIXED; 3801193240Ssam } else if (IEEE80211_IS_CHAN_B(chan)) 3802193240Ssam mode = AP_MODE_B_ONLY; 3803193240Ssam else if (IEEE80211_IS_CHAN_A(chan)) 3804193240Ssam mode = AP_MODE_A_ONLY; 3805193240Ssam else 3806193240Ssam mode = AP_MODE_MIXED; /* XXX should not happen? */ 3807193240Ssam return mode; 3808193240Ssam} 3809193240Ssam 3810193240Ssamstatic int 3811193240Ssammwl_setapmode(struct ieee80211vap *vap, struct ieee80211_channel *chan) 3812193240Ssam{ 3813193240Ssam struct mwl_hal_vap *hvap = MWL_VAP(vap)->mv_hvap; 3814193240Ssam return mwl_hal_setapmode(hvap, mwl_getapmode(vap, chan)); 3815193240Ssam} 3816193240Ssam 3817193240Ssam/* 3818193240Ssam * Set/change channels. 3819193240Ssam */ 3820193240Ssamstatic int 3821193240Ssammwl_chan_set(struct mwl_softc *sc, struct ieee80211_channel *chan) 3822193240Ssam{ 3823193240Ssam struct mwl_hal *mh = sc->sc_mh; 3824287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 3825193240Ssam MWL_HAL_CHANNEL hchan; 3826193240Ssam int maxtxpow; 3827193240Ssam 3828193240Ssam DPRINTF(sc, MWL_DEBUG_RESET, "%s: chan %u MHz/flags 0x%x\n", 3829193240Ssam __func__, chan->ic_freq, chan->ic_flags); 3830193240Ssam 3831193240Ssam /* 3832193240Ssam * Convert to a HAL channel description with 3833193240Ssam * the flags constrained to reflect the current 3834193240Ssam * operating mode. 3835193240Ssam */ 3836193240Ssam mwl_mapchan(&hchan, chan); 3837193240Ssam mwl_hal_intrset(mh, 0); /* disable interrupts */ 3838193240Ssam#if 0 3839193240Ssam mwl_draintxq(sc); /* clear pending tx frames */ 3840193240Ssam#endif 3841193240Ssam mwl_hal_setchannel(mh, &hchan); 3842193240Ssam /* 3843193240Ssam * Tx power is cap'd by the regulatory setting and 3844193240Ssam * possibly a user-set limit. We pass the min of 3845193240Ssam * these to the hal to apply them to the cal data 3846193240Ssam * for this channel. 3847193240Ssam * XXX min bound? 3848193240Ssam */ 3849193240Ssam maxtxpow = 2*chan->ic_maxregpower; 3850193240Ssam if (maxtxpow > ic->ic_txpowlimit) 3851193240Ssam maxtxpow = ic->ic_txpowlimit; 3852193240Ssam mwl_hal_settxpower(mh, &hchan, maxtxpow / 2); 3853193240Ssam /* NB: potentially change mcast/mgt rates */ 3854193240Ssam mwl_setcurchanrates(sc); 3855193240Ssam 3856193240Ssam /* 3857193240Ssam * Update internal state. 3858193240Ssam */ 3859193240Ssam sc->sc_tx_th.wt_chan_freq = htole16(chan->ic_freq); 3860193240Ssam sc->sc_rx_th.wr_chan_freq = htole16(chan->ic_freq); 3861193240Ssam if (IEEE80211_IS_CHAN_A(chan)) { 3862193240Ssam sc->sc_tx_th.wt_chan_flags = htole16(IEEE80211_CHAN_A); 3863193240Ssam sc->sc_rx_th.wr_chan_flags = htole16(IEEE80211_CHAN_A); 3864193240Ssam } else if (IEEE80211_IS_CHAN_ANYG(chan)) { 3865193240Ssam sc->sc_tx_th.wt_chan_flags = htole16(IEEE80211_CHAN_G); 3866193240Ssam sc->sc_rx_th.wr_chan_flags = htole16(IEEE80211_CHAN_G); 3867193240Ssam } else { 3868193240Ssam sc->sc_tx_th.wt_chan_flags = htole16(IEEE80211_CHAN_B); 3869193240Ssam sc->sc_rx_th.wr_chan_flags = htole16(IEEE80211_CHAN_B); 3870193240Ssam } 3871193240Ssam sc->sc_curchan = hchan; 3872193240Ssam mwl_hal_intrset(mh, sc->sc_imask); 3873193240Ssam 3874193240Ssam return 0; 3875193240Ssam} 3876193240Ssam 3877193240Ssamstatic void 3878193240Ssammwl_scan_start(struct ieee80211com *ic) 3879193240Ssam{ 3880287197Sglebius struct mwl_softc *sc = ic->ic_softc; 3881193240Ssam 3882193240Ssam DPRINTF(sc, MWL_DEBUG_STATE, "%s\n", __func__); 3883193240Ssam} 3884193240Ssam 3885193240Ssamstatic void 3886193240Ssammwl_scan_end(struct ieee80211com *ic) 3887193240Ssam{ 3888287197Sglebius struct mwl_softc *sc = ic->ic_softc; 3889193240Ssam 3890193240Ssam DPRINTF(sc, MWL_DEBUG_STATE, "%s\n", __func__); 3891193240Ssam} 3892193240Ssam 3893193240Ssamstatic void 3894193240Ssammwl_set_channel(struct ieee80211com *ic) 3895193240Ssam{ 3896287197Sglebius struct mwl_softc *sc = ic->ic_softc; 3897193240Ssam 3898193240Ssam (void) mwl_chan_set(sc, ic->ic_curchan); 3899193240Ssam} 3900193240Ssam 3901193240Ssam/* 3902193240Ssam * Handle a channel switch request. We inform the firmware 3903193240Ssam * and mark the global state to suppress various actions. 3904193240Ssam * NB: we issue only one request to the fw; we may be called 3905193240Ssam * multiple times if there are multiple vap's. 3906193240Ssam */ 3907193240Ssamstatic void 3908193240Ssammwl_startcsa(struct ieee80211vap *vap) 3909193240Ssam{ 3910193240Ssam struct ieee80211com *ic = vap->iv_ic; 3911287197Sglebius struct mwl_softc *sc = ic->ic_softc; 3912193240Ssam MWL_HAL_CHANNEL hchan; 3913193240Ssam 3914193240Ssam if (sc->sc_csapending) 3915193240Ssam return; 3916193240Ssam 3917193240Ssam mwl_mapchan(&hchan, ic->ic_csa_newchan); 3918193240Ssam /* 1 =>'s quiet channel */ 3919193240Ssam mwl_hal_setchannelswitchie(sc->sc_mh, &hchan, 1, ic->ic_csa_count); 3920193240Ssam sc->sc_csapending = 1; 3921193240Ssam} 3922193240Ssam 3923193240Ssam/* 3924193240Ssam * Plumb any static WEP key for the station. This is 3925193240Ssam * necessary as we must propagate the key from the 3926193240Ssam * global key table of the vap to each sta db entry. 3927193240Ssam */ 3928193240Ssamstatic void 3929193240Ssammwl_setanywepkey(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN]) 3930193240Ssam{ 3931193240Ssam if ((vap->iv_flags & (IEEE80211_F_PRIVACY|IEEE80211_F_WPA)) == 3932193240Ssam IEEE80211_F_PRIVACY && 3933193240Ssam vap->iv_def_txkey != IEEE80211_KEYIX_NONE && 3934193240Ssam vap->iv_nw_keys[vap->iv_def_txkey].wk_keyix != IEEE80211_KEYIX_NONE) 3935193240Ssam (void) mwl_key_set(vap, &vap->iv_nw_keys[vap->iv_def_txkey], mac); 3936193240Ssam} 3937193240Ssam 3938193240Ssamstatic int 3939193240Ssammwl_peerstadb(struct ieee80211_node *ni, int aid, int staid, MWL_HAL_PEERINFO *pi) 3940193240Ssam{ 3941193240Ssam#define WME(ie) ((const struct ieee80211_wme_info *) ie) 3942193240Ssam struct ieee80211vap *vap = ni->ni_vap; 3943193240Ssam struct mwl_hal_vap *hvap; 3944193240Ssam int error; 3945193240Ssam 3946193240Ssam if (vap->iv_opmode == IEEE80211_M_WDS) { 3947193240Ssam /* 3948193240Ssam * WDS vap's do not have a f/w vap; instead they piggyback 3949193240Ssam * on an AP vap and we must install the sta db entry and 3950193240Ssam * crypto state using that AP's handle (the WDS vap has none). 3951193240Ssam */ 3952193240Ssam hvap = MWL_VAP(vap)->mv_ap_hvap; 3953193240Ssam } else 3954193240Ssam hvap = MWL_VAP(vap)->mv_hvap; 3955193240Ssam error = mwl_hal_newstation(hvap, ni->ni_macaddr, 3956193240Ssam aid, staid, pi, 3957193240Ssam ni->ni_flags & (IEEE80211_NODE_QOS | IEEE80211_NODE_HT), 3958193240Ssam ni->ni_ies.wme_ie != NULL ? WME(ni->ni_ies.wme_ie)->wme_info : 0); 3959193240Ssam if (error == 0) { 3960193240Ssam /* 3961193240Ssam * Setup security for this station. For sta mode this is 3962193240Ssam * needed even though do the same thing on transition to 3963193240Ssam * AUTH state because the call to mwl_hal_newstation 3964193240Ssam * clobbers the crypto state we setup. 3965193240Ssam */ 3966193240Ssam mwl_setanywepkey(vap, ni->ni_macaddr); 3967193240Ssam } 3968193240Ssam return error; 3969193240Ssam#undef WME 3970193240Ssam} 3971193240Ssam 3972193240Ssamstatic void 3973193240Ssammwl_setglobalkeys(struct ieee80211vap *vap) 3974193240Ssam{ 3975193240Ssam struct ieee80211_key *wk; 3976193240Ssam 3977193240Ssam wk = &vap->iv_nw_keys[0]; 3978193240Ssam for (; wk < &vap->iv_nw_keys[IEEE80211_WEP_NKID]; wk++) 3979193240Ssam if (wk->wk_keyix != IEEE80211_KEYIX_NONE) 3980193240Ssam (void) mwl_key_set(vap, wk, vap->iv_myaddr); 3981193240Ssam} 3982193240Ssam 3983193240Ssam/* 3984195171Ssam * Convert a legacy rate set to a firmware bitmask. 3985195171Ssam */ 3986195171Ssamstatic uint32_t 3987195171Ssamget_rate_bitmap(const struct ieee80211_rateset *rs) 3988195171Ssam{ 3989195171Ssam uint32_t rates; 3990195171Ssam int i; 3991195171Ssam 3992195171Ssam rates = 0; 3993195171Ssam for (i = 0; i < rs->rs_nrates; i++) 3994195171Ssam switch (rs->rs_rates[i] & IEEE80211_RATE_VAL) { 3995195171Ssam case 2: rates |= 0x001; break; 3996195171Ssam case 4: rates |= 0x002; break; 3997195171Ssam case 11: rates |= 0x004; break; 3998195171Ssam case 22: rates |= 0x008; break; 3999195171Ssam case 44: rates |= 0x010; break; 4000195171Ssam case 12: rates |= 0x020; break; 4001195171Ssam case 18: rates |= 0x040; break; 4002195171Ssam case 24: rates |= 0x080; break; 4003195171Ssam case 36: rates |= 0x100; break; 4004195171Ssam case 48: rates |= 0x200; break; 4005195171Ssam case 72: rates |= 0x400; break; 4006195171Ssam case 96: rates |= 0x800; break; 4007195171Ssam case 108: rates |= 0x1000; break; 4008195171Ssam } 4009195171Ssam return rates; 4010195171Ssam} 4011195171Ssam 4012195171Ssam/* 4013195171Ssam * Construct an HT firmware bitmask from an HT rate set. 4014195171Ssam */ 4015195171Ssamstatic uint32_t 4016195171Ssamget_htrate_bitmap(const struct ieee80211_htrateset *rs) 4017195171Ssam{ 4018195171Ssam uint32_t rates; 4019195171Ssam int i; 4020195171Ssam 4021195171Ssam rates = 0; 4022195171Ssam for (i = 0; i < rs->rs_nrates; i++) { 4023195171Ssam if (rs->rs_rates[i] < 16) 4024195171Ssam rates |= 1<<rs->rs_rates[i]; 4025195171Ssam } 4026195171Ssam return rates; 4027195171Ssam} 4028195171Ssam 4029195171Ssam/* 4030195171Ssam * Craft station database entry for station. 4031195171Ssam * NB: use host byte order here, the hal handles byte swapping. 4032195171Ssam */ 4033195171Ssamstatic MWL_HAL_PEERINFO * 4034195171Ssammkpeerinfo(MWL_HAL_PEERINFO *pi, const struct ieee80211_node *ni) 4035195171Ssam{ 4036195171Ssam const struct ieee80211vap *vap = ni->ni_vap; 4037195171Ssam 4038195171Ssam memset(pi, 0, sizeof(*pi)); 4039195171Ssam pi->LegacyRateBitMap = get_rate_bitmap(&ni->ni_rates); 4040195171Ssam pi->CapInfo = ni->ni_capinfo; 4041195171Ssam if (ni->ni_flags & IEEE80211_NODE_HT) { 4042195171Ssam /* HT capabilities, etc */ 4043195171Ssam pi->HTCapabilitiesInfo = ni->ni_htcap; 4044195171Ssam /* XXX pi.HTCapabilitiesInfo */ 4045195171Ssam pi->MacHTParamInfo = ni->ni_htparam; 4046195171Ssam pi->HTRateBitMap = get_htrate_bitmap(&ni->ni_htrates); 4047195171Ssam pi->AddHtInfo.ControlChan = ni->ni_htctlchan; 4048195171Ssam pi->AddHtInfo.AddChan = ni->ni_ht2ndchan; 4049195171Ssam pi->AddHtInfo.OpMode = ni->ni_htopmode; 4050195171Ssam pi->AddHtInfo.stbc = ni->ni_htstbc; 4051195171Ssam 4052195171Ssam /* constrain according to local configuration */ 4053195171Ssam if ((vap->iv_flags_ht & IEEE80211_FHT_SHORTGI40) == 0) 4054195171Ssam pi->HTCapabilitiesInfo &= ~IEEE80211_HTCAP_SHORTGI40; 4055195171Ssam if ((vap->iv_flags_ht & IEEE80211_FHT_SHORTGI20) == 0) 4056195171Ssam pi->HTCapabilitiesInfo &= ~IEEE80211_HTCAP_SHORTGI20; 4057195171Ssam if (ni->ni_chw != 40) 4058195171Ssam pi->HTCapabilitiesInfo &= ~IEEE80211_HTCAP_CHWIDTH40; 4059195171Ssam } 4060195171Ssam return pi; 4061195171Ssam} 4062195171Ssam 4063195171Ssam/* 4064193240Ssam * Re-create the local sta db entry for a vap to ensure 4065193240Ssam * up to date WME state is pushed to the firmware. Because 4066193240Ssam * this resets crypto state this must be followed by a 4067193240Ssam * reload of any keys in the global key table. 4068193240Ssam */ 4069193240Ssamstatic int 4070193240Ssammwl_localstadb(struct ieee80211vap *vap) 4071193240Ssam{ 4072193240Ssam#define WME(ie) ((const struct ieee80211_wme_info *) ie) 4073193240Ssam struct mwl_hal_vap *hvap = MWL_VAP(vap)->mv_hvap; 4074193240Ssam struct ieee80211_node *bss; 4075195171Ssam MWL_HAL_PEERINFO pi; 4076193240Ssam int error; 4077193240Ssam 4078193240Ssam switch (vap->iv_opmode) { 4079193240Ssam case IEEE80211_M_STA: 4080193240Ssam bss = vap->iv_bss; 4081195171Ssam error = mwl_hal_newstation(hvap, vap->iv_myaddr, 0, 0, 4082195171Ssam vap->iv_state == IEEE80211_S_RUN ? 4083195171Ssam mkpeerinfo(&pi, bss) : NULL, 4084195171Ssam (bss->ni_flags & (IEEE80211_NODE_QOS | IEEE80211_NODE_HT)), 4085193240Ssam bss->ni_ies.wme_ie != NULL ? 4086193240Ssam WME(bss->ni_ies.wme_ie)->wme_info : 0); 4087193240Ssam if (error == 0) 4088193240Ssam mwl_setglobalkeys(vap); 4089193240Ssam break; 4090193240Ssam case IEEE80211_M_HOSTAP: 4091195618Srpaulo case IEEE80211_M_MBSS: 4092193240Ssam error = mwl_hal_newstation(hvap, vap->iv_myaddr, 4093193240Ssam 0, 0, NULL, vap->iv_flags & IEEE80211_F_WME, 0); 4094193240Ssam if (error == 0) 4095193240Ssam mwl_setglobalkeys(vap); 4096193240Ssam break; 4097193240Ssam default: 4098193240Ssam error = 0; 4099193240Ssam break; 4100193240Ssam } 4101193240Ssam return error; 4102193240Ssam#undef WME 4103193240Ssam} 4104193240Ssam 4105193240Ssamstatic int 4106193240Ssammwl_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 4107193240Ssam{ 4108193240Ssam struct mwl_vap *mvp = MWL_VAP(vap); 4109193240Ssam struct mwl_hal_vap *hvap = mvp->mv_hvap; 4110193240Ssam struct ieee80211com *ic = vap->iv_ic; 4111193240Ssam struct ieee80211_node *ni = NULL; 4112287197Sglebius struct mwl_softc *sc = ic->ic_softc; 4113193240Ssam struct mwl_hal *mh = sc->sc_mh; 4114193240Ssam enum ieee80211_state ostate = vap->iv_state; 4115193240Ssam int error; 4116193240Ssam 4117193240Ssam DPRINTF(sc, MWL_DEBUG_STATE, "%s: %s: %s -> %s\n", 4118193240Ssam vap->iv_ifp->if_xname, __func__, 4119193240Ssam ieee80211_state_name[ostate], ieee80211_state_name[nstate]); 4120193240Ssam 4121193240Ssam callout_stop(&sc->sc_timer); 4122193240Ssam /* 4123193240Ssam * Clear current radar detection state. 4124193240Ssam */ 4125193240Ssam if (ostate == IEEE80211_S_CAC) { 4126193240Ssam /* stop quiet mode radar detection */ 4127193240Ssam mwl_hal_setradardetection(mh, DR_CHK_CHANNEL_AVAILABLE_STOP); 4128193240Ssam } else if (sc->sc_radarena) { 4129193240Ssam /* stop in-service radar detection */ 4130193240Ssam mwl_hal_setradardetection(mh, DR_DFS_DISABLE); 4131193240Ssam sc->sc_radarena = 0; 4132193240Ssam } 4133193240Ssam /* 4134193240Ssam * Carry out per-state actions before doing net80211 work. 4135193240Ssam */ 4136193240Ssam if (nstate == IEEE80211_S_INIT) { 4137193240Ssam /* NB: only ap+sta vap's have a fw entity */ 4138193240Ssam if (hvap != NULL) 4139193240Ssam mwl_hal_stop(hvap); 4140193240Ssam } else if (nstate == IEEE80211_S_SCAN) { 4141193240Ssam mwl_hal_start(hvap); 4142193240Ssam /* NB: this disables beacon frames */ 4143193240Ssam mwl_hal_setinframode(hvap); 4144193240Ssam } else if (nstate == IEEE80211_S_AUTH) { 4145193240Ssam /* 4146193240Ssam * Must create a sta db entry in case a WEP key needs to 4147193240Ssam * be plumbed. This entry will be overwritten if we 4148193240Ssam * associate; otherwise it will be reclaimed on node free. 4149193240Ssam */ 4150193240Ssam ni = vap->iv_bss; 4151193240Ssam MWL_NODE(ni)->mn_hvap = hvap; 4152193240Ssam (void) mwl_peerstadb(ni, 0, 0, NULL); 4153193240Ssam } else if (nstate == IEEE80211_S_CSA) { 4154193240Ssam /* XXX move to below? */ 4155195618Srpaulo if (vap->iv_opmode == IEEE80211_M_HOSTAP || 4156195618Srpaulo vap->iv_opmode == IEEE80211_M_MBSS) 4157193240Ssam mwl_startcsa(vap); 4158193240Ssam } else if (nstate == IEEE80211_S_CAC) { 4159193240Ssam /* XXX move to below? */ 4160193240Ssam /* stop ap xmit and enable quiet mode radar detection */ 4161193240Ssam mwl_hal_setradardetection(mh, DR_CHK_CHANNEL_AVAILABLE_START); 4162193240Ssam } 4163193240Ssam 4164193240Ssam /* 4165193240Ssam * Invoke the parent method to do net80211 work. 4166193240Ssam */ 4167193240Ssam error = mvp->mv_newstate(vap, nstate, arg); 4168193240Ssam 4169193240Ssam /* 4170193240Ssam * Carry out work that must be done after net80211 runs; 4171193240Ssam * this work requires up to date state (e.g. iv_bss). 4172193240Ssam */ 4173193240Ssam if (error == 0 && nstate == IEEE80211_S_RUN) { 4174193240Ssam /* NB: collect bss node again, it may have changed */ 4175193240Ssam ni = vap->iv_bss; 4176193240Ssam 4177193240Ssam DPRINTF(sc, MWL_DEBUG_STATE, 4178193240Ssam "%s: %s(RUN): iv_flags 0x%08x bintvl %d bssid %s " 4179193240Ssam "capinfo 0x%04x chan %d\n", 4180193240Ssam vap->iv_ifp->if_xname, __func__, vap->iv_flags, 4181193240Ssam ni->ni_intval, ether_sprintf(ni->ni_bssid), ni->ni_capinfo, 4182193240Ssam ieee80211_chan2ieee(ic, ic->ic_curchan)); 4183193240Ssam 4184193240Ssam /* 4185195171Ssam * Recreate local sta db entry to update WME/HT state. 4186193240Ssam */ 4187193240Ssam mwl_localstadb(vap); 4188193240Ssam switch (vap->iv_opmode) { 4189193240Ssam case IEEE80211_M_HOSTAP: 4190195618Srpaulo case IEEE80211_M_MBSS: 4191193240Ssam if (ostate == IEEE80211_S_CAC) { 4192193240Ssam /* enable in-service radar detection */ 4193193240Ssam mwl_hal_setradardetection(mh, 4194193240Ssam DR_IN_SERVICE_MONITOR_START); 4195193240Ssam sc->sc_radarena = 1; 4196193240Ssam } 4197193240Ssam /* 4198193240Ssam * Allocate and setup the beacon frame 4199193240Ssam * (and related state). 4200193240Ssam */ 4201193240Ssam error = mwl_reset_vap(vap, IEEE80211_S_RUN); 4202193240Ssam if (error != 0) { 4203193240Ssam DPRINTF(sc, MWL_DEBUG_STATE, 4204193240Ssam "%s: beacon setup failed, error %d\n", 4205193240Ssam __func__, error); 4206193240Ssam goto bad; 4207193240Ssam } 4208193240Ssam /* NB: must be after setting up beacon */ 4209193240Ssam mwl_hal_start(hvap); 4210193240Ssam break; 4211193240Ssam case IEEE80211_M_STA: 4212193240Ssam DPRINTF(sc, MWL_DEBUG_STATE, "%s: %s: aid 0x%x\n", 4213193240Ssam vap->iv_ifp->if_xname, __func__, ni->ni_associd); 4214193240Ssam /* 4215193240Ssam * Set state now that we're associated. 4216193240Ssam */ 4217193240Ssam mwl_hal_setassocid(hvap, ni->ni_bssid, ni->ni_associd); 4218193240Ssam mwl_setrates(vap); 4219193240Ssam mwl_hal_setrtsthreshold(hvap, vap->iv_rtsthreshold); 4220195171Ssam if ((vap->iv_flags & IEEE80211_F_DWDS) && 4221195171Ssam sc->sc_ndwdsvaps++ == 0) 4222195171Ssam mwl_hal_setdwds(mh, 1); 4223193240Ssam break; 4224193240Ssam case IEEE80211_M_WDS: 4225193240Ssam DPRINTF(sc, MWL_DEBUG_STATE, "%s: %s: bssid %s\n", 4226193240Ssam vap->iv_ifp->if_xname, __func__, 4227193240Ssam ether_sprintf(ni->ni_bssid)); 4228193240Ssam mwl_seteapolformat(vap); 4229193240Ssam break; 4230193240Ssam default: 4231193240Ssam break; 4232193240Ssam } 4233193240Ssam /* 4234193240Ssam * Set CS mode according to operating channel; 4235193240Ssam * this mostly an optimization for 5GHz. 4236193240Ssam * 4237193240Ssam * NB: must follow mwl_hal_start which resets csmode 4238193240Ssam */ 4239193240Ssam if (IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan)) 4240193240Ssam mwl_hal_setcsmode(mh, CSMODE_AGGRESSIVE); 4241193240Ssam else 4242193240Ssam mwl_hal_setcsmode(mh, CSMODE_AUTO_ENA); 4243193240Ssam /* 4244193240Ssam * Start timer to prod firmware. 4245193240Ssam */ 4246193240Ssam if (sc->sc_ageinterval != 0) 4247193240Ssam callout_reset(&sc->sc_timer, sc->sc_ageinterval*hz, 4248193240Ssam mwl_agestations, sc); 4249193240Ssam } else if (nstate == IEEE80211_S_SLEEP) { 4250193240Ssam /* XXX set chip in power save */ 4251195171Ssam } else if ((vap->iv_flags & IEEE80211_F_DWDS) && 4252195171Ssam --sc->sc_ndwdsvaps == 0) 4253195171Ssam mwl_hal_setdwds(mh, 0); 4254193240Ssambad: 4255193240Ssam return error; 4256193240Ssam} 4257193240Ssam 4258193240Ssam/* 4259193240Ssam * Manage station id's; these are separate from AID's 4260193240Ssam * as AID's may have values out of the range of possible 4261193240Ssam * station id's acceptable to the firmware. 4262193240Ssam */ 4263193240Ssamstatic int 4264193240Ssamallocstaid(struct mwl_softc *sc, int aid) 4265193240Ssam{ 4266193240Ssam int staid; 4267193240Ssam 4268193240Ssam if (!(0 < aid && aid < MWL_MAXSTAID) || isset(sc->sc_staid, aid)) { 4269193240Ssam /* NB: don't use 0 */ 4270193240Ssam for (staid = 1; staid < MWL_MAXSTAID; staid++) 4271193240Ssam if (isclr(sc->sc_staid, staid)) 4272193240Ssam break; 4273193240Ssam } else 4274193240Ssam staid = aid; 4275193240Ssam setbit(sc->sc_staid, staid); 4276193240Ssam return staid; 4277193240Ssam} 4278193240Ssam 4279193240Ssamstatic void 4280193240Ssamdelstaid(struct mwl_softc *sc, int staid) 4281193240Ssam{ 4282193240Ssam clrbit(sc->sc_staid, staid); 4283193240Ssam} 4284193240Ssam 4285193240Ssam/* 4286193240Ssam * Setup driver-specific state for a newly associated node. 4287193240Ssam * Note that we're called also on a re-associate, the isnew 4288193240Ssam * param tells us if this is the first time or not. 4289193240Ssam */ 4290193240Ssamstatic void 4291193240Ssammwl_newassoc(struct ieee80211_node *ni, int isnew) 4292193240Ssam{ 4293193240Ssam struct ieee80211vap *vap = ni->ni_vap; 4294287197Sglebius struct mwl_softc *sc = vap->iv_ic->ic_softc; 4295193240Ssam struct mwl_node *mn = MWL_NODE(ni); 4296193240Ssam MWL_HAL_PEERINFO pi; 4297193240Ssam uint16_t aid; 4298193240Ssam int error; 4299193240Ssam 4300193240Ssam aid = IEEE80211_AID(ni->ni_associd); 4301193240Ssam if (isnew) { 4302193240Ssam mn->mn_staid = allocstaid(sc, aid); 4303193240Ssam mn->mn_hvap = MWL_VAP(vap)->mv_hvap; 4304193240Ssam } else { 4305193240Ssam mn = MWL_NODE(ni); 4306193240Ssam /* XXX reset BA stream? */ 4307193240Ssam } 4308193240Ssam DPRINTF(sc, MWL_DEBUG_NODE, "%s: mac %s isnew %d aid %d staid %d\n", 4309193240Ssam __func__, ether_sprintf(ni->ni_macaddr), isnew, aid, mn->mn_staid); 4310195171Ssam error = mwl_peerstadb(ni, aid, mn->mn_staid, mkpeerinfo(&pi, ni)); 4311193240Ssam if (error != 0) { 4312193240Ssam DPRINTF(sc, MWL_DEBUG_NODE, 4313193240Ssam "%s: error %d creating sta db entry\n", 4314193240Ssam __func__, error); 4315193240Ssam /* XXX how to deal with error? */ 4316193240Ssam } 4317193240Ssam} 4318193240Ssam 4319193240Ssam/* 4320193240Ssam * Periodically poke the firmware to age out station state 4321193240Ssam * (power save queues, pending tx aggregates). 4322193240Ssam */ 4323193240Ssamstatic void 4324193240Ssammwl_agestations(void *arg) 4325193240Ssam{ 4326193240Ssam struct mwl_softc *sc = arg; 4327193240Ssam 4328193240Ssam mwl_hal_setkeepalive(sc->sc_mh); 4329193240Ssam if (sc->sc_ageinterval != 0) /* NB: catch dynamic changes */ 4330195171Ssam callout_schedule(&sc->sc_timer, sc->sc_ageinterval*hz); 4331193240Ssam} 4332193240Ssam 4333193240Ssamstatic const struct mwl_hal_channel * 4334193240Ssamfindhalchannel(const MWL_HAL_CHANNELINFO *ci, int ieee) 4335193240Ssam{ 4336193240Ssam int i; 4337193240Ssam 4338193240Ssam for (i = 0; i < ci->nchannels; i++) { 4339193240Ssam const struct mwl_hal_channel *hc = &ci->channels[i]; 4340193240Ssam if (hc->ieee == ieee) 4341193240Ssam return hc; 4342193240Ssam } 4343193240Ssam return NULL; 4344193240Ssam} 4345193240Ssam 4346193240Ssamstatic int 4347193240Ssammwl_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *rd, 4348193240Ssam int nchan, struct ieee80211_channel chans[]) 4349193240Ssam{ 4350287197Sglebius struct mwl_softc *sc = ic->ic_softc; 4351193240Ssam struct mwl_hal *mh = sc->sc_mh; 4352193240Ssam const MWL_HAL_CHANNELINFO *ci; 4353193240Ssam int i; 4354193240Ssam 4355193240Ssam for (i = 0; i < nchan; i++) { 4356193240Ssam struct ieee80211_channel *c = &chans[i]; 4357193240Ssam const struct mwl_hal_channel *hc; 4358193240Ssam 4359193240Ssam if (IEEE80211_IS_CHAN_2GHZ(c)) { 4360193240Ssam mwl_hal_getchannelinfo(mh, MWL_FREQ_BAND_2DOT4GHZ, 4361193240Ssam IEEE80211_IS_CHAN_HT40(c) ? 4362193240Ssam MWL_CH_40_MHz_WIDTH : MWL_CH_20_MHz_WIDTH, &ci); 4363193240Ssam } else if (IEEE80211_IS_CHAN_5GHZ(c)) { 4364193240Ssam mwl_hal_getchannelinfo(mh, MWL_FREQ_BAND_5GHZ, 4365193240Ssam IEEE80211_IS_CHAN_HT40(c) ? 4366193240Ssam MWL_CH_40_MHz_WIDTH : MWL_CH_20_MHz_WIDTH, &ci); 4367193240Ssam } else { 4368287197Sglebius device_printf(sc->sc_dev, 4369193240Ssam "%s: channel %u freq %u/0x%x not 2.4/5GHz\n", 4370193240Ssam __func__, c->ic_ieee, c->ic_freq, c->ic_flags); 4371193240Ssam return EINVAL; 4372193240Ssam } 4373193240Ssam /* 4374193240Ssam * Verify channel has cal data and cap tx power. 4375193240Ssam */ 4376193240Ssam hc = findhalchannel(ci, c->ic_ieee); 4377193240Ssam if (hc != NULL) { 4378193240Ssam if (c->ic_maxpower > 2*hc->maxTxPow) 4379193240Ssam c->ic_maxpower = 2*hc->maxTxPow; 4380193240Ssam goto next; 4381193240Ssam } 4382193240Ssam if (IEEE80211_IS_CHAN_HT40(c)) { 4383193240Ssam /* 4384193240Ssam * Look for the extension channel since the 4385193240Ssam * hal table only has the primary channel. 4386193240Ssam */ 4387193240Ssam hc = findhalchannel(ci, c->ic_extieee); 4388193240Ssam if (hc != NULL) { 4389193240Ssam if (c->ic_maxpower > 2*hc->maxTxPow) 4390193240Ssam c->ic_maxpower = 2*hc->maxTxPow; 4391193240Ssam goto next; 4392193240Ssam } 4393193240Ssam } 4394287197Sglebius device_printf(sc->sc_dev, 4395193240Ssam "%s: no cal data for channel %u ext %u freq %u/0x%x\n", 4396193240Ssam __func__, c->ic_ieee, c->ic_extieee, 4397193240Ssam c->ic_freq, c->ic_flags); 4398193240Ssam return EINVAL; 4399193240Ssam next: 4400193240Ssam ; 4401193240Ssam } 4402193240Ssam return 0; 4403193240Ssam} 4404193240Ssam 4405193240Ssam#define IEEE80211_CHAN_HTG (IEEE80211_CHAN_HT|IEEE80211_CHAN_G) 4406193240Ssam#define IEEE80211_CHAN_HTA (IEEE80211_CHAN_HT|IEEE80211_CHAN_A) 4407193240Ssam 4408193240Ssamstatic void 4409193240Ssamaddchan(struct ieee80211_channel *c, int freq, int flags, int ieee, int txpow) 4410193240Ssam{ 4411193240Ssam c->ic_freq = freq; 4412193240Ssam c->ic_flags = flags; 4413193240Ssam c->ic_ieee = ieee; 4414193240Ssam c->ic_minpower = 0; 4415193240Ssam c->ic_maxpower = 2*txpow; 4416193240Ssam c->ic_maxregpower = txpow; 4417193240Ssam} 4418193240Ssam 4419193240Ssamstatic const struct ieee80211_channel * 4420193240Ssamfindchannel(const struct ieee80211_channel chans[], int nchans, 4421193240Ssam int freq, int flags) 4422193240Ssam{ 4423193240Ssam const struct ieee80211_channel *c; 4424193240Ssam int i; 4425193240Ssam 4426193240Ssam for (i = 0; i < nchans; i++) { 4427193240Ssam c = &chans[i]; 4428193240Ssam if (c->ic_freq == freq && c->ic_flags == flags) 4429193240Ssam return c; 4430193240Ssam } 4431193240Ssam return NULL; 4432193240Ssam} 4433193240Ssam 4434193240Ssamstatic void 4435193240Ssamaddht40channels(struct ieee80211_channel chans[], int maxchans, int *nchans, 4436193240Ssam const MWL_HAL_CHANNELINFO *ci, int flags) 4437193240Ssam{ 4438193240Ssam struct ieee80211_channel *c; 4439193240Ssam const struct ieee80211_channel *extc; 4440193240Ssam const struct mwl_hal_channel *hc; 4441193240Ssam int i; 4442193240Ssam 4443193240Ssam c = &chans[*nchans]; 4444193240Ssam 4445193240Ssam flags &= ~IEEE80211_CHAN_HT; 4446193240Ssam for (i = 0; i < ci->nchannels; i++) { 4447193240Ssam /* 4448193240Ssam * Each entry defines an HT40 channel pair; find the 4449193240Ssam * extension channel above and the insert the pair. 4450193240Ssam */ 4451193240Ssam hc = &ci->channels[i]; 4452193240Ssam extc = findchannel(chans, *nchans, hc->freq+20, 4453193240Ssam flags | IEEE80211_CHAN_HT20); 4454193240Ssam if (extc != NULL) { 4455193240Ssam if (*nchans >= maxchans) 4456193240Ssam break; 4457193240Ssam addchan(c, hc->freq, flags | IEEE80211_CHAN_HT40U, 4458193240Ssam hc->ieee, hc->maxTxPow); 4459193240Ssam c->ic_extieee = extc->ic_ieee; 4460193240Ssam c++, (*nchans)++; 4461193240Ssam if (*nchans >= maxchans) 4462193240Ssam break; 4463193240Ssam addchan(c, extc->ic_freq, flags | IEEE80211_CHAN_HT40D, 4464193240Ssam extc->ic_ieee, hc->maxTxPow); 4465193240Ssam c->ic_extieee = hc->ieee; 4466193240Ssam c++, (*nchans)++; 4467193240Ssam } 4468193240Ssam } 4469193240Ssam} 4470193240Ssam 4471193240Ssamstatic void 4472193240Ssamaddchannels(struct ieee80211_channel chans[], int maxchans, int *nchans, 4473193240Ssam const MWL_HAL_CHANNELINFO *ci, int flags) 4474193240Ssam{ 4475193240Ssam struct ieee80211_channel *c; 4476193240Ssam int i; 4477193240Ssam 4478193240Ssam c = &chans[*nchans]; 4479193240Ssam 4480193240Ssam for (i = 0; i < ci->nchannels; i++) { 4481193240Ssam const struct mwl_hal_channel *hc; 4482193240Ssam 4483193240Ssam hc = &ci->channels[i]; 4484193240Ssam if (*nchans >= maxchans) 4485193240Ssam break; 4486193240Ssam addchan(c, hc->freq, flags, hc->ieee, hc->maxTxPow); 4487193240Ssam c++, (*nchans)++; 4488193240Ssam if (flags == IEEE80211_CHAN_G || flags == IEEE80211_CHAN_HTG) { 4489193240Ssam /* g channel have a separate b-only entry */ 4490193240Ssam if (*nchans >= maxchans) 4491193240Ssam break; 4492193240Ssam c[0] = c[-1]; 4493193240Ssam c[-1].ic_flags = IEEE80211_CHAN_B; 4494193240Ssam c++, (*nchans)++; 4495193240Ssam } 4496193240Ssam if (flags == IEEE80211_CHAN_HTG) { 4497193240Ssam /* HT g channel have a separate g-only entry */ 4498193240Ssam if (*nchans >= maxchans) 4499193240Ssam break; 4500193240Ssam c[-1].ic_flags = IEEE80211_CHAN_G; 4501193240Ssam c[0] = c[-1]; 4502193240Ssam c[0].ic_flags &= ~IEEE80211_CHAN_HT; 4503193240Ssam c[0].ic_flags |= IEEE80211_CHAN_HT20; /* HT20 */ 4504193240Ssam c++, (*nchans)++; 4505193240Ssam } 4506193240Ssam if (flags == IEEE80211_CHAN_HTA) { 4507193240Ssam /* HT a channel have a separate a-only entry */ 4508193240Ssam if (*nchans >= maxchans) 4509193240Ssam break; 4510193240Ssam c[-1].ic_flags = IEEE80211_CHAN_A; 4511193240Ssam c[0] = c[-1]; 4512193240Ssam c[0].ic_flags &= ~IEEE80211_CHAN_HT; 4513193240Ssam c[0].ic_flags |= IEEE80211_CHAN_HT20; /* HT20 */ 4514193240Ssam c++, (*nchans)++; 4515193240Ssam } 4516193240Ssam } 4517193240Ssam} 4518193240Ssam 4519193240Ssamstatic void 4520193240Ssamgetchannels(struct mwl_softc *sc, int maxchans, int *nchans, 4521193240Ssam struct ieee80211_channel chans[]) 4522193240Ssam{ 4523193240Ssam const MWL_HAL_CHANNELINFO *ci; 4524193240Ssam 4525193240Ssam /* 4526193240Ssam * Use the channel info from the hal to craft the 4527193240Ssam * channel list. Note that we pass back an unsorted 4528193240Ssam * list; the caller is required to sort it for us 4529193240Ssam * (if desired). 4530193240Ssam */ 4531193240Ssam *nchans = 0; 4532193240Ssam if (mwl_hal_getchannelinfo(sc->sc_mh, 4533193240Ssam MWL_FREQ_BAND_2DOT4GHZ, MWL_CH_20_MHz_WIDTH, &ci) == 0) 4534193240Ssam addchannels(chans, maxchans, nchans, ci, IEEE80211_CHAN_HTG); 4535193240Ssam if (mwl_hal_getchannelinfo(sc->sc_mh, 4536193240Ssam MWL_FREQ_BAND_5GHZ, MWL_CH_20_MHz_WIDTH, &ci) == 0) 4537193240Ssam addchannels(chans, maxchans, nchans, ci, IEEE80211_CHAN_HTA); 4538193240Ssam if (mwl_hal_getchannelinfo(sc->sc_mh, 4539193240Ssam MWL_FREQ_BAND_2DOT4GHZ, MWL_CH_40_MHz_WIDTH, &ci) == 0) 4540193240Ssam addht40channels(chans, maxchans, nchans, ci, IEEE80211_CHAN_HTG); 4541193240Ssam if (mwl_hal_getchannelinfo(sc->sc_mh, 4542193240Ssam MWL_FREQ_BAND_5GHZ, MWL_CH_40_MHz_WIDTH, &ci) == 0) 4543193240Ssam addht40channels(chans, maxchans, nchans, ci, IEEE80211_CHAN_HTA); 4544193240Ssam} 4545193240Ssam 4546193240Ssamstatic void 4547193240Ssammwl_getradiocaps(struct ieee80211com *ic, 4548193240Ssam int maxchans, int *nchans, struct ieee80211_channel chans[]) 4549193240Ssam{ 4550287197Sglebius struct mwl_softc *sc = ic->ic_softc; 4551193240Ssam 4552193240Ssam getchannels(sc, maxchans, nchans, chans); 4553193240Ssam} 4554193240Ssam 4555193240Ssamstatic int 4556193240Ssammwl_getchannels(struct mwl_softc *sc) 4557193240Ssam{ 4558287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 4559193240Ssam 4560193240Ssam /* 4561193240Ssam * Use the channel info from the hal to craft the 4562193240Ssam * channel list for net80211. Note that we pass up 4563193240Ssam * an unsorted list; net80211 will sort it for us. 4564193240Ssam */ 4565193240Ssam memset(ic->ic_channels, 0, sizeof(ic->ic_channels)); 4566193240Ssam ic->ic_nchans = 0; 4567193240Ssam getchannels(sc, IEEE80211_CHAN_MAX, &ic->ic_nchans, ic->ic_channels); 4568193240Ssam 4569193240Ssam ic->ic_regdomain.regdomain = SKU_DEBUG; 4570193240Ssam ic->ic_regdomain.country = CTRY_DEFAULT; 4571193240Ssam ic->ic_regdomain.location = 'I'; 4572193240Ssam ic->ic_regdomain.isocc[0] = ' '; /* XXX? */ 4573193240Ssam ic->ic_regdomain.isocc[1] = ' '; 4574193240Ssam return (ic->ic_nchans == 0 ? EIO : 0); 4575193240Ssam} 4576193240Ssam#undef IEEE80211_CHAN_HTA 4577193240Ssam#undef IEEE80211_CHAN_HTG 4578193240Ssam 4579193240Ssam#ifdef MWL_DEBUG 4580193240Ssamstatic void 4581193240Ssammwl_printrxbuf(const struct mwl_rxbuf *bf, u_int ix) 4582193240Ssam{ 4583193240Ssam const struct mwl_rxdesc *ds = bf->bf_desc; 4584193240Ssam uint32_t status = le32toh(ds->Status); 4585193240Ssam 4586278532Smarius printf("R[%2u] (DS.V:%p DS.P:0x%jx) NEXT:%08x DATA:%08x RC:%02x%s\n" 4587193240Ssam " STAT:%02x LEN:%04x RSSI:%02x CHAN:%02x RATE:%02x QOS:%04x HT:%04x\n", 4588278532Smarius ix, ds, (uintmax_t)bf->bf_daddr, le32toh(ds->pPhysNext), 4589278532Smarius le32toh(ds->pPhysBuffData), ds->RxControl, 4590193240Ssam ds->RxControl != EAGLE_RXD_CTRL_DRIVER_OWN ? 4591193240Ssam "" : (status & EAGLE_RXD_STATUS_OK) ? " *" : " !", 4592193240Ssam ds->Status, le16toh(ds->PktLen), ds->RSSI, ds->Channel, 4593193240Ssam ds->Rate, le16toh(ds->QosCtrl), le16toh(ds->HtSig2)); 4594193240Ssam} 4595193240Ssam 4596193240Ssamstatic void 4597193240Ssammwl_printtxbuf(const struct mwl_txbuf *bf, u_int qnum, u_int ix) 4598193240Ssam{ 4599193240Ssam const struct mwl_txdesc *ds = bf->bf_desc; 4600193240Ssam uint32_t status = le32toh(ds->Status); 4601193240Ssam 4602193240Ssam printf("Q%u[%3u]", qnum, ix); 4603278532Smarius printf(" (DS.V:%p DS.P:0x%jx)\n", ds, (uintmax_t)bf->bf_daddr); 4604193240Ssam printf(" NEXT:%08x DATA:%08x LEN:%04x STAT:%08x%s\n", 4605193240Ssam le32toh(ds->pPhysNext), 4606193240Ssam le32toh(ds->PktPtr), le16toh(ds->PktLen), status, 4607193240Ssam status & EAGLE_TXD_STATUS_USED ? 4608193240Ssam "" : (status & 3) != 0 ? " *" : " !"); 4609193240Ssam printf(" RATE:%02x PRI:%x QOS:%04x SAP:%08x FORMAT:%04x\n", 4610193240Ssam ds->DataRate, ds->TxPriority, le16toh(ds->QosCtrl), 4611193240Ssam le32toh(ds->SapPktInfo), le16toh(ds->Format)); 4612193240Ssam#if MWL_TXDESC > 1 4613193240Ssam printf(" MULTIFRAMES:%u LEN:%04x %04x %04x %04x %04x %04x\n" 4614193240Ssam , le32toh(ds->multiframes) 4615193240Ssam , le16toh(ds->PktLenArray[0]), le16toh(ds->PktLenArray[1]) 4616193240Ssam , le16toh(ds->PktLenArray[2]), le16toh(ds->PktLenArray[3]) 4617193240Ssam , le16toh(ds->PktLenArray[4]), le16toh(ds->PktLenArray[5]) 4618193240Ssam ); 4619193240Ssam printf(" DATA:%08x %08x %08x %08x %08x %08x\n" 4620193240Ssam , le32toh(ds->PktPtrArray[0]), le32toh(ds->PktPtrArray[1]) 4621193240Ssam , le32toh(ds->PktPtrArray[2]), le32toh(ds->PktPtrArray[3]) 4622193240Ssam , le32toh(ds->PktPtrArray[4]), le32toh(ds->PktPtrArray[5]) 4623193240Ssam ); 4624193240Ssam#endif 4625193240Ssam#if 0 4626193240Ssam{ const uint8_t *cp = (const uint8_t *) ds; 4627193240Ssam int i; 4628193240Ssam for (i = 0; i < sizeof(struct mwl_txdesc); i++) { 4629193240Ssam printf("%02x ", cp[i]); 4630193240Ssam if (((i+1) % 16) == 0) 4631193240Ssam printf("\n"); 4632193240Ssam } 4633193240Ssam printf("\n"); 4634193240Ssam} 4635193240Ssam#endif 4636193240Ssam} 4637193240Ssam#endif /* MWL_DEBUG */ 4638193240Ssam 4639193240Ssam#if 0 4640193240Ssamstatic void 4641193240Ssammwl_txq_dump(struct mwl_txq *txq) 4642193240Ssam{ 4643193240Ssam struct mwl_txbuf *bf; 4644193240Ssam int i = 0; 4645193240Ssam 4646193240Ssam MWL_TXQ_LOCK(txq); 4647193240Ssam STAILQ_FOREACH(bf, &txq->active, bf_list) { 4648193240Ssam struct mwl_txdesc *ds = bf->bf_desc; 4649193240Ssam MWL_TXDESC_SYNC(txq, ds, 4650193240Ssam BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4651193240Ssam#ifdef MWL_DEBUG 4652193240Ssam mwl_printtxbuf(bf, txq->qnum, i); 4653193240Ssam#endif 4654193240Ssam i++; 4655193240Ssam } 4656193240Ssam MWL_TXQ_UNLOCK(txq); 4657193240Ssam} 4658193240Ssam#endif 4659193240Ssam 4660193240Ssamstatic void 4661199559Sjhbmwl_watchdog(void *arg) 4662193240Ssam{ 4663287197Sglebius struct mwl_softc *sc = arg; 4664193240Ssam 4665199559Sjhb callout_reset(&sc->sc_watchdog, hz, mwl_watchdog, sc); 4666199559Sjhb if (sc->sc_tx_timer == 0 || --sc->sc_tx_timer > 0) 4667199559Sjhb return; 4668199559Sjhb 4669287197Sglebius if (sc->sc_running && !sc->sc_invalid) { 4670193240Ssam if (mwl_hal_setkeepalive(sc->sc_mh)) 4671287197Sglebius device_printf(sc->sc_dev, 4672287197Sglebius "transmit timeout (firmware hung?)\n"); 4673193240Ssam else 4674287197Sglebius device_printf(sc->sc_dev, 4675287197Sglebius "transmit timeout\n"); 4676193240Ssam#if 0 4677287197Sglebius mwl_reset(sc); 4678193240Ssammwl_txq_dump(&sc->sc_txq[0]);/*XXX*/ 4679193240Ssam#endif 4680287197Sglebius counter_u64_add(sc->sc_ic.ic_oerrors, 1); 4681193240Ssam sc->sc_stats.mst_watchdog++; 4682193240Ssam } 4683193240Ssam} 4684193240Ssam 4685193240Ssam#ifdef MWL_DIAGAPI 4686193240Ssam/* 4687193240Ssam * Diagnostic interface to the HAL. This is used by various 4688193240Ssam * tools to do things like retrieve register contents for 4689193240Ssam * debugging. The mechanism is intentionally opaque so that 4690193240Ssam * it can change frequently w/o concern for compatiblity. 4691193240Ssam */ 4692193240Ssamstatic int 4693193240Ssammwl_ioctl_diag(struct mwl_softc *sc, struct mwl_diag *md) 4694193240Ssam{ 4695193240Ssam struct mwl_hal *mh = sc->sc_mh; 4696193240Ssam u_int id = md->md_id & MWL_DIAG_ID; 4697193240Ssam void *indata = NULL; 4698193240Ssam void *outdata = NULL; 4699193240Ssam u_int32_t insize = md->md_in_size; 4700193240Ssam u_int32_t outsize = md->md_out_size; 4701193240Ssam int error = 0; 4702193240Ssam 4703193240Ssam if (md->md_id & MWL_DIAG_IN) { 4704193240Ssam /* 4705193240Ssam * Copy in data. 4706193240Ssam */ 4707193240Ssam indata = malloc(insize, M_TEMP, M_NOWAIT); 4708193240Ssam if (indata == NULL) { 4709193240Ssam error = ENOMEM; 4710193240Ssam goto bad; 4711193240Ssam } 4712193240Ssam error = copyin(md->md_in_data, indata, insize); 4713193240Ssam if (error) 4714193240Ssam goto bad; 4715193240Ssam } 4716193240Ssam if (md->md_id & MWL_DIAG_DYN) { 4717193240Ssam /* 4718193240Ssam * Allocate a buffer for the results (otherwise the HAL 4719193240Ssam * returns a pointer to a buffer where we can read the 4720193240Ssam * results). Note that we depend on the HAL leaving this 4721193240Ssam * pointer for us to use below in reclaiming the buffer; 4722193240Ssam * may want to be more defensive. 4723193240Ssam */ 4724193240Ssam outdata = malloc(outsize, M_TEMP, M_NOWAIT); 4725193240Ssam if (outdata == NULL) { 4726193240Ssam error = ENOMEM; 4727193240Ssam goto bad; 4728193240Ssam } 4729193240Ssam } 4730193240Ssam if (mwl_hal_getdiagstate(mh, id, indata, insize, &outdata, &outsize)) { 4731193240Ssam if (outsize < md->md_out_size) 4732193240Ssam md->md_out_size = outsize; 4733193240Ssam if (outdata != NULL) 4734193240Ssam error = copyout(outdata, md->md_out_data, 4735193240Ssam md->md_out_size); 4736193240Ssam } else { 4737193240Ssam error = EINVAL; 4738193240Ssam } 4739193240Ssambad: 4740193240Ssam if ((md->md_id & MWL_DIAG_IN) && indata != NULL) 4741193240Ssam free(indata, M_TEMP); 4742193240Ssam if ((md->md_id & MWL_DIAG_DYN) && outdata != NULL) 4743193240Ssam free(outdata, M_TEMP); 4744193240Ssam return error; 4745193240Ssam} 4746193240Ssam 4747193240Ssamstatic int 4748193240Ssammwl_ioctl_reset(struct mwl_softc *sc, struct mwl_diag *md) 4749193240Ssam{ 4750193240Ssam struct mwl_hal *mh = sc->sc_mh; 4751193240Ssam int error; 4752193240Ssam 4753193240Ssam MWL_LOCK_ASSERT(sc); 4754193240Ssam 4755193240Ssam if (md->md_id == 0 && mwl_hal_fwload(mh, NULL) != 0) { 4756193240Ssam device_printf(sc->sc_dev, "unable to load firmware\n"); 4757193240Ssam return EIO; 4758193240Ssam } 4759193240Ssam if (mwl_hal_gethwspecs(mh, &sc->sc_hwspecs) != 0) { 4760193240Ssam device_printf(sc->sc_dev, "unable to fetch h/w specs\n"); 4761193240Ssam return EIO; 4762193240Ssam } 4763193240Ssam error = mwl_setupdma(sc); 4764193240Ssam if (error != 0) { 4765193240Ssam /* NB: mwl_setupdma prints a msg */ 4766193240Ssam return error; 4767193240Ssam } 4768193240Ssam /* 4769193240Ssam * Reset tx/rx data structures; after reload we must 4770193240Ssam * re-start the driver's notion of the next xmit/recv. 4771193240Ssam */ 4772193240Ssam mwl_draintxq(sc); /* clear pending frames */ 4773193240Ssam mwl_resettxq(sc); /* rebuild tx q lists */ 4774193240Ssam sc->sc_rxnext = NULL; /* force rx to start at the list head */ 4775193240Ssam return 0; 4776193240Ssam} 4777193240Ssam#endif /* MWL_DIAGAPI */ 4778193240Ssam 4779287197Sglebiusstatic void 4780287197Sglebiusmwl_parent(struct ieee80211com *ic) 4781193240Ssam{ 4782287197Sglebius struct mwl_softc *sc = ic->ic_softc; 4783287197Sglebius int startall = 0; 4784193240Ssam 4785287197Sglebius MWL_LOCK(sc); 4786287197Sglebius if (ic->ic_nrunning > 0) { 4787287197Sglebius if (sc->sc_running) { 4788193240Ssam /* 4789193240Ssam * To avoid rescanning another access point, 4790193240Ssam * do not call mwl_init() here. Instead, 4791193240Ssam * only reflect promisc mode settings. 4792193240Ssam */ 4793193240Ssam mwl_mode_init(sc); 4794287197Sglebius } else { 4795193240Ssam /* 4796193240Ssam * Beware of being called during attach/detach 4797193240Ssam * to reset promiscuous mode. In that case we 4798193240Ssam * will still be marked UP but not RUNNING. 4799193240Ssam * However trying to re-init the interface 4800193240Ssam * is the wrong thing to do as we've already 4801193240Ssam * torn down much of our state. There's 4802193240Ssam * probably a better way to deal with this. 4803193240Ssam */ 4804193240Ssam if (!sc->sc_invalid) { 4805287197Sglebius mwl_init(sc); /* XXX lose error */ 4806193240Ssam startall = 1; 4807193240Ssam } 4808287197Sglebius } 4809287197Sglebius } else 4810287197Sglebius mwl_stop(sc); 4811287197Sglebius MWL_UNLOCK(sc); 4812287197Sglebius if (startall) 4813287197Sglebius ieee80211_start_all(ic); 4814287197Sglebius} 4815287197Sglebius 4816287197Sglebiusstatic int 4817287197Sglebiusmwl_ioctl(struct ieee80211com *ic, u_long cmd, void *data) 4818287197Sglebius{ 4819287197Sglebius struct mwl_softc *sc = ic->ic_softc; 4820287197Sglebius struct ifreq *ifr = data; 4821287197Sglebius int error = 0; 4822287197Sglebius 4823287197Sglebius switch (cmd) { 4824193240Ssam case SIOCGMVSTATS: 4825193240Ssam mwl_hal_gethwstats(sc->sc_mh, &sc->sc_stats.hw_stats); 4826287197Sglebius#if 0 4827193240Ssam /* NB: embed these numbers to get a consistent view */ 4828271810Sglebius sc->sc_stats.mst_tx_packets = 4829271810Sglebius ifp->if_get_counter(ifp, IFCOUNTER_OPACKETS); 4830271810Sglebius sc->sc_stats.mst_rx_packets = 4831271810Sglebius ifp->if_get_counter(ifp, IFCOUNTER_IPACKETS); 4832287197Sglebius#endif 4833193240Ssam /* 4834193240Ssam * NB: Drop the softc lock in case of a page fault; 4835193240Ssam * we'll accept any potential inconsisentcy in the 4836193240Ssam * statistics. The alternative is to copy the data 4837193240Ssam * to a local structure. 4838193240Ssam */ 4839287197Sglebius return (copyout(&sc->sc_stats, 4840287197Sglebius ifr->ifr_data, sizeof (sc->sc_stats))); 4841193240Ssam#ifdef MWL_DIAGAPI 4842193240Ssam case SIOCGMVDIAG: 4843193240Ssam /* XXX check privs */ 4844193240Ssam return mwl_ioctl_diag(sc, (struct mwl_diag *) ifr); 4845193240Ssam case SIOCGMVRESET: 4846193240Ssam /* XXX check privs */ 4847193240Ssam MWL_LOCK(sc); 4848193240Ssam error = mwl_ioctl_reset(sc,(struct mwl_diag *) ifr); 4849193240Ssam MWL_UNLOCK(sc); 4850193240Ssam break; 4851193240Ssam#endif /* MWL_DIAGAPI */ 4852193240Ssam default: 4853287197Sglebius error = ENOTTY; 4854193240Ssam break; 4855193240Ssam } 4856287197Sglebius return (error); 4857193240Ssam} 4858193240Ssam 4859193240Ssam#ifdef MWL_DEBUG 4860193240Ssamstatic int 4861193240Ssammwl_sysctl_debug(SYSCTL_HANDLER_ARGS) 4862193240Ssam{ 4863193240Ssam struct mwl_softc *sc = arg1; 4864193240Ssam int debug, error; 4865193240Ssam 4866193240Ssam debug = sc->sc_debug | (mwl_hal_getdebug(sc->sc_mh) << 24); 4867193240Ssam error = sysctl_handle_int(oidp, &debug, 0, req); 4868193240Ssam if (error || !req->newptr) 4869193240Ssam return error; 4870193240Ssam mwl_hal_setdebug(sc->sc_mh, debug >> 24); 4871193240Ssam sc->sc_debug = debug & 0x00ffffff; 4872193240Ssam return 0; 4873193240Ssam} 4874193240Ssam#endif /* MWL_DEBUG */ 4875193240Ssam 4876193240Ssamstatic void 4877193240Ssammwl_sysctlattach(struct mwl_softc *sc) 4878193240Ssam{ 4879193240Ssam#ifdef MWL_DEBUG 4880193240Ssam struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev); 4881193240Ssam struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev); 4882193240Ssam 4883193240Ssam sc->sc_debug = mwl_debug; 4884193240Ssam SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 4885193240Ssam "debug", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 4886193240Ssam mwl_sysctl_debug, "I", "control debugging printfs"); 4887193240Ssam#endif 4888193240Ssam} 4889193240Ssam 4890193240Ssam/* 4891193240Ssam * Announce various information on device/driver attach. 4892193240Ssam */ 4893193240Ssamstatic void 4894193240Ssammwl_announce(struct mwl_softc *sc) 4895193240Ssam{ 4896193240Ssam 4897287197Sglebius device_printf(sc->sc_dev, "Rev A%d hardware, v%d.%d.%d.%d firmware (regioncode %d)\n", 4898193240Ssam sc->sc_hwspecs.hwVersion, 4899193240Ssam (sc->sc_hwspecs.fwReleaseNumber>>24) & 0xff, 4900193240Ssam (sc->sc_hwspecs.fwReleaseNumber>>16) & 0xff, 4901193240Ssam (sc->sc_hwspecs.fwReleaseNumber>>8) & 0xff, 4902193240Ssam (sc->sc_hwspecs.fwReleaseNumber>>0) & 0xff, 4903193240Ssam sc->sc_hwspecs.regionCode); 4904193240Ssam sc->sc_fwrelease = sc->sc_hwspecs.fwReleaseNumber; 4905193240Ssam 4906193240Ssam if (bootverbose) { 4907193240Ssam int i; 4908193240Ssam for (i = 0; i <= WME_AC_VO; i++) { 4909193240Ssam struct mwl_txq *txq = sc->sc_ac2q[i]; 4910287197Sglebius device_printf(sc->sc_dev, "Use hw queue %u for %s traffic\n", 4911193240Ssam txq->qnum, ieee80211_wme_acnames[i]); 4912193240Ssam } 4913193240Ssam } 4914193240Ssam if (bootverbose || mwl_rxdesc != MWL_RXDESC) 4915287197Sglebius device_printf(sc->sc_dev, "using %u rx descriptors\n", mwl_rxdesc); 4916193240Ssam if (bootverbose || mwl_rxbuf != MWL_RXBUF) 4917287197Sglebius device_printf(sc->sc_dev, "using %u rx buffers\n", mwl_rxbuf); 4918193240Ssam if (bootverbose || mwl_txbuf != MWL_TXBUF) 4919287197Sglebius device_printf(sc->sc_dev, "using %u tx buffers\n", mwl_txbuf); 4920193240Ssam if (bootverbose && mwl_hal_ismbsscapable(sc->sc_mh)) 4921287197Sglebius device_printf(sc->sc_dev, "multi-bss support\n"); 4922193240Ssam#ifdef MWL_TX_NODROP 4923193240Ssam if (bootverbose) 4924287197Sglebius device_printf(sc->sc_dev, "no tx drop\n"); 4925193240Ssam#endif 4926193240Ssam} 4927