1193240Ssam/*- 2193240Ssam * Copyright (c) 2007-2009 Sam Leffler, Errno Consulting 3193240Ssam * Copyright (c) 2007-2008 Marvell Semiconductor, Inc. 4193240Ssam * All rights reserved. 5193240Ssam * 6193240Ssam * Redistribution and use in source and binary forms, with or without 7193240Ssam * modification, are permitted provided that the following conditions 8193240Ssam * are met: 9193240Ssam * 1. Redistributions of source code must retain the above copyright 10193240Ssam * notice, this list of conditions and the following disclaimer, 11193240Ssam * without modification. 12193240Ssam * 2. Redistributions in binary form must reproduce at minimum a disclaimer 13193240Ssam * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 14193240Ssam * redistribution must be conditioned upon including a substantially 15193240Ssam * similar Disclaimer requirement for further binary redistribution. 16193240Ssam * 17193240Ssam * NO WARRANTY 18193240Ssam * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19193240Ssam * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20193240Ssam * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 21193240Ssam * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 22193240Ssam * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 23193240Ssam * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24193240Ssam * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25193240Ssam * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 26193240Ssam * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27193240Ssam * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 28193240Ssam * THE POSSIBILITY OF SUCH DAMAGES. 29193240Ssam */ 30193240Ssam 31193240Ssam#include <sys/cdefs.h> 32193240Ssam__FBSDID("$FreeBSD: stable/11/sys/dev/mwl/if_mwl.c 344969 2019-03-09 12:54:10Z avos $"); 33193240Ssam 34193240Ssam/* 35193240Ssam * Driver for the Marvell 88W8363 Wireless LAN controller. 36193240Ssam */ 37193240Ssam 38193240Ssam#include "opt_inet.h" 39193240Ssam#include "opt_mwl.h" 40234367Sadrian#include "opt_wlan.h" 41193240Ssam 42193240Ssam#include <sys/param.h> 43193240Ssam#include <sys/systm.h> 44193240Ssam#include <sys/sysctl.h> 45193240Ssam#include <sys/mbuf.h> 46193240Ssam#include <sys/malloc.h> 47193240Ssam#include <sys/lock.h> 48193240Ssam#include <sys/mutex.h> 49193240Ssam#include <sys/kernel.h> 50193240Ssam#include <sys/socket.h> 51193240Ssam#include <sys/sockio.h> 52193240Ssam#include <sys/errno.h> 53193240Ssam#include <sys/callout.h> 54193240Ssam#include <sys/bus.h> 55193240Ssam#include <sys/endian.h> 56193240Ssam#include <sys/kthread.h> 57193240Ssam#include <sys/taskqueue.h> 58193240Ssam 59193240Ssam#include <machine/bus.h> 60193240Ssam 61193240Ssam#include <net/if.h> 62257176Sglebius#include <net/if_var.h> 63193240Ssam#include <net/if_dl.h> 64193240Ssam#include <net/if_media.h> 65193240Ssam#include <net/if_types.h> 66193240Ssam#include <net/if_arp.h> 67193240Ssam#include <net/ethernet.h> 68193240Ssam#include <net/if_llc.h> 69193240Ssam 70193240Ssam#include <net/bpf.h> 71193240Ssam 72193240Ssam#include <net80211/ieee80211_var.h> 73288087Sadrian#include <net80211/ieee80211_input.h> 74193240Ssam#include <net80211/ieee80211_regdomain.h> 75193240Ssam 76193240Ssam#ifdef INET 77193240Ssam#include <netinet/in.h> 78193240Ssam#include <netinet/if_ether.h> 79193240Ssam#endif /* INET */ 80193240Ssam 81193240Ssam#include <dev/mwl/if_mwlvar.h> 82193240Ssam#include <dev/mwl/mwldiag.h> 83193240Ssam 84193240Ssam/* idiomatic shorthands: MS = mask+shift, SM = shift+mask */ 85193240Ssam#define MS(v,x) (((v) & x) >> x##_S) 86193240Ssam#define SM(v,x) (((v) << x##_S) & x) 87193240Ssam 88193240Ssamstatic struct ieee80211vap *mwl_vap_create(struct ieee80211com *, 89228621Sbschmidt const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 90228621Sbschmidt const uint8_t [IEEE80211_ADDR_LEN], 91228621Sbschmidt const uint8_t [IEEE80211_ADDR_LEN]); 92193240Ssamstatic void mwl_vap_delete(struct ieee80211vap *); 93193240Ssamstatic int mwl_setupdma(struct mwl_softc *); 94193240Ssamstatic int mwl_hal_reset(struct mwl_softc *sc); 95287197Sglebiusstatic int mwl_init(struct mwl_softc *); 96287197Sglebiusstatic void mwl_parent(struct ieee80211com *); 97193240Ssamstatic int mwl_reset(struct ieee80211vap *, u_long); 98287197Sglebiusstatic void mwl_stop(struct mwl_softc *); 99287197Sglebiusstatic void mwl_start(struct mwl_softc *); 100287197Sglebiusstatic int mwl_transmit(struct ieee80211com *, struct mbuf *); 101193240Ssamstatic int mwl_raw_xmit(struct ieee80211_node *, struct mbuf *, 102193240Ssam const struct ieee80211_bpf_params *); 103193240Ssamstatic int mwl_media_change(struct ifnet *); 104199559Sjhbstatic void mwl_watchdog(void *); 105287197Sglebiusstatic int mwl_ioctl(struct ieee80211com *, u_long, void *); 106193240Ssamstatic void mwl_radar_proc(void *, int); 107193240Ssamstatic void mwl_chanswitch_proc(void *, int); 108193240Ssamstatic void mwl_bawatchdog_proc(void *, int); 109193240Ssamstatic int mwl_key_alloc(struct ieee80211vap *, 110193240Ssam struct ieee80211_key *, 111193240Ssam ieee80211_keyix *, ieee80211_keyix *); 112193240Ssamstatic int mwl_key_delete(struct ieee80211vap *, 113193240Ssam const struct ieee80211_key *); 114288635Sadrianstatic int mwl_key_set(struct ieee80211vap *, 115288635Sadrian const struct ieee80211_key *); 116288635Sadrianstatic int _mwl_key_set(struct ieee80211vap *, 117288635Sadrian const struct ieee80211_key *, 118193240Ssam const uint8_t mac[IEEE80211_ADDR_LEN]); 119193240Ssamstatic int mwl_mode_init(struct mwl_softc *); 120283540Sglebiusstatic void mwl_update_mcast(struct ieee80211com *); 121283540Sglebiusstatic void mwl_update_promisc(struct ieee80211com *); 122283540Sglebiusstatic void mwl_updateslot(struct ieee80211com *); 123193240Ssamstatic int mwl_beacon_setup(struct ieee80211vap *); 124193240Ssamstatic void mwl_beacon_update(struct ieee80211vap *, int); 125193240Ssam#ifdef MWL_HOST_PS_SUPPORT 126193240Ssamstatic void mwl_update_ps(struct ieee80211vap *, int); 127193240Ssamstatic int mwl_set_tim(struct ieee80211_node *, int); 128193240Ssam#endif 129193240Ssamstatic int mwl_dma_setup(struct mwl_softc *); 130193240Ssamstatic void mwl_dma_cleanup(struct mwl_softc *); 131193240Ssamstatic struct ieee80211_node *mwl_node_alloc(struct ieee80211vap *, 132193240Ssam const uint8_t [IEEE80211_ADDR_LEN]); 133193240Ssamstatic void mwl_node_cleanup(struct ieee80211_node *); 134193240Ssamstatic void mwl_node_drain(struct ieee80211_node *); 135193240Ssamstatic void mwl_node_getsignal(const struct ieee80211_node *, 136193240Ssam int8_t *, int8_t *); 137193240Ssamstatic void mwl_node_getmimoinfo(const struct ieee80211_node *, 138193240Ssam struct ieee80211_mimo_info *); 139193240Ssamstatic int mwl_rxbuf_init(struct mwl_softc *, struct mwl_rxbuf *); 140193240Ssamstatic void mwl_rx_proc(void *, int); 141193240Ssamstatic void mwl_txq_init(struct mwl_softc *sc, struct mwl_txq *, int); 142193240Ssamstatic int mwl_tx_setup(struct mwl_softc *, int, int); 143193240Ssamstatic int mwl_wme_update(struct ieee80211com *); 144193240Ssamstatic void mwl_tx_cleanupq(struct mwl_softc *, struct mwl_txq *); 145193240Ssamstatic void mwl_tx_cleanup(struct mwl_softc *); 146193240Ssamstatic uint16_t mwl_calcformat(uint8_t rate, const struct ieee80211_node *); 147193240Ssamstatic int mwl_tx_start(struct mwl_softc *, struct ieee80211_node *, 148193240Ssam struct mwl_txbuf *, struct mbuf *); 149193240Ssamstatic void mwl_tx_proc(void *, int); 150193240Ssamstatic int mwl_chan_set(struct mwl_softc *, struct ieee80211_channel *); 151193240Ssamstatic void mwl_draintxq(struct mwl_softc *); 152193240Ssamstatic void mwl_cleartxq(struct mwl_softc *, struct ieee80211vap *); 153195377Ssamstatic int mwl_recv_action(struct ieee80211_node *, 154195377Ssam const struct ieee80211_frame *, 155193240Ssam const uint8_t *, const uint8_t *); 156193240Ssamstatic int mwl_addba_request(struct ieee80211_node *, 157193240Ssam struct ieee80211_tx_ampdu *, int dialogtoken, 158193240Ssam int baparamset, int batimeout); 159193240Ssamstatic int mwl_addba_response(struct ieee80211_node *, 160193240Ssam struct ieee80211_tx_ampdu *, int status, 161193240Ssam int baparamset, int batimeout); 162193240Ssamstatic void mwl_addba_stop(struct ieee80211_node *, 163193240Ssam struct ieee80211_tx_ampdu *); 164193240Ssamstatic int mwl_startrecv(struct mwl_softc *); 165193240Ssamstatic MWL_HAL_APMODE mwl_getapmode(const struct ieee80211vap *, 166193240Ssam struct ieee80211_channel *); 167193240Ssamstatic int mwl_setapmode(struct ieee80211vap *, struct ieee80211_channel*); 168193240Ssamstatic void mwl_scan_start(struct ieee80211com *); 169193240Ssamstatic void mwl_scan_end(struct ieee80211com *); 170193240Ssamstatic void mwl_set_channel(struct ieee80211com *); 171193240Ssamstatic int mwl_peerstadb(struct ieee80211_node *, 172193240Ssam int aid, int staid, MWL_HAL_PEERINFO *pi); 173193240Ssamstatic int mwl_localstadb(struct ieee80211vap *); 174193240Ssamstatic int mwl_newstate(struct ieee80211vap *, enum ieee80211_state, int); 175193240Ssamstatic int allocstaid(struct mwl_softc *sc, int aid); 176193240Ssamstatic void delstaid(struct mwl_softc *sc, int staid); 177193240Ssamstatic void mwl_newassoc(struct ieee80211_node *, int); 178193240Ssamstatic void mwl_agestations(void *); 179193240Ssamstatic int mwl_setregdomain(struct ieee80211com *, 180193240Ssam struct ieee80211_regdomain *, int, 181193240Ssam struct ieee80211_channel []); 182193240Ssamstatic void mwl_getradiocaps(struct ieee80211com *, int, int *, 183193240Ssam struct ieee80211_channel []); 184193240Ssamstatic int mwl_getchannels(struct mwl_softc *); 185193240Ssam 186193240Ssamstatic void mwl_sysctlattach(struct mwl_softc *); 187193240Ssamstatic void mwl_announce(struct mwl_softc *); 188193240Ssam 189193240SsamSYSCTL_NODE(_hw, OID_AUTO, mwl, CTLFLAG_RD, 0, "Marvell driver parameters"); 190193240Ssam 191193240Ssamstatic int mwl_rxdesc = MWL_RXDESC; /* # rx desc's to allocate */ 192193240SsamSYSCTL_INT(_hw_mwl, OID_AUTO, rxdesc, CTLFLAG_RW, &mwl_rxdesc, 193193240Ssam 0, "rx descriptors allocated"); 194193240Ssamstatic int mwl_rxbuf = MWL_RXBUF; /* # rx buffers to allocate */ 195267992ShselaskySYSCTL_INT(_hw_mwl, OID_AUTO, rxbuf, CTLFLAG_RWTUN, &mwl_rxbuf, 196193240Ssam 0, "rx buffers allocated"); 197193240Ssamstatic int mwl_txbuf = MWL_TXBUF; /* # tx buffers to allocate */ 198267992ShselaskySYSCTL_INT(_hw_mwl, OID_AUTO, txbuf, CTLFLAG_RWTUN, &mwl_txbuf, 199193240Ssam 0, "tx buffers allocated"); 200193240Ssamstatic int mwl_txcoalesce = 8; /* # tx packets to q before poking f/w*/ 201267992ShselaskySYSCTL_INT(_hw_mwl, OID_AUTO, txcoalesce, CTLFLAG_RWTUN, &mwl_txcoalesce, 202193240Ssam 0, "tx buffers to send at once"); 203193240Ssamstatic int mwl_rxquota = MWL_RXBUF; /* # max buffers to process */ 204267992ShselaskySYSCTL_INT(_hw_mwl, OID_AUTO, rxquota, CTLFLAG_RWTUN, &mwl_rxquota, 205193240Ssam 0, "max rx buffers to process per interrupt"); 206193240Ssamstatic int mwl_rxdmalow = 3; /* # min buffers for wakeup */ 207267992ShselaskySYSCTL_INT(_hw_mwl, OID_AUTO, rxdmalow, CTLFLAG_RWTUN, &mwl_rxdmalow, 208193240Ssam 0, "min free rx buffers before restarting traffic"); 209193240Ssam 210193240Ssam#ifdef MWL_DEBUG 211193240Ssamstatic int mwl_debug = 0; 212267992ShselaskySYSCTL_INT(_hw_mwl, OID_AUTO, debug, CTLFLAG_RWTUN, &mwl_debug, 213193240Ssam 0, "control debugging printfs"); 214193240Ssamenum { 215193240Ssam MWL_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 216193240Ssam MWL_DEBUG_XMIT_DESC = 0x00000002, /* xmit descriptors */ 217193240Ssam MWL_DEBUG_RECV = 0x00000004, /* basic recv operation */ 218193240Ssam MWL_DEBUG_RECV_DESC = 0x00000008, /* recv descriptors */ 219193240Ssam MWL_DEBUG_RESET = 0x00000010, /* reset processing */ 220193240Ssam MWL_DEBUG_BEACON = 0x00000020, /* beacon handling */ 221193240Ssam MWL_DEBUG_INTR = 0x00000040, /* ISR */ 222193240Ssam MWL_DEBUG_TX_PROC = 0x00000080, /* tx ISR proc */ 223193240Ssam MWL_DEBUG_RX_PROC = 0x00000100, /* rx ISR proc */ 224193240Ssam MWL_DEBUG_KEYCACHE = 0x00000200, /* key cache management */ 225193240Ssam MWL_DEBUG_STATE = 0x00000400, /* 802.11 state transitions */ 226193240Ssam MWL_DEBUG_NODE = 0x00000800, /* node management */ 227193240Ssam MWL_DEBUG_RECV_ALL = 0x00001000, /* trace all frames (beacons) */ 228193240Ssam MWL_DEBUG_TSO = 0x00002000, /* TSO processing */ 229193240Ssam MWL_DEBUG_AMPDU = 0x00004000, /* BA stream handling */ 230193240Ssam MWL_DEBUG_ANY = 0xffffffff 231193240Ssam}; 232193240Ssam#define IS_BEACON(wh) \ 233193240Ssam ((wh->i_fc[0] & (IEEE80211_FC0_TYPE_MASK|IEEE80211_FC0_SUBTYPE_MASK)) == \ 234193240Ssam (IEEE80211_FC0_TYPE_MGT|IEEE80211_FC0_SUBTYPE_BEACON)) 235193240Ssam#define IFF_DUMPPKTS_RECV(sc, wh) \ 236287197Sglebius ((sc->sc_debug & MWL_DEBUG_RECV) && \ 237287197Sglebius ((sc->sc_debug & MWL_DEBUG_RECV_ALL) || !IS_BEACON(wh))) 238193240Ssam#define IFF_DUMPPKTS_XMIT(sc) \ 239287197Sglebius (sc->sc_debug & MWL_DEBUG_XMIT) 240287197Sglebius 241193240Ssam#define DPRINTF(sc, m, fmt, ...) do { \ 242193240Ssam if (sc->sc_debug & (m)) \ 243193240Ssam printf(fmt, __VA_ARGS__); \ 244193240Ssam} while (0) 245193240Ssam#define KEYPRINTF(sc, hk, mac) do { \ 246193240Ssam if (sc->sc_debug & MWL_DEBUG_KEYCACHE) \ 247193240Ssam mwl_keyprint(sc, __func__, hk, mac); \ 248193240Ssam} while (0) 249193240Ssamstatic void mwl_printrxbuf(const struct mwl_rxbuf *bf, u_int ix); 250193240Ssamstatic void mwl_printtxbuf(const struct mwl_txbuf *bf, u_int qnum, u_int ix); 251193240Ssam#else 252287197Sglebius#define IFF_DUMPPKTS_RECV(sc, wh) 0 253287197Sglebius#define IFF_DUMPPKTS_XMIT(sc) 0 254287197Sglebius#define DPRINTF(sc, m, fmt, ...) do { (void )sc; } while (0) 255287197Sglebius#define KEYPRINTF(sc, k, mac) do { (void )sc; } while (0) 256193240Ssam#endif 257193240Ssam 258227293Sedstatic MALLOC_DEFINE(M_MWLDEV, "mwldev", "mwl driver dma buffers"); 259193240Ssam 260193240Ssam/* 261193240Ssam * Each packet has fixed front matter: a 2-byte length 262193240Ssam * of the payload, followed by a 4-address 802.11 header 263193240Ssam * (regardless of the actual header and always w/o any 264193240Ssam * QoS header). The payload then follows. 265193240Ssam */ 266193240Ssamstruct mwltxrec { 267193240Ssam uint16_t fwlen; 268193240Ssam struct ieee80211_frame_addr4 wh; 269193240Ssam} __packed; 270193240Ssam 271193240Ssam/* 272193240Ssam * Read/Write shorthands for accesses to BAR 0. Note 273193240Ssam * that all BAR 1 operations are done in the "hal" and 274193240Ssam * there should be no reference to them here. 275193240Ssam */ 276259869Sdim#ifdef MWL_DEBUG 277193240Ssamstatic __inline uint32_t 278193240SsamRD4(struct mwl_softc *sc, bus_size_t off) 279193240Ssam{ 280193240Ssam return bus_space_read_4(sc->sc_io0t, sc->sc_io0h, off); 281193240Ssam} 282259869Sdim#endif 283193240Ssam 284193240Ssamstatic __inline void 285193240SsamWR4(struct mwl_softc *sc, bus_size_t off, uint32_t val) 286193240Ssam{ 287193240Ssam bus_space_write_4(sc->sc_io0t, sc->sc_io0h, off, val); 288193240Ssam} 289193240Ssam 290193240Ssamint 291193240Ssammwl_attach(uint16_t devid, struct mwl_softc *sc) 292193240Ssam{ 293287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 294193240Ssam struct mwl_hal *mh; 295193240Ssam int error = 0; 296193240Ssam 297193240Ssam DPRINTF(sc, MWL_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid); 298193240Ssam 299234368Sadrian /* 300234368Sadrian * Setup the RX free list lock early, so it can be consistently 301234368Sadrian * removed. 302234368Sadrian */ 303234368Sadrian MWL_RXFREE_INIT(sc); 304234368Sadrian 305193240Ssam mh = mwl_hal_attach(sc->sc_dev, devid, 306193240Ssam sc->sc_io1h, sc->sc_io1t, sc->sc_dmat); 307193240Ssam if (mh == NULL) { 308287197Sglebius device_printf(sc->sc_dev, "unable to attach HAL\n"); 309193240Ssam error = EIO; 310193240Ssam goto bad; 311193240Ssam } 312193240Ssam sc->sc_mh = mh; 313193240Ssam /* 314193240Ssam * Load firmware so we can get setup. We arbitrarily 315193240Ssam * pick station firmware; we'll re-load firmware as 316193240Ssam * needed so setting up the wrong mode isn't a big deal. 317193240Ssam */ 318193240Ssam if (mwl_hal_fwload(mh, NULL) != 0) { 319287197Sglebius device_printf(sc->sc_dev, "unable to setup builtin firmware\n"); 320193240Ssam error = EIO; 321193240Ssam goto bad1; 322193240Ssam } 323193240Ssam if (mwl_hal_gethwspecs(mh, &sc->sc_hwspecs) != 0) { 324287197Sglebius device_printf(sc->sc_dev, "unable to fetch h/w specs\n"); 325193240Ssam error = EIO; 326193240Ssam goto bad1; 327193240Ssam } 328193240Ssam error = mwl_getchannels(sc); 329193240Ssam if (error != 0) 330193240Ssam goto bad1; 331193240Ssam 332193240Ssam sc->sc_txantenna = 0; /* h/w default */ 333193240Ssam sc->sc_rxantenna = 0; /* h/w default */ 334193240Ssam sc->sc_invalid = 0; /* ready to go, enable int handling */ 335193240Ssam sc->sc_ageinterval = MWL_AGEINTERVAL; 336193240Ssam 337193240Ssam /* 338193240Ssam * Allocate tx+rx descriptors and populate the lists. 339193240Ssam * We immediately push the information to the firmware 340193240Ssam * as otherwise it gets upset. 341193240Ssam */ 342193240Ssam error = mwl_dma_setup(sc); 343193240Ssam if (error != 0) { 344287197Sglebius device_printf(sc->sc_dev, "failed to setup descriptors: %d\n", 345287197Sglebius error); 346193240Ssam goto bad1; 347193240Ssam } 348193240Ssam error = mwl_setupdma(sc); /* push to firmware */ 349193240Ssam if (error != 0) /* NB: mwl_setupdma prints msg */ 350193240Ssam goto bad1; 351193240Ssam 352283291Sjkim callout_init(&sc->sc_timer, 1); 353199559Sjhb callout_init_mtx(&sc->sc_watchdog, &sc->sc_mtx, 0); 354287197Sglebius mbufq_init(&sc->sc_snd, ifqmaxlen); 355193240Ssam 356193240Ssam sc->sc_tq = taskqueue_create("mwl_taskq", M_NOWAIT, 357193240Ssam taskqueue_thread_enqueue, &sc->sc_tq); 358193240Ssam taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, 359287197Sglebius "%s taskq", device_get_nameunit(sc->sc_dev)); 360193240Ssam 361193240Ssam TASK_INIT(&sc->sc_rxtask, 0, mwl_rx_proc, sc); 362193240Ssam TASK_INIT(&sc->sc_radartask, 0, mwl_radar_proc, sc); 363193240Ssam TASK_INIT(&sc->sc_chanswitchtask, 0, mwl_chanswitch_proc, sc); 364193240Ssam TASK_INIT(&sc->sc_bawatchdogtask, 0, mwl_bawatchdog_proc, sc); 365193240Ssam 366193240Ssam /* NB: insure BK queue is the lowest priority h/w queue */ 367193240Ssam if (!mwl_tx_setup(sc, WME_AC_BK, MWL_WME_AC_BK)) { 368287197Sglebius device_printf(sc->sc_dev, 369287197Sglebius "unable to setup xmit queue for %s traffic!\n", 370287197Sglebius ieee80211_wme_acnames[WME_AC_BK]); 371193240Ssam error = EIO; 372193240Ssam goto bad2; 373193240Ssam } 374193240Ssam if (!mwl_tx_setup(sc, WME_AC_BE, MWL_WME_AC_BE) || 375193240Ssam !mwl_tx_setup(sc, WME_AC_VI, MWL_WME_AC_VI) || 376193240Ssam !mwl_tx_setup(sc, WME_AC_VO, MWL_WME_AC_VO)) { 377193240Ssam /* 378193240Ssam * Not enough hardware tx queues to properly do WME; 379193240Ssam * just punt and assign them all to the same h/w queue. 380193240Ssam * We could do a better job of this if, for example, 381193240Ssam * we allocate queues when we switch from station to 382193240Ssam * AP mode. 383193240Ssam */ 384193240Ssam if (sc->sc_ac2q[WME_AC_VI] != NULL) 385193240Ssam mwl_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]); 386193240Ssam if (sc->sc_ac2q[WME_AC_BE] != NULL) 387193240Ssam mwl_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]); 388193240Ssam sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK]; 389193240Ssam sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK]; 390193240Ssam sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK]; 391193240Ssam } 392193240Ssam TASK_INIT(&sc->sc_txtask, 0, mwl_tx_proc, sc); 393193240Ssam 394283537Sglebius ic->ic_softc = sc; 395283527Sglebius ic->ic_name = device_get_nameunit(sc->sc_dev); 396193240Ssam /* XXX not right but it's not used anywhere important */ 397193240Ssam ic->ic_phytype = IEEE80211_T_OFDM; 398193240Ssam ic->ic_opmode = IEEE80211_M_STA; 399193240Ssam ic->ic_caps = 400193240Ssam IEEE80211_C_STA /* station mode supported */ 401193240Ssam | IEEE80211_C_HOSTAP /* hostap mode */ 402193240Ssam | IEEE80211_C_MONITOR /* monitor mode */ 403193240Ssam#if 0 404193240Ssam | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 405193240Ssam | IEEE80211_C_AHDEMO /* adhoc demo mode */ 406193240Ssam#endif 407195618Srpaulo | IEEE80211_C_MBSS /* mesh point link mode */ 408193240Ssam | IEEE80211_C_WDS /* WDS supported */ 409193240Ssam | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 410193240Ssam | IEEE80211_C_SHSLOT /* short slot time supported */ 411193240Ssam | IEEE80211_C_WME /* WME/WMM supported */ 412193240Ssam | IEEE80211_C_BURST /* xmit bursting supported */ 413193240Ssam | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 414193240Ssam | IEEE80211_C_BGSCAN /* capable of bg scanning */ 415193240Ssam | IEEE80211_C_TXFRAG /* handle tx frags */ 416193240Ssam | IEEE80211_C_TXPMGT /* capable of txpow mgt */ 417193240Ssam | IEEE80211_C_DFS /* DFS supported */ 418193240Ssam ; 419193240Ssam 420193240Ssam ic->ic_htcaps = 421193240Ssam IEEE80211_HTCAP_SMPS_ENA /* SM PS mode enabled */ 422193240Ssam | IEEE80211_HTCAP_CHWIDTH40 /* 40MHz channel width */ 423193240Ssam | IEEE80211_HTCAP_SHORTGI20 /* short GI in 20MHz */ 424193240Ssam | IEEE80211_HTCAP_SHORTGI40 /* short GI in 40MHz */ 425193240Ssam | IEEE80211_HTCAP_RXSTBC_2STREAM/* 1-2 spatial streams */ 426193240Ssam#if MWL_AGGR_SIZE == 7935 427193240Ssam | IEEE80211_HTCAP_MAXAMSDU_7935 /* max A-MSDU length */ 428193240Ssam#else 429193240Ssam | IEEE80211_HTCAP_MAXAMSDU_3839 /* max A-MSDU length */ 430193240Ssam#endif 431193240Ssam#if 0 432193240Ssam | IEEE80211_HTCAP_PSMP /* PSMP supported */ 433193240Ssam | IEEE80211_HTCAP_40INTOLERANT /* 40MHz intolerant */ 434193240Ssam#endif 435193240Ssam /* s/w capabilities */ 436193240Ssam | IEEE80211_HTC_HT /* HT operation */ 437193240Ssam | IEEE80211_HTC_AMPDU /* tx A-MPDU */ 438193240Ssam | IEEE80211_HTC_AMSDU /* tx A-MSDU */ 439193240Ssam | IEEE80211_HTC_SMPS /* SMPS available */ 440193240Ssam ; 441193240Ssam 442193240Ssam /* 443193240Ssam * Mark h/w crypto support. 444193240Ssam * XXX no way to query h/w support. 445193240Ssam */ 446193240Ssam ic->ic_cryptocaps |= IEEE80211_CRYPTO_WEP 447193240Ssam | IEEE80211_CRYPTO_AES_CCM 448193240Ssam | IEEE80211_CRYPTO_TKIP 449193240Ssam | IEEE80211_CRYPTO_TKIPMIC 450193240Ssam ; 451193240Ssam /* 452193240Ssam * Transmit requires space in the packet for a special 453193240Ssam * format transmit record and optional padding between 454193240Ssam * this record and the payload. Ask the net80211 layer 455193240Ssam * to arrange this when encapsulating packets so we can 456193240Ssam * add it efficiently. 457193240Ssam */ 458193240Ssam ic->ic_headroom = sizeof(struct mwltxrec) - 459193240Ssam sizeof(struct ieee80211_frame); 460193240Ssam 461287197Sglebius IEEE80211_ADDR_COPY(ic->ic_macaddr, sc->sc_hwspecs.macAddr); 462287197Sglebius 463193240Ssam /* call MI attach routine. */ 464287197Sglebius ieee80211_ifattach(ic); 465193240Ssam ic->ic_setregdomain = mwl_setregdomain; 466193240Ssam ic->ic_getradiocaps = mwl_getradiocaps; 467193240Ssam /* override default methods */ 468193240Ssam ic->ic_raw_xmit = mwl_raw_xmit; 469193240Ssam ic->ic_newassoc = mwl_newassoc; 470193240Ssam ic->ic_updateslot = mwl_updateslot; 471193240Ssam ic->ic_update_mcast = mwl_update_mcast; 472193240Ssam ic->ic_update_promisc = mwl_update_promisc; 473193240Ssam ic->ic_wme.wme_update = mwl_wme_update; 474287197Sglebius ic->ic_transmit = mwl_transmit; 475287197Sglebius ic->ic_ioctl = mwl_ioctl; 476287197Sglebius ic->ic_parent = mwl_parent; 477193240Ssam 478193240Ssam ic->ic_node_alloc = mwl_node_alloc; 479193240Ssam sc->sc_node_cleanup = ic->ic_node_cleanup; 480193240Ssam ic->ic_node_cleanup = mwl_node_cleanup; 481193240Ssam sc->sc_node_drain = ic->ic_node_drain; 482193240Ssam ic->ic_node_drain = mwl_node_drain; 483193240Ssam ic->ic_node_getsignal = mwl_node_getsignal; 484193240Ssam ic->ic_node_getmimoinfo = mwl_node_getmimoinfo; 485193240Ssam 486193240Ssam ic->ic_scan_start = mwl_scan_start; 487193240Ssam ic->ic_scan_end = mwl_scan_end; 488193240Ssam ic->ic_set_channel = mwl_set_channel; 489193240Ssam 490193240Ssam sc->sc_recv_action = ic->ic_recv_action; 491193240Ssam ic->ic_recv_action = mwl_recv_action; 492193240Ssam sc->sc_addba_request = ic->ic_addba_request; 493193240Ssam ic->ic_addba_request = mwl_addba_request; 494193240Ssam sc->sc_addba_response = ic->ic_addba_response; 495193240Ssam ic->ic_addba_response = mwl_addba_response; 496193240Ssam sc->sc_addba_stop = ic->ic_addba_stop; 497193240Ssam ic->ic_addba_stop = mwl_addba_stop; 498193240Ssam 499193240Ssam ic->ic_vap_create = mwl_vap_create; 500193240Ssam ic->ic_vap_delete = mwl_vap_delete; 501193240Ssam 502193240Ssam ieee80211_radiotap_attach(ic, 503193240Ssam &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th), 504193240Ssam MWL_TX_RADIOTAP_PRESENT, 505193240Ssam &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th), 506193240Ssam MWL_RX_RADIOTAP_PRESENT); 507193240Ssam /* 508193240Ssam * Setup dynamic sysctl's now that country code and 509193240Ssam * regdomain are available from the hal. 510193240Ssam */ 511193240Ssam mwl_sysctlattach(sc); 512193240Ssam 513193240Ssam if (bootverbose) 514193240Ssam ieee80211_announce(ic); 515193240Ssam mwl_announce(sc); 516193240Ssam return 0; 517193240Ssambad2: 518193240Ssam mwl_dma_cleanup(sc); 519193240Ssambad1: 520193240Ssam mwl_hal_detach(mh); 521193240Ssambad: 522234368Sadrian MWL_RXFREE_DESTROY(sc); 523193240Ssam sc->sc_invalid = 1; 524193240Ssam return error; 525193240Ssam} 526193240Ssam 527193240Ssamint 528193240Ssammwl_detach(struct mwl_softc *sc) 529193240Ssam{ 530287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 531193240Ssam 532287197Sglebius MWL_LOCK(sc); 533287197Sglebius mwl_stop(sc); 534287197Sglebius MWL_UNLOCK(sc); 535193240Ssam /* 536193240Ssam * NB: the order of these is important: 537193240Ssam * o call the 802.11 layer before detaching the hal to 538193240Ssam * insure callbacks into the driver to delete global 539193240Ssam * key cache entries can be handled 540193240Ssam * o reclaim the tx queue data structures after calling 541193240Ssam * the 802.11 layer as we'll get called back to reclaim 542193240Ssam * node state and potentially want to use them 543193240Ssam * o to cleanup the tx queues the hal is called, so detach 544193240Ssam * it last 545193240Ssam * Other than that, it's straightforward... 546193240Ssam */ 547193240Ssam ieee80211_ifdetach(ic); 548199559Sjhb callout_drain(&sc->sc_watchdog); 549193240Ssam mwl_dma_cleanup(sc); 550234368Sadrian MWL_RXFREE_DESTROY(sc); 551193240Ssam mwl_tx_cleanup(sc); 552193240Ssam mwl_hal_detach(sc->sc_mh); 553287197Sglebius mbufq_drain(&sc->sc_snd); 554193240Ssam 555193240Ssam return 0; 556193240Ssam} 557193240Ssam 558193240Ssam/* 559193240Ssam * MAC address handling for multiple BSS on the same radio. 560193240Ssam * The first vap uses the MAC address from the EEPROM. For 561193240Ssam * subsequent vap's we set the U/L bit (bit 1) in the MAC 562193240Ssam * address and use the next six bits as an index. 563193240Ssam */ 564193240Ssamstatic void 565193240Ssamassign_address(struct mwl_softc *sc, uint8_t mac[IEEE80211_ADDR_LEN], int clone) 566193240Ssam{ 567193240Ssam int i; 568193240Ssam 569193240Ssam if (clone && mwl_hal_ismbsscapable(sc->sc_mh)) { 570193240Ssam /* NB: we only do this if h/w supports multiple bssid */ 571193240Ssam for (i = 0; i < 32; i++) 572193240Ssam if ((sc->sc_bssidmask & (1<<i)) == 0) 573193240Ssam break; 574193240Ssam if (i != 0) 575193240Ssam mac[0] |= (i << 2)|0x2; 576193240Ssam } else 577193240Ssam i = 0; 578193240Ssam sc->sc_bssidmask |= 1<<i; 579193240Ssam if (i == 0) 580193240Ssam sc->sc_nbssid0++; 581193240Ssam} 582193240Ssam 583193240Ssamstatic void 584287197Sglebiusreclaim_address(struct mwl_softc *sc, const uint8_t mac[IEEE80211_ADDR_LEN]) 585193240Ssam{ 586193240Ssam int i = mac[0] >> 2; 587193240Ssam if (i != 0 || --sc->sc_nbssid0 == 0) 588193240Ssam sc->sc_bssidmask &= ~(1<<i); 589193240Ssam} 590193240Ssam 591193240Ssamstatic struct ieee80211vap * 592228621Sbschmidtmwl_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 593228621Sbschmidt enum ieee80211_opmode opmode, int flags, 594228621Sbschmidt const uint8_t bssid[IEEE80211_ADDR_LEN], 595228621Sbschmidt const uint8_t mac0[IEEE80211_ADDR_LEN]) 596193240Ssam{ 597287197Sglebius struct mwl_softc *sc = ic->ic_softc; 598193240Ssam struct mwl_hal *mh = sc->sc_mh; 599193240Ssam struct ieee80211vap *vap, *apvap; 600193240Ssam struct mwl_hal_vap *hvap; 601193240Ssam struct mwl_vap *mvp; 602193240Ssam uint8_t mac[IEEE80211_ADDR_LEN]; 603193240Ssam 604193240Ssam IEEE80211_ADDR_COPY(mac, mac0); 605193240Ssam switch (opmode) { 606193240Ssam case IEEE80211_M_HOSTAP: 607195618Srpaulo case IEEE80211_M_MBSS: 608193240Ssam if ((flags & IEEE80211_CLONE_MACADDR) == 0) 609193240Ssam assign_address(sc, mac, flags & IEEE80211_CLONE_BSSID); 610193240Ssam hvap = mwl_hal_newvap(mh, MWL_HAL_AP, mac); 611193240Ssam if (hvap == NULL) { 612193240Ssam if ((flags & IEEE80211_CLONE_MACADDR) == 0) 613193240Ssam reclaim_address(sc, mac); 614193240Ssam return NULL; 615193240Ssam } 616193240Ssam break; 617193240Ssam case IEEE80211_M_STA: 618193240Ssam if ((flags & IEEE80211_CLONE_MACADDR) == 0) 619193240Ssam assign_address(sc, mac, flags & IEEE80211_CLONE_BSSID); 620193240Ssam hvap = mwl_hal_newvap(mh, MWL_HAL_STA, mac); 621193240Ssam if (hvap == NULL) { 622193240Ssam if ((flags & IEEE80211_CLONE_MACADDR) == 0) 623193240Ssam reclaim_address(sc, mac); 624193240Ssam return NULL; 625193240Ssam } 626193240Ssam /* no h/w beacon miss support; always use s/w */ 627193240Ssam flags |= IEEE80211_CLONE_NOBEACONS; 628193240Ssam break; 629193240Ssam case IEEE80211_M_WDS: 630193240Ssam hvap = NULL; /* NB: we use associated AP vap */ 631193240Ssam if (sc->sc_napvaps == 0) 632193240Ssam return NULL; /* no existing AP vap */ 633193240Ssam break; 634193240Ssam case IEEE80211_M_MONITOR: 635193240Ssam hvap = NULL; 636193240Ssam break; 637193240Ssam case IEEE80211_M_IBSS: 638193240Ssam case IEEE80211_M_AHDEMO: 639193240Ssam default: 640193240Ssam return NULL; 641193240Ssam } 642193240Ssam 643287197Sglebius mvp = malloc(sizeof(struct mwl_vap), M_80211_VAP, M_WAITOK | M_ZERO); 644193240Ssam mvp->mv_hvap = hvap; 645193240Ssam if (opmode == IEEE80211_M_WDS) { 646193240Ssam /* 647193240Ssam * WDS vaps must have an associated AP vap; find one. 648193240Ssam * XXX not right. 649193240Ssam */ 650193240Ssam TAILQ_FOREACH(apvap, &ic->ic_vaps, iv_next) 651193240Ssam if (apvap->iv_opmode == IEEE80211_M_HOSTAP) { 652193240Ssam mvp->mv_ap_hvap = MWL_VAP(apvap)->mv_hvap; 653193240Ssam break; 654193240Ssam } 655193240Ssam KASSERT(mvp->mv_ap_hvap != NULL, ("no ap vap")); 656193240Ssam } 657193240Ssam vap = &mvp->mv_vap; 658287197Sglebius ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid); 659193240Ssam /* override with driver methods */ 660193240Ssam mvp->mv_newstate = vap->iv_newstate; 661193240Ssam vap->iv_newstate = mwl_newstate; 662193240Ssam vap->iv_max_keyix = 0; /* XXX */ 663193240Ssam vap->iv_key_alloc = mwl_key_alloc; 664193240Ssam vap->iv_key_delete = mwl_key_delete; 665193240Ssam vap->iv_key_set = mwl_key_set; 666193240Ssam#ifdef MWL_HOST_PS_SUPPORT 667195618Srpaulo if (opmode == IEEE80211_M_HOSTAP || opmode == IEEE80211_M_MBSS) { 668193240Ssam vap->iv_update_ps = mwl_update_ps; 669193240Ssam mvp->mv_set_tim = vap->iv_set_tim; 670193240Ssam vap->iv_set_tim = mwl_set_tim; 671193240Ssam } 672193240Ssam#endif 673193240Ssam vap->iv_reset = mwl_reset; 674193240Ssam vap->iv_update_beacon = mwl_beacon_update; 675193240Ssam 676193240Ssam /* override max aid so sta's cannot assoc when we're out of sta id's */ 677193240Ssam vap->iv_max_aid = MWL_MAXSTAID; 678193240Ssam /* override default A-MPDU rx parameters */ 679193240Ssam vap->iv_ampdu_rxmax = IEEE80211_HTCAP_MAXRXAMPDU_64K; 680193240Ssam vap->iv_ampdu_density = IEEE80211_HTCAP_MPDUDENSITY_4; 681193240Ssam 682193240Ssam /* complete setup */ 683287197Sglebius ieee80211_vap_attach(vap, mwl_media_change, ieee80211_media_status, 684287197Sglebius mac); 685193240Ssam 686193240Ssam switch (vap->iv_opmode) { 687193240Ssam case IEEE80211_M_HOSTAP: 688195618Srpaulo case IEEE80211_M_MBSS: 689193240Ssam case IEEE80211_M_STA: 690193240Ssam /* 691193240Ssam * Setup sta db entry for local address. 692193240Ssam */ 693193240Ssam mwl_localstadb(vap); 694195618Srpaulo if (vap->iv_opmode == IEEE80211_M_HOSTAP || 695195618Srpaulo vap->iv_opmode == IEEE80211_M_MBSS) 696193240Ssam sc->sc_napvaps++; 697193240Ssam else 698193240Ssam sc->sc_nstavaps++; 699193240Ssam break; 700193240Ssam case IEEE80211_M_WDS: 701193240Ssam sc->sc_nwdsvaps++; 702193240Ssam break; 703193240Ssam default: 704193240Ssam break; 705193240Ssam } 706193240Ssam /* 707193240Ssam * Setup overall operating mode. 708193240Ssam */ 709193240Ssam if (sc->sc_napvaps) 710193240Ssam ic->ic_opmode = IEEE80211_M_HOSTAP; 711193240Ssam else if (sc->sc_nstavaps) 712193240Ssam ic->ic_opmode = IEEE80211_M_STA; 713193240Ssam else 714193240Ssam ic->ic_opmode = opmode; 715193240Ssam 716193240Ssam return vap; 717193240Ssam} 718193240Ssam 719193240Ssamstatic void 720193240Ssammwl_vap_delete(struct ieee80211vap *vap) 721193240Ssam{ 722193240Ssam struct mwl_vap *mvp = MWL_VAP(vap); 723287197Sglebius struct mwl_softc *sc = vap->iv_ic->ic_softc; 724193240Ssam struct mwl_hal *mh = sc->sc_mh; 725193240Ssam struct mwl_hal_vap *hvap = mvp->mv_hvap; 726193240Ssam enum ieee80211_opmode opmode = vap->iv_opmode; 727193240Ssam 728193240Ssam /* XXX disallow ap vap delete if WDS still present */ 729287197Sglebius if (sc->sc_running) { 730193240Ssam /* quiesce h/w while we remove the vap */ 731193240Ssam mwl_hal_intrset(mh, 0); /* disable interrupts */ 732193240Ssam } 733193240Ssam ieee80211_vap_detach(vap); 734193240Ssam switch (opmode) { 735193240Ssam case IEEE80211_M_HOSTAP: 736195618Srpaulo case IEEE80211_M_MBSS: 737193240Ssam case IEEE80211_M_STA: 738193240Ssam KASSERT(hvap != NULL, ("no hal vap handle")); 739193240Ssam (void) mwl_hal_delstation(hvap, vap->iv_myaddr); 740193240Ssam mwl_hal_delvap(hvap); 741195618Srpaulo if (opmode == IEEE80211_M_HOSTAP || opmode == IEEE80211_M_MBSS) 742193240Ssam sc->sc_napvaps--; 743193240Ssam else 744193240Ssam sc->sc_nstavaps--; 745193240Ssam /* XXX don't do it for IEEE80211_CLONE_MACADDR */ 746193240Ssam reclaim_address(sc, vap->iv_myaddr); 747193240Ssam break; 748193240Ssam case IEEE80211_M_WDS: 749193240Ssam sc->sc_nwdsvaps--; 750193240Ssam break; 751193240Ssam default: 752193240Ssam break; 753193240Ssam } 754193240Ssam mwl_cleartxq(sc, vap); 755193240Ssam free(mvp, M_80211_VAP); 756287197Sglebius if (sc->sc_running) 757193240Ssam mwl_hal_intrset(mh, sc->sc_imask); 758193240Ssam} 759193240Ssam 760193240Ssamvoid 761193240Ssammwl_suspend(struct mwl_softc *sc) 762193240Ssam{ 763193240Ssam 764287197Sglebius MWL_LOCK(sc); 765287197Sglebius mwl_stop(sc); 766287197Sglebius MWL_UNLOCK(sc); 767193240Ssam} 768193240Ssam 769193240Ssamvoid 770193240Ssammwl_resume(struct mwl_softc *sc) 771193240Ssam{ 772287197Sglebius int error = EDOOFUS; 773193240Ssam 774287197Sglebius MWL_LOCK(sc); 775287197Sglebius if (sc->sc_ic.ic_nrunning > 0) 776287197Sglebius error = mwl_init(sc); 777287197Sglebius MWL_UNLOCK(sc); 778193240Ssam 779287197Sglebius if (error == 0) 780287197Sglebius ieee80211_start_all(&sc->sc_ic); /* start all vap's */ 781193240Ssam} 782193240Ssam 783193240Ssamvoid 784193240Ssammwl_shutdown(void *arg) 785193240Ssam{ 786193240Ssam struct mwl_softc *sc = arg; 787193240Ssam 788287197Sglebius MWL_LOCK(sc); 789287197Sglebius mwl_stop(sc); 790287197Sglebius MWL_UNLOCK(sc); 791193240Ssam} 792193240Ssam 793193240Ssam/* 794193240Ssam * Interrupt handler. Most of the actual processing is deferred. 795193240Ssam */ 796193240Ssamvoid 797193240Ssammwl_intr(void *arg) 798193240Ssam{ 799193240Ssam struct mwl_softc *sc = arg; 800193240Ssam struct mwl_hal *mh = sc->sc_mh; 801193240Ssam uint32_t status; 802193240Ssam 803193240Ssam if (sc->sc_invalid) { 804193240Ssam /* 805193240Ssam * The hardware is not ready/present, don't touch anything. 806193240Ssam * Note this can happen early on if the IRQ is shared. 807193240Ssam */ 808193240Ssam DPRINTF(sc, MWL_DEBUG_ANY, "%s: invalid; ignored\n", __func__); 809193240Ssam return; 810193240Ssam } 811193240Ssam /* 812193240Ssam * Figure out the reason(s) for the interrupt. 813193240Ssam */ 814193240Ssam mwl_hal_getisr(mh, &status); /* NB: clears ISR too */ 815193240Ssam if (status == 0) /* must be a shared irq */ 816193240Ssam return; 817193240Ssam 818193240Ssam DPRINTF(sc, MWL_DEBUG_INTR, "%s: status 0x%x imask 0x%x\n", 819193240Ssam __func__, status, sc->sc_imask); 820193240Ssam if (status & MACREG_A2HRIC_BIT_RX_RDY) 821193240Ssam taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 822193240Ssam if (status & MACREG_A2HRIC_BIT_TX_DONE) 823193240Ssam taskqueue_enqueue(sc->sc_tq, &sc->sc_txtask); 824193240Ssam if (status & MACREG_A2HRIC_BIT_BA_WATCHDOG) 825193240Ssam taskqueue_enqueue(sc->sc_tq, &sc->sc_bawatchdogtask); 826193240Ssam if (status & MACREG_A2HRIC_BIT_OPC_DONE) 827193240Ssam mwl_hal_cmddone(mh); 828193240Ssam if (status & MACREG_A2HRIC_BIT_MAC_EVENT) { 829193240Ssam ; 830193240Ssam } 831193240Ssam if (status & MACREG_A2HRIC_BIT_ICV_ERROR) { 832193240Ssam /* TKIP ICV error */ 833193240Ssam sc->sc_stats.mst_rx_badtkipicv++; 834193240Ssam } 835193240Ssam if (status & MACREG_A2HRIC_BIT_QUEUE_EMPTY) { 836193240Ssam /* 11n aggregation queue is empty, re-fill */ 837193240Ssam ; 838193240Ssam } 839193240Ssam if (status & MACREG_A2HRIC_BIT_QUEUE_FULL) { 840193240Ssam ; 841193240Ssam } 842193240Ssam if (status & MACREG_A2HRIC_BIT_RADAR_DETECT) { 843193240Ssam /* radar detected, process event */ 844193240Ssam taskqueue_enqueue(sc->sc_tq, &sc->sc_radartask); 845193240Ssam } 846193240Ssam if (status & MACREG_A2HRIC_BIT_CHAN_SWITCH) { 847193240Ssam /* DFS channel switch */ 848193240Ssam taskqueue_enqueue(sc->sc_tq, &sc->sc_chanswitchtask); 849193240Ssam } 850193240Ssam} 851193240Ssam 852193240Ssamstatic void 853193240Ssammwl_radar_proc(void *arg, int pending) 854193240Ssam{ 855193240Ssam struct mwl_softc *sc = arg; 856287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 857193240Ssam 858193240Ssam DPRINTF(sc, MWL_DEBUG_ANY, "%s: radar detected, pending %u\n", 859193240Ssam __func__, pending); 860193240Ssam 861193240Ssam sc->sc_stats.mst_radardetect++; 862195171Ssam /* XXX stop h/w BA streams? */ 863193240Ssam 864193240Ssam IEEE80211_LOCK(ic); 865193240Ssam ieee80211_dfs_notify_radar(ic, ic->ic_curchan); 866193240Ssam IEEE80211_UNLOCK(ic); 867193240Ssam} 868193240Ssam 869193240Ssamstatic void 870193240Ssammwl_chanswitch_proc(void *arg, int pending) 871193240Ssam{ 872193240Ssam struct mwl_softc *sc = arg; 873287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 874193240Ssam 875193240Ssam DPRINTF(sc, MWL_DEBUG_ANY, "%s: channel switch notice, pending %u\n", 876193240Ssam __func__, pending); 877193240Ssam 878193240Ssam IEEE80211_LOCK(ic); 879193240Ssam sc->sc_csapending = 0; 880193240Ssam ieee80211_csa_completeswitch(ic); 881193240Ssam IEEE80211_UNLOCK(ic); 882193240Ssam} 883193240Ssam 884193240Ssamstatic void 885193240Ssammwl_bawatchdog(const MWL_HAL_BASTREAM *sp) 886193240Ssam{ 887193240Ssam struct ieee80211_node *ni = sp->data[0]; 888193240Ssam 889193240Ssam /* send DELBA and drop the stream */ 890193240Ssam ieee80211_ampdu_stop(ni, sp->data[1], IEEE80211_REASON_UNSPECIFIED); 891193240Ssam} 892193240Ssam 893193240Ssamstatic void 894193240Ssammwl_bawatchdog_proc(void *arg, int pending) 895193240Ssam{ 896193240Ssam struct mwl_softc *sc = arg; 897193240Ssam struct mwl_hal *mh = sc->sc_mh; 898193240Ssam const MWL_HAL_BASTREAM *sp; 899193240Ssam uint8_t bitmap, n; 900193240Ssam 901193240Ssam sc->sc_stats.mst_bawatchdog++; 902193240Ssam 903193240Ssam if (mwl_hal_getwatchdogbitmap(mh, &bitmap) != 0) { 904193240Ssam DPRINTF(sc, MWL_DEBUG_AMPDU, 905193240Ssam "%s: could not get bitmap\n", __func__); 906193240Ssam sc->sc_stats.mst_bawatchdog_failed++; 907193240Ssam return; 908193240Ssam } 909193240Ssam DPRINTF(sc, MWL_DEBUG_AMPDU, "%s: bitmap 0x%x\n", __func__, bitmap); 910193240Ssam if (bitmap == 0xff) { 911193240Ssam n = 0; 912193240Ssam /* disable all ba streams */ 913193240Ssam for (bitmap = 0; bitmap < 8; bitmap++) { 914193240Ssam sp = mwl_hal_bastream_lookup(mh, bitmap); 915193240Ssam if (sp != NULL) { 916193240Ssam mwl_bawatchdog(sp); 917193240Ssam n++; 918193240Ssam } 919193240Ssam } 920193240Ssam if (n == 0) { 921193240Ssam DPRINTF(sc, MWL_DEBUG_AMPDU, 922193240Ssam "%s: no BA streams found\n", __func__); 923193240Ssam sc->sc_stats.mst_bawatchdog_empty++; 924193240Ssam } 925193240Ssam } else if (bitmap != 0xaa) { 926193240Ssam /* disable a single ba stream */ 927193240Ssam sp = mwl_hal_bastream_lookup(mh, bitmap); 928193240Ssam if (sp != NULL) { 929193240Ssam mwl_bawatchdog(sp); 930193240Ssam } else { 931193240Ssam DPRINTF(sc, MWL_DEBUG_AMPDU, 932193240Ssam "%s: no BA stream %d\n", __func__, bitmap); 933193240Ssam sc->sc_stats.mst_bawatchdog_notfound++; 934193240Ssam } 935193240Ssam } 936193240Ssam} 937193240Ssam 938193240Ssam/* 939193240Ssam * Convert net80211 channel to a HAL channel. 940193240Ssam */ 941193240Ssamstatic void 942193240Ssammwl_mapchan(MWL_HAL_CHANNEL *hc, const struct ieee80211_channel *chan) 943193240Ssam{ 944193240Ssam hc->channel = chan->ic_ieee; 945193240Ssam 946193240Ssam *(uint32_t *)&hc->channelFlags = 0; 947193240Ssam if (IEEE80211_IS_CHAN_2GHZ(chan)) 948193240Ssam hc->channelFlags.FreqBand = MWL_FREQ_BAND_2DOT4GHZ; 949193240Ssam else if (IEEE80211_IS_CHAN_5GHZ(chan)) 950193240Ssam hc->channelFlags.FreqBand = MWL_FREQ_BAND_5GHZ; 951193240Ssam if (IEEE80211_IS_CHAN_HT40(chan)) { 952193240Ssam hc->channelFlags.ChnlWidth = MWL_CH_40_MHz_WIDTH; 953193240Ssam if (IEEE80211_IS_CHAN_HT40U(chan)) 954193240Ssam hc->channelFlags.ExtChnlOffset = MWL_EXT_CH_ABOVE_CTRL_CH; 955193240Ssam else 956193240Ssam hc->channelFlags.ExtChnlOffset = MWL_EXT_CH_BELOW_CTRL_CH; 957193240Ssam } else 958193240Ssam hc->channelFlags.ChnlWidth = MWL_CH_20_MHz_WIDTH; 959193240Ssam /* XXX 10MHz channels */ 960193240Ssam} 961193240Ssam 962193240Ssam/* 963193240Ssam * Inform firmware of our tx/rx dma setup. The BAR 0 964193240Ssam * writes below are for compatibility with older firmware. 965193240Ssam * For current firmware we send this information with a 966193240Ssam * cmd block via mwl_hal_sethwdma. 967193240Ssam */ 968193240Ssamstatic int 969193240Ssammwl_setupdma(struct mwl_softc *sc) 970193240Ssam{ 971193240Ssam int error, i; 972193240Ssam 973193240Ssam sc->sc_hwdma.rxDescRead = sc->sc_rxdma.dd_desc_paddr; 974193240Ssam WR4(sc, sc->sc_hwspecs.rxDescRead, sc->sc_hwdma.rxDescRead); 975193240Ssam WR4(sc, sc->sc_hwspecs.rxDescWrite, sc->sc_hwdma.rxDescRead); 976193240Ssam 977195171Ssam for (i = 0; i < MWL_NUM_TX_QUEUES-MWL_NUM_ACK_QUEUES; i++) { 978193240Ssam struct mwl_txq *txq = &sc->sc_txq[i]; 979193240Ssam sc->sc_hwdma.wcbBase[i] = txq->dma.dd_desc_paddr; 980193240Ssam WR4(sc, sc->sc_hwspecs.wcbBase[i], sc->sc_hwdma.wcbBase[i]); 981193240Ssam } 982193240Ssam sc->sc_hwdma.maxNumTxWcb = mwl_txbuf; 983195171Ssam sc->sc_hwdma.maxNumWCB = MWL_NUM_TX_QUEUES-MWL_NUM_ACK_QUEUES; 984193240Ssam 985193240Ssam error = mwl_hal_sethwdma(sc->sc_mh, &sc->sc_hwdma); 986193240Ssam if (error != 0) { 987193240Ssam device_printf(sc->sc_dev, 988193240Ssam "unable to setup tx/rx dma; hal status %u\n", error); 989193240Ssam /* XXX */ 990193240Ssam } 991193240Ssam return error; 992193240Ssam} 993193240Ssam 994193240Ssam/* 995193240Ssam * Inform firmware of tx rate parameters. 996193240Ssam * Called after a channel change. 997193240Ssam */ 998193240Ssamstatic int 999193240Ssammwl_setcurchanrates(struct mwl_softc *sc) 1000193240Ssam{ 1001287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 1002193240Ssam const struct ieee80211_rateset *rs; 1003193240Ssam MWL_HAL_TXRATE rates; 1004193240Ssam 1005193240Ssam memset(&rates, 0, sizeof(rates)); 1006193240Ssam rs = ieee80211_get_suprates(ic, ic->ic_curchan); 1007193240Ssam /* rate used to send management frames */ 1008193240Ssam rates.MgtRate = rs->rs_rates[0] & IEEE80211_RATE_VAL; 1009193240Ssam /* rate used to send multicast frames */ 1010193240Ssam rates.McastRate = rates.MgtRate; 1011193240Ssam 1012193240Ssam return mwl_hal_settxrate_auto(sc->sc_mh, &rates); 1013193240Ssam} 1014193240Ssam 1015193240Ssam/* 1016193240Ssam * Inform firmware of tx rate parameters. Called whenever 1017193240Ssam * user-settable params change and after a channel change. 1018193240Ssam */ 1019193240Ssamstatic int 1020193240Ssammwl_setrates(struct ieee80211vap *vap) 1021193240Ssam{ 1022193240Ssam struct mwl_vap *mvp = MWL_VAP(vap); 1023193240Ssam struct ieee80211_node *ni = vap->iv_bss; 1024193240Ssam const struct ieee80211_txparam *tp = ni->ni_txparms; 1025193240Ssam MWL_HAL_TXRATE rates; 1026193240Ssam 1027193240Ssam KASSERT(vap->iv_state == IEEE80211_S_RUN, ("state %d", vap->iv_state)); 1028193240Ssam 1029193240Ssam /* 1030193240Ssam * Update the h/w rate map. 1031193240Ssam * NB: 0x80 for MCS is passed through unchanged 1032193240Ssam */ 1033193240Ssam memset(&rates, 0, sizeof(rates)); 1034193240Ssam /* rate used to send management frames */ 1035193240Ssam rates.MgtRate = tp->mgmtrate; 1036193240Ssam /* rate used to send multicast frames */ 1037193240Ssam rates.McastRate = tp->mcastrate; 1038193240Ssam 1039193240Ssam /* while here calculate EAPOL fixed rate cookie */ 1040193240Ssam mvp->mv_eapolformat = htole16(mwl_calcformat(rates.MgtRate, ni)); 1041193240Ssam 1042195171Ssam return mwl_hal_settxrate(mvp->mv_hvap, 1043195171Ssam tp->ucastrate != IEEE80211_FIXED_RATE_NONE ? 1044195171Ssam RATE_FIXED : RATE_AUTO, &rates); 1045193240Ssam} 1046193240Ssam 1047193240Ssam/* 1048193240Ssam * Setup a fixed xmit rate cookie for EAPOL frames. 1049193240Ssam */ 1050193240Ssamstatic void 1051193240Ssammwl_seteapolformat(struct ieee80211vap *vap) 1052193240Ssam{ 1053193240Ssam struct mwl_vap *mvp = MWL_VAP(vap); 1054193240Ssam struct ieee80211_node *ni = vap->iv_bss; 1055193240Ssam enum ieee80211_phymode mode; 1056193240Ssam uint8_t rate; 1057193240Ssam 1058193240Ssam KASSERT(vap->iv_state == IEEE80211_S_RUN, ("state %d", vap->iv_state)); 1059193240Ssam 1060193240Ssam mode = ieee80211_chan2mode(ni->ni_chan); 1061193240Ssam /* 1062193240Ssam * Use legacy rates when operating a mixed HT+non-HT bss. 1063193240Ssam * NB: this may violate POLA for sta and wds vap's. 1064193240Ssam */ 1065193240Ssam if (mode == IEEE80211_MODE_11NA && 1066193656Ssam (vap->iv_flags_ht & IEEE80211_FHT_PUREN) == 0) 1067193240Ssam rate = vap->iv_txparms[IEEE80211_MODE_11A].mgmtrate; 1068193240Ssam else if (mode == IEEE80211_MODE_11NG && 1069193656Ssam (vap->iv_flags_ht & IEEE80211_FHT_PUREN) == 0) 1070193240Ssam rate = vap->iv_txparms[IEEE80211_MODE_11G].mgmtrate; 1071193240Ssam else 1072193240Ssam rate = vap->iv_txparms[mode].mgmtrate; 1073193240Ssam 1074193240Ssam mvp->mv_eapolformat = htole16(mwl_calcformat(rate, ni)); 1075193240Ssam} 1076193240Ssam 1077193240Ssam/* 1078193240Ssam * Map SKU+country code to region code for radar bin'ing. 1079193240Ssam */ 1080193240Ssamstatic int 1081193240Ssammwl_map2regioncode(const struct ieee80211_regdomain *rd) 1082193240Ssam{ 1083193240Ssam switch (rd->regdomain) { 1084193240Ssam case SKU_FCC: 1085193240Ssam case SKU_FCC3: 1086193240Ssam return DOMAIN_CODE_FCC; 1087193240Ssam case SKU_CA: 1088193240Ssam return DOMAIN_CODE_IC; 1089193240Ssam case SKU_ETSI: 1090193240Ssam case SKU_ETSI2: 1091193240Ssam case SKU_ETSI3: 1092193240Ssam if (rd->country == CTRY_SPAIN) 1093193240Ssam return DOMAIN_CODE_SPAIN; 1094193240Ssam if (rd->country == CTRY_FRANCE || rd->country == CTRY_FRANCE2) 1095193240Ssam return DOMAIN_CODE_FRANCE; 1096193240Ssam /* XXX force 1.3.1 radar type */ 1097193240Ssam return DOMAIN_CODE_ETSI_131; 1098193240Ssam case SKU_JAPAN: 1099193240Ssam return DOMAIN_CODE_MKK; 1100193240Ssam case SKU_ROW: 1101193240Ssam return DOMAIN_CODE_DGT; /* Taiwan */ 1102193240Ssam case SKU_APAC: 1103193240Ssam case SKU_APAC2: 1104193240Ssam case SKU_APAC3: 1105193240Ssam return DOMAIN_CODE_AUS; /* Australia */ 1106193240Ssam } 1107193240Ssam /* XXX KOREA? */ 1108193240Ssam return DOMAIN_CODE_FCC; /* XXX? */ 1109193240Ssam} 1110193240Ssam 1111193240Ssamstatic int 1112193240Ssammwl_hal_reset(struct mwl_softc *sc) 1113193240Ssam{ 1114287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 1115193240Ssam struct mwl_hal *mh = sc->sc_mh; 1116193240Ssam 1117193240Ssam mwl_hal_setantenna(mh, WL_ANTENNATYPE_RX, sc->sc_rxantenna); 1118193240Ssam mwl_hal_setantenna(mh, WL_ANTENNATYPE_TX, sc->sc_txantenna); 1119193240Ssam mwl_hal_setradio(mh, 1, WL_AUTO_PREAMBLE); 1120193240Ssam mwl_hal_setwmm(sc->sc_mh, (ic->ic_flags & IEEE80211_F_WME) != 0); 1121193240Ssam mwl_chan_set(sc, ic->ic_curchan); 1122195171Ssam /* NB: RF/RA performance tuned for indoor mode */ 1123195171Ssam mwl_hal_setrateadaptmode(mh, 0); 1124193240Ssam mwl_hal_setoptimizationlevel(mh, 1125193240Ssam (ic->ic_flags & IEEE80211_F_BURST) != 0); 1126193240Ssam 1127193240Ssam mwl_hal_setregioncode(mh, mwl_map2regioncode(&ic->ic_regdomain)); 1128193240Ssam 1129195171Ssam mwl_hal_setaggampduratemode(mh, 1, 80); /* XXX */ 1130195171Ssam mwl_hal_setcfend(mh, 0); /* XXX */ 1131195171Ssam 1132193240Ssam return 1; 1133193240Ssam} 1134193240Ssam 1135193240Ssamstatic int 1136287197Sglebiusmwl_init(struct mwl_softc *sc) 1137193240Ssam{ 1138193240Ssam struct mwl_hal *mh = sc->sc_mh; 1139193240Ssam int error = 0; 1140193240Ssam 1141193240Ssam MWL_LOCK_ASSERT(sc); 1142193240Ssam 1143193240Ssam /* 1144193240Ssam * Stop anything previously setup. This is safe 1145193240Ssam * whether this is the first time through or not. 1146193240Ssam */ 1147287197Sglebius mwl_stop(sc); 1148193240Ssam 1149193240Ssam /* 1150193240Ssam * Push vap-independent state to the firmware. 1151193240Ssam */ 1152193240Ssam if (!mwl_hal_reset(sc)) { 1153287197Sglebius device_printf(sc->sc_dev, "unable to reset hardware\n"); 1154193240Ssam return EIO; 1155193240Ssam } 1156193240Ssam 1157193240Ssam /* 1158193240Ssam * Setup recv (once); transmit is already good to go. 1159193240Ssam */ 1160193240Ssam error = mwl_startrecv(sc); 1161193240Ssam if (error != 0) { 1162287197Sglebius device_printf(sc->sc_dev, "unable to start recv logic\n"); 1163193240Ssam return error; 1164193240Ssam } 1165193240Ssam 1166193240Ssam /* 1167193240Ssam * Enable interrupts. 1168193240Ssam */ 1169193240Ssam sc->sc_imask = MACREG_A2HRIC_BIT_RX_RDY 1170193240Ssam | MACREG_A2HRIC_BIT_TX_DONE 1171193240Ssam | MACREG_A2HRIC_BIT_OPC_DONE 1172193240Ssam#if 0 1173193240Ssam | MACREG_A2HRIC_BIT_MAC_EVENT 1174193240Ssam#endif 1175193240Ssam | MACREG_A2HRIC_BIT_ICV_ERROR 1176193240Ssam | MACREG_A2HRIC_BIT_RADAR_DETECT 1177193240Ssam | MACREG_A2HRIC_BIT_CHAN_SWITCH 1178193240Ssam#if 0 1179193240Ssam | MACREG_A2HRIC_BIT_QUEUE_EMPTY 1180193240Ssam#endif 1181193240Ssam | MACREG_A2HRIC_BIT_BA_WATCHDOG 1182195171Ssam | MACREQ_A2HRIC_BIT_TX_ACK 1183193240Ssam ; 1184193240Ssam 1185287197Sglebius sc->sc_running = 1; 1186193240Ssam mwl_hal_intrset(mh, sc->sc_imask); 1187199559Sjhb callout_reset(&sc->sc_watchdog, hz, mwl_watchdog, sc); 1188193240Ssam 1189193240Ssam return 0; 1190193240Ssam} 1191193240Ssam 1192193240Ssamstatic void 1193287197Sglebiusmwl_stop(struct mwl_softc *sc) 1194193240Ssam{ 1195193240Ssam 1196193240Ssam MWL_LOCK_ASSERT(sc); 1197287197Sglebius if (sc->sc_running) { 1198193240Ssam /* 1199193240Ssam * Shutdown the hardware and driver. 1200193240Ssam */ 1201287197Sglebius sc->sc_running = 0; 1202199559Sjhb callout_stop(&sc->sc_watchdog); 1203199559Sjhb sc->sc_tx_timer = 0; 1204193240Ssam mwl_draintxq(sc); 1205193240Ssam } 1206193240Ssam} 1207193240Ssam 1208193240Ssamstatic int 1209193240Ssammwl_reset_vap(struct ieee80211vap *vap, int state) 1210193240Ssam{ 1211193240Ssam struct mwl_hal_vap *hvap = MWL_VAP(vap)->mv_hvap; 1212193240Ssam struct ieee80211com *ic = vap->iv_ic; 1213193240Ssam 1214193240Ssam if (state == IEEE80211_S_RUN) 1215193240Ssam mwl_setrates(vap); 1216193240Ssam /* XXX off by 1? */ 1217193240Ssam mwl_hal_setrtsthreshold(hvap, vap->iv_rtsthreshold); 1218193240Ssam /* XXX auto? 20/40 split? */ 1219193656Ssam mwl_hal_sethtgi(hvap, (vap->iv_flags_ht & 1220193656Ssam (IEEE80211_FHT_SHORTGI20|IEEE80211_FHT_SHORTGI40)) ? 1 : 0); 1221193240Ssam mwl_hal_setnprot(hvap, ic->ic_htprotmode == IEEE80211_PROT_NONE ? 1222193240Ssam HTPROTECT_NONE : HTPROTECT_AUTO); 1223193240Ssam /* XXX txpower cap */ 1224193240Ssam 1225193240Ssam /* re-setup beacons */ 1226193240Ssam if (state == IEEE80211_S_RUN && 1227193240Ssam (vap->iv_opmode == IEEE80211_M_HOSTAP || 1228195618Srpaulo vap->iv_opmode == IEEE80211_M_MBSS || 1229193240Ssam vap->iv_opmode == IEEE80211_M_IBSS)) { 1230193240Ssam mwl_setapmode(vap, vap->iv_bss->ni_chan); 1231193240Ssam mwl_hal_setnprotmode(hvap, 1232193240Ssam MS(ic->ic_curhtprotmode, IEEE80211_HTINFO_OPMODE)); 1233193240Ssam return mwl_beacon_setup(vap); 1234193240Ssam } 1235193240Ssam return 0; 1236193240Ssam} 1237193240Ssam 1238193240Ssam/* 1239193240Ssam * Reset the hardware w/o losing operational state. 1240330446Seadler * Used to reset or reload hardware state for a vap. 1241193240Ssam */ 1242193240Ssamstatic int 1243193240Ssammwl_reset(struct ieee80211vap *vap, u_long cmd) 1244193240Ssam{ 1245193240Ssam struct mwl_hal_vap *hvap = MWL_VAP(vap)->mv_hvap; 1246193240Ssam int error = 0; 1247193240Ssam 1248193240Ssam if (hvap != NULL) { /* WDS, MONITOR, etc. */ 1249193240Ssam struct ieee80211com *ic = vap->iv_ic; 1250287197Sglebius struct mwl_softc *sc = ic->ic_softc; 1251193240Ssam struct mwl_hal *mh = sc->sc_mh; 1252193240Ssam 1253195171Ssam /* XXX handle DWDS sta vap change */ 1254193240Ssam /* XXX do we need to disable interrupts? */ 1255193240Ssam mwl_hal_intrset(mh, 0); /* disable interrupts */ 1256193240Ssam error = mwl_reset_vap(vap, vap->iv_state); 1257193240Ssam mwl_hal_intrset(mh, sc->sc_imask); 1258193240Ssam } 1259193240Ssam return error; 1260193240Ssam} 1261193240Ssam 1262193240Ssam/* 1263193240Ssam * Allocate a tx buffer for sending a frame. The 1264193240Ssam * packet is assumed to have the WME AC stored so 1265193240Ssam * we can use it to select the appropriate h/w queue. 1266193240Ssam */ 1267193240Ssamstatic struct mwl_txbuf * 1268193240Ssammwl_gettxbuf(struct mwl_softc *sc, struct mwl_txq *txq) 1269193240Ssam{ 1270193240Ssam struct mwl_txbuf *bf; 1271193240Ssam 1272193240Ssam /* 1273193240Ssam * Grab a TX buffer and associated resources. 1274193240Ssam */ 1275193240Ssam MWL_TXQ_LOCK(txq); 1276193240Ssam bf = STAILQ_FIRST(&txq->free); 1277193240Ssam if (bf != NULL) { 1278193240Ssam STAILQ_REMOVE_HEAD(&txq->free, bf_list); 1279193240Ssam txq->nfree--; 1280193240Ssam } 1281193240Ssam MWL_TXQ_UNLOCK(txq); 1282193240Ssam if (bf == NULL) 1283193240Ssam DPRINTF(sc, MWL_DEBUG_XMIT, 1284193240Ssam "%s: out of xmit buffers on q %d\n", __func__, txq->qnum); 1285193240Ssam return bf; 1286193240Ssam} 1287193240Ssam 1288193240Ssam/* 1289193240Ssam * Return a tx buffer to the queue it came from. Note there 1290193240Ssam * are two cases because we must preserve the order of buffers 1291193240Ssam * as it reflects the fixed order of descriptors in memory 1292193240Ssam * (the firmware pre-fetches descriptors so we cannot reorder). 1293193240Ssam */ 1294193240Ssamstatic void 1295193240Ssammwl_puttxbuf_head(struct mwl_txq *txq, struct mwl_txbuf *bf) 1296193240Ssam{ 1297193240Ssam bf->bf_m = NULL; 1298193240Ssam bf->bf_node = NULL; 1299193240Ssam MWL_TXQ_LOCK(txq); 1300193240Ssam STAILQ_INSERT_HEAD(&txq->free, bf, bf_list); 1301193240Ssam txq->nfree++; 1302193240Ssam MWL_TXQ_UNLOCK(txq); 1303193240Ssam} 1304193240Ssam 1305193240Ssamstatic void 1306193240Ssammwl_puttxbuf_tail(struct mwl_txq *txq, struct mwl_txbuf *bf) 1307193240Ssam{ 1308193240Ssam bf->bf_m = NULL; 1309193240Ssam bf->bf_node = NULL; 1310193240Ssam MWL_TXQ_LOCK(txq); 1311193240Ssam STAILQ_INSERT_TAIL(&txq->free, bf, bf_list); 1312193240Ssam txq->nfree++; 1313193240Ssam MWL_TXQ_UNLOCK(txq); 1314193240Ssam} 1315193240Ssam 1316287197Sglebiusstatic int 1317287197Sglebiusmwl_transmit(struct ieee80211com *ic, struct mbuf *m) 1318287197Sglebius{ 1319287197Sglebius struct mwl_softc *sc = ic->ic_softc; 1320287197Sglebius int error; 1321287197Sglebius 1322287197Sglebius MWL_LOCK(sc); 1323287197Sglebius if (!sc->sc_running) { 1324287197Sglebius MWL_UNLOCK(sc); 1325287197Sglebius return (ENXIO); 1326287197Sglebius } 1327287197Sglebius error = mbufq_enqueue(&sc->sc_snd, m); 1328287197Sglebius if (error) { 1329287197Sglebius MWL_UNLOCK(sc); 1330287197Sglebius return (error); 1331287197Sglebius } 1332287197Sglebius mwl_start(sc); 1333287197Sglebius MWL_UNLOCK(sc); 1334287197Sglebius return (0); 1335287197Sglebius} 1336287197Sglebius 1337193240Ssamstatic void 1338287197Sglebiusmwl_start(struct mwl_softc *sc) 1339193240Ssam{ 1340193240Ssam struct ieee80211_node *ni; 1341193240Ssam struct mwl_txbuf *bf; 1342193240Ssam struct mbuf *m; 1343193240Ssam struct mwl_txq *txq = NULL; /* XXX silence gcc */ 1344193240Ssam int nqueued; 1345193240Ssam 1346287197Sglebius MWL_LOCK_ASSERT(sc); 1347287197Sglebius if (!sc->sc_running || sc->sc_invalid) 1348193240Ssam return; 1349193240Ssam nqueued = 0; 1350287197Sglebius while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 1351193240Ssam /* 1352193240Ssam * Grab the node for the destination. 1353193240Ssam */ 1354193240Ssam ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1355193240Ssam KASSERT(ni != NULL, ("no node")); 1356193240Ssam m->m_pkthdr.rcvif = NULL; /* committed, clear ref */ 1357193240Ssam /* 1358193240Ssam * Grab a TX buffer and associated resources. 1359193240Ssam * We honor the classification by the 802.11 layer. 1360193240Ssam */ 1361193240Ssam txq = sc->sc_ac2q[M_WME_GETAC(m)]; 1362193240Ssam bf = mwl_gettxbuf(sc, txq); 1363193240Ssam if (bf == NULL) { 1364193240Ssam m_freem(m); 1365193240Ssam ieee80211_free_node(ni); 1366193240Ssam#ifdef MWL_TX_NODROP 1367193240Ssam sc->sc_stats.mst_tx_qstop++; 1368193240Ssam break; 1369193240Ssam#else 1370193240Ssam DPRINTF(sc, MWL_DEBUG_XMIT, 1371193240Ssam "%s: tail drop on q %d\n", __func__, txq->qnum); 1372193240Ssam sc->sc_stats.mst_tx_qdrop++; 1373193240Ssam continue; 1374193240Ssam#endif /* MWL_TX_NODROP */ 1375193240Ssam } 1376193240Ssam 1377193240Ssam /* 1378193240Ssam * Pass the frame to the h/w for transmission. 1379193240Ssam */ 1380193240Ssam if (mwl_tx_start(sc, ni, bf, m)) { 1381287197Sglebius if_inc_counter(ni->ni_vap->iv_ifp, 1382287197Sglebius IFCOUNTER_OERRORS, 1); 1383193240Ssam mwl_puttxbuf_head(txq, bf); 1384193240Ssam ieee80211_free_node(ni); 1385193240Ssam continue; 1386193240Ssam } 1387193240Ssam nqueued++; 1388193240Ssam if (nqueued >= mwl_txcoalesce) { 1389193240Ssam /* 1390193240Ssam * Poke the firmware to process queued frames; 1391193240Ssam * see below about (lack of) locking. 1392193240Ssam */ 1393193240Ssam nqueued = 0; 1394193240Ssam mwl_hal_txstart(sc->sc_mh, 0/*XXX*/); 1395193240Ssam } 1396193240Ssam } 1397193240Ssam if (nqueued) { 1398193240Ssam /* 1399193240Ssam * NB: We don't need to lock against tx done because 1400193240Ssam * this just prods the firmware to check the transmit 1401193240Ssam * descriptors. The firmware will also start fetching 1402193240Ssam * descriptors by itself if it notices new ones are 1403193240Ssam * present when it goes to deliver a tx done interrupt 1404193240Ssam * to the host. So if we race with tx done processing 1405193240Ssam * it's ok. Delivering the kick here rather than in 1406193240Ssam * mwl_tx_start is an optimization to avoid poking the 1407193240Ssam * firmware for each packet. 1408193240Ssam * 1409193240Ssam * NB: the queue id isn't used so 0 is ok. 1410193240Ssam */ 1411193240Ssam mwl_hal_txstart(sc->sc_mh, 0/*XXX*/); 1412193240Ssam } 1413193240Ssam} 1414193240Ssam 1415193240Ssamstatic int 1416193240Ssammwl_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1417193240Ssam const struct ieee80211_bpf_params *params) 1418193240Ssam{ 1419193240Ssam struct ieee80211com *ic = ni->ni_ic; 1420287197Sglebius struct mwl_softc *sc = ic->ic_softc; 1421193240Ssam struct mwl_txbuf *bf; 1422193240Ssam struct mwl_txq *txq; 1423193240Ssam 1424287197Sglebius if (!sc->sc_running || sc->sc_invalid) { 1425193240Ssam m_freem(m); 1426193240Ssam return ENETDOWN; 1427193240Ssam } 1428193240Ssam /* 1429193240Ssam * Grab a TX buffer and associated resources. 1430193240Ssam * Note that we depend on the classification 1431193240Ssam * by the 802.11 layer to get to the right h/w 1432193240Ssam * queue. Management frames must ALWAYS go on 1433193240Ssam * queue 1 but we cannot just force that here 1434193240Ssam * because we may receive non-mgt frames. 1435193240Ssam */ 1436193240Ssam txq = sc->sc_ac2q[M_WME_GETAC(m)]; 1437193240Ssam bf = mwl_gettxbuf(sc, txq); 1438193240Ssam if (bf == NULL) { 1439193240Ssam sc->sc_stats.mst_tx_qstop++; 1440193240Ssam m_freem(m); 1441193240Ssam return ENOBUFS; 1442193240Ssam } 1443193240Ssam /* 1444193240Ssam * Pass the frame to the h/w for transmission. 1445193240Ssam */ 1446193240Ssam if (mwl_tx_start(sc, ni, bf, m)) { 1447193240Ssam mwl_puttxbuf_head(txq, bf); 1448193240Ssam 1449193240Ssam return EIO; /* XXX */ 1450193240Ssam } 1451193240Ssam /* 1452193240Ssam * NB: We don't need to lock against tx done because 1453193240Ssam * this just prods the firmware to check the transmit 1454193240Ssam * descriptors. The firmware will also start fetching 1455193240Ssam * descriptors by itself if it notices new ones are 1456193240Ssam * present when it goes to deliver a tx done interrupt 1457193240Ssam * to the host. So if we race with tx done processing 1458193240Ssam * it's ok. Delivering the kick here rather than in 1459193240Ssam * mwl_tx_start is an optimization to avoid poking the 1460193240Ssam * firmware for each packet. 1461193240Ssam * 1462193240Ssam * NB: the queue id isn't used so 0 is ok. 1463193240Ssam */ 1464193240Ssam mwl_hal_txstart(sc->sc_mh, 0/*XXX*/); 1465193240Ssam return 0; 1466193240Ssam} 1467193240Ssam 1468193240Ssamstatic int 1469193240Ssammwl_media_change(struct ifnet *ifp) 1470193240Ssam{ 1471193240Ssam struct ieee80211vap *vap = ifp->if_softc; 1472193240Ssam int error; 1473193240Ssam 1474193240Ssam error = ieee80211_media_change(ifp); 1475193240Ssam /* NB: only the fixed rate can change and that doesn't need a reset */ 1476193240Ssam if (error == ENETRESET) { 1477193240Ssam mwl_setrates(vap); 1478193240Ssam error = 0; 1479193240Ssam } 1480193240Ssam return error; 1481193240Ssam} 1482193240Ssam 1483193240Ssam#ifdef MWL_DEBUG 1484193240Ssamstatic void 1485193240Ssammwl_keyprint(struct mwl_softc *sc, const char *tag, 1486193240Ssam const MWL_HAL_KEYVAL *hk, const uint8_t mac[IEEE80211_ADDR_LEN]) 1487193240Ssam{ 1488193240Ssam static const char *ciphers[] = { 1489193240Ssam "WEP", 1490193240Ssam "TKIP", 1491193240Ssam "AES-CCM", 1492193240Ssam }; 1493193240Ssam int i, n; 1494193240Ssam 1495193240Ssam printf("%s: [%u] %-7s", tag, hk->keyIndex, ciphers[hk->keyTypeId]); 1496193240Ssam for (i = 0, n = hk->keyLen; i < n; i++) 1497193240Ssam printf(" %02x", hk->key.aes[i]); 1498193240Ssam printf(" mac %s", ether_sprintf(mac)); 1499193240Ssam if (hk->keyTypeId == KEY_TYPE_ID_TKIP) { 1500193240Ssam printf(" %s", "rxmic"); 1501193240Ssam for (i = 0; i < sizeof(hk->key.tkip.rxMic); i++) 1502193240Ssam printf(" %02x", hk->key.tkip.rxMic[i]); 1503193240Ssam printf(" txmic"); 1504193240Ssam for (i = 0; i < sizeof(hk->key.tkip.txMic); i++) 1505193240Ssam printf(" %02x", hk->key.tkip.txMic[i]); 1506193240Ssam } 1507193240Ssam printf(" flags 0x%x\n", hk->keyFlags); 1508193240Ssam} 1509193240Ssam#endif 1510193240Ssam 1511193240Ssam/* 1512193240Ssam * Allocate a key cache slot for a unicast key. The 1513193240Ssam * firmware handles key allocation and every station is 1514193240Ssam * guaranteed key space so we are always successful. 1515193240Ssam */ 1516193240Ssamstatic int 1517193240Ssammwl_key_alloc(struct ieee80211vap *vap, struct ieee80211_key *k, 1518193240Ssam ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix) 1519193240Ssam{ 1520287197Sglebius struct mwl_softc *sc = vap->iv_ic->ic_softc; 1521193240Ssam 1522193240Ssam if (k->wk_keyix != IEEE80211_KEYIX_NONE || 1523193240Ssam (k->wk_flags & IEEE80211_KEY_GROUP)) { 1524193240Ssam if (!(&vap->iv_nw_keys[0] <= k && 1525193240Ssam k < &vap->iv_nw_keys[IEEE80211_WEP_NKID])) { 1526193240Ssam /* should not happen */ 1527193240Ssam DPRINTF(sc, MWL_DEBUG_KEYCACHE, 1528193240Ssam "%s: bogus group key\n", __func__); 1529193240Ssam return 0; 1530193240Ssam } 1531193240Ssam /* give the caller what they requested */ 1532193240Ssam *keyix = *rxkeyix = k - vap->iv_nw_keys; 1533193240Ssam } else { 1534193240Ssam /* 1535193240Ssam * Firmware handles key allocation. 1536193240Ssam */ 1537193240Ssam *keyix = *rxkeyix = 0; 1538193240Ssam } 1539193240Ssam return 1; 1540193240Ssam} 1541193240Ssam 1542193240Ssam/* 1543193240Ssam * Delete a key entry allocated by mwl_key_alloc. 1544193240Ssam */ 1545193240Ssamstatic int 1546193240Ssammwl_key_delete(struct ieee80211vap *vap, const struct ieee80211_key *k) 1547193240Ssam{ 1548287197Sglebius struct mwl_softc *sc = vap->iv_ic->ic_softc; 1549193240Ssam struct mwl_hal_vap *hvap = MWL_VAP(vap)->mv_hvap; 1550193240Ssam MWL_HAL_KEYVAL hk; 1551193240Ssam const uint8_t bcastaddr[IEEE80211_ADDR_LEN] = 1552193240Ssam { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 1553193240Ssam 1554193240Ssam if (hvap == NULL) { 1555193240Ssam if (vap->iv_opmode != IEEE80211_M_WDS) { 1556193240Ssam /* XXX monitor mode? */ 1557193240Ssam DPRINTF(sc, MWL_DEBUG_KEYCACHE, 1558193240Ssam "%s: no hvap for opmode %d\n", __func__, 1559193240Ssam vap->iv_opmode); 1560193240Ssam return 0; 1561193240Ssam } 1562193240Ssam hvap = MWL_VAP(vap)->mv_ap_hvap; 1563193240Ssam } 1564193240Ssam 1565193240Ssam DPRINTF(sc, MWL_DEBUG_KEYCACHE, "%s: delete key %u\n", 1566193240Ssam __func__, k->wk_keyix); 1567193240Ssam 1568193240Ssam memset(&hk, 0, sizeof(hk)); 1569193240Ssam hk.keyIndex = k->wk_keyix; 1570193240Ssam switch (k->wk_cipher->ic_cipher) { 1571193240Ssam case IEEE80211_CIPHER_WEP: 1572193240Ssam hk.keyTypeId = KEY_TYPE_ID_WEP; 1573193240Ssam break; 1574193240Ssam case IEEE80211_CIPHER_TKIP: 1575193240Ssam hk.keyTypeId = KEY_TYPE_ID_TKIP; 1576193240Ssam break; 1577193240Ssam case IEEE80211_CIPHER_AES_CCM: 1578193240Ssam hk.keyTypeId = KEY_TYPE_ID_AES; 1579193240Ssam break; 1580193240Ssam default: 1581193240Ssam /* XXX should not happen */ 1582193240Ssam DPRINTF(sc, MWL_DEBUG_KEYCACHE, "%s: unknown cipher %d\n", 1583193240Ssam __func__, k->wk_cipher->ic_cipher); 1584193240Ssam return 0; 1585193240Ssam } 1586193240Ssam return (mwl_hal_keyreset(hvap, &hk, bcastaddr) == 0); /*XXX*/ 1587193240Ssam} 1588193240Ssam 1589193240Ssamstatic __inline int 1590193240Ssamaddgroupflags(MWL_HAL_KEYVAL *hk, const struct ieee80211_key *k) 1591193240Ssam{ 1592193240Ssam if (k->wk_flags & IEEE80211_KEY_GROUP) { 1593193240Ssam if (k->wk_flags & IEEE80211_KEY_XMIT) 1594193240Ssam hk->keyFlags |= KEY_FLAG_TXGROUPKEY; 1595193240Ssam if (k->wk_flags & IEEE80211_KEY_RECV) 1596193240Ssam hk->keyFlags |= KEY_FLAG_RXGROUPKEY; 1597193240Ssam return 1; 1598193240Ssam } else 1599193240Ssam return 0; 1600193240Ssam} 1601193240Ssam 1602193240Ssam/* 1603193240Ssam * Set the key cache contents for the specified key. Key cache 1604193240Ssam * slot(s) must already have been allocated by mwl_key_alloc. 1605193240Ssam */ 1606193240Ssamstatic int 1607288635Sadrianmwl_key_set(struct ieee80211vap *vap, const struct ieee80211_key *k) 1608288635Sadrian{ 1609288635Sadrian return (_mwl_key_set(vap, k, k->wk_macaddr)); 1610288635Sadrian} 1611288635Sadrian 1612288635Sadrianstatic int 1613288635Sadrian_mwl_key_set(struct ieee80211vap *vap, const struct ieee80211_key *k, 1614193240Ssam const uint8_t mac[IEEE80211_ADDR_LEN]) 1615193240Ssam{ 1616193240Ssam#define GRPXMIT (IEEE80211_KEY_XMIT | IEEE80211_KEY_GROUP) 1617193240Ssam/* NB: static wep keys are marked GROUP+tx/rx; GTK will be tx or rx */ 1618193240Ssam#define IEEE80211_IS_STATICKEY(k) \ 1619193240Ssam (((k)->wk_flags & (GRPXMIT|IEEE80211_KEY_RECV)) == \ 1620193240Ssam (GRPXMIT|IEEE80211_KEY_RECV)) 1621287197Sglebius struct mwl_softc *sc = vap->iv_ic->ic_softc; 1622193240Ssam struct mwl_hal_vap *hvap = MWL_VAP(vap)->mv_hvap; 1623193240Ssam const struct ieee80211_cipher *cip = k->wk_cipher; 1624193240Ssam const uint8_t *macaddr; 1625193240Ssam MWL_HAL_KEYVAL hk; 1626193240Ssam 1627193240Ssam KASSERT((k->wk_flags & IEEE80211_KEY_SWCRYPT) == 0, 1628193240Ssam ("s/w crypto set?")); 1629193240Ssam 1630193240Ssam if (hvap == NULL) { 1631193240Ssam if (vap->iv_opmode != IEEE80211_M_WDS) { 1632193240Ssam /* XXX monitor mode? */ 1633193240Ssam DPRINTF(sc, MWL_DEBUG_KEYCACHE, 1634193240Ssam "%s: no hvap for opmode %d\n", __func__, 1635193240Ssam vap->iv_opmode); 1636193240Ssam return 0; 1637193240Ssam } 1638193240Ssam hvap = MWL_VAP(vap)->mv_ap_hvap; 1639193240Ssam } 1640193240Ssam memset(&hk, 0, sizeof(hk)); 1641193240Ssam hk.keyIndex = k->wk_keyix; 1642193240Ssam switch (cip->ic_cipher) { 1643193240Ssam case IEEE80211_CIPHER_WEP: 1644193240Ssam hk.keyTypeId = KEY_TYPE_ID_WEP; 1645193240Ssam hk.keyLen = k->wk_keylen; 1646193240Ssam if (k->wk_keyix == vap->iv_def_txkey) 1647193240Ssam hk.keyFlags = KEY_FLAG_WEP_TXKEY; 1648193240Ssam if (!IEEE80211_IS_STATICKEY(k)) { 1649193240Ssam /* NB: WEP is never used for the PTK */ 1650193240Ssam (void) addgroupflags(&hk, k); 1651193240Ssam } 1652193240Ssam break; 1653193240Ssam case IEEE80211_CIPHER_TKIP: 1654193240Ssam hk.keyTypeId = KEY_TYPE_ID_TKIP; 1655193240Ssam hk.key.tkip.tsc.high = (uint32_t)(k->wk_keytsc >> 16); 1656193240Ssam hk.key.tkip.tsc.low = (uint16_t)k->wk_keytsc; 1657193240Ssam hk.keyFlags = KEY_FLAG_TSC_VALID | KEY_FLAG_MICKEY_VALID; 1658193240Ssam hk.keyLen = k->wk_keylen + IEEE80211_MICBUF_SIZE; 1659193240Ssam if (!addgroupflags(&hk, k)) 1660193240Ssam hk.keyFlags |= KEY_FLAG_PAIRWISE; 1661193240Ssam break; 1662193240Ssam case IEEE80211_CIPHER_AES_CCM: 1663193240Ssam hk.keyTypeId = KEY_TYPE_ID_AES; 1664193240Ssam hk.keyLen = k->wk_keylen; 1665193240Ssam if (!addgroupflags(&hk, k)) 1666193240Ssam hk.keyFlags |= KEY_FLAG_PAIRWISE; 1667193240Ssam break; 1668193240Ssam default: 1669193240Ssam /* XXX should not happen */ 1670193240Ssam DPRINTF(sc, MWL_DEBUG_KEYCACHE, "%s: unknown cipher %d\n", 1671193240Ssam __func__, k->wk_cipher->ic_cipher); 1672193240Ssam return 0; 1673193240Ssam } 1674193240Ssam /* 1675193240Ssam * NB: tkip mic keys get copied here too; the layout 1676193240Ssam * just happens to match that in ieee80211_key. 1677193240Ssam */ 1678193240Ssam memcpy(hk.key.aes, k->wk_key, hk.keyLen); 1679193240Ssam 1680193240Ssam /* 1681193240Ssam * Locate address of sta db entry for writing key; 1682193240Ssam * the convention unfortunately is somewhat different 1683193240Ssam * than how net80211, hostapd, and wpa_supplicant think. 1684193240Ssam */ 1685193240Ssam if (vap->iv_opmode == IEEE80211_M_STA) { 1686193240Ssam /* 1687193240Ssam * NB: keys plumbed before the sta reaches AUTH state 1688193240Ssam * will be discarded or written to the wrong sta db 1689193240Ssam * entry because iv_bss is meaningless. This is ok 1690193240Ssam * (right now) because we handle deferred plumbing of 1691193240Ssam * WEP keys when the sta reaches AUTH state. 1692193240Ssam */ 1693193240Ssam macaddr = vap->iv_bss->ni_bssid; 1694196842Ssam if ((k->wk_flags & IEEE80211_KEY_GROUP) == 0) { 1695196842Ssam /* XXX plumb to local sta db too for static key wep */ 1696196842Ssam mwl_hal_keyset(hvap, &hk, vap->iv_myaddr); 1697196842Ssam } 1698193240Ssam } else if (vap->iv_opmode == IEEE80211_M_WDS && 1699193240Ssam vap->iv_state != IEEE80211_S_RUN) { 1700193240Ssam /* 1701193240Ssam * Prior to RUN state a WDS vap will not it's BSS node 1702193240Ssam * setup so we will plumb the key to the wrong mac 1703193240Ssam * address (it'll be our local address). Workaround 1704193240Ssam * this for the moment by grabbing the correct address. 1705193240Ssam */ 1706193240Ssam macaddr = vap->iv_des_bssid; 1707193240Ssam } else if ((k->wk_flags & GRPXMIT) == GRPXMIT) 1708193240Ssam macaddr = vap->iv_myaddr; 1709193240Ssam else 1710193240Ssam macaddr = mac; 1711193240Ssam KEYPRINTF(sc, &hk, macaddr); 1712193240Ssam return (mwl_hal_keyset(hvap, &hk, macaddr) == 0); 1713193240Ssam#undef IEEE80211_IS_STATICKEY 1714193240Ssam#undef GRPXMIT 1715193240Ssam} 1716193240Ssam 1717193240Ssam/* 1718193240Ssam * Set the multicast filter contents into the hardware. 1719193240Ssam * XXX f/w has no support; just defer to the os. 1720193240Ssam */ 1721193240Ssamstatic void 1722193240Ssammwl_setmcastfilter(struct mwl_softc *sc) 1723193240Ssam{ 1724193240Ssam#if 0 1725193240Ssam struct ether_multi *enm; 1726193240Ssam struct ether_multistep estep; 1727193240Ssam uint8_t macs[IEEE80211_ADDR_LEN*MWL_HAL_MCAST_MAX];/* XXX stack use */ 1728193240Ssam uint8_t *mp; 1729193240Ssam int nmc; 1730193240Ssam 1731193240Ssam mp = macs; 1732193240Ssam nmc = 0; 1733193240Ssam ETHER_FIRST_MULTI(estep, &sc->sc_ec, enm); 1734193240Ssam while (enm != NULL) { 1735193240Ssam /* XXX Punt on ranges. */ 1736193240Ssam if (nmc == MWL_HAL_MCAST_MAX || 1737193240Ssam !IEEE80211_ADDR_EQ(enm->enm_addrlo, enm->enm_addrhi)) { 1738193240Ssam ifp->if_flags |= IFF_ALLMULTI; 1739193240Ssam return; 1740193240Ssam } 1741193240Ssam IEEE80211_ADDR_COPY(mp, enm->enm_addrlo); 1742193240Ssam mp += IEEE80211_ADDR_LEN, nmc++; 1743193240Ssam ETHER_NEXT_MULTI(estep, enm); 1744193240Ssam } 1745193240Ssam ifp->if_flags &= ~IFF_ALLMULTI; 1746193240Ssam mwl_hal_setmcast(sc->sc_mh, nmc, macs); 1747193240Ssam#endif 1748193240Ssam} 1749193240Ssam 1750193240Ssamstatic int 1751193240Ssammwl_mode_init(struct mwl_softc *sc) 1752193240Ssam{ 1753287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 1754193240Ssam struct mwl_hal *mh = sc->sc_mh; 1755193240Ssam 1756298389Savos mwl_hal_setpromisc(mh, ic->ic_promisc > 0); 1757193240Ssam mwl_setmcastfilter(sc); 1758193240Ssam 1759193240Ssam return 0; 1760193240Ssam} 1761193240Ssam 1762193240Ssam/* 1763193240Ssam * Callback from the 802.11 layer after a multicast state change. 1764193240Ssam */ 1765193240Ssamstatic void 1766283540Sglebiusmwl_update_mcast(struct ieee80211com *ic) 1767193240Ssam{ 1768283540Sglebius struct mwl_softc *sc = ic->ic_softc; 1769193240Ssam 1770193240Ssam mwl_setmcastfilter(sc); 1771193240Ssam} 1772193240Ssam 1773193240Ssam/* 1774193240Ssam * Callback from the 802.11 layer after a promiscuous mode change. 1775193240Ssam * Note this interface does not check the operating mode as this 1776193240Ssam * is an internal callback and we are expected to honor the current 1777193240Ssam * state (e.g. this is used for setting the interface in promiscuous 1778193240Ssam * mode when operating in hostap mode to do ACS). 1779193240Ssam */ 1780193240Ssamstatic void 1781283540Sglebiusmwl_update_promisc(struct ieee80211com *ic) 1782193240Ssam{ 1783283540Sglebius struct mwl_softc *sc = ic->ic_softc; 1784193240Ssam 1785287197Sglebius mwl_hal_setpromisc(sc->sc_mh, ic->ic_promisc > 0); 1786193240Ssam} 1787193240Ssam 1788193240Ssam/* 1789193240Ssam * Callback from the 802.11 layer to update the slot time 1790193240Ssam * based on the current setting. We use it to notify the 1791193240Ssam * firmware of ERP changes and the f/w takes care of things 1792193240Ssam * like slot time and preamble. 1793193240Ssam */ 1794193240Ssamstatic void 1795283540Sglebiusmwl_updateslot(struct ieee80211com *ic) 1796193240Ssam{ 1797283540Sglebius struct mwl_softc *sc = ic->ic_softc; 1798193240Ssam struct mwl_hal *mh = sc->sc_mh; 1799193240Ssam int prot; 1800193240Ssam 1801193240Ssam /* NB: can be called early; suppress needless cmds */ 1802287197Sglebius if (!sc->sc_running) 1803193240Ssam return; 1804193240Ssam 1805193240Ssam /* 1806193240Ssam * Calculate the ERP flags. The firwmare will use 1807193240Ssam * this to carry out the appropriate measures. 1808193240Ssam */ 1809193240Ssam prot = 0; 1810193240Ssam if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) { 1811193240Ssam if ((ic->ic_flags & IEEE80211_F_SHSLOT) == 0) 1812193240Ssam prot |= IEEE80211_ERP_NON_ERP_PRESENT; 1813193240Ssam if (ic->ic_flags & IEEE80211_F_USEPROT) 1814193240Ssam prot |= IEEE80211_ERP_USE_PROTECTION; 1815193240Ssam if (ic->ic_flags & IEEE80211_F_USEBARKER) 1816193240Ssam prot |= IEEE80211_ERP_LONG_PREAMBLE; 1817193240Ssam } 1818193240Ssam 1819193240Ssam DPRINTF(sc, MWL_DEBUG_RESET, 1820193240Ssam "%s: chan %u MHz/flags 0x%x %s slot, (prot 0x%x ic_flags 0x%x)\n", 1821193240Ssam __func__, ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags, 1822193240Ssam ic->ic_flags & IEEE80211_F_SHSLOT ? "short" : "long", prot, 1823193240Ssam ic->ic_flags); 1824193240Ssam 1825193240Ssam mwl_hal_setgprot(mh, prot); 1826193240Ssam} 1827193240Ssam 1828193240Ssam/* 1829193240Ssam * Setup the beacon frame. 1830193240Ssam */ 1831193240Ssamstatic int 1832193240Ssammwl_beacon_setup(struct ieee80211vap *vap) 1833193240Ssam{ 1834193240Ssam struct mwl_hal_vap *hvap = MWL_VAP(vap)->mv_hvap; 1835193240Ssam struct ieee80211_node *ni = vap->iv_bss; 1836193240Ssam struct mbuf *m; 1837193240Ssam 1838288636Sadrian m = ieee80211_beacon_alloc(ni); 1839193240Ssam if (m == NULL) 1840193240Ssam return ENOBUFS; 1841193240Ssam mwl_hal_setbeacon(hvap, mtod(m, const void *), m->m_len); 1842193240Ssam m_free(m); 1843193240Ssam 1844193240Ssam return 0; 1845193240Ssam} 1846193240Ssam 1847193240Ssam/* 1848193240Ssam * Update the beacon frame in response to a change. 1849193240Ssam */ 1850193240Ssamstatic void 1851193240Ssammwl_beacon_update(struct ieee80211vap *vap, int item) 1852193240Ssam{ 1853193240Ssam struct mwl_hal_vap *hvap = MWL_VAP(vap)->mv_hvap; 1854193240Ssam struct ieee80211com *ic = vap->iv_ic; 1855193240Ssam 1856193240Ssam KASSERT(hvap != NULL, ("no beacon")); 1857193240Ssam switch (item) { 1858193240Ssam case IEEE80211_BEACON_ERP: 1859283540Sglebius mwl_updateslot(ic); 1860193240Ssam break; 1861193240Ssam case IEEE80211_BEACON_HTINFO: 1862193240Ssam mwl_hal_setnprotmode(hvap, 1863193240Ssam MS(ic->ic_curhtprotmode, IEEE80211_HTINFO_OPMODE)); 1864193240Ssam break; 1865193240Ssam case IEEE80211_BEACON_CAPS: 1866193240Ssam case IEEE80211_BEACON_WME: 1867193240Ssam case IEEE80211_BEACON_APPIE: 1868193240Ssam case IEEE80211_BEACON_CSA: 1869193240Ssam break; 1870193240Ssam case IEEE80211_BEACON_TIM: 1871193240Ssam /* NB: firmware always forms TIM */ 1872193240Ssam return; 1873193240Ssam } 1874193240Ssam /* XXX retain beacon frame and update */ 1875193240Ssam mwl_beacon_setup(vap); 1876193240Ssam} 1877193240Ssam 1878193240Ssamstatic void 1879193240Ssammwl_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1880193240Ssam{ 1881193240Ssam bus_addr_t *paddr = (bus_addr_t*) arg; 1882193240Ssam KASSERT(error == 0, ("error %u on bus_dma callback", error)); 1883193240Ssam *paddr = segs->ds_addr; 1884193240Ssam} 1885193240Ssam 1886193240Ssam#ifdef MWL_HOST_PS_SUPPORT 1887193240Ssam/* 1888193240Ssam * Handle power save station occupancy changes. 1889193240Ssam */ 1890193240Ssamstatic void 1891193240Ssammwl_update_ps(struct ieee80211vap *vap, int nsta) 1892193240Ssam{ 1893193240Ssam struct mwl_vap *mvp = MWL_VAP(vap); 1894193240Ssam 1895193240Ssam if (nsta == 0 || mvp->mv_last_ps_sta == 0) 1896193240Ssam mwl_hal_setpowersave_bss(mvp->mv_hvap, nsta); 1897193240Ssam mvp->mv_last_ps_sta = nsta; 1898193240Ssam} 1899193240Ssam 1900193240Ssam/* 1901193240Ssam * Handle associated station power save state changes. 1902193240Ssam */ 1903193240Ssamstatic int 1904193240Ssammwl_set_tim(struct ieee80211_node *ni, int set) 1905193240Ssam{ 1906193240Ssam struct ieee80211vap *vap = ni->ni_vap; 1907193240Ssam struct mwl_vap *mvp = MWL_VAP(vap); 1908193240Ssam 1909193240Ssam if (mvp->mv_set_tim(ni, set)) { /* NB: state change */ 1910193240Ssam mwl_hal_setpowersave_sta(mvp->mv_hvap, 1911193240Ssam IEEE80211_AID(ni->ni_associd), set); 1912193240Ssam return 1; 1913193240Ssam } else 1914193240Ssam return 0; 1915193240Ssam} 1916193240Ssam#endif /* MWL_HOST_PS_SUPPORT */ 1917193240Ssam 1918193240Ssamstatic int 1919193240Ssammwl_desc_setup(struct mwl_softc *sc, const char *name, 1920193240Ssam struct mwl_descdma *dd, 1921193240Ssam int nbuf, size_t bufsize, int ndesc, size_t descsize) 1922193240Ssam{ 1923193240Ssam uint8_t *ds; 1924193240Ssam int error; 1925193240Ssam 1926193240Ssam DPRINTF(sc, MWL_DEBUG_RESET, 1927193240Ssam "%s: %s DMA: %u bufs (%ju) %u desc/buf (%ju)\n", 1928193240Ssam __func__, name, nbuf, (uintmax_t) bufsize, 1929193240Ssam ndesc, (uintmax_t) descsize); 1930193240Ssam 1931193240Ssam dd->dd_name = name; 1932193240Ssam dd->dd_desc_len = nbuf * ndesc * descsize; 1933193240Ssam 1934193240Ssam /* 1935193240Ssam * Setup DMA descriptor area. 1936193240Ssam */ 1937193240Ssam error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */ 1938193240Ssam PAGE_SIZE, 0, /* alignment, bounds */ 1939193240Ssam BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1940193240Ssam BUS_SPACE_MAXADDR, /* highaddr */ 1941193240Ssam NULL, NULL, /* filter, filterarg */ 1942193240Ssam dd->dd_desc_len, /* maxsize */ 1943193240Ssam 1, /* nsegments */ 1944193240Ssam dd->dd_desc_len, /* maxsegsize */ 1945193240Ssam BUS_DMA_ALLOCNOW, /* flags */ 1946193240Ssam NULL, /* lockfunc */ 1947193240Ssam NULL, /* lockarg */ 1948193240Ssam &dd->dd_dmat); 1949193240Ssam if (error != 0) { 1950287197Sglebius device_printf(sc->sc_dev, "cannot allocate %s DMA tag\n", dd->dd_name); 1951193240Ssam return error; 1952193240Ssam } 1953193240Ssam 1954193240Ssam /* allocate descriptors */ 1955193240Ssam error = bus_dmamem_alloc(dd->dd_dmat, (void**) &dd->dd_desc, 1956193240Ssam BUS_DMA_NOWAIT | BUS_DMA_COHERENT, 1957193240Ssam &dd->dd_dmamap); 1958193240Ssam if (error != 0) { 1959287197Sglebius device_printf(sc->sc_dev, "unable to alloc memory for %u %s descriptors, " 1960193240Ssam "error %u\n", nbuf * ndesc, dd->dd_name, error); 1961193240Ssam goto fail1; 1962193240Ssam } 1963193240Ssam 1964193240Ssam error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap, 1965193240Ssam dd->dd_desc, dd->dd_desc_len, 1966193240Ssam mwl_load_cb, &dd->dd_desc_paddr, 1967193240Ssam BUS_DMA_NOWAIT); 1968193240Ssam if (error != 0) { 1969287197Sglebius device_printf(sc->sc_dev, "unable to map %s descriptors, error %u\n", 1970193240Ssam dd->dd_name, error); 1971193240Ssam goto fail2; 1972193240Ssam } 1973193240Ssam 1974193240Ssam ds = dd->dd_desc; 1975193240Ssam memset(ds, 0, dd->dd_desc_len); 1976278532Smarius DPRINTF(sc, MWL_DEBUG_RESET, 1977278532Smarius "%s: %s DMA map: %p (%lu) -> 0x%jx (%lu)\n", 1978193240Ssam __func__, dd->dd_name, ds, (u_long) dd->dd_desc_len, 1979278532Smarius (uintmax_t) dd->dd_desc_paddr, /*XXX*/ (u_long) dd->dd_desc_len); 1980193240Ssam 1981193240Ssam return 0; 1982193240Ssamfail2: 1983193240Ssam bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap); 1984193240Ssamfail1: 1985193240Ssam bus_dma_tag_destroy(dd->dd_dmat); 1986193240Ssam memset(dd, 0, sizeof(*dd)); 1987193240Ssam return error; 1988193240Ssam#undef DS2PHYS 1989193240Ssam} 1990193240Ssam 1991193240Ssamstatic void 1992193240Ssammwl_desc_cleanup(struct mwl_softc *sc, struct mwl_descdma *dd) 1993193240Ssam{ 1994193240Ssam bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 1995193240Ssam bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap); 1996193240Ssam bus_dma_tag_destroy(dd->dd_dmat); 1997193240Ssam 1998193240Ssam memset(dd, 0, sizeof(*dd)); 1999193240Ssam} 2000193240Ssam 2001193240Ssam/* 2002193240Ssam * Construct a tx q's free list. The order of entries on 2003193240Ssam * the list must reflect the physical layout of tx descriptors 2004193240Ssam * because the firmware pre-fetches descriptors. 2005193240Ssam * 2006193240Ssam * XXX might be better to use indices into the buffer array. 2007193240Ssam */ 2008193240Ssamstatic void 2009193240Ssammwl_txq_reset(struct mwl_softc *sc, struct mwl_txq *txq) 2010193240Ssam{ 2011193240Ssam struct mwl_txbuf *bf; 2012193240Ssam int i; 2013193240Ssam 2014193240Ssam bf = txq->dma.dd_bufptr; 2015193240Ssam STAILQ_INIT(&txq->free); 2016193240Ssam for (i = 0; i < mwl_txbuf; i++, bf++) 2017193240Ssam STAILQ_INSERT_TAIL(&txq->free, bf, bf_list); 2018193240Ssam txq->nfree = i; 2019193240Ssam} 2020193240Ssam 2021193240Ssam#define DS2PHYS(_dd, _ds) \ 2022193240Ssam ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) 2023193240Ssam 2024193240Ssamstatic int 2025193240Ssammwl_txdma_setup(struct mwl_softc *sc, struct mwl_txq *txq) 2026193240Ssam{ 2027193240Ssam int error, bsize, i; 2028193240Ssam struct mwl_txbuf *bf; 2029193240Ssam struct mwl_txdesc *ds; 2030193240Ssam 2031193240Ssam error = mwl_desc_setup(sc, "tx", &txq->dma, 2032193240Ssam mwl_txbuf, sizeof(struct mwl_txbuf), 2033193240Ssam MWL_TXDESC, sizeof(struct mwl_txdesc)); 2034193240Ssam if (error != 0) 2035193240Ssam return error; 2036193240Ssam 2037193240Ssam /* allocate and setup tx buffers */ 2038193240Ssam bsize = mwl_txbuf * sizeof(struct mwl_txbuf); 2039193240Ssam bf = malloc(bsize, M_MWLDEV, M_NOWAIT | M_ZERO); 2040193240Ssam if (bf == NULL) { 2041287197Sglebius device_printf(sc->sc_dev, "malloc of %u tx buffers failed\n", 2042193240Ssam mwl_txbuf); 2043193240Ssam return ENOMEM; 2044193240Ssam } 2045193240Ssam txq->dma.dd_bufptr = bf; 2046193240Ssam 2047193240Ssam ds = txq->dma.dd_desc; 2048193240Ssam for (i = 0; i < mwl_txbuf; i++, bf++, ds += MWL_TXDESC) { 2049193240Ssam bf->bf_desc = ds; 2050193240Ssam bf->bf_daddr = DS2PHYS(&txq->dma, ds); 2051193240Ssam error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, 2052193240Ssam &bf->bf_dmamap); 2053193240Ssam if (error != 0) { 2054287197Sglebius device_printf(sc->sc_dev, "unable to create dmamap for tx " 2055193240Ssam "buffer %u, error %u\n", i, error); 2056193240Ssam return error; 2057193240Ssam } 2058193240Ssam } 2059193240Ssam mwl_txq_reset(sc, txq); 2060193240Ssam return 0; 2061193240Ssam} 2062193240Ssam 2063193240Ssamstatic void 2064193240Ssammwl_txdma_cleanup(struct mwl_softc *sc, struct mwl_txq *txq) 2065193240Ssam{ 2066193240Ssam struct mwl_txbuf *bf; 2067193240Ssam int i; 2068193240Ssam 2069193240Ssam bf = txq->dma.dd_bufptr; 2070193240Ssam for (i = 0; i < mwl_txbuf; i++, bf++) { 2071193240Ssam KASSERT(bf->bf_m == NULL, ("mbuf on free list")); 2072193240Ssam KASSERT(bf->bf_node == NULL, ("node on free list")); 2073193240Ssam if (bf->bf_dmamap != NULL) 2074193240Ssam bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 2075193240Ssam } 2076193240Ssam STAILQ_INIT(&txq->free); 2077193240Ssam txq->nfree = 0; 2078193240Ssam if (txq->dma.dd_bufptr != NULL) { 2079193240Ssam free(txq->dma.dd_bufptr, M_MWLDEV); 2080193240Ssam txq->dma.dd_bufptr = NULL; 2081193240Ssam } 2082193240Ssam if (txq->dma.dd_desc_len != 0) 2083193240Ssam mwl_desc_cleanup(sc, &txq->dma); 2084193240Ssam} 2085193240Ssam 2086193240Ssamstatic int 2087193240Ssammwl_rxdma_setup(struct mwl_softc *sc) 2088193240Ssam{ 2089193240Ssam int error, jumbosize, bsize, i; 2090193240Ssam struct mwl_rxbuf *bf; 2091193240Ssam struct mwl_jumbo *rbuf; 2092193240Ssam struct mwl_rxdesc *ds; 2093193240Ssam caddr_t data; 2094193240Ssam 2095193240Ssam error = mwl_desc_setup(sc, "rx", &sc->sc_rxdma, 2096193240Ssam mwl_rxdesc, sizeof(struct mwl_rxbuf), 2097193240Ssam 1, sizeof(struct mwl_rxdesc)); 2098193240Ssam if (error != 0) 2099193240Ssam return error; 2100193240Ssam 2101193240Ssam /* 2102193240Ssam * Receive is done to a private pool of jumbo buffers. 2103193240Ssam * This allows us to attach to mbuf's and avoid re-mapping 2104193240Ssam * memory on each rx we post. We allocate a large chunk 2105193240Ssam * of memory and manage it in the driver. The mbuf free 2106193240Ssam * callback method is used to reclaim frames after sending 2107193240Ssam * them up the stack. By default we allocate 2x the number of 2108193240Ssam * rx descriptors configured so we have some slop to hold 2109193240Ssam * us while frames are processed. 2110193240Ssam */ 2111193240Ssam if (mwl_rxbuf < 2*mwl_rxdesc) { 2112287197Sglebius device_printf(sc->sc_dev, 2113193240Ssam "too few rx dma buffers (%d); increasing to %d\n", 2114193240Ssam mwl_rxbuf, 2*mwl_rxdesc); 2115193240Ssam mwl_rxbuf = 2*mwl_rxdesc; 2116193240Ssam } 2117193240Ssam jumbosize = roundup(MWL_AGGR_SIZE, PAGE_SIZE); 2118193240Ssam sc->sc_rxmemsize = mwl_rxbuf*jumbosize; 2119193240Ssam 2120193240Ssam error = bus_dma_tag_create(sc->sc_dmat, /* parent */ 2121193240Ssam PAGE_SIZE, 0, /* alignment, bounds */ 2122193240Ssam BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 2123193240Ssam BUS_SPACE_MAXADDR, /* highaddr */ 2124193240Ssam NULL, NULL, /* filter, filterarg */ 2125193240Ssam sc->sc_rxmemsize, /* maxsize */ 2126193240Ssam 1, /* nsegments */ 2127193240Ssam sc->sc_rxmemsize, /* maxsegsize */ 2128193240Ssam BUS_DMA_ALLOCNOW, /* flags */ 2129193240Ssam NULL, /* lockfunc */ 2130193240Ssam NULL, /* lockarg */ 2131193240Ssam &sc->sc_rxdmat); 2132193240Ssam if (error != 0) { 2133287197Sglebius device_printf(sc->sc_dev, "could not create rx DMA tag\n"); 2134193240Ssam return error; 2135193240Ssam } 2136193240Ssam 2137193240Ssam error = bus_dmamem_alloc(sc->sc_rxdmat, (void**) &sc->sc_rxmem, 2138193240Ssam BUS_DMA_NOWAIT | BUS_DMA_COHERENT, 2139193240Ssam &sc->sc_rxmap); 2140193240Ssam if (error != 0) { 2141287197Sglebius device_printf(sc->sc_dev, "could not alloc %ju bytes of rx DMA memory\n", 2142193240Ssam (uintmax_t) sc->sc_rxmemsize); 2143193240Ssam return error; 2144193240Ssam } 2145193240Ssam 2146193240Ssam error = bus_dmamap_load(sc->sc_rxdmat, sc->sc_rxmap, 2147193240Ssam sc->sc_rxmem, sc->sc_rxmemsize, 2148193240Ssam mwl_load_cb, &sc->sc_rxmem_paddr, 2149193240Ssam BUS_DMA_NOWAIT); 2150193240Ssam if (error != 0) { 2151287197Sglebius device_printf(sc->sc_dev, "could not load rx DMA map\n"); 2152193240Ssam return error; 2153193240Ssam } 2154193240Ssam 2155193240Ssam /* 2156193240Ssam * Allocate rx buffers and set them up. 2157193240Ssam */ 2158193240Ssam bsize = mwl_rxdesc * sizeof(struct mwl_rxbuf); 2159193240Ssam bf = malloc(bsize, M_MWLDEV, M_NOWAIT | M_ZERO); 2160193240Ssam if (bf == NULL) { 2161287197Sglebius device_printf(sc->sc_dev, "malloc of %u rx buffers failed\n", bsize); 2162193240Ssam return error; 2163193240Ssam } 2164193240Ssam sc->sc_rxdma.dd_bufptr = bf; 2165193240Ssam 2166193240Ssam STAILQ_INIT(&sc->sc_rxbuf); 2167193240Ssam ds = sc->sc_rxdma.dd_desc; 2168193240Ssam for (i = 0; i < mwl_rxdesc; i++, bf++, ds++) { 2169193240Ssam bf->bf_desc = ds; 2170193240Ssam bf->bf_daddr = DS2PHYS(&sc->sc_rxdma, ds); 2171193240Ssam /* pre-assign dma buffer */ 2172193240Ssam bf->bf_data = ((uint8_t *)sc->sc_rxmem) + (i*jumbosize); 2173193240Ssam /* NB: tail is intentional to preserve descriptor order */ 2174193240Ssam STAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 2175193240Ssam } 2176193240Ssam 2177193240Ssam /* 2178193240Ssam * Place remainder of dma memory buffers on the free list. 2179193240Ssam */ 2180193240Ssam SLIST_INIT(&sc->sc_rxfree); 2181193240Ssam for (; i < mwl_rxbuf; i++) { 2182193240Ssam data = ((uint8_t *)sc->sc_rxmem) + (i*jumbosize); 2183193240Ssam rbuf = MWL_JUMBO_DATA2BUF(data); 2184193240Ssam SLIST_INSERT_HEAD(&sc->sc_rxfree, rbuf, next); 2185193240Ssam sc->sc_nrxfree++; 2186193240Ssam } 2187193240Ssam return 0; 2188193240Ssam} 2189193240Ssam#undef DS2PHYS 2190193240Ssam 2191193240Ssamstatic void 2192193240Ssammwl_rxdma_cleanup(struct mwl_softc *sc) 2193193240Ssam{ 2194267340Sjhb if (sc->sc_rxmem_paddr != 0) { 2195193240Ssam bus_dmamap_unload(sc->sc_rxdmat, sc->sc_rxmap); 2196267340Sjhb sc->sc_rxmem_paddr = 0; 2197267340Sjhb } 2198193240Ssam if (sc->sc_rxmem != NULL) { 2199193240Ssam bus_dmamem_free(sc->sc_rxdmat, sc->sc_rxmem, sc->sc_rxmap); 2200193240Ssam sc->sc_rxmem = NULL; 2201193240Ssam } 2202193240Ssam if (sc->sc_rxdma.dd_bufptr != NULL) { 2203193240Ssam free(sc->sc_rxdma.dd_bufptr, M_MWLDEV); 2204193240Ssam sc->sc_rxdma.dd_bufptr = NULL; 2205193240Ssam } 2206193240Ssam if (sc->sc_rxdma.dd_desc_len != 0) 2207193240Ssam mwl_desc_cleanup(sc, &sc->sc_rxdma); 2208193240Ssam} 2209193240Ssam 2210193240Ssamstatic int 2211193240Ssammwl_dma_setup(struct mwl_softc *sc) 2212193240Ssam{ 2213193240Ssam int error, i; 2214193240Ssam 2215193240Ssam error = mwl_rxdma_setup(sc); 2216197307Srpaulo if (error != 0) { 2217197307Srpaulo mwl_rxdma_cleanup(sc); 2218193240Ssam return error; 2219197307Srpaulo } 2220193240Ssam 2221193240Ssam for (i = 0; i < MWL_NUM_TX_QUEUES; i++) { 2222193240Ssam error = mwl_txdma_setup(sc, &sc->sc_txq[i]); 2223193240Ssam if (error != 0) { 2224193240Ssam mwl_dma_cleanup(sc); 2225193240Ssam return error; 2226193240Ssam } 2227193240Ssam } 2228193240Ssam return 0; 2229193240Ssam} 2230193240Ssam 2231193240Ssamstatic void 2232193240Ssammwl_dma_cleanup(struct mwl_softc *sc) 2233193240Ssam{ 2234193240Ssam int i; 2235193240Ssam 2236193240Ssam for (i = 0; i < MWL_NUM_TX_QUEUES; i++) 2237193240Ssam mwl_txdma_cleanup(sc, &sc->sc_txq[i]); 2238193240Ssam mwl_rxdma_cleanup(sc); 2239193240Ssam} 2240193240Ssam 2241193240Ssamstatic struct ieee80211_node * 2242193240Ssammwl_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN]) 2243193240Ssam{ 2244193240Ssam struct ieee80211com *ic = vap->iv_ic; 2245287197Sglebius struct mwl_softc *sc = ic->ic_softc; 2246193240Ssam const size_t space = sizeof(struct mwl_node); 2247193240Ssam struct mwl_node *mn; 2248193240Ssam 2249193240Ssam mn = malloc(space, M_80211_NODE, M_NOWAIT|M_ZERO); 2250193240Ssam if (mn == NULL) { 2251193240Ssam /* XXX stat+msg */ 2252193240Ssam return NULL; 2253193240Ssam } 2254193240Ssam DPRINTF(sc, MWL_DEBUG_NODE, "%s: mn %p\n", __func__, mn); 2255193240Ssam return &mn->mn_node; 2256193240Ssam} 2257193240Ssam 2258193240Ssamstatic void 2259193240Ssammwl_node_cleanup(struct ieee80211_node *ni) 2260193240Ssam{ 2261193240Ssam struct ieee80211com *ic = ni->ni_ic; 2262287197Sglebius struct mwl_softc *sc = ic->ic_softc; 2263193240Ssam struct mwl_node *mn = MWL_NODE(ni); 2264193240Ssam 2265193240Ssam DPRINTF(sc, MWL_DEBUG_NODE, "%s: ni %p ic %p staid %d\n", 2266193240Ssam __func__, ni, ni->ni_ic, mn->mn_staid); 2267193240Ssam 2268193240Ssam if (mn->mn_staid != 0) { 2269193240Ssam struct ieee80211vap *vap = ni->ni_vap; 2270193240Ssam 2271193240Ssam if (mn->mn_hvap != NULL) { 2272193240Ssam if (vap->iv_opmode == IEEE80211_M_STA) 2273193240Ssam mwl_hal_delstation(mn->mn_hvap, vap->iv_myaddr); 2274193240Ssam else 2275193240Ssam mwl_hal_delstation(mn->mn_hvap, ni->ni_macaddr); 2276193240Ssam } 2277193240Ssam /* 2278193240Ssam * NB: legacy WDS peer sta db entry is installed using 2279193240Ssam * the associate ap's hvap; use it again to delete it. 2280193240Ssam * XXX can vap be NULL? 2281193240Ssam */ 2282193240Ssam else if (vap->iv_opmode == IEEE80211_M_WDS && 2283193240Ssam MWL_VAP(vap)->mv_ap_hvap != NULL) 2284193240Ssam mwl_hal_delstation(MWL_VAP(vap)->mv_ap_hvap, 2285193240Ssam ni->ni_macaddr); 2286193240Ssam delstaid(sc, mn->mn_staid); 2287193240Ssam mn->mn_staid = 0; 2288193240Ssam } 2289193240Ssam sc->sc_node_cleanup(ni); 2290193240Ssam} 2291193240Ssam 2292193240Ssam/* 2293193240Ssam * Reclaim rx dma buffers from packets sitting on the ampdu 2294193240Ssam * reorder queue for a station. We replace buffers with a 2295193240Ssam * system cluster (if available). 2296193240Ssam */ 2297193240Ssamstatic void 2298193240Ssammwl_ampdu_rxdma_reclaim(struct ieee80211_rx_ampdu *rap) 2299193240Ssam{ 2300193240Ssam#if 0 2301193240Ssam int i, n, off; 2302193240Ssam struct mbuf *m; 2303193240Ssam void *cl; 2304193240Ssam 2305193240Ssam n = rap->rxa_qframes; 2306193240Ssam for (i = 0; i < rap->rxa_wnd && n > 0; i++) { 2307193240Ssam m = rap->rxa_m[i]; 2308193240Ssam if (m == NULL) 2309193240Ssam continue; 2310193240Ssam n--; 2311193240Ssam /* our dma buffers have a well-known free routine */ 2312193240Ssam if ((m->m_flags & M_EXT) == 0 || 2313193240Ssam m->m_ext.ext_free != mwl_ext_free) 2314193240Ssam continue; 2315193240Ssam /* 2316193240Ssam * Try to allocate a cluster and move the data. 2317193240Ssam */ 2318193240Ssam off = m->m_data - m->m_ext.ext_buf; 2319193240Ssam if (off + m->m_pkthdr.len > MCLBYTES) { 2320193240Ssam /* XXX no AMSDU for now */ 2321193240Ssam continue; 2322193240Ssam } 2323193240Ssam cl = pool_cache_get_paddr(&mclpool_cache, 0, 2324193240Ssam &m->m_ext.ext_paddr); 2325193240Ssam if (cl != NULL) { 2326193240Ssam /* 2327193240Ssam * Copy the existing data to the cluster, remove 2328193240Ssam * the rx dma buffer, and attach the cluster in 2329193240Ssam * its place. Note we preserve the offset to the 2330193240Ssam * data so frames being bridged can still prepend 2331193240Ssam * their headers without adding another mbuf. 2332193240Ssam */ 2333193240Ssam memcpy((caddr_t) cl + off, m->m_data, m->m_pkthdr.len); 2334193240Ssam MEXTREMOVE(m); 2335193240Ssam MEXTADD(m, cl, MCLBYTES, 0, NULL, &mclpool_cache); 2336193240Ssam /* setup mbuf like _MCLGET does */ 2337193240Ssam m->m_flags |= M_CLUSTER | M_EXT_RW; 2338193240Ssam _MOWNERREF(m, M_EXT | M_CLUSTER); 2339193240Ssam /* NB: m_data is clobbered by MEXTADDR, adjust */ 2340193240Ssam m->m_data += off; 2341193240Ssam } 2342193240Ssam } 2343193240Ssam#endif 2344193240Ssam} 2345193240Ssam 2346193240Ssam/* 2347193240Ssam * Callback to reclaim resources. We first let the 2348193240Ssam * net80211 layer do it's thing, then if we are still 2349193240Ssam * blocked by a lack of rx dma buffers we walk the ampdu 2350193240Ssam * reorder q's to reclaim buffers by copying to a system 2351193240Ssam * cluster. 2352193240Ssam */ 2353193240Ssamstatic void 2354193240Ssammwl_node_drain(struct ieee80211_node *ni) 2355193240Ssam{ 2356193240Ssam struct ieee80211com *ic = ni->ni_ic; 2357287197Sglebius struct mwl_softc *sc = ic->ic_softc; 2358193240Ssam struct mwl_node *mn = MWL_NODE(ni); 2359193240Ssam 2360193240Ssam DPRINTF(sc, MWL_DEBUG_NODE, "%s: ni %p vap %p staid %d\n", 2361193240Ssam __func__, ni, ni->ni_vap, mn->mn_staid); 2362193240Ssam 2363193240Ssam /* NB: call up first to age out ampdu q's */ 2364193240Ssam sc->sc_node_drain(ni); 2365193240Ssam 2366193240Ssam /* XXX better to not check low water mark? */ 2367193240Ssam if (sc->sc_rxblocked && mn->mn_staid != 0 && 2368193240Ssam (ni->ni_flags & IEEE80211_NODE_HT)) { 2369193240Ssam uint8_t tid; 2370193240Ssam /* 2371193240Ssam * Walk the reorder q and reclaim rx dma buffers by copying 2372193240Ssam * the packet contents into clusters. 2373193240Ssam */ 2374193240Ssam for (tid = 0; tid < WME_NUM_TID; tid++) { 2375193240Ssam struct ieee80211_rx_ampdu *rap; 2376193240Ssam 2377193240Ssam rap = &ni->ni_rx_ampdu[tid]; 2378193240Ssam if ((rap->rxa_flags & IEEE80211_AGGR_XCHGPEND) == 0) 2379193240Ssam continue; 2380193240Ssam if (rap->rxa_qframes) 2381193240Ssam mwl_ampdu_rxdma_reclaim(rap); 2382193240Ssam } 2383193240Ssam } 2384193240Ssam} 2385193240Ssam 2386193240Ssamstatic void 2387193240Ssammwl_node_getsignal(const struct ieee80211_node *ni, int8_t *rssi, int8_t *noise) 2388193240Ssam{ 2389193240Ssam *rssi = ni->ni_ic->ic_node_getrssi(ni); 2390193240Ssam#ifdef MWL_ANT_INFO_SUPPORT 2391193240Ssam#if 0 2392193240Ssam /* XXX need to smooth data */ 2393193240Ssam *noise = -MWL_NODE_CONST(ni)->mn_ai.nf; 2394193240Ssam#else 2395193240Ssam *noise = -95; /* XXX */ 2396193240Ssam#endif 2397193240Ssam#else 2398193240Ssam *noise = -95; /* XXX */ 2399193240Ssam#endif 2400193240Ssam} 2401193240Ssam 2402193240Ssam/* 2403193240Ssam * Convert Hardware per-antenna rssi info to common format: 2404193240Ssam * Let a1, a2, a3 represent the amplitudes per chain 2405193240Ssam * Let amax represent max[a1, a2, a3] 2406193240Ssam * Rssi1_dBm = RSSI_dBm + 20*log10(a1/amax) 2407193240Ssam * Rssi1_dBm = RSSI_dBm + 20*log10(a1) - 20*log10(amax) 2408193240Ssam * We store a table that is 4*20*log10(idx) - the extra 4 is to store or 2409193240Ssam * maintain some extra precision. 2410193240Ssam * 2411193240Ssam * Values are stored in .5 db format capped at 127. 2412193240Ssam */ 2413193240Ssamstatic void 2414193240Ssammwl_node_getmimoinfo(const struct ieee80211_node *ni, 2415193240Ssam struct ieee80211_mimo_info *mi) 2416193240Ssam{ 2417193240Ssam#define CVT(_dst, _src) do { \ 2418193240Ssam (_dst) = rssi + ((logdbtbl[_src] - logdbtbl[rssi_max]) >> 2); \ 2419193240Ssam (_dst) = (_dst) > 64 ? 127 : ((_dst) << 1); \ 2420193240Ssam} while (0) 2421193240Ssam static const int8_t logdbtbl[32] = { 2422193240Ssam 0, 0, 24, 38, 48, 56, 62, 68, 2423193240Ssam 72, 76, 80, 83, 86, 89, 92, 94, 2424193240Ssam 96, 98, 100, 102, 104, 106, 107, 109, 2425193240Ssam 110, 112, 113, 115, 116, 117, 118, 119 2426193240Ssam }; 2427193240Ssam const struct mwl_node *mn = MWL_NODE_CONST(ni); 2428193240Ssam uint8_t rssi = mn->mn_ai.rsvd1/2; /* XXX */ 2429193240Ssam uint32_t rssi_max; 2430193240Ssam 2431193240Ssam rssi_max = mn->mn_ai.rssi_a; 2432193240Ssam if (mn->mn_ai.rssi_b > rssi_max) 2433193240Ssam rssi_max = mn->mn_ai.rssi_b; 2434193240Ssam if (mn->mn_ai.rssi_c > rssi_max) 2435193240Ssam rssi_max = mn->mn_ai.rssi_c; 2436193240Ssam 2437220935Sadrian CVT(mi->rssi[0], mn->mn_ai.rssi_a); 2438220935Sadrian CVT(mi->rssi[1], mn->mn_ai.rssi_b); 2439220935Sadrian CVT(mi->rssi[2], mn->mn_ai.rssi_c); 2440193240Ssam 2441220935Sadrian mi->noise[0] = mn->mn_ai.nf_a; 2442220935Sadrian mi->noise[1] = mn->mn_ai.nf_b; 2443220935Sadrian mi->noise[2] = mn->mn_ai.nf_c; 2444193240Ssam#undef CVT 2445193240Ssam} 2446193240Ssam 2447193240Ssamstatic __inline void * 2448193240Ssammwl_getrxdma(struct mwl_softc *sc) 2449193240Ssam{ 2450193240Ssam struct mwl_jumbo *buf; 2451193240Ssam void *data; 2452193240Ssam 2453193240Ssam /* 2454193240Ssam * Allocate from jumbo pool. 2455193240Ssam */ 2456193240Ssam MWL_RXFREE_LOCK(sc); 2457193240Ssam buf = SLIST_FIRST(&sc->sc_rxfree); 2458193240Ssam if (buf == NULL) { 2459193240Ssam DPRINTF(sc, MWL_DEBUG_ANY, 2460193240Ssam "%s: out of rx dma buffers\n", __func__); 2461193240Ssam sc->sc_stats.mst_rx_nodmabuf++; 2462193240Ssam data = NULL; 2463193240Ssam } else { 2464193240Ssam SLIST_REMOVE_HEAD(&sc->sc_rxfree, next); 2465193240Ssam sc->sc_nrxfree--; 2466193240Ssam data = MWL_JUMBO_BUF2DATA(buf); 2467193240Ssam } 2468193240Ssam MWL_RXFREE_UNLOCK(sc); 2469193240Ssam return data; 2470193240Ssam} 2471193240Ssam 2472193240Ssamstatic __inline void 2473193240Ssammwl_putrxdma(struct mwl_softc *sc, void *data) 2474193240Ssam{ 2475193240Ssam struct mwl_jumbo *buf; 2476193240Ssam 2477193240Ssam /* XXX bounds check data */ 2478193240Ssam MWL_RXFREE_LOCK(sc); 2479193240Ssam buf = MWL_JUMBO_DATA2BUF(data); 2480193240Ssam SLIST_INSERT_HEAD(&sc->sc_rxfree, buf, next); 2481193240Ssam sc->sc_nrxfree++; 2482193240Ssam MWL_RXFREE_UNLOCK(sc); 2483193240Ssam} 2484193240Ssam 2485193240Ssamstatic int 2486193240Ssammwl_rxbuf_init(struct mwl_softc *sc, struct mwl_rxbuf *bf) 2487193240Ssam{ 2488193240Ssam struct mwl_rxdesc *ds; 2489193240Ssam 2490193240Ssam ds = bf->bf_desc; 2491193240Ssam if (bf->bf_data == NULL) { 2492193240Ssam bf->bf_data = mwl_getrxdma(sc); 2493193240Ssam if (bf->bf_data == NULL) { 2494193240Ssam /* mark descriptor to be skipped */ 2495193240Ssam ds->RxControl = EAGLE_RXD_CTRL_OS_OWN; 2496193240Ssam /* NB: don't need PREREAD */ 2497193240Ssam MWL_RXDESC_SYNC(sc, ds, BUS_DMASYNC_PREWRITE); 2498193240Ssam sc->sc_stats.mst_rxbuf_failed++; 2499193240Ssam return ENOMEM; 2500193240Ssam } 2501193240Ssam } 2502193240Ssam /* 2503193240Ssam * NB: DMA buffer contents is known to be unmodified 2504193240Ssam * so there's no need to flush the data cache. 2505193240Ssam */ 2506193240Ssam 2507193240Ssam /* 2508193240Ssam * Setup descriptor. 2509193240Ssam */ 2510193240Ssam ds->QosCtrl = 0; 2511193240Ssam ds->RSSI = 0; 2512193240Ssam ds->Status = EAGLE_RXD_STATUS_IDLE; 2513193240Ssam ds->Channel = 0; 2514193240Ssam ds->PktLen = htole16(MWL_AGGR_SIZE); 2515193240Ssam ds->SQ2 = 0; 2516193240Ssam ds->pPhysBuffData = htole32(MWL_JUMBO_DMA_ADDR(sc, bf->bf_data)); 2517193240Ssam /* NB: don't touch pPhysNext, set once */ 2518193240Ssam ds->RxControl = EAGLE_RXD_CTRL_DRIVER_OWN; 2519193240Ssam MWL_RXDESC_SYNC(sc, ds, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2520193240Ssam 2521193240Ssam return 0; 2522193240Ssam} 2523193240Ssam 2524268529Sglebiusstatic void 2525254799Sandremwl_ext_free(struct mbuf *m, void *data, void *arg) 2526193240Ssam{ 2527193240Ssam struct mwl_softc *sc = arg; 2528193240Ssam 2529193240Ssam /* XXX bounds check data */ 2530193240Ssam mwl_putrxdma(sc, data); 2531193240Ssam /* 2532193240Ssam * If we were previously blocked by a lack of rx dma buffers 2533193240Ssam * check if we now have enough to restart rx interrupt handling. 2534193240Ssam * NB: we know we are called at splvm which is above splnet. 2535193240Ssam */ 2536193240Ssam if (sc->sc_rxblocked && sc->sc_nrxfree > mwl_rxdmalow) { 2537193240Ssam sc->sc_rxblocked = 0; 2538193240Ssam mwl_hal_intrset(sc->sc_mh, sc->sc_imask); 2539193240Ssam } 2540193240Ssam} 2541193240Ssam 2542193240Ssamstruct mwl_frame_bar { 2543193240Ssam u_int8_t i_fc[2]; 2544193240Ssam u_int8_t i_dur[2]; 2545193240Ssam u_int8_t i_ra[IEEE80211_ADDR_LEN]; 2546193240Ssam u_int8_t i_ta[IEEE80211_ADDR_LEN]; 2547193240Ssam /* ctl, seq, FCS */ 2548193240Ssam} __packed; 2549193240Ssam 2550193240Ssam/* 2551193240Ssam * Like ieee80211_anyhdrsize, but handles BAR frames 2552193240Ssam * specially so the logic below to piece the 802.11 2553193240Ssam * header together works. 2554193240Ssam */ 2555193240Ssamstatic __inline int 2556193240Ssammwl_anyhdrsize(const void *data) 2557193240Ssam{ 2558193240Ssam const struct ieee80211_frame *wh = data; 2559193240Ssam 2560193240Ssam if ((wh->i_fc[0]&IEEE80211_FC0_TYPE_MASK) == IEEE80211_FC0_TYPE_CTL) { 2561193240Ssam switch (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) { 2562193240Ssam case IEEE80211_FC0_SUBTYPE_CTS: 2563193240Ssam case IEEE80211_FC0_SUBTYPE_ACK: 2564193240Ssam return sizeof(struct ieee80211_frame_ack); 2565193240Ssam case IEEE80211_FC0_SUBTYPE_BAR: 2566193240Ssam return sizeof(struct mwl_frame_bar); 2567193240Ssam } 2568193240Ssam return sizeof(struct ieee80211_frame_min); 2569193240Ssam } else 2570193240Ssam return ieee80211_hdrsize(data); 2571193240Ssam} 2572193240Ssam 2573193240Ssamstatic void 2574193240Ssammwl_handlemicerror(struct ieee80211com *ic, const uint8_t *data) 2575193240Ssam{ 2576193240Ssam const struct ieee80211_frame *wh; 2577193240Ssam struct ieee80211_node *ni; 2578193240Ssam 2579193240Ssam wh = (const struct ieee80211_frame *)(data + sizeof(uint16_t)); 2580193240Ssam ni = ieee80211_find_rxnode(ic, (const struct ieee80211_frame_min *) wh); 2581193240Ssam if (ni != NULL) { 2582193240Ssam ieee80211_notify_michael_failure(ni->ni_vap, wh, 0); 2583193240Ssam ieee80211_free_node(ni); 2584193240Ssam } 2585193240Ssam} 2586193240Ssam 2587193240Ssam/* 2588193240Ssam * Convert hardware signal strength to rssi. The value 2589193240Ssam * provided by the device has the noise floor added in; 2590193240Ssam * we need to compensate for this but we don't have that 2591193240Ssam * so we use a fixed value. 2592193240Ssam * 2593193240Ssam * The offset of 8 is good for both 2.4 and 5GHz. The LNA 2594193240Ssam * offset is already set as part of the initial gain. This 2595193240Ssam * will give at least +/- 3dB for 2.4GHz and +/- 5dB for 5GHz. 2596193240Ssam */ 2597193240Ssamstatic __inline int 2598193240Ssamcvtrssi(uint8_t ssi) 2599193240Ssam{ 2600193240Ssam int rssi = (int) ssi + 8; 2601193240Ssam /* XXX hack guess until we have a real noise floor */ 2602193240Ssam rssi = 2*(87 - rssi); /* NB: .5 dBm units */ 2603193240Ssam return (rssi < 0 ? 0 : rssi > 127 ? 127 : rssi); 2604193240Ssam} 2605193240Ssam 2606193240Ssamstatic void 2607193240Ssammwl_rx_proc(void *arg, int npending) 2608193240Ssam{ 2609193240Ssam struct mwl_softc *sc = arg; 2610287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 2611193240Ssam struct mwl_rxbuf *bf; 2612193240Ssam struct mwl_rxdesc *ds; 2613193240Ssam struct mbuf *m; 2614193240Ssam struct ieee80211_qosframe *wh; 2615193240Ssam struct ieee80211_node *ni; 2616193240Ssam struct mwl_node *mn; 2617193240Ssam int off, len, hdrlen, pktlen, rssi, ntodo; 2618193240Ssam uint8_t *data, status; 2619193240Ssam void *newdata; 2620193240Ssam int16_t nf; 2621193240Ssam 2622193240Ssam DPRINTF(sc, MWL_DEBUG_RX_PROC, "%s: pending %u rdptr 0x%x wrptr 0x%x\n", 2623193240Ssam __func__, npending, RD4(sc, sc->sc_hwspecs.rxDescRead), 2624193240Ssam RD4(sc, sc->sc_hwspecs.rxDescWrite)); 2625193240Ssam nf = -96; /* XXX */ 2626193240Ssam bf = sc->sc_rxnext; 2627193240Ssam for (ntodo = mwl_rxquota; ntodo > 0; ntodo--) { 2628193240Ssam if (bf == NULL) 2629193240Ssam bf = STAILQ_FIRST(&sc->sc_rxbuf); 2630193240Ssam ds = bf->bf_desc; 2631193240Ssam data = bf->bf_data; 2632193240Ssam if (data == NULL) { 2633193240Ssam /* 2634193240Ssam * If data allocation failed previously there 2635193240Ssam * will be no buffer; try again to re-populate it. 2636193240Ssam * Note the firmware will not advance to the next 2637193240Ssam * descriptor with a dma buffer so we must mimic 2638193240Ssam * this or we'll get out of sync. 2639193240Ssam */ 2640193240Ssam DPRINTF(sc, MWL_DEBUG_ANY, 2641193240Ssam "%s: rx buf w/o dma memory\n", __func__); 2642193240Ssam (void) mwl_rxbuf_init(sc, bf); 2643193240Ssam sc->sc_stats.mst_rx_dmabufmissing++; 2644193240Ssam break; 2645193240Ssam } 2646193240Ssam MWL_RXDESC_SYNC(sc, ds, 2647193240Ssam BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2648193240Ssam if (ds->RxControl != EAGLE_RXD_CTRL_DMA_OWN) 2649193240Ssam break; 2650193240Ssam#ifdef MWL_DEBUG 2651193240Ssam if (sc->sc_debug & MWL_DEBUG_RECV_DESC) 2652193240Ssam mwl_printrxbuf(bf, 0); 2653193240Ssam#endif 2654193240Ssam status = ds->Status; 2655193240Ssam if (status & EAGLE_RXD_STATUS_DECRYPT_ERR_MASK) { 2656287197Sglebius counter_u64_add(ic->ic_ierrors, 1); 2657193240Ssam sc->sc_stats.mst_rx_crypto++; 2658193240Ssam /* 2659193240Ssam * NB: Check EAGLE_RXD_STATUS_GENERAL_DECRYPT_ERR 2660193240Ssam * for backwards compatibility. 2661193240Ssam */ 2662193240Ssam if (status != EAGLE_RXD_STATUS_GENERAL_DECRYPT_ERR && 2663193240Ssam (status & EAGLE_RXD_STATUS_TKIP_MIC_DECRYPT_ERR)) { 2664193240Ssam /* 2665193240Ssam * MIC error, notify upper layers. 2666193240Ssam */ 2667193240Ssam bus_dmamap_sync(sc->sc_rxdmat, sc->sc_rxmap, 2668193240Ssam BUS_DMASYNC_POSTREAD); 2669193240Ssam mwl_handlemicerror(ic, data); 2670193240Ssam sc->sc_stats.mst_rx_tkipmic++; 2671193240Ssam } 2672193240Ssam /* XXX too painful to tap packets */ 2673193240Ssam goto rx_next; 2674193240Ssam } 2675193240Ssam /* 2676193240Ssam * Sync the data buffer. 2677193240Ssam */ 2678193240Ssam len = le16toh(ds->PktLen); 2679193240Ssam bus_dmamap_sync(sc->sc_rxdmat, sc->sc_rxmap, BUS_DMASYNC_POSTREAD); 2680193240Ssam /* 2681193240Ssam * The 802.11 header is provided all or in part at the front; 2682193240Ssam * use it to calculate the true size of the header that we'll 2683193240Ssam * construct below. We use this to figure out where to copy 2684193240Ssam * payload prior to constructing the header. 2685193240Ssam */ 2686193240Ssam hdrlen = mwl_anyhdrsize(data + sizeof(uint16_t)); 2687193240Ssam off = sizeof(uint16_t) + sizeof(struct ieee80211_frame_addr4); 2688193240Ssam 2689193240Ssam /* calculate rssi early so we can re-use for each aggregate */ 2690193240Ssam rssi = cvtrssi(ds->RSSI); 2691193240Ssam 2692193240Ssam pktlen = hdrlen + (len - off); 2693193240Ssam /* 2694193240Ssam * NB: we know our frame is at least as large as 2695193240Ssam * IEEE80211_MIN_LEN because there is a 4-address 2696193240Ssam * frame at the front. Hence there's no need to 2697193240Ssam * vet the packet length. If the frame in fact 2698193240Ssam * is too small it should be discarded at the 2699193240Ssam * net80211 layer. 2700193240Ssam */ 2701193240Ssam 2702193240Ssam /* 2703193240Ssam * Attach dma buffer to an mbuf. We tried 2704193240Ssam * doing this based on the packet size (i.e. 2705193240Ssam * copying small packets) but it turns out to 2706193240Ssam * be a net loss. The tradeoff might be system 2707193240Ssam * dependent (cache architecture is important). 2708193240Ssam */ 2709243857Sglebius MGETHDR(m, M_NOWAIT, MT_DATA); 2710193240Ssam if (m == NULL) { 2711193240Ssam DPRINTF(sc, MWL_DEBUG_ANY, 2712193240Ssam "%s: no rx mbuf\n", __func__); 2713193240Ssam sc->sc_stats.mst_rx_nombuf++; 2714193240Ssam goto rx_next; 2715193240Ssam } 2716193240Ssam /* 2717193240Ssam * Acquire the replacement dma buffer before 2718193240Ssam * processing the frame. If we're out of dma 2719193240Ssam * buffers we disable rx interrupts and wait 2720193240Ssam * for the free pool to reach mlw_rxdmalow buffers 2721193240Ssam * before starting to do work again. If the firmware 2722193240Ssam * runs out of descriptors then it will toss frames 2723193240Ssam * which is better than our doing it as that can 2724193240Ssam * starve our processing. It is also important that 2725193240Ssam * we always process rx'd frames in case they are 2726193240Ssam * A-MPDU as otherwise the host's view of the BA 2727193240Ssam * window may get out of sync with the firmware. 2728193240Ssam */ 2729193240Ssam newdata = mwl_getrxdma(sc); 2730193240Ssam if (newdata == NULL) { 2731193240Ssam /* NB: stat+msg in mwl_getrxdma */ 2732193240Ssam m_free(m); 2733193240Ssam /* disable RX interrupt and mark state */ 2734193240Ssam mwl_hal_intrset(sc->sc_mh, 2735193240Ssam sc->sc_imask &~ MACREG_A2HRIC_BIT_RX_RDY); 2736193240Ssam sc->sc_rxblocked = 1; 2737193240Ssam ieee80211_drain(ic); 2738193240Ssam /* XXX check rxblocked and immediately start again? */ 2739193240Ssam goto rx_stop; 2740193240Ssam } 2741193240Ssam bf->bf_data = newdata; 2742193240Ssam /* 2743193240Ssam * Attach the dma buffer to the mbuf; 2744193240Ssam * mwl_rxbuf_init will re-setup the rx 2745193240Ssam * descriptor using the replacement dma 2746193240Ssam * buffer we just installed above. 2747193240Ssam */ 2748193240Ssam MEXTADD(m, data, MWL_AGGR_SIZE, mwl_ext_free, 2749193240Ssam data, sc, 0, EXT_NET_DRV); 2750193240Ssam m->m_data += off - hdrlen; 2751193240Ssam m->m_pkthdr.len = m->m_len = pktlen; 2752193240Ssam /* NB: dma buffer assumed read-only */ 2753193240Ssam 2754193240Ssam /* 2755193240Ssam * Piece 802.11 header together. 2756193240Ssam */ 2757193240Ssam wh = mtod(m, struct ieee80211_qosframe *); 2758193240Ssam /* NB: don't need to do this sometimes but ... */ 2759193240Ssam /* XXX special case so we can memcpy after m_devget? */ 2760193240Ssam ovbcopy(data + sizeof(uint16_t), wh, hdrlen); 2761344969Savos if (IEEE80211_QOS_HAS_SEQ(wh)) 2762344969Savos *(uint16_t *)ieee80211_getqos(wh) = ds->QosCtrl; 2763193240Ssam /* 2764193240Ssam * The f/w strips WEP header but doesn't clear 2765193240Ssam * the WEP bit; mark the packet with M_WEP so 2766193240Ssam * net80211 will treat the data as decrypted. 2767193240Ssam * While here also clear the PWR_MGT bit since 2768193240Ssam * power save is handled by the firmware and 2769193240Ssam * passing this up will potentially cause the 2770193240Ssam * upper layer to put a station in power save 2771193240Ssam * (except when configured with MWL_HOST_PS_SUPPORT). 2772193240Ssam */ 2773260444Skevlo if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) 2774193240Ssam m->m_flags |= M_WEP; 2775193240Ssam#ifdef MWL_HOST_PS_SUPPORT 2776260444Skevlo wh->i_fc[1] &= ~IEEE80211_FC1_PROTECTED; 2777193240Ssam#else 2778260444Skevlo wh->i_fc[1] &= ~(IEEE80211_FC1_PROTECTED | 2779260444Skevlo IEEE80211_FC1_PWR_MGT); 2780193240Ssam#endif 2781193240Ssam 2782193240Ssam if (ieee80211_radiotap_active(ic)) { 2783193240Ssam struct mwl_rx_radiotap_header *tap = &sc->sc_rx_th; 2784193240Ssam 2785193240Ssam tap->wr_flags = 0; 2786193240Ssam tap->wr_rate = ds->Rate; 2787193240Ssam tap->wr_antsignal = rssi + nf; 2788193240Ssam tap->wr_antnoise = nf; 2789193240Ssam } 2790193240Ssam if (IFF_DUMPPKTS_RECV(sc, wh)) { 2791193240Ssam ieee80211_dump_pkt(ic, mtod(m, caddr_t), 2792193240Ssam len, ds->Rate, rssi); 2793193240Ssam } 2794193240Ssam /* dispatch */ 2795193240Ssam ni = ieee80211_find_rxnode(ic, 2796193240Ssam (const struct ieee80211_frame_min *) wh); 2797193240Ssam if (ni != NULL) { 2798193240Ssam mn = MWL_NODE(ni); 2799193240Ssam#ifdef MWL_ANT_INFO_SUPPORT 2800193240Ssam mn->mn_ai.rssi_a = ds->ai.rssi_a; 2801193240Ssam mn->mn_ai.rssi_b = ds->ai.rssi_b; 2802193240Ssam mn->mn_ai.rssi_c = ds->ai.rssi_c; 2803193240Ssam mn->mn_ai.rsvd1 = rssi; 2804193240Ssam#endif 2805193240Ssam /* tag AMPDU aggregates for reorder processing */ 2806193240Ssam if (ni->ni_flags & IEEE80211_NODE_HT) 2807193240Ssam m->m_flags |= M_AMPDU; 2808193240Ssam (void) ieee80211_input(ni, m, rssi, nf); 2809193240Ssam ieee80211_free_node(ni); 2810193240Ssam } else 2811193240Ssam (void) ieee80211_input_all(ic, m, rssi, nf); 2812193240Ssamrx_next: 2813193240Ssam /* NB: ignore ENOMEM so we process more descriptors */ 2814193240Ssam (void) mwl_rxbuf_init(sc, bf); 2815193240Ssam bf = STAILQ_NEXT(bf, bf_list); 2816193240Ssam } 2817193240Ssamrx_stop: 2818193240Ssam sc->sc_rxnext = bf; 2819193240Ssam 2820287197Sglebius if (mbufq_first(&sc->sc_snd) != NULL) { 2821193240Ssam /* NB: kick fw; the tx thread may have been preempted */ 2822193240Ssam mwl_hal_txstart(sc->sc_mh, 0); 2823287197Sglebius mwl_start(sc); 2824193240Ssam } 2825193240Ssam} 2826193240Ssam 2827193240Ssamstatic void 2828193240Ssammwl_txq_init(struct mwl_softc *sc, struct mwl_txq *txq, int qnum) 2829193240Ssam{ 2830193240Ssam struct mwl_txbuf *bf, *bn; 2831193240Ssam struct mwl_txdesc *ds; 2832193240Ssam 2833193240Ssam MWL_TXQ_LOCK_INIT(sc, txq); 2834193240Ssam txq->qnum = qnum; 2835193240Ssam txq->txpri = 0; /* XXX */ 2836193240Ssam#if 0 2837193240Ssam /* NB: q setup by mwl_txdma_setup XXX */ 2838193240Ssam STAILQ_INIT(&txq->free); 2839193240Ssam#endif 2840193240Ssam STAILQ_FOREACH(bf, &txq->free, bf_list) { 2841193240Ssam bf->bf_txq = txq; 2842193240Ssam 2843193240Ssam ds = bf->bf_desc; 2844193240Ssam bn = STAILQ_NEXT(bf, bf_list); 2845193240Ssam if (bn == NULL) 2846193240Ssam bn = STAILQ_FIRST(&txq->free); 2847193240Ssam ds->pPhysNext = htole32(bn->bf_daddr); 2848193240Ssam } 2849193240Ssam STAILQ_INIT(&txq->active); 2850193240Ssam} 2851193240Ssam 2852193240Ssam/* 2853193240Ssam * Setup a hardware data transmit queue for the specified 2854193240Ssam * access control. We record the mapping from ac's 2855193240Ssam * to h/w queues for use by mwl_tx_start. 2856193240Ssam */ 2857193240Ssamstatic int 2858193240Ssammwl_tx_setup(struct mwl_softc *sc, int ac, int mvtype) 2859193240Ssam{ 2860193240Ssam struct mwl_txq *txq; 2861193240Ssam 2862288087Sadrian if (ac >= nitems(sc->sc_ac2q)) { 2863193240Ssam device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n", 2864288087Sadrian ac, nitems(sc->sc_ac2q)); 2865193240Ssam return 0; 2866193240Ssam } 2867193240Ssam if (mvtype >= MWL_NUM_TX_QUEUES) { 2868193240Ssam device_printf(sc->sc_dev, "mvtype %u out of range, max %u!\n", 2869193240Ssam mvtype, MWL_NUM_TX_QUEUES); 2870193240Ssam return 0; 2871193240Ssam } 2872193240Ssam txq = &sc->sc_txq[mvtype]; 2873193240Ssam mwl_txq_init(sc, txq, mvtype); 2874193240Ssam sc->sc_ac2q[ac] = txq; 2875193240Ssam return 1; 2876193240Ssam} 2877193240Ssam 2878193240Ssam/* 2879193240Ssam * Update WME parameters for a transmit queue. 2880193240Ssam */ 2881193240Ssamstatic int 2882193240Ssammwl_txq_update(struct mwl_softc *sc, int ac) 2883193240Ssam{ 2884193240Ssam#define MWL_EXPONENT_TO_VALUE(v) ((1<<v)-1) 2885287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 2886193240Ssam struct mwl_txq *txq = sc->sc_ac2q[ac]; 2887193240Ssam struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 2888193240Ssam struct mwl_hal *mh = sc->sc_mh; 2889193240Ssam int aifs, cwmin, cwmax, txoplim; 2890193240Ssam 2891193240Ssam aifs = wmep->wmep_aifsn; 2892193240Ssam /* XXX in sta mode need to pass log values for cwmin/max */ 2893193240Ssam cwmin = MWL_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 2894193240Ssam cwmax = MWL_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 2895193240Ssam txoplim = wmep->wmep_txopLimit; /* NB: units of 32us */ 2896193240Ssam 2897193240Ssam if (mwl_hal_setedcaparams(mh, txq->qnum, cwmin, cwmax, aifs, txoplim)) { 2898193240Ssam device_printf(sc->sc_dev, "unable to update hardware queue " 2899193240Ssam "parameters for %s traffic!\n", 2900193240Ssam ieee80211_wme_acnames[ac]); 2901193240Ssam return 0; 2902193240Ssam } 2903193240Ssam return 1; 2904193240Ssam#undef MWL_EXPONENT_TO_VALUE 2905193240Ssam} 2906193240Ssam 2907193240Ssam/* 2908193240Ssam * Callback from the 802.11 layer to update WME parameters. 2909193240Ssam */ 2910193240Ssamstatic int 2911193240Ssammwl_wme_update(struct ieee80211com *ic) 2912193240Ssam{ 2913287197Sglebius struct mwl_softc *sc = ic->ic_softc; 2914193240Ssam 2915193240Ssam return !mwl_txq_update(sc, WME_AC_BE) || 2916193240Ssam !mwl_txq_update(sc, WME_AC_BK) || 2917193240Ssam !mwl_txq_update(sc, WME_AC_VI) || 2918193240Ssam !mwl_txq_update(sc, WME_AC_VO) ? EIO : 0; 2919193240Ssam} 2920193240Ssam 2921193240Ssam/* 2922193240Ssam * Reclaim resources for a setup queue. 2923193240Ssam */ 2924193240Ssamstatic void 2925193240Ssammwl_tx_cleanupq(struct mwl_softc *sc, struct mwl_txq *txq) 2926193240Ssam{ 2927193240Ssam /* XXX hal work? */ 2928193240Ssam MWL_TXQ_LOCK_DESTROY(txq); 2929193240Ssam} 2930193240Ssam 2931193240Ssam/* 2932193240Ssam * Reclaim all tx queue resources. 2933193240Ssam */ 2934193240Ssamstatic void 2935193240Ssammwl_tx_cleanup(struct mwl_softc *sc) 2936193240Ssam{ 2937193240Ssam int i; 2938193240Ssam 2939193240Ssam for (i = 0; i < MWL_NUM_TX_QUEUES; i++) 2940193240Ssam mwl_tx_cleanupq(sc, &sc->sc_txq[i]); 2941193240Ssam} 2942193240Ssam 2943193240Ssamstatic int 2944193240Ssammwl_tx_dmasetup(struct mwl_softc *sc, struct mwl_txbuf *bf, struct mbuf *m0) 2945193240Ssam{ 2946193240Ssam struct mbuf *m; 2947193240Ssam int error; 2948193240Ssam 2949193240Ssam /* 2950193240Ssam * Load the DMA map so any coalescing is done. This 2951193240Ssam * also calculates the number of descriptors we need. 2952193240Ssam */ 2953193240Ssam error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0, 2954193240Ssam bf->bf_segs, &bf->bf_nseg, 2955193240Ssam BUS_DMA_NOWAIT); 2956193240Ssam if (error == EFBIG) { 2957193240Ssam /* XXX packet requires too many descriptors */ 2958193240Ssam bf->bf_nseg = MWL_TXDESC+1; 2959193240Ssam } else if (error != 0) { 2960193240Ssam sc->sc_stats.mst_tx_busdma++; 2961193240Ssam m_freem(m0); 2962193240Ssam return error; 2963193240Ssam } 2964193240Ssam /* 2965193240Ssam * Discard null packets and check for packets that 2966193240Ssam * require too many TX descriptors. We try to convert 2967193240Ssam * the latter to a cluster. 2968193240Ssam */ 2969193240Ssam if (error == EFBIG) { /* too many desc's, linearize */ 2970193240Ssam sc->sc_stats.mst_tx_linear++; 2971193240Ssam#if MWL_TXDESC > 1 2972243857Sglebius m = m_collapse(m0, M_NOWAIT, MWL_TXDESC); 2973193240Ssam#else 2974243857Sglebius m = m_defrag(m0, M_NOWAIT); 2975193240Ssam#endif 2976193240Ssam if (m == NULL) { 2977193240Ssam m_freem(m0); 2978193240Ssam sc->sc_stats.mst_tx_nombuf++; 2979193240Ssam return ENOMEM; 2980193240Ssam } 2981193240Ssam m0 = m; 2982193240Ssam error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0, 2983193240Ssam bf->bf_segs, &bf->bf_nseg, 2984193240Ssam BUS_DMA_NOWAIT); 2985193240Ssam if (error != 0) { 2986193240Ssam sc->sc_stats.mst_tx_busdma++; 2987193240Ssam m_freem(m0); 2988193240Ssam return error; 2989193240Ssam } 2990193240Ssam KASSERT(bf->bf_nseg <= MWL_TXDESC, 2991193240Ssam ("too many segments after defrag; nseg %u", bf->bf_nseg)); 2992193240Ssam } else if (bf->bf_nseg == 0) { /* null packet, discard */ 2993193240Ssam sc->sc_stats.mst_tx_nodata++; 2994193240Ssam m_freem(m0); 2995193240Ssam return EIO; 2996193240Ssam } 2997193240Ssam DPRINTF(sc, MWL_DEBUG_XMIT, "%s: m %p len %u\n", 2998193240Ssam __func__, m0, m0->m_pkthdr.len); 2999193240Ssam bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 3000193240Ssam bf->bf_m = m0; 3001193240Ssam 3002193240Ssam return 0; 3003193240Ssam} 3004193240Ssam 3005193240Ssamstatic __inline int 3006193240Ssammwl_cvtlegacyrate(int rate) 3007193240Ssam{ 3008193240Ssam switch (rate) { 3009193240Ssam case 2: return 0; 3010193240Ssam case 4: return 1; 3011193240Ssam case 11: return 2; 3012193240Ssam case 22: return 3; 3013193240Ssam case 44: return 4; 3014193240Ssam case 12: return 5; 3015193240Ssam case 18: return 6; 3016193240Ssam case 24: return 7; 3017193240Ssam case 36: return 8; 3018193240Ssam case 48: return 9; 3019193240Ssam case 72: return 10; 3020193240Ssam case 96: return 11; 3021193240Ssam case 108:return 12; 3022193240Ssam } 3023193240Ssam return 0; 3024193240Ssam} 3025193240Ssam 3026193240Ssam/* 3027193240Ssam * Calculate fixed tx rate information per client state; 3028193240Ssam * this value is suitable for writing to the Format field 3029193240Ssam * of a tx descriptor. 3030193240Ssam */ 3031193240Ssamstatic uint16_t 3032193240Ssammwl_calcformat(uint8_t rate, const struct ieee80211_node *ni) 3033193240Ssam{ 3034193240Ssam uint16_t fmt; 3035193240Ssam 3036193240Ssam fmt = SM(3, EAGLE_TXD_ANTENNA) 3037193240Ssam | (IEEE80211_IS_CHAN_HT40D(ni->ni_chan) ? 3038193240Ssam EAGLE_TXD_EXTCHAN_LO : EAGLE_TXD_EXTCHAN_HI); 3039195171Ssam if (rate & IEEE80211_RATE_MCS) { /* HT MCS */ 3040193240Ssam fmt |= EAGLE_TXD_FORMAT_HT 3041193240Ssam /* NB: 0x80 implicitly stripped from ucastrate */ 3042193240Ssam | SM(rate, EAGLE_TXD_RATE); 3043193240Ssam /* XXX short/long GI may be wrong; re-check */ 3044193240Ssam if (IEEE80211_IS_CHAN_HT40(ni->ni_chan)) { 3045193240Ssam fmt |= EAGLE_TXD_CHW_40 3046193240Ssam | (ni->ni_htcap & IEEE80211_HTCAP_SHORTGI40 ? 3047193240Ssam EAGLE_TXD_GI_SHORT : EAGLE_TXD_GI_LONG); 3048193240Ssam } else { 3049193240Ssam fmt |= EAGLE_TXD_CHW_20 3050193240Ssam | (ni->ni_htcap & IEEE80211_HTCAP_SHORTGI20 ? 3051193240Ssam EAGLE_TXD_GI_SHORT : EAGLE_TXD_GI_LONG); 3052193240Ssam } 3053193240Ssam } else { /* legacy rate */ 3054193240Ssam fmt |= EAGLE_TXD_FORMAT_LEGACY 3055193240Ssam | SM(mwl_cvtlegacyrate(rate), EAGLE_TXD_RATE) 3056193240Ssam | EAGLE_TXD_CHW_20 3057193240Ssam /* XXX iv_flags & IEEE80211_F_SHPREAMBLE? */ 3058193240Ssam | (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE ? 3059193240Ssam EAGLE_TXD_PREAMBLE_SHORT : EAGLE_TXD_PREAMBLE_LONG); 3060193240Ssam } 3061193240Ssam return fmt; 3062193240Ssam} 3063193240Ssam 3064193240Ssamstatic int 3065193240Ssammwl_tx_start(struct mwl_softc *sc, struct ieee80211_node *ni, struct mwl_txbuf *bf, 3066193240Ssam struct mbuf *m0) 3067193240Ssam{ 3068287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 3069193240Ssam struct ieee80211vap *vap = ni->ni_vap; 3070193240Ssam int error, iswep, ismcast; 3071193240Ssam int hdrlen, copyhdrlen, pktlen; 3072193240Ssam struct mwl_txdesc *ds; 3073193240Ssam struct mwl_txq *txq; 3074193240Ssam struct ieee80211_frame *wh; 3075193240Ssam struct mwltxrec *tr; 3076193240Ssam struct mwl_node *mn; 3077193240Ssam uint16_t qos; 3078193240Ssam#if MWL_TXDESC > 1 3079193240Ssam int i; 3080193240Ssam#endif 3081193240Ssam 3082193240Ssam wh = mtod(m0, struct ieee80211_frame *); 3083260444Skevlo iswep = wh->i_fc[1] & IEEE80211_FC1_PROTECTED; 3084193240Ssam ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 3085193240Ssam hdrlen = ieee80211_anyhdrsize(wh); 3086193240Ssam copyhdrlen = hdrlen; 3087193240Ssam pktlen = m0->m_pkthdr.len; 3088193240Ssam if (IEEE80211_QOS_HAS_SEQ(wh)) { 3089344969Savos qos = *(uint16_t *)ieee80211_getqos(wh); 3090344969Savos if (IEEE80211_IS_DSTODS(wh)) 3091193240Ssam copyhdrlen -= sizeof(qos); 3092193240Ssam } else 3093193240Ssam qos = 0; 3094193240Ssam 3095193240Ssam if (iswep) { 3096193240Ssam const struct ieee80211_cipher *cip; 3097193240Ssam struct ieee80211_key *k; 3098193240Ssam 3099193240Ssam /* 3100193240Ssam * Construct the 802.11 header+trailer for an encrypted 3101193240Ssam * frame. The only reason this can fail is because of an 3102193240Ssam * unknown or unsupported cipher/key type. 3103193240Ssam * 3104193240Ssam * NB: we do this even though the firmware will ignore 3105193240Ssam * what we've done for WEP and TKIP as we need the 3106193240Ssam * ExtIV filled in for CCMP and this also adjusts 3107193240Ssam * the headers which simplifies our work below. 3108193240Ssam */ 3109193240Ssam k = ieee80211_crypto_encap(ni, m0); 3110193240Ssam if (k == NULL) { 3111193240Ssam /* 3112193240Ssam * This can happen when the key is yanked after the 3113193240Ssam * frame was queued. Just discard the frame; the 3114193240Ssam * 802.11 layer counts failures and provides 3115193240Ssam * debugging/diagnostics. 3116193240Ssam */ 3117193240Ssam m_freem(m0); 3118193240Ssam return EIO; 3119193240Ssam } 3120193240Ssam /* 3121193240Ssam * Adjust the packet length for the crypto additions 3122193240Ssam * done during encap and any other bits that the f/w 3123193240Ssam * will add later on. 3124193240Ssam */ 3125193240Ssam cip = k->wk_cipher; 3126193240Ssam pktlen += cip->ic_header + cip->ic_miclen + cip->ic_trailer; 3127193240Ssam 3128193240Ssam /* packet header may have moved, reset our local pointer */ 3129193240Ssam wh = mtod(m0, struct ieee80211_frame *); 3130193240Ssam } 3131193240Ssam 3132193240Ssam if (ieee80211_radiotap_active_vap(vap)) { 3133193240Ssam sc->sc_tx_th.wt_flags = 0; /* XXX */ 3134193240Ssam if (iswep) 3135193240Ssam sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3136193240Ssam#if 0 3137193240Ssam sc->sc_tx_th.wt_rate = ds->DataRate; 3138193240Ssam#endif 3139193240Ssam sc->sc_tx_th.wt_txpower = ni->ni_txpower; 3140193240Ssam sc->sc_tx_th.wt_antenna = sc->sc_txantenna; 3141193240Ssam 3142193240Ssam ieee80211_radiotap_tx(vap, m0); 3143193240Ssam } 3144193240Ssam /* 3145193240Ssam * Copy up/down the 802.11 header; the firmware requires 3146193240Ssam * we present a 2-byte payload length followed by a 3147193240Ssam * 4-address header (w/o QoS), followed (optionally) by 3148193240Ssam * any WEP/ExtIV header (but only filled in for CCMP). 3149193240Ssam * We are assured the mbuf has sufficient headroom to 3150193240Ssam * prepend in-place by the setup of ic_headroom in 3151193240Ssam * mwl_attach. 3152193240Ssam */ 3153193240Ssam if (hdrlen < sizeof(struct mwltxrec)) { 3154193240Ssam const int space = sizeof(struct mwltxrec) - hdrlen; 3155193240Ssam if (M_LEADINGSPACE(m0) < space) { 3156193240Ssam /* NB: should never happen */ 3157193240Ssam device_printf(sc->sc_dev, 3158193240Ssam "not enough headroom, need %d found %zd, " 3159193240Ssam "m_flags 0x%x m_len %d\n", 3160193240Ssam space, M_LEADINGSPACE(m0), m0->m_flags, m0->m_len); 3161193240Ssam ieee80211_dump_pkt(ic, 3162193240Ssam mtod(m0, const uint8_t *), m0->m_len, 0, -1); 3163193240Ssam m_freem(m0); 3164193240Ssam sc->sc_stats.mst_tx_noheadroom++; 3165193240Ssam return EIO; 3166193240Ssam } 3167193240Ssam M_PREPEND(m0, space, M_NOWAIT); 3168193240Ssam } 3169193240Ssam tr = mtod(m0, struct mwltxrec *); 3170193240Ssam if (wh != (struct ieee80211_frame *) &tr->wh) 3171193240Ssam ovbcopy(wh, &tr->wh, hdrlen); 3172193240Ssam /* 3173193240Ssam * Note: the "firmware length" is actually the length 3174193240Ssam * of the fully formed "802.11 payload". That is, it's 3175193240Ssam * everything except for the 802.11 header. In particular 3176193240Ssam * this includes all crypto material including the MIC! 3177193240Ssam */ 3178193240Ssam tr->fwlen = htole16(pktlen - hdrlen); 3179193240Ssam 3180193240Ssam /* 3181193240Ssam * Load the DMA map so any coalescing is done. This 3182193240Ssam * also calculates the number of descriptors we need. 3183193240Ssam */ 3184193240Ssam error = mwl_tx_dmasetup(sc, bf, m0); 3185193240Ssam if (error != 0) { 3186193240Ssam /* NB: stat collected in mwl_tx_dmasetup */ 3187193240Ssam DPRINTF(sc, MWL_DEBUG_XMIT, 3188193240Ssam "%s: unable to setup dma\n", __func__); 3189193240Ssam return error; 3190193240Ssam } 3191193240Ssam bf->bf_node = ni; /* NB: held reference */ 3192193240Ssam m0 = bf->bf_m; /* NB: may have changed */ 3193193240Ssam tr = mtod(m0, struct mwltxrec *); 3194193240Ssam wh = (struct ieee80211_frame *)&tr->wh; 3195193240Ssam 3196193240Ssam /* 3197193240Ssam * Formulate tx descriptor. 3198193240Ssam */ 3199193240Ssam ds = bf->bf_desc; 3200193240Ssam txq = bf->bf_txq; 3201193240Ssam 3202193240Ssam ds->QosCtrl = qos; /* NB: already little-endian */ 3203193240Ssam#if MWL_TXDESC == 1 3204193240Ssam /* 3205193240Ssam * NB: multiframes should be zero because the descriptors 3206193240Ssam * are initialized to zero. This should handle the case 3207193240Ssam * where the driver is built with MWL_TXDESC=1 but we are 3208193240Ssam * using firmware with multi-segment support. 3209193240Ssam */ 3210193240Ssam ds->PktPtr = htole32(bf->bf_segs[0].ds_addr); 3211193240Ssam ds->PktLen = htole16(bf->bf_segs[0].ds_len); 3212193240Ssam#else 3213193240Ssam ds->multiframes = htole32(bf->bf_nseg); 3214193240Ssam ds->PktLen = htole16(m0->m_pkthdr.len); 3215193240Ssam for (i = 0; i < bf->bf_nseg; i++) { 3216193240Ssam ds->PktPtrArray[i] = htole32(bf->bf_segs[i].ds_addr); 3217193240Ssam ds->PktLenArray[i] = htole16(bf->bf_segs[i].ds_len); 3218193240Ssam } 3219193240Ssam#endif 3220193240Ssam /* NB: pPhysNext, DataRate, and SapPktInfo setup once, don't touch */ 3221193240Ssam ds->Format = 0; 3222193240Ssam ds->pad = 0; 3223195171Ssam ds->ack_wcb_addr = 0; 3224193240Ssam 3225193240Ssam mn = MWL_NODE(ni); 3226193240Ssam /* 3227193240Ssam * Select transmit rate. 3228193240Ssam */ 3229193240Ssam switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 3230193240Ssam case IEEE80211_FC0_TYPE_MGT: 3231193240Ssam sc->sc_stats.mst_tx_mgmt++; 3232193240Ssam /* fall thru... */ 3233193240Ssam case IEEE80211_FC0_TYPE_CTL: 3234193240Ssam /* NB: assign to BE q to avoid bursting */ 3235193240Ssam ds->TxPriority = MWL_WME_AC_BE; 3236193240Ssam break; 3237193240Ssam case IEEE80211_FC0_TYPE_DATA: 3238193240Ssam if (!ismcast) { 3239193240Ssam const struct ieee80211_txparam *tp = ni->ni_txparms; 3240193240Ssam /* 3241193240Ssam * EAPOL frames get forced to a fixed rate and w/o 3242193240Ssam * aggregation; otherwise check for any fixed rate 3243193240Ssam * for the client (may depend on association state). 3244193240Ssam */ 3245193240Ssam if (m0->m_flags & M_EAPOL) { 3246193240Ssam const struct mwl_vap *mvp = MWL_VAP_CONST(vap); 3247193240Ssam ds->Format = mvp->mv_eapolformat; 3248193240Ssam ds->pad = htole16( 3249193240Ssam EAGLE_TXD_FIXED_RATE | EAGLE_TXD_DONT_AGGR); 3250195171Ssam } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) { 3251193240Ssam /* XXX pre-calculate per node */ 3252193240Ssam ds->Format = htole16( 3253193240Ssam mwl_calcformat(tp->ucastrate, ni)); 3254193240Ssam ds->pad = htole16(EAGLE_TXD_FIXED_RATE); 3255193240Ssam } 3256193240Ssam /* NB: EAPOL frames will never have qos set */ 3257193240Ssam if (qos == 0) 3258193240Ssam ds->TxPriority = txq->qnum; 3259193240Ssam#if MWL_MAXBA > 3 3260193240Ssam else if (mwl_bastream_match(&mn->mn_ba[3], qos)) 3261193240Ssam ds->TxPriority = mn->mn_ba[3].txq; 3262193240Ssam#endif 3263193240Ssam#if MWL_MAXBA > 2 3264193240Ssam else if (mwl_bastream_match(&mn->mn_ba[2], qos)) 3265193240Ssam ds->TxPriority = mn->mn_ba[2].txq; 3266193240Ssam#endif 3267193240Ssam#if MWL_MAXBA > 1 3268193240Ssam else if (mwl_bastream_match(&mn->mn_ba[1], qos)) 3269193240Ssam ds->TxPriority = mn->mn_ba[1].txq; 3270193240Ssam#endif 3271193240Ssam#if MWL_MAXBA > 0 3272193240Ssam else if (mwl_bastream_match(&mn->mn_ba[0], qos)) 3273193240Ssam ds->TxPriority = mn->mn_ba[0].txq; 3274193240Ssam#endif 3275193240Ssam else 3276193240Ssam ds->TxPriority = txq->qnum; 3277193240Ssam } else 3278193240Ssam ds->TxPriority = txq->qnum; 3279193240Ssam break; 3280193240Ssam default: 3281287197Sglebius device_printf(sc->sc_dev, "bogus frame type 0x%x (%s)\n", 3282193240Ssam wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__); 3283193240Ssam sc->sc_stats.mst_tx_badframetype++; 3284193240Ssam m_freem(m0); 3285193240Ssam return EIO; 3286193240Ssam } 3287193240Ssam 3288193240Ssam if (IFF_DUMPPKTS_XMIT(sc)) 3289193240Ssam ieee80211_dump_pkt(ic, 3290193240Ssam mtod(m0, const uint8_t *)+sizeof(uint16_t), 3291193240Ssam m0->m_len - sizeof(uint16_t), ds->DataRate, -1); 3292193240Ssam 3293193240Ssam MWL_TXQ_LOCK(txq); 3294193240Ssam ds->Status = htole32(EAGLE_TXD_STATUS_FW_OWNED); 3295193240Ssam STAILQ_INSERT_TAIL(&txq->active, bf, bf_list); 3296193240Ssam MWL_TXDESC_SYNC(txq, ds, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3297193240Ssam 3298199559Sjhb sc->sc_tx_timer = 5; 3299193240Ssam MWL_TXQ_UNLOCK(txq); 3300193240Ssam 3301193240Ssam return 0; 3302193240Ssam} 3303193240Ssam 3304193240Ssamstatic __inline int 3305193240Ssammwl_cvtlegacyrix(int rix) 3306193240Ssam{ 3307193240Ssam static const int ieeerates[] = 3308193240Ssam { 2, 4, 11, 22, 44, 12, 18, 24, 36, 48, 72, 96, 108 }; 3309288087Sadrian return (rix < nitems(ieeerates) ? ieeerates[rix] : 0); 3310193240Ssam} 3311193240Ssam 3312193240Ssam/* 3313193240Ssam * Process completed xmit descriptors from the specified queue. 3314193240Ssam */ 3315193240Ssamstatic int 3316193240Ssammwl_tx_processq(struct mwl_softc *sc, struct mwl_txq *txq) 3317193240Ssam{ 3318193240Ssam#define EAGLE_TXD_STATUS_MCAST \ 3319193240Ssam (EAGLE_TXD_STATUS_MULTICAST_TX | EAGLE_TXD_STATUS_BROADCAST_TX) 3320287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 3321193240Ssam struct mwl_txbuf *bf; 3322193240Ssam struct mwl_txdesc *ds; 3323193240Ssam struct ieee80211_node *ni; 3324193240Ssam struct mwl_node *an; 3325193240Ssam int nreaped; 3326193240Ssam uint32_t status; 3327193240Ssam 3328193240Ssam DPRINTF(sc, MWL_DEBUG_TX_PROC, "%s: tx queue %u\n", __func__, txq->qnum); 3329193240Ssam for (nreaped = 0;; nreaped++) { 3330193240Ssam MWL_TXQ_LOCK(txq); 3331193240Ssam bf = STAILQ_FIRST(&txq->active); 3332193240Ssam if (bf == NULL) { 3333193240Ssam MWL_TXQ_UNLOCK(txq); 3334193240Ssam break; 3335193240Ssam } 3336193240Ssam ds = bf->bf_desc; 3337193240Ssam MWL_TXDESC_SYNC(txq, ds, 3338193240Ssam BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3339193240Ssam if (ds->Status & htole32(EAGLE_TXD_STATUS_FW_OWNED)) { 3340193240Ssam MWL_TXQ_UNLOCK(txq); 3341193240Ssam break; 3342193240Ssam } 3343193240Ssam STAILQ_REMOVE_HEAD(&txq->active, bf_list); 3344193240Ssam MWL_TXQ_UNLOCK(txq); 3345193240Ssam 3346193240Ssam#ifdef MWL_DEBUG 3347193240Ssam if (sc->sc_debug & MWL_DEBUG_XMIT_DESC) 3348193240Ssam mwl_printtxbuf(bf, txq->qnum, nreaped); 3349193240Ssam#endif 3350193240Ssam ni = bf->bf_node; 3351193240Ssam if (ni != NULL) { 3352193240Ssam an = MWL_NODE(ni); 3353193240Ssam status = le32toh(ds->Status); 3354193240Ssam if (status & EAGLE_TXD_STATUS_OK) { 3355193240Ssam uint16_t Format = le16toh(ds->Format); 3356193240Ssam uint8_t txant = MS(Format, EAGLE_TXD_ANTENNA); 3357193240Ssam 3358193240Ssam sc->sc_stats.mst_ant_tx[txant]++; 3359193240Ssam if (status & EAGLE_TXD_STATUS_OK_RETRY) 3360193240Ssam sc->sc_stats.mst_tx_retries++; 3361193240Ssam if (status & EAGLE_TXD_STATUS_OK_MORE_RETRY) 3362193240Ssam sc->sc_stats.mst_tx_mretries++; 3363193240Ssam if (txq->qnum >= MWL_WME_AC_VO) 3364193240Ssam ic->ic_wme.wme_hipri_traffic++; 3365193240Ssam ni->ni_txrate = MS(Format, EAGLE_TXD_RATE); 3366193240Ssam if ((Format & EAGLE_TXD_FORMAT_HT) == 0) { 3367193240Ssam ni->ni_txrate = mwl_cvtlegacyrix( 3368193240Ssam ni->ni_txrate); 3369193240Ssam } else 3370193240Ssam ni->ni_txrate |= IEEE80211_RATE_MCS; 3371193240Ssam sc->sc_stats.mst_tx_rate = ni->ni_txrate; 3372193240Ssam } else { 3373193240Ssam if (status & EAGLE_TXD_STATUS_FAILED_LINK_ERROR) 3374193240Ssam sc->sc_stats.mst_tx_linkerror++; 3375193240Ssam if (status & EAGLE_TXD_STATUS_FAILED_XRETRY) 3376193240Ssam sc->sc_stats.mst_tx_xretries++; 3377193240Ssam if (status & EAGLE_TXD_STATUS_FAILED_AGING) 3378193240Ssam sc->sc_stats.mst_tx_aging++; 3379193240Ssam if (bf->bf_m->m_flags & M_FF) 3380193240Ssam sc->sc_stats.mst_ff_txerr++; 3381193240Ssam } 3382287197Sglebius if (bf->bf_m->m_flags & M_TXCB) 3383193240Ssam /* XXX strip fw len in case header inspected */ 3384193240Ssam m_adj(bf->bf_m, sizeof(uint16_t)); 3385287197Sglebius ieee80211_tx_complete(ni, bf->bf_m, 3386287197Sglebius (status & EAGLE_TXD_STATUS_OK) == 0); 3387287197Sglebius } else 3388287197Sglebius m_freem(bf->bf_m); 3389193240Ssam ds->Status = htole32(EAGLE_TXD_STATUS_IDLE); 3390193240Ssam 3391193240Ssam bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 3392193240Ssam BUS_DMASYNC_POSTWRITE); 3393193240Ssam bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3394193240Ssam 3395193240Ssam mwl_puttxbuf_tail(txq, bf); 3396193240Ssam } 3397193240Ssam return nreaped; 3398193240Ssam#undef EAGLE_TXD_STATUS_MCAST 3399193240Ssam} 3400193240Ssam 3401193240Ssam/* 3402193240Ssam * Deferred processing of transmit interrupt; special-cased 3403193240Ssam * for four hardware queues, 0-3. 3404193240Ssam */ 3405193240Ssamstatic void 3406193240Ssammwl_tx_proc(void *arg, int npending) 3407193240Ssam{ 3408193240Ssam struct mwl_softc *sc = arg; 3409193240Ssam int nreaped; 3410193240Ssam 3411193240Ssam /* 3412193240Ssam * Process each active queue. 3413193240Ssam */ 3414193240Ssam nreaped = 0; 3415193240Ssam if (!STAILQ_EMPTY(&sc->sc_txq[0].active)) 3416193240Ssam nreaped += mwl_tx_processq(sc, &sc->sc_txq[0]); 3417193240Ssam if (!STAILQ_EMPTY(&sc->sc_txq[1].active)) 3418193240Ssam nreaped += mwl_tx_processq(sc, &sc->sc_txq[1]); 3419193240Ssam if (!STAILQ_EMPTY(&sc->sc_txq[2].active)) 3420193240Ssam nreaped += mwl_tx_processq(sc, &sc->sc_txq[2]); 3421193240Ssam if (!STAILQ_EMPTY(&sc->sc_txq[3].active)) 3422193240Ssam nreaped += mwl_tx_processq(sc, &sc->sc_txq[3]); 3423193240Ssam 3424193240Ssam if (nreaped != 0) { 3425199559Sjhb sc->sc_tx_timer = 0; 3426287197Sglebius if (mbufq_first(&sc->sc_snd) != NULL) { 3427193240Ssam /* NB: kick fw; the tx thread may have been preempted */ 3428193240Ssam mwl_hal_txstart(sc->sc_mh, 0); 3429287197Sglebius mwl_start(sc); 3430193240Ssam } 3431193240Ssam } 3432193240Ssam} 3433193240Ssam 3434193240Ssamstatic void 3435193240Ssammwl_tx_draintxq(struct mwl_softc *sc, struct mwl_txq *txq) 3436193240Ssam{ 3437193240Ssam struct ieee80211_node *ni; 3438193240Ssam struct mwl_txbuf *bf; 3439193240Ssam u_int ix; 3440193240Ssam 3441193240Ssam /* 3442193240Ssam * NB: this assumes output has been stopped and 3443193240Ssam * we do not need to block mwl_tx_tasklet 3444193240Ssam */ 3445193240Ssam for (ix = 0;; ix++) { 3446193240Ssam MWL_TXQ_LOCK(txq); 3447193240Ssam bf = STAILQ_FIRST(&txq->active); 3448193240Ssam if (bf == NULL) { 3449193240Ssam MWL_TXQ_UNLOCK(txq); 3450193240Ssam break; 3451193240Ssam } 3452193240Ssam STAILQ_REMOVE_HEAD(&txq->active, bf_list); 3453193240Ssam MWL_TXQ_UNLOCK(txq); 3454193240Ssam#ifdef MWL_DEBUG 3455193240Ssam if (sc->sc_debug & MWL_DEBUG_RESET) { 3456287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 3457193240Ssam const struct mwltxrec *tr = 3458193240Ssam mtod(bf->bf_m, const struct mwltxrec *); 3459193240Ssam mwl_printtxbuf(bf, txq->qnum, ix); 3460193240Ssam ieee80211_dump_pkt(ic, (const uint8_t *)&tr->wh, 3461193240Ssam bf->bf_m->m_len - sizeof(tr->fwlen), 0, -1); 3462193240Ssam } 3463193240Ssam#endif /* MWL_DEBUG */ 3464193240Ssam bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3465193240Ssam ni = bf->bf_node; 3466193240Ssam if (ni != NULL) { 3467193240Ssam /* 3468193240Ssam * Reclaim node reference. 3469193240Ssam */ 3470193240Ssam ieee80211_free_node(ni); 3471193240Ssam } 3472193240Ssam m_freem(bf->bf_m); 3473193240Ssam 3474193240Ssam mwl_puttxbuf_tail(txq, bf); 3475193240Ssam } 3476193240Ssam} 3477193240Ssam 3478193240Ssam/* 3479193240Ssam * Drain the transmit queues and reclaim resources. 3480193240Ssam */ 3481193240Ssamstatic void 3482193240Ssammwl_draintxq(struct mwl_softc *sc) 3483193240Ssam{ 3484193240Ssam int i; 3485193240Ssam 3486193240Ssam for (i = 0; i < MWL_NUM_TX_QUEUES; i++) 3487193240Ssam mwl_tx_draintxq(sc, &sc->sc_txq[i]); 3488199559Sjhb sc->sc_tx_timer = 0; 3489193240Ssam} 3490193240Ssam 3491193240Ssam#ifdef MWL_DIAGAPI 3492193240Ssam/* 3493193240Ssam * Reset the transmit queues to a pristine state after a fw download. 3494193240Ssam */ 3495193240Ssamstatic void 3496193240Ssammwl_resettxq(struct mwl_softc *sc) 3497193240Ssam{ 3498193240Ssam int i; 3499193240Ssam 3500193240Ssam for (i = 0; i < MWL_NUM_TX_QUEUES; i++) 3501193240Ssam mwl_txq_reset(sc, &sc->sc_txq[i]); 3502193240Ssam} 3503193240Ssam#endif /* MWL_DIAGAPI */ 3504193240Ssam 3505193240Ssam/* 3506193240Ssam * Clear the transmit queues of any frames submitted for the 3507193240Ssam * specified vap. This is done when the vap is deleted so we 3508193240Ssam * don't potentially reference the vap after it is gone. 3509193240Ssam * Note we cannot remove the frames; we only reclaim the node 3510193240Ssam * reference. 3511193240Ssam */ 3512193240Ssamstatic void 3513193240Ssammwl_cleartxq(struct mwl_softc *sc, struct ieee80211vap *vap) 3514193240Ssam{ 3515193240Ssam struct mwl_txq *txq; 3516193240Ssam struct mwl_txbuf *bf; 3517193240Ssam int i; 3518193240Ssam 3519193240Ssam for (i = 0; i < MWL_NUM_TX_QUEUES; i++) { 3520193240Ssam txq = &sc->sc_txq[i]; 3521193240Ssam MWL_TXQ_LOCK(txq); 3522193240Ssam STAILQ_FOREACH(bf, &txq->active, bf_list) { 3523193240Ssam struct ieee80211_node *ni = bf->bf_node; 3524193240Ssam if (ni != NULL && ni->ni_vap == vap) { 3525193240Ssam bf->bf_node = NULL; 3526193240Ssam ieee80211_free_node(ni); 3527193240Ssam } 3528193240Ssam } 3529193240Ssam MWL_TXQ_UNLOCK(txq); 3530193240Ssam } 3531193240Ssam} 3532193240Ssam 3533195377Ssamstatic int 3534195377Ssammwl_recv_action(struct ieee80211_node *ni, const struct ieee80211_frame *wh, 3535195377Ssam const uint8_t *frm, const uint8_t *efrm) 3536193240Ssam{ 3537287197Sglebius struct mwl_softc *sc = ni->ni_ic->ic_softc; 3538193240Ssam const struct ieee80211_action *ia; 3539193240Ssam 3540193240Ssam ia = (const struct ieee80211_action *) frm; 3541193240Ssam if (ia->ia_category == IEEE80211_ACTION_CAT_HT && 3542193240Ssam ia->ia_action == IEEE80211_ACTION_HT_MIMOPWRSAVE) { 3543193240Ssam const struct ieee80211_action_ht_mimopowersave *mps = 3544193240Ssam (const struct ieee80211_action_ht_mimopowersave *) ia; 3545193240Ssam 3546193240Ssam mwl_hal_setmimops(sc->sc_mh, ni->ni_macaddr, 3547193240Ssam mps->am_control & IEEE80211_A_HT_MIMOPWRSAVE_ENA, 3548193240Ssam MS(mps->am_control, IEEE80211_A_HT_MIMOPWRSAVE_MODE)); 3549195377Ssam return 0; 3550193240Ssam } else 3551195377Ssam return sc->sc_recv_action(ni, wh, frm, efrm); 3552193240Ssam} 3553193240Ssam 3554193240Ssamstatic int 3555193240Ssammwl_addba_request(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, 3556193240Ssam int dialogtoken, int baparamset, int batimeout) 3557193240Ssam{ 3558287197Sglebius struct mwl_softc *sc = ni->ni_ic->ic_softc; 3559195171Ssam struct ieee80211vap *vap = ni->ni_vap; 3560193240Ssam struct mwl_node *mn = MWL_NODE(ni); 3561193240Ssam struct mwl_bastate *bas; 3562193240Ssam 3563193240Ssam bas = tap->txa_private; 3564193240Ssam if (bas == NULL) { 3565193240Ssam const MWL_HAL_BASTREAM *sp; 3566193240Ssam /* 3567193240Ssam * Check for a free BA stream slot. 3568193240Ssam */ 3569193240Ssam#if MWL_MAXBA > 3 3570193240Ssam if (mn->mn_ba[3].bastream == NULL) 3571193240Ssam bas = &mn->mn_ba[3]; 3572193240Ssam else 3573193240Ssam#endif 3574193240Ssam#if MWL_MAXBA > 2 3575193240Ssam if (mn->mn_ba[2].bastream == NULL) 3576193240Ssam bas = &mn->mn_ba[2]; 3577193240Ssam else 3578193240Ssam#endif 3579193240Ssam#if MWL_MAXBA > 1 3580193240Ssam if (mn->mn_ba[1].bastream == NULL) 3581193240Ssam bas = &mn->mn_ba[1]; 3582193240Ssam else 3583193240Ssam#endif 3584193240Ssam#if MWL_MAXBA > 0 3585193240Ssam if (mn->mn_ba[0].bastream == NULL) 3586193240Ssam bas = &mn->mn_ba[0]; 3587193240Ssam else 3588193240Ssam#endif 3589193240Ssam { 3590193240Ssam /* sta already has max BA streams */ 3591193240Ssam /* XXX assign BA stream to highest priority tid */ 3592193240Ssam DPRINTF(sc, MWL_DEBUG_AMPDU, 3593193240Ssam "%s: already has max bastreams\n", __func__); 3594193240Ssam sc->sc_stats.mst_ampdu_reject++; 3595193240Ssam return 0; 3596193240Ssam } 3597193240Ssam /* NB: no held reference to ni */ 3598195171Ssam sp = mwl_hal_bastream_alloc(MWL_VAP(vap)->mv_hvap, 3599195171Ssam (baparamset & IEEE80211_BAPS_POLICY_IMMEDIATE) != 0, 3600234324Sadrian ni->ni_macaddr, tap->txa_tid, ni->ni_htparam, 3601195171Ssam ni, tap); 3602193240Ssam if (sp == NULL) { 3603193240Ssam /* 3604193240Ssam * No available stream, return 0 so no 3605193240Ssam * a-mpdu aggregation will be done. 3606193240Ssam */ 3607193240Ssam DPRINTF(sc, MWL_DEBUG_AMPDU, 3608193240Ssam "%s: no bastream available\n", __func__); 3609193240Ssam sc->sc_stats.mst_ampdu_nostream++; 3610193240Ssam return 0; 3611193240Ssam } 3612193240Ssam DPRINTF(sc, MWL_DEBUG_AMPDU, "%s: alloc bastream %p\n", 3613193240Ssam __func__, sp); 3614193240Ssam /* NB: qos is left zero so we won't match in mwl_tx_start */ 3615193240Ssam bas->bastream = sp; 3616193240Ssam tap->txa_private = bas; 3617193240Ssam } 3618193240Ssam /* fetch current seq# from the firmware; if available */ 3619193240Ssam if (mwl_hal_bastream_get_seqno(sc->sc_mh, bas->bastream, 3620195171Ssam vap->iv_opmode == IEEE80211_M_STA ? vap->iv_myaddr : ni->ni_macaddr, 3621193240Ssam &tap->txa_start) != 0) 3622193240Ssam tap->txa_start = 0; 3623193240Ssam return sc->sc_addba_request(ni, tap, dialogtoken, baparamset, batimeout); 3624193240Ssam} 3625193240Ssam 3626193240Ssamstatic int 3627193240Ssammwl_addba_response(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, 3628193240Ssam int code, int baparamset, int batimeout) 3629193240Ssam{ 3630287197Sglebius struct mwl_softc *sc = ni->ni_ic->ic_softc; 3631193240Ssam struct mwl_bastate *bas; 3632193240Ssam 3633193240Ssam bas = tap->txa_private; 3634193240Ssam if (bas == NULL) { 3635193240Ssam /* XXX should not happen */ 3636193240Ssam DPRINTF(sc, MWL_DEBUG_AMPDU, 3637234324Sadrian "%s: no BA stream allocated, TID %d\n", 3638234324Sadrian __func__, tap->txa_tid); 3639193240Ssam sc->sc_stats.mst_addba_nostream++; 3640193240Ssam return 0; 3641193240Ssam } 3642193240Ssam if (code == IEEE80211_STATUS_SUCCESS) { 3643195171Ssam struct ieee80211vap *vap = ni->ni_vap; 3644193240Ssam int bufsiz, error; 3645193240Ssam 3646193240Ssam /* 3647193240Ssam * Tell the firmware to setup the BA stream; 3648193240Ssam * we know resources are available because we 3649193240Ssam * pre-allocated one before forming the request. 3650193240Ssam */ 3651193240Ssam bufsiz = MS(baparamset, IEEE80211_BAPS_BUFSIZ); 3652193240Ssam if (bufsiz == 0) 3653193240Ssam bufsiz = IEEE80211_AGGR_BAWMAX; 3654195171Ssam error = mwl_hal_bastream_create(MWL_VAP(vap)->mv_hvap, 3655195171Ssam bas->bastream, bufsiz, bufsiz, tap->txa_start); 3656193240Ssam if (error != 0) { 3657193240Ssam /* 3658193240Ssam * Setup failed, return immediately so no a-mpdu 3659193240Ssam * aggregation will be done. 3660193240Ssam */ 3661193240Ssam mwl_hal_bastream_destroy(sc->sc_mh, bas->bastream); 3662193240Ssam mwl_bastream_free(bas); 3663193240Ssam tap->txa_private = NULL; 3664193240Ssam 3665193240Ssam DPRINTF(sc, MWL_DEBUG_AMPDU, 3666234324Sadrian "%s: create failed, error %d, bufsiz %d TID %d " 3667193240Ssam "htparam 0x%x\n", __func__, error, bufsiz, 3668234324Sadrian tap->txa_tid, ni->ni_htparam); 3669193240Ssam sc->sc_stats.mst_bacreate_failed++; 3670193240Ssam return 0; 3671193240Ssam } 3672193240Ssam /* NB: cache txq to avoid ptr indirect */ 3673234324Sadrian mwl_bastream_setup(bas, tap->txa_tid, bas->bastream->txq); 3674193240Ssam DPRINTF(sc, MWL_DEBUG_AMPDU, 3675234324Sadrian "%s: bastream %p assigned to txq %d TID %d bufsiz %d " 3676193240Ssam "htparam 0x%x\n", __func__, bas->bastream, 3677234324Sadrian bas->txq, tap->txa_tid, bufsiz, ni->ni_htparam); 3678193240Ssam } else { 3679193240Ssam /* 3680193240Ssam * Other side NAK'd us; return the resources. 3681193240Ssam */ 3682193240Ssam DPRINTF(sc, MWL_DEBUG_AMPDU, 3683193240Ssam "%s: request failed with code %d, destroy bastream %p\n", 3684193240Ssam __func__, code, bas->bastream); 3685193240Ssam mwl_hal_bastream_destroy(sc->sc_mh, bas->bastream); 3686193240Ssam mwl_bastream_free(bas); 3687193240Ssam tap->txa_private = NULL; 3688193240Ssam } 3689193240Ssam /* NB: firmware sends BAR so we don't need to */ 3690193240Ssam return sc->sc_addba_response(ni, tap, code, baparamset, batimeout); 3691193240Ssam} 3692193240Ssam 3693193240Ssamstatic void 3694193240Ssammwl_addba_stop(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap) 3695193240Ssam{ 3696287197Sglebius struct mwl_softc *sc = ni->ni_ic->ic_softc; 3697193240Ssam struct mwl_bastate *bas; 3698193240Ssam 3699193240Ssam bas = tap->txa_private; 3700193240Ssam if (bas != NULL) { 3701193240Ssam DPRINTF(sc, MWL_DEBUG_AMPDU, "%s: destroy bastream %p\n", 3702193240Ssam __func__, bas->bastream); 3703193240Ssam mwl_hal_bastream_destroy(sc->sc_mh, bas->bastream); 3704193240Ssam mwl_bastream_free(bas); 3705193240Ssam tap->txa_private = NULL; 3706193240Ssam } 3707193240Ssam sc->sc_addba_stop(ni, tap); 3708193240Ssam} 3709193240Ssam 3710193240Ssam/* 3711193240Ssam * Setup the rx data structures. This should only be 3712193240Ssam * done once or we may get out of sync with the firmware. 3713193240Ssam */ 3714193240Ssamstatic int 3715193240Ssammwl_startrecv(struct mwl_softc *sc) 3716193240Ssam{ 3717193240Ssam if (!sc->sc_recvsetup) { 3718193240Ssam struct mwl_rxbuf *bf, *prev; 3719193240Ssam struct mwl_rxdesc *ds; 3720193240Ssam 3721193240Ssam prev = NULL; 3722193240Ssam STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 3723193240Ssam int error = mwl_rxbuf_init(sc, bf); 3724193240Ssam if (error != 0) { 3725193240Ssam DPRINTF(sc, MWL_DEBUG_RECV, 3726193240Ssam "%s: mwl_rxbuf_init failed %d\n", 3727193240Ssam __func__, error); 3728193240Ssam return error; 3729193240Ssam } 3730193240Ssam if (prev != NULL) { 3731193240Ssam ds = prev->bf_desc; 3732193240Ssam ds->pPhysNext = htole32(bf->bf_daddr); 3733193240Ssam } 3734193240Ssam prev = bf; 3735193240Ssam } 3736193240Ssam if (prev != NULL) { 3737193240Ssam ds = prev->bf_desc; 3738193240Ssam ds->pPhysNext = 3739193240Ssam htole32(STAILQ_FIRST(&sc->sc_rxbuf)->bf_daddr); 3740193240Ssam } 3741193240Ssam sc->sc_recvsetup = 1; 3742193240Ssam } 3743193240Ssam mwl_mode_init(sc); /* set filters, etc. */ 3744193240Ssam return 0; 3745193240Ssam} 3746193240Ssam 3747193240Ssamstatic MWL_HAL_APMODE 3748193240Ssammwl_getapmode(const struct ieee80211vap *vap, struct ieee80211_channel *chan) 3749193240Ssam{ 3750193240Ssam MWL_HAL_APMODE mode; 3751193240Ssam 3752193240Ssam if (IEEE80211_IS_CHAN_HT(chan)) { 3753193656Ssam if (vap->iv_flags_ht & IEEE80211_FHT_PUREN) 3754193240Ssam mode = AP_MODE_N_ONLY; 3755193240Ssam else if (IEEE80211_IS_CHAN_5GHZ(chan)) 3756193240Ssam mode = AP_MODE_AandN; 3757193240Ssam else if (vap->iv_flags & IEEE80211_F_PUREG) 3758193240Ssam mode = AP_MODE_GandN; 3759193240Ssam else 3760193240Ssam mode = AP_MODE_BandGandN; 3761193240Ssam } else if (IEEE80211_IS_CHAN_ANYG(chan)) { 3762193240Ssam if (vap->iv_flags & IEEE80211_F_PUREG) 3763193240Ssam mode = AP_MODE_G_ONLY; 3764193240Ssam else 3765193240Ssam mode = AP_MODE_MIXED; 3766193240Ssam } else if (IEEE80211_IS_CHAN_B(chan)) 3767193240Ssam mode = AP_MODE_B_ONLY; 3768193240Ssam else if (IEEE80211_IS_CHAN_A(chan)) 3769193240Ssam mode = AP_MODE_A_ONLY; 3770193240Ssam else 3771193240Ssam mode = AP_MODE_MIXED; /* XXX should not happen? */ 3772193240Ssam return mode; 3773193240Ssam} 3774193240Ssam 3775193240Ssamstatic int 3776193240Ssammwl_setapmode(struct ieee80211vap *vap, struct ieee80211_channel *chan) 3777193240Ssam{ 3778193240Ssam struct mwl_hal_vap *hvap = MWL_VAP(vap)->mv_hvap; 3779193240Ssam return mwl_hal_setapmode(hvap, mwl_getapmode(vap, chan)); 3780193240Ssam} 3781193240Ssam 3782193240Ssam/* 3783193240Ssam * Set/change channels. 3784193240Ssam */ 3785193240Ssamstatic int 3786193240Ssammwl_chan_set(struct mwl_softc *sc, struct ieee80211_channel *chan) 3787193240Ssam{ 3788193240Ssam struct mwl_hal *mh = sc->sc_mh; 3789287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 3790193240Ssam MWL_HAL_CHANNEL hchan; 3791193240Ssam int maxtxpow; 3792193240Ssam 3793193240Ssam DPRINTF(sc, MWL_DEBUG_RESET, "%s: chan %u MHz/flags 0x%x\n", 3794193240Ssam __func__, chan->ic_freq, chan->ic_flags); 3795193240Ssam 3796193240Ssam /* 3797193240Ssam * Convert to a HAL channel description with 3798193240Ssam * the flags constrained to reflect the current 3799193240Ssam * operating mode. 3800193240Ssam */ 3801193240Ssam mwl_mapchan(&hchan, chan); 3802193240Ssam mwl_hal_intrset(mh, 0); /* disable interrupts */ 3803193240Ssam#if 0 3804193240Ssam mwl_draintxq(sc); /* clear pending tx frames */ 3805193240Ssam#endif 3806193240Ssam mwl_hal_setchannel(mh, &hchan); 3807193240Ssam /* 3808193240Ssam * Tx power is cap'd by the regulatory setting and 3809193240Ssam * possibly a user-set limit. We pass the min of 3810193240Ssam * these to the hal to apply them to the cal data 3811193240Ssam * for this channel. 3812193240Ssam * XXX min bound? 3813193240Ssam */ 3814193240Ssam maxtxpow = 2*chan->ic_maxregpower; 3815193240Ssam if (maxtxpow > ic->ic_txpowlimit) 3816193240Ssam maxtxpow = ic->ic_txpowlimit; 3817193240Ssam mwl_hal_settxpower(mh, &hchan, maxtxpow / 2); 3818193240Ssam /* NB: potentially change mcast/mgt rates */ 3819193240Ssam mwl_setcurchanrates(sc); 3820193240Ssam 3821193240Ssam /* 3822193240Ssam * Update internal state. 3823193240Ssam */ 3824193240Ssam sc->sc_tx_th.wt_chan_freq = htole16(chan->ic_freq); 3825193240Ssam sc->sc_rx_th.wr_chan_freq = htole16(chan->ic_freq); 3826193240Ssam if (IEEE80211_IS_CHAN_A(chan)) { 3827193240Ssam sc->sc_tx_th.wt_chan_flags = htole16(IEEE80211_CHAN_A); 3828193240Ssam sc->sc_rx_th.wr_chan_flags = htole16(IEEE80211_CHAN_A); 3829193240Ssam } else if (IEEE80211_IS_CHAN_ANYG(chan)) { 3830193240Ssam sc->sc_tx_th.wt_chan_flags = htole16(IEEE80211_CHAN_G); 3831193240Ssam sc->sc_rx_th.wr_chan_flags = htole16(IEEE80211_CHAN_G); 3832193240Ssam } else { 3833193240Ssam sc->sc_tx_th.wt_chan_flags = htole16(IEEE80211_CHAN_B); 3834193240Ssam sc->sc_rx_th.wr_chan_flags = htole16(IEEE80211_CHAN_B); 3835193240Ssam } 3836193240Ssam sc->sc_curchan = hchan; 3837193240Ssam mwl_hal_intrset(mh, sc->sc_imask); 3838193240Ssam 3839193240Ssam return 0; 3840193240Ssam} 3841193240Ssam 3842193240Ssamstatic void 3843193240Ssammwl_scan_start(struct ieee80211com *ic) 3844193240Ssam{ 3845287197Sglebius struct mwl_softc *sc = ic->ic_softc; 3846193240Ssam 3847193240Ssam DPRINTF(sc, MWL_DEBUG_STATE, "%s\n", __func__); 3848193240Ssam} 3849193240Ssam 3850193240Ssamstatic void 3851193240Ssammwl_scan_end(struct ieee80211com *ic) 3852193240Ssam{ 3853287197Sglebius struct mwl_softc *sc = ic->ic_softc; 3854193240Ssam 3855193240Ssam DPRINTF(sc, MWL_DEBUG_STATE, "%s\n", __func__); 3856193240Ssam} 3857193240Ssam 3858193240Ssamstatic void 3859193240Ssammwl_set_channel(struct ieee80211com *ic) 3860193240Ssam{ 3861287197Sglebius struct mwl_softc *sc = ic->ic_softc; 3862193240Ssam 3863193240Ssam (void) mwl_chan_set(sc, ic->ic_curchan); 3864193240Ssam} 3865193240Ssam 3866193240Ssam/* 3867193240Ssam * Handle a channel switch request. We inform the firmware 3868193240Ssam * and mark the global state to suppress various actions. 3869193240Ssam * NB: we issue only one request to the fw; we may be called 3870193240Ssam * multiple times if there are multiple vap's. 3871193240Ssam */ 3872193240Ssamstatic void 3873193240Ssammwl_startcsa(struct ieee80211vap *vap) 3874193240Ssam{ 3875193240Ssam struct ieee80211com *ic = vap->iv_ic; 3876287197Sglebius struct mwl_softc *sc = ic->ic_softc; 3877193240Ssam MWL_HAL_CHANNEL hchan; 3878193240Ssam 3879193240Ssam if (sc->sc_csapending) 3880193240Ssam return; 3881193240Ssam 3882193240Ssam mwl_mapchan(&hchan, ic->ic_csa_newchan); 3883193240Ssam /* 1 =>'s quiet channel */ 3884193240Ssam mwl_hal_setchannelswitchie(sc->sc_mh, &hchan, 1, ic->ic_csa_count); 3885193240Ssam sc->sc_csapending = 1; 3886193240Ssam} 3887193240Ssam 3888193240Ssam/* 3889193240Ssam * Plumb any static WEP key for the station. This is 3890193240Ssam * necessary as we must propagate the key from the 3891193240Ssam * global key table of the vap to each sta db entry. 3892193240Ssam */ 3893193240Ssamstatic void 3894193240Ssammwl_setanywepkey(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN]) 3895193240Ssam{ 3896193240Ssam if ((vap->iv_flags & (IEEE80211_F_PRIVACY|IEEE80211_F_WPA)) == 3897193240Ssam IEEE80211_F_PRIVACY && 3898193240Ssam vap->iv_def_txkey != IEEE80211_KEYIX_NONE && 3899193240Ssam vap->iv_nw_keys[vap->iv_def_txkey].wk_keyix != IEEE80211_KEYIX_NONE) 3900288635Sadrian (void) _mwl_key_set(vap, &vap->iv_nw_keys[vap->iv_def_txkey], 3901288635Sadrian mac); 3902193240Ssam} 3903193240Ssam 3904193240Ssamstatic int 3905193240Ssammwl_peerstadb(struct ieee80211_node *ni, int aid, int staid, MWL_HAL_PEERINFO *pi) 3906193240Ssam{ 3907193240Ssam#define WME(ie) ((const struct ieee80211_wme_info *) ie) 3908193240Ssam struct ieee80211vap *vap = ni->ni_vap; 3909193240Ssam struct mwl_hal_vap *hvap; 3910193240Ssam int error; 3911193240Ssam 3912193240Ssam if (vap->iv_opmode == IEEE80211_M_WDS) { 3913193240Ssam /* 3914193240Ssam * WDS vap's do not have a f/w vap; instead they piggyback 3915193240Ssam * on an AP vap and we must install the sta db entry and 3916193240Ssam * crypto state using that AP's handle (the WDS vap has none). 3917193240Ssam */ 3918193240Ssam hvap = MWL_VAP(vap)->mv_ap_hvap; 3919193240Ssam } else 3920193240Ssam hvap = MWL_VAP(vap)->mv_hvap; 3921193240Ssam error = mwl_hal_newstation(hvap, ni->ni_macaddr, 3922193240Ssam aid, staid, pi, 3923193240Ssam ni->ni_flags & (IEEE80211_NODE_QOS | IEEE80211_NODE_HT), 3924193240Ssam ni->ni_ies.wme_ie != NULL ? WME(ni->ni_ies.wme_ie)->wme_info : 0); 3925193240Ssam if (error == 0) { 3926193240Ssam /* 3927193240Ssam * Setup security for this station. For sta mode this is 3928193240Ssam * needed even though do the same thing on transition to 3929193240Ssam * AUTH state because the call to mwl_hal_newstation 3930193240Ssam * clobbers the crypto state we setup. 3931193240Ssam */ 3932193240Ssam mwl_setanywepkey(vap, ni->ni_macaddr); 3933193240Ssam } 3934193240Ssam return error; 3935193240Ssam#undef WME 3936193240Ssam} 3937193240Ssam 3938193240Ssamstatic void 3939193240Ssammwl_setglobalkeys(struct ieee80211vap *vap) 3940193240Ssam{ 3941193240Ssam struct ieee80211_key *wk; 3942193240Ssam 3943193240Ssam wk = &vap->iv_nw_keys[0]; 3944193240Ssam for (; wk < &vap->iv_nw_keys[IEEE80211_WEP_NKID]; wk++) 3945193240Ssam if (wk->wk_keyix != IEEE80211_KEYIX_NONE) 3946288635Sadrian (void) _mwl_key_set(vap, wk, vap->iv_myaddr); 3947193240Ssam} 3948193240Ssam 3949193240Ssam/* 3950195171Ssam * Convert a legacy rate set to a firmware bitmask. 3951195171Ssam */ 3952195171Ssamstatic uint32_t 3953195171Ssamget_rate_bitmap(const struct ieee80211_rateset *rs) 3954195171Ssam{ 3955195171Ssam uint32_t rates; 3956195171Ssam int i; 3957195171Ssam 3958195171Ssam rates = 0; 3959195171Ssam for (i = 0; i < rs->rs_nrates; i++) 3960195171Ssam switch (rs->rs_rates[i] & IEEE80211_RATE_VAL) { 3961195171Ssam case 2: rates |= 0x001; break; 3962195171Ssam case 4: rates |= 0x002; break; 3963195171Ssam case 11: rates |= 0x004; break; 3964195171Ssam case 22: rates |= 0x008; break; 3965195171Ssam case 44: rates |= 0x010; break; 3966195171Ssam case 12: rates |= 0x020; break; 3967195171Ssam case 18: rates |= 0x040; break; 3968195171Ssam case 24: rates |= 0x080; break; 3969195171Ssam case 36: rates |= 0x100; break; 3970195171Ssam case 48: rates |= 0x200; break; 3971195171Ssam case 72: rates |= 0x400; break; 3972195171Ssam case 96: rates |= 0x800; break; 3973195171Ssam case 108: rates |= 0x1000; break; 3974195171Ssam } 3975195171Ssam return rates; 3976195171Ssam} 3977195171Ssam 3978195171Ssam/* 3979195171Ssam * Construct an HT firmware bitmask from an HT rate set. 3980195171Ssam */ 3981195171Ssamstatic uint32_t 3982195171Ssamget_htrate_bitmap(const struct ieee80211_htrateset *rs) 3983195171Ssam{ 3984195171Ssam uint32_t rates; 3985195171Ssam int i; 3986195171Ssam 3987195171Ssam rates = 0; 3988195171Ssam for (i = 0; i < rs->rs_nrates; i++) { 3989195171Ssam if (rs->rs_rates[i] < 16) 3990195171Ssam rates |= 1<<rs->rs_rates[i]; 3991195171Ssam } 3992195171Ssam return rates; 3993195171Ssam} 3994195171Ssam 3995195171Ssam/* 3996195171Ssam * Craft station database entry for station. 3997195171Ssam * NB: use host byte order here, the hal handles byte swapping. 3998195171Ssam */ 3999195171Ssamstatic MWL_HAL_PEERINFO * 4000195171Ssammkpeerinfo(MWL_HAL_PEERINFO *pi, const struct ieee80211_node *ni) 4001195171Ssam{ 4002195171Ssam const struct ieee80211vap *vap = ni->ni_vap; 4003195171Ssam 4004195171Ssam memset(pi, 0, sizeof(*pi)); 4005195171Ssam pi->LegacyRateBitMap = get_rate_bitmap(&ni->ni_rates); 4006195171Ssam pi->CapInfo = ni->ni_capinfo; 4007195171Ssam if (ni->ni_flags & IEEE80211_NODE_HT) { 4008195171Ssam /* HT capabilities, etc */ 4009195171Ssam pi->HTCapabilitiesInfo = ni->ni_htcap; 4010195171Ssam /* XXX pi.HTCapabilitiesInfo */ 4011195171Ssam pi->MacHTParamInfo = ni->ni_htparam; 4012195171Ssam pi->HTRateBitMap = get_htrate_bitmap(&ni->ni_htrates); 4013195171Ssam pi->AddHtInfo.ControlChan = ni->ni_htctlchan; 4014195171Ssam pi->AddHtInfo.AddChan = ni->ni_ht2ndchan; 4015195171Ssam pi->AddHtInfo.OpMode = ni->ni_htopmode; 4016195171Ssam pi->AddHtInfo.stbc = ni->ni_htstbc; 4017195171Ssam 4018195171Ssam /* constrain according to local configuration */ 4019195171Ssam if ((vap->iv_flags_ht & IEEE80211_FHT_SHORTGI40) == 0) 4020195171Ssam pi->HTCapabilitiesInfo &= ~IEEE80211_HTCAP_SHORTGI40; 4021195171Ssam if ((vap->iv_flags_ht & IEEE80211_FHT_SHORTGI20) == 0) 4022195171Ssam pi->HTCapabilitiesInfo &= ~IEEE80211_HTCAP_SHORTGI20; 4023195171Ssam if (ni->ni_chw != 40) 4024195171Ssam pi->HTCapabilitiesInfo &= ~IEEE80211_HTCAP_CHWIDTH40; 4025195171Ssam } 4026195171Ssam return pi; 4027195171Ssam} 4028195171Ssam 4029195171Ssam/* 4030193240Ssam * Re-create the local sta db entry for a vap to ensure 4031193240Ssam * up to date WME state is pushed to the firmware. Because 4032193240Ssam * this resets crypto state this must be followed by a 4033193240Ssam * reload of any keys in the global key table. 4034193240Ssam */ 4035193240Ssamstatic int 4036193240Ssammwl_localstadb(struct ieee80211vap *vap) 4037193240Ssam{ 4038193240Ssam#define WME(ie) ((const struct ieee80211_wme_info *) ie) 4039193240Ssam struct mwl_hal_vap *hvap = MWL_VAP(vap)->mv_hvap; 4040193240Ssam struct ieee80211_node *bss; 4041195171Ssam MWL_HAL_PEERINFO pi; 4042193240Ssam int error; 4043193240Ssam 4044193240Ssam switch (vap->iv_opmode) { 4045193240Ssam case IEEE80211_M_STA: 4046193240Ssam bss = vap->iv_bss; 4047195171Ssam error = mwl_hal_newstation(hvap, vap->iv_myaddr, 0, 0, 4048195171Ssam vap->iv_state == IEEE80211_S_RUN ? 4049195171Ssam mkpeerinfo(&pi, bss) : NULL, 4050195171Ssam (bss->ni_flags & (IEEE80211_NODE_QOS | IEEE80211_NODE_HT)), 4051193240Ssam bss->ni_ies.wme_ie != NULL ? 4052193240Ssam WME(bss->ni_ies.wme_ie)->wme_info : 0); 4053193240Ssam if (error == 0) 4054193240Ssam mwl_setglobalkeys(vap); 4055193240Ssam break; 4056193240Ssam case IEEE80211_M_HOSTAP: 4057195618Srpaulo case IEEE80211_M_MBSS: 4058193240Ssam error = mwl_hal_newstation(hvap, vap->iv_myaddr, 4059193240Ssam 0, 0, NULL, vap->iv_flags & IEEE80211_F_WME, 0); 4060193240Ssam if (error == 0) 4061193240Ssam mwl_setglobalkeys(vap); 4062193240Ssam break; 4063193240Ssam default: 4064193240Ssam error = 0; 4065193240Ssam break; 4066193240Ssam } 4067193240Ssam return error; 4068193240Ssam#undef WME 4069193240Ssam} 4070193240Ssam 4071193240Ssamstatic int 4072193240Ssammwl_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 4073193240Ssam{ 4074193240Ssam struct mwl_vap *mvp = MWL_VAP(vap); 4075193240Ssam struct mwl_hal_vap *hvap = mvp->mv_hvap; 4076193240Ssam struct ieee80211com *ic = vap->iv_ic; 4077193240Ssam struct ieee80211_node *ni = NULL; 4078287197Sglebius struct mwl_softc *sc = ic->ic_softc; 4079193240Ssam struct mwl_hal *mh = sc->sc_mh; 4080193240Ssam enum ieee80211_state ostate = vap->iv_state; 4081193240Ssam int error; 4082193240Ssam 4083193240Ssam DPRINTF(sc, MWL_DEBUG_STATE, "%s: %s: %s -> %s\n", 4084193240Ssam vap->iv_ifp->if_xname, __func__, 4085193240Ssam ieee80211_state_name[ostate], ieee80211_state_name[nstate]); 4086193240Ssam 4087193240Ssam callout_stop(&sc->sc_timer); 4088193240Ssam /* 4089193240Ssam * Clear current radar detection state. 4090193240Ssam */ 4091193240Ssam if (ostate == IEEE80211_S_CAC) { 4092193240Ssam /* stop quiet mode radar detection */ 4093193240Ssam mwl_hal_setradardetection(mh, DR_CHK_CHANNEL_AVAILABLE_STOP); 4094193240Ssam } else if (sc->sc_radarena) { 4095193240Ssam /* stop in-service radar detection */ 4096193240Ssam mwl_hal_setradardetection(mh, DR_DFS_DISABLE); 4097193240Ssam sc->sc_radarena = 0; 4098193240Ssam } 4099193240Ssam /* 4100193240Ssam * Carry out per-state actions before doing net80211 work. 4101193240Ssam */ 4102193240Ssam if (nstate == IEEE80211_S_INIT) { 4103193240Ssam /* NB: only ap+sta vap's have a fw entity */ 4104193240Ssam if (hvap != NULL) 4105193240Ssam mwl_hal_stop(hvap); 4106193240Ssam } else if (nstate == IEEE80211_S_SCAN) { 4107193240Ssam mwl_hal_start(hvap); 4108193240Ssam /* NB: this disables beacon frames */ 4109193240Ssam mwl_hal_setinframode(hvap); 4110193240Ssam } else if (nstate == IEEE80211_S_AUTH) { 4111193240Ssam /* 4112193240Ssam * Must create a sta db entry in case a WEP key needs to 4113193240Ssam * be plumbed. This entry will be overwritten if we 4114193240Ssam * associate; otherwise it will be reclaimed on node free. 4115193240Ssam */ 4116193240Ssam ni = vap->iv_bss; 4117193240Ssam MWL_NODE(ni)->mn_hvap = hvap; 4118193240Ssam (void) mwl_peerstadb(ni, 0, 0, NULL); 4119193240Ssam } else if (nstate == IEEE80211_S_CSA) { 4120193240Ssam /* XXX move to below? */ 4121195618Srpaulo if (vap->iv_opmode == IEEE80211_M_HOSTAP || 4122195618Srpaulo vap->iv_opmode == IEEE80211_M_MBSS) 4123193240Ssam mwl_startcsa(vap); 4124193240Ssam } else if (nstate == IEEE80211_S_CAC) { 4125193240Ssam /* XXX move to below? */ 4126193240Ssam /* stop ap xmit and enable quiet mode radar detection */ 4127193240Ssam mwl_hal_setradardetection(mh, DR_CHK_CHANNEL_AVAILABLE_START); 4128193240Ssam } 4129193240Ssam 4130193240Ssam /* 4131193240Ssam * Invoke the parent method to do net80211 work. 4132193240Ssam */ 4133193240Ssam error = mvp->mv_newstate(vap, nstate, arg); 4134193240Ssam 4135193240Ssam /* 4136193240Ssam * Carry out work that must be done after net80211 runs; 4137193240Ssam * this work requires up to date state (e.g. iv_bss). 4138193240Ssam */ 4139193240Ssam if (error == 0 && nstate == IEEE80211_S_RUN) { 4140193240Ssam /* NB: collect bss node again, it may have changed */ 4141193240Ssam ni = vap->iv_bss; 4142193240Ssam 4143193240Ssam DPRINTF(sc, MWL_DEBUG_STATE, 4144193240Ssam "%s: %s(RUN): iv_flags 0x%08x bintvl %d bssid %s " 4145193240Ssam "capinfo 0x%04x chan %d\n", 4146193240Ssam vap->iv_ifp->if_xname, __func__, vap->iv_flags, 4147193240Ssam ni->ni_intval, ether_sprintf(ni->ni_bssid), ni->ni_capinfo, 4148193240Ssam ieee80211_chan2ieee(ic, ic->ic_curchan)); 4149193240Ssam 4150193240Ssam /* 4151195171Ssam * Recreate local sta db entry to update WME/HT state. 4152193240Ssam */ 4153193240Ssam mwl_localstadb(vap); 4154193240Ssam switch (vap->iv_opmode) { 4155193240Ssam case IEEE80211_M_HOSTAP: 4156195618Srpaulo case IEEE80211_M_MBSS: 4157193240Ssam if (ostate == IEEE80211_S_CAC) { 4158193240Ssam /* enable in-service radar detection */ 4159193240Ssam mwl_hal_setradardetection(mh, 4160193240Ssam DR_IN_SERVICE_MONITOR_START); 4161193240Ssam sc->sc_radarena = 1; 4162193240Ssam } 4163193240Ssam /* 4164193240Ssam * Allocate and setup the beacon frame 4165193240Ssam * (and related state). 4166193240Ssam */ 4167193240Ssam error = mwl_reset_vap(vap, IEEE80211_S_RUN); 4168193240Ssam if (error != 0) { 4169193240Ssam DPRINTF(sc, MWL_DEBUG_STATE, 4170193240Ssam "%s: beacon setup failed, error %d\n", 4171193240Ssam __func__, error); 4172193240Ssam goto bad; 4173193240Ssam } 4174193240Ssam /* NB: must be after setting up beacon */ 4175193240Ssam mwl_hal_start(hvap); 4176193240Ssam break; 4177193240Ssam case IEEE80211_M_STA: 4178193240Ssam DPRINTF(sc, MWL_DEBUG_STATE, "%s: %s: aid 0x%x\n", 4179193240Ssam vap->iv_ifp->if_xname, __func__, ni->ni_associd); 4180193240Ssam /* 4181193240Ssam * Set state now that we're associated. 4182193240Ssam */ 4183193240Ssam mwl_hal_setassocid(hvap, ni->ni_bssid, ni->ni_associd); 4184193240Ssam mwl_setrates(vap); 4185193240Ssam mwl_hal_setrtsthreshold(hvap, vap->iv_rtsthreshold); 4186195171Ssam if ((vap->iv_flags & IEEE80211_F_DWDS) && 4187195171Ssam sc->sc_ndwdsvaps++ == 0) 4188195171Ssam mwl_hal_setdwds(mh, 1); 4189193240Ssam break; 4190193240Ssam case IEEE80211_M_WDS: 4191193240Ssam DPRINTF(sc, MWL_DEBUG_STATE, "%s: %s: bssid %s\n", 4192193240Ssam vap->iv_ifp->if_xname, __func__, 4193193240Ssam ether_sprintf(ni->ni_bssid)); 4194193240Ssam mwl_seteapolformat(vap); 4195193240Ssam break; 4196193240Ssam default: 4197193240Ssam break; 4198193240Ssam } 4199193240Ssam /* 4200193240Ssam * Set CS mode according to operating channel; 4201193240Ssam * this mostly an optimization for 5GHz. 4202193240Ssam * 4203193240Ssam * NB: must follow mwl_hal_start which resets csmode 4204193240Ssam */ 4205193240Ssam if (IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan)) 4206193240Ssam mwl_hal_setcsmode(mh, CSMODE_AGGRESSIVE); 4207193240Ssam else 4208193240Ssam mwl_hal_setcsmode(mh, CSMODE_AUTO_ENA); 4209193240Ssam /* 4210193240Ssam * Start timer to prod firmware. 4211193240Ssam */ 4212193240Ssam if (sc->sc_ageinterval != 0) 4213193240Ssam callout_reset(&sc->sc_timer, sc->sc_ageinterval*hz, 4214193240Ssam mwl_agestations, sc); 4215193240Ssam } else if (nstate == IEEE80211_S_SLEEP) { 4216193240Ssam /* XXX set chip in power save */ 4217195171Ssam } else if ((vap->iv_flags & IEEE80211_F_DWDS) && 4218195171Ssam --sc->sc_ndwdsvaps == 0) 4219195171Ssam mwl_hal_setdwds(mh, 0); 4220193240Ssambad: 4221193240Ssam return error; 4222193240Ssam} 4223193240Ssam 4224193240Ssam/* 4225193240Ssam * Manage station id's; these are separate from AID's 4226193240Ssam * as AID's may have values out of the range of possible 4227193240Ssam * station id's acceptable to the firmware. 4228193240Ssam */ 4229193240Ssamstatic int 4230193240Ssamallocstaid(struct mwl_softc *sc, int aid) 4231193240Ssam{ 4232193240Ssam int staid; 4233193240Ssam 4234193240Ssam if (!(0 < aid && aid < MWL_MAXSTAID) || isset(sc->sc_staid, aid)) { 4235193240Ssam /* NB: don't use 0 */ 4236193240Ssam for (staid = 1; staid < MWL_MAXSTAID; staid++) 4237193240Ssam if (isclr(sc->sc_staid, staid)) 4238193240Ssam break; 4239193240Ssam } else 4240193240Ssam staid = aid; 4241193240Ssam setbit(sc->sc_staid, staid); 4242193240Ssam return staid; 4243193240Ssam} 4244193240Ssam 4245193240Ssamstatic void 4246193240Ssamdelstaid(struct mwl_softc *sc, int staid) 4247193240Ssam{ 4248193240Ssam clrbit(sc->sc_staid, staid); 4249193240Ssam} 4250193240Ssam 4251193240Ssam/* 4252193240Ssam * Setup driver-specific state for a newly associated node. 4253193240Ssam * Note that we're called also on a re-associate, the isnew 4254193240Ssam * param tells us if this is the first time or not. 4255193240Ssam */ 4256193240Ssamstatic void 4257193240Ssammwl_newassoc(struct ieee80211_node *ni, int isnew) 4258193240Ssam{ 4259193240Ssam struct ieee80211vap *vap = ni->ni_vap; 4260287197Sglebius struct mwl_softc *sc = vap->iv_ic->ic_softc; 4261193240Ssam struct mwl_node *mn = MWL_NODE(ni); 4262193240Ssam MWL_HAL_PEERINFO pi; 4263193240Ssam uint16_t aid; 4264193240Ssam int error; 4265193240Ssam 4266193240Ssam aid = IEEE80211_AID(ni->ni_associd); 4267193240Ssam if (isnew) { 4268193240Ssam mn->mn_staid = allocstaid(sc, aid); 4269193240Ssam mn->mn_hvap = MWL_VAP(vap)->mv_hvap; 4270193240Ssam } else { 4271193240Ssam mn = MWL_NODE(ni); 4272193240Ssam /* XXX reset BA stream? */ 4273193240Ssam } 4274193240Ssam DPRINTF(sc, MWL_DEBUG_NODE, "%s: mac %s isnew %d aid %d staid %d\n", 4275193240Ssam __func__, ether_sprintf(ni->ni_macaddr), isnew, aid, mn->mn_staid); 4276195171Ssam error = mwl_peerstadb(ni, aid, mn->mn_staid, mkpeerinfo(&pi, ni)); 4277193240Ssam if (error != 0) { 4278193240Ssam DPRINTF(sc, MWL_DEBUG_NODE, 4279193240Ssam "%s: error %d creating sta db entry\n", 4280193240Ssam __func__, error); 4281193240Ssam /* XXX how to deal with error? */ 4282193240Ssam } 4283193240Ssam} 4284193240Ssam 4285193240Ssam/* 4286193240Ssam * Periodically poke the firmware to age out station state 4287193240Ssam * (power save queues, pending tx aggregates). 4288193240Ssam */ 4289193240Ssamstatic void 4290193240Ssammwl_agestations(void *arg) 4291193240Ssam{ 4292193240Ssam struct mwl_softc *sc = arg; 4293193240Ssam 4294193240Ssam mwl_hal_setkeepalive(sc->sc_mh); 4295193240Ssam if (sc->sc_ageinterval != 0) /* NB: catch dynamic changes */ 4296195171Ssam callout_schedule(&sc->sc_timer, sc->sc_ageinterval*hz); 4297193240Ssam} 4298193240Ssam 4299193240Ssamstatic const struct mwl_hal_channel * 4300193240Ssamfindhalchannel(const MWL_HAL_CHANNELINFO *ci, int ieee) 4301193240Ssam{ 4302193240Ssam int i; 4303193240Ssam 4304193240Ssam for (i = 0; i < ci->nchannels; i++) { 4305193240Ssam const struct mwl_hal_channel *hc = &ci->channels[i]; 4306193240Ssam if (hc->ieee == ieee) 4307193240Ssam return hc; 4308193240Ssam } 4309193240Ssam return NULL; 4310193240Ssam} 4311193240Ssam 4312193240Ssamstatic int 4313193240Ssammwl_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *rd, 4314193240Ssam int nchan, struct ieee80211_channel chans[]) 4315193240Ssam{ 4316287197Sglebius struct mwl_softc *sc = ic->ic_softc; 4317193240Ssam struct mwl_hal *mh = sc->sc_mh; 4318193240Ssam const MWL_HAL_CHANNELINFO *ci; 4319193240Ssam int i; 4320193240Ssam 4321193240Ssam for (i = 0; i < nchan; i++) { 4322193240Ssam struct ieee80211_channel *c = &chans[i]; 4323193240Ssam const struct mwl_hal_channel *hc; 4324193240Ssam 4325193240Ssam if (IEEE80211_IS_CHAN_2GHZ(c)) { 4326193240Ssam mwl_hal_getchannelinfo(mh, MWL_FREQ_BAND_2DOT4GHZ, 4327193240Ssam IEEE80211_IS_CHAN_HT40(c) ? 4328193240Ssam MWL_CH_40_MHz_WIDTH : MWL_CH_20_MHz_WIDTH, &ci); 4329193240Ssam } else if (IEEE80211_IS_CHAN_5GHZ(c)) { 4330193240Ssam mwl_hal_getchannelinfo(mh, MWL_FREQ_BAND_5GHZ, 4331193240Ssam IEEE80211_IS_CHAN_HT40(c) ? 4332193240Ssam MWL_CH_40_MHz_WIDTH : MWL_CH_20_MHz_WIDTH, &ci); 4333193240Ssam } else { 4334287197Sglebius device_printf(sc->sc_dev, 4335193240Ssam "%s: channel %u freq %u/0x%x not 2.4/5GHz\n", 4336193240Ssam __func__, c->ic_ieee, c->ic_freq, c->ic_flags); 4337193240Ssam return EINVAL; 4338193240Ssam } 4339193240Ssam /* 4340193240Ssam * Verify channel has cal data and cap tx power. 4341193240Ssam */ 4342193240Ssam hc = findhalchannel(ci, c->ic_ieee); 4343193240Ssam if (hc != NULL) { 4344193240Ssam if (c->ic_maxpower > 2*hc->maxTxPow) 4345193240Ssam c->ic_maxpower = 2*hc->maxTxPow; 4346193240Ssam goto next; 4347193240Ssam } 4348193240Ssam if (IEEE80211_IS_CHAN_HT40(c)) { 4349193240Ssam /* 4350193240Ssam * Look for the extension channel since the 4351193240Ssam * hal table only has the primary channel. 4352193240Ssam */ 4353193240Ssam hc = findhalchannel(ci, c->ic_extieee); 4354193240Ssam if (hc != NULL) { 4355193240Ssam if (c->ic_maxpower > 2*hc->maxTxPow) 4356193240Ssam c->ic_maxpower = 2*hc->maxTxPow; 4357193240Ssam goto next; 4358193240Ssam } 4359193240Ssam } 4360287197Sglebius device_printf(sc->sc_dev, 4361193240Ssam "%s: no cal data for channel %u ext %u freq %u/0x%x\n", 4362193240Ssam __func__, c->ic_ieee, c->ic_extieee, 4363193240Ssam c->ic_freq, c->ic_flags); 4364193240Ssam return EINVAL; 4365193240Ssam next: 4366193240Ssam ; 4367193240Ssam } 4368193240Ssam return 0; 4369193240Ssam} 4370193240Ssam 4371193240Ssam#define IEEE80211_CHAN_HTG (IEEE80211_CHAN_HT|IEEE80211_CHAN_G) 4372193240Ssam#define IEEE80211_CHAN_HTA (IEEE80211_CHAN_HT|IEEE80211_CHAN_A) 4373193240Ssam 4374193240Ssamstatic void 4375193240Ssamaddht40channels(struct ieee80211_channel chans[], int maxchans, int *nchans, 4376193240Ssam const MWL_HAL_CHANNELINFO *ci, int flags) 4377193240Ssam{ 4378300241Savos int i, error; 4379193240Ssam 4380300241Savos for (i = 0; i < ci->nchannels; i++) { 4381300241Savos const struct mwl_hal_channel *hc = &ci->channels[i]; 4382193240Ssam 4383300241Savos error = ieee80211_add_channel_ht40(chans, maxchans, nchans, 4384300241Savos hc->ieee, hc->maxTxPow, flags); 4385300241Savos if (error != 0 && error != ENOENT) 4386300241Savos break; 4387193240Ssam } 4388193240Ssam} 4389193240Ssam 4390193240Ssamstatic void 4391193240Ssamaddchannels(struct ieee80211_channel chans[], int maxchans, int *nchans, 4392300241Savos const MWL_HAL_CHANNELINFO *ci, const uint8_t bands[]) 4393193240Ssam{ 4394300241Savos int i, error; 4395193240Ssam 4396300241Savos error = 0; 4397300241Savos for (i = 0; i < ci->nchannels && error == 0; i++) { 4398300241Savos const struct mwl_hal_channel *hc = &ci->channels[i]; 4399193240Ssam 4400300241Savos error = ieee80211_add_channel(chans, maxchans, nchans, 4401300241Savos hc->ieee, hc->freq, hc->maxTxPow, 0, bands); 4402193240Ssam } 4403193240Ssam} 4404193240Ssam 4405193240Ssamstatic void 4406193240Ssamgetchannels(struct mwl_softc *sc, int maxchans, int *nchans, 4407193240Ssam struct ieee80211_channel chans[]) 4408193240Ssam{ 4409193240Ssam const MWL_HAL_CHANNELINFO *ci; 4410300241Savos uint8_t bands[IEEE80211_MODE_BYTES]; 4411193240Ssam 4412193240Ssam /* 4413193240Ssam * Use the channel info from the hal to craft the 4414193240Ssam * channel list. Note that we pass back an unsorted 4415193240Ssam * list; the caller is required to sort it for us 4416193240Ssam * (if desired). 4417193240Ssam */ 4418193240Ssam *nchans = 0; 4419193240Ssam if (mwl_hal_getchannelinfo(sc->sc_mh, 4420300241Savos MWL_FREQ_BAND_2DOT4GHZ, MWL_CH_20_MHz_WIDTH, &ci) == 0) { 4421300241Savos memset(bands, 0, sizeof(bands)); 4422300241Savos setbit(bands, IEEE80211_MODE_11B); 4423300241Savos setbit(bands, IEEE80211_MODE_11G); 4424300241Savos setbit(bands, IEEE80211_MODE_11NG); 4425300241Savos addchannels(chans, maxchans, nchans, ci, bands); 4426300241Savos } 4427193240Ssam if (mwl_hal_getchannelinfo(sc->sc_mh, 4428300241Savos MWL_FREQ_BAND_5GHZ, MWL_CH_20_MHz_WIDTH, &ci) == 0) { 4429300241Savos memset(bands, 0, sizeof(bands)); 4430300241Savos setbit(bands, IEEE80211_MODE_11A); 4431300241Savos setbit(bands, IEEE80211_MODE_11NA); 4432300241Savos addchannels(chans, maxchans, nchans, ci, bands); 4433300241Savos } 4434193240Ssam if (mwl_hal_getchannelinfo(sc->sc_mh, 4435193240Ssam MWL_FREQ_BAND_2DOT4GHZ, MWL_CH_40_MHz_WIDTH, &ci) == 0) 4436193240Ssam addht40channels(chans, maxchans, nchans, ci, IEEE80211_CHAN_HTG); 4437193240Ssam if (mwl_hal_getchannelinfo(sc->sc_mh, 4438193240Ssam MWL_FREQ_BAND_5GHZ, MWL_CH_40_MHz_WIDTH, &ci) == 0) 4439193240Ssam addht40channels(chans, maxchans, nchans, ci, IEEE80211_CHAN_HTA); 4440193240Ssam} 4441193240Ssam 4442193240Ssamstatic void 4443193240Ssammwl_getradiocaps(struct ieee80211com *ic, 4444193240Ssam int maxchans, int *nchans, struct ieee80211_channel chans[]) 4445193240Ssam{ 4446287197Sglebius struct mwl_softc *sc = ic->ic_softc; 4447193240Ssam 4448193240Ssam getchannels(sc, maxchans, nchans, chans); 4449193240Ssam} 4450193240Ssam 4451193240Ssamstatic int 4452193240Ssammwl_getchannels(struct mwl_softc *sc) 4453193240Ssam{ 4454287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 4455193240Ssam 4456193240Ssam /* 4457193240Ssam * Use the channel info from the hal to craft the 4458193240Ssam * channel list for net80211. Note that we pass up 4459193240Ssam * an unsorted list; net80211 will sort it for us. 4460193240Ssam */ 4461193240Ssam memset(ic->ic_channels, 0, sizeof(ic->ic_channels)); 4462193240Ssam ic->ic_nchans = 0; 4463193240Ssam getchannels(sc, IEEE80211_CHAN_MAX, &ic->ic_nchans, ic->ic_channels); 4464193240Ssam 4465193240Ssam ic->ic_regdomain.regdomain = SKU_DEBUG; 4466193240Ssam ic->ic_regdomain.country = CTRY_DEFAULT; 4467193240Ssam ic->ic_regdomain.location = 'I'; 4468193240Ssam ic->ic_regdomain.isocc[0] = ' '; /* XXX? */ 4469193240Ssam ic->ic_regdomain.isocc[1] = ' '; 4470193240Ssam return (ic->ic_nchans == 0 ? EIO : 0); 4471193240Ssam} 4472193240Ssam#undef IEEE80211_CHAN_HTA 4473193240Ssam#undef IEEE80211_CHAN_HTG 4474193240Ssam 4475193240Ssam#ifdef MWL_DEBUG 4476193240Ssamstatic void 4477193240Ssammwl_printrxbuf(const struct mwl_rxbuf *bf, u_int ix) 4478193240Ssam{ 4479193240Ssam const struct mwl_rxdesc *ds = bf->bf_desc; 4480193240Ssam uint32_t status = le32toh(ds->Status); 4481193240Ssam 4482278532Smarius printf("R[%2u] (DS.V:%p DS.P:0x%jx) NEXT:%08x DATA:%08x RC:%02x%s\n" 4483193240Ssam " STAT:%02x LEN:%04x RSSI:%02x CHAN:%02x RATE:%02x QOS:%04x HT:%04x\n", 4484278532Smarius ix, ds, (uintmax_t)bf->bf_daddr, le32toh(ds->pPhysNext), 4485278532Smarius le32toh(ds->pPhysBuffData), ds->RxControl, 4486193240Ssam ds->RxControl != EAGLE_RXD_CTRL_DRIVER_OWN ? 4487193240Ssam "" : (status & EAGLE_RXD_STATUS_OK) ? " *" : " !", 4488193240Ssam ds->Status, le16toh(ds->PktLen), ds->RSSI, ds->Channel, 4489193240Ssam ds->Rate, le16toh(ds->QosCtrl), le16toh(ds->HtSig2)); 4490193240Ssam} 4491193240Ssam 4492193240Ssamstatic void 4493193240Ssammwl_printtxbuf(const struct mwl_txbuf *bf, u_int qnum, u_int ix) 4494193240Ssam{ 4495193240Ssam const struct mwl_txdesc *ds = bf->bf_desc; 4496193240Ssam uint32_t status = le32toh(ds->Status); 4497193240Ssam 4498193240Ssam printf("Q%u[%3u]", qnum, ix); 4499278532Smarius printf(" (DS.V:%p DS.P:0x%jx)\n", ds, (uintmax_t)bf->bf_daddr); 4500193240Ssam printf(" NEXT:%08x DATA:%08x LEN:%04x STAT:%08x%s\n", 4501193240Ssam le32toh(ds->pPhysNext), 4502193240Ssam le32toh(ds->PktPtr), le16toh(ds->PktLen), status, 4503193240Ssam status & EAGLE_TXD_STATUS_USED ? 4504193240Ssam "" : (status & 3) != 0 ? " *" : " !"); 4505193240Ssam printf(" RATE:%02x PRI:%x QOS:%04x SAP:%08x FORMAT:%04x\n", 4506193240Ssam ds->DataRate, ds->TxPriority, le16toh(ds->QosCtrl), 4507193240Ssam le32toh(ds->SapPktInfo), le16toh(ds->Format)); 4508193240Ssam#if MWL_TXDESC > 1 4509193240Ssam printf(" MULTIFRAMES:%u LEN:%04x %04x %04x %04x %04x %04x\n" 4510193240Ssam , le32toh(ds->multiframes) 4511193240Ssam , le16toh(ds->PktLenArray[0]), le16toh(ds->PktLenArray[1]) 4512193240Ssam , le16toh(ds->PktLenArray[2]), le16toh(ds->PktLenArray[3]) 4513193240Ssam , le16toh(ds->PktLenArray[4]), le16toh(ds->PktLenArray[5]) 4514193240Ssam ); 4515193240Ssam printf(" DATA:%08x %08x %08x %08x %08x %08x\n" 4516193240Ssam , le32toh(ds->PktPtrArray[0]), le32toh(ds->PktPtrArray[1]) 4517193240Ssam , le32toh(ds->PktPtrArray[2]), le32toh(ds->PktPtrArray[3]) 4518193240Ssam , le32toh(ds->PktPtrArray[4]), le32toh(ds->PktPtrArray[5]) 4519193240Ssam ); 4520193240Ssam#endif 4521193240Ssam#if 0 4522193240Ssam{ const uint8_t *cp = (const uint8_t *) ds; 4523193240Ssam int i; 4524193240Ssam for (i = 0; i < sizeof(struct mwl_txdesc); i++) { 4525193240Ssam printf("%02x ", cp[i]); 4526193240Ssam if (((i+1) % 16) == 0) 4527193240Ssam printf("\n"); 4528193240Ssam } 4529193240Ssam printf("\n"); 4530193240Ssam} 4531193240Ssam#endif 4532193240Ssam} 4533193240Ssam#endif /* MWL_DEBUG */ 4534193240Ssam 4535193240Ssam#if 0 4536193240Ssamstatic void 4537193240Ssammwl_txq_dump(struct mwl_txq *txq) 4538193240Ssam{ 4539193240Ssam struct mwl_txbuf *bf; 4540193240Ssam int i = 0; 4541193240Ssam 4542193240Ssam MWL_TXQ_LOCK(txq); 4543193240Ssam STAILQ_FOREACH(bf, &txq->active, bf_list) { 4544193240Ssam struct mwl_txdesc *ds = bf->bf_desc; 4545193240Ssam MWL_TXDESC_SYNC(txq, ds, 4546193240Ssam BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4547193240Ssam#ifdef MWL_DEBUG 4548193240Ssam mwl_printtxbuf(bf, txq->qnum, i); 4549193240Ssam#endif 4550193240Ssam i++; 4551193240Ssam } 4552193240Ssam MWL_TXQ_UNLOCK(txq); 4553193240Ssam} 4554193240Ssam#endif 4555193240Ssam 4556193240Ssamstatic void 4557199559Sjhbmwl_watchdog(void *arg) 4558193240Ssam{ 4559287197Sglebius struct mwl_softc *sc = arg; 4560193240Ssam 4561199559Sjhb callout_reset(&sc->sc_watchdog, hz, mwl_watchdog, sc); 4562199559Sjhb if (sc->sc_tx_timer == 0 || --sc->sc_tx_timer > 0) 4563199559Sjhb return; 4564199559Sjhb 4565287197Sglebius if (sc->sc_running && !sc->sc_invalid) { 4566193240Ssam if (mwl_hal_setkeepalive(sc->sc_mh)) 4567287197Sglebius device_printf(sc->sc_dev, 4568287197Sglebius "transmit timeout (firmware hung?)\n"); 4569193240Ssam else 4570287197Sglebius device_printf(sc->sc_dev, 4571287197Sglebius "transmit timeout\n"); 4572193240Ssam#if 0 4573287197Sglebius mwl_reset(sc); 4574193240Ssammwl_txq_dump(&sc->sc_txq[0]);/*XXX*/ 4575193240Ssam#endif 4576287197Sglebius counter_u64_add(sc->sc_ic.ic_oerrors, 1); 4577193240Ssam sc->sc_stats.mst_watchdog++; 4578193240Ssam } 4579193240Ssam} 4580193240Ssam 4581193240Ssam#ifdef MWL_DIAGAPI 4582193240Ssam/* 4583193240Ssam * Diagnostic interface to the HAL. This is used by various 4584193240Ssam * tools to do things like retrieve register contents for 4585193240Ssam * debugging. The mechanism is intentionally opaque so that 4586298955Spfg * it can change frequently w/o concern for compatibility. 4587193240Ssam */ 4588193240Ssamstatic int 4589193240Ssammwl_ioctl_diag(struct mwl_softc *sc, struct mwl_diag *md) 4590193240Ssam{ 4591193240Ssam struct mwl_hal *mh = sc->sc_mh; 4592193240Ssam u_int id = md->md_id & MWL_DIAG_ID; 4593193240Ssam void *indata = NULL; 4594193240Ssam void *outdata = NULL; 4595193240Ssam u_int32_t insize = md->md_in_size; 4596193240Ssam u_int32_t outsize = md->md_out_size; 4597193240Ssam int error = 0; 4598193240Ssam 4599193240Ssam if (md->md_id & MWL_DIAG_IN) { 4600193240Ssam /* 4601193240Ssam * Copy in data. 4602193240Ssam */ 4603193240Ssam indata = malloc(insize, M_TEMP, M_NOWAIT); 4604193240Ssam if (indata == NULL) { 4605193240Ssam error = ENOMEM; 4606193240Ssam goto bad; 4607193240Ssam } 4608193240Ssam error = copyin(md->md_in_data, indata, insize); 4609193240Ssam if (error) 4610193240Ssam goto bad; 4611193240Ssam } 4612193240Ssam if (md->md_id & MWL_DIAG_DYN) { 4613193240Ssam /* 4614193240Ssam * Allocate a buffer for the results (otherwise the HAL 4615193240Ssam * returns a pointer to a buffer where we can read the 4616193240Ssam * results). Note that we depend on the HAL leaving this 4617193240Ssam * pointer for us to use below in reclaiming the buffer; 4618193240Ssam * may want to be more defensive. 4619193240Ssam */ 4620193240Ssam outdata = malloc(outsize, M_TEMP, M_NOWAIT); 4621193240Ssam if (outdata == NULL) { 4622193240Ssam error = ENOMEM; 4623193240Ssam goto bad; 4624193240Ssam } 4625193240Ssam } 4626193240Ssam if (mwl_hal_getdiagstate(mh, id, indata, insize, &outdata, &outsize)) { 4627193240Ssam if (outsize < md->md_out_size) 4628193240Ssam md->md_out_size = outsize; 4629193240Ssam if (outdata != NULL) 4630193240Ssam error = copyout(outdata, md->md_out_data, 4631193240Ssam md->md_out_size); 4632193240Ssam } else { 4633193240Ssam error = EINVAL; 4634193240Ssam } 4635193240Ssambad: 4636193240Ssam if ((md->md_id & MWL_DIAG_IN) && indata != NULL) 4637193240Ssam free(indata, M_TEMP); 4638193240Ssam if ((md->md_id & MWL_DIAG_DYN) && outdata != NULL) 4639193240Ssam free(outdata, M_TEMP); 4640193240Ssam return error; 4641193240Ssam} 4642193240Ssam 4643193240Ssamstatic int 4644193240Ssammwl_ioctl_reset(struct mwl_softc *sc, struct mwl_diag *md) 4645193240Ssam{ 4646193240Ssam struct mwl_hal *mh = sc->sc_mh; 4647193240Ssam int error; 4648193240Ssam 4649193240Ssam MWL_LOCK_ASSERT(sc); 4650193240Ssam 4651193240Ssam if (md->md_id == 0 && mwl_hal_fwload(mh, NULL) != 0) { 4652193240Ssam device_printf(sc->sc_dev, "unable to load firmware\n"); 4653193240Ssam return EIO; 4654193240Ssam } 4655193240Ssam if (mwl_hal_gethwspecs(mh, &sc->sc_hwspecs) != 0) { 4656193240Ssam device_printf(sc->sc_dev, "unable to fetch h/w specs\n"); 4657193240Ssam return EIO; 4658193240Ssam } 4659193240Ssam error = mwl_setupdma(sc); 4660193240Ssam if (error != 0) { 4661193240Ssam /* NB: mwl_setupdma prints a msg */ 4662193240Ssam return error; 4663193240Ssam } 4664193240Ssam /* 4665193240Ssam * Reset tx/rx data structures; after reload we must 4666193240Ssam * re-start the driver's notion of the next xmit/recv. 4667193240Ssam */ 4668193240Ssam mwl_draintxq(sc); /* clear pending frames */ 4669193240Ssam mwl_resettxq(sc); /* rebuild tx q lists */ 4670193240Ssam sc->sc_rxnext = NULL; /* force rx to start at the list head */ 4671193240Ssam return 0; 4672193240Ssam} 4673193240Ssam#endif /* MWL_DIAGAPI */ 4674193240Ssam 4675287197Sglebiusstatic void 4676287197Sglebiusmwl_parent(struct ieee80211com *ic) 4677193240Ssam{ 4678287197Sglebius struct mwl_softc *sc = ic->ic_softc; 4679287197Sglebius int startall = 0; 4680193240Ssam 4681287197Sglebius MWL_LOCK(sc); 4682287197Sglebius if (ic->ic_nrunning > 0) { 4683287197Sglebius if (sc->sc_running) { 4684193240Ssam /* 4685193240Ssam * To avoid rescanning another access point, 4686193240Ssam * do not call mwl_init() here. Instead, 4687193240Ssam * only reflect promisc mode settings. 4688193240Ssam */ 4689193240Ssam mwl_mode_init(sc); 4690287197Sglebius } else { 4691193240Ssam /* 4692193240Ssam * Beware of being called during attach/detach 4693193240Ssam * to reset promiscuous mode. In that case we 4694193240Ssam * will still be marked UP but not RUNNING. 4695193240Ssam * However trying to re-init the interface 4696193240Ssam * is the wrong thing to do as we've already 4697193240Ssam * torn down much of our state. There's 4698193240Ssam * probably a better way to deal with this. 4699193240Ssam */ 4700193240Ssam if (!sc->sc_invalid) { 4701287197Sglebius mwl_init(sc); /* XXX lose error */ 4702193240Ssam startall = 1; 4703193240Ssam } 4704287197Sglebius } 4705287197Sglebius } else 4706287197Sglebius mwl_stop(sc); 4707287197Sglebius MWL_UNLOCK(sc); 4708287197Sglebius if (startall) 4709287197Sglebius ieee80211_start_all(ic); 4710287197Sglebius} 4711287197Sglebius 4712287197Sglebiusstatic int 4713287197Sglebiusmwl_ioctl(struct ieee80211com *ic, u_long cmd, void *data) 4714287197Sglebius{ 4715287197Sglebius struct mwl_softc *sc = ic->ic_softc; 4716287197Sglebius struct ifreq *ifr = data; 4717287197Sglebius int error = 0; 4718287197Sglebius 4719287197Sglebius switch (cmd) { 4720193240Ssam case SIOCGMVSTATS: 4721193240Ssam mwl_hal_gethwstats(sc->sc_mh, &sc->sc_stats.hw_stats); 4722287197Sglebius#if 0 4723193240Ssam /* NB: embed these numbers to get a consistent view */ 4724271810Sglebius sc->sc_stats.mst_tx_packets = 4725271810Sglebius ifp->if_get_counter(ifp, IFCOUNTER_OPACKETS); 4726271810Sglebius sc->sc_stats.mst_rx_packets = 4727271810Sglebius ifp->if_get_counter(ifp, IFCOUNTER_IPACKETS); 4728287197Sglebius#endif 4729193240Ssam /* 4730193240Ssam * NB: Drop the softc lock in case of a page fault; 4731193240Ssam * we'll accept any potential inconsisentcy in the 4732193240Ssam * statistics. The alternative is to copy the data 4733193240Ssam * to a local structure. 4734193240Ssam */ 4735332288Sbrooks return (copyout(&sc->sc_stats, ifr_data_get_ptr(ifr), 4736332288Sbrooks sizeof (sc->sc_stats))); 4737193240Ssam#ifdef MWL_DIAGAPI 4738193240Ssam case SIOCGMVDIAG: 4739193240Ssam /* XXX check privs */ 4740193240Ssam return mwl_ioctl_diag(sc, (struct mwl_diag *) ifr); 4741193240Ssam case SIOCGMVRESET: 4742193240Ssam /* XXX check privs */ 4743193240Ssam MWL_LOCK(sc); 4744193240Ssam error = mwl_ioctl_reset(sc,(struct mwl_diag *) ifr); 4745193240Ssam MWL_UNLOCK(sc); 4746193240Ssam break; 4747193240Ssam#endif /* MWL_DIAGAPI */ 4748193240Ssam default: 4749287197Sglebius error = ENOTTY; 4750193240Ssam break; 4751193240Ssam } 4752287197Sglebius return (error); 4753193240Ssam} 4754193240Ssam 4755193240Ssam#ifdef MWL_DEBUG 4756193240Ssamstatic int 4757193240Ssammwl_sysctl_debug(SYSCTL_HANDLER_ARGS) 4758193240Ssam{ 4759193240Ssam struct mwl_softc *sc = arg1; 4760193240Ssam int debug, error; 4761193240Ssam 4762193240Ssam debug = sc->sc_debug | (mwl_hal_getdebug(sc->sc_mh) << 24); 4763193240Ssam error = sysctl_handle_int(oidp, &debug, 0, req); 4764193240Ssam if (error || !req->newptr) 4765193240Ssam return error; 4766193240Ssam mwl_hal_setdebug(sc->sc_mh, debug >> 24); 4767193240Ssam sc->sc_debug = debug & 0x00ffffff; 4768193240Ssam return 0; 4769193240Ssam} 4770193240Ssam#endif /* MWL_DEBUG */ 4771193240Ssam 4772193240Ssamstatic void 4773193240Ssammwl_sysctlattach(struct mwl_softc *sc) 4774193240Ssam{ 4775193240Ssam#ifdef MWL_DEBUG 4776193240Ssam struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev); 4777193240Ssam struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev); 4778193240Ssam 4779193240Ssam sc->sc_debug = mwl_debug; 4780193240Ssam SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 4781193240Ssam "debug", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 4782193240Ssam mwl_sysctl_debug, "I", "control debugging printfs"); 4783193240Ssam#endif 4784193240Ssam} 4785193240Ssam 4786193240Ssam/* 4787193240Ssam * Announce various information on device/driver attach. 4788193240Ssam */ 4789193240Ssamstatic void 4790193240Ssammwl_announce(struct mwl_softc *sc) 4791193240Ssam{ 4792193240Ssam 4793287197Sglebius device_printf(sc->sc_dev, "Rev A%d hardware, v%d.%d.%d.%d firmware (regioncode %d)\n", 4794193240Ssam sc->sc_hwspecs.hwVersion, 4795193240Ssam (sc->sc_hwspecs.fwReleaseNumber>>24) & 0xff, 4796193240Ssam (sc->sc_hwspecs.fwReleaseNumber>>16) & 0xff, 4797193240Ssam (sc->sc_hwspecs.fwReleaseNumber>>8) & 0xff, 4798193240Ssam (sc->sc_hwspecs.fwReleaseNumber>>0) & 0xff, 4799193240Ssam sc->sc_hwspecs.regionCode); 4800193240Ssam sc->sc_fwrelease = sc->sc_hwspecs.fwReleaseNumber; 4801193240Ssam 4802193240Ssam if (bootverbose) { 4803193240Ssam int i; 4804193240Ssam for (i = 0; i <= WME_AC_VO; i++) { 4805193240Ssam struct mwl_txq *txq = sc->sc_ac2q[i]; 4806287197Sglebius device_printf(sc->sc_dev, "Use hw queue %u for %s traffic\n", 4807193240Ssam txq->qnum, ieee80211_wme_acnames[i]); 4808193240Ssam } 4809193240Ssam } 4810193240Ssam if (bootverbose || mwl_rxdesc != MWL_RXDESC) 4811287197Sglebius device_printf(sc->sc_dev, "using %u rx descriptors\n", mwl_rxdesc); 4812193240Ssam if (bootverbose || mwl_rxbuf != MWL_RXBUF) 4813287197Sglebius device_printf(sc->sc_dev, "using %u rx buffers\n", mwl_rxbuf); 4814193240Ssam if (bootverbose || mwl_txbuf != MWL_TXBUF) 4815287197Sglebius device_printf(sc->sc_dev, "using %u tx buffers\n", mwl_txbuf); 4816193240Ssam if (bootverbose && mwl_hal_ismbsscapable(sc->sc_mh)) 4817287197Sglebius device_printf(sc->sc_dev, "multi-bss support\n"); 4818193240Ssam#ifdef MWL_TX_NODROP 4819193240Ssam if (bootverbose) 4820287197Sglebius device_printf(sc->sc_dev, "no tx drop\n"); 4821193240Ssam#endif 4822193240Ssam} 4823