1/*- 2 * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD$"); 29 30#include <sys/param.h> 31#include <sys/module.h> 32#include <sys/systm.h> 33#include <sys/kernel.h> 34#include <sys/bus.h> 35#include <sys/endian.h> 36#include <sys/malloc.h> 37#include <sys/lock.h> 38#include <sys/mutex.h> 39#include <vm/uma.h> 40#include <machine/stdarg.h> 41#include <machine/resource.h> 42#include <machine/bus.h> 43#include <sys/rman.h> 44#include <arm/mv/mvreg.h> 45#include <arm/mv/mvvar.h> 46#include <dev/ofw/ofw_bus.h> 47#include <dev/ofw/ofw_bus_subr.h> 48#include "mvs.h" 49 50/* local prototypes */ 51static int mvs_setup_interrupt(device_t dev); 52static void mvs_intr(void *data); 53static int mvs_suspend(device_t dev); 54static int mvs_resume(device_t dev); 55static int mvs_ctlr_setup(device_t dev); 56 57static struct { 58 uint32_t id; 59 uint8_t rev; 60 const char *name; 61 int ports; 62 int quirks; 63} mvs_ids[] = { 64 {MV_DEV_88F5182, 0x00, "Marvell 88F5182", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 65 {MV_DEV_88F6281, 0x00, "Marvell 88F6281", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 66 {MV_DEV_88F6282, 0x00, "Marvell 88F6282", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 67 {MV_DEV_MV78100, 0x00, "Marvell MV78100", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 68 {MV_DEV_MV78100_Z0, 0x00,"Marvell MV78100", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 69 {MV_DEV_MV78260, 0x00, "Marvell MV78260", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 70 {MV_DEV_MV78460, 0x00, "Marvell MV78460", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 71 {0, 0x00, NULL, 0, 0} 72}; 73 74static int 75mvs_probe(device_t dev) 76{ 77 char buf[64]; 78 int i; 79 uint32_t devid, revid; 80 81 if (!ofw_bus_status_okay(dev)) 82 return (ENXIO); 83 84 if (!ofw_bus_is_compatible(dev, "mrvl,sata")) 85 return (ENXIO); 86 87 soc_id(&devid, &revid); 88 for (i = 0; mvs_ids[i].id != 0; i++) { 89 if (mvs_ids[i].id == devid && 90 mvs_ids[i].rev <= revid) { 91 snprintf(buf, sizeof(buf), "%s SATA controller", 92 mvs_ids[i].name); 93 device_set_desc_copy(dev, buf); 94 return (BUS_PROBE_DEFAULT); 95 } 96 } 97 return (ENXIO); 98} 99 100static int 101mvs_attach(device_t dev) 102{ 103 struct mvs_controller *ctlr = device_get_softc(dev); 104 device_t child; 105 int error, unit, i; 106 uint32_t devid, revid; 107 108 soc_id(&devid, &revid); 109 ctlr->dev = dev; 110 i = 0; 111 while (mvs_ids[i].id != 0 && 112 (mvs_ids[i].id != devid || 113 mvs_ids[i].rev > revid)) 114 i++; 115 ctlr->channels = mvs_ids[i].ports; 116 ctlr->quirks = mvs_ids[i].quirks; 117 ctlr->ccc = 0; 118 resource_int_value(device_get_name(dev), 119 device_get_unit(dev), "ccc", &ctlr->ccc); 120 ctlr->cccc = 8; 121 resource_int_value(device_get_name(dev), 122 device_get_unit(dev), "cccc", &ctlr->cccc); 123 if (ctlr->ccc == 0 || ctlr->cccc == 0) { 124 ctlr->ccc = 0; 125 ctlr->cccc = 0; 126 } 127 if (ctlr->ccc > 100000) 128 ctlr->ccc = 100000; 129 device_printf(dev, 130 "Gen-%s, %d %sGbps ports, Port Multiplier %s%s\n", 131 ((ctlr->quirks & MVS_Q_GENI) ? "I" : 132 ((ctlr->quirks & MVS_Q_GENII) ? "II" : "IIe")), 133 ctlr->channels, 134 ((ctlr->quirks & MVS_Q_GENI) ? "1.5" : "3"), 135 ((ctlr->quirks & MVS_Q_GENI) ? 136 "not supported" : "supported"), 137 ((ctlr->quirks & MVS_Q_GENIIE) ? 138 " with FBS" : "")); 139 mtx_init(&ctlr->mtx, "MVS controller lock", NULL, MTX_DEF); 140 /* We should have a memory BAR(0). */ 141 ctlr->r_rid = 0; 142 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 143 &ctlr->r_rid, RF_ACTIVE))) 144 return ENXIO; 145 if (ATA_INL(ctlr->r_mem, PORT_BASE(0) + SATA_PHYCFG_OFS) != 0) 146 ctlr->quirks |= MVS_Q_SOC65; 147 /* Setup our own memory management for channels. */ 148 ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem); 149 ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem); 150 ctlr->sc_iomem.rm_type = RMAN_ARRAY; 151 ctlr->sc_iomem.rm_descr = "I/O memory addresses"; 152 if ((error = rman_init(&ctlr->sc_iomem)) != 0) { 153 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 154 return (error); 155 } 156 if ((error = rman_manage_region(&ctlr->sc_iomem, 157 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) { 158 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 159 rman_fini(&ctlr->sc_iomem); 160 return (error); 161 } 162 mvs_ctlr_setup(dev); 163 /* Setup interrupts. */ 164 if (mvs_setup_interrupt(dev)) { 165 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 166 rman_fini(&ctlr->sc_iomem); 167 return ENXIO; 168 } 169 /* Attach all channels on this controller */ 170 for (unit = 0; unit < ctlr->channels; unit++) { 171 child = device_add_child(dev, "mvsch", -1); 172 if (child == NULL) 173 device_printf(dev, "failed to add channel device\n"); 174 else 175 device_set_ivars(child, (void *)(intptr_t)unit); 176 } 177 bus_generic_attach(dev); 178 return 0; 179} 180 181static int 182mvs_detach(device_t dev) 183{ 184 struct mvs_controller *ctlr = device_get_softc(dev); 185 186 /* Detach & delete all children */ 187 device_delete_children(dev); 188 189 /* Free interrupt. */ 190 if (ctlr->irq.r_irq) { 191 bus_teardown_intr(dev, ctlr->irq.r_irq, 192 ctlr->irq.handle); 193 bus_release_resource(dev, SYS_RES_IRQ, 194 ctlr->irq.r_irq_rid, ctlr->irq.r_irq); 195 } 196 /* Free memory. */ 197 rman_fini(&ctlr->sc_iomem); 198 if (ctlr->r_mem) 199 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 200 mtx_destroy(&ctlr->mtx); 201 return (0); 202} 203 204static int 205mvs_ctlr_setup(device_t dev) 206{ 207 struct mvs_controller *ctlr = device_get_softc(dev); 208 int ccc = ctlr->ccc, cccc = ctlr->cccc, ccim = 0; 209 210 /* Mask chip interrupts */ 211 ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, 0x00000000); 212 /* Clear HC interrupts */ 213 ATA_OUTL(ctlr->r_mem, HC_IC, 0x00000000); 214 /* Clear chip interrupts */ 215 ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIC, 0); 216 /* Configure per-HC CCC */ 217 if (ccc && bootverbose) { 218 device_printf(dev, 219 "CCC with %dus/%dcmd enabled\n", 220 ctlr->ccc, ctlr->cccc); 221 } 222 ccc *= 150; 223 ATA_OUTL(ctlr->r_mem, HC_ICT, cccc); 224 ATA_OUTL(ctlr->r_mem, HC_ITT, ccc); 225 if (ccc) 226 ccim |= IC_HC0_COAL_DONE; 227 /* Enable chip interrupts */ 228 ctlr->gmim = ((ccc ? IC_HC0_COAL_DONE : 229 (IC_DONE_HC0 & CHIP_SOC_HC0_MASK(ctlr->channels))) | 230 (IC_ERR_HC0 & CHIP_SOC_HC0_MASK(ctlr->channels))); 231 ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, ctlr->gmim | ctlr->pmim); 232 return (0); 233} 234 235static void 236mvs_edma(device_t dev, device_t child, int mode) 237{ 238 struct mvs_controller *ctlr = device_get_softc(dev); 239 int unit = ((struct mvs_channel *)device_get_softc(child))->unit; 240 int bit = IC_DONE_IRQ << (unit * 2); 241 242 if (ctlr->ccc == 0) 243 return; 244 /* CCC is not working for non-EDMA mode. Unmask device interrupts. */ 245 mtx_lock(&ctlr->mtx); 246 if (mode == MVS_EDMA_OFF) 247 ctlr->pmim |= bit; 248 else 249 ctlr->pmim &= ~bit; 250 ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, ctlr->gmim | ctlr->pmim); 251 mtx_unlock(&ctlr->mtx); 252} 253 254static int 255mvs_suspend(device_t dev) 256{ 257 struct mvs_controller *ctlr = device_get_softc(dev); 258 259 bus_generic_suspend(dev); 260 /* Mask chip interrupts */ 261 ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, 0x00000000); 262 return 0; 263} 264 265static int 266mvs_resume(device_t dev) 267{ 268 269 mvs_ctlr_setup(dev); 270 return (bus_generic_resume(dev)); 271} 272 273static int 274mvs_setup_interrupt(device_t dev) 275{ 276 struct mvs_controller *ctlr = device_get_softc(dev); 277 278 /* Allocate all IRQs. */ 279 ctlr->irq.r_irq_rid = 0; 280 if (!(ctlr->irq.r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 281 &ctlr->irq.r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) { 282 device_printf(dev, "unable to map interrupt\n"); 283 return (ENXIO); 284 } 285 if ((bus_setup_intr(dev, ctlr->irq.r_irq, ATA_INTR_FLAGS, NULL, 286 mvs_intr, ctlr, &ctlr->irq.handle))) { 287 device_printf(dev, "unable to setup interrupt\n"); 288 bus_release_resource(dev, SYS_RES_IRQ, 289 ctlr->irq.r_irq_rid, ctlr->irq.r_irq); 290 ctlr->irq.r_irq = NULL; 291 return (ENXIO); 292 } 293 return (0); 294} 295 296/* 297 * Common case interrupt handler. 298 */ 299static void 300mvs_intr(void *data) 301{ 302 struct mvs_controller *ctlr = data; 303 struct mvs_intr_arg arg; 304 void (*function)(void *); 305 int p, chan_num; 306 u_int32_t ic, aic; 307 308 ic = ATA_INL(ctlr->r_mem, CHIP_SOC_MIC); 309 if ((ic & IC_HC0) == 0) 310 return; 311 312 /* Acknowledge interrupts of this HC. */ 313 aic = 0; 314 315 /* Processing interrupts from each initialized channel */ 316 for (chan_num = 0; chan_num < ctlr->channels; chan_num++) { 317 if (ic & (IC_DONE_IRQ << (chan_num * 2))) 318 aic |= HC_IC_DONE(chan_num) | HC_IC_DEV(chan_num); 319 } 320 321 if (ic & IC_HC0_COAL_DONE) 322 aic |= HC_IC_COAL; 323 ATA_OUTL(ctlr->r_mem, HC_IC, ~aic); 324 325 /* Call per-port interrupt handler. */ 326 for (p = 0; p < ctlr->channels; p++) { 327 arg.cause = ic & (IC_ERR_IRQ|IC_DONE_IRQ); 328 if ((arg.cause != 0) && 329 (function = ctlr->interrupt[p].function)) { 330 arg.arg = ctlr->interrupt[p].argument; 331 function(&arg); 332 } 333 ic >>= 2; 334 } 335} 336 337static struct resource * 338mvs_alloc_resource(device_t dev, device_t child, int type, int *rid, 339 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 340{ 341 struct mvs_controller *ctlr = device_get_softc(dev); 342 int unit = ((struct mvs_channel *)device_get_softc(child))->unit; 343 struct resource *res = NULL; 344 int offset = PORT_BASE(unit & 0x03); 345 rman_res_t st; 346 347 switch (type) { 348 case SYS_RES_MEMORY: 349 st = rman_get_start(ctlr->r_mem); 350 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset, 351 st + offset + PORT_SIZE - 1, PORT_SIZE, RF_ACTIVE, child); 352 if (res) { 353 bus_space_handle_t bsh; 354 bus_space_tag_t bst; 355 bsh = rman_get_bushandle(ctlr->r_mem); 356 bst = rman_get_bustag(ctlr->r_mem); 357 bus_space_subregion(bst, bsh, offset, PORT_SIZE, &bsh); 358 rman_set_bushandle(res, bsh); 359 rman_set_bustag(res, bst); 360 } 361 break; 362 case SYS_RES_IRQ: 363 if (*rid == ATA_IRQ_RID) 364 res = ctlr->irq.r_irq; 365 break; 366 } 367 return (res); 368} 369 370static int 371mvs_release_resource(device_t dev, device_t child, int type, int rid, 372 struct resource *r) 373{ 374 375 switch (type) { 376 case SYS_RES_MEMORY: 377 rman_release_resource(r); 378 return (0); 379 case SYS_RES_IRQ: 380 if (rid != ATA_IRQ_RID) 381 return ENOENT; 382 return (0); 383 } 384 return (EINVAL); 385} 386 387static int 388mvs_setup_intr(device_t dev, device_t child, struct resource *irq, 389 int flags, driver_filter_t *filter, driver_intr_t *function, 390 void *argument, void **cookiep) 391{ 392 struct mvs_controller *ctlr = device_get_softc(dev); 393 int unit = (intptr_t)device_get_ivars(child); 394 395 if (filter != NULL) { 396 printf("mvs.c: we cannot use a filter here\n"); 397 return (EINVAL); 398 } 399 ctlr->interrupt[unit].function = function; 400 ctlr->interrupt[unit].argument = argument; 401 return (0); 402} 403 404static int 405mvs_teardown_intr(device_t dev, device_t child, struct resource *irq, 406 void *cookie) 407{ 408 struct mvs_controller *ctlr = device_get_softc(dev); 409 int unit = (intptr_t)device_get_ivars(child); 410 411 ctlr->interrupt[unit].function = NULL; 412 ctlr->interrupt[unit].argument = NULL; 413 return (0); 414} 415 416static int 417mvs_print_child(device_t dev, device_t child) 418{ 419 int retval; 420 421 retval = bus_print_child_header(dev, child); 422 retval += printf(" at channel %d", 423 (int)(intptr_t)device_get_ivars(child)); 424 retval += bus_print_child_footer(dev, child); 425 426 return (retval); 427} 428 429static int 430mvs_child_location_str(device_t dev, device_t child, char *buf, 431 size_t buflen) 432{ 433 434 snprintf(buf, buflen, "channel=%d", 435 (int)(intptr_t)device_get_ivars(child)); 436 return (0); 437} 438 439static bus_dma_tag_t 440mvs_get_dma_tag(device_t bus, device_t child) 441{ 442 443 return (bus_get_dma_tag(bus)); 444} 445 446static device_method_t mvs_methods[] = { 447 DEVMETHOD(device_probe, mvs_probe), 448 DEVMETHOD(device_attach, mvs_attach), 449 DEVMETHOD(device_detach, mvs_detach), 450 DEVMETHOD(device_suspend, mvs_suspend), 451 DEVMETHOD(device_resume, mvs_resume), 452 DEVMETHOD(bus_print_child, mvs_print_child), 453 DEVMETHOD(bus_alloc_resource, mvs_alloc_resource), 454 DEVMETHOD(bus_release_resource, mvs_release_resource), 455 DEVMETHOD(bus_setup_intr, mvs_setup_intr), 456 DEVMETHOD(bus_teardown_intr,mvs_teardown_intr), 457 DEVMETHOD(bus_child_location_str, mvs_child_location_str), 458 DEVMETHOD(bus_get_dma_tag, mvs_get_dma_tag), 459 DEVMETHOD(mvs_edma, mvs_edma), 460 { 0, 0 } 461}; 462static driver_t mvs_driver = { 463 "mvs", 464 mvs_methods, 465 sizeof(struct mvs_controller) 466}; 467DRIVER_MODULE(mvs, simplebus, mvs_driver, mvs_devclass, 0, 0); 468MODULE_VERSION(mvs, 1); 469MODULE_DEPEND(mvs, cam, 1, 1, 1); 470