1/*- 2 * Copyright (c) 2006-2015 LSI Corp. 3 * Copyright (c) 2013-2015 Avago Technologies 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * Avago Technologies (LSI) MPT-Fusion Host Adapter FreeBSD 28 * 29 * $FreeBSD$ 30 */ 31 32/* 33 * Copyright (c) 2006-2015 LSI Corporation. 34 * Copyright (c) 2013-2015 Avago Technologies 35 * 36 * 37 * Name: mpi2_ioc.h 38 * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages 39 * Creation Date: October 11, 2006 40 * 41 * mpi2_ioc.h Version: 02.00.16 42 * 43 * Version History 44 * --------------- 45 * 46 * Date Version Description 47 * -------- -------- ------------------------------------------------------ 48 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 49 * 06-04-07 02.00.01 In IOCFacts Reply structure, renamed MaxDevices to 50 * MaxTargets. 51 * Added TotalImageSize field to FWDownload Request. 52 * Added reserved words to FWUpload Request. 53 * 06-26-07 02.00.02 Added IR Configuration Change List Event. 54 * 08-31-07 02.00.03 Removed SystemReplyQueueDepth field from the IOCInit 55 * request and replaced it with 56 * ReplyDescriptorPostQueueDepth and ReplyFreeQueueDepth. 57 * Replaced the MinReplyQueueDepth field of the IOCFacts 58 * reply with MaxReplyDescriptorPostQueueDepth. 59 * Added MPI2_RDPQ_DEPTH_MIN define to specify the minimum 60 * depth for the Reply Descriptor Post Queue. 61 * Added SASAddress field to Initiator Device Table 62 * Overflow Event data. 63 * 10-31-07 02.00.04 Added ReasonCode MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING 64 * for SAS Initiator Device Status Change Event data. 65 * Modified Reason Code defines for SAS Topology Change 66 * List Event data, including adding a bit for PHY Vacant 67 * status, and adding a mask for the Reason Code. 68 * Added define for 69 * MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING. 70 * Added define for MPI2_EXT_IMAGE_TYPE_MEGARAID. 71 * 12-18-07 02.00.05 Added Boot Status defines for the IOCExceptions field of 72 * the IOCFacts Reply. 73 * Removed MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define. 74 * Moved MPI2_VERSION_UNION to mpi2.h. 75 * Changed MPI2_EVENT_NOTIFICATION_REQUEST to use masks 76 * instead of enables, and added SASBroadcastPrimitiveMasks 77 * field. 78 * Added Log Entry Added Event and related structure. 79 * 02-29-08 02.00.06 Added define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID. 80 * Removed define MPI2_IOCFACTS_PROTOCOL_SMP_TARGET. 81 * Added MaxVolumes and MaxPersistentEntries fields to 82 * IOCFacts reply. 83 * Added ProtocalFlags and IOCCapabilities fields to 84 * MPI2_FW_IMAGE_HEADER. 85 * Removed MPI2_PORTENABLE_FLAGS_ENABLE_SINGLE_PORT. 86 * 03-03-08 02.00.07 Fixed MPI2_FW_IMAGE_HEADER by changing Reserved26 to 87 * a U16 (from a U32). 88 * Removed extra 's' from EventMasks name. 89 * 06-27-08 02.00.08 Fixed an offset in a comment. 90 * 10-02-08 02.00.09 Removed SystemReplyFrameSize from MPI2_IOC_INIT_REQUEST. 91 * Removed CurReplyFrameSize from MPI2_IOC_FACTS_REPLY and 92 * renamed MinReplyFrameSize to ReplyFrameSize. 93 * Added MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX. 94 * Added two new RAIDOperation values for Integrated RAID 95 * Operations Status Event data. 96 * Added four new IR Configuration Change List Event data 97 * ReasonCode values. 98 * Added two new ReasonCode defines for SAS Device Status 99 * Change Event data. 100 * Added three new DiscoveryStatus bits for the SAS 101 * Discovery event data. 102 * Added Multiplexing Status Change bit to the PhyStatus 103 * field of the SAS Topology Change List event data. 104 * Removed define for MPI2_INIT_IMAGE_BOOTFLAGS_XMEMCOPY. 105 * BootFlags are now product-specific. 106 * Added defines for the indivdual signature bytes 107 * for MPI2_INIT_IMAGE_FOOTER. 108 * 01-19-09 02.00.10 Added MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY define. 109 * Added MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR 110 * define. 111 * Added MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE 112 * define. 113 * Removed MPI2_EVENT_SAS_DISC_DS_SATA_INIT_FAILURE define. 114 * 05-06-09 02.00.11 Added MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR define. 115 * Added MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX define. 116 * Added two new reason codes for SAS Device Status Change 117 * Event. 118 * Added new event: SAS PHY Counter. 119 * 07-30-09 02.00.12 Added GPIO Interrupt event define and structure. 120 * Added MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define. 121 * Added new product id family for 2208. 122 * 10-28-09 02.00.13 Added HostMSIxVectors field to MPI2_IOC_INIT_REQUEST. 123 * Added MaxMSIxVectors field to MPI2_IOC_FACTS_REPLY. 124 * Added MinDevHandle field to MPI2_IOC_FACTS_REPLY. 125 * Added MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY. 126 * Added MPI2_EVENT_HOST_BASED_DISCOVERY_PHY define. 127 * Added MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER define. 128 * Added Host Based Discovery Phy Event data. 129 * Added defines for ProductID Product field 130 * (MPI2_FW_HEADER_PID_). 131 * Modified values for SAS ProductID Family 132 * (MPI2_FW_HEADER_PID_FAMILY_). 133 * 02-10-10 02.00.14 Added SAS Quiesce Event structure and defines. 134 * Added PowerManagementControl Request structures and 135 * defines. 136 * 05-12-10 02.00.15 Marked Task Set Full Event as obsolete. 137 * Added MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY define. 138 * 11-10-10 02.00.16 Added MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC. 139 * -------------------------------------------------------------------------- 140 */ 141 142#ifndef MPI2_IOC_H 143#define MPI2_IOC_H 144 145/***************************************************************************** 146* 147* IOC Messages 148* 149*****************************************************************************/ 150 151/**************************************************************************** 152* IOCInit message 153****************************************************************************/ 154 155/* IOCInit Request message */ 156typedef struct _MPI2_IOC_INIT_REQUEST 157{ 158 U8 WhoInit; /* 0x00 */ 159 U8 Reserved1; /* 0x01 */ 160 U8 ChainOffset; /* 0x02 */ 161 U8 Function; /* 0x03 */ 162 U16 Reserved2; /* 0x04 */ 163 U8 Reserved3; /* 0x06 */ 164 U8 MsgFlags; /* 0x07 */ 165 U8 VP_ID; /* 0x08 */ 166 U8 VF_ID; /* 0x09 */ 167 U16 Reserved4; /* 0x0A */ 168 U16 MsgVersion; /* 0x0C */ 169 U16 HeaderVersion; /* 0x0E */ 170 U32 Reserved5; /* 0x10 */ 171 U16 Reserved6; /* 0x14 */ 172 U8 Reserved7; /* 0x16 */ 173 U8 HostMSIxVectors; /* 0x17 */ 174 U16 Reserved8; /* 0x18 */ 175 U16 SystemRequestFrameSize; /* 0x1A */ 176 U16 ReplyDescriptorPostQueueDepth; /* 0x1C */ 177 U16 ReplyFreeQueueDepth; /* 0x1E */ 178 U32 SenseBufferAddressHigh; /* 0x20 */ 179 U32 SystemReplyAddressHigh; /* 0x24 */ 180 U64 SystemRequestFrameBaseAddress; /* 0x28 */ 181 U64 ReplyDescriptorPostQueueAddress;/* 0x30 */ 182 U64 ReplyFreeQueueAddress; /* 0x38 */ 183 U64 TimeStamp; /* 0x40 */ 184} MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST, 185 Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t; 186 187/* WhoInit values */ 188#define MPI2_WHOINIT_NOT_INITIALIZED (0x00) 189#define MPI2_WHOINIT_SYSTEM_BIOS (0x01) 190#define MPI2_WHOINIT_ROM_BIOS (0x02) 191#define MPI2_WHOINIT_PCI_PEER (0x03) 192#define MPI2_WHOINIT_HOST_DRIVER (0x04) 193#define MPI2_WHOINIT_MANUFACTURER (0x05) 194 195/* MsgVersion */ 196#define MPI2_IOCINIT_MSGVERSION_MAJOR_MASK (0xFF00) 197#define MPI2_IOCINIT_MSGVERSION_MAJOR_SHIFT (8) 198#define MPI2_IOCINIT_MSGVERSION_MINOR_MASK (0x00FF) 199#define MPI2_IOCINIT_MSGVERSION_MINOR_SHIFT (0) 200 201/* HeaderVersion */ 202#define MPI2_IOCINIT_HDRVERSION_UNIT_MASK (0xFF00) 203#define MPI2_IOCINIT_HDRVERSION_UNIT_SHIFT (8) 204#define MPI2_IOCINIT_HDRVERSION_DEV_MASK (0x00FF) 205#define MPI2_IOCINIT_HDRVERSION_DEV_SHIFT (0) 206 207/* minimum depth for the Reply Descriptor Post Queue */ 208#define MPI2_RDPQ_DEPTH_MIN (16) 209 210 211/* IOCInit Reply message */ 212typedef struct _MPI2_IOC_INIT_REPLY 213{ 214 U8 WhoInit; /* 0x00 */ 215 U8 Reserved1; /* 0x01 */ 216 U8 MsgLength; /* 0x02 */ 217 U8 Function; /* 0x03 */ 218 U16 Reserved2; /* 0x04 */ 219 U8 Reserved3; /* 0x06 */ 220 U8 MsgFlags; /* 0x07 */ 221 U8 VP_ID; /* 0x08 */ 222 U8 VF_ID; /* 0x09 */ 223 U16 Reserved4; /* 0x0A */ 224 U16 Reserved5; /* 0x0C */ 225 U16 IOCStatus; /* 0x0E */ 226 U32 IOCLogInfo; /* 0x10 */ 227} MPI2_IOC_INIT_REPLY, MPI2_POINTER PTR_MPI2_IOC_INIT_REPLY, 228 Mpi2IOCInitReply_t, MPI2_POINTER pMpi2IOCInitReply_t; 229 230 231/**************************************************************************** 232* IOCFacts message 233****************************************************************************/ 234 235/* IOCFacts Request message */ 236typedef struct _MPI2_IOC_FACTS_REQUEST 237{ 238 U16 Reserved1; /* 0x00 */ 239 U8 ChainOffset; /* 0x02 */ 240 U8 Function; /* 0x03 */ 241 U16 Reserved2; /* 0x04 */ 242 U8 Reserved3; /* 0x06 */ 243 U8 MsgFlags; /* 0x07 */ 244 U8 VP_ID; /* 0x08 */ 245 U8 VF_ID; /* 0x09 */ 246 U16 Reserved4; /* 0x0A */ 247} MPI2_IOC_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_IOC_FACTS_REQUEST, 248 Mpi2IOCFactsRequest_t, MPI2_POINTER pMpi2IOCFactsRequest_t; 249 250 251/* IOCFacts Reply message */ 252typedef struct _MPI2_IOC_FACTS_REPLY 253{ 254 U16 MsgVersion; /* 0x00 */ 255 U8 MsgLength; /* 0x02 */ 256 U8 Function; /* 0x03 */ 257 U16 HeaderVersion; /* 0x04 */ 258 U8 IOCNumber; /* 0x06 */ 259 U8 MsgFlags; /* 0x07 */ 260 U8 VP_ID; /* 0x08 */ 261 U8 VF_ID; /* 0x09 */ 262 U16 Reserved1; /* 0x0A */ 263 U16 IOCExceptions; /* 0x0C */ 264 U16 IOCStatus; /* 0x0E */ 265 U32 IOCLogInfo; /* 0x10 */ 266 U8 MaxChainDepth; /* 0x14 */ 267 U8 WhoInit; /* 0x15 */ 268 U8 NumberOfPorts; /* 0x16 */ 269 U8 MaxMSIxVectors; /* 0x17 */ 270 U16 RequestCredit; /* 0x18 */ 271 U16 ProductID; /* 0x1A */ 272 U32 IOCCapabilities; /* 0x1C */ 273 MPI2_VERSION_UNION FWVersion; /* 0x20 */ 274 U16 IOCRequestFrameSize; /* 0x24 */ 275 U16 Reserved3; /* 0x26 */ 276 U16 MaxInitiators; /* 0x28 */ 277 U16 MaxTargets; /* 0x2A */ 278 U16 MaxSasExpanders; /* 0x2C */ 279 U16 MaxEnclosures; /* 0x2E */ 280 U16 ProtocolFlags; /* 0x30 */ 281 U16 HighPriorityCredit; /* 0x32 */ 282 U16 MaxReplyDescriptorPostQueueDepth; /* 0x34 */ 283 U8 ReplyFrameSize; /* 0x36 */ 284 U8 MaxVolumes; /* 0x37 */ 285 U16 MaxDevHandle; /* 0x38 */ 286 U16 MaxPersistentEntries; /* 0x3A */ 287 U16 MinDevHandle; /* 0x3C */ 288 U16 Reserved4; /* 0x3E */ 289} MPI2_IOC_FACTS_REPLY, MPI2_POINTER PTR_MPI2_IOC_FACTS_REPLY, 290 Mpi2IOCFactsReply_t, MPI2_POINTER pMpi2IOCFactsReply_t; 291 292/* MsgVersion */ 293#define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK (0xFF00) 294#define MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT (8) 295#define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK (0x00FF) 296#define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT (0) 297 298/* HeaderVersion */ 299#define MPI2_IOCFACTS_HDRVERSION_UNIT_MASK (0xFF00) 300#define MPI2_IOCFACTS_HDRVERSION_UNIT_SHIFT (8) 301#define MPI2_IOCFACTS_HDRVERSION_DEV_MASK (0x00FF) 302#define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT (0) 303 304/* IOCExceptions */ 305#define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX (0x0100) 306 307#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_MASK (0x00E0) 308#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_GOOD (0x0000) 309#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_BACKUP (0x0020) 310#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_RESTORED (0x0040) 311#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_CORRUPT_BACKUP (0x0060) 312 313#define MPI2_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED (0x0010) 314#define MPI2_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0x0008) 315#define MPI2_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0004) 316#define MPI2_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID (0x0002) 317#define MPI2_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0001) 318 319/* defines for WhoInit field are after the IOCInit Request */ 320 321/* ProductID field uses MPI2_FW_HEADER_PID_ */ 322 323/* IOCCapabilities */ 324#define MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY (0x00010000) 325#define MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX (0x00008000) 326#define MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR (0x00004000) 327#define MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY (0x00002000) 328#define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID (0x00001000) 329#define MPI2_IOCFACTS_CAPABILITY_TLR (0x00000800) 330#define MPI2_IOCFACTS_CAPABILITY_MULTICAST (0x00000100) 331#define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET (0x00000080) 332#define MPI2_IOCFACTS_CAPABILITY_EEDP (0x00000040) 333#define MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER (0x00000020) 334#define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (0x00000010) 335#define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (0x00000008) 336#define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004) 337 338/* ProtocolFlags */ 339#define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001) 340#define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0x0002) 341 342 343/**************************************************************************** 344* PortFacts message 345****************************************************************************/ 346 347/* PortFacts Request message */ 348typedef struct _MPI2_PORT_FACTS_REQUEST 349{ 350 U16 Reserved1; /* 0x00 */ 351 U8 ChainOffset; /* 0x02 */ 352 U8 Function; /* 0x03 */ 353 U16 Reserved2; /* 0x04 */ 354 U8 PortNumber; /* 0x06 */ 355 U8 MsgFlags; /* 0x07 */ 356 U8 VP_ID; /* 0x08 */ 357 U8 VF_ID; /* 0x09 */ 358 U16 Reserved3; /* 0x0A */ 359} MPI2_PORT_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_PORT_FACTS_REQUEST, 360 Mpi2PortFactsRequest_t, MPI2_POINTER pMpi2PortFactsRequest_t; 361 362/* PortFacts Reply message */ 363typedef struct _MPI2_PORT_FACTS_REPLY 364{ 365 U16 Reserved1; /* 0x00 */ 366 U8 MsgLength; /* 0x02 */ 367 U8 Function; /* 0x03 */ 368 U16 Reserved2; /* 0x04 */ 369 U8 PortNumber; /* 0x06 */ 370 U8 MsgFlags; /* 0x07 */ 371 U8 VP_ID; /* 0x08 */ 372 U8 VF_ID; /* 0x09 */ 373 U16 Reserved3; /* 0x0A */ 374 U16 Reserved4; /* 0x0C */ 375 U16 IOCStatus; /* 0x0E */ 376 U32 IOCLogInfo; /* 0x10 */ 377 U8 Reserved5; /* 0x14 */ 378 U8 PortType; /* 0x15 */ 379 U16 Reserved6; /* 0x16 */ 380 U16 MaxPostedCmdBuffers; /* 0x18 */ 381 U16 Reserved7; /* 0x1A */ 382} MPI2_PORT_FACTS_REPLY, MPI2_POINTER PTR_MPI2_PORT_FACTS_REPLY, 383 Mpi2PortFactsReply_t, MPI2_POINTER pMpi2PortFactsReply_t; 384 385/* PortType values */ 386#define MPI2_PORTFACTS_PORTTYPE_INACTIVE (0x00) 387#define MPI2_PORTFACTS_PORTTYPE_FC (0x10) 388#define MPI2_PORTFACTS_PORTTYPE_ISCSI (0x20) 389#define MPI2_PORTFACTS_PORTTYPE_SAS_PHYSICAL (0x30) 390#define MPI2_PORTFACTS_PORTTYPE_SAS_VIRTUAL (0x31) 391 392 393/**************************************************************************** 394* PortEnable message 395****************************************************************************/ 396 397/* PortEnable Request message */ 398typedef struct _MPI2_PORT_ENABLE_REQUEST 399{ 400 U16 Reserved1; /* 0x00 */ 401 U8 ChainOffset; /* 0x02 */ 402 U8 Function; /* 0x03 */ 403 U8 Reserved2; /* 0x04 */ 404 U8 PortFlags; /* 0x05 */ 405 U8 Reserved3; /* 0x06 */ 406 U8 MsgFlags; /* 0x07 */ 407 U8 VP_ID; /* 0x08 */ 408 U8 VF_ID; /* 0x09 */ 409 U16 Reserved4; /* 0x0A */ 410} MPI2_PORT_ENABLE_REQUEST, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REQUEST, 411 Mpi2PortEnableRequest_t, MPI2_POINTER pMpi2PortEnableRequest_t; 412 413 414/* PortEnable Reply message */ 415typedef struct _MPI2_PORT_ENABLE_REPLY 416{ 417 U16 Reserved1; /* 0x00 */ 418 U8 MsgLength; /* 0x02 */ 419 U8 Function; /* 0x03 */ 420 U8 Reserved2; /* 0x04 */ 421 U8 PortFlags; /* 0x05 */ 422 U8 Reserved3; /* 0x06 */ 423 U8 MsgFlags; /* 0x07 */ 424 U8 VP_ID; /* 0x08 */ 425 U8 VF_ID; /* 0x09 */ 426 U16 Reserved4; /* 0x0A */ 427 U16 Reserved5; /* 0x0C */ 428 U16 IOCStatus; /* 0x0E */ 429 U32 IOCLogInfo; /* 0x10 */ 430} MPI2_PORT_ENABLE_REPLY, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REPLY, 431 Mpi2PortEnableReply_t, MPI2_POINTER pMpi2PortEnableReply_t; 432 433 434/**************************************************************************** 435* EventNotification message 436****************************************************************************/ 437 438/* EventNotification Request message */ 439#define MPI2_EVENT_NOTIFY_EVENTMASK_WORDS (4) 440 441typedef struct _MPI2_EVENT_NOTIFICATION_REQUEST 442{ 443 U16 Reserved1; /* 0x00 */ 444 U8 ChainOffset; /* 0x02 */ 445 U8 Function; /* 0x03 */ 446 U16 Reserved2; /* 0x04 */ 447 U8 Reserved3; /* 0x06 */ 448 U8 MsgFlags; /* 0x07 */ 449 U8 VP_ID; /* 0x08 */ 450 U8 VF_ID; /* 0x09 */ 451 U16 Reserved4; /* 0x0A */ 452 U32 Reserved5; /* 0x0C */ 453 U32 Reserved6; /* 0x10 */ 454 U32 EventMasks[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS];/* 0x14 */ 455 U16 SASBroadcastPrimitiveMasks; /* 0x24 */ 456 U16 Reserved7; /* 0x26 */ 457 U32 Reserved8; /* 0x28 */ 458} MPI2_EVENT_NOTIFICATION_REQUEST, 459 MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REQUEST, 460 Mpi2EventNotificationRequest_t, MPI2_POINTER pMpi2EventNotificationRequest_t; 461 462 463/* EventNotification Reply message */ 464typedef struct _MPI2_EVENT_NOTIFICATION_REPLY 465{ 466 U16 EventDataLength; /* 0x00 */ 467 U8 MsgLength; /* 0x02 */ 468 U8 Function; /* 0x03 */ 469 U16 Reserved1; /* 0x04 */ 470 U8 AckRequired; /* 0x06 */ 471 U8 MsgFlags; /* 0x07 */ 472 U8 VP_ID; /* 0x08 */ 473 U8 VF_ID; /* 0x09 */ 474 U16 Reserved2; /* 0x0A */ 475 U16 Reserved3; /* 0x0C */ 476 U16 IOCStatus; /* 0x0E */ 477 U32 IOCLogInfo; /* 0x10 */ 478 U16 Event; /* 0x14 */ 479 U16 Reserved4; /* 0x16 */ 480 U32 EventContext; /* 0x18 */ 481 U32 EventData[1]; /* 0x1C */ 482} MPI2_EVENT_NOTIFICATION_REPLY, MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REPLY, 483 Mpi2EventNotificationReply_t, MPI2_POINTER pMpi2EventNotificationReply_t; 484 485/* AckRequired */ 486#define MPI2_EVENT_NOTIFICATION_ACK_NOT_REQUIRED (0x00) 487#define MPI2_EVENT_NOTIFICATION_ACK_REQUIRED (0x01) 488 489/* Event */ 490#define MPI2_EVENT_LOG_DATA (0x0001) 491#define MPI2_EVENT_STATE_CHANGE (0x0002) 492#define MPI2_EVENT_HARD_RESET_RECEIVED (0x0005) 493#define MPI2_EVENT_EVENT_CHANGE (0x000A) 494#define MPI2_EVENT_TASK_SET_FULL (0x000E) /* obsolete */ 495#define MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE (0x000F) 496#define MPI2_EVENT_IR_OPERATION_STATUS (0x0014) 497#define MPI2_EVENT_SAS_DISCOVERY (0x0016) 498#define MPI2_EVENT_SAS_BROADCAST_PRIMITIVE (0x0017) 499#define MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x0018) 500#define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW (0x0019) 501#define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x001C) 502#define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE (0x001D) 503#define MPI2_EVENT_IR_VOLUME (0x001E) 504#define MPI2_EVENT_IR_PHYSICAL_DISK (0x001F) 505#define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST (0x0020) 506#define MPI2_EVENT_LOG_ENTRY_ADDED (0x0021) 507#define MPI2_EVENT_SAS_PHY_COUNTER (0x0022) 508#define MPI2_EVENT_GPIO_INTERRUPT (0x0023) 509#define MPI2_EVENT_HOST_BASED_DISCOVERY_PHY (0x0024) 510#define MPI2_EVENT_SAS_QUIESCE (0x0025) 511 512 513/* Log Entry Added Event data */ 514 515/* the following structure matches MPI2_LOG_0_ENTRY in mpi2_cnfg.h */ 516#define MPI2_EVENT_DATA_LOG_DATA_LENGTH (0x1C) 517 518typedef struct _MPI2_EVENT_DATA_LOG_ENTRY_ADDED 519{ 520 U64 TimeStamp; /* 0x00 */ 521 U32 Reserved1; /* 0x08 */ 522 U16 LogSequence; /* 0x0C */ 523 U16 LogEntryQualifier; /* 0x0E */ 524 U8 VP_ID; /* 0x10 */ 525 U8 VF_ID; /* 0x11 */ 526 U16 Reserved2; /* 0x12 */ 527 U8 LogData[MPI2_EVENT_DATA_LOG_DATA_LENGTH];/* 0x14 */ 528} MPI2_EVENT_DATA_LOG_ENTRY_ADDED, 529 MPI2_POINTER PTR_MPI2_EVENT_DATA_LOG_ENTRY_ADDED, 530 Mpi2EventDataLogEntryAdded_t, MPI2_POINTER pMpi2EventDataLogEntryAdded_t; 531 532/* GPIO Interrupt Event data */ 533 534typedef struct _MPI2_EVENT_DATA_GPIO_INTERRUPT 535{ 536 U8 GPIONum; /* 0x00 */ 537 U8 Reserved1; /* 0x01 */ 538 U16 Reserved2; /* 0x02 */ 539} MPI2_EVENT_DATA_GPIO_INTERRUPT, 540 MPI2_POINTER PTR_MPI2_EVENT_DATA_GPIO_INTERRUPT, 541 Mpi2EventDataGpioInterrupt_t, MPI2_POINTER pMpi2EventDataGpioInterrupt_t; 542 543/* Hard Reset Received Event data */ 544 545typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED 546{ 547 U8 Reserved1; /* 0x00 */ 548 U8 Port; /* 0x01 */ 549 U16 Reserved2; /* 0x02 */ 550} MPI2_EVENT_DATA_HARD_RESET_RECEIVED, 551 MPI2_POINTER PTR_MPI2_EVENT_DATA_HARD_RESET_RECEIVED, 552 Mpi2EventDataHardResetReceived_t, 553 MPI2_POINTER pMpi2EventDataHardResetReceived_t; 554 555/* Task Set Full Event data */ 556/* this event is obsolete */ 557 558typedef struct _MPI2_EVENT_DATA_TASK_SET_FULL 559{ 560 U16 DevHandle; /* 0x00 */ 561 U16 CurrentDepth; /* 0x02 */ 562} MPI2_EVENT_DATA_TASK_SET_FULL, MPI2_POINTER PTR_MPI2_EVENT_DATA_TASK_SET_FULL, 563 Mpi2EventDataTaskSetFull_t, MPI2_POINTER pMpi2EventDataTaskSetFull_t; 564 565 566/* SAS Device Status Change Event data */ 567 568typedef struct _MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE 569{ 570 U16 TaskTag; /* 0x00 */ 571 U8 ReasonCode; /* 0x02 */ 572 U8 Reserved1; /* 0x03 */ 573 U8 ASC; /* 0x04 */ 574 U8 ASCQ; /* 0x05 */ 575 U16 DevHandle; /* 0x06 */ 576 U32 Reserved2; /* 0x08 */ 577 U64 SASAddress; /* 0x0C */ 578 U8 LUN[8]; /* 0x14 */ 579} MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE, 580 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE, 581 Mpi2EventDataSasDeviceStatusChange_t, 582 MPI2_POINTER pMpi2EventDataSasDeviceStatusChange_t; 583 584/* SAS Device Status Change Event data ReasonCode values */ 585#define MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA (0x05) 586#define MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED (0x07) 587#define MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08) 588#define MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL (0x09) 589#define MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A) 590#define MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B) 591#define MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C) 592#define MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION (0x0D) 593#define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET (0x0E) 594#define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL (0x0F) 595#define MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE (0x10) 596#define MPI2_EVENT_SAS_DEV_STAT_RC_EXPANDER_REDUCED_FUNCTIONALITY (0x11) 597#define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_EXPANDER_REDUCED_FUNCTIONALITY (0x12) 598 599 600/* Integrated RAID Operation Status Event data */ 601 602typedef struct _MPI2_EVENT_DATA_IR_OPERATION_STATUS 603{ 604 U16 VolDevHandle; /* 0x00 */ 605 U16 Reserved1; /* 0x02 */ 606 U8 RAIDOperation; /* 0x04 */ 607 U8 PercentComplete; /* 0x05 */ 608 U16 Reserved2; /* 0x06 */ 609 U32 Resereved3; /* 0x08 */ 610} MPI2_EVENT_DATA_IR_OPERATION_STATUS, 611 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_OPERATION_STATUS, 612 Mpi2EventDataIrOperationStatus_t, 613 MPI2_POINTER pMpi2EventDataIrOperationStatus_t; 614 615/* Integrated RAID Operation Status Event data RAIDOperation values */ 616#define MPI2_EVENT_IR_RAIDOP_RESYNC (0x00) 617#define MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION (0x01) 618#define MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK (0x02) 619#define MPI2_EVENT_IR_RAIDOP_BACKGROUND_INIT (0x03) 620#define MPI2_EVENT_IR_RAIDOP_MAKE_DATA_CONSISTENT (0x04) 621 622 623/* Integrated RAID Volume Event data */ 624 625typedef struct _MPI2_EVENT_DATA_IR_VOLUME 626{ 627 U16 VolDevHandle; /* 0x00 */ 628 U8 ReasonCode; /* 0x02 */ 629 U8 Reserved1; /* 0x03 */ 630 U32 NewValue; /* 0x04 */ 631 U32 PreviousValue; /* 0x08 */ 632} MPI2_EVENT_DATA_IR_VOLUME, MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_VOLUME, 633 Mpi2EventDataIrVolume_t, MPI2_POINTER pMpi2EventDataIrVolume_t; 634 635/* Integrated RAID Volume Event data ReasonCode values */ 636#define MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED (0x01) 637#define MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED (0x02) 638#define MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED (0x03) 639 640 641/* Integrated RAID Physical Disk Event data */ 642 643typedef struct _MPI2_EVENT_DATA_IR_PHYSICAL_DISK 644{ 645 U16 Reserved1; /* 0x00 */ 646 U8 ReasonCode; /* 0x02 */ 647 U8 PhysDiskNum; /* 0x03 */ 648 U16 PhysDiskDevHandle; /* 0x04 */ 649 U16 Reserved2; /* 0x06 */ 650 U16 Slot; /* 0x08 */ 651 U16 EnclosureHandle; /* 0x0A */ 652 U32 NewValue; /* 0x0C */ 653 U32 PreviousValue; /* 0x10 */ 654} MPI2_EVENT_DATA_IR_PHYSICAL_DISK, 655 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_PHYSICAL_DISK, 656 Mpi2EventDataIrPhysicalDisk_t, MPI2_POINTER pMpi2EventDataIrPhysicalDisk_t; 657 658/* Integrated RAID Physical Disk Event data ReasonCode values */ 659#define MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED (0x01) 660#define MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED (0x02) 661#define MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED (0x03) 662 663 664/* Integrated RAID Configuration Change List Event data */ 665 666/* 667 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 668 * one and check NumElements at runtime. 669 */ 670#ifndef MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT 671#define MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT (1) 672#endif 673 674typedef struct _MPI2_EVENT_IR_CONFIG_ELEMENT 675{ 676 U16 ElementFlags; /* 0x00 */ 677 U16 VolDevHandle; /* 0x02 */ 678 U8 ReasonCode; /* 0x04 */ 679 U8 PhysDiskNum; /* 0x05 */ 680 U16 PhysDiskDevHandle; /* 0x06 */ 681} MPI2_EVENT_IR_CONFIG_ELEMENT, MPI2_POINTER PTR_MPI2_EVENT_IR_CONFIG_ELEMENT, 682 Mpi2EventIrConfigElement_t, MPI2_POINTER pMpi2EventIrConfigElement_t; 683 684/* IR Configuration Change List Event data ElementFlags values */ 685#define MPI2_EVENT_IR_CHANGE_EFLAGS_ELEMENT_TYPE_MASK (0x000F) 686#define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLUME_ELEMENT (0x0000) 687#define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLPHYSDISK_ELEMENT (0x0001) 688#define MPI2_EVENT_IR_CHANGE_EFLAGS_HOTSPARE_ELEMENT (0x0002) 689 690/* IR Configuration Change List Event data ReasonCode values */ 691#define MPI2_EVENT_IR_CHANGE_RC_ADDED (0x01) 692#define MPI2_EVENT_IR_CHANGE_RC_REMOVED (0x02) 693#define MPI2_EVENT_IR_CHANGE_RC_NO_CHANGE (0x03) 694#define MPI2_EVENT_IR_CHANGE_RC_HIDE (0x04) 695#define MPI2_EVENT_IR_CHANGE_RC_UNHIDE (0x05) 696#define MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED (0x06) 697#define MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED (0x07) 698#define MPI2_EVENT_IR_CHANGE_RC_PD_CREATED (0x08) 699#define MPI2_EVENT_IR_CHANGE_RC_PD_DELETED (0x09) 700 701typedef struct _MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST 702{ 703 U8 NumElements; /* 0x00 */ 704 U8 Reserved1; /* 0x01 */ 705 U8 Reserved2; /* 0x02 */ 706 U8 ConfigNum; /* 0x03 */ 707 U32 Flags; /* 0x04 */ 708 MPI2_EVENT_IR_CONFIG_ELEMENT ConfigElement[MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT]; /* 0x08 */ 709} MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST, 710 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST, 711 Mpi2EventDataIrConfigChangeList_t, 712 MPI2_POINTER pMpi2EventDataIrConfigChangeList_t; 713 714/* IR Configuration Change List Event data Flags values */ 715#define MPI2_EVENT_IR_CHANGE_FLAGS_FOREIGN_CONFIG (0x00000001) 716 717 718/* SAS Discovery Event data */ 719 720typedef struct _MPI2_EVENT_DATA_SAS_DISCOVERY 721{ 722 U8 Flags; /* 0x00 */ 723 U8 ReasonCode; /* 0x01 */ 724 U8 PhysicalPort; /* 0x02 */ 725 U8 Reserved1; /* 0x03 */ 726 U32 DiscoveryStatus; /* 0x04 */ 727} MPI2_EVENT_DATA_SAS_DISCOVERY, 728 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DISCOVERY, 729 Mpi2EventDataSasDiscovery_t, MPI2_POINTER pMpi2EventDataSasDiscovery_t; 730 731/* SAS Discovery Event data Flags values */ 732#define MPI2_EVENT_SAS_DISC_DEVICE_CHANGE (0x02) 733#define MPI2_EVENT_SAS_DISC_IN_PROGRESS (0x01) 734 735/* SAS Discovery Event data ReasonCode values */ 736#define MPI2_EVENT_SAS_DISC_RC_STARTED (0x01) 737#define MPI2_EVENT_SAS_DISC_RC_COMPLETED (0x02) 738 739/* SAS Discovery Event data DiscoveryStatus values */ 740#define MPI2_EVENT_SAS_DISC_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 741#define MPI2_EVENT_SAS_DISC_DS_MAX_EXPANDERS_EXCEED (0x40000000) 742#define MPI2_EVENT_SAS_DISC_DS_MAX_DEVICES_EXCEED (0x20000000) 743#define MPI2_EVENT_SAS_DISC_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 744#define MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR (0x08000000) 745#define MPI2_EVENT_SAS_DISC_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 746#define MPI2_EVENT_SAS_DISC_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 747#define MPI2_EVENT_SAS_DISC_DS_MULTI_PORT_DOMAIN (0x00002000) 748#define MPI2_EVENT_SAS_DISC_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 749#define MPI2_EVENT_SAS_DISC_DS_UNSUPPORTED_DEVICE (0x00000800) 750#define MPI2_EVENT_SAS_DISC_DS_TABLE_LINK (0x00000400) 751#define MPI2_EVENT_SAS_DISC_DS_SUBTRACTIVE_LINK (0x00000200) 752#define MPI2_EVENT_SAS_DISC_DS_SMP_CRC_ERROR (0x00000100) 753#define MPI2_EVENT_SAS_DISC_DS_SMP_FUNCTION_FAILED (0x00000080) 754#define MPI2_EVENT_SAS_DISC_DS_INDEX_NOT_EXIST (0x00000040) 755#define MPI2_EVENT_SAS_DISC_DS_OUT_ROUTE_ENTRIES (0x00000020) 756#define MPI2_EVENT_SAS_DISC_DS_SMP_TIMEOUT (0x00000010) 757#define MPI2_EVENT_SAS_DISC_DS_MULTIPLE_PORTS (0x00000004) 758#define MPI2_EVENT_SAS_DISC_DS_UNADDRESSABLE_DEVICE (0x00000002) 759#define MPI2_EVENT_SAS_DISC_DS_LOOP_DETECTED (0x00000001) 760 761 762/* SAS Broadcast Primitive Event data */ 763 764typedef struct _MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE 765{ 766 U8 PhyNum; /* 0x00 */ 767 U8 Port; /* 0x01 */ 768 U8 PortWidth; /* 0x02 */ 769 U8 Primitive; /* 0x03 */ 770} MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE, 771 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE, 772 Mpi2EventDataSasBroadcastPrimitive_t, 773 MPI2_POINTER pMpi2EventDataSasBroadcastPrimitive_t; 774 775/* defines for the Primitive field */ 776#define MPI2_EVENT_PRIMITIVE_CHANGE (0x01) 777#define MPI2_EVENT_PRIMITIVE_SES (0x02) 778#define MPI2_EVENT_PRIMITIVE_EXPANDER (0x03) 779#define MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT (0x04) 780#define MPI2_EVENT_PRIMITIVE_RESERVED3 (0x05) 781#define MPI2_EVENT_PRIMITIVE_RESERVED4 (0x06) 782#define MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED (0x07) 783#define MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED (0x08) 784 785 786/* SAS Initiator Device Status Change Event data */ 787 788typedef struct _MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE 789{ 790 U8 ReasonCode; /* 0x00 */ 791 U8 PhysicalPort; /* 0x01 */ 792 U16 DevHandle; /* 0x02 */ 793 U64 SASAddress; /* 0x04 */ 794} MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE, 795 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE, 796 Mpi2EventDataSasInitDevStatusChange_t, 797 MPI2_POINTER pMpi2EventDataSasInitDevStatusChange_t; 798 799/* SAS Initiator Device Status Change event ReasonCode values */ 800#define MPI2_EVENT_SAS_INIT_RC_ADDED (0x01) 801#define MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING (0x02) 802 803 804/* SAS Initiator Device Table Overflow Event data */ 805 806typedef struct _MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW 807{ 808 U16 MaxInit; /* 0x00 */ 809 U16 CurrentInit; /* 0x02 */ 810 U64 SASAddress; /* 0x04 */ 811} MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW, 812 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW, 813 Mpi2EventDataSasInitTableOverflow_t, 814 MPI2_POINTER pMpi2EventDataSasInitTableOverflow_t; 815 816 817/* SAS Topology Change List Event data */ 818 819/* 820 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 821 * one and check NumEntries at runtime. 822 */ 823#ifndef MPI2_EVENT_SAS_TOPO_PHY_COUNT 824#define MPI2_EVENT_SAS_TOPO_PHY_COUNT (1) 825#endif 826 827typedef struct _MPI2_EVENT_SAS_TOPO_PHY_ENTRY 828{ 829 U16 AttachedDevHandle; /* 0x00 */ 830 U8 LinkRate; /* 0x02 */ 831 U8 PhyStatus; /* 0x03 */ 832} MPI2_EVENT_SAS_TOPO_PHY_ENTRY, MPI2_POINTER PTR_MPI2_EVENT_SAS_TOPO_PHY_ENTRY, 833 Mpi2EventSasTopoPhyEntry_t, MPI2_POINTER pMpi2EventSasTopoPhyEntry_t; 834 835typedef struct _MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST 836{ 837 U16 EnclosureHandle; /* 0x00 */ 838 U16 ExpanderDevHandle; /* 0x02 */ 839 U8 NumPhys; /* 0x04 */ 840 U8 Reserved1; /* 0x05 */ 841 U16 Reserved2; /* 0x06 */ 842 U8 NumEntries; /* 0x08 */ 843 U8 StartPhyNum; /* 0x09 */ 844 U8 ExpStatus; /* 0x0A */ 845 U8 PhysicalPort; /* 0x0B */ 846 MPI2_EVENT_SAS_TOPO_PHY_ENTRY PHY[MPI2_EVENT_SAS_TOPO_PHY_COUNT]; /* 0x0C*/ 847} MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST, 848 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST, 849 Mpi2EventDataSasTopologyChangeList_t, 850 MPI2_POINTER pMpi2EventDataSasTopologyChangeList_t; 851 852/* values for the ExpStatus field */ 853#define MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER (0x00) 854#define MPI2_EVENT_SAS_TOPO_ES_ADDED (0x01) 855#define MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02) 856#define MPI2_EVENT_SAS_TOPO_ES_RESPONDING (0x03) 857#define MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04) 858 859/* defines for the LinkRate field */ 860#define MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK (0xF0) 861#define MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT (4) 862#define MPI2_EVENT_SAS_TOPO_LR_PREV_MASK (0x0F) 863#define MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT (0) 864 865#define MPI2_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE (0x00) 866#define MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED (0x01) 867#define MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED (0x02) 868#define MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE (0x03) 869#define MPI2_EVENT_SAS_TOPO_LR_PORT_SELECTOR (0x04) 870#define MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS (0x05) 871#define MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY (0x06) 872#define MPI2_EVENT_SAS_TOPO_LR_RATE_1_5 (0x08) 873#define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0 (0x09) 874#define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0 (0x0A) 875 876/* values for the PhyStatus field */ 877#define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT (0x80) 878#define MPI2_EVENT_SAS_TOPO_PS_MULTIPLEX_CHANGE (0x10) 879/* values for the PhyStatus ReasonCode sub-field */ 880#define MPI2_EVENT_SAS_TOPO_RC_MASK (0x0F) 881#define MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED (0x01) 882#define MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING (0x02) 883#define MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED (0x03) 884#define MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE (0x04) 885#define MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING (0x05) 886 887 888/* SAS Enclosure Device Status Change Event data */ 889 890typedef struct _MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE 891{ 892 U16 EnclosureHandle; /* 0x00 */ 893 U8 ReasonCode; /* 0x02 */ 894 U8 PhysicalPort; /* 0x03 */ 895 U64 EnclosureLogicalID; /* 0x04 */ 896 U16 NumSlots; /* 0x0C */ 897 U16 StartSlot; /* 0x0E */ 898 U32 PhyBits; /* 0x10 */ 899} MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE, 900 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE, 901 Mpi2EventDataSasEnclDevStatusChange_t, 902 MPI2_POINTER pMpi2EventDataSasEnclDevStatusChange_t; 903 904/* SAS Enclosure Device Status Change event ReasonCode values */ 905#define MPI2_EVENT_SAS_ENCL_RC_ADDED (0x01) 906#define MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING (0x02) 907 908 909/* SAS PHY Counter Event data */ 910 911typedef struct _MPI2_EVENT_DATA_SAS_PHY_COUNTER 912{ 913 U64 TimeStamp; /* 0x00 */ 914 U32 Reserved1; /* 0x08 */ 915 U8 PhyEventCode; /* 0x0C */ 916 U8 PhyNum; /* 0x0D */ 917 U16 Reserved2; /* 0x0E */ 918 U32 PhyEventInfo; /* 0x10 */ 919 U8 CounterType; /* 0x14 */ 920 U8 ThresholdWindow; /* 0x15 */ 921 U8 TimeUnits; /* 0x16 */ 922 U8 Reserved3; /* 0x17 */ 923 U32 EventThreshold; /* 0x18 */ 924 U16 ThresholdFlags; /* 0x1C */ 925 U16 Reserved4; /* 0x1E */ 926} MPI2_EVENT_DATA_SAS_PHY_COUNTER, 927 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_PHY_COUNTER, 928 Mpi2EventDataSasPhyCounter_t, MPI2_POINTER pMpi2EventDataSasPhyCounter_t; 929 930/* use MPI2_SASPHY3_EVENT_CODE_ values from mpi2_cnfg.h for the PhyEventCode field */ 931 932/* use MPI2_SASPHY3_COUNTER_TYPE_ values from mpi2_cnfg.h for the CounterType field */ 933 934/* use MPI2_SASPHY3_TIME_UNITS_ values from mpi2_cnfg.h for the TimeUnits field */ 935 936/* use MPI2_SASPHY3_TFLAGS_ values from mpi2_cnfg.h for the ThresholdFlags field */ 937 938 939/* SAS Quiesce Event data */ 940 941typedef struct _MPI2_EVENT_DATA_SAS_QUIESCE 942{ 943 U8 ReasonCode; /* 0x00 */ 944 U8 Reserved1; /* 0x01 */ 945 U16 Reserved2; /* 0x02 */ 946 U32 Reserved3; /* 0x04 */ 947} MPI2_EVENT_DATA_SAS_QUIESCE, 948 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_QUIESCE, 949 Mpi2EventDataSasQuiesce_t, MPI2_POINTER pMpi2EventDataSasQuiesce_t; 950 951/* SAS Quiesce Event data ReasonCode values */ 952#define MPI2_EVENT_SAS_QUIESCE_RC_STARTED (0x01) 953#define MPI2_EVENT_SAS_QUIESCE_RC_COMPLETED (0x02) 954 955 956/* Host Based Discovery Phy Event data */ 957 958typedef struct _MPI2_EVENT_HBD_PHY_SAS 959{ 960 U8 Flags; /* 0x00 */ 961 U8 NegotiatedLinkRate; /* 0x01 */ 962 U8 PhyNum; /* 0x02 */ 963 U8 PhysicalPort; /* 0x03 */ 964 U32 Reserved1; /* 0x04 */ 965 U8 InitialFrame[28]; /* 0x08 */ 966} MPI2_EVENT_HBD_PHY_SAS, MPI2_POINTER PTR_MPI2_EVENT_HBD_PHY_SAS, 967 Mpi2EventHbdPhySas_t, MPI2_POINTER pMpi2EventHbdPhySas_t; 968 969/* values for the Flags field */ 970#define MPI2_EVENT_HBD_SAS_FLAGS_FRAME_VALID (0x02) 971#define MPI2_EVENT_HBD_SAS_FLAGS_SATA_FRAME (0x01) 972 973/* use MPI2_SAS_NEG_LINK_RATE_ defines from mpi2_cnfg.h for the NegotiatedLinkRate field */ 974 975typedef union _MPI2_EVENT_HBD_DESCRIPTOR 976{ 977 MPI2_EVENT_HBD_PHY_SAS Sas; 978} MPI2_EVENT_HBD_DESCRIPTOR, MPI2_POINTER PTR_MPI2_EVENT_HBD_DESCRIPTOR, 979 Mpi2EventHbdDescriptor_t, MPI2_POINTER pMpi2EventHbdDescriptor_t; 980 981typedef struct _MPI2_EVENT_DATA_HBD_PHY 982{ 983 U8 DescriptorType; /* 0x00 */ 984 U8 Reserved1; /* 0x01 */ 985 U16 Reserved2; /* 0x02 */ 986 U32 Reserved3; /* 0x04 */ 987 MPI2_EVENT_HBD_DESCRIPTOR Descriptor; /* 0x08 */ 988} MPI2_EVENT_DATA_HBD_PHY, MPI2_POINTER PTR_MPI2_EVENT_DATA_HBD_PHY, 989 Mpi2EventDataHbdPhy_t, MPI2_POINTER pMpi2EventDataMpi2EventDataHbdPhy_t; 990 991/* values for the DescriptorType field */ 992#define MPI2_EVENT_HBD_DT_SAS (0x01) 993 994 995 996/**************************************************************************** 997* EventAck message 998****************************************************************************/ 999 1000/* EventAck Request message */ 1001typedef struct _MPI2_EVENT_ACK_REQUEST 1002{ 1003 U16 Reserved1; /* 0x00 */ 1004 U8 ChainOffset; /* 0x02 */ 1005 U8 Function; /* 0x03 */ 1006 U16 Reserved2; /* 0x04 */ 1007 U8 Reserved3; /* 0x06 */ 1008 U8 MsgFlags; /* 0x07 */ 1009 U8 VP_ID; /* 0x08 */ 1010 U8 VF_ID; /* 0x09 */ 1011 U16 Reserved4; /* 0x0A */ 1012 U16 Event; /* 0x0C */ 1013 U16 Reserved5; /* 0x0E */ 1014 U32 EventContext; /* 0x10 */ 1015} MPI2_EVENT_ACK_REQUEST, MPI2_POINTER PTR_MPI2_EVENT_ACK_REQUEST, 1016 Mpi2EventAckRequest_t, MPI2_POINTER pMpi2EventAckRequest_t; 1017 1018 1019/* EventAck Reply message */ 1020typedef struct _MPI2_EVENT_ACK_REPLY 1021{ 1022 U16 Reserved1; /* 0x00 */ 1023 U8 MsgLength; /* 0x02 */ 1024 U8 Function; /* 0x03 */ 1025 U16 Reserved2; /* 0x04 */ 1026 U8 Reserved3; /* 0x06 */ 1027 U8 MsgFlags; /* 0x07 */ 1028 U8 VP_ID; /* 0x08 */ 1029 U8 VF_ID; /* 0x09 */ 1030 U16 Reserved4; /* 0x0A */ 1031 U16 Reserved5; /* 0x0C */ 1032 U16 IOCStatus; /* 0x0E */ 1033 U32 IOCLogInfo; /* 0x10 */ 1034} MPI2_EVENT_ACK_REPLY, MPI2_POINTER PTR_MPI2_EVENT_ACK_REPLY, 1035 Mpi2EventAckReply_t, MPI2_POINTER pMpi2EventAckReply_t; 1036 1037 1038/**************************************************************************** 1039* FWDownload message 1040****************************************************************************/ 1041 1042/* FWDownload Request message */ 1043typedef struct _MPI2_FW_DOWNLOAD_REQUEST 1044{ 1045 U8 ImageType; /* 0x00 */ 1046 U8 Reserved1; /* 0x01 */ 1047 U8 ChainOffset; /* 0x02 */ 1048 U8 Function; /* 0x03 */ 1049 U16 Reserved2; /* 0x04 */ 1050 U8 Reserved3; /* 0x06 */ 1051 U8 MsgFlags; /* 0x07 */ 1052 U8 VP_ID; /* 0x08 */ 1053 U8 VF_ID; /* 0x09 */ 1054 U16 Reserved4; /* 0x0A */ 1055 U32 TotalImageSize; /* 0x0C */ 1056 U32 Reserved5; /* 0x10 */ 1057 MPI2_MPI_SGE_UNION SGL; /* 0x14 */ 1058} MPI2_FW_DOWNLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REQUEST, 1059 Mpi2FWDownloadRequest, MPI2_POINTER pMpi2FWDownloadRequest; 1060 1061#define MPI2_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT (0x01) 1062 1063#define MPI2_FW_DOWNLOAD_ITYPE_FW (0x01) 1064#define MPI2_FW_DOWNLOAD_ITYPE_BIOS (0x02) 1065#define MPI2_FW_DOWNLOAD_ITYPE_MANUFACTURING (0x06) 1066#define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_1 (0x07) 1067#define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_2 (0x08) 1068#define MPI2_FW_DOWNLOAD_ITYPE_MEGARAID (0x09) 1069#define MPI2_FW_DOWNLOAD_ITYPE_COMPLETE (0x0A) 1070#define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B) 1071#define MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC (0xF0) 1072 1073/* FWDownload TransactionContext Element */ 1074typedef struct _MPI2_FW_DOWNLOAD_TCSGE 1075{ 1076 U8 Reserved1; /* 0x00 */ 1077 U8 ContextSize; /* 0x01 */ 1078 U8 DetailsLength; /* 0x02 */ 1079 U8 Flags; /* 0x03 */ 1080 U32 Reserved2; /* 0x04 */ 1081 U32 ImageOffset; /* 0x08 */ 1082 U32 ImageSize; /* 0x0C */ 1083} MPI2_FW_DOWNLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_TCSGE, 1084 Mpi2FWDownloadTCSGE_t, MPI2_POINTER pMpi2FWDownloadTCSGE_t; 1085 1086/* FWDownload Reply message */ 1087typedef struct _MPI2_FW_DOWNLOAD_REPLY 1088{ 1089 U8 ImageType; /* 0x00 */ 1090 U8 Reserved1; /* 0x01 */ 1091 U8 MsgLength; /* 0x02 */ 1092 U8 Function; /* 0x03 */ 1093 U16 Reserved2; /* 0x04 */ 1094 U8 Reserved3; /* 0x06 */ 1095 U8 MsgFlags; /* 0x07 */ 1096 U8 VP_ID; /* 0x08 */ 1097 U8 VF_ID; /* 0x09 */ 1098 U16 Reserved4; /* 0x0A */ 1099 U16 Reserved5; /* 0x0C */ 1100 U16 IOCStatus; /* 0x0E */ 1101 U32 IOCLogInfo; /* 0x10 */ 1102} MPI2_FW_DOWNLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REPLY, 1103 Mpi2FWDownloadReply_t, MPI2_POINTER pMpi2FWDownloadReply_t; 1104 1105 1106/**************************************************************************** 1107* FWUpload message 1108****************************************************************************/ 1109 1110/* FWUpload Request message */ 1111typedef struct _MPI2_FW_UPLOAD_REQUEST 1112{ 1113 U8 ImageType; /* 0x00 */ 1114 U8 Reserved1; /* 0x01 */ 1115 U8 ChainOffset; /* 0x02 */ 1116 U8 Function; /* 0x03 */ 1117 U16 Reserved2; /* 0x04 */ 1118 U8 Reserved3; /* 0x06 */ 1119 U8 MsgFlags; /* 0x07 */ 1120 U8 VP_ID; /* 0x08 */ 1121 U8 VF_ID; /* 0x09 */ 1122 U16 Reserved4; /* 0x0A */ 1123 U32 Reserved5; /* 0x0C */ 1124 U32 Reserved6; /* 0x10 */ 1125 MPI2_MPI_SGE_UNION SGL; /* 0x14 */ 1126} MPI2_FW_UPLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REQUEST, 1127 Mpi2FWUploadRequest_t, MPI2_POINTER pMpi2FWUploadRequest_t; 1128 1129#define MPI2_FW_UPLOAD_ITYPE_FW_CURRENT (0x00) 1130#define MPI2_FW_UPLOAD_ITYPE_FW_FLASH (0x01) 1131#define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH (0x02) 1132#define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP (0x05) 1133#define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING (0x06) 1134#define MPI2_FW_UPLOAD_ITYPE_CONFIG_1 (0x07) 1135#define MPI2_FW_UPLOAD_ITYPE_CONFIG_2 (0x08) 1136#define MPI2_FW_UPLOAD_ITYPE_MEGARAID (0x09) 1137#define MPI2_FW_UPLOAD_ITYPE_COMPLETE (0x0A) 1138#define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B) 1139 1140typedef struct _MPI2_FW_UPLOAD_TCSGE 1141{ 1142 U8 Reserved1; /* 0x00 */ 1143 U8 ContextSize; /* 0x01 */ 1144 U8 DetailsLength; /* 0x02 */ 1145 U8 Flags; /* 0x03 */ 1146 U32 Reserved2; /* 0x04 */ 1147 U32 ImageOffset; /* 0x08 */ 1148 U32 ImageSize; /* 0x0C */ 1149} MPI2_FW_UPLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_UPLOAD_TCSGE, 1150 Mpi2FWUploadTCSGE_t, MPI2_POINTER pMpi2FWUploadTCSGE_t; 1151 1152/* FWUpload Reply message */ 1153typedef struct _MPI2_FW_UPLOAD_REPLY 1154{ 1155 U8 ImageType; /* 0x00 */ 1156 U8 Reserved1; /* 0x01 */ 1157 U8 MsgLength; /* 0x02 */ 1158 U8 Function; /* 0x03 */ 1159 U16 Reserved2; /* 0x04 */ 1160 U8 Reserved3; /* 0x06 */ 1161 U8 MsgFlags; /* 0x07 */ 1162 U8 VP_ID; /* 0x08 */ 1163 U8 VF_ID; /* 0x09 */ 1164 U16 Reserved4; /* 0x0A */ 1165 U16 Reserved5; /* 0x0C */ 1166 U16 IOCStatus; /* 0x0E */ 1167 U32 IOCLogInfo; /* 0x10 */ 1168 U32 ActualImageSize; /* 0x14 */ 1169} MPI2_FW_UPLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REPLY, 1170 Mpi2FWUploadReply_t, MPI2_POINTER pMPi2FWUploadReply_t; 1171 1172 1173/* FW Image Header */ 1174typedef struct _MPI2_FW_IMAGE_HEADER 1175{ 1176 U32 Signature; /* 0x00 */ 1177 U32 Signature0; /* 0x04 */ 1178 U32 Signature1; /* 0x08 */ 1179 U32 Signature2; /* 0x0C */ 1180 MPI2_VERSION_UNION MPIVersion; /* 0x10 */ 1181 MPI2_VERSION_UNION FWVersion; /* 0x14 */ 1182 MPI2_VERSION_UNION NVDATAVersion; /* 0x18 */ 1183 MPI2_VERSION_UNION PackageVersion; /* 0x1C */ 1184 U16 VendorID; /* 0x20 */ 1185 U16 ProductID; /* 0x22 */ 1186 U16 ProtocolFlags; /* 0x24 */ 1187 U16 Reserved26; /* 0x26 */ 1188 U32 IOCCapabilities; /* 0x28 */ 1189 U32 ImageSize; /* 0x2C */ 1190 U32 NextImageHeaderOffset; /* 0x30 */ 1191 U32 Checksum; /* 0x34 */ 1192 U32 Reserved38; /* 0x38 */ 1193 U32 Reserved3C; /* 0x3C */ 1194 U32 Reserved40; /* 0x40 */ 1195 U32 Reserved44; /* 0x44 */ 1196 U32 Reserved48; /* 0x48 */ 1197 U32 Reserved4C; /* 0x4C */ 1198 U32 Reserved50; /* 0x50 */ 1199 U32 Reserved54; /* 0x54 */ 1200 U32 Reserved58; /* 0x58 */ 1201 U32 Reserved5C; /* 0x5C */ 1202 U32 Reserved60; /* 0x60 */ 1203 U32 FirmwareVersionNameWhat; /* 0x64 */ 1204 U8 FirmwareVersionName[32]; /* 0x68 */ 1205 U32 VendorNameWhat; /* 0x88 */ 1206 U8 VendorName[32]; /* 0x8C */ 1207 U32 PackageNameWhat; /* 0x88 */ 1208 U8 PackageName[32]; /* 0x8C */ 1209 U32 ReservedD0; /* 0xD0 */ 1210 U32 ReservedD4; /* 0xD4 */ 1211 U32 ReservedD8; /* 0xD8 */ 1212 U32 ReservedDC; /* 0xDC */ 1213 U32 ReservedE0; /* 0xE0 */ 1214 U32 ReservedE4; /* 0xE4 */ 1215 U32 ReservedE8; /* 0xE8 */ 1216 U32 ReservedEC; /* 0xEC */ 1217 U32 ReservedF0; /* 0xF0 */ 1218 U32 ReservedF4; /* 0xF4 */ 1219 U32 ReservedF8; /* 0xF8 */ 1220 U32 ReservedFC; /* 0xFC */ 1221} MPI2_FW_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_FW_IMAGE_HEADER, 1222 Mpi2FWImageHeader_t, MPI2_POINTER pMpi2FWImageHeader_t; 1223 1224/* Signature field */ 1225#define MPI2_FW_HEADER_SIGNATURE_OFFSET (0x00) 1226#define MPI2_FW_HEADER_SIGNATURE_MASK (0xFF000000) 1227#define MPI2_FW_HEADER_SIGNATURE (0xEA000000) 1228 1229/* Signature0 field */ 1230#define MPI2_FW_HEADER_SIGNATURE0_OFFSET (0x04) 1231#define MPI2_FW_HEADER_SIGNATURE0 (0x5AFAA55A) 1232 1233/* Signature1 field */ 1234#define MPI2_FW_HEADER_SIGNATURE1_OFFSET (0x08) 1235#define MPI2_FW_HEADER_SIGNATURE1 (0xA55AFAA5) 1236 1237/* Signature2 field */ 1238#define MPI2_FW_HEADER_SIGNATURE2_OFFSET (0x0C) 1239#define MPI2_FW_HEADER_SIGNATURE2 (0x5AA55AFA) 1240 1241 1242/* defines for using the ProductID field */ 1243#define MPI2_FW_HEADER_PID_TYPE_MASK (0xF000) 1244#define MPI2_FW_HEADER_PID_TYPE_SAS (0x2000) 1245 1246#define MPI2_FW_HEADER_PID_PROD_MASK (0x0F00) 1247#define MPI2_FW_HEADER_PID_PROD_A (0x0000) 1248#define MPI2_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI (0x0200) 1249#define MPI2_FW_HEADER_PID_PROD_IR_SCSI (0x0700) 1250 1251 1252#define MPI2_FW_HEADER_PID_FAMILY_MASK (0x00FF) 1253/* SAS */ 1254#define MPI2_FW_HEADER_PID_FAMILY_2108_SAS (0x0013) 1255#define MPI2_FW_HEADER_PID_FAMILY_2208_SAS (0x0014) 1256 1257/* use MPI2_IOCFACTS_PROTOCOL_ defines for ProtocolFlags field */ 1258 1259/* use MPI2_IOCFACTS_CAPABILITY_ defines for IOCCapabilities field */ 1260 1261 1262#define MPI2_FW_HEADER_IMAGESIZE_OFFSET (0x2C) 1263#define MPI2_FW_HEADER_NEXTIMAGE_OFFSET (0x30) 1264#define MPI2_FW_HEADER_VERNMHWAT_OFFSET (0x64) 1265 1266#define MPI2_FW_HEADER_WHAT_SIGNATURE (0x29232840) 1267 1268#define MPI2_FW_HEADER_SIZE (0x100) 1269 1270 1271/* Extended Image Header */ 1272typedef struct _MPI2_EXT_IMAGE_HEADER 1273 1274{ 1275 U8 ImageType; /* 0x00 */ 1276 U8 Reserved1; /* 0x01 */ 1277 U16 Reserved2; /* 0x02 */ 1278 U32 Checksum; /* 0x04 */ 1279 U32 ImageSize; /* 0x08 */ 1280 U32 NextImageHeaderOffset; /* 0x0C */ 1281 U32 PackageVersion; /* 0x10 */ 1282 U32 Reserved3; /* 0x14 */ 1283 U32 Reserved4; /* 0x18 */ 1284 U32 Reserved5; /* 0x1C */ 1285 U8 IdentifyString[32]; /* 0x20 */ 1286} MPI2_EXT_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_EXT_IMAGE_HEADER, 1287 Mpi2ExtImageHeader_t, MPI2_POINTER pMpi2ExtImageHeader_t; 1288 1289/* useful offsets */ 1290#define MPI2_EXT_IMAGE_IMAGETYPE_OFFSET (0x00) 1291#define MPI2_EXT_IMAGE_IMAGESIZE_OFFSET (0x08) 1292#define MPI2_EXT_IMAGE_NEXTIMAGE_OFFSET (0x0C) 1293 1294#define MPI2_EXT_IMAGE_HEADER_SIZE (0x40) 1295 1296/* defines for the ImageType field */ 1297#define MPI2_EXT_IMAGE_TYPE_UNSPECIFIED (0x00) 1298#define MPI2_EXT_IMAGE_TYPE_FW (0x01) 1299#define MPI2_EXT_IMAGE_TYPE_NVDATA (0x03) 1300#define MPI2_EXT_IMAGE_TYPE_BOOTLOADER (0x04) 1301#define MPI2_EXT_IMAGE_TYPE_INITIALIZATION (0x05) 1302#define MPI2_EXT_IMAGE_TYPE_FLASH_LAYOUT (0x06) 1303#define MPI2_EXT_IMAGE_TYPE_SUPPORTED_DEVICES (0x07) 1304#define MPI2_EXT_IMAGE_TYPE_MEGARAID (0x08) 1305 1306#define MPI2_EXT_IMAGE_TYPE_MAX (MPI2_EXT_IMAGE_TYPE_MEGARAID) 1307 1308 1309 1310/* FLASH Layout Extended Image Data */ 1311 1312/* 1313 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1314 * one and check RegionsPerLayout at runtime. 1315 */ 1316#ifndef MPI2_FLASH_NUMBER_OF_REGIONS 1317#define MPI2_FLASH_NUMBER_OF_REGIONS (1) 1318#endif 1319 1320/* 1321 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1322 * one and check NumberOfLayouts at runtime. 1323 */ 1324#ifndef MPI2_FLASH_NUMBER_OF_LAYOUTS 1325#define MPI2_FLASH_NUMBER_OF_LAYOUTS (1) 1326#endif 1327 1328typedef struct _MPI2_FLASH_REGION 1329{ 1330 U8 RegionType; /* 0x00 */ 1331 U8 Reserved1; /* 0x01 */ 1332 U16 Reserved2; /* 0x02 */ 1333 U32 RegionOffset; /* 0x04 */ 1334 U32 RegionSize; /* 0x08 */ 1335 U32 Reserved3; /* 0x0C */ 1336} MPI2_FLASH_REGION, MPI2_POINTER PTR_MPI2_FLASH_REGION, 1337 Mpi2FlashRegion_t, MPI2_POINTER pMpi2FlashRegion_t; 1338 1339typedef struct _MPI2_FLASH_LAYOUT 1340{ 1341 U32 FlashSize; /* 0x00 */ 1342 U32 Reserved1; /* 0x04 */ 1343 U32 Reserved2; /* 0x08 */ 1344 U32 Reserved3; /* 0x0C */ 1345 MPI2_FLASH_REGION Region[MPI2_FLASH_NUMBER_OF_REGIONS];/* 0x10 */ 1346} MPI2_FLASH_LAYOUT, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT, 1347 Mpi2FlashLayout_t, MPI2_POINTER pMpi2FlashLayout_t; 1348 1349typedef struct _MPI2_FLASH_LAYOUT_DATA 1350{ 1351 U8 ImageRevision; /* 0x00 */ 1352 U8 Reserved1; /* 0x01 */ 1353 U8 SizeOfRegion; /* 0x02 */ 1354 U8 Reserved2; /* 0x03 */ 1355 U16 NumberOfLayouts; /* 0x04 */ 1356 U16 RegionsPerLayout; /* 0x06 */ 1357 U16 MinimumSectorAlignment; /* 0x08 */ 1358 U16 Reserved3; /* 0x0A */ 1359 U32 Reserved4; /* 0x0C */ 1360 MPI2_FLASH_LAYOUT Layout[MPI2_FLASH_NUMBER_OF_LAYOUTS];/* 0x10 */ 1361} MPI2_FLASH_LAYOUT_DATA, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT_DATA, 1362 Mpi2FlashLayoutData_t, MPI2_POINTER pMpi2FlashLayoutData_t; 1363 1364/* defines for the RegionType field */ 1365#define MPI2_FLASH_REGION_UNUSED (0x00) 1366#define MPI2_FLASH_REGION_FIRMWARE (0x01) 1367#define MPI2_FLASH_REGION_BIOS (0x02) 1368#define MPI2_FLASH_REGION_NVDATA (0x03) 1369#define MPI2_FLASH_REGION_FIRMWARE_BACKUP (0x05) 1370#define MPI2_FLASH_REGION_MFG_INFORMATION (0x06) 1371#define MPI2_FLASH_REGION_CONFIG_1 (0x07) 1372#define MPI2_FLASH_REGION_CONFIG_2 (0x08) 1373#define MPI2_FLASH_REGION_MEGARAID (0x09) 1374#define MPI2_FLASH_REGION_INIT (0x0A) 1375 1376/* ImageRevision */ 1377#define MPI2_FLASH_LAYOUT_IMAGE_REVISION (0x00) 1378 1379 1380 1381/* Supported Devices Extended Image Data */ 1382 1383/* 1384 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1385 * one and check NumberOfDevices at runtime. 1386 */ 1387#ifndef MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES 1388#define MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES (1) 1389#endif 1390 1391typedef struct _MPI2_SUPPORTED_DEVICE 1392{ 1393 U16 DeviceID; /* 0x00 */ 1394 U16 VendorID; /* 0x02 */ 1395 U16 DeviceIDMask; /* 0x04 */ 1396 U16 Reserved1; /* 0x06 */ 1397 U8 LowPCIRev; /* 0x08 */ 1398 U8 HighPCIRev; /* 0x09 */ 1399 U16 Reserved2; /* 0x0A */ 1400 U32 Reserved3; /* 0x0C */ 1401} MPI2_SUPPORTED_DEVICE, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICE, 1402 Mpi2SupportedDevice_t, MPI2_POINTER pMpi2SupportedDevice_t; 1403 1404typedef struct _MPI2_SUPPORTED_DEVICES_DATA 1405{ 1406 U8 ImageRevision; /* 0x00 */ 1407 U8 Reserved1; /* 0x01 */ 1408 U8 NumberOfDevices; /* 0x02 */ 1409 U8 Reserved2; /* 0x03 */ 1410 U32 Reserved3; /* 0x04 */ 1411 MPI2_SUPPORTED_DEVICE SupportedDevice[MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES]; /* 0x08 */ 1412} MPI2_SUPPORTED_DEVICES_DATA, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICES_DATA, 1413 Mpi2SupportedDevicesData_t, MPI2_POINTER pMpi2SupportedDevicesData_t; 1414 1415/* ImageRevision */ 1416#define MPI2_SUPPORTED_DEVICES_IMAGE_REVISION (0x00) 1417 1418 1419/* Init Extended Image Data */ 1420 1421typedef struct _MPI2_INIT_IMAGE_FOOTER 1422 1423{ 1424 U32 BootFlags; /* 0x00 */ 1425 U32 ImageSize; /* 0x04 */ 1426 U32 Signature0; /* 0x08 */ 1427 U32 Signature1; /* 0x0C */ 1428 U32 Signature2; /* 0x10 */ 1429 U32 ResetVector; /* 0x14 */ 1430} MPI2_INIT_IMAGE_FOOTER, MPI2_POINTER PTR_MPI2_INIT_IMAGE_FOOTER, 1431 Mpi2InitImageFooter_t, MPI2_POINTER pMpi2InitImageFooter_t; 1432 1433/* defines for the BootFlags field */ 1434#define MPI2_INIT_IMAGE_BOOTFLAGS_OFFSET (0x00) 1435 1436/* defines for the ImageSize field */ 1437#define MPI2_INIT_IMAGE_IMAGESIZE_OFFSET (0x04) 1438 1439/* defines for the Signature0 field */ 1440#define MPI2_INIT_IMAGE_SIGNATURE0_OFFSET (0x08) 1441#define MPI2_INIT_IMAGE_SIGNATURE0 (0x5AA55AEA) 1442 1443/* defines for the Signature1 field */ 1444#define MPI2_INIT_IMAGE_SIGNATURE1_OFFSET (0x0C) 1445#define MPI2_INIT_IMAGE_SIGNATURE1 (0xA55AEAA5) 1446 1447/* defines for the Signature2 field */ 1448#define MPI2_INIT_IMAGE_SIGNATURE2_OFFSET (0x10) 1449#define MPI2_INIT_IMAGE_SIGNATURE2 (0x5AEAA55A) 1450 1451/* Signature fields as individual bytes */ 1452#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_0 (0xEA) 1453#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_1 (0x5A) 1454#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_2 (0xA5) 1455#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_3 (0x5A) 1456 1457#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_4 (0xA5) 1458#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_5 (0xEA) 1459#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_6 (0x5A) 1460#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_7 (0xA5) 1461 1462#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_8 (0x5A) 1463#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_9 (0xA5) 1464#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_A (0xEA) 1465#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_B (0x5A) 1466 1467/* defines for the ResetVector field */ 1468#define MPI2_INIT_IMAGE_RESETVECTOR_OFFSET (0x14) 1469 1470 1471/**************************************************************************** 1472* PowerManagementControl message 1473****************************************************************************/ 1474 1475/* PowerManagementControl Request message */ 1476typedef struct _MPI2_PWR_MGMT_CONTROL_REQUEST 1477{ 1478 U8 Feature; /* 0x00 */ 1479 U8 Reserved1; /* 0x01 */ 1480 U8 ChainOffset; /* 0x02 */ 1481 U8 Function; /* 0x03 */ 1482 U16 Reserved2; /* 0x04 */ 1483 U8 Reserved3; /* 0x06 */ 1484 U8 MsgFlags; /* 0x07 */ 1485 U8 VP_ID; /* 0x08 */ 1486 U8 VF_ID; /* 0x09 */ 1487 U16 Reserved4; /* 0x0A */ 1488 U8 Parameter1; /* 0x0C */ 1489 U8 Parameter2; /* 0x0D */ 1490 U8 Parameter3; /* 0x0E */ 1491 U8 Parameter4; /* 0x0F */ 1492 U32 Reserved5; /* 0x10 */ 1493 U32 Reserved6; /* 0x14 */ 1494} MPI2_PWR_MGMT_CONTROL_REQUEST, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REQUEST, 1495 Mpi2PwrMgmtControlRequest_t, MPI2_POINTER pMpi2PwrMgmtControlRequest_t; 1496 1497/* defines for the Feature field */ 1498#define MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND (0x01) 1499#define MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION (0x02) 1500#define MPI2_PM_CONTROL_FEATURE_PCIE_LINK (0x03) 1501#define MPI2_PM_CONTROL_FEATURE_IOC_SPEED (0x04) 1502#define MPI2_PM_CONTROL_FEATURE_MIN_PRODUCT_SPECIFIC (0x80) 1503#define MPI2_PM_CONTROL_FEATURE_MAX_PRODUCT_SPECIFIC (0xFF) 1504 1505/* parameter usage for the MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND Feature */ 1506/* Parameter1 contains a PHY number */ 1507/* Parameter2 indicates power condition action using these defines */ 1508#define MPI2_PM_CONTROL_PARAM2_PARTIAL (0x01) 1509#define MPI2_PM_CONTROL_PARAM2_SLUMBER (0x02) 1510#define MPI2_PM_CONTROL_PARAM2_EXIT_PWR_MGMT (0x03) 1511/* Parameter3 and Parameter4 are reserved */ 1512 1513/* parameter usage for the MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION Feature */ 1514/* Parameter1 contains SAS port width modulation group number */ 1515/* Parameter2 indicates IOC action using these defines */ 1516#define MPI2_PM_CONTROL_PARAM2_REQUEST_OWNERSHIP (0x01) 1517#define MPI2_PM_CONTROL_PARAM2_CHANGE_MODULATION (0x02) 1518#define MPI2_PM_CONTROL_PARAM2_RELINQUISH_OWNERSHIP (0x03) 1519/* Parameter3 indicates desired modulation level using these defines */ 1520#define MPI2_PM_CONTROL_PARAM3_25_PERCENT (0x00) 1521#define MPI2_PM_CONTROL_PARAM3_50_PERCENT (0x01) 1522#define MPI2_PM_CONTROL_PARAM3_75_PERCENT (0x02) 1523#define MPI2_PM_CONTROL_PARAM3_100_PERCENT (0x03) 1524/* Parameter4 is reserved */ 1525 1526/* parameter usage for the MPI2_PM_CONTROL_FEATURE_PCIE_LINK Feature */ 1527/* Parameter1 indicates desired PCIe link speed using these defines */ 1528#define MPI2_PM_CONTROL_PARAM1_PCIE_2_5_GBPS (0x00) 1529#define MPI2_PM_CONTROL_PARAM1_PCIE_5_0_GBPS (0x01) 1530#define MPI2_PM_CONTROL_PARAM1_PCIE_8_0_GBPS (0x02) 1531/* Parameter2 indicates desired PCIe link width using these defines */ 1532#define MPI2_PM_CONTROL_PARAM2_WIDTH_X1 (0x01) 1533#define MPI2_PM_CONTROL_PARAM2_WIDTH_X2 (0x02) 1534#define MPI2_PM_CONTROL_PARAM2_WIDTH_X4 (0x04) 1535#define MPI2_PM_CONTROL_PARAM2_WIDTH_X8 (0x08) 1536/* Parameter3 and Parameter4 are reserved */ 1537 1538/* parameter usage for the MPI2_PM_CONTROL_FEATURE_IOC_SPEED Feature */ 1539/* Parameter1 indicates desired IOC hardware clock speed using these defines */ 1540#define MPI2_PM_CONTROL_PARAM1_FULL_IOC_SPEED (0x01) 1541#define MPI2_PM_CONTROL_PARAM1_HALF_IOC_SPEED (0x02) 1542#define MPI2_PM_CONTROL_PARAM1_QUARTER_IOC_SPEED (0x04) 1543#define MPI2_PM_CONTROL_PARAM1_EIGHTH_IOC_SPEED (0x08) 1544/* Parameter2, Parameter3, and Parameter4 are reserved */ 1545 1546 1547/* PowerManagementControl Reply message */ 1548typedef struct _MPI2_PWR_MGMT_CONTROL_REPLY 1549{ 1550 U8 Feature; /* 0x00 */ 1551 U8 Reserved1; /* 0x01 */ 1552 U8 MsgLength; /* 0x02 */ 1553 U8 Function; /* 0x03 */ 1554 U16 Reserved2; /* 0x04 */ 1555 U8 Reserved3; /* 0x06 */ 1556 U8 MsgFlags; /* 0x07 */ 1557 U8 VP_ID; /* 0x08 */ 1558 U8 VF_ID; /* 0x09 */ 1559 U16 Reserved4; /* 0x0A */ 1560 U16 Reserved5; /* 0x0C */ 1561 U16 IOCStatus; /* 0x0E */ 1562 U32 IOCLogInfo; /* 0x10 */ 1563} MPI2_PWR_MGMT_CONTROL_REPLY, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REPLY, 1564 Mpi2PwrMgmtControlReply_t, MPI2_POINTER pMpi2PwrMgmtControlReply_t; 1565 1566 1567#endif 1568 1569