1/*- 2 * Copyright (c) 2012-2015 LSI Corp. 3 * Copyright (c) 2013-2016 Avago Technologies 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the name of the author nor the names of any co-contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * Avago Technologies (LSI) MPT-Fusion Host Adapter FreeBSD 31 * 32 * $FreeBSD: stable/11/sys/dev/mpr/mpi/mpi2_pci.h 319435 2017-06-01 15:39:09Z slm $ 33 */ 34 35/* 36 * Copyright (c) 2000-2015 LSI Corporation. 37 * Copyright (c) 2013-2016 Avago Technologies 38 * All rights reserved. 39 * 40 * 41 * Name: mpi2_pci.h 42 * Title: MPI PCIe Attached Devices structures and definitions. 43 * Creation Date: October 9, 2012 44 * 45 * mpi2_pci.h Version: 02.00.02 46 * 47 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 48 * prefix are for use only on MPI v2.5 products, and must not be used 49 * with MPI v2.0 products. Unless otherwise noted, names beginning with 50 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products. 51 * 52 * Version History 53 * --------------- 54 * 55 * Date Version Description 56 * -------- -------- ------------------------------------------------------ 57 * 03-16-15 02.00.00 Initial version. 58 * 02-17-16 02.00.01 Removed AHCI support. 59 * Removed SOP support. 60 * 07-01-16 02.00.02 Added MPI26_NVME_FLAGS_FORCE_ADMIN_ERR_RESP to 61 * NVME Encapsulated Request. 62 * -------------------------------------------------------------------------- 63 */ 64 65#ifndef MPI2_PCI_H 66#define MPI2_PCI_H 67 68 69/* 70 * Values for the PCIe DeviceInfo field used in PCIe Device Status Change Event 71 * data and PCIe Configuration pages. 72 */ 73#define MPI26_PCIE_DEVINFO_DIRECT_ATTACH (0x00000010) 74 75#define MPI26_PCIE_DEVINFO_MASK_DEVICE_TYPE (0x0000000F) 76#define MPI26_PCIE_DEVINFO_NO_DEVICE (0x00000000) 77#define MPI26_PCIE_DEVINFO_PCI_SWITCH (0x00000001) 78#define MPI26_PCIE_DEVINFO_NVME (0x00000003) 79 80 81/**************************************************************************** 82* NVMe Encapsulated message 83****************************************************************************/ 84 85/* NVME Encapsulated Request Message */ 86typedef struct _MPI26_NVME_ENCAPSULATED_REQUEST 87{ 88 U16 DevHandle; /* 0x00 */ 89 U8 ChainOffset; /* 0x02 */ 90 U8 Function; /* 0x03 */ 91 U16 EncapsulatedCommandLength; /* 0x04 */ 92 U8 Reserved1; /* 0x06 */ 93 U8 MsgFlags; /* 0x07 */ 94 U8 VP_ID; /* 0x08 */ 95 U8 VF_ID; /* 0x09 */ 96 U16 Reserved2; /* 0x0A */ 97 U32 Reserved3; /* 0x0C */ 98 U64 ErrorResponseBaseAddress; /* 0x10 */ 99 U16 ErrorResponseAllocationLength; /* 0x18 */ 100 U16 Flags; /* 0x1A */ 101 U32 DataLength; /* 0x1C */ 102 U8 NVMe_Command[4]; /* 0x20 */ /* variable length */ 103 104} MPI26_NVME_ENCAPSULATED_REQUEST, MPI2_POINTER PTR_MPI26_NVME_ENCAPSULATED_REQUEST, 105 Mpi26NVMeEncapsulatedRequest_t, MPI2_POINTER pMpi26NVMeEncapsulatedRequest_t; 106 107/* defines for the Flags field */ 108#define MPI26_NVME_FLAGS_FORCE_ADMIN_ERR_RESP (0x0020) 109/* Submission Queue Type*/ 110#define MPI26_NVME_FLAGS_SUBMISSIONQ_MASK (0x0010) 111#define MPI26_NVME_FLAGS_SUBMISSIONQ_IO (0x0000) 112#define MPI26_NVME_FLAGS_SUBMISSIONQ_ADMIN (0x0010) 113/* Error Response Address Space */ 114#define MPI26_NVME_FLAGS_MASK_ERROR_RSP_ADDR (0x000C) 115#define MPI26_NVME_FLAGS_SYSTEM_RSP_ADDR (0x0000) 116#define MPI26_NVME_FLAGS_IOCPLB_RSP_ADDR (0x0008) 117#define MPI26_NVME_FLAGS_IOCPLBNTA_RSP_ADDR (0x000C) 118/* Data Direction*/ 119#define MPI26_NVME_FLAGS_DATADIRECTION_MASK (0x0003) 120#define MPI26_NVME_FLAGS_NODATATRANSFER (0x0000) 121#define MPI26_NVME_FLAGS_WRITE (0x0001) 122#define MPI26_NVME_FLAGS_READ (0x0002) 123#define MPI26_NVME_FLAGS_BIDIRECTIONAL (0x0003) 124 125 126/* NVMe Encapuslated Reply Message */ 127typedef struct _MPI26_NVME_ENCAPSULATED_ERROR_REPLY 128{ 129 U16 DevHandle; /* 0x00 */ 130 U8 MsgLength; /* 0x02 */ 131 U8 Function; /* 0x03 */ 132 U16 EncapsulatedCommandLength; /* 0x04 */ 133 U8 Reserved1; /* 0x06 */ 134 U8 MsgFlags; /* 0x07 */ 135 U8 VP_ID; /* 0x08 */ 136 U8 VF_ID; /* 0x09 */ 137 U16 Reserved2; /* 0x0A */ 138 U16 Reserved3; /* 0x0C */ 139 U16 IOCStatus; /* 0x0E */ 140 U32 IOCLogInfo; /* 0x10 */ 141 U16 ErrorResponseCount; /* 0x14 */ 142 U16 Reserved4; /* 0x16 */ 143} MPI26_NVME_ENCAPSULATED_ERROR_REPLY, 144 MPI2_POINTER PTR_MPI26_NVME_ENCAPSULATED_ERROR_REPLY, 145 Mpi26NVMeEncapsulatedErrorReply_t, 146 MPI2_POINTER pMpi26NVMeEncapsulatedErrorReply_t; 147 148 149#endif 150 151 152