mlx5_ib_main.c revision 347855
1/*- 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD: stable/11/sys/dev/mlx5/mlx5_ib/mlx5_ib_main.c 347855 2019-05-16 18:06:56Z hselasky $ 26 */ 27 28#include <linux/module.h> 29#include <linux/errno.h> 30#include <linux/pci.h> 31#include <linux/dma-mapping.h> 32#include <linux/slab.h> 33#if defined(CONFIG_X86) 34#include <asm/pat.h> 35#endif 36#include <linux/sched.h> 37#include <linux/delay.h> 38#include <linux/fs.h> 39#undef inode 40#include <rdma/ib_user_verbs.h> 41#include <rdma/ib_addr.h> 42#include <rdma/ib_cache.h> 43#include <dev/mlx5/port.h> 44#include <dev/mlx5/vport.h> 45#include <linux/list.h> 46#include <rdma/ib_smi.h> 47#include <rdma/ib_umem.h> 48#include <linux/in.h> 49#include <linux/etherdevice.h> 50#include <dev/mlx5/fs.h> 51#include "mlx5_ib.h" 52 53#define DRIVER_NAME "mlx5ib" 54#ifndef DRIVER_VERSION 55#define DRIVER_VERSION "3.5.0" 56#endif 57#define DRIVER_RELDATE "November 2018" 58 59MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver"); 60MODULE_LICENSE("Dual BSD/GPL"); 61MODULE_DEPEND(mlx5ib, linuxkpi, 1, 1, 1); 62MODULE_DEPEND(mlx5ib, mlx5, 1, 1, 1); 63MODULE_DEPEND(mlx5ib, ibcore, 1, 1, 1); 64MODULE_VERSION(mlx5ib, 1); 65 66static const char mlx5_version[] = 67 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver " 68 DRIVER_VERSION " (" DRIVER_RELDATE ")\n"; 69 70enum { 71 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 72}; 73 74static enum rdma_link_layer 75mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 76{ 77 switch (port_type_cap) { 78 case MLX5_CAP_PORT_TYPE_IB: 79 return IB_LINK_LAYER_INFINIBAND; 80 case MLX5_CAP_PORT_TYPE_ETH: 81 return IB_LINK_LAYER_ETHERNET; 82 default: 83 return IB_LINK_LAYER_UNSPECIFIED; 84 } 85} 86 87static enum rdma_link_layer 88mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num) 89{ 90 struct mlx5_ib_dev *dev = to_mdev(device); 91 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 92 93 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 94} 95 96static bool mlx5_netdev_match(struct net_device *ndev, 97 struct mlx5_core_dev *mdev, 98 const char *dname) 99{ 100 return ndev->if_type == IFT_ETHER && 101 ndev->if_dname != NULL && 102 strcmp(ndev->if_dname, dname) == 0 && 103 ndev->if_softc != NULL && 104 *(struct mlx5_core_dev **)ndev->if_softc == mdev; 105} 106 107static int mlx5_netdev_event(struct notifier_block *this, 108 unsigned long event, void *ptr) 109{ 110 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 111 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev, 112 roce.nb); 113 114 switch (event) { 115 case NETDEV_REGISTER: 116 case NETDEV_UNREGISTER: 117 write_lock(&ibdev->roce.netdev_lock); 118 /* check if network interface belongs to mlx5en */ 119 if (mlx5_netdev_match(ndev, ibdev->mdev, "mce")) 120 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ? 121 NULL : ndev; 122 write_unlock(&ibdev->roce.netdev_lock); 123 break; 124 125 case NETDEV_UP: 126 case NETDEV_DOWN: { 127 struct net_device *upper = NULL; 128 129 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev)) 130 && ibdev->ib_active) { 131 struct ib_event ibev = {0}; 132 133 ibev.device = &ibdev->ib_dev; 134 ibev.event = (event == NETDEV_UP) ? 135 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 136 ibev.element.port_num = 1; 137 ib_dispatch_event(&ibev); 138 } 139 break; 140 } 141 142 default: 143 break; 144 } 145 146 return NOTIFY_DONE; 147} 148 149static struct net_device *mlx5_ib_get_netdev(struct ib_device *device, 150 u8 port_num) 151{ 152 struct mlx5_ib_dev *ibdev = to_mdev(device); 153 struct net_device *ndev; 154 155 /* Ensure ndev does not disappear before we invoke dev_hold() 156 */ 157 read_lock(&ibdev->roce.netdev_lock); 158 ndev = ibdev->roce.netdev; 159 if (ndev) 160 dev_hold(ndev); 161 read_unlock(&ibdev->roce.netdev_lock); 162 163 return ndev; 164} 165 166static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed, 167 u8 *active_width) 168{ 169 switch (eth_proto_oper) { 170 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII): 171 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX): 172 case MLX5E_PROT_MASK(MLX5E_100BASE_TX): 173 case MLX5E_PROT_MASK(MLX5E_1000BASE_T): 174 *active_width = IB_WIDTH_1X; 175 *active_speed = IB_SPEED_SDR; 176 break; 177 case MLX5E_PROT_MASK(MLX5E_10GBASE_T): 178 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4): 179 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4): 180 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR): 181 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR): 182 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR): 183 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER_LR): 184 *active_width = IB_WIDTH_1X; 185 *active_speed = IB_SPEED_QDR; 186 break; 187 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR): 188 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR): 189 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR): 190 *active_width = IB_WIDTH_1X; 191 *active_speed = IB_SPEED_EDR; 192 break; 193 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4): 194 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4): 195 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4): 196 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4_ER4): 197 *active_width = IB_WIDTH_4X; 198 *active_speed = IB_SPEED_QDR; 199 break; 200 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2): 201 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2): 202 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2): 203 *active_width = IB_WIDTH_1X; 204 *active_speed = IB_SPEED_HDR; 205 break; 206 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4): 207 *active_width = IB_WIDTH_4X; 208 *active_speed = IB_SPEED_FDR; 209 break; 210 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4): 211 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4): 212 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4): 213 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4): 214 *active_width = IB_WIDTH_4X; 215 *active_speed = IB_SPEED_EDR; 216 break; 217 default: 218 *active_width = IB_WIDTH_4X; 219 *active_speed = IB_SPEED_QDR; 220 return -EINVAL; 221 } 222 223 return 0; 224} 225 226static int mlx5_query_port_roce(struct ib_device *device, u8 port_num, 227 struct ib_port_attr *props) 228{ 229 struct mlx5_ib_dev *dev = to_mdev(device); 230 struct net_device *ndev; 231 enum ib_mtu ndev_ib_mtu; 232 u16 qkey_viol_cntr; 233 u32 eth_prot_oper; 234 int err; 235 236 memset(props, 0, sizeof(*props)); 237 238 /* Possible bad flows are checked before filling out props so in case 239 * of an error it will still be zeroed out. 240 */ 241 err = mlx5_query_port_eth_proto_oper(dev->mdev, ð_prot_oper, port_num); 242 if (err) 243 return err; 244 245 translate_eth_proto_oper(eth_prot_oper, &props->active_speed, 246 &props->active_width); 247 248 props->port_cap_flags |= IB_PORT_CM_SUP; 249 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS; 250 251 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 252 roce_address_table_size); 253 props->max_mtu = IB_MTU_4096; 254 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 255 props->pkey_tbl_len = 1; 256 props->state = IB_PORT_DOWN; 257 props->phys_state = 3; 258 259 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr); 260 props->qkey_viol_cntr = qkey_viol_cntr; 261 262 ndev = mlx5_ib_get_netdev(device, port_num); 263 if (!ndev) 264 return 0; 265 266 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 267 props->state = IB_PORT_ACTIVE; 268 props->phys_state = 5; 269 } 270 271 ndev_ib_mtu = iboe_get_mtu(ndev->if_mtu); 272 273 dev_put(ndev); 274 275 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 276 return 0; 277} 278 279static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid, 280 const struct ib_gid_attr *attr, 281 void *mlx5_addr) 282{ 283#define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v) 284 char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr, 285 source_l3_address); 286 void *mlx5_addr_mac = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr, 287 source_mac_47_32); 288 u16 vlan_id; 289 290 if (!gid) 291 return; 292 ether_addr_copy(mlx5_addr_mac, IF_LLADDR(attr->ndev)); 293 294 vlan_id = rdma_vlan_dev_vlan_id(attr->ndev); 295 if (vlan_id != 0xffff) { 296 MLX5_SET_RA(mlx5_addr, vlan_valid, 1); 297 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_id); 298 } 299 300 switch (attr->gid_type) { 301 case IB_GID_TYPE_IB: 302 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1); 303 break; 304 case IB_GID_TYPE_ROCE_UDP_ENCAP: 305 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2); 306 break; 307 308 default: 309 WARN_ON(true); 310 } 311 312 if (attr->gid_type != IB_GID_TYPE_IB) { 313 if (ipv6_addr_v4mapped((void *)gid)) 314 MLX5_SET_RA(mlx5_addr, roce_l3_type, 315 MLX5_ROCE_L3_TYPE_IPV4); 316 else 317 MLX5_SET_RA(mlx5_addr, roce_l3_type, 318 MLX5_ROCE_L3_TYPE_IPV6); 319 } 320 321 if ((attr->gid_type == IB_GID_TYPE_IB) || 322 !ipv6_addr_v4mapped((void *)gid)) 323 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid)); 324 else 325 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4); 326} 327 328static int set_roce_addr(struct ib_device *device, u8 port_num, 329 unsigned int index, 330 const union ib_gid *gid, 331 const struct ib_gid_attr *attr) 332{ 333 struct mlx5_ib_dev *dev = to_mdev(device); 334 u32 in[MLX5_ST_SZ_DW(set_roce_address_in)] = {0}; 335 u32 out[MLX5_ST_SZ_DW(set_roce_address_out)] = {0}; 336 void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address); 337 enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num); 338 339 if (ll != IB_LINK_LAYER_ETHERNET) 340 return -EINVAL; 341 342 ib_gid_to_mlx5_roce_addr(gid, attr, in_addr); 343 344 MLX5_SET(set_roce_address_in, in, roce_address_index, index); 345 MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS); 346 return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out)); 347} 348 349static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num, 350 unsigned int index, const union ib_gid *gid, 351 const struct ib_gid_attr *attr, 352 __always_unused void **context) 353{ 354 return set_roce_addr(device, port_num, index, gid, attr); 355} 356 357static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num, 358 unsigned int index, __always_unused void **context) 359{ 360 return set_roce_addr(device, port_num, index, NULL, NULL); 361} 362 363__be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num, 364 int index) 365{ 366 struct ib_gid_attr attr; 367 union ib_gid gid; 368 369 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr)) 370 return 0; 371 372 if (!attr.ndev) 373 return 0; 374 375 dev_put(attr.ndev); 376 377 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 378 return 0; 379 380 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 381} 382 383int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num, 384 int index, enum ib_gid_type *gid_type) 385{ 386 struct ib_gid_attr attr; 387 union ib_gid gid; 388 int ret; 389 390 ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr); 391 if (ret) 392 return ret; 393 394 if (!attr.ndev) 395 return -ENODEV; 396 397 dev_put(attr.ndev); 398 399 *gid_type = attr.gid_type; 400 401 return 0; 402} 403 404static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 405{ 406 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 407 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 408 return 0; 409} 410 411enum { 412 MLX5_VPORT_ACCESS_METHOD_MAD, 413 MLX5_VPORT_ACCESS_METHOD_HCA, 414 MLX5_VPORT_ACCESS_METHOD_NIC, 415}; 416 417static int mlx5_get_vport_access_method(struct ib_device *ibdev) 418{ 419 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 420 return MLX5_VPORT_ACCESS_METHOD_MAD; 421 422 if (mlx5_ib_port_link_layer(ibdev, 1) == 423 IB_LINK_LAYER_ETHERNET) 424 return MLX5_VPORT_ACCESS_METHOD_NIC; 425 426 return MLX5_VPORT_ACCESS_METHOD_HCA; 427} 428 429static void get_atomic_caps(struct mlx5_ib_dev *dev, 430 struct ib_device_attr *props) 431{ 432 u8 tmp; 433 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 434 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 435 u8 atomic_req_8B_endianness_mode = 436 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode); 437 438 /* Check if HW supports 8 bytes standard atomic operations and capable 439 * of host endianness respond 440 */ 441 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 442 if (((atomic_operations & tmp) == tmp) && 443 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 444 (atomic_req_8B_endianness_mode)) { 445 props->atomic_cap = IB_ATOMIC_HCA; 446 } else { 447 props->atomic_cap = IB_ATOMIC_NONE; 448 } 449} 450 451static int mlx5_query_system_image_guid(struct ib_device *ibdev, 452 __be64 *sys_image_guid) 453{ 454 struct mlx5_ib_dev *dev = to_mdev(ibdev); 455 struct mlx5_core_dev *mdev = dev->mdev; 456 u64 tmp; 457 int err; 458 459 switch (mlx5_get_vport_access_method(ibdev)) { 460 case MLX5_VPORT_ACCESS_METHOD_MAD: 461 return mlx5_query_mad_ifc_system_image_guid(ibdev, 462 sys_image_guid); 463 464 case MLX5_VPORT_ACCESS_METHOD_HCA: 465 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 466 break; 467 468 case MLX5_VPORT_ACCESS_METHOD_NIC: 469 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 470 break; 471 472 default: 473 return -EINVAL; 474 } 475 476 if (!err) 477 *sys_image_guid = cpu_to_be64(tmp); 478 479 return err; 480 481} 482 483static int mlx5_query_max_pkeys(struct ib_device *ibdev, 484 u16 *max_pkeys) 485{ 486 struct mlx5_ib_dev *dev = to_mdev(ibdev); 487 struct mlx5_core_dev *mdev = dev->mdev; 488 489 switch (mlx5_get_vport_access_method(ibdev)) { 490 case MLX5_VPORT_ACCESS_METHOD_MAD: 491 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 492 493 case MLX5_VPORT_ACCESS_METHOD_HCA: 494 case MLX5_VPORT_ACCESS_METHOD_NIC: 495 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 496 pkey_table_size)); 497 return 0; 498 499 default: 500 return -EINVAL; 501 } 502} 503 504static int mlx5_query_vendor_id(struct ib_device *ibdev, 505 u32 *vendor_id) 506{ 507 struct mlx5_ib_dev *dev = to_mdev(ibdev); 508 509 switch (mlx5_get_vport_access_method(ibdev)) { 510 case MLX5_VPORT_ACCESS_METHOD_MAD: 511 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 512 513 case MLX5_VPORT_ACCESS_METHOD_HCA: 514 case MLX5_VPORT_ACCESS_METHOD_NIC: 515 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 516 517 default: 518 return -EINVAL; 519 } 520} 521 522static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 523 __be64 *node_guid) 524{ 525 u64 tmp; 526 int err; 527 528 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 529 case MLX5_VPORT_ACCESS_METHOD_MAD: 530 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 531 532 case MLX5_VPORT_ACCESS_METHOD_HCA: 533 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 534 break; 535 536 case MLX5_VPORT_ACCESS_METHOD_NIC: 537 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 538 break; 539 540 default: 541 return -EINVAL; 542 } 543 544 if (!err) 545 *node_guid = cpu_to_be64(tmp); 546 547 return err; 548} 549 550struct mlx5_reg_node_desc { 551 u8 desc[IB_DEVICE_NODE_DESC_MAX]; 552}; 553 554static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 555{ 556 struct mlx5_reg_node_desc in; 557 558 if (mlx5_use_mad_ifc(dev)) 559 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 560 561 memset(&in, 0, sizeof(in)); 562 563 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 564 sizeof(struct mlx5_reg_node_desc), 565 MLX5_REG_NODE_DESC, 0, 0); 566} 567 568static int mlx5_ib_query_device(struct ib_device *ibdev, 569 struct ib_device_attr *props, 570 struct ib_udata *uhw) 571{ 572 struct mlx5_ib_dev *dev = to_mdev(ibdev); 573 struct mlx5_core_dev *mdev = dev->mdev; 574 int err = -ENOMEM; 575 int max_rq_sg; 576 int max_sq_sg; 577 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 578 struct mlx5_ib_query_device_resp resp = {}; 579 size_t resp_len; 580 u64 max_tso; 581 582 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 583 if (uhw->outlen && uhw->outlen < resp_len) 584 return -EINVAL; 585 else 586 resp.response_length = resp_len; 587 588 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) 589 return -EINVAL; 590 591 memset(props, 0, sizeof(*props)); 592 err = mlx5_query_system_image_guid(ibdev, 593 &props->sys_image_guid); 594 if (err) 595 return err; 596 597 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys); 598 if (err) 599 return err; 600 601 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 602 if (err) 603 return err; 604 605 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 606 ((u32)fw_rev_min(dev->mdev) << 16) | 607 fw_rev_sub(dev->mdev); 608 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 609 IB_DEVICE_PORT_ACTIVE_EVENT | 610 IB_DEVICE_SYS_IMAGE_GUID | 611 IB_DEVICE_RC_RNR_NAK_GEN; 612 613 if (MLX5_CAP_GEN(mdev, pkv)) 614 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 615 if (MLX5_CAP_GEN(mdev, qkv)) 616 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 617 if (MLX5_CAP_GEN(mdev, apm)) 618 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 619 if (MLX5_CAP_GEN(mdev, xrc)) 620 props->device_cap_flags |= IB_DEVICE_XRC; 621 if (MLX5_CAP_GEN(mdev, imaicl)) { 622 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 623 IB_DEVICE_MEM_WINDOW_TYPE_2B; 624 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 625 /* We support 'Gappy' memory registration too */ 626 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG; 627 } 628 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 629 if (MLX5_CAP_GEN(mdev, sho)) { 630 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER; 631 /* At this stage no support for signature handover */ 632 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 633 IB_PROT_T10DIF_TYPE_2 | 634 IB_PROT_T10DIF_TYPE_3; 635 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 636 IB_GUARD_T10DIF_CSUM; 637 } 638 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 639 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 640 641 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) { 642 if (MLX5_CAP_ETH(mdev, csum_cap)) 643 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 644 645 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) { 646 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 647 if (max_tso) { 648 resp.tso_caps.max_tso = 1 << max_tso; 649 resp.tso_caps.supported_qpts |= 650 1 << IB_QPT_RAW_PACKET; 651 resp.response_length += sizeof(resp.tso_caps); 652 } 653 } 654 655 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) { 656 resp.rss_caps.rx_hash_function = 657 MLX5_RX_HASH_FUNC_TOEPLITZ; 658 resp.rss_caps.rx_hash_fields_mask = 659 MLX5_RX_HASH_SRC_IPV4 | 660 MLX5_RX_HASH_DST_IPV4 | 661 MLX5_RX_HASH_SRC_IPV6 | 662 MLX5_RX_HASH_DST_IPV6 | 663 MLX5_RX_HASH_SRC_PORT_TCP | 664 MLX5_RX_HASH_DST_PORT_TCP | 665 MLX5_RX_HASH_SRC_PORT_UDP | 666 MLX5_RX_HASH_DST_PORT_UDP; 667 resp.response_length += sizeof(resp.rss_caps); 668 } 669 } else { 670 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) 671 resp.response_length += sizeof(resp.tso_caps); 672 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) 673 resp.response_length += sizeof(resp.rss_caps); 674 } 675 676 if (MLX5_CAP_GEN(mdev, ipoib_ipoib_offloads)) { 677 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 678 props->device_cap_flags |= IB_DEVICE_UD_TSO; 679 } 680 681 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 682 MLX5_CAP_ETH(dev->mdev, scatter_fcs)) 683 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 684 685 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 686 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 687 688 props->vendor_part_id = mdev->pdev->device; 689 props->hw_ver = mdev->pdev->revision; 690 691 props->max_mr_size = ~0ull; 692 props->page_size_cap = ~(min_page_size - 1); 693 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 694 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 695 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 696 sizeof(struct mlx5_wqe_data_seg); 697 max_sq_sg = (MLX5_CAP_GEN(mdev, max_wqe_sz_sq) - 698 sizeof(struct mlx5_wqe_ctrl_seg)) / 699 sizeof(struct mlx5_wqe_data_seg); 700 props->max_sge = min(max_rq_sg, max_sq_sg); 701 props->max_sge_rd = MLX5_MAX_SGE_RD; 702 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 703 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 704 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 705 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 706 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 707 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 708 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 709 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 710 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 711 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 712 props->max_srq_sge = max_rq_sg - 1; 713 props->max_fast_reg_page_list_len = 714 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 715 get_atomic_caps(dev, props); 716 props->masked_atomic_cap = IB_ATOMIC_NONE; 717 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 718 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 719 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 720 props->max_mcast_grp; 721 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */ 722 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 723 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 724 725#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 726 if (MLX5_CAP_GEN(mdev, pg)) 727 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING; 728 props->odp_caps = dev->odp_caps; 729#endif 730 731 if (MLX5_CAP_GEN(mdev, cd)) 732 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL; 733 734 if (!mlx5_core_is_pf(mdev)) 735 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION; 736 737 if (mlx5_ib_port_link_layer(ibdev, 1) == 738 IB_LINK_LAYER_ETHERNET) { 739 props->rss_caps.max_rwq_indirection_tables = 740 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); 741 props->rss_caps.max_rwq_indirection_table_size = 742 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); 743 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 744 props->max_wq_type_rq = 745 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 746 } 747 748 if (uhw->outlen) { 749 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 750 751 if (err) 752 return err; 753 } 754 755 return 0; 756} 757 758enum mlx5_ib_width { 759 MLX5_IB_WIDTH_1X = 1 << 0, 760 MLX5_IB_WIDTH_2X = 1 << 1, 761 MLX5_IB_WIDTH_4X = 1 << 2, 762 MLX5_IB_WIDTH_8X = 1 << 3, 763 MLX5_IB_WIDTH_12X = 1 << 4 764}; 765 766static int translate_active_width(struct ib_device *ibdev, u8 active_width, 767 u8 *ib_width) 768{ 769 struct mlx5_ib_dev *dev = to_mdev(ibdev); 770 int err = 0; 771 772 if (active_width & MLX5_IB_WIDTH_1X) { 773 *ib_width = IB_WIDTH_1X; 774 } else if (active_width & MLX5_IB_WIDTH_2X) { 775 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n", 776 (int)active_width); 777 err = -EINVAL; 778 } else if (active_width & MLX5_IB_WIDTH_4X) { 779 *ib_width = IB_WIDTH_4X; 780 } else if (active_width & MLX5_IB_WIDTH_8X) { 781 *ib_width = IB_WIDTH_8X; 782 } else if (active_width & MLX5_IB_WIDTH_12X) { 783 *ib_width = IB_WIDTH_12X; 784 } else { 785 mlx5_ib_dbg(dev, "Invalid active_width %d\n", 786 (int)active_width); 787 err = -EINVAL; 788 } 789 790 return err; 791} 792 793enum ib_max_vl_num { 794 __IB_MAX_VL_0 = 1, 795 __IB_MAX_VL_0_1 = 2, 796 __IB_MAX_VL_0_3 = 3, 797 __IB_MAX_VL_0_7 = 4, 798 __IB_MAX_VL_0_14 = 5, 799}; 800 801enum mlx5_vl_hw_cap { 802 MLX5_VL_HW_0 = 1, 803 MLX5_VL_HW_0_1 = 2, 804 MLX5_VL_HW_0_2 = 3, 805 MLX5_VL_HW_0_3 = 4, 806 MLX5_VL_HW_0_4 = 5, 807 MLX5_VL_HW_0_5 = 6, 808 MLX5_VL_HW_0_6 = 7, 809 MLX5_VL_HW_0_7 = 8, 810 MLX5_VL_HW_0_14 = 15 811}; 812 813static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 814 u8 *max_vl_num) 815{ 816 switch (vl_hw_cap) { 817 case MLX5_VL_HW_0: 818 *max_vl_num = __IB_MAX_VL_0; 819 break; 820 case MLX5_VL_HW_0_1: 821 *max_vl_num = __IB_MAX_VL_0_1; 822 break; 823 case MLX5_VL_HW_0_3: 824 *max_vl_num = __IB_MAX_VL_0_3; 825 break; 826 case MLX5_VL_HW_0_7: 827 *max_vl_num = __IB_MAX_VL_0_7; 828 break; 829 case MLX5_VL_HW_0_14: 830 *max_vl_num = __IB_MAX_VL_0_14; 831 break; 832 833 default: 834 return -EINVAL; 835 } 836 837 return 0; 838} 839 840static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port, 841 struct ib_port_attr *props) 842{ 843 struct mlx5_ib_dev *dev = to_mdev(ibdev); 844 struct mlx5_core_dev *mdev = dev->mdev; 845 u32 *rep; 846 int replen = MLX5_ST_SZ_BYTES(query_hca_vport_context_out); 847 struct mlx5_ptys_reg *ptys; 848 struct mlx5_pmtu_reg *pmtu; 849 struct mlx5_pvlc_reg pvlc; 850 void *ctx; 851 int err; 852 853 rep = mlx5_vzalloc(replen); 854 ptys = kzalloc(sizeof(*ptys), GFP_KERNEL); 855 pmtu = kzalloc(sizeof(*pmtu), GFP_KERNEL); 856 if (!rep || !ptys || !pmtu) { 857 err = -ENOMEM; 858 goto out; 859 } 860 861 memset(props, 0, sizeof(*props)); 862 863 err = mlx5_query_hca_vport_context(mdev, port, 0, rep, replen); 864 if (err) 865 goto out; 866 867 ctx = MLX5_ADDR_OF(query_hca_vport_context_out, rep, hca_vport_context); 868 869 props->lid = MLX5_GET(hca_vport_context, ctx, lid); 870 props->lmc = MLX5_GET(hca_vport_context, ctx, lmc); 871 props->sm_lid = MLX5_GET(hca_vport_context, ctx, sm_lid); 872 props->sm_sl = MLX5_GET(hca_vport_context, ctx, sm_sl); 873 props->state = MLX5_GET(hca_vport_context, ctx, vport_state); 874 props->phys_state = MLX5_GET(hca_vport_context, ctx, 875 port_physical_state); 876 props->port_cap_flags = MLX5_GET(hca_vport_context, ctx, cap_mask1); 877 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 878 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 879 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 880 props->bad_pkey_cntr = MLX5_GET(hca_vport_context, ctx, 881 pkey_violation_counter); 882 props->qkey_viol_cntr = MLX5_GET(hca_vport_context, ctx, 883 qkey_violation_counter); 884 props->subnet_timeout = MLX5_GET(hca_vport_context, ctx, 885 subnet_timeout); 886 props->init_type_reply = MLX5_GET(hca_vport_context, ctx, 887 init_type_reply); 888 props->grh_required = MLX5_GET(hca_vport_context, ctx, grh_required); 889 890 ptys->proto_mask |= MLX5_PTYS_IB; 891 ptys->local_port = port; 892 err = mlx5_core_access_ptys(mdev, ptys, 0); 893 if (err) 894 goto out; 895 896 err = translate_active_width(ibdev, ptys->ib_link_width_oper, 897 &props->active_width); 898 if (err) 899 goto out; 900 901 props->active_speed = (u8)ptys->ib_proto_oper; 902 903 pmtu->local_port = port; 904 err = mlx5_core_access_pmtu(mdev, pmtu, 0); 905 if (err) 906 goto out; 907 908 props->max_mtu = pmtu->max_mtu; 909 props->active_mtu = pmtu->oper_mtu; 910 911 memset(&pvlc, 0, sizeof(pvlc)); 912 pvlc.local_port = port; 913 err = mlx5_core_access_pvlc(mdev, &pvlc, 0); 914 if (err) 915 goto out; 916 917 err = translate_max_vl_num(ibdev, pvlc.vl_hw_cap, 918 &props->max_vl_num); 919out: 920 kvfree(rep); 921 kfree(ptys); 922 kfree(pmtu); 923 return err; 924} 925 926int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 927 struct ib_port_attr *props) 928{ 929 switch (mlx5_get_vport_access_method(ibdev)) { 930 case MLX5_VPORT_ACCESS_METHOD_MAD: 931 return mlx5_query_mad_ifc_port(ibdev, port, props); 932 933 case MLX5_VPORT_ACCESS_METHOD_HCA: 934 return mlx5_query_hca_port(ibdev, port, props); 935 936 case MLX5_VPORT_ACCESS_METHOD_NIC: 937 return mlx5_query_port_roce(ibdev, port, props); 938 939 default: 940 return -EINVAL; 941 } 942} 943 944static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 945 union ib_gid *gid) 946{ 947 struct mlx5_ib_dev *dev = to_mdev(ibdev); 948 struct mlx5_core_dev *mdev = dev->mdev; 949 950 switch (mlx5_get_vport_access_method(ibdev)) { 951 case MLX5_VPORT_ACCESS_METHOD_MAD: 952 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 953 954 case MLX5_VPORT_ACCESS_METHOD_HCA: 955 return mlx5_query_hca_vport_gid(mdev, port, 0, index, gid); 956 957 default: 958 return -EINVAL; 959 } 960 961} 962 963static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 964 u16 *pkey) 965{ 966 struct mlx5_ib_dev *dev = to_mdev(ibdev); 967 struct mlx5_core_dev *mdev = dev->mdev; 968 969 switch (mlx5_get_vport_access_method(ibdev)) { 970 case MLX5_VPORT_ACCESS_METHOD_MAD: 971 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 972 973 case MLX5_VPORT_ACCESS_METHOD_HCA: 974 case MLX5_VPORT_ACCESS_METHOD_NIC: 975 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index, 976 pkey); 977 default: 978 return -EINVAL; 979 } 980} 981 982static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 983 struct ib_device_modify *props) 984{ 985 struct mlx5_ib_dev *dev = to_mdev(ibdev); 986 struct mlx5_reg_node_desc in; 987 struct mlx5_reg_node_desc out; 988 int err; 989 990 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 991 return -EOPNOTSUPP; 992 993 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 994 return 0; 995 996 /* 997 * If possible, pass node desc to FW, so it can generate 998 * a 144 trap. If cmd fails, just ignore. 999 */ 1000 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1001 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 1002 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 1003 if (err) 1004 return err; 1005 1006 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1007 1008 return err; 1009} 1010 1011static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, 1012 struct ib_port_modify *props) 1013{ 1014 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1015 struct ib_port_attr attr; 1016 u32 tmp; 1017 int err; 1018 1019 mutex_lock(&dev->cap_mask_mutex); 1020 1021 err = mlx5_ib_query_port(ibdev, port, &attr); 1022 if (err) 1023 goto out; 1024 1025 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 1026 ~props->clr_port_cap_mask; 1027 1028 err = mlx5_set_port_caps(dev->mdev, port, tmp); 1029 1030out: 1031 mutex_unlock(&dev->cap_mask_mutex); 1032 return err; 1033} 1034 1035static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev, 1036 struct ib_udata *udata) 1037{ 1038 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1039 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 1040 struct mlx5_ib_alloc_ucontext_resp resp = {}; 1041 struct mlx5_ib_ucontext *context; 1042 struct mlx5_uuar_info *uuari; 1043 struct mlx5_uar *uars; 1044 int gross_uuars; 1045 int num_uars; 1046 int ver; 1047 int uuarn; 1048 int err; 1049 int i; 1050 size_t reqlen; 1051 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 1052 max_cqe_version); 1053 1054 if (!dev->ib_active) 1055 return ERR_PTR(-EAGAIN); 1056 1057 if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr)) 1058 return ERR_PTR(-EINVAL); 1059 1060 reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr); 1061 if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 1062 ver = 0; 1063 else if (reqlen >= min_req_v2) 1064 ver = 2; 1065 else 1066 return ERR_PTR(-EINVAL); 1067 1068 err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req))); 1069 if (err) 1070 return ERR_PTR(err); 1071 1072 if (req.flags) 1073 return ERR_PTR(-EINVAL); 1074 1075 if (req.total_num_uuars > MLX5_MAX_UUARS) 1076 return ERR_PTR(-ENOMEM); 1077 1078 if (req.total_num_uuars == 0) 1079 return ERR_PTR(-EINVAL); 1080 1081 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 1082 return ERR_PTR(-EOPNOTSUPP); 1083 1084 if (reqlen > sizeof(req) && 1085 !ib_is_udata_cleared(udata, sizeof(req), 1086 reqlen - sizeof(req))) 1087 return ERR_PTR(-EOPNOTSUPP); 1088 1089 req.total_num_uuars = ALIGN(req.total_num_uuars, 1090 MLX5_NON_FP_BF_REGS_PER_PAGE); 1091 if (req.num_low_latency_uuars > req.total_num_uuars - 1) 1092 return ERR_PTR(-EINVAL); 1093 1094 num_uars = req.total_num_uuars / MLX5_NON_FP_BF_REGS_PER_PAGE; 1095 gross_uuars = num_uars * MLX5_BF_REGS_PER_PAGE; 1096 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 1097 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf)) 1098 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size); 1099 resp.cache_line_size = cache_line_size(); 1100 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 1101 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 1102 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1103 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1104 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 1105 resp.cqe_version = min_t(__u8, 1106 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 1107 req.max_cqe_version); 1108 resp.response_length = min(offsetof(typeof(resp), response_length) + 1109 sizeof(resp.response_length), udata->outlen); 1110 1111 context = kzalloc(sizeof(*context), GFP_KERNEL); 1112 if (!context) 1113 return ERR_PTR(-ENOMEM); 1114 1115 uuari = &context->uuari; 1116 mutex_init(&uuari->lock); 1117 uars = kcalloc(num_uars, sizeof(*uars), GFP_KERNEL); 1118 if (!uars) { 1119 err = -ENOMEM; 1120 goto out_ctx; 1121 } 1122 1123 uuari->bitmap = kcalloc(BITS_TO_LONGS(gross_uuars), 1124 sizeof(*uuari->bitmap), 1125 GFP_KERNEL); 1126 if (!uuari->bitmap) { 1127 err = -ENOMEM; 1128 goto out_uar_ctx; 1129 } 1130 /* 1131 * clear all fast path uuars 1132 */ 1133 for (i = 0; i < gross_uuars; i++) { 1134 uuarn = i & 3; 1135 if (uuarn == 2 || uuarn == 3) 1136 set_bit(i, uuari->bitmap); 1137 } 1138 1139 uuari->count = kcalloc(gross_uuars, sizeof(*uuari->count), GFP_KERNEL); 1140 if (!uuari->count) { 1141 err = -ENOMEM; 1142 goto out_bitmap; 1143 } 1144 1145 for (i = 0; i < num_uars; i++) { 1146 err = mlx5_cmd_alloc_uar(dev->mdev, &uars[i].index); 1147 if (err) 1148 goto out_count; 1149 } 1150 1151#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1152 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range; 1153#endif 1154 1155 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) { 1156 err = mlx5_alloc_transport_domain(dev->mdev, 1157 &context->tdn); 1158 if (err) 1159 goto out_uars; 1160 } 1161 1162 INIT_LIST_HEAD(&context->vma_private_list); 1163 INIT_LIST_HEAD(&context->db_page_list); 1164 mutex_init(&context->db_page_mutex); 1165 1166 resp.tot_uuars = req.total_num_uuars; 1167 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports); 1168 1169 if (field_avail(typeof(resp), cqe_version, udata->outlen)) 1170 resp.response_length += sizeof(resp.cqe_version); 1171 1172 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) { 1173 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | 1174 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; 1175 resp.response_length += sizeof(resp.cmds_supp_uhw); 1176 } 1177 1178 /* 1179 * We don't want to expose information from the PCI bar that is located 1180 * after 4096 bytes, so if the arch only supports larger pages, let's 1181 * pretend we don't support reading the HCA's core clock. This is also 1182 * forced by mmap function. 1183 */ 1184 if (PAGE_SIZE <= 4096 && 1185 field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) { 1186 resp.comp_mask |= 1187 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 1188 resp.hca_core_clock_offset = 1189 offsetof(struct mlx5_init_seg, internal_timer_h) % 1190 PAGE_SIZE; 1191 resp.response_length += sizeof(resp.hca_core_clock_offset) + 1192 sizeof(resp.reserved2); 1193 } 1194 1195 err = ib_copy_to_udata(udata, &resp, resp.response_length); 1196 if (err) 1197 goto out_td; 1198 1199 uuari->ver = ver; 1200 uuari->num_low_latency_uuars = req.num_low_latency_uuars; 1201 uuari->uars = uars; 1202 uuari->num_uars = num_uars; 1203 context->cqe_version = resp.cqe_version; 1204 1205 return &context->ibucontext; 1206 1207out_td: 1208 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1209 mlx5_dealloc_transport_domain(dev->mdev, context->tdn); 1210 1211out_uars: 1212 for (i--; i >= 0; i--) 1213 mlx5_cmd_free_uar(dev->mdev, uars[i].index); 1214out_count: 1215 kfree(uuari->count); 1216 1217out_bitmap: 1218 kfree(uuari->bitmap); 1219 1220out_uar_ctx: 1221 kfree(uars); 1222 1223out_ctx: 1224 kfree(context); 1225 return ERR_PTR(err); 1226} 1227 1228static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1229{ 1230 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1231 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1232 struct mlx5_uuar_info *uuari = &context->uuari; 1233 int i; 1234 1235 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1236 mlx5_dealloc_transport_domain(dev->mdev, context->tdn); 1237 1238 for (i = 0; i < uuari->num_uars; i++) { 1239 if (mlx5_cmd_free_uar(dev->mdev, uuari->uars[i].index)) 1240 mlx5_ib_warn(dev, "failed to free UAR 0x%x\n", uuari->uars[i].index); 1241 } 1242 1243 kfree(uuari->count); 1244 kfree(uuari->bitmap); 1245 kfree(uuari->uars); 1246 kfree(context); 1247 1248 return 0; 1249} 1250 1251static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, int index) 1252{ 1253 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + index; 1254} 1255 1256static int get_command(unsigned long offset) 1257{ 1258 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 1259} 1260 1261static int get_arg(unsigned long offset) 1262{ 1263 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 1264} 1265 1266static int get_index(unsigned long offset) 1267{ 1268 return get_arg(offset); 1269} 1270 1271static void mlx5_ib_vma_open(struct vm_area_struct *area) 1272{ 1273 /* vma_open is called when a new VMA is created on top of our VMA. This 1274 * is done through either mremap flow or split_vma (usually due to 1275 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA, 1276 * as this VMA is strongly hardware related. Therefore we set the 1277 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from 1278 * calling us again and trying to do incorrect actions. We assume that 1279 * the original VMA size is exactly a single page, and therefore all 1280 * "splitting" operation will not happen to it. 1281 */ 1282 area->vm_ops = NULL; 1283} 1284 1285static void mlx5_ib_vma_close(struct vm_area_struct *area) 1286{ 1287 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data; 1288 1289 /* It's guaranteed that all VMAs opened on a FD are closed before the 1290 * file itself is closed, therefore no sync is needed with the regular 1291 * closing flow. (e.g. mlx5 ib_dealloc_ucontext) 1292 * However need a sync with accessing the vma as part of 1293 * mlx5_ib_disassociate_ucontext. 1294 * The close operation is usually called under mm->mmap_sem except when 1295 * process is exiting. 1296 * The exiting case is handled explicitly as part of 1297 * mlx5_ib_disassociate_ucontext. 1298 */ 1299 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data; 1300 1301 /* setting the vma context pointer to null in the mlx5_ib driver's 1302 * private data, to protect a race condition in 1303 * mlx5_ib_disassociate_ucontext(). 1304 */ 1305 mlx5_ib_vma_priv_data->vma = NULL; 1306 list_del(&mlx5_ib_vma_priv_data->list); 1307 kfree(mlx5_ib_vma_priv_data); 1308} 1309 1310static const struct vm_operations_struct mlx5_ib_vm_ops = { 1311 .open = mlx5_ib_vma_open, 1312 .close = mlx5_ib_vma_close 1313}; 1314 1315static int mlx5_ib_set_vma_data(struct vm_area_struct *vma, 1316 struct mlx5_ib_ucontext *ctx) 1317{ 1318 struct mlx5_ib_vma_private_data *vma_prv; 1319 struct list_head *vma_head = &ctx->vma_private_list; 1320 1321 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL); 1322 if (!vma_prv) 1323 return -ENOMEM; 1324 1325 vma_prv->vma = vma; 1326 vma->vm_private_data = vma_prv; 1327 vma->vm_ops = &mlx5_ib_vm_ops; 1328 1329 list_add(&vma_prv->list, vma_head); 1330 1331 return 0; 1332} 1333 1334static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 1335{ 1336 int ret; 1337 struct vm_area_struct *vma; 1338 struct mlx5_ib_vma_private_data *vma_private, *n; 1339 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1340 struct task_struct *owning_process = NULL; 1341 struct mm_struct *owning_mm = NULL; 1342 1343 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID); 1344 if (!owning_process) 1345 return; 1346 1347 owning_mm = get_task_mm(owning_process); 1348 if (!owning_mm) { 1349 pr_info("no mm, disassociate ucontext is pending task termination\n"); 1350 while (1) { 1351 put_task_struct(owning_process); 1352 usleep_range(1000, 2000); 1353 owning_process = get_pid_task(ibcontext->tgid, 1354 PIDTYPE_PID); 1355 if (!owning_process || owning_process->task_thread-> 1356 td_proc->p_state == PRS_ZOMBIE) { 1357 pr_info("disassociate ucontext done, task was terminated\n"); 1358 /* in case task was dead need to release the 1359 * task struct. 1360 */ 1361 if (owning_process) 1362 put_task_struct(owning_process); 1363 return; 1364 } 1365 } 1366 } 1367 1368 /* need to protect from a race on closing the vma as part of 1369 * mlx5_ib_vma_close. 1370 */ 1371 down_write(&owning_mm->mmap_sem); 1372 list_for_each_entry_safe(vma_private, n, &context->vma_private_list, 1373 list) { 1374 vma = vma_private->vma; 1375 ret = zap_vma_ptes(vma, vma->vm_start, 1376 PAGE_SIZE); 1377 if (ret == -ENOTSUP) { 1378 if (bootverbose) 1379 WARN_ONCE( 1380 "%s: zap_vma_ptes not implemented for unmanaged mappings", __func__); 1381 } else { 1382 WARN(ret, "%s: zap_vma_ptes failed, error %d", 1383 __func__, -ret); 1384 } 1385 /* context going to be destroyed, should 1386 * not access ops any more. 1387 */ 1388 /* XXXKIB vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE); */ 1389 vma->vm_ops = NULL; 1390 list_del(&vma_private->list); 1391 kfree(vma_private); 1392 } 1393 up_write(&owning_mm->mmap_sem); 1394 mmput(owning_mm); 1395 put_task_struct(owning_process); 1396} 1397 1398static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 1399{ 1400 switch (cmd) { 1401 case MLX5_IB_MMAP_WC_PAGE: 1402 return "WC"; 1403 case MLX5_IB_MMAP_REGULAR_PAGE: 1404 return "best effort WC"; 1405 case MLX5_IB_MMAP_NC_PAGE: 1406 return "NC"; 1407 default: 1408 return NULL; 1409 } 1410} 1411 1412static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 1413 struct vm_area_struct *vma, 1414 struct mlx5_ib_ucontext *context) 1415{ 1416 struct mlx5_uuar_info *uuari = &context->uuari; 1417 int err; 1418 unsigned long idx; 1419 phys_addr_t pfn, pa; 1420 pgprot_t prot; 1421 1422 switch (cmd) { 1423 case MLX5_IB_MMAP_WC_PAGE: 1424/* Some architectures don't support WC memory */ 1425#if defined(CONFIG_X86) 1426 if (!pat_enabled()) 1427 return -EPERM; 1428#elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU))) 1429 return -EPERM; 1430#endif 1431 /* fall through */ 1432 case MLX5_IB_MMAP_REGULAR_PAGE: 1433 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 1434 prot = pgprot_writecombine(vma->vm_page_prot); 1435 break; 1436 case MLX5_IB_MMAP_NC_PAGE: 1437 prot = pgprot_noncached(vma->vm_page_prot); 1438 break; 1439 default: 1440 return -EINVAL; 1441 } 1442 1443 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1444 return -EINVAL; 1445 1446 idx = get_index(vma->vm_pgoff); 1447 if (idx >= uuari->num_uars) 1448 return -EINVAL; 1449 1450 pfn = uar_index2pfn(dev, uuari->uars[idx].index); 1451 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 1452 1453 vma->vm_page_prot = prot; 1454 err = io_remap_pfn_range(vma, vma->vm_start, pfn, 1455 PAGE_SIZE, vma->vm_page_prot); 1456 if (err) { 1457 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%llx, pfn=%pa, mmap_cmd=%s\n", 1458 err, (unsigned long long)vma->vm_start, &pfn, mmap_cmd2str(cmd)); 1459 return -EAGAIN; 1460 } 1461 1462 pa = pfn << PAGE_SHIFT; 1463 mlx5_ib_dbg(dev, "mapped %s at 0x%llx, PA %pa\n", mmap_cmd2str(cmd), 1464 (unsigned long long)vma->vm_start, &pa); 1465 1466 return mlx5_ib_set_vma_data(vma, context); 1467} 1468 1469static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 1470{ 1471 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1472 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1473 unsigned long command; 1474 phys_addr_t pfn; 1475 1476 command = get_command(vma->vm_pgoff); 1477 switch (command) { 1478 case MLX5_IB_MMAP_WC_PAGE: 1479 case MLX5_IB_MMAP_NC_PAGE: 1480 case MLX5_IB_MMAP_REGULAR_PAGE: 1481 return uar_mmap(dev, command, vma, context); 1482 1483 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 1484 return -ENOSYS; 1485 1486 case MLX5_IB_MMAP_CORE_CLOCK: 1487 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1488 return -EINVAL; 1489 1490 if (vma->vm_flags & VM_WRITE) 1491 return -EPERM; 1492 1493 /* Don't expose to user-space information it shouldn't have */ 1494 if (PAGE_SIZE > 4096) 1495 return -EOPNOTSUPP; 1496 1497 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 1498 pfn = (dev->mdev->iseg_base + 1499 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 1500 PAGE_SHIFT; 1501 if (io_remap_pfn_range(vma, vma->vm_start, pfn, 1502 PAGE_SIZE, vma->vm_page_prot)) 1503 return -EAGAIN; 1504 1505 mlx5_ib_dbg(dev, "mapped internal timer at 0x%llx, PA 0x%llx\n", 1506 (unsigned long long)vma->vm_start, 1507 (unsigned long long)pfn << PAGE_SHIFT); 1508 break; 1509 1510 default: 1511 return -EINVAL; 1512 } 1513 1514 return 0; 1515} 1516 1517static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev, 1518 struct ib_ucontext *context, 1519 struct ib_udata *udata) 1520{ 1521 struct mlx5_ib_alloc_pd_resp resp; 1522 struct mlx5_ib_pd *pd; 1523 int err; 1524 1525 pd = kmalloc(sizeof(*pd), GFP_KERNEL); 1526 if (!pd) 1527 return ERR_PTR(-ENOMEM); 1528 1529 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn); 1530 if (err) { 1531 kfree(pd); 1532 return ERR_PTR(err); 1533 } 1534 1535 if (context) { 1536 resp.pdn = pd->pdn; 1537 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 1538 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn); 1539 kfree(pd); 1540 return ERR_PTR(-EFAULT); 1541 } 1542 } 1543 1544 return &pd->ibpd; 1545} 1546 1547static int mlx5_ib_dealloc_pd(struct ib_pd *pd) 1548{ 1549 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 1550 struct mlx5_ib_pd *mpd = to_mpd(pd); 1551 1552 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn); 1553 kfree(mpd); 1554 1555 return 0; 1556} 1557 1558enum { 1559 MATCH_CRITERIA_ENABLE_OUTER_BIT, 1560 MATCH_CRITERIA_ENABLE_MISC_BIT, 1561 MATCH_CRITERIA_ENABLE_INNER_BIT 1562}; 1563 1564#define HEADER_IS_ZERO(match_criteria, headers) \ 1565 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \ 1566 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \ 1567 1568static u8 get_match_criteria_enable(u32 *match_criteria) 1569{ 1570 u8 match_criteria_enable; 1571 1572 match_criteria_enable = 1573 (!HEADER_IS_ZERO(match_criteria, outer_headers)) << 1574 MATCH_CRITERIA_ENABLE_OUTER_BIT; 1575 match_criteria_enable |= 1576 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) << 1577 MATCH_CRITERIA_ENABLE_MISC_BIT; 1578 match_criteria_enable |= 1579 (!HEADER_IS_ZERO(match_criteria, inner_headers)) << 1580 MATCH_CRITERIA_ENABLE_INNER_BIT; 1581 1582 return match_criteria_enable; 1583} 1584 1585static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val) 1586{ 1587 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask); 1588 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val); 1589} 1590 1591static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val) 1592{ 1593 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask); 1594 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val); 1595 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2); 1596 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2); 1597} 1598 1599#define LAST_ETH_FIELD vlan_tag 1600#define LAST_IB_FIELD sl 1601#define LAST_IPV4_FIELD tos 1602#define LAST_IPV6_FIELD traffic_class 1603#define LAST_TCP_UDP_FIELD src_port 1604 1605/* Field is the last supported field */ 1606#define FIELDS_NOT_SUPPORTED(filter, field)\ 1607 memchr_inv((void *)&filter.field +\ 1608 sizeof(filter.field), 0,\ 1609 sizeof(filter) -\ 1610 offsetof(typeof(filter), field) -\ 1611 sizeof(filter.field)) 1612 1613static int parse_flow_attr(u32 *match_c, u32 *match_v, 1614 const union ib_flow_spec *ib_spec) 1615{ 1616 void *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 1617 outer_headers); 1618 void *outer_headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 1619 outer_headers); 1620 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c, 1621 misc_parameters); 1622 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v, 1623 misc_parameters); 1624 1625 switch (ib_spec->type) { 1626 case IB_FLOW_SPEC_ETH: 1627 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD)) 1628 return -ENOTSUPP; 1629 1630 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1631 dmac_47_16), 1632 ib_spec->eth.mask.dst_mac); 1633 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1634 dmac_47_16), 1635 ib_spec->eth.val.dst_mac); 1636 1637 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1638 smac_47_16), 1639 ib_spec->eth.mask.src_mac); 1640 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1641 smac_47_16), 1642 ib_spec->eth.val.src_mac); 1643 1644 if (ib_spec->eth.mask.vlan_tag) { 1645 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1646 cvlan_tag, 1); 1647 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1648 cvlan_tag, 1); 1649 1650 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1651 first_vid, ntohs(ib_spec->eth.mask.vlan_tag)); 1652 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1653 first_vid, ntohs(ib_spec->eth.val.vlan_tag)); 1654 1655 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1656 first_cfi, 1657 ntohs(ib_spec->eth.mask.vlan_tag) >> 12); 1658 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1659 first_cfi, 1660 ntohs(ib_spec->eth.val.vlan_tag) >> 12); 1661 1662 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1663 first_prio, 1664 ntohs(ib_spec->eth.mask.vlan_tag) >> 13); 1665 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1666 first_prio, 1667 ntohs(ib_spec->eth.val.vlan_tag) >> 13); 1668 } 1669 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1670 ethertype, ntohs(ib_spec->eth.mask.ether_type)); 1671 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1672 ethertype, ntohs(ib_spec->eth.val.ether_type)); 1673 break; 1674 case IB_FLOW_SPEC_IPV4: 1675 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD)) 1676 return -ENOTSUPP; 1677 1678 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1679 ethertype, 0xffff); 1680 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1681 ethertype, ETH_P_IP); 1682 1683 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1684 src_ipv4_src_ipv6.ipv4_layout.ipv4), 1685 &ib_spec->ipv4.mask.src_ip, 1686 sizeof(ib_spec->ipv4.mask.src_ip)); 1687 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1688 src_ipv4_src_ipv6.ipv4_layout.ipv4), 1689 &ib_spec->ipv4.val.src_ip, 1690 sizeof(ib_spec->ipv4.val.src_ip)); 1691 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1692 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 1693 &ib_spec->ipv4.mask.dst_ip, 1694 sizeof(ib_spec->ipv4.mask.dst_ip)); 1695 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1696 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 1697 &ib_spec->ipv4.val.dst_ip, 1698 sizeof(ib_spec->ipv4.val.dst_ip)); 1699 1700 set_tos(outer_headers_c, outer_headers_v, 1701 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos); 1702 1703 set_proto(outer_headers_c, outer_headers_v, 1704 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto); 1705 break; 1706 case IB_FLOW_SPEC_IPV6: 1707 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD)) 1708 return -ENOTSUPP; 1709 1710 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1711 ethertype, 0xffff); 1712 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1713 ethertype, IPPROTO_IPV6); 1714 1715 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1716 src_ipv4_src_ipv6.ipv6_layout.ipv6), 1717 &ib_spec->ipv6.mask.src_ip, 1718 sizeof(ib_spec->ipv6.mask.src_ip)); 1719 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1720 src_ipv4_src_ipv6.ipv6_layout.ipv6), 1721 &ib_spec->ipv6.val.src_ip, 1722 sizeof(ib_spec->ipv6.val.src_ip)); 1723 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1724 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 1725 &ib_spec->ipv6.mask.dst_ip, 1726 sizeof(ib_spec->ipv6.mask.dst_ip)); 1727 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1728 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 1729 &ib_spec->ipv6.val.dst_ip, 1730 sizeof(ib_spec->ipv6.val.dst_ip)); 1731 1732 set_tos(outer_headers_c, outer_headers_v, 1733 ib_spec->ipv6.mask.traffic_class, 1734 ib_spec->ipv6.val.traffic_class); 1735 1736 set_proto(outer_headers_c, outer_headers_v, 1737 ib_spec->ipv6.mask.next_hdr, 1738 ib_spec->ipv6.val.next_hdr); 1739 1740 MLX5_SET(fte_match_set_misc, misc_params_c, 1741 outer_ipv6_flow_label, 1742 ntohl(ib_spec->ipv6.mask.flow_label)); 1743 MLX5_SET(fte_match_set_misc, misc_params_v, 1744 outer_ipv6_flow_label, 1745 ntohl(ib_spec->ipv6.val.flow_label)); 1746 break; 1747 case IB_FLOW_SPEC_TCP: 1748 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 1749 LAST_TCP_UDP_FIELD)) 1750 return -ENOTSUPP; 1751 1752 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol, 1753 0xff); 1754 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol, 1755 IPPROTO_TCP); 1756 1757 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_sport, 1758 ntohs(ib_spec->tcp_udp.mask.src_port)); 1759 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_sport, 1760 ntohs(ib_spec->tcp_udp.val.src_port)); 1761 1762 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_dport, 1763 ntohs(ib_spec->tcp_udp.mask.dst_port)); 1764 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_dport, 1765 ntohs(ib_spec->tcp_udp.val.dst_port)); 1766 break; 1767 case IB_FLOW_SPEC_UDP: 1768 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 1769 LAST_TCP_UDP_FIELD)) 1770 return -ENOTSUPP; 1771 1772 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol, 1773 0xff); 1774 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol, 1775 IPPROTO_UDP); 1776 1777 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_sport, 1778 ntohs(ib_spec->tcp_udp.mask.src_port)); 1779 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_sport, 1780 ntohs(ib_spec->tcp_udp.val.src_port)); 1781 1782 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_dport, 1783 ntohs(ib_spec->tcp_udp.mask.dst_port)); 1784 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_dport, 1785 ntohs(ib_spec->tcp_udp.val.dst_port)); 1786 break; 1787 default: 1788 return -EINVAL; 1789 } 1790 1791 return 0; 1792} 1793 1794/* If a flow could catch both multicast and unicast packets, 1795 * it won't fall into the multicast flow steering table and this rule 1796 * could steal other multicast packets. 1797 */ 1798static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr) 1799{ 1800 struct ib_flow_spec_eth *eth_spec; 1801 1802 if (ib_attr->type != IB_FLOW_ATTR_NORMAL || 1803 ib_attr->size < sizeof(struct ib_flow_attr) + 1804 sizeof(struct ib_flow_spec_eth) || 1805 ib_attr->num_of_specs < 1) 1806 return false; 1807 1808 eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1); 1809 if (eth_spec->type != IB_FLOW_SPEC_ETH || 1810 eth_spec->size != sizeof(*eth_spec)) 1811 return false; 1812 1813 return is_multicast_ether_addr(eth_spec->mask.dst_mac) && 1814 is_multicast_ether_addr(eth_spec->val.dst_mac); 1815} 1816 1817static bool is_valid_attr(const struct ib_flow_attr *flow_attr) 1818{ 1819 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1); 1820 bool has_ipv4_spec = false; 1821 bool eth_type_ipv4 = true; 1822 unsigned int spec_index; 1823 1824 /* Validate that ethertype is correct */ 1825 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 1826 if (ib_spec->type == IB_FLOW_SPEC_ETH && 1827 ib_spec->eth.mask.ether_type) { 1828 if (!((ib_spec->eth.mask.ether_type == htons(0xffff)) && 1829 ib_spec->eth.val.ether_type == htons(ETH_P_IP))) 1830 eth_type_ipv4 = false; 1831 } else if (ib_spec->type == IB_FLOW_SPEC_IPV4) { 1832 has_ipv4_spec = true; 1833 } 1834 ib_spec = (void *)ib_spec + ib_spec->size; 1835 } 1836 return !has_ipv4_spec || eth_type_ipv4; 1837} 1838 1839static void put_flow_table(struct mlx5_ib_dev *dev, 1840 struct mlx5_ib_flow_prio *prio, bool ft_added) 1841{ 1842 prio->refcount -= !!ft_added; 1843 if (!prio->refcount) { 1844 mlx5_destroy_flow_table(prio->flow_table); 1845 prio->flow_table = NULL; 1846 } 1847} 1848 1849static int mlx5_ib_destroy_flow(struct ib_flow *flow_id) 1850{ 1851 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device); 1852 struct mlx5_ib_flow_handler *handler = container_of(flow_id, 1853 struct mlx5_ib_flow_handler, 1854 ibflow); 1855 struct mlx5_ib_flow_handler *iter, *tmp; 1856 1857 mutex_lock(&dev->flow_db.lock); 1858 1859 list_for_each_entry_safe(iter, tmp, &handler->list, list) { 1860 mlx5_del_flow_rule(iter->rule); 1861 put_flow_table(dev, iter->prio, true); 1862 list_del(&iter->list); 1863 kfree(iter); 1864 } 1865 1866 mlx5_del_flow_rule(handler->rule); 1867 put_flow_table(dev, handler->prio, true); 1868 mutex_unlock(&dev->flow_db.lock); 1869 1870 kfree(handler); 1871 1872 return 0; 1873} 1874 1875static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap) 1876{ 1877 priority *= 2; 1878 if (!dont_trap) 1879 priority++; 1880 return priority; 1881} 1882 1883enum flow_table_type { 1884 MLX5_IB_FT_RX, 1885 MLX5_IB_FT_TX 1886}; 1887 1888#define MLX5_FS_MAX_TYPES 10 1889#define MLX5_FS_MAX_ENTRIES 32000UL 1890static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev, 1891 struct ib_flow_attr *flow_attr, 1892 enum flow_table_type ft_type) 1893{ 1894 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP; 1895 struct mlx5_flow_namespace *ns = NULL; 1896 struct mlx5_ib_flow_prio *prio; 1897 struct mlx5_flow_table *ft; 1898 int num_entries; 1899 int num_groups; 1900 int priority; 1901 int err = 0; 1902 1903 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 1904 if (flow_is_multicast_only(flow_attr) && 1905 !dont_trap) 1906 priority = MLX5_IB_FLOW_MCAST_PRIO; 1907 else 1908 priority = ib_prio_to_core_prio(flow_attr->priority, 1909 dont_trap); 1910 ns = mlx5_get_flow_namespace(dev->mdev, 1911 MLX5_FLOW_NAMESPACE_BYPASS); 1912 num_entries = MLX5_FS_MAX_ENTRIES; 1913 num_groups = MLX5_FS_MAX_TYPES; 1914 prio = &dev->flow_db.prios[priority]; 1915 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 1916 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 1917 ns = mlx5_get_flow_namespace(dev->mdev, 1918 MLX5_FLOW_NAMESPACE_LEFTOVERS); 1919 build_leftovers_ft_param("bypass", &priority, 1920 &num_entries, 1921 &num_groups); 1922 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO]; 1923 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 1924 if (!MLX5_CAP_FLOWTABLE(dev->mdev, 1925 allow_sniffer_and_nic_rx_shared_tir)) 1926 return ERR_PTR(-ENOTSUPP); 1927 1928 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ? 1929 MLX5_FLOW_NAMESPACE_SNIFFER_RX : 1930 MLX5_FLOW_NAMESPACE_SNIFFER_TX); 1931 1932 prio = &dev->flow_db.sniffer[ft_type]; 1933 priority = 0; 1934 num_entries = 1; 1935 num_groups = 1; 1936 } 1937 1938 if (!ns) 1939 return ERR_PTR(-ENOTSUPP); 1940 1941 ft = prio->flow_table; 1942 if (!ft) { 1943 ft = mlx5_create_auto_grouped_flow_table(ns, priority, "bypass", 1944 num_entries, 1945 num_groups); 1946 1947 if (!IS_ERR(ft)) { 1948 prio->refcount = 0; 1949 prio->flow_table = ft; 1950 } else { 1951 err = PTR_ERR(ft); 1952 } 1953 } 1954 1955 return err ? ERR_PTR(err) : prio; 1956} 1957 1958static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev, 1959 struct mlx5_ib_flow_prio *ft_prio, 1960 const struct ib_flow_attr *flow_attr, 1961 struct mlx5_flow_destination *dst) 1962{ 1963 struct mlx5_flow_table *ft = ft_prio->flow_table; 1964 struct mlx5_ib_flow_handler *handler; 1965 struct mlx5_flow_spec *spec; 1966 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr); 1967 unsigned int spec_index; 1968 u32 action; 1969 int err = 0; 1970 1971 if (!is_valid_attr(flow_attr)) 1972 return ERR_PTR(-EINVAL); 1973 1974 spec = mlx5_vzalloc(sizeof(*spec)); 1975 handler = kzalloc(sizeof(*handler), GFP_KERNEL); 1976 if (!handler || !spec) { 1977 err = -ENOMEM; 1978 goto free; 1979 } 1980 1981 INIT_LIST_HEAD(&handler->list); 1982 1983 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 1984 err = parse_flow_attr(spec->match_criteria, 1985 spec->match_value, ib_flow); 1986 if (err < 0) 1987 goto free; 1988 1989 ib_flow += ((union ib_flow_spec *)ib_flow)->size; 1990 } 1991 1992 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria); 1993 action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST : 1994 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO; 1995 handler->rule = mlx5_add_flow_rule(ft, spec->match_criteria_enable, 1996 spec->match_criteria, 1997 spec->match_value, 1998 action, 1999 MLX5_FS_DEFAULT_FLOW_TAG, 2000 dst); 2001 2002 if (IS_ERR(handler->rule)) { 2003 err = PTR_ERR(handler->rule); 2004 goto free; 2005 } 2006 2007 ft_prio->refcount++; 2008 handler->prio = ft_prio; 2009 2010 ft_prio->flow_table = ft; 2011free: 2012 if (err) 2013 kfree(handler); 2014 kvfree(spec); 2015 return err ? ERR_PTR(err) : handler; 2016} 2017 2018static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev, 2019 struct mlx5_ib_flow_prio *ft_prio, 2020 struct ib_flow_attr *flow_attr, 2021 struct mlx5_flow_destination *dst) 2022{ 2023 struct mlx5_ib_flow_handler *handler_dst = NULL; 2024 struct mlx5_ib_flow_handler *handler = NULL; 2025 2026 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL); 2027 if (!IS_ERR(handler)) { 2028 handler_dst = create_flow_rule(dev, ft_prio, 2029 flow_attr, dst); 2030 if (IS_ERR(handler_dst)) { 2031 mlx5_del_flow_rule(handler->rule); 2032 ft_prio->refcount--; 2033 kfree(handler); 2034 handler = handler_dst; 2035 } else { 2036 list_add(&handler_dst->list, &handler->list); 2037 } 2038 } 2039 2040 return handler; 2041} 2042enum { 2043 LEFTOVERS_MC, 2044 LEFTOVERS_UC, 2045}; 2046 2047static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev, 2048 struct mlx5_ib_flow_prio *ft_prio, 2049 struct ib_flow_attr *flow_attr, 2050 struct mlx5_flow_destination *dst) 2051{ 2052 struct mlx5_ib_flow_handler *handler_ucast = NULL; 2053 struct mlx5_ib_flow_handler *handler = NULL; 2054 2055 static struct { 2056 struct ib_flow_attr flow_attr; 2057 struct ib_flow_spec_eth eth_flow; 2058 } leftovers_specs[] = { 2059 [LEFTOVERS_MC] = { 2060 .flow_attr = { 2061 .num_of_specs = 1, 2062 .size = sizeof(leftovers_specs[0]) 2063 }, 2064 .eth_flow = { 2065 .type = IB_FLOW_SPEC_ETH, 2066 .size = sizeof(struct ib_flow_spec_eth), 2067 .mask = {.dst_mac = {0x1} }, 2068 .val = {.dst_mac = {0x1} } 2069 } 2070 }, 2071 [LEFTOVERS_UC] = { 2072 .flow_attr = { 2073 .num_of_specs = 1, 2074 .size = sizeof(leftovers_specs[0]) 2075 }, 2076 .eth_flow = { 2077 .type = IB_FLOW_SPEC_ETH, 2078 .size = sizeof(struct ib_flow_spec_eth), 2079 .mask = {.dst_mac = {0x1} }, 2080 .val = {.dst_mac = {} } 2081 } 2082 } 2083 }; 2084 2085 handler = create_flow_rule(dev, ft_prio, 2086 &leftovers_specs[LEFTOVERS_MC].flow_attr, 2087 dst); 2088 if (!IS_ERR(handler) && 2089 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) { 2090 handler_ucast = create_flow_rule(dev, ft_prio, 2091 &leftovers_specs[LEFTOVERS_UC].flow_attr, 2092 dst); 2093 if (IS_ERR(handler_ucast)) { 2094 mlx5_del_flow_rule(handler->rule); 2095 ft_prio->refcount--; 2096 kfree(handler); 2097 handler = handler_ucast; 2098 } else { 2099 list_add(&handler_ucast->list, &handler->list); 2100 } 2101 } 2102 2103 return handler; 2104} 2105 2106static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev, 2107 struct mlx5_ib_flow_prio *ft_rx, 2108 struct mlx5_ib_flow_prio *ft_tx, 2109 struct mlx5_flow_destination *dst) 2110{ 2111 struct mlx5_ib_flow_handler *handler_rx; 2112 struct mlx5_ib_flow_handler *handler_tx; 2113 int err; 2114 static const struct ib_flow_attr flow_attr = { 2115 .num_of_specs = 0, 2116 .size = sizeof(flow_attr) 2117 }; 2118 2119 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst); 2120 if (IS_ERR(handler_rx)) { 2121 err = PTR_ERR(handler_rx); 2122 goto err; 2123 } 2124 2125 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst); 2126 if (IS_ERR(handler_tx)) { 2127 err = PTR_ERR(handler_tx); 2128 goto err_tx; 2129 } 2130 2131 list_add(&handler_tx->list, &handler_rx->list); 2132 2133 return handler_rx; 2134 2135err_tx: 2136 mlx5_del_flow_rule(handler_rx->rule); 2137 ft_rx->refcount--; 2138 kfree(handler_rx); 2139err: 2140 return ERR_PTR(err); 2141} 2142 2143static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp, 2144 struct ib_flow_attr *flow_attr, 2145 int domain) 2146{ 2147 struct mlx5_ib_dev *dev = to_mdev(qp->device); 2148 struct mlx5_ib_qp *mqp = to_mqp(qp); 2149 struct mlx5_ib_flow_handler *handler = NULL; 2150 struct mlx5_flow_destination *dst = NULL; 2151 struct mlx5_ib_flow_prio *ft_prio_tx = NULL; 2152 struct mlx5_ib_flow_prio *ft_prio; 2153 int err; 2154 2155 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) 2156 return ERR_PTR(-ENOSPC); 2157 2158 if (domain != IB_FLOW_DOMAIN_USER || 2159 flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) || 2160 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP)) 2161 return ERR_PTR(-EINVAL); 2162 2163 dst = kzalloc(sizeof(*dst), GFP_KERNEL); 2164 if (!dst) 2165 return ERR_PTR(-ENOMEM); 2166 2167 mutex_lock(&dev->flow_db.lock); 2168 2169 ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX); 2170 if (IS_ERR(ft_prio)) { 2171 err = PTR_ERR(ft_prio); 2172 goto unlock; 2173 } 2174 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 2175 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX); 2176 if (IS_ERR(ft_prio_tx)) { 2177 err = PTR_ERR(ft_prio_tx); 2178 ft_prio_tx = NULL; 2179 goto destroy_ft; 2180 } 2181 } 2182 2183 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR; 2184 if (mqp->flags & MLX5_IB_QP_RSS) 2185 dst->tir_num = mqp->rss_qp.tirn; 2186 else 2187 dst->tir_num = mqp->raw_packet_qp.rq.tirn; 2188 2189 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 2190 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) { 2191 handler = create_dont_trap_rule(dev, ft_prio, 2192 flow_attr, dst); 2193 } else { 2194 handler = create_flow_rule(dev, ft_prio, flow_attr, 2195 dst); 2196 } 2197 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 2198 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 2199 handler = create_leftovers_rule(dev, ft_prio, flow_attr, 2200 dst); 2201 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 2202 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst); 2203 } else { 2204 err = -EINVAL; 2205 goto destroy_ft; 2206 } 2207 2208 if (IS_ERR(handler)) { 2209 err = PTR_ERR(handler); 2210 handler = NULL; 2211 goto destroy_ft; 2212 } 2213 2214 mutex_unlock(&dev->flow_db.lock); 2215 kfree(dst); 2216 2217 return &handler->ibflow; 2218 2219destroy_ft: 2220 put_flow_table(dev, ft_prio, false); 2221 if (ft_prio_tx) 2222 put_flow_table(dev, ft_prio_tx, false); 2223unlock: 2224 mutex_unlock(&dev->flow_db.lock); 2225 kfree(dst); 2226 kfree(handler); 2227 return ERR_PTR(err); 2228} 2229 2230static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2231{ 2232 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2233 int err; 2234 2235 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num); 2236 if (err) 2237 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 2238 ibqp->qp_num, gid->raw); 2239 2240 return err; 2241} 2242 2243static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2244{ 2245 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2246 int err; 2247 2248 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num); 2249 if (err) 2250 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 2251 ibqp->qp_num, gid->raw); 2252 2253 return err; 2254} 2255 2256static int init_node_data(struct mlx5_ib_dev *dev) 2257{ 2258 int err; 2259 2260 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 2261 if (err) 2262 return err; 2263 2264 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 2265} 2266 2267static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr, 2268 char *buf) 2269{ 2270 struct mlx5_ib_dev *dev = 2271 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2272 2273 return sprintf(buf, "%lld\n", (long long)dev->mdev->priv.fw_pages); 2274} 2275 2276static ssize_t show_reg_pages(struct device *device, 2277 struct device_attribute *attr, char *buf) 2278{ 2279 struct mlx5_ib_dev *dev = 2280 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2281 2282 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 2283} 2284 2285static ssize_t show_hca(struct device *device, struct device_attribute *attr, 2286 char *buf) 2287{ 2288 struct mlx5_ib_dev *dev = 2289 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2290 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device); 2291} 2292 2293static ssize_t show_rev(struct device *device, struct device_attribute *attr, 2294 char *buf) 2295{ 2296 struct mlx5_ib_dev *dev = 2297 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2298 return sprintf(buf, "%x\n", dev->mdev->pdev->revision); 2299} 2300 2301static ssize_t show_board(struct device *device, struct device_attribute *attr, 2302 char *buf) 2303{ 2304 struct mlx5_ib_dev *dev = 2305 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2306 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 2307 dev->mdev->board_id); 2308} 2309 2310static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL); 2311static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL); 2312static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL); 2313static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL); 2314static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL); 2315 2316static struct device_attribute *mlx5_class_attributes[] = { 2317 &dev_attr_hw_rev, 2318 &dev_attr_hca_type, 2319 &dev_attr_board_id, 2320 &dev_attr_fw_pages, 2321 &dev_attr_reg_pages, 2322}; 2323 2324static void pkey_change_handler(struct work_struct *work) 2325{ 2326 struct mlx5_ib_port_resources *ports = 2327 container_of(work, struct mlx5_ib_port_resources, 2328 pkey_change_work); 2329 2330 mutex_lock(&ports->devr->mutex); 2331 mlx5_ib_gsi_pkey_change(ports->gsi); 2332 mutex_unlock(&ports->devr->mutex); 2333} 2334 2335static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 2336{ 2337 struct mlx5_ib_qp *mqp; 2338 struct mlx5_ib_cq *send_mcq, *recv_mcq; 2339 struct mlx5_core_cq *mcq; 2340 struct list_head cq_armed_list; 2341 unsigned long flags_qp; 2342 unsigned long flags_cq; 2343 unsigned long flags; 2344 2345 INIT_LIST_HEAD(&cq_armed_list); 2346 2347 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 2348 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 2349 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 2350 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 2351 if (mqp->sq.tail != mqp->sq.head) { 2352 send_mcq = to_mcq(mqp->ibqp.send_cq); 2353 spin_lock_irqsave(&send_mcq->lock, flags_cq); 2354 if (send_mcq->mcq.comp && 2355 mqp->ibqp.send_cq->comp_handler) { 2356 if (!send_mcq->mcq.reset_notify_added) { 2357 send_mcq->mcq.reset_notify_added = 1; 2358 list_add_tail(&send_mcq->mcq.reset_notify, 2359 &cq_armed_list); 2360 } 2361 } 2362 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 2363 } 2364 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 2365 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 2366 /* no handling is needed for SRQ */ 2367 if (!mqp->ibqp.srq) { 2368 if (mqp->rq.tail != mqp->rq.head) { 2369 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 2370 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 2371 if (recv_mcq->mcq.comp && 2372 mqp->ibqp.recv_cq->comp_handler) { 2373 if (!recv_mcq->mcq.reset_notify_added) { 2374 recv_mcq->mcq.reset_notify_added = 1; 2375 list_add_tail(&recv_mcq->mcq.reset_notify, 2376 &cq_armed_list); 2377 } 2378 } 2379 spin_unlock_irqrestore(&recv_mcq->lock, 2380 flags_cq); 2381 } 2382 } 2383 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 2384 } 2385 /*At that point all inflight post send were put to be executed as of we 2386 * lock/unlock above locks Now need to arm all involved CQs. 2387 */ 2388 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 2389 mcq->comp(mcq); 2390 } 2391 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 2392} 2393 2394static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context, 2395 enum mlx5_dev_event event, unsigned long param) 2396{ 2397 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context; 2398 struct ib_event ibev; 2399 bool fatal = false; 2400 u8 port = (u8)param; 2401 2402 switch (event) { 2403 case MLX5_DEV_EVENT_SYS_ERROR: 2404 ibev.event = IB_EVENT_DEVICE_FATAL; 2405 mlx5_ib_handle_internal_error(ibdev); 2406 fatal = true; 2407 break; 2408 2409 case MLX5_DEV_EVENT_PORT_UP: 2410 case MLX5_DEV_EVENT_PORT_DOWN: 2411 case MLX5_DEV_EVENT_PORT_INITIALIZED: 2412 /* In RoCE, port up/down events are handled in 2413 * mlx5_netdev_event(). 2414 */ 2415 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2416 IB_LINK_LAYER_ETHERNET) 2417 return; 2418 2419 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ? 2420 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 2421 break; 2422 2423 case MLX5_DEV_EVENT_LID_CHANGE: 2424 ibev.event = IB_EVENT_LID_CHANGE; 2425 break; 2426 2427 case MLX5_DEV_EVENT_PKEY_CHANGE: 2428 ibev.event = IB_EVENT_PKEY_CHANGE; 2429 2430 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 2431 break; 2432 2433 case MLX5_DEV_EVENT_GUID_CHANGE: 2434 ibev.event = IB_EVENT_GID_CHANGE; 2435 break; 2436 2437 case MLX5_DEV_EVENT_CLIENT_REREG: 2438 ibev.event = IB_EVENT_CLIENT_REREGISTER; 2439 break; 2440 2441 default: 2442 /* unsupported event */ 2443 return; 2444 } 2445 2446 ibev.device = &ibdev->ib_dev; 2447 ibev.element.port_num = port; 2448 2449 if (!rdma_is_port_valid(&ibdev->ib_dev, port)) { 2450 mlx5_ib_warn(ibdev, "warning: event(%d) on port %d\n", event, port); 2451 return; 2452 } 2453 2454 if (ibdev->ib_active) 2455 ib_dispatch_event(&ibev); 2456 2457 if (fatal) 2458 ibdev->ib_active = false; 2459} 2460 2461static void get_ext_port_caps(struct mlx5_ib_dev *dev) 2462{ 2463 int port; 2464 2465 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) 2466 mlx5_query_ext_port_caps(dev, port); 2467} 2468 2469static int get_port_caps(struct mlx5_ib_dev *dev) 2470{ 2471 struct ib_device_attr *dprops = NULL; 2472 struct ib_port_attr *pprops = NULL; 2473 int err = -ENOMEM; 2474 int port; 2475 struct ib_udata uhw = {.inlen = 0, .outlen = 0}; 2476 2477 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL); 2478 if (!pprops) 2479 goto out; 2480 2481 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL); 2482 if (!dprops) 2483 goto out; 2484 2485 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw); 2486 if (err) { 2487 mlx5_ib_warn(dev, "query_device failed %d\n", err); 2488 goto out; 2489 } 2490 2491 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) { 2492 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops); 2493 if (err) { 2494 mlx5_ib_warn(dev, "query_port %d failed %d\n", 2495 port, err); 2496 break; 2497 } 2498 dev->mdev->port_caps[port - 1].pkey_table_len = 2499 dprops->max_pkeys; 2500 dev->mdev->port_caps[port - 1].gid_table_len = 2501 pprops->gid_tbl_len; 2502 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n", 2503 dprops->max_pkeys, pprops->gid_tbl_len); 2504 } 2505 2506out: 2507 kfree(pprops); 2508 kfree(dprops); 2509 2510 return err; 2511} 2512 2513static void destroy_umrc_res(struct mlx5_ib_dev *dev) 2514{ 2515 int err; 2516 2517 err = mlx5_mr_cache_cleanup(dev); 2518 if (err) 2519 mlx5_ib_warn(dev, "mr cache cleanup failed\n"); 2520 2521 mlx5_ib_destroy_qp(dev->umrc.qp); 2522 ib_free_cq(dev->umrc.cq); 2523 ib_dealloc_pd(dev->umrc.pd); 2524} 2525 2526enum { 2527 MAX_UMR_WR = 128, 2528}; 2529 2530static int create_umr_res(struct mlx5_ib_dev *dev) 2531{ 2532 struct ib_qp_init_attr *init_attr = NULL; 2533 struct ib_qp_attr *attr = NULL; 2534 struct ib_pd *pd; 2535 struct ib_cq *cq; 2536 struct ib_qp *qp; 2537 int ret; 2538 2539 attr = kzalloc(sizeof(*attr), GFP_KERNEL); 2540 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL); 2541 if (!attr || !init_attr) { 2542 ret = -ENOMEM; 2543 goto error_0; 2544 } 2545 2546 pd = ib_alloc_pd(&dev->ib_dev, 0); 2547 if (IS_ERR(pd)) { 2548 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n"); 2549 ret = PTR_ERR(pd); 2550 goto error_0; 2551 } 2552 2553 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ); 2554 if (IS_ERR(cq)) { 2555 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n"); 2556 ret = PTR_ERR(cq); 2557 goto error_2; 2558 } 2559 2560 init_attr->send_cq = cq; 2561 init_attr->recv_cq = cq; 2562 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR; 2563 init_attr->cap.max_send_wr = MAX_UMR_WR; 2564 init_attr->cap.max_send_sge = 1; 2565 init_attr->qp_type = MLX5_IB_QPT_REG_UMR; 2566 init_attr->port_num = 1; 2567 qp = mlx5_ib_create_qp(pd, init_attr, NULL); 2568 if (IS_ERR(qp)) { 2569 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n"); 2570 ret = PTR_ERR(qp); 2571 goto error_3; 2572 } 2573 qp->device = &dev->ib_dev; 2574 qp->real_qp = qp; 2575 qp->uobject = NULL; 2576 qp->qp_type = MLX5_IB_QPT_REG_UMR; 2577 2578 attr->qp_state = IB_QPS_INIT; 2579 attr->port_num = 1; 2580 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX | 2581 IB_QP_PORT, NULL); 2582 if (ret) { 2583 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n"); 2584 goto error_4; 2585 } 2586 2587 memset(attr, 0, sizeof(*attr)); 2588 attr->qp_state = IB_QPS_RTR; 2589 attr->path_mtu = IB_MTU_256; 2590 2591 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 2592 if (ret) { 2593 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n"); 2594 goto error_4; 2595 } 2596 2597 memset(attr, 0, sizeof(*attr)); 2598 attr->qp_state = IB_QPS_RTS; 2599 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 2600 if (ret) { 2601 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n"); 2602 goto error_4; 2603 } 2604 2605 dev->umrc.qp = qp; 2606 dev->umrc.cq = cq; 2607 dev->umrc.pd = pd; 2608 2609 sema_init(&dev->umrc.sem, MAX_UMR_WR); 2610 ret = mlx5_mr_cache_init(dev); 2611 if (ret) { 2612 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 2613 goto error_4; 2614 } 2615 2616 kfree(attr); 2617 kfree(init_attr); 2618 2619 return 0; 2620 2621error_4: 2622 mlx5_ib_destroy_qp(qp); 2623 2624error_3: 2625 ib_free_cq(cq); 2626 2627error_2: 2628 ib_dealloc_pd(pd); 2629 2630error_0: 2631 kfree(attr); 2632 kfree(init_attr); 2633 return ret; 2634} 2635 2636static int create_dev_resources(struct mlx5_ib_resources *devr) 2637{ 2638 struct ib_srq_init_attr attr; 2639 struct mlx5_ib_dev *dev; 2640 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 2641 int port; 2642 int ret = 0; 2643 2644 dev = container_of(devr, struct mlx5_ib_dev, devr); 2645 2646 mutex_init(&devr->mutex); 2647 2648 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL); 2649 if (IS_ERR(devr->p0)) { 2650 ret = PTR_ERR(devr->p0); 2651 goto error0; 2652 } 2653 devr->p0->device = &dev->ib_dev; 2654 devr->p0->uobject = NULL; 2655 atomic_set(&devr->p0->usecnt, 0); 2656 2657 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL); 2658 if (IS_ERR(devr->c0)) { 2659 ret = PTR_ERR(devr->c0); 2660 goto error1; 2661 } 2662 devr->c0->device = &dev->ib_dev; 2663 devr->c0->uobject = NULL; 2664 devr->c0->comp_handler = NULL; 2665 devr->c0->event_handler = NULL; 2666 devr->c0->cq_context = NULL; 2667 atomic_set(&devr->c0->usecnt, 0); 2668 2669 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 2670 if (IS_ERR(devr->x0)) { 2671 ret = PTR_ERR(devr->x0); 2672 goto error2; 2673 } 2674 devr->x0->device = &dev->ib_dev; 2675 devr->x0->inode = NULL; 2676 atomic_set(&devr->x0->usecnt, 0); 2677 mutex_init(&devr->x0->tgt_qp_mutex); 2678 INIT_LIST_HEAD(&devr->x0->tgt_qp_list); 2679 2680 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 2681 if (IS_ERR(devr->x1)) { 2682 ret = PTR_ERR(devr->x1); 2683 goto error3; 2684 } 2685 devr->x1->device = &dev->ib_dev; 2686 devr->x1->inode = NULL; 2687 atomic_set(&devr->x1->usecnt, 0); 2688 mutex_init(&devr->x1->tgt_qp_mutex); 2689 INIT_LIST_HEAD(&devr->x1->tgt_qp_list); 2690 2691 memset(&attr, 0, sizeof(attr)); 2692 attr.attr.max_sge = 1; 2693 attr.attr.max_wr = 1; 2694 attr.srq_type = IB_SRQT_XRC; 2695 attr.ext.xrc.cq = devr->c0; 2696 attr.ext.xrc.xrcd = devr->x0; 2697 2698 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 2699 if (IS_ERR(devr->s0)) { 2700 ret = PTR_ERR(devr->s0); 2701 goto error4; 2702 } 2703 devr->s0->device = &dev->ib_dev; 2704 devr->s0->pd = devr->p0; 2705 devr->s0->uobject = NULL; 2706 devr->s0->event_handler = NULL; 2707 devr->s0->srq_context = NULL; 2708 devr->s0->srq_type = IB_SRQT_XRC; 2709 devr->s0->ext.xrc.xrcd = devr->x0; 2710 devr->s0->ext.xrc.cq = devr->c0; 2711 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt); 2712 atomic_inc(&devr->s0->ext.xrc.cq->usecnt); 2713 atomic_inc(&devr->p0->usecnt); 2714 atomic_set(&devr->s0->usecnt, 0); 2715 2716 memset(&attr, 0, sizeof(attr)); 2717 attr.attr.max_sge = 1; 2718 attr.attr.max_wr = 1; 2719 attr.srq_type = IB_SRQT_BASIC; 2720 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 2721 if (IS_ERR(devr->s1)) { 2722 ret = PTR_ERR(devr->s1); 2723 goto error5; 2724 } 2725 devr->s1->device = &dev->ib_dev; 2726 devr->s1->pd = devr->p0; 2727 devr->s1->uobject = NULL; 2728 devr->s1->event_handler = NULL; 2729 devr->s1->srq_context = NULL; 2730 devr->s1->srq_type = IB_SRQT_BASIC; 2731 devr->s1->ext.xrc.cq = devr->c0; 2732 atomic_inc(&devr->p0->usecnt); 2733 atomic_set(&devr->s0->usecnt, 0); 2734 2735 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) { 2736 INIT_WORK(&devr->ports[port].pkey_change_work, 2737 pkey_change_handler); 2738 devr->ports[port].devr = devr; 2739 } 2740 2741 return 0; 2742 2743error5: 2744 mlx5_ib_destroy_srq(devr->s0); 2745error4: 2746 mlx5_ib_dealloc_xrcd(devr->x1); 2747error3: 2748 mlx5_ib_dealloc_xrcd(devr->x0); 2749error2: 2750 mlx5_ib_destroy_cq(devr->c0); 2751error1: 2752 mlx5_ib_dealloc_pd(devr->p0); 2753error0: 2754 return ret; 2755} 2756 2757static void destroy_dev_resources(struct mlx5_ib_resources *devr) 2758{ 2759 struct mlx5_ib_dev *dev = 2760 container_of(devr, struct mlx5_ib_dev, devr); 2761 int port; 2762 2763 mlx5_ib_destroy_srq(devr->s1); 2764 mlx5_ib_destroy_srq(devr->s0); 2765 mlx5_ib_dealloc_xrcd(devr->x0); 2766 mlx5_ib_dealloc_xrcd(devr->x1); 2767 mlx5_ib_destroy_cq(devr->c0); 2768 mlx5_ib_dealloc_pd(devr->p0); 2769 2770 /* Make sure no change P_Key work items are still executing */ 2771 for (port = 0; port < dev->num_ports; ++port) 2772 cancel_work_sync(&devr->ports[port].pkey_change_work); 2773} 2774 2775static u32 get_core_cap_flags(struct ib_device *ibdev) 2776{ 2777 struct mlx5_ib_dev *dev = to_mdev(ibdev); 2778 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 2779 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 2780 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 2781 u32 ret = 0; 2782 2783 if (ll == IB_LINK_LAYER_INFINIBAND) 2784 return RDMA_CORE_PORT_IBA_IB; 2785 2786 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 2787 return 0; 2788 2789 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 2790 return 0; 2791 2792 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 2793 ret |= RDMA_CORE_PORT_IBA_ROCE; 2794 2795 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 2796 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 2797 2798 return ret; 2799} 2800 2801static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num, 2802 struct ib_port_immutable *immutable) 2803{ 2804 struct ib_port_attr attr; 2805 int err; 2806 2807 err = mlx5_ib_query_port(ibdev, port_num, &attr); 2808 if (err) 2809 return err; 2810 2811 immutable->pkey_tbl_len = attr.pkey_tbl_len; 2812 immutable->gid_tbl_len = attr.gid_tbl_len; 2813 immutable->core_cap_flags = get_core_cap_flags(ibdev); 2814 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 2815 2816 return 0; 2817} 2818 2819static void get_dev_fw_str(struct ib_device *ibdev, char *str, 2820 size_t str_len) 2821{ 2822 struct mlx5_ib_dev *dev = 2823 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 2824 snprintf(str, str_len, "%d.%d.%04d", fw_rev_maj(dev->mdev), 2825 fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev)); 2826} 2827 2828static int mlx5_roce_lag_init(struct mlx5_ib_dev *dev) 2829{ 2830 return 0; 2831} 2832 2833static void mlx5_roce_lag_cleanup(struct mlx5_ib_dev *dev) 2834{ 2835} 2836 2837static void mlx5_remove_roce_notifier(struct mlx5_ib_dev *dev) 2838{ 2839 if (dev->roce.nb.notifier_call) { 2840 unregister_netdevice_notifier(&dev->roce.nb); 2841 dev->roce.nb.notifier_call = NULL; 2842 } 2843} 2844 2845static int mlx5_enable_roce(struct mlx5_ib_dev *dev) 2846{ 2847 VNET_ITERATOR_DECL(vnet_iter); 2848 struct net_device *idev; 2849 int err; 2850 2851 /* Check if mlx5en net device already exists */ 2852 VNET_LIST_RLOCK(); 2853 VNET_FOREACH(vnet_iter) { 2854 IFNET_RLOCK(); 2855 CURVNET_SET_QUIET(vnet_iter); 2856 TAILQ_FOREACH(idev, &V_ifnet, if_link) { 2857 /* check if network interface belongs to mlx5en */ 2858 if (!mlx5_netdev_match(idev, dev->mdev, "mce")) 2859 continue; 2860 write_lock(&dev->roce.netdev_lock); 2861 dev->roce.netdev = idev; 2862 write_unlock(&dev->roce.netdev_lock); 2863 } 2864 CURVNET_RESTORE(); 2865 IFNET_RUNLOCK(); 2866 } 2867 VNET_LIST_RUNLOCK(); 2868 2869 dev->roce.nb.notifier_call = mlx5_netdev_event; 2870 err = register_netdevice_notifier(&dev->roce.nb); 2871 if (err) { 2872 dev->roce.nb.notifier_call = NULL; 2873 return err; 2874 } 2875 2876 err = mlx5_nic_vport_enable_roce(dev->mdev); 2877 if (err) 2878 goto err_unregister_netdevice_notifier; 2879 2880 err = mlx5_roce_lag_init(dev); 2881 if (err) 2882 goto err_disable_roce; 2883 2884 return 0; 2885 2886err_disable_roce: 2887 mlx5_nic_vport_disable_roce(dev->mdev); 2888 2889err_unregister_netdevice_notifier: 2890 mlx5_remove_roce_notifier(dev); 2891 return err; 2892} 2893 2894static void mlx5_disable_roce(struct mlx5_ib_dev *dev) 2895{ 2896 mlx5_roce_lag_cleanup(dev); 2897 mlx5_nic_vport_disable_roce(dev->mdev); 2898} 2899 2900static void mlx5_ib_dealloc_q_port_counter(struct mlx5_ib_dev *dev, u8 port_num) 2901{ 2902 mlx5_vport_dealloc_q_counter(dev->mdev, 2903 MLX5_INTERFACE_PROTOCOL_IB, 2904 dev->port[port_num].q_cnt_id); 2905 dev->port[port_num].q_cnt_id = 0; 2906} 2907 2908static void mlx5_ib_dealloc_q_counters(struct mlx5_ib_dev *dev) 2909{ 2910 unsigned int i; 2911 2912 for (i = 0; i < dev->num_ports; i++) 2913 mlx5_ib_dealloc_q_port_counter(dev, i); 2914} 2915 2916static int mlx5_ib_alloc_q_counters(struct mlx5_ib_dev *dev) 2917{ 2918 int i; 2919 int ret; 2920 2921 for (i = 0; i < dev->num_ports; i++) { 2922 ret = mlx5_vport_alloc_q_counter(dev->mdev, 2923 MLX5_INTERFACE_PROTOCOL_IB, 2924 &dev->port[i].q_cnt_id); 2925 if (ret) { 2926 mlx5_ib_warn(dev, 2927 "couldn't allocate queue counter for port %d, err %d\n", 2928 i + 1, ret); 2929 goto dealloc_counters; 2930 } 2931 } 2932 2933 return 0; 2934 2935dealloc_counters: 2936 while (--i >= 0) 2937 mlx5_ib_dealloc_q_port_counter(dev, i); 2938 2939 return ret; 2940} 2941 2942static const char * const names[] = { 2943 "rx_write_requests", 2944 "rx_read_requests", 2945 "rx_atomic_requests", 2946 "out_of_buffer", 2947 "out_of_sequence", 2948 "duplicate_request", 2949 "rnr_nak_retry_err", 2950 "packet_seq_err", 2951 "implied_nak_seq_err", 2952 "local_ack_timeout_err", 2953}; 2954 2955static const size_t stats_offsets[] = { 2956 MLX5_BYTE_OFF(query_q_counter_out, rx_write_requests), 2957 MLX5_BYTE_OFF(query_q_counter_out, rx_read_requests), 2958 MLX5_BYTE_OFF(query_q_counter_out, rx_atomic_requests), 2959 MLX5_BYTE_OFF(query_q_counter_out, out_of_buffer), 2960 MLX5_BYTE_OFF(query_q_counter_out, out_of_sequence), 2961 MLX5_BYTE_OFF(query_q_counter_out, duplicate_request), 2962 MLX5_BYTE_OFF(query_q_counter_out, rnr_nak_retry_err), 2963 MLX5_BYTE_OFF(query_q_counter_out, packet_seq_err), 2964 MLX5_BYTE_OFF(query_q_counter_out, implied_nak_seq_err), 2965 MLX5_BYTE_OFF(query_q_counter_out, local_ack_timeout_err), 2966}; 2967 2968static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev, 2969 u8 port_num) 2970{ 2971 BUILD_BUG_ON(ARRAY_SIZE(names) != ARRAY_SIZE(stats_offsets)); 2972 2973 /* We support only per port stats */ 2974 if (port_num == 0) 2975 return NULL; 2976 2977 return rdma_alloc_hw_stats_struct(names, ARRAY_SIZE(names), 2978 RDMA_HW_STATS_DEFAULT_LIFESPAN); 2979} 2980 2981static int mlx5_ib_get_hw_stats(struct ib_device *ibdev, 2982 struct rdma_hw_stats *stats, 2983 u8 port, int index) 2984{ 2985 struct mlx5_ib_dev *dev = to_mdev(ibdev); 2986 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out); 2987 void *out; 2988 __be32 val; 2989 int ret; 2990 int i; 2991 2992 if (!port || !stats) 2993 return -ENOSYS; 2994 2995 out = mlx5_vzalloc(outlen); 2996 if (!out) 2997 return -ENOMEM; 2998 2999 ret = mlx5_vport_query_q_counter(dev->mdev, 3000 dev->port[port - 1].q_cnt_id, 0, 3001 out, outlen); 3002 if (ret) 3003 goto free; 3004 3005 for (i = 0; i < ARRAY_SIZE(names); i++) { 3006 val = *(__be32 *)(out + stats_offsets[i]); 3007 stats->value[i] = (u64)be32_to_cpu(val); 3008 } 3009free: 3010 kvfree(out); 3011 return ARRAY_SIZE(names); 3012} 3013 3014static void *mlx5_ib_add(struct mlx5_core_dev *mdev) 3015{ 3016 struct mlx5_ib_dev *dev; 3017 enum rdma_link_layer ll; 3018 int port_type_cap; 3019 int err; 3020 int i; 3021 3022 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 3023 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 3024 3025 if ((ll == IB_LINK_LAYER_ETHERNET) && !MLX5_CAP_GEN(mdev, roce)) 3026 return NULL; 3027 3028 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev)); 3029 if (!dev) 3030 return NULL; 3031 3032 dev->mdev = mdev; 3033 3034 dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port), 3035 GFP_KERNEL); 3036 if (!dev->port) 3037 goto err_dealloc; 3038 3039 rwlock_init(&dev->roce.netdev_lock); 3040 err = get_port_caps(dev); 3041 if (err) 3042 goto err_free_port; 3043 3044 if (mlx5_use_mad_ifc(dev)) 3045 get_ext_port_caps(dev); 3046 3047 MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock); 3048 3049 snprintf(dev->ib_dev.name, IB_DEVICE_NAME_MAX, "mlx5_%d", device_get_unit(mdev->pdev->dev.bsddev)); 3050 dev->ib_dev.owner = THIS_MODULE; 3051 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 3052 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 3053 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports); 3054 dev->ib_dev.phys_port_cnt = dev->num_ports; 3055 dev->ib_dev.num_comp_vectors = 3056 dev->mdev->priv.eq_table.num_comp_vectors; 3057 dev->ib_dev.dma_device = &mdev->pdev->dev; 3058 3059 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION; 3060 dev->ib_dev.uverbs_cmd_mask = 3061 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | 3062 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | 3063 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | 3064 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | 3065 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | 3066 (1ull << IB_USER_VERBS_CMD_CREATE_AH) | 3067 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) | 3068 (1ull << IB_USER_VERBS_CMD_REG_MR) | 3069 (1ull << IB_USER_VERBS_CMD_REREG_MR) | 3070 (1ull << IB_USER_VERBS_CMD_DEREG_MR) | 3071 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 3072 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | 3073 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) | 3074 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | 3075 (1ull << IB_USER_VERBS_CMD_CREATE_QP) | 3076 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | 3077 (1ull << IB_USER_VERBS_CMD_QUERY_QP) | 3078 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | 3079 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) | 3080 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) | 3081 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) | 3082 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) | 3083 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) | 3084 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | 3085 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) | 3086 (1ull << IB_USER_VERBS_CMD_OPEN_QP); 3087 dev->ib_dev.uverbs_ex_cmd_mask = 3088 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) | 3089 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) | 3090 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP); 3091 3092 dev->ib_dev.query_device = mlx5_ib_query_device; 3093 dev->ib_dev.query_port = mlx5_ib_query_port; 3094 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer; 3095 if (ll == IB_LINK_LAYER_ETHERNET) 3096 dev->ib_dev.get_netdev = mlx5_ib_get_netdev; 3097 dev->ib_dev.query_gid = mlx5_ib_query_gid; 3098 dev->ib_dev.add_gid = mlx5_ib_add_gid; 3099 dev->ib_dev.del_gid = mlx5_ib_del_gid; 3100 dev->ib_dev.query_pkey = mlx5_ib_query_pkey; 3101 dev->ib_dev.modify_device = mlx5_ib_modify_device; 3102 dev->ib_dev.modify_port = mlx5_ib_modify_port; 3103 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext; 3104 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext; 3105 dev->ib_dev.mmap = mlx5_ib_mmap; 3106 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd; 3107 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd; 3108 dev->ib_dev.create_ah = mlx5_ib_create_ah; 3109 dev->ib_dev.query_ah = mlx5_ib_query_ah; 3110 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah; 3111 dev->ib_dev.create_srq = mlx5_ib_create_srq; 3112 dev->ib_dev.modify_srq = mlx5_ib_modify_srq; 3113 dev->ib_dev.query_srq = mlx5_ib_query_srq; 3114 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq; 3115 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv; 3116 dev->ib_dev.create_qp = mlx5_ib_create_qp; 3117 dev->ib_dev.modify_qp = mlx5_ib_modify_qp; 3118 dev->ib_dev.query_qp = mlx5_ib_query_qp; 3119 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp; 3120 dev->ib_dev.post_send = mlx5_ib_post_send; 3121 dev->ib_dev.post_recv = mlx5_ib_post_recv; 3122 dev->ib_dev.create_cq = mlx5_ib_create_cq; 3123 dev->ib_dev.modify_cq = mlx5_ib_modify_cq; 3124 dev->ib_dev.resize_cq = mlx5_ib_resize_cq; 3125 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq; 3126 dev->ib_dev.poll_cq = mlx5_ib_poll_cq; 3127 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq; 3128 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr; 3129 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr; 3130 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr; 3131 dev->ib_dev.reg_phys_mr = mlx5_ib_reg_phys_mr; 3132 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr; 3133 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach; 3134 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach; 3135 dev->ib_dev.process_mad = mlx5_ib_process_mad; 3136 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr; 3137 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg; 3138 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status; 3139 dev->ib_dev.get_port_immutable = mlx5_port_immutable; 3140 dev->ib_dev.get_dev_fw_str = get_dev_fw_str; 3141 if (mlx5_core_is_pf(mdev)) { 3142 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config; 3143 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state; 3144 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats; 3145 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid; 3146 } 3147 3148 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext; 3149 3150 mlx5_ib_internal_fill_odp_caps(dev); 3151 3152 if (MLX5_CAP_GEN(mdev, imaicl)) { 3153 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw; 3154 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw; 3155 dev->ib_dev.uverbs_cmd_mask |= 3156 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) | 3157 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW); 3158 } 3159 3160 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt) && 3161 MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) { 3162 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats; 3163 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats; 3164 } 3165 3166 if (MLX5_CAP_GEN(mdev, xrc)) { 3167 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd; 3168 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd; 3169 dev->ib_dev.uverbs_cmd_mask |= 3170 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) | 3171 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD); 3172 } 3173 3174 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) == 3175 IB_LINK_LAYER_ETHERNET) { 3176 dev->ib_dev.create_flow = mlx5_ib_create_flow; 3177 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow; 3178 dev->ib_dev.create_wq = mlx5_ib_create_wq; 3179 dev->ib_dev.modify_wq = mlx5_ib_modify_wq; 3180 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq; 3181 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table; 3182 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table; 3183 dev->ib_dev.uverbs_ex_cmd_mask |= 3184 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) | 3185 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW) | 3186 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) | 3187 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) | 3188 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) | 3189 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) | 3190 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL); 3191 } 3192 err = init_node_data(dev); 3193 if (err) 3194 goto err_free_port; 3195 3196 mutex_init(&dev->flow_db.lock); 3197 mutex_init(&dev->cap_mask_mutex); 3198 INIT_LIST_HEAD(&dev->qp_list); 3199 spin_lock_init(&dev->reset_flow_resource_lock); 3200 3201 if (ll == IB_LINK_LAYER_ETHERNET) { 3202 err = mlx5_enable_roce(dev); 3203 if (err) 3204 goto err_free_port; 3205 } 3206 3207 err = create_dev_resources(&dev->devr); 3208 if (err) 3209 goto err_disable_roce; 3210 3211 err = mlx5_ib_odp_init_one(dev); 3212 if (err) 3213 goto err_rsrc; 3214 3215 err = mlx5_ib_alloc_q_counters(dev); 3216 if (err) 3217 goto err_odp; 3218 3219 err = ib_register_device(&dev->ib_dev, NULL); 3220 if (err) 3221 goto err_q_cnt; 3222 3223 err = create_umr_res(dev); 3224 if (err) 3225 goto err_dev; 3226 3227 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) { 3228 err = device_create_file(&dev->ib_dev.dev, 3229 mlx5_class_attributes[i]); 3230 if (err) 3231 goto err_umrc; 3232 } 3233 3234 err = mlx5_ib_init_congestion(dev); 3235 if (err) 3236 goto err_umrc; 3237 3238 dev->ib_active = true; 3239 3240 return dev; 3241 3242err_umrc: 3243 destroy_umrc_res(dev); 3244 3245err_dev: 3246 ib_unregister_device(&dev->ib_dev); 3247 3248err_q_cnt: 3249 mlx5_ib_dealloc_q_counters(dev); 3250 3251err_odp: 3252 mlx5_ib_odp_remove_one(dev); 3253 3254err_rsrc: 3255 destroy_dev_resources(&dev->devr); 3256 3257err_disable_roce: 3258 if (ll == IB_LINK_LAYER_ETHERNET) { 3259 mlx5_disable_roce(dev); 3260 mlx5_remove_roce_notifier(dev); 3261 } 3262 3263err_free_port: 3264 kfree(dev->port); 3265 3266err_dealloc: 3267 ib_dealloc_device((struct ib_device *)dev); 3268 3269 return NULL; 3270} 3271 3272static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context) 3273{ 3274 struct mlx5_ib_dev *dev = context; 3275 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1); 3276 3277 mlx5_ib_cleanup_congestion(dev); 3278 mlx5_remove_roce_notifier(dev); 3279 ib_unregister_device(&dev->ib_dev); 3280 mlx5_ib_dealloc_q_counters(dev); 3281 destroy_umrc_res(dev); 3282 mlx5_ib_odp_remove_one(dev); 3283 destroy_dev_resources(&dev->devr); 3284 if (ll == IB_LINK_LAYER_ETHERNET) 3285 mlx5_disable_roce(dev); 3286 kfree(dev->port); 3287 ib_dealloc_device(&dev->ib_dev); 3288} 3289 3290static struct mlx5_interface mlx5_ib_interface = { 3291 .add = mlx5_ib_add, 3292 .remove = mlx5_ib_remove, 3293 .event = mlx5_ib_event, 3294 .protocol = MLX5_INTERFACE_PROTOCOL_IB, 3295}; 3296 3297static int __init mlx5_ib_init(void) 3298{ 3299 int err; 3300 3301 err = mlx5_ib_odp_init(); 3302 if (err) 3303 return err; 3304 3305 err = mlx5_register_interface(&mlx5_ib_interface); 3306 if (err) 3307 goto clean_odp; 3308 3309 return err; 3310 3311clean_odp: 3312 mlx5_ib_odp_cleanup(); 3313 return err; 3314} 3315 3316static void __exit mlx5_ib_cleanup(void) 3317{ 3318 mlx5_unregister_interface(&mlx5_ib_interface); 3319 mlx5_ib_odp_cleanup(); 3320} 3321 3322static void 3323mlx5_ib_show_version(void __unused *arg) 3324{ 3325 3326 printf("%s", mlx5_version); 3327} 3328SYSINIT(mlx5_ib_show_version, SI_SUB_DRIVERS, SI_ORDER_ANY, mlx5_ib_show_version, NULL); 3329 3330module_init_order(mlx5_ib_init, SI_ORDER_THIRD); 3331module_exit_order(mlx5_ib_cleanup, SI_ORDER_THIRD); 3332