1/*-
2 * Copyright (c) 2017 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses.  You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 *     Redistribution and use in source and binary forms, with or
11 *     without modification, are permitted provided that the following
12 *     conditions are met:
13 *
14 *      - Redistributions of source code must retain the above
15 *        copyright notice, this list of conditions and the following
16 *        disclaimer.
17 *
18 *      - Redistributions in binary form must reproduce the above
19 *        copyright notice, this list of conditions and the following
20 *        disclaimer in the documentation and/or other materials
21 *        provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 * $FreeBSD: stable/11/sys/dev/mlx5/mlx5_fpga/conn.h 341572 2018-12-05 14:11:20Z slavash $
33 */
34
35#ifndef __MLX5_FPGA_CONN_H__
36#define __MLX5_FPGA_CONN_H__
37
38#include <dev/mlx5/cq.h>
39#include <dev/mlx5/qp.h>
40#include <dev/mlx5/mlx5_fpga/core.h>
41#include <dev/mlx5/mlx5_fpga/sdk.h>
42#include <dev/mlx5/mlx5_core/wq.h>
43#include <linux/interrupt.h>
44
45struct mlx5_fpga_conn {
46	struct mlx5_fpga_device *fdev;
47
48	void (*recv_cb)(void *cb_arg, struct mlx5_fpga_dma_buf *buf);
49	void *cb_arg;
50
51	/* FPGA QP */
52	u32 fpga_qpc[MLX5_ST_SZ_DW(fpga_qpc)];
53	u32 fpga_qpn;
54
55	/* CQ */
56	struct {
57		struct mlx5_cqwq wq;
58		struct mlx5_frag_wq_ctrl wq_ctrl;
59		struct mlx5_core_cq mcq;
60		struct tasklet_struct tasklet;
61	} cq;
62
63	/* QP */
64	struct {
65		bool active;
66		int sgid_index;
67		struct mlx5_wq_qp wq;
68		struct mlx5_wq_ctrl wq_ctrl;
69		struct mlx5_core_qp mqp;
70		struct {
71			spinlock_t lock; /* Protects all SQ state */
72			unsigned int pc;
73			unsigned int cc;
74			unsigned int size;
75			struct mlx5_fpga_dma_buf **bufs;
76			struct list_head backlog;
77		} sq;
78		struct {
79			unsigned int pc;
80			unsigned int cc;
81			unsigned int size;
82			struct mlx5_fpga_dma_buf **bufs;
83		} rq;
84	} qp;
85};
86
87int mlx5_fpga_conn_device_init(struct mlx5_fpga_device *fdev);
88void mlx5_fpga_conn_device_cleanup(struct mlx5_fpga_device *fdev);
89struct mlx5_fpga_conn *
90mlx5_fpga_conn_create(struct mlx5_fpga_device *fdev,
91		      struct mlx5_fpga_conn_attr *attr,
92		      enum mlx5_ifc_fpga_qp_type qp_type);
93void mlx5_fpga_conn_destroy(struct mlx5_fpga_conn *conn);
94int mlx5_fpga_conn_send(struct mlx5_fpga_conn *conn,
95			struct mlx5_fpga_dma_buf *buf);
96
97#endif /* __MLX5_FPGA_CONN_H__ */
98