brgphy.c revision 165343
1/*- 2 * Copyright (c) 2000 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/mii/brgphy.c 165343 2006-12-19 08:41:48Z oleg $"); 35 36/* 37 * Driver for the Broadcom BCR5400 1000baseTX PHY. Speed is always 38 * 1000mbps; all we need to negotiate here is full or half duplex. 39 */ 40 41#include <sys/param.h> 42#include <sys/systm.h> 43#include <sys/kernel.h> 44#include <sys/module.h> 45#include <sys/socket.h> 46#include <sys/bus.h> 47 48#include <net/if.h> 49#include <net/ethernet.h> 50#include <net/if_media.h> 51 52#include <dev/mii/mii.h> 53#include <dev/mii/miivar.h> 54#include "miidevs.h" 55 56#include <dev/mii/brgphyreg.h> 57#include <net/if_arp.h> 58#include <machine/bus.h> 59#include <dev/bge/if_bgereg.h> 60#include <dev/bce/if_bcereg.h> 61 62#include <dev/pci/pcireg.h> 63#include <dev/pci/pcivar.h> 64 65#include "miibus_if.h" 66 67static int brgphy_probe(device_t); 68static int brgphy_attach(device_t); 69 70static device_method_t brgphy_methods[] = { 71 /* device interface */ 72 DEVMETHOD(device_probe, brgphy_probe), 73 DEVMETHOD(device_attach, brgphy_attach), 74 DEVMETHOD(device_detach, mii_phy_detach), 75 DEVMETHOD(device_shutdown, bus_generic_shutdown), 76 { 0, 0 } 77}; 78 79static devclass_t brgphy_devclass; 80 81static driver_t brgphy_driver = { 82 "brgphy", 83 brgphy_methods, 84 sizeof(struct mii_softc) 85}; 86 87DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0); 88 89static int brgphy_service(struct mii_softc *, struct mii_data *, int); 90static void brgphy_status(struct mii_softc *); 91static int brgphy_mii_phy_auto(struct mii_softc *); 92static void brgphy_reset(struct mii_softc *); 93static void brgphy_loop(struct mii_softc *); 94static void bcm5401_load_dspcode(struct mii_softc *); 95static void bcm5411_load_dspcode(struct mii_softc *); 96static void bcm5703_load_dspcode(struct mii_softc *); 97static void bcm5750_load_dspcode(struct mii_softc *); 98static int brgphy_mii_model; 99 100static const struct mii_phydesc brgphys[] = { 101 MII_PHY_DESC(xxBROADCOM, BCM5400), 102 MII_PHY_DESC(xxBROADCOM, BCM5401), 103 MII_PHY_DESC(xxBROADCOM, BCM5411), 104 MII_PHY_DESC(xxBROADCOM, BCM5701), 105 MII_PHY_DESC(xxBROADCOM, BCM5703), 106 MII_PHY_DESC(xxBROADCOM, BCM5704), 107 MII_PHY_DESC(xxBROADCOM, BCM5705), 108 MII_PHY_DESC(xxBROADCOM, BCM5706C), 109 MII_PHY_DESC(xxBROADCOM, BCM5708C), 110 MII_PHY_DESC(xxBROADCOM, BCM5714), 111 MII_PHY_DESC(xxBROADCOM, BCM5750), 112 MII_PHY_DESC(xxBROADCOM, BCM5752), 113 MII_PHY_DESC(xxBROADCOM, BCM5754), 114 MII_PHY_DESC(xxBROADCOM, BCM5780), 115 MII_PHY_END 116}; 117 118static int 119brgphy_probe(device_t dev) 120{ 121 122 return (mii_phy_dev_probe(dev, brgphys, BUS_PROBE_DEFAULT)); 123} 124 125static int 126brgphy_attach(device_t dev) 127{ 128 struct mii_softc *sc; 129 struct mii_attach_args *ma; 130 struct mii_data *mii; 131 const char *sep = ""; 132 struct bge_softc *bge_sc = NULL; 133 struct bce_softc *bce_sc = NULL; 134 int fast_ether_only = FALSE; 135 136 sc = device_get_softc(dev); 137 ma = device_get_ivars(dev); 138 sc->mii_dev = device_get_parent(dev); 139 mii = device_get_softc(sc->mii_dev); 140 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); 141 142 sc->mii_inst = mii->mii_instance; 143 sc->mii_phy = ma->mii_phyno; 144 sc->mii_service = brgphy_service; 145 sc->mii_pdata = mii; 146 147 sc->mii_flags |= MIIF_NOISOLATE; 148 mii->mii_instance++; 149 150#define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 151#define PRINT(s) printf("%s%s", sep, s); sep = ", " 152 153 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst), 154 BMCR_ISO); 155#if 0 156 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), 157 BMCR_LOOP|BMCR_S100); 158#endif 159 160 brgphy_mii_model = MII_MODEL(ma->mii_id2); 161 brgphy_reset(sc); 162 163 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 164 sc->mii_capabilities &= ~BMSR_ANEG; 165 device_printf(dev, " "); 166 mii_add_media(sc); 167 168 /* Find the driver associated with this PHY. */ 169 if (strcmp(mii->mii_ifp->if_dname, "bge") == 0) { 170 bge_sc = mii->mii_ifp->if_softc; 171 } else if (strcmp(mii->mii_ifp->if_dname, "bce") == 0) { 172 bce_sc = mii->mii_ifp->if_softc; 173 } 174 175 /* The 590x chips are 10/100 only. */ 176 if (strcmp(mii->mii_ifp->if_dname, "bge") == 0 && 177 pci_get_vendor(bge_sc->bge_dev) == BCOM_VENDORID && 178 (pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901 || 179 pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901A2)) 180 fast_ether_only = TRUE; 181 182 if (fast_ether_only == FALSE) { 183 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0, 184 sc->mii_inst), BRGPHY_BMCR_FDX); 185 PRINT(", 1000baseTX"); 186 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 187 IFM_FDX, sc->mii_inst), 0); 188 PRINT("1000baseTX-FDX"); 189 sc->mii_anegticks = MII_ANEGTICKS_GIGE; 190 } else 191 sc->mii_anegticks = MII_ANEGTICKS; 192 193 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0); 194 PRINT("auto"); 195 196 printf("\n"); 197#undef ADD 198#undef PRINT 199 200 MIIBUS_MEDIAINIT(sc->mii_dev); 201 return (0); 202} 203 204static int 205brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 206{ 207 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 208 int reg, speed, gig; 209 210 switch (cmd) { 211 case MII_POLLSTAT: 212 /* If we're not polling our PHY instance, just return. */ 213 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 214 return (0); 215 break; 216 case MII_MEDIACHG: 217 /* 218 * If the media indicates a different PHY instance, 219 * isolate ourselves. 220 */ 221 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 222 reg = PHY_READ(sc, MII_BMCR); 223 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 224 return (0); 225 } 226 227 /* If the interface is not up, don't do anything. */ 228 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 229 break; 230 231 brgphy_reset(sc); /* XXX hardware bug work-around */ 232 233 switch (IFM_SUBTYPE(ife->ifm_media)) { 234 case IFM_AUTO: 235#ifdef foo 236 /* If we're already in auto mode, just return. */ 237 if (PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_AUTOEN) 238 return (0); 239#endif 240 (void) brgphy_mii_phy_auto(sc); 241 break; 242 case IFM_1000_T: 243 speed = BRGPHY_S1000; 244 goto setit; 245 case IFM_100_TX: 246 speed = BRGPHY_S100; 247 goto setit; 248 case IFM_10_T: 249 speed = BRGPHY_S10; 250setit: 251 brgphy_loop(sc); 252 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 253 speed |= BRGPHY_BMCR_FDX; 254 gig = BRGPHY_1000CTL_AFD; 255 } else { 256 gig = BRGPHY_1000CTL_AHD; 257 } 258 259 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0); 260 PHY_WRITE(sc, BRGPHY_MII_BMCR, speed); 261 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE); 262 263 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) 264 break; 265 266 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig); 267 PHY_WRITE(sc, BRGPHY_MII_BMCR, 268 speed|BRGPHY_BMCR_AUTOEN|BRGPHY_BMCR_STARTNEG); 269 270 if (brgphy_mii_model != MII_MODEL_xxBROADCOM_BCM5701) 271 break; 272 273 /* 274 * When setting the link manually, one side must 275 * be the master and the other the slave. However 276 * ifmedia doesn't give us a good way to specify 277 * this, so we fake it by using one of the LINK 278 * flags. If LINK0 is set, we program the PHY to 279 * be a master, otherwise it's a slave. 280 */ 281 if ((mii->mii_ifp->if_flags & IFF_LINK0)) { 282 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 283 gig|BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC); 284 } else { 285 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 286 gig|BRGPHY_1000CTL_MSE); 287 } 288 break; 289#ifdef foo 290 case IFM_NONE: 291 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN); 292 break; 293#endif 294 case IFM_100_T4: 295 default: 296 return (EINVAL); 297 } 298 break; 299 300 case MII_TICK: 301 /* If we're not currently selected, just return. */ 302 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 303 return (0); 304 305 /* Is the interface even up? */ 306 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 307 return (0); 308 309 /* Only used for autonegotiation. */ 310 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 311 sc->mii_ticks = 0; /* Reset autoneg timer. */ 312 break; 313 } 314 315 /* 316 * Check to see if we have link. If we do, we don't 317 * need to restart the autonegotiation process. 318 */ 319 if (PHY_READ(sc, BRGPHY_MII_AUXSTS) & BRGPHY_AUXSTS_LINK) { 320 sc->mii_ticks = 0; /* Reset autoneg timer. */ 321 break; 322 } 323 324 /* Announce link loss right after it happens. */ 325 if (sc->mii_ticks++ == 0) 326 break; 327 328 /* Only retry autonegotiation every mii_anegticks seconds. */ 329 if (sc->mii_ticks <= sc->mii_anegticks) 330 return (0); 331 332 sc->mii_ticks = 0; 333 brgphy_mii_phy_auto(sc); 334 break; 335 } 336 337 /* Update the media status. */ 338 brgphy_status(sc); 339 340 /* 341 * Callback if something changed. Note that we need to poke 342 * the DSP on the Broadcom PHYs if the media changes. 343 */ 344 if (sc->mii_media_active != mii->mii_media_active || 345 sc->mii_media_status != mii->mii_media_status || 346 cmd == MII_MEDIACHG) { 347 switch (brgphy_mii_model) { 348 case MII_MODEL_xxBROADCOM_BCM5400: 349 case MII_MODEL_xxBROADCOM_BCM5401: 350 bcm5401_load_dspcode(sc); 351 break; 352 case MII_MODEL_xxBROADCOM_BCM5411: 353 bcm5411_load_dspcode(sc); 354 break; 355 } 356 } 357 mii_phy_update(sc, cmd); 358 return (0); 359} 360 361static void 362brgphy_status(struct mii_softc *sc) 363{ 364 struct mii_data *mii = sc->mii_pdata; 365 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 366 int bmsr, bmcr; 367 368 mii->mii_media_status = IFM_AVALID; 369 mii->mii_media_active = IFM_ETHER; 370 371 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR); 372 if (PHY_READ(sc, BRGPHY_MII_AUXSTS) & BRGPHY_AUXSTS_LINK) 373 mii->mii_media_status |= IFM_ACTIVE; 374 375 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR); 376 377 if (bmcr & BRGPHY_BMCR_LOOP) 378 mii->mii_media_active |= IFM_LOOP; 379 380 if (bmcr & BRGPHY_BMCR_AUTOEN) { 381 if ((bmsr & BRGPHY_BMSR_ACOMP) == 0) { 382 /* Erg, still trying, I guess... */ 383 mii->mii_media_active |= IFM_NONE; 384 return; 385 } 386 387 switch (PHY_READ(sc, BRGPHY_MII_AUXSTS) & 388 BRGPHY_AUXSTS_AN_RES) { 389 case BRGPHY_RES_1000FD: 390 mii->mii_media_active |= IFM_1000_T | IFM_FDX; 391 break; 392 case BRGPHY_RES_1000HD: 393 mii->mii_media_active |= IFM_1000_T | IFM_HDX; 394 break; 395 case BRGPHY_RES_100FD: 396 mii->mii_media_active |= IFM_100_TX | IFM_FDX; 397 break; 398 case BRGPHY_RES_100T4: 399 mii->mii_media_active |= IFM_100_T4; 400 break; 401 case BRGPHY_RES_100HD: 402 mii->mii_media_active |= IFM_100_TX | IFM_HDX; 403 break; 404 case BRGPHY_RES_10FD: 405 mii->mii_media_active |= IFM_10_T | IFM_FDX; 406 break; 407 case BRGPHY_RES_10HD: 408 mii->mii_media_active |= IFM_10_T | IFM_HDX; 409 break; 410 default: 411 mii->mii_media_active |= IFM_NONE; 412 break; 413 } 414 return; 415 } 416 417 mii->mii_media_active = ife->ifm_media; 418} 419 420static int 421brgphy_mii_phy_auto(struct mii_softc *mii) 422{ 423 int ktcr = 0; 424 425 brgphy_loop(mii); 426 brgphy_reset(mii); 427 ktcr = BRGPHY_1000CTL_AFD|BRGPHY_1000CTL_AHD; 428 if (brgphy_mii_model == MII_MODEL_xxBROADCOM_BCM5701) 429 ktcr |= BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC; 430 PHY_WRITE(mii, BRGPHY_MII_1000CTL, ktcr); 431 ktcr = PHY_READ(mii, BRGPHY_MII_1000CTL); 432 DELAY(1000); 433 PHY_WRITE(mii, BRGPHY_MII_ANAR, 434 BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA); 435 DELAY(1000); 436 PHY_WRITE(mii, BRGPHY_MII_BMCR, 437 BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG); 438 PHY_WRITE(mii, BRGPHY_MII_IMR, 0xFF00); 439 return (EJUSTRETURN); 440} 441 442static void 443brgphy_loop(struct mii_softc *sc) 444{ 445 int i; 446 447 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP); 448 for (i = 0; i < 15000; i++) { 449 if (!(PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_LINK)) { 450#if 0 451 device_printf(sc->mii_dev, "looped %d\n", i); 452#endif 453 break; 454 } 455 DELAY(10); 456 } 457} 458 459/* Turn off tap power management on 5401. */ 460static void 461bcm5401_load_dspcode(struct mii_softc *sc) 462{ 463 static const struct { 464 int reg; 465 uint16_t val; 466 } dspcode[] = { 467 { BRGPHY_MII_AUXCTL, 0x0c20 }, 468 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 469 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 470 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 471 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 472 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 473 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 474 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 475 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 476 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 477 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 478 { 0, 0 }, 479 }; 480 int i; 481 482 for (i = 0; dspcode[i].reg != 0; i++) 483 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 484 DELAY(40); 485} 486 487static void 488bcm5411_load_dspcode(struct mii_softc *sc) 489{ 490 static const struct { 491 int reg; 492 uint16_t val; 493 } dspcode[] = { 494 { 0x1c, 0x8c23 }, 495 { 0x1c, 0x8ca3 }, 496 { 0x1c, 0x8c23 }, 497 { 0, 0 }, 498 }; 499 int i; 500 501 for (i = 0; dspcode[i].reg != 0; i++) 502 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 503} 504 505static void 506bcm5703_load_dspcode(struct mii_softc *sc) 507{ 508 static const struct { 509 int reg; 510 uint16_t val; 511 } dspcode[] = { 512 { BRGPHY_MII_AUXCTL, 0x0c00 }, 513 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 514 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 515 { 0, 0 }, 516 }; 517 int i; 518 519 for (i = 0; dspcode[i].reg != 0; i++) 520 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 521} 522 523static void 524bcm5704_load_dspcode(struct mii_softc *sc) 525{ 526 static const struct { 527 int reg; 528 u_int16_t val; 529 } dspcode[] = { 530 { 0x1c, 0x8d68 }, 531 { 0x1c, 0x8d68 }, 532 { 0, 0 }, 533 }; 534 int i; 535 536 for (i = 0; dspcode[i].reg != 0; i++) 537 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 538} 539 540static void 541bcm5750_load_dspcode(struct mii_softc *sc) 542{ 543 static const struct { 544 int reg; 545 u_int16_t val; 546 } dspcode[] = { 547 { 0x18, 0x0c00 }, 548 { 0x17, 0x000a }, 549 { 0x15, 0x310b }, 550 { 0x17, 0x201f }, 551 { 0x15, 0x9506 }, 552 { 0x17, 0x401f }, 553 { 0x15, 0x14e2 }, 554 { 0x18, 0x0400 }, 555 { 0, 0 }, 556 }; 557 int i; 558 559 for (i = 0; dspcode[i].reg != 0; i++) 560 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 561} 562 563static void 564brgphy_reset(struct mii_softc *sc) 565{ 566 u_int32_t val; 567 struct ifnet *ifp; 568 struct bge_softc *bge_sc = NULL; 569 struct bce_softc *bce_sc = NULL; 570 571 mii_phy_reset(sc); 572 573 switch (brgphy_mii_model) { 574 case MII_MODEL_xxBROADCOM_BCM5400: 575 case MII_MODEL_xxBROADCOM_BCM5401: 576 bcm5401_load_dspcode(sc); 577 break; 578 case MII_MODEL_xxBROADCOM_BCM5411: 579 bcm5411_load_dspcode(sc); 580 break; 581 case MII_MODEL_xxBROADCOM_BCM5703: 582 bcm5703_load_dspcode(sc); 583 break; 584 case MII_MODEL_xxBROADCOM_BCM5704: 585 bcm5704_load_dspcode(sc); 586 break; 587 case MII_MODEL_xxBROADCOM_BCM5750: 588 case MII_MODEL_xxBROADCOM_BCM5752: 589 case MII_MODEL_xxBROADCOM_BCM5714: 590 case MII_MODEL_xxBROADCOM_BCM5780: 591 case MII_MODEL_xxBROADCOM_BCM5706C: 592 case MII_MODEL_xxBROADCOM_BCM5708C: 593 bcm5750_load_dspcode(sc); 594 break; 595 } 596 597 ifp = sc->mii_pdata->mii_ifp; 598 599 /* Find the driver associated with this PHY. */ 600 if (strcmp(ifp->if_dname, "bge") == 0) { 601 bge_sc = ifp->if_softc; 602 } else if (strcmp(ifp->if_dname, "bce") == 0) { 603 bce_sc = ifp->if_softc; 604 } 605 606 /* Handle any NetXtreme/bge workarounds. */ 607 if (bge_sc) { 608 /* 609 * Don't enable Ethernet@WireSpeed for the 5700 or the 610 * 5705 A1 and A2 chips. Make sure we only do this test 611 * on "bge" NICs, since other drivers may use this same 612 * PHY subdriver. 613 */ 614 if (bge_sc->bge_asicrev == BGE_ASICREV_BCM5700 || 615 bge_sc->bge_chipid == BGE_CHIPID_BCM5705_A1 || 616 bge_sc->bge_chipid == BGE_CHIPID_BCM5705_A2) 617 return; 618 619 /* Enable Ethernet@WireSpeed. */ 620 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 621 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 622 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4)); 623 624 /* Enable Link LED on Dell boxes */ 625 if (bge_sc->bge_flags & BGE_FLAG_NO3LED) { 626 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 627 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) & 628 ~BRGPHY_PHY_EXTCTL_3_LED); 629 } 630 } else if (bce_sc) { 631 /* Set or clear jumbo frame settings in the PHY. */ 632 if (ifp->if_mtu > ETHER_MAX_LEN) { 633 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 634 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 635 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 636 val | BRGPHY_AUXCTL_LONG_PKT); 637 638 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 639 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 640 val | BRGPHY_PHY_EXTCTL_HIGH_LA); 641 } else { 642 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 643 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 644 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 645 val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7)); 646 647 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 648 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 649 val & ~BRGPHY_PHY_EXTCTL_HIGH_LA); 650 } 651 652 /* Enable Ethernet@Wirespeed */ 653 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 654 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 655 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, (val | (1 << 15) | (1 << 4))); 656 } 657} 658