1/*- 2 * Copyright (c) 2000 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: stable/11/sys/dev/mii/brgphy.c 359843 2020-04-13 00:50:35Z jhibbits $"); 35 36/* 37 * Driver for the Broadcom BCM54xx/57xx 1000baseTX PHY. 38 */ 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/kernel.h> 43#include <sys/module.h> 44#include <sys/socket.h> 45#include <sys/bus.h> 46#include <sys/taskqueue.h> 47 48#include <net/if.h> 49#include <net/if_var.h> 50#include <net/ethernet.h> 51#include <net/if_media.h> 52 53#include <dev/mii/mii.h> 54#include <dev/mii/miivar.h> 55#include "miidevs.h" 56 57#include <dev/mii/brgphyreg.h> 58#include <net/if_arp.h> 59#include <machine/bus.h> 60#include <dev/bge/if_bgereg.h> 61#include <dev/bce/if_bcereg.h> 62 63#include <dev/pci/pcireg.h> 64#include <dev/pci/pcivar.h> 65 66#include "miibus_if.h" 67 68static int brgphy_probe(device_t); 69static int brgphy_attach(device_t); 70 71struct brgphy_softc { 72 struct mii_softc mii_sc; 73 int serdes_flags; /* Keeps track of the serdes type used */ 74#define BRGPHY_5706S 0x0001 75#define BRGPHY_5708S 0x0002 76#define BRGPHY_NOANWAIT 0x0004 77#define BRGPHY_5709S 0x0008 78 int bce_phy_flags; /* PHY flags transferred from the MAC driver */ 79}; 80 81static device_method_t brgphy_methods[] = { 82 /* device interface */ 83 DEVMETHOD(device_probe, brgphy_probe), 84 DEVMETHOD(device_attach, brgphy_attach), 85 DEVMETHOD(device_detach, mii_phy_detach), 86 DEVMETHOD(device_shutdown, bus_generic_shutdown), 87 DEVMETHOD_END 88}; 89 90static devclass_t brgphy_devclass; 91 92static driver_t brgphy_driver = { 93 "brgphy", 94 brgphy_methods, 95 sizeof(struct brgphy_softc) 96}; 97 98DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0); 99 100static int brgphy_service(struct mii_softc *, struct mii_data *, int); 101static void brgphy_setmedia(struct mii_softc *, int); 102static void brgphy_status(struct mii_softc *); 103static void brgphy_mii_phy_auto(struct mii_softc *, int); 104static void brgphy_reset(struct mii_softc *); 105static void brgphy_enable_loopback(struct mii_softc *); 106static void bcm5401_load_dspcode(struct mii_softc *); 107static void bcm5411_load_dspcode(struct mii_softc *); 108static void bcm54k2_load_dspcode(struct mii_softc *); 109static void brgphy_fixup_5704_a0_bug(struct mii_softc *); 110static void brgphy_fixup_adc_bug(struct mii_softc *); 111static void brgphy_fixup_adjust_trim(struct mii_softc *); 112static void brgphy_fixup_ber_bug(struct mii_softc *); 113static void brgphy_fixup_crc_bug(struct mii_softc *); 114static void brgphy_fixup_jitter_bug(struct mii_softc *); 115static void brgphy_ethernet_wirespeed(struct mii_softc *); 116static void brgphy_jumbo_settings(struct mii_softc *, u_long); 117 118static const struct mii_phydesc brgphys[] = { 119 MII_PHY_DESC(BROADCOM, BCM5400), 120 MII_PHY_DESC(BROADCOM, BCM5401), 121 MII_PHY_DESC(BROADCOM, BCM5402), 122 MII_PHY_DESC(BROADCOM, BCM5411), 123 MII_PHY_DESC(BROADCOM, BCM5404), 124 MII_PHY_DESC(BROADCOM, BCM5424), 125 MII_PHY_DESC(BROADCOM, BCM54K2), 126 MII_PHY_DESC(BROADCOM, BCM5701), 127 MII_PHY_DESC(BROADCOM, BCM5703), 128 MII_PHY_DESC(BROADCOM, BCM5704), 129 MII_PHY_DESC(BROADCOM, BCM5705), 130 MII_PHY_DESC(BROADCOM, BCM5706), 131 MII_PHY_DESC(BROADCOM, BCM5714), 132 MII_PHY_DESC(BROADCOM, BCM5421), 133 MII_PHY_DESC(BROADCOM, BCM5750), 134 MII_PHY_DESC(BROADCOM, BCM5752), 135 MII_PHY_DESC(BROADCOM, BCM5780), 136 MII_PHY_DESC(BROADCOM, BCM5708C), 137 MII_PHY_DESC(BROADCOM, BCM5466), 138 MII_PHY_DESC(BROADCOM2, BCM5478), 139 MII_PHY_DESC(BROADCOM2, BCM5488), 140 MII_PHY_DESC(BROADCOM2, BCM5482), 141 MII_PHY_DESC(BROADCOM2, BCM5708S), 142 MII_PHY_DESC(BROADCOM2, BCM5709C), 143 MII_PHY_DESC(BROADCOM2, BCM5709S), 144 MII_PHY_DESC(BROADCOM2, BCM5709CAX), 145 MII_PHY_DESC(BROADCOM2, BCM5722), 146 MII_PHY_DESC(BROADCOM2, BCM5755), 147 MII_PHY_DESC(BROADCOM2, BCM5754), 148 MII_PHY_DESC(BROADCOM2, BCM5761), 149 MII_PHY_DESC(BROADCOM2, BCM5784), 150#ifdef notyet /* better handled by ukphy(4) until WARs are implemented */ 151 MII_PHY_DESC(BROADCOM2, BCM5785), 152#endif 153 MII_PHY_DESC(BROADCOM3, BCM54618SE), 154 MII_PHY_DESC(BROADCOM3, BCM5717C), 155 MII_PHY_DESC(BROADCOM3, BCM5719C), 156 MII_PHY_DESC(BROADCOM3, BCM5720C), 157 MII_PHY_DESC(BROADCOM3, BCM57765), 158 MII_PHY_DESC(BROADCOM3, BCM57780), 159 MII_PHY_DESC(BROADCOM4, BCM5725C), 160 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5906), 161 MII_PHY_END 162}; 163 164static const struct mii_phy_funcs brgphy_funcs = { 165 brgphy_service, 166 brgphy_status, 167 brgphy_reset 168}; 169 170static const struct hs21_type { 171 const uint32_t id; 172 const char *prod; 173} hs21_type_lists[] = { 174 { 0x57081021, "IBM eServer BladeCenter HS21" }, 175 { 0x57081011, "IBM eServer BladeCenter HS21 -[8853PAU]-" }, 176}; 177 178static int 179detect_hs21(struct bce_softc *bce_sc) 180{ 181 char *sysenv; 182 int found, i; 183 184 found = 0; 185 sysenv = kern_getenv("smbios.system.product"); 186 if (sysenv == NULL) 187 return (found); 188 for (i = 0; i < nitems(hs21_type_lists); i++) { 189 if (bce_sc->bce_chipid == hs21_type_lists[i].id && 190 strncmp(sysenv, hs21_type_lists[i].prod, 191 strlen(hs21_type_lists[i].prod)) == 0) { 192 found++; 193 break; 194 } 195 } 196 freeenv(sysenv); 197 return (found); 198} 199 200/* Search for our PHY in the list of known PHYs */ 201static int 202brgphy_probe(device_t dev) 203{ 204 205 return (mii_phy_dev_probe(dev, brgphys, BUS_PROBE_DEFAULT)); 206} 207 208/* Attach the PHY to the MII bus */ 209static int 210brgphy_attach(device_t dev) 211{ 212 struct brgphy_softc *bsc; 213 struct bge_softc *bge_sc = NULL; 214 struct bce_softc *bce_sc = NULL; 215 struct mii_softc *sc; 216 217 bsc = device_get_softc(dev); 218 sc = &bsc->mii_sc; 219 220 mii_phy_dev_attach(dev, MIIF_NOISOLATE | MIIF_NOMANPAUSE, 221 &brgphy_funcs, 0); 222 223 bsc->serdes_flags = 0; 224 225 /* Find the MAC driver associated with this PHY. */ 226 if (mii_dev_mac_match(dev, "bge")) 227 bge_sc = mii_dev_mac_softc(dev); 228 else if (mii_dev_mac_match(dev, "bce")) 229 bce_sc = mii_dev_mac_softc(dev); 230 231 /* Handle any special cases based on the PHY ID */ 232 switch (sc->mii_mpd_oui) { 233 case MII_OUI_BROADCOM: 234 switch (sc->mii_mpd_model) { 235 case MII_MODEL_BROADCOM_BCM5706: 236 case MII_MODEL_BROADCOM_BCM5714: 237 /* 238 * The 5464 PHY used in the 5706 supports both copper 239 * and fiber interfaces over GMII. Need to check the 240 * shadow registers to see which mode is actually 241 * in effect, and therefore whether we have 5706C or 242 * 5706S. 243 */ 244 PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C, 245 BRGPHY_SHADOW_1C_MODE_CTRL); 246 if (PHY_READ(sc, BRGPHY_MII_SHADOW_1C) & 247 BRGPHY_SHADOW_1C_ENA_1000X) { 248 bsc->serdes_flags |= BRGPHY_5706S; 249 sc->mii_flags |= MIIF_HAVEFIBER; 250 } 251 break; 252 } 253 break; 254 case MII_OUI_BROADCOM2: 255 switch (sc->mii_mpd_model) { 256 case MII_MODEL_BROADCOM2_BCM5708S: 257 bsc->serdes_flags |= BRGPHY_5708S; 258 sc->mii_flags |= MIIF_HAVEFIBER; 259 break; 260 case MII_MODEL_BROADCOM2_BCM5709S: 261 /* 262 * XXX 263 * 5720S and 5709S shares the same PHY id. 264 * Assume 5720S PHY if parent device is bge(4). 265 */ 266 if (bge_sc != NULL) 267 bsc->serdes_flags |= BRGPHY_5708S; 268 else 269 bsc->serdes_flags |= BRGPHY_5709S; 270 sc->mii_flags |= MIIF_HAVEFIBER; 271 break; 272 } 273 break; 274 } 275 276 PHY_RESET(sc); 277 278 /* Read the PHY's capabilities. */ 279 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & sc->mii_capmask; 280 if (sc->mii_capabilities & BMSR_EXTSTAT) 281 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 282 device_printf(dev, " "); 283 284 /* Add the supported media types */ 285 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 286 mii_phy_add_media(sc); 287 printf("\n"); 288 } else { 289 sc->mii_anegticks = MII_ANEGTICKS_GIGE; 290 ifmedia_add(&sc->mii_pdata->mii_media, 291 IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, sc->mii_inst), 292 0, NULL); 293 printf("1000baseSX-FDX, "); 294 /* 295 * 2.5G support is a software enabled feature 296 * on the 5708S and 5709S. 297 */ 298 if (bce_sc && (bce_sc->bce_phy_flags & 299 BCE_PHY_2_5G_CAPABLE_FLAG)) { 300 ifmedia_add(&sc->mii_pdata->mii_media, 301 IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX, IFM_FDX, 302 sc->mii_inst), 0, NULL); 303 printf("2500baseSX-FDX, "); 304 } else if ((bsc->serdes_flags & BRGPHY_5708S) && bce_sc && 305 (detect_hs21(bce_sc) != 0)) { 306 /* 307 * There appears to be certain silicon revision 308 * in IBM HS21 blades that is having issues with 309 * this driver wating for the auto-negotiation to 310 * complete. This happens with a specific chip id 311 * only and when the 1000baseSX-FDX is the only 312 * mode. Workaround this issue since it's unlikely 313 * to be ever addressed. 314 */ 315 printf("auto-neg workaround, "); 316 bsc->serdes_flags |= BRGPHY_NOANWAIT; 317 } 318 ifmedia_add(&sc->mii_pdata->mii_media, IFM_MAKEWORD(IFM_ETHER, 319 IFM_AUTO, 0, sc->mii_inst), 0, NULL); 320 printf("auto\n"); 321 } 322 323 MIIBUS_MEDIAINIT(sc->mii_dev); 324 return (0); 325} 326 327static int 328brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 329{ 330 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 331 int val; 332 333 switch (cmd) { 334 case MII_POLLSTAT: 335 break; 336 case MII_MEDIACHG: 337 /* Todo: Why is this here? Is it really needed? */ 338 PHY_RESET(sc); /* XXX hardware bug work-around */ 339 340 switch (IFM_SUBTYPE(ife->ifm_media)) { 341 case IFM_AUTO: 342 brgphy_mii_phy_auto(sc, ife->ifm_media); 343 break; 344 case IFM_2500_SX: 345 case IFM_1000_SX: 346 case IFM_1000_T: 347 case IFM_100_TX: 348 case IFM_10_T: 349 brgphy_setmedia(sc, ife->ifm_media); 350 break; 351 default: 352 return (EINVAL); 353 } 354 break; 355 case MII_TICK: 356 /* Bail if autoneg isn't in process. */ 357 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 358 sc->mii_ticks = 0; 359 break; 360 } 361 362 /* 363 * Check to see if we have link. If we do, we don't 364 * need to restart the autonegotiation process. 365 */ 366 val = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 367 if (val & BMSR_LINK) { 368 sc->mii_ticks = 0; /* Reset autoneg timer. */ 369 break; 370 } 371 372 /* Announce link loss right after it happens. */ 373 if (sc->mii_ticks++ == 0) 374 break; 375 376 /* Only retry autonegotiation every mii_anegticks seconds. */ 377 if (sc->mii_ticks <= sc->mii_anegticks) 378 break; 379 380 381 /* Retry autonegotiation */ 382 sc->mii_ticks = 0; 383 brgphy_mii_phy_auto(sc, ife->ifm_media); 384 break; 385 } 386 387 /* Update the media status. */ 388 PHY_STATUS(sc); 389 390 /* 391 * Callback if something changed. Note that we need to poke 392 * the DSP on the Broadcom PHYs if the media changes. 393 */ 394 if (sc->mii_media_active != mii->mii_media_active || 395 sc->mii_media_status != mii->mii_media_status || 396 cmd == MII_MEDIACHG) { 397 switch (sc->mii_mpd_oui) { 398 case MII_OUI_BROADCOM: 399 switch (sc->mii_mpd_model) { 400 case MII_MODEL_BROADCOM_BCM5400: 401 bcm5401_load_dspcode(sc); 402 break; 403 case MII_MODEL_BROADCOM_BCM5401: 404 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3) 405 bcm5401_load_dspcode(sc); 406 break; 407 case MII_MODEL_BROADCOM_BCM5411: 408 bcm5411_load_dspcode(sc); 409 break; 410 case MII_MODEL_BROADCOM_BCM54K2: 411 bcm54k2_load_dspcode(sc); 412 break; 413 } 414 break; 415 } 416 } 417 mii_phy_update(sc, cmd); 418 return (0); 419} 420 421/****************************************************************************/ 422/* Sets the PHY link speed. */ 423/* */ 424/* Returns: */ 425/* None */ 426/****************************************************************************/ 427static void 428brgphy_setmedia(struct mii_softc *sc, int media) 429{ 430 int bmcr = 0, gig; 431 432 switch (IFM_SUBTYPE(media)) { 433 case IFM_2500_SX: 434 break; 435 case IFM_1000_SX: 436 case IFM_1000_T: 437 bmcr = BRGPHY_S1000; 438 break; 439 case IFM_100_TX: 440 bmcr = BRGPHY_S100; 441 break; 442 case IFM_10_T: 443 default: 444 bmcr = BRGPHY_S10; 445 break; 446 } 447 448 if ((media & IFM_FDX) != 0) { 449 bmcr |= BRGPHY_BMCR_FDX; 450 gig = BRGPHY_1000CTL_AFD; 451 } else { 452 gig = BRGPHY_1000CTL_AHD; 453 } 454 455 /* Force loopback to disconnect PHY from Ethernet medium. */ 456 brgphy_enable_loopback(sc); 457 458 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0); 459 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE); 460 461 if (IFM_SUBTYPE(media) != IFM_1000_T && 462 IFM_SUBTYPE(media) != IFM_1000_SX) { 463 PHY_WRITE(sc, BRGPHY_MII_BMCR, bmcr); 464 return; 465 } 466 467 if (IFM_SUBTYPE(media) == IFM_1000_T) { 468 gig |= BRGPHY_1000CTL_MSE; 469 if ((media & IFM_ETH_MASTER) != 0) 470 gig |= BRGPHY_1000CTL_MSC; 471 } 472 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig); 473 PHY_WRITE(sc, BRGPHY_MII_BMCR, 474 bmcr | BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG); 475} 476 477/****************************************************************************/ 478/* Set the media status based on the PHY settings. */ 479/* */ 480/* Returns: */ 481/* None */ 482/****************************************************************************/ 483static void 484brgphy_status(struct mii_softc *sc) 485{ 486 struct brgphy_softc *bsc = (struct brgphy_softc *)sc; 487 struct mii_data *mii = sc->mii_pdata; 488 int aux, bmcr, bmsr, val, xstat; 489 u_int flowstat; 490 491 mii->mii_media_status = IFM_AVALID; 492 mii->mii_media_active = IFM_ETHER; 493 494 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR) | PHY_READ(sc, BRGPHY_MII_BMSR); 495 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR); 496 497 if (bmcr & BRGPHY_BMCR_LOOP) { 498 mii->mii_media_active |= IFM_LOOP; 499 } 500 501 if ((bmcr & BRGPHY_BMCR_AUTOEN) && 502 (bmsr & BRGPHY_BMSR_ACOMP) == 0 && 503 (bsc->serdes_flags & BRGPHY_NOANWAIT) == 0) { 504 /* Erg, still trying, I guess... */ 505 mii->mii_media_active |= IFM_NONE; 506 return; 507 } 508 509 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 510 /* 511 * NB: reading the ANAR, ANLPAR or 1000STS after the AUXSTS 512 * wedges at least the PHY of BCM5704 (but not others). 513 */ 514 flowstat = mii_phy_flowstatus(sc); 515 xstat = PHY_READ(sc, BRGPHY_MII_1000STS); 516 aux = PHY_READ(sc, BRGPHY_MII_AUXSTS); 517 518 /* If copper link is up, get the negotiated speed/duplex. */ 519 if (aux & BRGPHY_AUXSTS_LINK) { 520 mii->mii_media_status |= IFM_ACTIVE; 521 switch (aux & BRGPHY_AUXSTS_AN_RES) { 522 case BRGPHY_RES_1000FD: 523 mii->mii_media_active |= IFM_1000_T | IFM_FDX; break; 524 case BRGPHY_RES_1000HD: 525 mii->mii_media_active |= IFM_1000_T | IFM_HDX; break; 526 case BRGPHY_RES_100FD: 527 mii->mii_media_active |= IFM_100_TX | IFM_FDX; break; 528 case BRGPHY_RES_100T4: 529 mii->mii_media_active |= IFM_100_T4; break; 530 case BRGPHY_RES_100HD: 531 mii->mii_media_active |= IFM_100_TX | IFM_HDX; break; 532 case BRGPHY_RES_10FD: 533 mii->mii_media_active |= IFM_10_T | IFM_FDX; break; 534 case BRGPHY_RES_10HD: 535 mii->mii_media_active |= IFM_10_T | IFM_HDX; break; 536 default: 537 mii->mii_media_active |= IFM_NONE; break; 538 } 539 540 if ((mii->mii_media_active & IFM_FDX) != 0) 541 mii->mii_media_active |= flowstat; 542 543 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T && 544 (xstat & BRGPHY_1000STS_MSR) != 0) 545 mii->mii_media_active |= IFM_ETH_MASTER; 546 } 547 } else { 548 /* Todo: Add support for flow control. */ 549 /* If serdes link is up, get the negotiated speed/duplex. */ 550 if (bmsr & BRGPHY_BMSR_LINK) { 551 mii->mii_media_status |= IFM_ACTIVE; 552 } 553 554 /* Check the link speed/duplex based on the PHY type. */ 555 if (bsc->serdes_flags & BRGPHY_5706S) { 556 mii->mii_media_active |= IFM_1000_SX; 557 558 /* If autoneg enabled, read negotiated duplex settings */ 559 if (bmcr & BRGPHY_BMCR_AUTOEN) { 560 val = PHY_READ(sc, BRGPHY_SERDES_ANAR) & PHY_READ(sc, BRGPHY_SERDES_ANLPAR); 561 if (val & BRGPHY_SERDES_ANAR_FDX) 562 mii->mii_media_active |= IFM_FDX; 563 else 564 mii->mii_media_active |= IFM_HDX; 565 } 566 } else if (bsc->serdes_flags & BRGPHY_5708S) { 567 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); 568 xstat = PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1); 569 570 /* Check for MRBE auto-negotiated speed results. */ 571 switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) { 572 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10: 573 mii->mii_media_active |= IFM_10_FL; break; 574 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100: 575 mii->mii_media_active |= IFM_100_FX; break; 576 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G: 577 mii->mii_media_active |= IFM_1000_SX; break; 578 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G: 579 mii->mii_media_active |= IFM_2500_SX; break; 580 } 581 582 /* Check for MRBE auto-negotiated duplex results. */ 583 if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX) 584 mii->mii_media_active |= IFM_FDX; 585 else 586 mii->mii_media_active |= IFM_HDX; 587 } else if (bsc->serdes_flags & BRGPHY_5709S) { 588 /* Select GP Status Block of the AN MMD, get autoneg results. */ 589 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_GP_STATUS); 590 xstat = PHY_READ(sc, BRGPHY_GP_STATUS_TOP_ANEG_STATUS); 591 592 /* Restore IEEE0 block (assumed in all brgphy(4) code). */ 593 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 594 595 /* Check for MRBE auto-negotiated speed results. */ 596 switch (xstat & BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK) { 597 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10: 598 mii->mii_media_active |= IFM_10_FL; break; 599 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100: 600 mii->mii_media_active |= IFM_100_FX; break; 601 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G: 602 mii->mii_media_active |= IFM_1000_SX; break; 603 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G: 604 mii->mii_media_active |= IFM_2500_SX; break; 605 } 606 607 /* Check for MRBE auto-negotiated duplex results. */ 608 if (xstat & BRGPHY_GP_STATUS_TOP_ANEG_FDX) 609 mii->mii_media_active |= IFM_FDX; 610 else 611 mii->mii_media_active |= IFM_HDX; 612 } 613 } 614} 615 616static void 617brgphy_mii_phy_auto(struct mii_softc *sc, int media) 618{ 619 int anar, ktcr = 0; 620 621 PHY_RESET(sc); 622 623 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 624 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 625 if ((media & IFM_FLOW) != 0 || 626 (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 627 anar |= BRGPHY_ANAR_PC | BRGPHY_ANAR_ASP; 628 PHY_WRITE(sc, BRGPHY_MII_ANAR, anar); 629 ktcr = BRGPHY_1000CTL_AFD | BRGPHY_1000CTL_AHD; 630 if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5701) 631 ktcr |= BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC; 632 PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr); 633 PHY_READ(sc, BRGPHY_MII_1000CTL); 634 } else { 635 anar = BRGPHY_SERDES_ANAR_FDX | BRGPHY_SERDES_ANAR_HDX; 636 if ((media & IFM_FLOW) != 0 || 637 (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 638 anar |= BRGPHY_SERDES_ANAR_BOTH_PAUSE; 639 PHY_WRITE(sc, BRGPHY_SERDES_ANAR, anar); 640 } 641 642 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_AUTOEN | 643 BRGPHY_BMCR_STARTNEG); 644 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00); 645} 646 647/* Enable loopback to force the link down. */ 648static void 649brgphy_enable_loopback(struct mii_softc *sc) 650{ 651 int i; 652 653 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP); 654 for (i = 0; i < 15000; i++) { 655 if (!(PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_LINK)) 656 break; 657 DELAY(10); 658 } 659} 660 661/* Turn off tap power management on 5401. */ 662static void 663bcm5401_load_dspcode(struct mii_softc *sc) 664{ 665 static const struct { 666 int reg; 667 uint16_t val; 668 } dspcode[] = { 669 { BRGPHY_MII_AUXCTL, 0x0c20 }, 670 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 671 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 672 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 673 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 674 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 675 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 676 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 677 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 678 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 679 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 680 { 0, 0 }, 681 }; 682 int i; 683 684 for (i = 0; dspcode[i].reg != 0; i++) 685 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 686 DELAY(40); 687} 688 689static void 690bcm5411_load_dspcode(struct mii_softc *sc) 691{ 692 static const struct { 693 int reg; 694 uint16_t val; 695 } dspcode[] = { 696 { 0x1c, 0x8c23 }, 697 { 0x1c, 0x8ca3 }, 698 { 0x1c, 0x8c23 }, 699 { 0, 0 }, 700 }; 701 int i; 702 703 for (i = 0; dspcode[i].reg != 0; i++) 704 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 705} 706 707void 708bcm54k2_load_dspcode(struct mii_softc *sc) 709{ 710 static const struct { 711 int reg; 712 uint16_t val; 713 } dspcode[] = { 714 { 4, 0x01e1 }, 715 { 9, 0x0300 }, 716 { 0, 0 }, 717 }; 718 int i; 719 720 for (i = 0; dspcode[i].reg != 0; i++) 721 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 722 723} 724 725static void 726brgphy_fixup_5704_a0_bug(struct mii_softc *sc) 727{ 728 static const struct { 729 int reg; 730 uint16_t val; 731 } dspcode[] = { 732 { 0x1c, 0x8d68 }, 733 { 0x1c, 0x8d68 }, 734 { 0, 0 }, 735 }; 736 int i; 737 738 for (i = 0; dspcode[i].reg != 0; i++) 739 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 740} 741 742static void 743brgphy_fixup_adc_bug(struct mii_softc *sc) 744{ 745 static const struct { 746 int reg; 747 uint16_t val; 748 } dspcode[] = { 749 { BRGPHY_MII_AUXCTL, 0x0c00 }, 750 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 751 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 752 { 0, 0 }, 753 }; 754 int i; 755 756 for (i = 0; dspcode[i].reg != 0; i++) 757 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 758} 759 760static void 761brgphy_fixup_adjust_trim(struct mii_softc *sc) 762{ 763 static const struct { 764 int reg; 765 uint16_t val; 766 } dspcode[] = { 767 { BRGPHY_MII_AUXCTL, 0x0c00 }, 768 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 769 { BRGPHY_MII_DSP_RW_PORT, 0x110b }, 770 { BRGPHY_MII_TEST1, 0x0014 }, 771 { BRGPHY_MII_AUXCTL, 0x0400 }, 772 { 0, 0 }, 773 }; 774 int i; 775 776 for (i = 0; dspcode[i].reg != 0; i++) 777 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 778} 779 780static void 781brgphy_fixup_ber_bug(struct mii_softc *sc) 782{ 783 static const struct { 784 int reg; 785 uint16_t val; 786 } dspcode[] = { 787 { BRGPHY_MII_AUXCTL, 0x0c00 }, 788 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 789 { BRGPHY_MII_DSP_RW_PORT, 0x310b }, 790 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 791 { BRGPHY_MII_DSP_RW_PORT, 0x9506 }, 792 { BRGPHY_MII_DSP_ADDR_REG, 0x401f }, 793 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 }, 794 { BRGPHY_MII_AUXCTL, 0x0400 }, 795 { 0, 0 }, 796 }; 797 int i; 798 799 for (i = 0; dspcode[i].reg != 0; i++) 800 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 801} 802 803static void 804brgphy_fixup_crc_bug(struct mii_softc *sc) 805{ 806 static const struct { 807 int reg; 808 uint16_t val; 809 } dspcode[] = { 810 { BRGPHY_MII_DSP_RW_PORT, 0x0a75 }, 811 { 0x1c, 0x8c68 }, 812 { 0x1c, 0x8d68 }, 813 { 0x1c, 0x8c68 }, 814 { 0, 0 }, 815 }; 816 int i; 817 818 for (i = 0; dspcode[i].reg != 0; i++) 819 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 820} 821 822static void 823brgphy_fixup_jitter_bug(struct mii_softc *sc) 824{ 825 static const struct { 826 int reg; 827 uint16_t val; 828 } dspcode[] = { 829 { BRGPHY_MII_AUXCTL, 0x0c00 }, 830 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 831 { BRGPHY_MII_DSP_RW_PORT, 0x010b }, 832 { BRGPHY_MII_AUXCTL, 0x0400 }, 833 { 0, 0 }, 834 }; 835 int i; 836 837 for (i = 0; dspcode[i].reg != 0; i++) 838 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 839} 840 841static void 842brgphy_fixup_disable_early_dac(struct mii_softc *sc) 843{ 844 uint32_t val; 845 846 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08); 847 val = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT); 848 val &= ~(1 << 8); 849 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val); 850 851} 852 853static void 854brgphy_ethernet_wirespeed(struct mii_softc *sc) 855{ 856 uint32_t val; 857 858 /* Enable Ethernet@WireSpeed. */ 859 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 860 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 861 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4)); 862} 863 864static void 865brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu) 866{ 867 uint32_t val; 868 869 /* Set or clear jumbo frame settings in the PHY. */ 870 if (mtu > ETHER_MAX_LEN) { 871 if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5401) { 872 /* BCM5401 PHY cannot read-modify-write. */ 873 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20); 874 } else { 875 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 876 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 877 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 878 val | BRGPHY_AUXCTL_LONG_PKT); 879 } 880 881 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 882 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 883 val | BRGPHY_PHY_EXTCTL_HIGH_LA); 884 } else { 885 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 886 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 887 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 888 val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7)); 889 890 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 891 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 892 val & ~BRGPHY_PHY_EXTCTL_HIGH_LA); 893 } 894} 895 896static void 897brgphy_reset(struct mii_softc *sc) 898{ 899 struct bge_softc *bge_sc = NULL; 900 struct bce_softc *bce_sc = NULL; 901 if_t ifp; 902 int i, val; 903 904 /* 905 * Perform a reset. Note that at least some Broadcom PHYs default to 906 * being powered down as well as isolated after a reset but don't work 907 * if one or both of these bits are cleared. However, they just work 908 * fine if both bits remain set, so we don't use mii_phy_reset() here. 909 */ 910 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET); 911 912 /* Wait 100ms for it to complete. */ 913 for (i = 0; i < 100; i++) { 914 if ((PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_RESET) == 0) 915 break; 916 DELAY(1000); 917 } 918 919 /* Handle any PHY specific procedures following the reset. */ 920 switch (sc->mii_mpd_oui) { 921 case MII_OUI_BROADCOM: 922 switch (sc->mii_mpd_model) { 923 case MII_MODEL_BROADCOM_BCM5400: 924 bcm5401_load_dspcode(sc); 925 break; 926 case MII_MODEL_BROADCOM_BCM5401: 927 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3) 928 bcm5401_load_dspcode(sc); 929 break; 930 case MII_MODEL_BROADCOM_BCM5411: 931 bcm5411_load_dspcode(sc); 932 break; 933 case MII_MODEL_BROADCOM_BCM54K2: 934 bcm54k2_load_dspcode(sc); 935 break; 936 } 937 break; 938 case MII_OUI_BROADCOM3: 939 switch (sc->mii_mpd_model) { 940 case MII_MODEL_BROADCOM3_BCM5717C: 941 case MII_MODEL_BROADCOM3_BCM5719C: 942 case MII_MODEL_BROADCOM3_BCM5720C: 943 case MII_MODEL_BROADCOM3_BCM57765: 944 return; 945 } 946 break; 947 case MII_OUI_BROADCOM4: 948 return; 949 } 950 951 ifp = sc->mii_pdata->mii_ifp; 952 953 /* Find the driver associated with this PHY. */ 954 if (mii_phy_mac_match(sc, "bge")) 955 bge_sc = mii_phy_mac_softc(sc); 956 else if (mii_phy_mac_match(sc, "bce")) 957 bce_sc = mii_phy_mac_softc(sc); 958 959 if (bge_sc) { 960 /* Fix up various bugs */ 961 if (bge_sc->bge_phy_flags & BGE_PHY_5704_A0_BUG) 962 brgphy_fixup_5704_a0_bug(sc); 963 if (bge_sc->bge_phy_flags & BGE_PHY_ADC_BUG) 964 brgphy_fixup_adc_bug(sc); 965 if (bge_sc->bge_phy_flags & BGE_PHY_ADJUST_TRIM) 966 brgphy_fixup_adjust_trim(sc); 967 if (bge_sc->bge_phy_flags & BGE_PHY_BER_BUG) 968 brgphy_fixup_ber_bug(sc); 969 if (bge_sc->bge_phy_flags & BGE_PHY_CRC_BUG) 970 brgphy_fixup_crc_bug(sc); 971 if (bge_sc->bge_phy_flags & BGE_PHY_JITTER_BUG) 972 brgphy_fixup_jitter_bug(sc); 973 974 if (bge_sc->bge_flags & BGE_FLAG_JUMBO) 975 brgphy_jumbo_settings(sc, if_getmtu(ifp)); 976 977 if ((bge_sc->bge_phy_flags & BGE_PHY_NO_WIRESPEED) == 0) 978 brgphy_ethernet_wirespeed(sc); 979 980 /* Enable Link LED on Dell boxes */ 981 if (bge_sc->bge_phy_flags & BGE_PHY_NO_3LED) { 982 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 983 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) & 984 ~BRGPHY_PHY_EXTCTL_3_LED); 985 } 986 987 /* Adjust output voltage (From Linux driver) */ 988 if (bge_sc->bge_asicrev == BGE_ASICREV_BCM5906) 989 PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12); 990 } else if (bce_sc) { 991 if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5708 && 992 (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) { 993 994 /* Store autoneg capabilities/results in digital block (Page 0) */ 995 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2); 996 PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0, 997 BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE); 998 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0); 999 1000 /* Enable fiber mode and autodetection */ 1001 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1, 1002 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) | 1003 BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN | 1004 BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE); 1005 1006 /* Enable parallel detection */ 1007 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2, 1008 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) | 1009 BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN); 1010 1011 /* Advertise 2.5G support through next page during autoneg */ 1012 if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 1013 PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1, 1014 PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) | 1015 BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G); 1016 1017 /* Increase TX signal amplitude */ 1018 if ((BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_A0) || 1019 (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B0) || 1020 (BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B1)) { 1021 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1022 BRGPHY_5708S_TX_MISC_PG5); 1023 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1, 1024 PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & ~0x30); 1025 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1026 BRGPHY_5708S_DIG_PG0); 1027 } 1028 1029 /* Backplanes use special driver/pre-driver/pre-emphasis values. */ 1030 if ((bce_sc->bce_shared_hw_cfg & BCE_SHARED_HW_CFG_PHY_BACKPLANE) && 1031 (bce_sc->bce_port_hw_cfg & BCE_PORT_HW_CFG_CFG_TXCTL3_MASK)) { 1032 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1033 BRGPHY_5708S_TX_MISC_PG5); 1034 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3, 1035 bce_sc->bce_port_hw_cfg & 1036 BCE_PORT_HW_CFG_CFG_TXCTL3_MASK); 1037 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 1038 BRGPHY_5708S_DIG_PG0); 1039 } 1040 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709 && 1041 (bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) { 1042 1043 /* Select the SerDes Digital block of the AN MMD. */ 1044 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_SERDES_DIG); 1045 val = PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1); 1046 val &= ~BRGPHY_SD_DIG_1000X_CTL1_AUTODET; 1047 val |= BRGPHY_SD_DIG_1000X_CTL1_FIBER; 1048 PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1, val); 1049 1050 /* Select the Over 1G block of the AN MMD. */ 1051 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_OVER_1G); 1052 1053 /* Enable autoneg "Next Page" to advertise 2.5G support. */ 1054 val = PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1); 1055 if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 1056 val |= BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G; 1057 else 1058 val &= ~BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G; 1059 PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1, val); 1060 1061 /* Select the Multi-Rate Backplane Ethernet block of the AN MMD. */ 1062 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_MRBE); 1063 1064 /* Enable MRBE speed autoneg. */ 1065 val = PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP); 1066 val |= BRGPHY_MRBE_MSG_PG5_NP_MBRE | 1067 BRGPHY_MRBE_MSG_PG5_NP_T2; 1068 PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP, val); 1069 1070 /* Select the Clause 73 User B0 block of the AN MMD. */ 1071 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_CL73_USER_B0); 1072 1073 /* Enable MRBE speed autoneg. */ 1074 PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1, 1075 BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP | 1076 BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR | 1077 BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG); 1078 1079 /* Restore IEEE0 block (assumed in all brgphy(4) code). */ 1080 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 1081 } else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709) { 1082 if ((BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Ax) || 1083 (BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Bx)) 1084 brgphy_fixup_disable_early_dac(sc); 1085 1086 brgphy_jumbo_settings(sc, if_getmtu(ifp)); 1087 brgphy_ethernet_wirespeed(sc); 1088 } else { 1089 brgphy_fixup_ber_bug(sc); 1090 brgphy_jumbo_settings(sc, if_getmtu(ifp)); 1091 brgphy_ethernet_wirespeed(sc); 1092 } 1093 } 1094} 1095