brgphy.c revision 135772
1/* 2 * Copyright (c) 2000 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/mii/brgphy.c 135772 2004-09-24 22:24:33Z ps $"); 35 36/* 37 * Driver for the Broadcom BCR5400 1000baseTX PHY. Speed is always 38 * 1000mbps; all we need to negotiate here is full or half duplex. 39 */ 40 41#include <sys/param.h> 42#include <sys/systm.h> 43#include <sys/kernel.h> 44#include <sys/module.h> 45#include <sys/socket.h> 46#include <sys/bus.h> 47 48#include <machine/clock.h> 49 50#include <net/if.h> 51#include <net/if_media.h> 52 53#include <dev/mii/mii.h> 54#include <dev/mii/miivar.h> 55#include "miidevs.h" 56 57#include <dev/mii/brgphyreg.h> 58#include <net/if_arp.h> 59#include <machine/bus.h> 60#include <dev/bge/if_bgereg.h> 61 62#include <dev/pci/pcireg.h> 63#include <dev/pci/pcivar.h> 64 65#include "miibus_if.h" 66 67static int brgphy_probe(device_t); 68static int brgphy_attach(device_t); 69 70static device_method_t brgphy_methods[] = { 71 /* device interface */ 72 DEVMETHOD(device_probe, brgphy_probe), 73 DEVMETHOD(device_attach, brgphy_attach), 74 DEVMETHOD(device_detach, mii_phy_detach), 75 DEVMETHOD(device_shutdown, bus_generic_shutdown), 76 { 0, 0 } 77}; 78 79static devclass_t brgphy_devclass; 80 81static driver_t brgphy_driver = { 82 "brgphy", 83 brgphy_methods, 84 sizeof(struct mii_softc) 85}; 86 87DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0); 88 89static int brgphy_service(struct mii_softc *, struct mii_data *, int); 90static void brgphy_status(struct mii_softc *); 91static int brgphy_mii_phy_auto(struct mii_softc *); 92static void brgphy_reset(struct mii_softc *); 93static void brgphy_loop(struct mii_softc *); 94static void bcm5401_load_dspcode(struct mii_softc *); 95static void bcm5411_load_dspcode(struct mii_softc *); 96static void bcm5703_load_dspcode(struct mii_softc *); 97static void bcm5750_load_dspcode(struct mii_softc *); 98static int brgphy_mii_model; 99 100static int 101brgphy_probe(dev) 102 device_t dev; 103{ 104 struct mii_attach_args *ma; 105 106 ma = device_get_ivars(dev); 107 108 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 109 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5400) { 110 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5400); 111 return(0); 112 } 113 114 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 115 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5401) { 116 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5401); 117 return(0); 118 } 119 120 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 121 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5411) { 122 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5411); 123 return(0); 124 } 125 126 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 127 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5701) { 128 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5701); 129 return(0); 130 } 131 132 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 133 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5703) { 134 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5703); 135 return(0); 136 } 137 138 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 139 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5704) { 140 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5704); 141 return(0); 142 } 143 144 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 145 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5705) { 146 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5705); 147 return(0); 148 } 149 150 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 151 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5750) { 152 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5750); 153 return(0); 154 } 155 156 return(ENXIO); 157} 158 159static int 160brgphy_attach(dev) 161 device_t dev; 162{ 163 struct mii_softc *sc; 164 struct mii_attach_args *ma; 165 struct mii_data *mii; 166 const char *sep = ""; 167 struct bge_softc *bge_sc; 168 int fast_ether_only = FALSE; 169 170 sc = device_get_softc(dev); 171 ma = device_get_ivars(dev); 172 sc->mii_dev = device_get_parent(dev); 173 mii = device_get_softc(sc->mii_dev); 174 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); 175 176 sc->mii_inst = mii->mii_instance; 177 sc->mii_phy = ma->mii_phyno; 178 sc->mii_service = brgphy_service; 179 sc->mii_pdata = mii; 180 181 sc->mii_flags |= MIIF_NOISOLATE; 182 mii->mii_instance++; 183 184#define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 185#define PRINT(s) printf("%s%s", sep, s); sep = ", " 186 187 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst), 188 BMCR_ISO); 189#if 0 190 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), 191 BMCR_LOOP|BMCR_S100); 192#endif 193 194 brgphy_mii_model = MII_MODEL(ma->mii_id2); 195 brgphy_reset(sc); 196 197 198 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 199 sc->mii_capabilities &= ~BMSR_ANEG; 200 device_printf(dev, " "); 201 mii_add_media(sc); 202 203 /* The 590x chips are 10/100 only. */ 204 205 bge_sc = mii->mii_ifp->if_softc; 206 207 if (strcmp(mii->mii_ifp->if_dname, "bge") == 0 && 208 pci_get_vendor(bge_sc->bge_dev) == BCOM_VENDORID && 209 (pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901 || 210 pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901A2)) 211 fast_ether_only = TRUE; 212 213 if (fast_ether_only == FALSE) { 214 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0, 215 sc->mii_inst), BRGPHY_BMCR_FDX); 216 PRINT(", 1000baseTX"); 217 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 218 IFM_FDX, sc->mii_inst), 0); 219 PRINT("1000baseTX-FDX"); 220 } 221 222 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0); 223 PRINT("auto"); 224 225 printf("\n"); 226#undef ADD 227#undef PRINT 228 229 MIIBUS_MEDIAINIT(sc->mii_dev); 230 return(0); 231} 232 233static int 234brgphy_service(sc, mii, cmd) 235 struct mii_softc *sc; 236 struct mii_data *mii; 237 int cmd; 238{ 239 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 240 int reg, speed, gig; 241 242 switch (cmd) { 243 case MII_POLLSTAT: 244 /* 245 * If we're not polling our PHY instance, just return. 246 */ 247 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 248 return (0); 249 break; 250 251 case MII_MEDIACHG: 252 /* 253 * If the media indicates a different PHY instance, 254 * isolate ourselves. 255 */ 256 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 257 reg = PHY_READ(sc, MII_BMCR); 258 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 259 return (0); 260 } 261 262 /* 263 * If the interface is not up, don't do anything. 264 */ 265 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 266 break; 267 268 brgphy_reset(sc); /* XXX hardware bug work-around */ 269 270 switch (IFM_SUBTYPE(ife->ifm_media)) { 271 case IFM_AUTO: 272#ifdef foo 273 /* 274 * If we're already in auto mode, just return. 275 */ 276 if (PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_AUTOEN) 277 return (0); 278#endif 279 (void) brgphy_mii_phy_auto(sc); 280 break; 281 case IFM_1000_T: 282 speed = BRGPHY_S1000; 283 goto setit; 284 case IFM_100_TX: 285 speed = BRGPHY_S100; 286 goto setit; 287 case IFM_10_T: 288 speed = BRGPHY_S10; 289setit: 290 brgphy_loop(sc); 291 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 292 speed |= BRGPHY_BMCR_FDX; 293 gig = BRGPHY_1000CTL_AFD; 294 } else { 295 gig = BRGPHY_1000CTL_AHD; 296 } 297 298 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0); 299 PHY_WRITE(sc, BRGPHY_MII_BMCR, speed); 300 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE); 301 302 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) 303 break; 304 305 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig); 306 PHY_WRITE(sc, BRGPHY_MII_BMCR, 307 speed|BRGPHY_BMCR_AUTOEN|BRGPHY_BMCR_STARTNEG); 308 309 if (brgphy_mii_model != MII_MODEL_xxBROADCOM_BCM5701) 310 break; 311 312 /* 313 * When settning the link manually, one side must 314 * be the master and the other the slave. However 315 * ifmedia doesn't give us a good way to specify 316 * this, so we fake it by using one of the LINK 317 * flags. If LINK0 is set, we program the PHY to 318 * be a master, otherwise it's a slave. 319 */ 320 if ((mii->mii_ifp->if_flags & IFF_LINK0)) { 321 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 322 gig|BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC); 323 } else { 324 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 325 gig|BRGPHY_1000CTL_MSE); 326 } 327 break; 328#ifdef foo 329 case IFM_NONE: 330 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN); 331 break; 332#endif 333 case IFM_100_T4: 334 default: 335 return (EINVAL); 336 } 337 break; 338 339 case MII_TICK: 340 /* 341 * If we're not currently selected, just return. 342 */ 343 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 344 return (0); 345 346 /* 347 * Is the interface even up? 348 */ 349 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 350 return (0); 351 352 /* 353 * Only used for autonegotiation. 354 */ 355 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 356 break; 357 358 /* 359 * Check to see if we have link. If we do, we don't 360 * need to restart the autonegotiation process. Read 361 * the BMSR twice in case it's latched. 362 */ 363 reg = PHY_READ(sc, BRGPHY_MII_AUXSTS); 364 if (reg & BRGPHY_AUXSTS_LINK) 365 break; 366 367 /* 368 * Only retry autonegotiation every 5 seconds. 369 */ 370 if (++sc->mii_ticks <= 5) 371 break; 372 373 sc->mii_ticks = 0; 374 brgphy_mii_phy_auto(sc); 375 return (0); 376 } 377 378 /* Update the media status. */ 379 brgphy_status(sc); 380 381 /* 382 * Callback if something changed. Note that we need to poke 383 * the DSP on the Broadcom PHYs if the media changes. 384 * 385 */ 386 if (sc->mii_media_active != mii->mii_media_active || 387 sc->mii_media_status != mii->mii_media_status || 388 cmd == MII_MEDIACHG) { 389 switch (brgphy_mii_model) { 390 case MII_MODEL_xxBROADCOM_BCM5401: 391 bcm5401_load_dspcode(sc); 392 break; 393 case MII_MODEL_xxBROADCOM_BCM5411: 394 bcm5411_load_dspcode(sc); 395 break; 396 } 397 } 398 mii_phy_update(sc, cmd); 399 return (0); 400} 401 402static void 403brgphy_status(sc) 404 struct mii_softc *sc; 405{ 406 struct mii_data *mii = sc->mii_pdata; 407 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 408 int bmsr, bmcr; 409 410 mii->mii_media_status = IFM_AVALID; 411 mii->mii_media_active = IFM_ETHER; 412 413 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR); 414 if (PHY_READ(sc, BRGPHY_MII_AUXSTS) & BRGPHY_AUXSTS_LINK) 415 mii->mii_media_status |= IFM_ACTIVE; 416 417 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR); 418 419 if (bmcr & BRGPHY_BMCR_LOOP) 420 mii->mii_media_active |= IFM_LOOP; 421 422 if (bmcr & BRGPHY_BMCR_AUTOEN) { 423 if ((bmsr & BRGPHY_BMSR_ACOMP) == 0) { 424 /* Erg, still trying, I guess... */ 425 mii->mii_media_active |= IFM_NONE; 426 return; 427 } 428 429 switch (PHY_READ(sc, BRGPHY_MII_AUXSTS) & 430 BRGPHY_AUXSTS_AN_RES) { 431 case BRGPHY_RES_1000FD: 432 mii->mii_media_active |= IFM_1000_T | IFM_FDX; 433 break; 434 case BRGPHY_RES_1000HD: 435 mii->mii_media_active |= IFM_1000_T | IFM_HDX; 436 break; 437 case BRGPHY_RES_100FD: 438 mii->mii_media_active |= IFM_100_TX | IFM_FDX; 439 break; 440 case BRGPHY_RES_100T4: 441 mii->mii_media_active |= IFM_100_T4; 442 break; 443 case BRGPHY_RES_100HD: 444 mii->mii_media_active |= IFM_100_TX | IFM_HDX; 445 break; 446 case BRGPHY_RES_10FD: 447 mii->mii_media_active |= IFM_10_T | IFM_FDX; 448 break; 449 case BRGPHY_RES_10HD: 450 mii->mii_media_active |= IFM_10_T | IFM_HDX; 451 break; 452 default: 453 mii->mii_media_active |= IFM_NONE; 454 break; 455 } 456 return; 457 } 458 459 mii->mii_media_active = ife->ifm_media; 460 461 return; 462} 463 464 465static int 466brgphy_mii_phy_auto(mii) 467 struct mii_softc *mii; 468{ 469 int ktcr = 0; 470 471 brgphy_loop(mii); 472 brgphy_reset(mii); 473 ktcr = BRGPHY_1000CTL_AFD|BRGPHY_1000CTL_AHD; 474 if (brgphy_mii_model == MII_MODEL_xxBROADCOM_BCM5701) 475 ktcr |= BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC; 476 PHY_WRITE(mii, BRGPHY_MII_1000CTL, ktcr); 477 ktcr = PHY_READ(mii, BRGPHY_MII_1000CTL); 478 DELAY(1000); 479 PHY_WRITE(mii, BRGPHY_MII_ANAR, 480 BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA); 481 DELAY(1000); 482 PHY_WRITE(mii, BRGPHY_MII_BMCR, 483 BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG); 484 PHY_WRITE(mii, BRGPHY_MII_IMR, 0xFF00); 485 return (EJUSTRETURN); 486} 487 488static void 489brgphy_loop(struct mii_softc *sc) 490{ 491 u_int32_t bmsr; 492 int i; 493 494 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP); 495 for (i = 0; i < 15000; i++) { 496 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR); 497 if (!(bmsr & BRGPHY_BMSR_LINK)) { 498#if 0 499 device_printf(sc->mii_dev, "looped %d\n", i); 500#endif 501 break; 502 } 503 DELAY(10); 504 } 505} 506 507/* Turn off tap power management on 5401. */ 508static void 509bcm5401_load_dspcode(struct mii_softc *sc) 510{ 511 static const struct { 512 int reg; 513 uint16_t val; 514 } dspcode[] = { 515 { BRGPHY_MII_AUXCTL, 0x0c20 }, 516 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 517 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 518 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 519 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 520 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 521 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 522 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 523 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 524 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 525 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 526 { 0, 0 }, 527 }; 528 int i; 529 530 for (i = 0; dspcode[i].reg != 0; i++) 531 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 532 DELAY(40); 533} 534 535static void 536bcm5411_load_dspcode(struct mii_softc *sc) 537{ 538 static const struct { 539 int reg; 540 uint16_t val; 541 } dspcode[] = { 542 { 0x1c, 0x8c23 }, 543 { 0x1c, 0x8ca3 }, 544 { 0x1c, 0x8c23 }, 545 { 0, 0 }, 546 }; 547 int i; 548 549 for (i = 0; dspcode[i].reg != 0; i++) 550 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 551} 552 553static void 554bcm5703_load_dspcode(struct mii_softc *sc) 555{ 556 static const struct { 557 int reg; 558 uint16_t val; 559 } dspcode[] = { 560 { BRGPHY_MII_AUXCTL, 0x0c00 }, 561 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 562 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 563 { 0, 0 }, 564 }; 565 int i; 566 567 for (i = 0; dspcode[i].reg != 0; i++) 568 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 569} 570 571static void 572bcm5704_load_dspcode(struct mii_softc *sc) 573{ 574 static const struct { 575 int reg; 576 u_int16_t val; 577 } dspcode[] = { 578 { 0x1c, 0x8d68 }, 579 { 0x1c, 0x8d68 }, 580 { 0, 0 }, 581 }; 582 int i; 583 584 for (i = 0; dspcode[i].reg != 0; i++) 585 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 586} 587 588static void 589bcm5750_load_dspcode(struct mii_softc *sc) 590{ 591 static const struct { 592 int reg; 593 u_int16_t val; 594 } dspcode[] = { 595 { 0x18, 0x0c00 }, 596 { 0x17, 0x000a }, 597 { 0x15, 0x310b }, 598 { 0x17, 0x201f }, 599 { 0x15, 0x9506 }, 600 { 0x17, 0x401f }, 601 { 0x15, 0x14e2 }, 602 { 0x18, 0x0400 }, 603 { 0, 0 }, 604 }; 605 int i; 606 607 for (i = 0; dspcode[i].reg != 0; i++) 608 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 609} 610 611static void 612brgphy_reset(struct mii_softc *sc) 613{ 614 u_int32_t val; 615 struct ifnet *ifp; 616 struct bge_softc *bge_sc; 617 618 mii_phy_reset(sc); 619 620 switch (brgphy_mii_model) { 621 case MII_MODEL_xxBROADCOM_BCM5401: 622 bcm5401_load_dspcode(sc); 623 break; 624 case MII_MODEL_xxBROADCOM_BCM5411: 625 bcm5411_load_dspcode(sc); 626 break; 627 case MII_MODEL_xxBROADCOM_BCM5703: 628 bcm5703_load_dspcode(sc); 629 break; 630 case MII_MODEL_xxBROADCOM_BCM5704: 631 bcm5704_load_dspcode(sc); 632 break; 633 case MII_MODEL_xxBROADCOM_BCM5750: 634 bcm5750_load_dspcode(sc); 635 break; 636 } 637 638 ifp = sc->mii_pdata->mii_ifp; 639 bge_sc = ifp->if_softc; 640 641 /* 642 * Don't enable Ethernet@WireSpeed for the 5700 or the 643 * 5705 A1 and A2 chips. Make sure we only do this test 644 * on "bge" NICs, since other drivers may use this same 645 * PHY subdriver. 646 */ 647 if (strcmp(ifp->if_dname, "bge") == 0 && 648 (bge_sc->bge_asicrev == BGE_ASICREV_BCM5700 || 649 bge_sc->bge_chipid == BGE_CHIPID_BCM5705_A1 || 650 bge_sc->bge_chipid == BGE_CHIPID_BCM5705_A2)) 651 return; 652 653 /* Enable Ethernet@WireSpeed. */ 654 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 655 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 656 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4)); 657 658 /* Enable Link LED on Dell boxes */ 659 if (bge_sc->bge_no_3_led) { 660 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 661 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) 662 & ~BRGPHY_PHY_EXTCTL_3_LED); 663 } 664} 665