1/*- 2 * Copyright (C) 2008 MARVELL INTERNATIONAL LTD. 3 * All rights reserved. 4 * 5 * Developed by Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of MARVELL nor the names of contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD$ 32 */ 33 34#ifndef __IF_MGE_H__ 35#define __IF_MGE_H__ 36 37#include <arm/mv/mvvar.h> 38 39#define MGE_INTR_COUNT 5 /* ETH controller occupies 5 IRQ lines */ 40#define MGE_TX_DESC_NUM 256 41#define MGE_RX_DESC_NUM 256 42#define MGE_RX_QUEUE_NUM 8 43#define MGE_RX_DEFAULT_QUEUE 0 44 45#define MGE_CHECKSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 46 47/* Interrupt Coalescing types */ 48#define MGE_IC_RX 0 49#define MGE_IC_TX 1 50 51struct mge_desc { 52 uint32_t cmd_status; 53 uint16_t buff_size; 54 uint16_t byte_count; 55 bus_addr_t buffer; 56 bus_addr_t next_desc; 57}; 58 59struct mge_desc_wrapper { 60 bus_dmamap_t desc_dmap; 61 struct mge_desc* mge_desc; 62 bus_addr_t mge_desc_paddr; 63 bus_dmamap_t buffer_dmap; 64 struct mbuf* buffer; 65}; 66 67struct mge_softc { 68 struct ifnet *ifp; /* per-interface network data */ 69 70 phandle_t node; 71 72 device_t dev; 73 device_t miibus; 74 75 struct mii_data *mii; 76 struct ifmedia mge_ifmedia; 77 struct resource *res[1 + MGE_INTR_COUNT]; /* resources */ 78 void *ih_cookie[MGE_INTR_COUNT]; /* interrupt handlers cookies */ 79 struct mtx transmit_lock; /* transmitter lock */ 80 struct mtx receive_lock; /* receiver lock */ 81 82 uint32_t mge_if_flags; 83 uint32_t mge_media_status; 84 85 struct callout wd_callout; 86 int wd_timer; 87 88 bus_dma_tag_t mge_desc_dtag; 89 bus_dma_tag_t mge_tx_dtag; 90 bus_dma_tag_t mge_rx_dtag; 91 bus_addr_t tx_desc_start; 92 bus_addr_t rx_desc_start; 93 uint32_t tx_desc_curr; 94 uint32_t rx_desc_curr; 95 uint32_t tx_desc_used_idx; 96 uint32_t tx_desc_used_count; 97 uint32_t rx_ic_time; 98 uint32_t tx_ic_time; 99 struct mge_desc_wrapper mge_tx_desc[MGE_TX_DESC_NUM]; 100 struct mge_desc_wrapper mge_rx_desc[MGE_RX_DESC_NUM]; 101 102 uint32_t mge_tfut_ipg_max; /* TX FIFO Urgent Threshold */ 103 uint32_t mge_rx_ipg_max; 104 uint32_t mge_tx_arb_cfg; 105 uint32_t mge_tx_tok_cfg; 106 uint32_t mge_tx_tok_cnt; 107 uint16_t mge_mtu; 108 int mge_ver; 109 int mge_intr_cnt; 110 uint8_t mge_hw_csum; 111 112 int phy_attached; 113 int switch_attached; 114 struct mge_softc *phy_sc; 115}; 116 117 118/* bus access macros */ 119#define MGE_READ(sc,reg) bus_read_4((sc)->res[0], (reg)) 120#define MGE_WRITE(sc,reg,val) bus_write_4((sc)->res[0], (reg), (val)) 121 122/* Locking macros */ 123#define MGE_TRANSMIT_LOCK(sc) do { \ 124 mtx_assert(&(sc)->receive_lock, MA_NOTOWNED); \ 125 mtx_lock(&(sc)->transmit_lock); \ 126} while (0) 127 128#define MGE_TRANSMIT_UNLOCK(sc) mtx_unlock(&(sc)->transmit_lock) 129#define MGE_TRANSMIT_LOCK_ASSERT(sc) mtx_assert(&(sc)->transmit_lock, MA_OWNED) 130 131#define MGE_RECEIVE_LOCK(sc) do { \ 132 mtx_assert(&(sc)->transmit_lock, MA_NOTOWNED); \ 133 mtx_lock(&(sc)->receive_lock); \ 134} while (0) 135 136#define MGE_RECEIVE_UNLOCK(sc) mtx_unlock(&(sc)->receive_lock) 137#define MGE_RECEIVE_LOCK_ASSERT(sc) mtx_assert(&(sc)->receive_lock, MA_OWNED) 138 139#define MGE_GLOBAL_LOCK(sc) do { \ 140 mtx_assert(&(sc)->transmit_lock, MA_NOTOWNED); \ 141 mtx_assert(&(sc)->receive_lock, MA_NOTOWNED); \ 142 mtx_lock(&(sc)->transmit_lock); \ 143 mtx_lock(&(sc)->receive_lock); \ 144} while (0) 145 146#define MGE_GLOBAL_UNLOCK(sc) do { \ 147 MGE_RECEIVE_UNLOCK(sc); \ 148 MGE_TRANSMIT_UNLOCK(sc); \ 149} while (0) 150 151#define MGE_GLOBAL_LOCK_ASSERT(sc) do { \ 152 MGE_TRANSMIT_LOCK_ASSERT(sc); \ 153 MGE_RECEIVE_LOCK_ASSERT(sc); \ 154} while (0) 155 156#define MGE_SMI_LOCK() do { \ 157 sx_assert(&sx_smi, SA_UNLOCKED); \ 158 sx_xlock(&sx_smi); \ 159} while (0) 160 161#define MGE_SMI_UNLOCK() sx_unlock(&sx_smi) 162#define MGE_SMI_LOCK_ASSERT() sx_assert(&sx_smi, SA_XLOCKED) 163 164/* SMI-related macros */ 165#define MGE_REG_PHYDEV 0x000 166#define MGE_REG_SMI 0x004 167#define MGE_SMI_READ (1 << 26) 168#define MGE_SMI_WRITE (0 << 26) 169#define MGE_SMI_READVALID (1 << 27) 170#define MGE_SMI_BUSY (1 << 28) 171 172#define MGE_SMI_MASK 0x1fffffff 173#define MGE_SMI_DATA_MASK 0xffff 174#define MGE_SMI_DELAY 1000 175 176#define MGE_SWITCH_PHYDEV 6 177 178/* Internal Switch SMI Command */ 179 180#define SW_SMI_READ_CMD(phy, reg) ((1 << 15) | (1 << 12) | (1 << 11) | (phy << 5) | reg) 181#define SW_SMI_WRITE_CMD(phy, reg) ((1 << 15) | (1 << 12) | (1 << 10) | (phy << 5) | reg) 182 183/* TODO verify the timings and retries count w/specs */ 184#define MGE_SMI_READ_RETRIES 1000 185#define MGE_SMI_READ_DELAY 100 186#define MGE_SMI_WRITE_RETRIES 1000 187#define MGE_SMI_WRITE_DELAY 100 188 189/* MGE registers */ 190#define MGE_INT_CAUSE 0x080 191#define MGE_INT_MASK 0x084 192 193#define MGE_PORT_CONFIG 0x400 194#define PORT_CONFIG_UPM (1 << 0) /* promiscuous */ 195#define PORT_CONFIG_DFLT_RXQ(val) (((val) & 7) << 1) /* default RX queue */ 196#define PORT_CONFIG_ARO_RXQ(val) (((val) & 7) << 4) /* ARP RX queue */ 197#define PORT_CONFIG_REJECT_BCAST (1 << 7) /* reject non-ip and non-arp bcast */ 198#define PORT_CONFIG_REJECT_IP_BCAST (1 << 8) /* reject ip bcast */ 199#define PORT_CONFIG_REJECT_ARP__BCAST (1 << 9) /* reject arp bcast */ 200#define PORT_CONFIG_AMNoTxES (1 << 12) /* Automatic mode not updating Error Summary in Tx descriptor */ 201#define PORT_CONFIG_TCP_CAP (1 << 14) /* capture tcp to a different queue */ 202#define PORT_CONFIG_UDP_CAP (1 << 15) /* capture udp to a different queue */ 203#define PORT_CONFIG_TCPQ (7 << 16) /* queue to capture tcp */ 204#define PORT_CONFIG_UDPQ (7 << 19) /* queue to capture udp */ 205#define PORT_CONFIG_BPDUQ (7 << 22) /* queue to capture bpdu */ 206#define PORT_CONFIG_RXCS (1 << 25) /* calculation Rx TCP checksum include pseudo header */ 207 208#define MGE_PORT_EXT_CONFIG 0x404 209#define MGE_MAC_ADDR_L 0x414 210#define MGE_MAC_ADDR_H 0x418 211 212#define MGE_SDMA_CONFIG 0x41c 213#define MGE_SDMA_INT_ON_FRAME_BOUND (1 << 0) 214#define MGE_SDMA_RX_BURST_SIZE(val) (((val) & 7) << 1) 215#define MGE_SDMA_TX_BURST_SIZE(val) (((val) & 7) << 22) 216#define MGE_SDMA_BURST_1_WORD 0x0 217#define MGE_SDMA_BURST_2_WORD 0x1 218#define MGE_SDMA_BURST_4_WORD 0x2 219#define MGE_SDMA_BURST_8_WORD 0x3 220#define MGE_SDMA_BURST_16_WORD 0x4 221#define MGE_SDMA_RX_BYTE_SWAP (1 << 4) 222#define MGE_SDMA_TX_BYTE_SWAP (1 << 5) 223#define MGE_SDMA_DESC_SWAP_MODE (1 << 6) 224 225#define MGE_PORT_SERIAL_CTRL 0x43c 226#define PORT_SERIAL_ENABLE (1 << 0) /* serial port enable */ 227#define PORT_SERIAL_FORCE_LINKUP (1 << 1) /* force link status to up */ 228#define PORT_SERIAL_AUTONEG (1 << 2) /* enable autoneg for duplex mode */ 229#define PORT_SERIAL_AUTONEG_FC (1 << 3) /* enable autoneg for FC */ 230#define PORT_SERIAL_PAUSE_ADV (1 << 4) /* advertise symmetric FC in autoneg */ 231#define PORT_SERIAL_FORCE_FC(val) (((val) & 3) << 5) /* pause enable & disable frames conf */ 232#define PORT_SERIAL_NO_PAUSE_DIS 0x00 233#define PORT_SERIAL_PAUSE_DIS 0x01 234#define PORT_SERIAL_FORCE_BP(val) (((val) & 3) << 7) /* transmitting JAM configuration */ 235#define PORT_SERIAL_NO_JAM 0x00 236#define PORT_SERIAL_JAM 0x01 237#define PORT_SERIAL_RES_BIT9 (1 << 9) 238#define PORT_SERIAL_FORCE_LINK_FAIL (1 << 10) 239#define PORT_SERIAL_SPEED_AUTONEG (1 << 13) 240#define PORT_SERIAL_FORCE_DTE_ADV (1 << 14) 241#define PORT_SERIAL_MRU(val) (((val) & 7) << 17) 242#define PORT_SERIAL_MRU_1518 0x0 243#define PORT_SERIAL_MRU_1522 0x1 244#define PORT_SERIAL_MRU_1552 0x2 245#define PORT_SERIAL_MRU_9022 0x3 246#define PORT_SERIAL_MRU_9192 0x4 247#define PORT_SERIAL_MRU_9700 0x5 248#define PORT_SERIAL_FULL_DUPLEX (1 << 21) 249#define PORT_SERIAL_FULL_DUPLEX_FC (1 << 22) 250#define PORT_SERIAL_GMII_SPEED_1000 (1 << 23) 251#define PORT_SERIAL_MII_SPEED_100 (1 << 24) 252 253#define MGE_PORT_STATUS 0x444 254#define MGE_STATUS_LINKUP (1 << 1) 255#define MGE_STATUS_FULL_DUPLEX (1 << 2) 256#define MGE_STATUS_FLOW_CONTROL (1 << 3) 257#define MGE_STATUS_1000MB (1 << 4) 258#define MGE_STATUS_100MB (1 << 5) 259#define MGE_STATUS_TX_IN_PROG (1 << 7) 260#define MGE_STATUS_TX_FIFO_EMPTY (1 << 10) 261 262#define MGE_TX_QUEUE_CMD 0x448 263#define MGE_ENABLE_TXQ (1 << 0) 264#define MGE_DISABLE_TXQ (1 << 8) 265 266/* 88F6281 only */ 267#define MGE_PORT_SERIAL_CTRL1 0x44c 268#define MGE_PCS_LOOPBACK (1 << 1) 269#define MGE_RGMII_EN (1 << 3) 270#define MGE_PORT_RESET (1 << 4) 271#define MGE_CLK125_BYPASS (1 << 5) 272#define MGE_INBAND_AUTONEG (1 << 6) 273#define MGE_INBAND_AUTONEG_BYPASS (1 << 6) 274#define MGE_INBAND_AUTONEG_RESTART (1 << 7) 275#define MGE_1000BASEX (1 << 11) 276#define MGE_BP_COLLISION_COUNT (1 << 15) 277#define MGE_COLLISION_LIMIT(val) (((val) & 0x3f) << 16) 278#define MGE_DROP_ODD_PREAMBLE (1 << 22) 279 280#define MGE_PORT_INT_CAUSE 0x460 281#define MGE_PORT_INT_MASK 0x468 282#define MGE_PORT_INT_RX (1 << 0) 283#define MGE_PORT_INT_EXTEND (1 << 1) 284#define MGE_PORT_INT_RXQ0 (1 << 2) 285#define MGE_PORT_INT_RXERR (1 << 10) 286#define MGE_PORT_INT_RXERRQ0 (1 << 11) 287#define MGE_PORT_INT_SUM (1U << 31) 288 289#define MGE_PORT_INT_CAUSE_EXT 0x464 290#define MGE_PORT_INT_MASK_EXT 0x46C 291#define MGE_PORT_INT_EXT_TXBUF0 (1 << 0) 292#define MGE_PORT_INT_EXT_TXERR0 (1 << 8) 293#define MGE_PORT_INT_EXT_PHYSC (1 << 16) 294#define MGE_PORT_INT_EXT_RXOR (1 << 18) 295#define MGE_PORT_INT_EXT_TXUR (1 << 19) 296#define MGE_PORT_INT_EXT_LC (1 << 20) 297#define MGE_PORT_INT_EXT_IAR (1 << 23) 298#define MGE_PORT_INT_EXT_SUM (1U << 31) 299 300#define MGE_RX_FIFO_URGENT_TRSH 0x470 301#define MGE_TX_FIFO_URGENT_TRSH 0x474 302 303#define MGE_FIXED_PRIO_CONF 0x4dc 304#define MGE_FIXED_PRIO_EN(q) (1 << (q)) 305 306#define MGE_RX_CUR_DESC_PTR(q) (0x60c + ((q)<<4)) 307 308#define MGE_RX_QUEUE_CMD 0x680 309#define MGE_ENABLE_RXQ(q) (1 << ((q) & 0x7)) 310#define MGE_ENABLE_RXQ_ALL (0xff) 311#define MGE_DISABLE_RXQ(q) (1 << (((q) & 0x7) + 8)) 312#define MGE_DISABLE_RXQ_ALL (0xff00) 313 314#define MGE_TX_CUR_DESC_PTR 0x6c0 315 316#define MGE_TX_TOKEN_COUNT(q) (0x700 + ((q)<<4)) 317#define MGE_TX_TOKEN_CONF(q) (0x704 + ((q)<<4)) 318#define MGE_TX_ARBITER_CONF(q) (0x704 + ((q)<<4)) 319 320#define MGE_MCAST_REG_NUMBER 64 321#define MGE_DA_FILTER_SPEC_MCAST(i) (0x1400 + ((i) << 2)) 322#define MGE_DA_FILTER_OTH_MCAST(i) (0x1500 + ((i) << 2)) 323 324#define MGE_UCAST_REG_NUMBER 4 325#define MGE_DA_FILTER_UCAST(i) (0x1600 + ((i) << 2)) 326 327 328/* TX descriptor bits */ 329#define MGE_TX_LLC_SNAP (1 << 9) 330#define MGE_TX_NOT_FRAGMENT (1 << 10) 331#define MGE_TX_VLAN_TAGGED (1 << 15) 332#define MGE_TX_UDP (1 << 16) 333#define MGE_TX_GEN_L4_CSUM (1 << 17) 334#define MGE_TX_GEN_IP_CSUM (1 << 18) 335#define MGE_TX_PADDING (1 << 19) 336#define MGE_TX_LAST (1 << 20) 337#define MGE_TX_FIRST (1 << 21) 338#define MGE_TX_ETH_CRC (1 << 22) 339#define MGE_TX_EN_INT (1 << 23) 340 341#define MGE_TX_IP_HDR_SIZE(size) ((size << 11) & 0xFFFF) 342 343/* RX descriptor bits */ 344#define MGE_ERR_SUMMARY (1 << 0) 345#define MGE_ERR_MASK (3 << 1) 346#define MGE_RX_L4_PROTO_MASK (3 << 21) 347#define MGE_RX_L4_PROTO_TCP (0 << 21) 348#define MGE_RX_L4_PROTO_UDP (1 << 21) 349#define MGE_RX_L3_IS_IP (1 << 24) 350#define MGE_RX_IP_OK (1 << 25) 351#define MGE_RX_DESC_LAST (1 << 26) 352#define MGE_RX_DESC_FIRST (1 << 27) 353#define MGE_RX_ENABLE_INT (1 << 29) 354#define MGE_RX_L4_CSUM_OK (1 << 30) 355#define MGE_DMA_OWNED (1U << 31) 356 357#define MGE_RX_IP_FRAGMENT (1 << 2) 358 359#define MGE_RX_L4_IS_TCP(status) ((status & MGE_RX_L4_PROTO_MASK) \ 360 == MGE_RX_L4_PROTO_TCP) 361 362#define MGE_RX_L4_IS_UDP(status) ((status & MGE_RX_L4_PROTO_MASK) \ 363 == MGE_RX_L4_PROTO_UDP) 364 365/* TX error codes */ 366#define MGE_TX_ERROR_LC (0 << 1) /* Late collision */ 367#define MGE_TX_ERROR_UR (1 << 1) /* Underrun error */ 368#define MGE_TX_ERROR_RL (2 << 1) /* Excessive collision */ 369 370/* RX error codes */ 371#define MGE_RX_ERROR_CE (0 << 1) /* CRC error */ 372#define MGE_RX_ERROR_OR (1 << 1) /* Overrun error */ 373#define MGE_RX_ERROR_MF (2 << 1) /* Max frame length error */ 374#define MGE_RX_ERROR_RE (3 << 1) /* Resource error */ 375 376#endif /* __IF_MGE_H__ */ 377