1/*- 2 * Copyright (c) 2008 Weongyo Jeong <weongyo@freebsd.org> 3 * Copyright (c) 2007 Marvell Semiconductor, Inc. 4 * Copyright (c) 2007 Sam Leffler, Errno Consulting 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 15 * redistribution must be conditioned upon including a substantially 16 * similar Disclaimer requirement for further binary redistribution. 17 * 18 * NO WARRANTY 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 21 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 22 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 23 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 24 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 27 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 29 * THE POSSIBILITY OF SUCH DAMAGES. 30 */ 31 32#include <sys/cdefs.h> 33#ifdef __FreeBSD__ 34__FBSDID("$FreeBSD: stable/11/sys/dev/malo/if_malo.c 344969 2019-03-09 12:54:10Z avos $"); 35#endif 36 37#include "opt_malo.h" 38 39#include <sys/param.h> 40#include <sys/endian.h> 41#include <sys/kernel.h> 42#include <sys/malloc.h> 43#include <sys/socket.h> 44#include <sys/sockio.h> 45#include <sys/sysctl.h> 46#include <sys/taskqueue.h> 47 48#include <machine/bus.h> 49#include <sys/bus.h> 50 51#include <net/if.h> 52#include <net/if_var.h> 53#include <net/if_dl.h> 54#include <net/if_media.h> 55#include <net/if_types.h> 56#include <net/ethernet.h> 57 58#include <net80211/ieee80211_var.h> 59#include <net80211/ieee80211_regdomain.h> 60 61#include <net/bpf.h> 62 63#include <dev/malo/if_malo.h> 64 65SYSCTL_NODE(_hw, OID_AUTO, malo, CTLFLAG_RD, 0, 66 "Marvell 88w8335 driver parameters"); 67 68static int malo_txcoalesce = 8; /* # tx pkts to q before poking f/w*/ 69SYSCTL_INT(_hw_malo, OID_AUTO, txcoalesce, CTLFLAG_RWTUN, &malo_txcoalesce, 70 0, "tx buffers to send at once"); 71static int malo_rxbuf = MALO_RXBUF; /* # rx buffers to allocate */ 72SYSCTL_INT(_hw_malo, OID_AUTO, rxbuf, CTLFLAG_RWTUN, &malo_rxbuf, 73 0, "rx buffers allocated"); 74static int malo_rxquota = MALO_RXBUF; /* # max buffers to process */ 75SYSCTL_INT(_hw_malo, OID_AUTO, rxquota, CTLFLAG_RWTUN, &malo_rxquota, 76 0, "max rx buffers to process per interrupt"); 77static int malo_txbuf = MALO_TXBUF; /* # tx buffers to allocate */ 78SYSCTL_INT(_hw_malo, OID_AUTO, txbuf, CTLFLAG_RWTUN, &malo_txbuf, 79 0, "tx buffers allocated"); 80 81#ifdef MALO_DEBUG 82static int malo_debug = 0; 83SYSCTL_INT(_hw_malo, OID_AUTO, debug, CTLFLAG_RWTUN, &malo_debug, 84 0, "control debugging printfs"); 85enum { 86 MALO_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 87 MALO_DEBUG_XMIT_DESC = 0x00000002, /* xmit descriptors */ 88 MALO_DEBUG_RECV = 0x00000004, /* basic recv operation */ 89 MALO_DEBUG_RECV_DESC = 0x00000008, /* recv descriptors */ 90 MALO_DEBUG_RESET = 0x00000010, /* reset processing */ 91 MALO_DEBUG_INTR = 0x00000040, /* ISR */ 92 MALO_DEBUG_TX_PROC = 0x00000080, /* tx ISR proc */ 93 MALO_DEBUG_RX_PROC = 0x00000100, /* rx ISR proc */ 94 MALO_DEBUG_STATE = 0x00000400, /* 802.11 state transitions */ 95 MALO_DEBUG_NODE = 0x00000800, /* node management */ 96 MALO_DEBUG_RECV_ALL = 0x00001000, /* trace all frames (beacons) */ 97 MALO_DEBUG_FW = 0x00008000, /* firmware */ 98 MALO_DEBUG_ANY = 0xffffffff 99}; 100#define IS_BEACON(wh) \ 101 ((wh->i_fc[0] & (IEEE80211_FC0_TYPE_MASK | \ 102 IEEE80211_FC0_SUBTYPE_MASK)) == \ 103 (IEEE80211_FC0_TYPE_MGT|IEEE80211_FC0_SUBTYPE_BEACON)) 104#define IFF_DUMPPKTS_RECV(sc, wh) \ 105 (((sc->malo_debug & MALO_DEBUG_RECV) && \ 106 ((sc->malo_debug & MALO_DEBUG_RECV_ALL) || !IS_BEACON(wh)))) 107#define IFF_DUMPPKTS_XMIT(sc) \ 108 (sc->malo_debug & MALO_DEBUG_XMIT) 109#define DPRINTF(sc, m, fmt, ...) do { \ 110 if (sc->malo_debug & (m)) \ 111 printf(fmt, __VA_ARGS__); \ 112} while (0) 113#else 114#define DPRINTF(sc, m, fmt, ...) do { \ 115 (void) sc; \ 116} while (0) 117#endif 118 119static MALLOC_DEFINE(M_MALODEV, "malodev", "malo driver dma buffers"); 120 121static struct ieee80211vap *malo_vap_create(struct ieee80211com *, 122 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 123 const uint8_t [IEEE80211_ADDR_LEN], 124 const uint8_t [IEEE80211_ADDR_LEN]); 125static void malo_vap_delete(struct ieee80211vap *); 126static int malo_dma_setup(struct malo_softc *); 127static int malo_setup_hwdma(struct malo_softc *); 128static void malo_txq_init(struct malo_softc *, struct malo_txq *, int); 129static void malo_tx_cleanupq(struct malo_softc *, struct malo_txq *); 130static void malo_parent(struct ieee80211com *); 131static int malo_transmit(struct ieee80211com *, struct mbuf *); 132static void malo_start(struct malo_softc *); 133static void malo_watchdog(void *); 134static void malo_updateslot(struct ieee80211com *); 135static int malo_newstate(struct ieee80211vap *, enum ieee80211_state, int); 136static void malo_scan_start(struct ieee80211com *); 137static void malo_scan_end(struct ieee80211com *); 138static void malo_set_channel(struct ieee80211com *); 139static int malo_raw_xmit(struct ieee80211_node *, struct mbuf *, 140 const struct ieee80211_bpf_params *); 141static void malo_sysctlattach(struct malo_softc *); 142static void malo_announce(struct malo_softc *); 143static void malo_dma_cleanup(struct malo_softc *); 144static void malo_stop(struct malo_softc *); 145static int malo_chan_set(struct malo_softc *, struct ieee80211_channel *); 146static int malo_mode_init(struct malo_softc *); 147static void malo_tx_proc(void *, int); 148static void malo_rx_proc(void *, int); 149static void malo_init(void *); 150 151/* 152 * Read/Write shorthands for accesses to BAR 0. Note that all BAR 1 153 * operations are done in the "hal" except getting H/W MAC address at 154 * malo_attach and there should be no reference to them here. 155 */ 156static uint32_t 157malo_bar0_read4(struct malo_softc *sc, bus_size_t off) 158{ 159 return bus_space_read_4(sc->malo_io0t, sc->malo_io0h, off); 160} 161 162static void 163malo_bar0_write4(struct malo_softc *sc, bus_size_t off, uint32_t val) 164{ 165 DPRINTF(sc, MALO_DEBUG_FW, "%s: off 0x%jx val 0x%x\n", 166 __func__, (uintmax_t)off, val); 167 168 bus_space_write_4(sc->malo_io0t, sc->malo_io0h, off, val); 169} 170 171int 172malo_attach(uint16_t devid, struct malo_softc *sc) 173{ 174 struct ieee80211com *ic = &sc->malo_ic; 175 struct malo_hal *mh; 176 int error; 177 uint8_t bands[IEEE80211_MODE_BYTES]; 178 179 MALO_LOCK_INIT(sc); 180 callout_init_mtx(&sc->malo_watchdog_timer, &sc->malo_mtx, 0); 181 mbufq_init(&sc->malo_snd, ifqmaxlen); 182 183 mh = malo_hal_attach(sc->malo_dev, devid, 184 sc->malo_io1h, sc->malo_io1t, sc->malo_dmat); 185 if (mh == NULL) { 186 device_printf(sc->malo_dev, "unable to attach HAL\n"); 187 error = EIO; 188 goto bad; 189 } 190 sc->malo_mh = mh; 191 192 /* 193 * Load firmware so we can get setup. We arbitrarily pick station 194 * firmware; we'll re-load firmware as needed so setting up 195 * the wrong mode isn't a big deal. 196 */ 197 error = malo_hal_fwload(mh, "malo8335-h", "malo8335-m"); 198 if (error != 0) { 199 device_printf(sc->malo_dev, "unable to setup firmware\n"); 200 goto bad1; 201 } 202 /* XXX gethwspecs() extracts correct informations? not maybe! */ 203 error = malo_hal_gethwspecs(mh, &sc->malo_hwspecs); 204 if (error != 0) { 205 device_printf(sc->malo_dev, "unable to fetch h/w specs\n"); 206 goto bad1; 207 } 208 209 DPRINTF(sc, MALO_DEBUG_FW, 210 "malo_hal_gethwspecs: hwversion 0x%x hostif 0x%x" 211 "maxnum_wcb 0x%x maxnum_mcaddr 0x%x maxnum_tx_wcb 0x%x" 212 "regioncode 0x%x num_antenna 0x%x fw_releasenum 0x%x" 213 "wcbbase0 0x%x rxdesc_read 0x%x rxdesc_write 0x%x" 214 "ul_fw_awakecookie 0x%x w[4] = %x %x %x %x", 215 sc->malo_hwspecs.hwversion, 216 sc->malo_hwspecs.hostinterface, sc->malo_hwspecs.maxnum_wcb, 217 sc->malo_hwspecs.maxnum_mcaddr, sc->malo_hwspecs.maxnum_tx_wcb, 218 sc->malo_hwspecs.regioncode, sc->malo_hwspecs.num_antenna, 219 sc->malo_hwspecs.fw_releasenum, sc->malo_hwspecs.wcbbase0, 220 sc->malo_hwspecs.rxdesc_read, sc->malo_hwspecs.rxdesc_write, 221 sc->malo_hwspecs.ul_fw_awakecookie, 222 sc->malo_hwspecs.wcbbase[0], sc->malo_hwspecs.wcbbase[1], 223 sc->malo_hwspecs.wcbbase[2], sc->malo_hwspecs.wcbbase[3]); 224 225 /* NB: firmware looks that it does not export regdomain info API. */ 226 memset(bands, 0, sizeof(bands)); 227 setbit(bands, IEEE80211_MODE_11B); 228 setbit(bands, IEEE80211_MODE_11G); 229 ieee80211_init_channels(ic, NULL, bands); 230 231 sc->malo_txantenna = 0x2; /* h/w default */ 232 sc->malo_rxantenna = 0xffff; /* h/w default */ 233 234 /* 235 * Allocate tx + rx descriptors and populate the lists. 236 * We immediately push the information to the firmware 237 * as otherwise it gets upset. 238 */ 239 error = malo_dma_setup(sc); 240 if (error != 0) { 241 device_printf(sc->malo_dev, 242 "failed to setup descriptors: %d\n", error); 243 goto bad1; 244 } 245 error = malo_setup_hwdma(sc); /* push to firmware */ 246 if (error != 0) /* NB: malo_setupdma prints msg */ 247 goto bad2; 248 249 sc->malo_tq = taskqueue_create_fast("malo_taskq", M_NOWAIT, 250 taskqueue_thread_enqueue, &sc->malo_tq); 251 taskqueue_start_threads(&sc->malo_tq, 1, PI_NET, 252 "%s taskq", device_get_nameunit(sc->malo_dev)); 253 254 TASK_INIT(&sc->malo_rxtask, 0, malo_rx_proc, sc); 255 TASK_INIT(&sc->malo_txtask, 0, malo_tx_proc, sc); 256 257 ic->ic_softc = sc; 258 ic->ic_name = device_get_nameunit(sc->malo_dev); 259 /* XXX not right but it's not used anywhere important */ 260 ic->ic_phytype = IEEE80211_T_OFDM; 261 ic->ic_opmode = IEEE80211_M_STA; 262 ic->ic_caps = 263 IEEE80211_C_STA /* station mode supported */ 264 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 265 | IEEE80211_C_MONITOR /* monitor mode */ 266 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 267 | IEEE80211_C_SHSLOT /* short slot time supported */ 268 | IEEE80211_C_TXPMGT /* capable of txpow mgt */ 269 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 270 ; 271 IEEE80211_ADDR_COPY(ic->ic_macaddr, sc->malo_hwspecs.macaddr); 272 273 /* 274 * Transmit requires space in the packet for a special format transmit 275 * record and optional padding between this record and the payload. 276 * Ask the net80211 layer to arrange this when encapsulating 277 * packets so we can add it efficiently. 278 */ 279 ic->ic_headroom = sizeof(struct malo_txrec) - 280 sizeof(struct ieee80211_frame); 281 282 /* call MI attach routine. */ 283 ieee80211_ifattach(ic); 284 /* override default methods */ 285 ic->ic_vap_create = malo_vap_create; 286 ic->ic_vap_delete = malo_vap_delete; 287 ic->ic_raw_xmit = malo_raw_xmit; 288 ic->ic_updateslot = malo_updateslot; 289 ic->ic_scan_start = malo_scan_start; 290 ic->ic_scan_end = malo_scan_end; 291 ic->ic_set_channel = malo_set_channel; 292 ic->ic_parent = malo_parent; 293 ic->ic_transmit = malo_transmit; 294 295 sc->malo_invalid = 0; /* ready to go, enable int handling */ 296 297 ieee80211_radiotap_attach(ic, 298 &sc->malo_tx_th.wt_ihdr, sizeof(sc->malo_tx_th), 299 MALO_TX_RADIOTAP_PRESENT, 300 &sc->malo_rx_th.wr_ihdr, sizeof(sc->malo_rx_th), 301 MALO_RX_RADIOTAP_PRESENT); 302 303 /* 304 * Setup dynamic sysctl's. 305 */ 306 malo_sysctlattach(sc); 307 308 if (bootverbose) 309 ieee80211_announce(ic); 310 malo_announce(sc); 311 312 return 0; 313bad2: 314 malo_dma_cleanup(sc); 315bad1: 316 malo_hal_detach(mh); 317bad: 318 sc->malo_invalid = 1; 319 320 return error; 321} 322 323static struct ieee80211vap * 324malo_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 325 enum ieee80211_opmode opmode, int flags, 326 const uint8_t bssid[IEEE80211_ADDR_LEN], 327 const uint8_t mac[IEEE80211_ADDR_LEN]) 328{ 329 struct malo_softc *sc = ic->ic_softc; 330 struct malo_vap *mvp; 331 struct ieee80211vap *vap; 332 333 if (!TAILQ_EMPTY(&ic->ic_vaps)) { 334 device_printf(sc->malo_dev, "multiple vaps not supported\n"); 335 return NULL; 336 } 337 switch (opmode) { 338 case IEEE80211_M_STA: 339 if (opmode == IEEE80211_M_STA) 340 flags |= IEEE80211_CLONE_NOBEACONS; 341 /* fall thru... */ 342 case IEEE80211_M_MONITOR: 343 break; 344 default: 345 device_printf(sc->malo_dev, "%s mode not supported\n", 346 ieee80211_opmode_name[opmode]); 347 return NULL; /* unsupported */ 348 } 349 mvp = malloc(sizeof(struct malo_vap), M_80211_VAP, M_WAITOK | M_ZERO); 350 vap = &mvp->malo_vap; 351 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid); 352 353 /* override state transition machine */ 354 mvp->malo_newstate = vap->iv_newstate; 355 vap->iv_newstate = malo_newstate; 356 357 /* complete setup */ 358 ieee80211_vap_attach(vap, 359 ieee80211_media_change, ieee80211_media_status, mac); 360 ic->ic_opmode = opmode; 361 return vap; 362} 363 364static void 365malo_vap_delete(struct ieee80211vap *vap) 366{ 367 struct malo_vap *mvp = MALO_VAP(vap); 368 369 ieee80211_vap_detach(vap); 370 free(mvp, M_80211_VAP); 371} 372 373int 374malo_intr(void *arg) 375{ 376 struct malo_softc *sc = arg; 377 struct malo_hal *mh = sc->malo_mh; 378 uint32_t status; 379 380 if (sc->malo_invalid) { 381 /* 382 * The hardware is not ready/present, don't touch anything. 383 * Note this can happen early on if the IRQ is shared. 384 */ 385 DPRINTF(sc, MALO_DEBUG_ANY, "%s: invalid; ignored\n", __func__); 386 return (FILTER_STRAY); 387 } 388 389 /* 390 * Figure out the reason(s) for the interrupt. 391 */ 392 malo_hal_getisr(mh, &status); /* NB: clears ISR too */ 393 if (status == 0) /* must be a shared irq */ 394 return (FILTER_STRAY); 395 396 DPRINTF(sc, MALO_DEBUG_INTR, "%s: status 0x%x imask 0x%x\n", 397 __func__, status, sc->malo_imask); 398 399 if (status & MALO_A2HRIC_BIT_RX_RDY) 400 taskqueue_enqueue(sc->malo_tq, &sc->malo_rxtask); 401 if (status & MALO_A2HRIC_BIT_TX_DONE) 402 taskqueue_enqueue(sc->malo_tq, &sc->malo_txtask); 403 if (status & MALO_A2HRIC_BIT_OPC_DONE) 404 malo_hal_cmddone(mh); 405 if (status & MALO_A2HRIC_BIT_MAC_EVENT) 406 ; 407 if (status & MALO_A2HRIC_BIT_RX_PROBLEM) 408 ; 409 if (status & MALO_A2HRIC_BIT_ICV_ERROR) { 410 /* TKIP ICV error */ 411 sc->malo_stats.mst_rx_badtkipicv++; 412 } 413#ifdef MALO_DEBUG 414 if (((status | sc->malo_imask) ^ sc->malo_imask) != 0) 415 DPRINTF(sc, MALO_DEBUG_INTR, 416 "%s: can't handle interrupt status 0x%x\n", 417 __func__, status); 418#endif 419 return (FILTER_HANDLED); 420} 421 422static void 423malo_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 424{ 425 bus_addr_t *paddr = (bus_addr_t*) arg; 426 427 KASSERT(error == 0, ("error %u on bus_dma callback", error)); 428 429 *paddr = segs->ds_addr; 430} 431 432static int 433malo_desc_setup(struct malo_softc *sc, const char *name, 434 struct malo_descdma *dd, 435 int nbuf, size_t bufsize, int ndesc, size_t descsize) 436{ 437 int error; 438 uint8_t *ds; 439 440 DPRINTF(sc, MALO_DEBUG_RESET, 441 "%s: %s DMA: %u bufs (%ju) %u desc/buf (%ju)\n", 442 __func__, name, nbuf, (uintmax_t) bufsize, 443 ndesc, (uintmax_t) descsize); 444 445 dd->dd_name = name; 446 dd->dd_desc_len = nbuf * ndesc * descsize; 447 448 /* 449 * Setup DMA descriptor area. 450 */ 451 error = bus_dma_tag_create(bus_get_dma_tag(sc->malo_dev),/* parent */ 452 PAGE_SIZE, 0, /* alignment, bounds */ 453 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 454 BUS_SPACE_MAXADDR, /* highaddr */ 455 NULL, NULL, /* filter, filterarg */ 456 dd->dd_desc_len, /* maxsize */ 457 1, /* nsegments */ 458 dd->dd_desc_len, /* maxsegsize */ 459 BUS_DMA_ALLOCNOW, /* flags */ 460 NULL, /* lockfunc */ 461 NULL, /* lockarg */ 462 &dd->dd_dmat); 463 if (error != 0) { 464 device_printf(sc->malo_dev, "cannot allocate %s DMA tag\n", 465 dd->dd_name); 466 return error; 467 } 468 469 /* allocate descriptors */ 470 error = bus_dmamem_alloc(dd->dd_dmat, (void**) &dd->dd_desc, 471 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &dd->dd_dmamap); 472 if (error != 0) { 473 device_printf(sc->malo_dev, 474 "unable to alloc memory for %u %s descriptors, " 475 "error %u\n", nbuf * ndesc, dd->dd_name, error); 476 goto fail1; 477 } 478 479 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap, 480 dd->dd_desc, dd->dd_desc_len, 481 malo_load_cb, &dd->dd_desc_paddr, BUS_DMA_NOWAIT); 482 if (error != 0) { 483 device_printf(sc->malo_dev, 484 "unable to map %s descriptors, error %u\n", 485 dd->dd_name, error); 486 goto fail2; 487 } 488 489 ds = dd->dd_desc; 490 memset(ds, 0, dd->dd_desc_len); 491 DPRINTF(sc, MALO_DEBUG_RESET, 492 "%s: %s DMA map: %p (%lu) -> 0x%jx (%lu)\n", 493 __func__, dd->dd_name, ds, (u_long) dd->dd_desc_len, 494 (uintmax_t) dd->dd_desc_paddr, /*XXX*/ (u_long) dd->dd_desc_len); 495 496 return 0; 497fail2: 498 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap); 499fail1: 500 bus_dma_tag_destroy(dd->dd_dmat); 501 memset(dd, 0, sizeof(*dd)); 502 return error; 503} 504 505#define DS2PHYS(_dd, _ds) \ 506 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) 507 508static int 509malo_rxdma_setup(struct malo_softc *sc) 510{ 511 int error, bsize, i; 512 struct malo_rxbuf *bf; 513 struct malo_rxdesc *ds; 514 515 error = malo_desc_setup(sc, "rx", &sc->malo_rxdma, 516 malo_rxbuf, sizeof(struct malo_rxbuf), 517 1, sizeof(struct malo_rxdesc)); 518 if (error != 0) 519 return error; 520 521 /* 522 * Allocate rx buffers and set them up. 523 */ 524 bsize = malo_rxbuf * sizeof(struct malo_rxbuf); 525 bf = malloc(bsize, M_MALODEV, M_NOWAIT | M_ZERO); 526 if (bf == NULL) { 527 device_printf(sc->malo_dev, 528 "malloc of %u rx buffers failed\n", bsize); 529 return error; 530 } 531 sc->malo_rxdma.dd_bufptr = bf; 532 533 STAILQ_INIT(&sc->malo_rxbuf); 534 ds = sc->malo_rxdma.dd_desc; 535 for (i = 0; i < malo_rxbuf; i++, bf++, ds++) { 536 bf->bf_desc = ds; 537 bf->bf_daddr = DS2PHYS(&sc->malo_rxdma, ds); 538 error = bus_dmamap_create(sc->malo_dmat, BUS_DMA_NOWAIT, 539 &bf->bf_dmamap); 540 if (error != 0) { 541 device_printf(sc->malo_dev, 542 "%s: unable to dmamap for rx buffer, error %d\n", 543 __func__, error); 544 return error; 545 } 546 /* NB: tail is intentional to preserve descriptor order */ 547 STAILQ_INSERT_TAIL(&sc->malo_rxbuf, bf, bf_list); 548 } 549 return 0; 550} 551 552static int 553malo_txdma_setup(struct malo_softc *sc, struct malo_txq *txq) 554{ 555 int error, bsize, i; 556 struct malo_txbuf *bf; 557 struct malo_txdesc *ds; 558 559 error = malo_desc_setup(sc, "tx", &txq->dma, 560 malo_txbuf, sizeof(struct malo_txbuf), 561 MALO_TXDESC, sizeof(struct malo_txdesc)); 562 if (error != 0) 563 return error; 564 565 /* allocate and setup tx buffers */ 566 bsize = malo_txbuf * sizeof(struct malo_txbuf); 567 bf = malloc(bsize, M_MALODEV, M_NOWAIT | M_ZERO); 568 if (bf == NULL) { 569 device_printf(sc->malo_dev, "malloc of %u tx buffers failed\n", 570 malo_txbuf); 571 return ENOMEM; 572 } 573 txq->dma.dd_bufptr = bf; 574 575 STAILQ_INIT(&txq->free); 576 txq->nfree = 0; 577 ds = txq->dma.dd_desc; 578 for (i = 0; i < malo_txbuf; i++, bf++, ds += MALO_TXDESC) { 579 bf->bf_desc = ds; 580 bf->bf_daddr = DS2PHYS(&txq->dma, ds); 581 error = bus_dmamap_create(sc->malo_dmat, BUS_DMA_NOWAIT, 582 &bf->bf_dmamap); 583 if (error != 0) { 584 device_printf(sc->malo_dev, 585 "unable to create dmamap for tx " 586 "buffer %u, error %u\n", i, error); 587 return error; 588 } 589 STAILQ_INSERT_TAIL(&txq->free, bf, bf_list); 590 txq->nfree++; 591 } 592 593 return 0; 594} 595 596static void 597malo_desc_cleanup(struct malo_softc *sc, struct malo_descdma *dd) 598{ 599 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 600 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap); 601 bus_dma_tag_destroy(dd->dd_dmat); 602 603 memset(dd, 0, sizeof(*dd)); 604} 605 606static void 607malo_rxdma_cleanup(struct malo_softc *sc) 608{ 609 struct malo_rxbuf *bf; 610 611 STAILQ_FOREACH(bf, &sc->malo_rxbuf, bf_list) { 612 if (bf->bf_m != NULL) { 613 m_freem(bf->bf_m); 614 bf->bf_m = NULL; 615 } 616 if (bf->bf_dmamap != NULL) { 617 bus_dmamap_destroy(sc->malo_dmat, bf->bf_dmamap); 618 bf->bf_dmamap = NULL; 619 } 620 } 621 STAILQ_INIT(&sc->malo_rxbuf); 622 if (sc->malo_rxdma.dd_bufptr != NULL) { 623 free(sc->malo_rxdma.dd_bufptr, M_MALODEV); 624 sc->malo_rxdma.dd_bufptr = NULL; 625 } 626 if (sc->malo_rxdma.dd_desc_len != 0) 627 malo_desc_cleanup(sc, &sc->malo_rxdma); 628} 629 630static void 631malo_txdma_cleanup(struct malo_softc *sc, struct malo_txq *txq) 632{ 633 struct malo_txbuf *bf; 634 struct ieee80211_node *ni; 635 636 STAILQ_FOREACH(bf, &txq->free, bf_list) { 637 if (bf->bf_m != NULL) { 638 m_freem(bf->bf_m); 639 bf->bf_m = NULL; 640 } 641 ni = bf->bf_node; 642 bf->bf_node = NULL; 643 if (ni != NULL) { 644 /* 645 * Reclaim node reference. 646 */ 647 ieee80211_free_node(ni); 648 } 649 if (bf->bf_dmamap != NULL) { 650 bus_dmamap_destroy(sc->malo_dmat, bf->bf_dmamap); 651 bf->bf_dmamap = NULL; 652 } 653 } 654 STAILQ_INIT(&txq->free); 655 txq->nfree = 0; 656 if (txq->dma.dd_bufptr != NULL) { 657 free(txq->dma.dd_bufptr, M_MALODEV); 658 txq->dma.dd_bufptr = NULL; 659 } 660 if (txq->dma.dd_desc_len != 0) 661 malo_desc_cleanup(sc, &txq->dma); 662} 663 664static void 665malo_dma_cleanup(struct malo_softc *sc) 666{ 667 int i; 668 669 for (i = 0; i < MALO_NUM_TX_QUEUES; i++) 670 malo_txdma_cleanup(sc, &sc->malo_txq[i]); 671 672 malo_rxdma_cleanup(sc); 673} 674 675static int 676malo_dma_setup(struct malo_softc *sc) 677{ 678 int error, i; 679 680 /* rxdma initializing. */ 681 error = malo_rxdma_setup(sc); 682 if (error != 0) 683 return error; 684 685 /* NB: we just have 1 tx queue now. */ 686 for (i = 0; i < MALO_NUM_TX_QUEUES; i++) { 687 error = malo_txdma_setup(sc, &sc->malo_txq[i]); 688 if (error != 0) { 689 malo_dma_cleanup(sc); 690 691 return error; 692 } 693 694 malo_txq_init(sc, &sc->malo_txq[i], i); 695 } 696 697 return 0; 698} 699 700static void 701malo_hal_set_rxtxdma(struct malo_softc *sc) 702{ 703 int i; 704 705 malo_bar0_write4(sc, sc->malo_hwspecs.rxdesc_read, 706 sc->malo_hwdma.rxdesc_read); 707 malo_bar0_write4(sc, sc->malo_hwspecs.rxdesc_write, 708 sc->malo_hwdma.rxdesc_read); 709 710 for (i = 0; i < MALO_NUM_TX_QUEUES; i++) { 711 malo_bar0_write4(sc, 712 sc->malo_hwspecs.wcbbase[i], sc->malo_hwdma.wcbbase[i]); 713 } 714} 715 716/* 717 * Inform firmware of our tx/rx dma setup. The BAR 0 writes below are 718 * for compatibility with older firmware. For current firmware we send 719 * this information with a cmd block via malo_hal_sethwdma. 720 */ 721static int 722malo_setup_hwdma(struct malo_softc *sc) 723{ 724 int i; 725 struct malo_txq *txq; 726 727 sc->malo_hwdma.rxdesc_read = sc->malo_rxdma.dd_desc_paddr; 728 729 for (i = 0; i < MALO_NUM_TX_QUEUES; i++) { 730 txq = &sc->malo_txq[i]; 731 sc->malo_hwdma.wcbbase[i] = txq->dma.dd_desc_paddr; 732 } 733 sc->malo_hwdma.maxnum_txwcb = malo_txbuf; 734 sc->malo_hwdma.maxnum_wcb = MALO_NUM_TX_QUEUES; 735 736 malo_hal_set_rxtxdma(sc); 737 738 return 0; 739} 740 741static void 742malo_txq_init(struct malo_softc *sc, struct malo_txq *txq, int qnum) 743{ 744 struct malo_txbuf *bf, *bn; 745 struct malo_txdesc *ds; 746 747 MALO_TXQ_LOCK_INIT(sc, txq); 748 txq->qnum = qnum; 749 txq->txpri = 0; /* XXX */ 750 751 STAILQ_FOREACH(bf, &txq->free, bf_list) { 752 bf->bf_txq = txq; 753 754 ds = bf->bf_desc; 755 bn = STAILQ_NEXT(bf, bf_list); 756 if (bn == NULL) 757 bn = STAILQ_FIRST(&txq->free); 758 ds->physnext = htole32(bn->bf_daddr); 759 } 760 STAILQ_INIT(&txq->active); 761} 762 763/* 764 * Reclaim resources for a setup queue. 765 */ 766static void 767malo_tx_cleanupq(struct malo_softc *sc, struct malo_txq *txq) 768{ 769 /* XXX hal work? */ 770 MALO_TXQ_LOCK_DESTROY(txq); 771} 772 773/* 774 * Allocate a tx buffer for sending a frame. 775 */ 776static struct malo_txbuf * 777malo_getbuf(struct malo_softc *sc, struct malo_txq *txq) 778{ 779 struct malo_txbuf *bf; 780 781 MALO_TXQ_LOCK(txq); 782 bf = STAILQ_FIRST(&txq->free); 783 if (bf != NULL) { 784 STAILQ_REMOVE_HEAD(&txq->free, bf_list); 785 txq->nfree--; 786 } 787 MALO_TXQ_UNLOCK(txq); 788 if (bf == NULL) { 789 DPRINTF(sc, MALO_DEBUG_XMIT, 790 "%s: out of xmit buffers on q %d\n", __func__, txq->qnum); 791 sc->malo_stats.mst_tx_qstop++; 792 } 793 return bf; 794} 795 796static int 797malo_tx_dmasetup(struct malo_softc *sc, struct malo_txbuf *bf, struct mbuf *m0) 798{ 799 struct mbuf *m; 800 int error; 801 802 /* 803 * Load the DMA map so any coalescing is done. This also calculates 804 * the number of descriptors we need. 805 */ 806 error = bus_dmamap_load_mbuf_sg(sc->malo_dmat, bf->bf_dmamap, m0, 807 bf->bf_segs, &bf->bf_nseg, 808 BUS_DMA_NOWAIT); 809 if (error == EFBIG) { 810 /* XXX packet requires too many descriptors */ 811 bf->bf_nseg = MALO_TXDESC + 1; 812 } else if (error != 0) { 813 sc->malo_stats.mst_tx_busdma++; 814 m_freem(m0); 815 return error; 816 } 817 /* 818 * Discard null packets and check for packets that require too many 819 * TX descriptors. We try to convert the latter to a cluster. 820 */ 821 if (error == EFBIG) { /* too many desc's, linearize */ 822 sc->malo_stats.mst_tx_linear++; 823 m = m_defrag(m0, M_NOWAIT); 824 if (m == NULL) { 825 m_freem(m0); 826 sc->malo_stats.mst_tx_nombuf++; 827 return ENOMEM; 828 } 829 m0 = m; 830 error = bus_dmamap_load_mbuf_sg(sc->malo_dmat, bf->bf_dmamap, m0, 831 bf->bf_segs, &bf->bf_nseg, 832 BUS_DMA_NOWAIT); 833 if (error != 0) { 834 sc->malo_stats.mst_tx_busdma++; 835 m_freem(m0); 836 return error; 837 } 838 KASSERT(bf->bf_nseg <= MALO_TXDESC, 839 ("too many segments after defrag; nseg %u", bf->bf_nseg)); 840 } else if (bf->bf_nseg == 0) { /* null packet, discard */ 841 sc->malo_stats.mst_tx_nodata++; 842 m_freem(m0); 843 return EIO; 844 } 845 DPRINTF(sc, MALO_DEBUG_XMIT, "%s: m %p len %u\n", 846 __func__, m0, m0->m_pkthdr.len); 847 bus_dmamap_sync(sc->malo_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 848 bf->bf_m = m0; 849 850 return 0; 851} 852 853#ifdef MALO_DEBUG 854static void 855malo_printrxbuf(const struct malo_rxbuf *bf, u_int ix) 856{ 857 const struct malo_rxdesc *ds = bf->bf_desc; 858 uint32_t status = le32toh(ds->status); 859 860 printf("R[%2u] (DS.V:%p DS.P:0x%jx) NEXT:%08x DATA:%08x RC:%02x%s\n" 861 " STAT:%02x LEN:%04x SNR:%02x NF:%02x CHAN:%02x" 862 " RATE:%02x QOS:%04x\n", ix, ds, (uintmax_t)bf->bf_daddr, 863 le32toh(ds->physnext), le32toh(ds->physbuffdata), 864 ds->rxcontrol, 865 ds->rxcontrol != MALO_RXD_CTRL_DRIVER_OWN ? 866 "" : (status & MALO_RXD_STATUS_OK) ? " *" : " !", 867 ds->status, le16toh(ds->pktlen), ds->snr, ds->nf, ds->channel, 868 ds->rate, le16toh(ds->qosctrl)); 869} 870 871static void 872malo_printtxbuf(const struct malo_txbuf *bf, u_int qnum, u_int ix) 873{ 874 const struct malo_txdesc *ds = bf->bf_desc; 875 uint32_t status = le32toh(ds->status); 876 877 printf("Q%u[%3u]", qnum, ix); 878 printf(" (DS.V:%p DS.P:0x%jx)\n", ds, (uintmax_t)bf->bf_daddr); 879 printf(" NEXT:%08x DATA:%08x LEN:%04x STAT:%08x%s\n", 880 le32toh(ds->physnext), 881 le32toh(ds->pktptr), le16toh(ds->pktlen), status, 882 status & MALO_TXD_STATUS_USED ? 883 "" : (status & 3) != 0 ? " *" : " !"); 884 printf(" RATE:%02x PRI:%x QOS:%04x SAP:%08x FORMAT:%04x\n", 885 ds->datarate, ds->txpriority, le16toh(ds->qosctrl), 886 le32toh(ds->sap_pktinfo), le16toh(ds->format)); 887#if 0 888 { 889 const uint8_t *cp = (const uint8_t *) ds; 890 int i; 891 for (i = 0; i < sizeof(struct malo_txdesc); i++) { 892 printf("%02x ", cp[i]); 893 if (((i+1) % 16) == 0) 894 printf("\n"); 895 } 896 printf("\n"); 897 } 898#endif 899} 900#endif /* MALO_DEBUG */ 901 902static __inline void 903malo_updatetxrate(struct ieee80211_node *ni, int rix) 904{ 905 static const int ieeerates[] = 906 { 2, 4, 11, 22, 44, 12, 18, 24, 36, 48, 96, 108 }; 907 if (rix < nitems(ieeerates)) 908 ni->ni_txrate = ieeerates[rix]; 909} 910 911static int 912malo_fix2rate(int fix_rate) 913{ 914 static const int rates[] = 915 { 2, 4, 11, 22, 12, 18, 24, 36, 48, 96, 108 }; 916 return (fix_rate < nitems(rates) ? rates[fix_rate] : 0); 917} 918 919/* idiomatic shorthands: MS = mask+shift, SM = shift+mask */ 920#define MS(v,x) (((v) & x) >> x##_S) 921#define SM(v,x) (((v) << x##_S) & x) 922 923/* 924 * Process completed xmit descriptors from the specified queue. 925 */ 926static int 927malo_tx_processq(struct malo_softc *sc, struct malo_txq *txq) 928{ 929 struct malo_txbuf *bf; 930 struct malo_txdesc *ds; 931 struct ieee80211_node *ni; 932 int nreaped; 933 uint32_t status; 934 935 DPRINTF(sc, MALO_DEBUG_TX_PROC, "%s: tx queue %u\n", 936 __func__, txq->qnum); 937 for (nreaped = 0;; nreaped++) { 938 MALO_TXQ_LOCK(txq); 939 bf = STAILQ_FIRST(&txq->active); 940 if (bf == NULL) { 941 MALO_TXQ_UNLOCK(txq); 942 break; 943 } 944 ds = bf->bf_desc; 945 MALO_TXDESC_SYNC(txq, ds, 946 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 947 if (ds->status & htole32(MALO_TXD_STATUS_FW_OWNED)) { 948 MALO_TXQ_UNLOCK(txq); 949 break; 950 } 951 STAILQ_REMOVE_HEAD(&txq->active, bf_list); 952 MALO_TXQ_UNLOCK(txq); 953 954#ifdef MALO_DEBUG 955 if (sc->malo_debug & MALO_DEBUG_XMIT_DESC) 956 malo_printtxbuf(bf, txq->qnum, nreaped); 957#endif 958 ni = bf->bf_node; 959 if (ni != NULL) { 960 status = le32toh(ds->status); 961 if (status & MALO_TXD_STATUS_OK) { 962 uint16_t format = le16toh(ds->format); 963 uint8_t txant = MS(format, MALO_TXD_ANTENNA); 964 965 sc->malo_stats.mst_ant_tx[txant]++; 966 if (status & MALO_TXD_STATUS_OK_RETRY) 967 sc->malo_stats.mst_tx_retries++; 968 if (status & MALO_TXD_STATUS_OK_MORE_RETRY) 969 sc->malo_stats.mst_tx_mretries++; 970 malo_updatetxrate(ni, ds->datarate); 971 sc->malo_stats.mst_tx_rate = ds->datarate; 972 } else { 973 if (status & MALO_TXD_STATUS_FAILED_LINK_ERROR) 974 sc->malo_stats.mst_tx_linkerror++; 975 if (status & MALO_TXD_STATUS_FAILED_XRETRY) 976 sc->malo_stats.mst_tx_xretries++; 977 if (status & MALO_TXD_STATUS_FAILED_AGING) 978 sc->malo_stats.mst_tx_aging++; 979 } 980 /* XXX strip fw len in case header inspected */ 981 m_adj(bf->bf_m, sizeof(uint16_t)); 982 ieee80211_tx_complete(ni, bf->bf_m, 983 (status & MALO_TXD_STATUS_OK) == 0); 984 } else 985 m_freem(bf->bf_m); 986 987 ds->status = htole32(MALO_TXD_STATUS_IDLE); 988 ds->pktlen = htole32(0); 989 990 bus_dmamap_sync(sc->malo_dmat, bf->bf_dmamap, 991 BUS_DMASYNC_POSTWRITE); 992 bus_dmamap_unload(sc->malo_dmat, bf->bf_dmamap); 993 bf->bf_m = NULL; 994 bf->bf_node = NULL; 995 996 MALO_TXQ_LOCK(txq); 997 STAILQ_INSERT_TAIL(&txq->free, bf, bf_list); 998 txq->nfree++; 999 MALO_TXQ_UNLOCK(txq); 1000 } 1001 return nreaped; 1002} 1003 1004/* 1005 * Deferred processing of transmit interrupt. 1006 */ 1007static void 1008malo_tx_proc(void *arg, int npending) 1009{ 1010 struct malo_softc *sc = arg; 1011 int i, nreaped; 1012 1013 /* 1014 * Process each active queue. 1015 */ 1016 nreaped = 0; 1017 MALO_LOCK(sc); 1018 for (i = 0; i < MALO_NUM_TX_QUEUES; i++) { 1019 if (!STAILQ_EMPTY(&sc->malo_txq[i].active)) 1020 nreaped += malo_tx_processq(sc, &sc->malo_txq[i]); 1021 } 1022 1023 if (nreaped != 0) { 1024 sc->malo_timer = 0; 1025 malo_start(sc); 1026 } 1027 MALO_UNLOCK(sc); 1028} 1029 1030static int 1031malo_tx_start(struct malo_softc *sc, struct ieee80211_node *ni, 1032 struct malo_txbuf *bf, struct mbuf *m0) 1033{ 1034#define IS_DATA_FRAME(wh) \ 1035 ((wh->i_fc[0] & (IEEE80211_FC0_TYPE_MASK)) == IEEE80211_FC0_TYPE_DATA) 1036 int error, ismcast, iswep; 1037 int copyhdrlen, hdrlen, pktlen; 1038 struct ieee80211_frame *wh; 1039 struct ieee80211com *ic = &sc->malo_ic; 1040 struct ieee80211vap *vap = ni->ni_vap; 1041 struct malo_txdesc *ds; 1042 struct malo_txrec *tr; 1043 struct malo_txq *txq; 1044 uint16_t qos; 1045 1046 wh = mtod(m0, struct ieee80211_frame *); 1047 iswep = wh->i_fc[1] & IEEE80211_FC1_PROTECTED; 1048 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 1049 copyhdrlen = hdrlen = ieee80211_anyhdrsize(wh); 1050 pktlen = m0->m_pkthdr.len; 1051 if (IEEE80211_QOS_HAS_SEQ(wh)) { 1052 qos = *(uint16_t *)ieee80211_getqos(wh); 1053 if (IEEE80211_IS_DSTODS(wh)) 1054 copyhdrlen -= sizeof(qos); 1055 } else 1056 qos = 0; 1057 1058 if (iswep) { 1059 struct ieee80211_key *k; 1060 1061 /* 1062 * Construct the 802.11 header+trailer for an encrypted 1063 * frame. The only reason this can fail is because of an 1064 * unknown or unsupported cipher/key type. 1065 * 1066 * NB: we do this even though the firmware will ignore 1067 * what we've done for WEP and TKIP as we need the 1068 * ExtIV filled in for CCMP and this also adjusts 1069 * the headers which simplifies our work below. 1070 */ 1071 k = ieee80211_crypto_encap(ni, m0); 1072 if (k == NULL) { 1073 /* 1074 * This can happen when the key is yanked after the 1075 * frame was queued. Just discard the frame; the 1076 * 802.11 layer counts failures and provides 1077 * debugging/diagnostics. 1078 */ 1079 m_freem(m0); 1080 return EIO; 1081 } 1082 1083 /* 1084 * Adjust the packet length for the crypto additions 1085 * done during encap and any other bits that the f/w 1086 * will add later on. 1087 */ 1088 pktlen = m0->m_pkthdr.len; 1089 1090 /* packet header may have moved, reset our local pointer */ 1091 wh = mtod(m0, struct ieee80211_frame *); 1092 } 1093 1094 if (ieee80211_radiotap_active_vap(vap)) { 1095 sc->malo_tx_th.wt_flags = 0; /* XXX */ 1096 if (iswep) 1097 sc->malo_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 1098 sc->malo_tx_th.wt_txpower = ni->ni_txpower; 1099 sc->malo_tx_th.wt_antenna = sc->malo_txantenna; 1100 1101 ieee80211_radiotap_tx(vap, m0); 1102 } 1103 1104 /* 1105 * Copy up/down the 802.11 header; the firmware requires 1106 * we present a 2-byte payload length followed by a 1107 * 4-address header (w/o QoS), followed (optionally) by 1108 * any WEP/ExtIV header (but only filled in for CCMP). 1109 * We are assured the mbuf has sufficient headroom to 1110 * prepend in-place by the setup of ic_headroom in 1111 * malo_attach. 1112 */ 1113 if (hdrlen < sizeof(struct malo_txrec)) { 1114 const int space = sizeof(struct malo_txrec) - hdrlen; 1115 if (M_LEADINGSPACE(m0) < space) { 1116 /* NB: should never happen */ 1117 device_printf(sc->malo_dev, 1118 "not enough headroom, need %d found %zd, " 1119 "m_flags 0x%x m_len %d\n", 1120 space, M_LEADINGSPACE(m0), m0->m_flags, m0->m_len); 1121 ieee80211_dump_pkt(ic, 1122 mtod(m0, const uint8_t *), m0->m_len, 0, -1); 1123 m_freem(m0); 1124 /* XXX stat */ 1125 return EIO; 1126 } 1127 M_PREPEND(m0, space, M_NOWAIT); 1128 } 1129 tr = mtod(m0, struct malo_txrec *); 1130 if (wh != (struct ieee80211_frame *) &tr->wh) 1131 ovbcopy(wh, &tr->wh, hdrlen); 1132 /* 1133 * Note: the "firmware length" is actually the length of the fully 1134 * formed "802.11 payload". That is, it's everything except for 1135 * the 802.11 header. In particular this includes all crypto 1136 * material including the MIC! 1137 */ 1138 tr->fwlen = htole16(pktlen - hdrlen); 1139 1140 /* 1141 * Load the DMA map so any coalescing is done. This 1142 * also calculates the number of descriptors we need. 1143 */ 1144 error = malo_tx_dmasetup(sc, bf, m0); 1145 if (error != 0) 1146 return error; 1147 bf->bf_node = ni; /* NB: held reference */ 1148 m0 = bf->bf_m; /* NB: may have changed */ 1149 tr = mtod(m0, struct malo_txrec *); 1150 wh = (struct ieee80211_frame *)&tr->wh; 1151 1152 /* 1153 * Formulate tx descriptor. 1154 */ 1155 ds = bf->bf_desc; 1156 txq = bf->bf_txq; 1157 1158 ds->qosctrl = qos; /* NB: already little-endian */ 1159 ds->pktptr = htole32(bf->bf_segs[0].ds_addr); 1160 ds->pktlen = htole16(bf->bf_segs[0].ds_len); 1161 /* NB: pPhysNext setup once, don't touch */ 1162 ds->datarate = IS_DATA_FRAME(wh) ? 1 : 0; 1163 ds->sap_pktinfo = 0; 1164 ds->format = 0; 1165 1166 /* 1167 * Select transmit rate. 1168 */ 1169 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 1170 case IEEE80211_FC0_TYPE_MGT: 1171 sc->malo_stats.mst_tx_mgmt++; 1172 /* fall thru... */ 1173 case IEEE80211_FC0_TYPE_CTL: 1174 ds->txpriority = 1; 1175 break; 1176 case IEEE80211_FC0_TYPE_DATA: 1177 ds->txpriority = txq->qnum; 1178 break; 1179 default: 1180 device_printf(sc->malo_dev, "bogus frame type 0x%x (%s)\n", 1181 wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__); 1182 /* XXX statistic */ 1183 m_freem(m0); 1184 return EIO; 1185 } 1186 1187#ifdef MALO_DEBUG 1188 if (IFF_DUMPPKTS_XMIT(sc)) 1189 ieee80211_dump_pkt(ic, 1190 mtod(m0, const uint8_t *)+sizeof(uint16_t), 1191 m0->m_len - sizeof(uint16_t), ds->datarate, -1); 1192#endif 1193 1194 MALO_TXQ_LOCK(txq); 1195 if (!IS_DATA_FRAME(wh)) 1196 ds->status |= htole32(1); 1197 ds->status |= htole32(MALO_TXD_STATUS_FW_OWNED); 1198 STAILQ_INSERT_TAIL(&txq->active, bf, bf_list); 1199 MALO_TXDESC_SYNC(txq, ds, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1200 1201 sc->malo_timer = 5; 1202 MALO_TXQ_UNLOCK(txq); 1203 return 0; 1204} 1205 1206static int 1207malo_transmit(struct ieee80211com *ic, struct mbuf *m) 1208{ 1209 struct malo_softc *sc = ic->ic_softc; 1210 int error; 1211 1212 MALO_LOCK(sc); 1213 if (!sc->malo_running) { 1214 MALO_UNLOCK(sc); 1215 return (ENXIO); 1216 } 1217 error = mbufq_enqueue(&sc->malo_snd, m); 1218 if (error) { 1219 MALO_UNLOCK(sc); 1220 return (error); 1221 } 1222 malo_start(sc); 1223 MALO_UNLOCK(sc); 1224 return (0); 1225} 1226 1227static void 1228malo_start(struct malo_softc *sc) 1229{ 1230 struct ieee80211_node *ni; 1231 struct malo_txq *txq = &sc->malo_txq[0]; 1232 struct malo_txbuf *bf = NULL; 1233 struct mbuf *m; 1234 int nqueued = 0; 1235 1236 MALO_LOCK_ASSERT(sc); 1237 1238 if (!sc->malo_running || sc->malo_invalid) 1239 return; 1240 1241 while ((m = mbufq_dequeue(&sc->malo_snd)) != NULL) { 1242 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1243 bf = malo_getbuf(sc, txq); 1244 if (bf == NULL) { 1245 mbufq_prepend(&sc->malo_snd, m); 1246 sc->malo_stats.mst_tx_qstop++; 1247 break; 1248 } 1249 /* 1250 * Pass the frame to the h/w for transmission. 1251 */ 1252 if (malo_tx_start(sc, ni, bf, m)) { 1253 if_inc_counter(ni->ni_vap->iv_ifp, 1254 IFCOUNTER_OERRORS, 1); 1255 if (bf != NULL) { 1256 bf->bf_m = NULL; 1257 bf->bf_node = NULL; 1258 MALO_TXQ_LOCK(txq); 1259 STAILQ_INSERT_HEAD(&txq->free, bf, bf_list); 1260 MALO_TXQ_UNLOCK(txq); 1261 } 1262 ieee80211_free_node(ni); 1263 continue; 1264 } 1265 nqueued++; 1266 1267 if (nqueued >= malo_txcoalesce) { 1268 /* 1269 * Poke the firmware to process queued frames; 1270 * see below about (lack of) locking. 1271 */ 1272 nqueued = 0; 1273 malo_hal_txstart(sc->malo_mh, 0/*XXX*/); 1274 } 1275 } 1276 1277 if (nqueued) { 1278 /* 1279 * NB: We don't need to lock against tx done because 1280 * this just prods the firmware to check the transmit 1281 * descriptors. The firmware will also start fetching 1282 * descriptors by itself if it notices new ones are 1283 * present when it goes to deliver a tx done interrupt 1284 * to the host. So if we race with tx done processing 1285 * it's ok. Delivering the kick here rather than in 1286 * malo_tx_start is an optimization to avoid poking the 1287 * firmware for each packet. 1288 * 1289 * NB: the queue id isn't used so 0 is ok. 1290 */ 1291 malo_hal_txstart(sc->malo_mh, 0/*XXX*/); 1292 } 1293} 1294 1295static void 1296malo_watchdog(void *arg) 1297{ 1298 struct malo_softc *sc = arg; 1299 1300 callout_reset(&sc->malo_watchdog_timer, hz, malo_watchdog, sc); 1301 if (sc->malo_timer == 0 || --sc->malo_timer > 0) 1302 return; 1303 1304 if (sc->malo_running && !sc->malo_invalid) { 1305 device_printf(sc->malo_dev, "watchdog timeout\n"); 1306 1307 /* XXX no way to reset h/w. now */ 1308 1309 counter_u64_add(sc->malo_ic.ic_oerrors, 1); 1310 sc->malo_stats.mst_watchdog++; 1311 } 1312} 1313 1314static int 1315malo_hal_reset(struct malo_softc *sc) 1316{ 1317 static int first = 0; 1318 struct ieee80211com *ic = &sc->malo_ic; 1319 struct malo_hal *mh = sc->malo_mh; 1320 1321 if (first == 0) { 1322 /* 1323 * NB: when the device firstly is initialized, sometimes 1324 * firmware could override rx/tx dma registers so we re-set 1325 * these values once. 1326 */ 1327 malo_hal_set_rxtxdma(sc); 1328 first = 1; 1329 } 1330 1331 malo_hal_setantenna(mh, MHA_ANTENNATYPE_RX, sc->malo_rxantenna); 1332 malo_hal_setantenna(mh, MHA_ANTENNATYPE_TX, sc->malo_txantenna); 1333 malo_hal_setradio(mh, 1, MHP_AUTO_PREAMBLE); 1334 malo_chan_set(sc, ic->ic_curchan); 1335 1336 /* XXX needs other stuffs? */ 1337 1338 return 1; 1339} 1340 1341static __inline struct mbuf * 1342malo_getrxmbuf(struct malo_softc *sc, struct malo_rxbuf *bf) 1343{ 1344 struct mbuf *m; 1345 bus_addr_t paddr; 1346 int error; 1347 1348 /* XXX don't need mbuf, just dma buffer */ 1349 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUMPAGESIZE); 1350 if (m == NULL) { 1351 sc->malo_stats.mst_rx_nombuf++; /* XXX */ 1352 return NULL; 1353 } 1354 error = bus_dmamap_load(sc->malo_dmat, bf->bf_dmamap, 1355 mtod(m, caddr_t), MJUMPAGESIZE, 1356 malo_load_cb, &paddr, BUS_DMA_NOWAIT); 1357 if (error != 0) { 1358 device_printf(sc->malo_dev, 1359 "%s: bus_dmamap_load failed, error %d\n", __func__, error); 1360 m_freem(m); 1361 return NULL; 1362 } 1363 bf->bf_data = paddr; 1364 bus_dmamap_sync(sc->malo_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 1365 1366 return m; 1367} 1368 1369static int 1370malo_rxbuf_init(struct malo_softc *sc, struct malo_rxbuf *bf) 1371{ 1372 struct malo_rxdesc *ds; 1373 1374 ds = bf->bf_desc; 1375 if (bf->bf_m == NULL) { 1376 bf->bf_m = malo_getrxmbuf(sc, bf); 1377 if (bf->bf_m == NULL) { 1378 /* mark descriptor to be skipped */ 1379 ds->rxcontrol = MALO_RXD_CTRL_OS_OWN; 1380 /* NB: don't need PREREAD */ 1381 MALO_RXDESC_SYNC(sc, ds, BUS_DMASYNC_PREWRITE); 1382 return ENOMEM; 1383 } 1384 } 1385 1386 /* 1387 * Setup descriptor. 1388 */ 1389 ds->qosctrl = 0; 1390 ds->snr = 0; 1391 ds->status = MALO_RXD_STATUS_IDLE; 1392 ds->channel = 0; 1393 ds->pktlen = htole16(MALO_RXSIZE); 1394 ds->nf = 0; 1395 ds->physbuffdata = htole32(bf->bf_data); 1396 /* NB: don't touch pPhysNext, set once */ 1397 ds->rxcontrol = MALO_RXD_CTRL_DRIVER_OWN; 1398 MALO_RXDESC_SYNC(sc, ds, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1399 1400 return 0; 1401} 1402 1403/* 1404 * Setup the rx data structures. This should only be done once or we may get 1405 * out of sync with the firmware. 1406 */ 1407static int 1408malo_startrecv(struct malo_softc *sc) 1409{ 1410 struct malo_rxbuf *bf, *prev; 1411 struct malo_rxdesc *ds; 1412 1413 if (sc->malo_recvsetup == 1) { 1414 malo_mode_init(sc); /* set filters, etc. */ 1415 return 0; 1416 } 1417 1418 prev = NULL; 1419 STAILQ_FOREACH(bf, &sc->malo_rxbuf, bf_list) { 1420 int error = malo_rxbuf_init(sc, bf); 1421 if (error != 0) { 1422 DPRINTF(sc, MALO_DEBUG_RECV, 1423 "%s: malo_rxbuf_init failed %d\n", 1424 __func__, error); 1425 return error; 1426 } 1427 if (prev != NULL) { 1428 ds = prev->bf_desc; 1429 ds->physnext = htole32(bf->bf_daddr); 1430 } 1431 prev = bf; 1432 } 1433 if (prev != NULL) { 1434 ds = prev->bf_desc; 1435 ds->physnext = 1436 htole32(STAILQ_FIRST(&sc->malo_rxbuf)->bf_daddr); 1437 } 1438 1439 sc->malo_recvsetup = 1; 1440 1441 malo_mode_init(sc); /* set filters, etc. */ 1442 1443 return 0; 1444} 1445 1446static void 1447malo_init_locked(struct malo_softc *sc) 1448{ 1449 struct malo_hal *mh = sc->malo_mh; 1450 int error; 1451 1452 MALO_LOCK_ASSERT(sc); 1453 1454 /* 1455 * Stop anything previously setup. This is safe whether this is 1456 * the first time through or not. 1457 */ 1458 malo_stop(sc); 1459 1460 /* 1461 * Push state to the firmware. 1462 */ 1463 if (!malo_hal_reset(sc)) { 1464 device_printf(sc->malo_dev, 1465 "%s: unable to reset hardware\n", __func__); 1466 return; 1467 } 1468 1469 /* 1470 * Setup recv (once); transmit is already good to go. 1471 */ 1472 error = malo_startrecv(sc); 1473 if (error != 0) { 1474 device_printf(sc->malo_dev, 1475 "%s: unable to start recv logic, error %d\n", 1476 __func__, error); 1477 return; 1478 } 1479 1480 /* 1481 * Enable interrupts. 1482 */ 1483 sc->malo_imask = MALO_A2HRIC_BIT_RX_RDY 1484 | MALO_A2HRIC_BIT_TX_DONE 1485 | MALO_A2HRIC_BIT_OPC_DONE 1486 | MALO_A2HRIC_BIT_MAC_EVENT 1487 | MALO_A2HRIC_BIT_RX_PROBLEM 1488 | MALO_A2HRIC_BIT_ICV_ERROR 1489 | MALO_A2HRIC_BIT_RADAR_DETECT 1490 | MALO_A2HRIC_BIT_CHAN_SWITCH; 1491 1492 sc->malo_running = 1; 1493 malo_hal_intrset(mh, sc->malo_imask); 1494 callout_reset(&sc->malo_watchdog_timer, hz, malo_watchdog, sc); 1495} 1496 1497static void 1498malo_init(void *arg) 1499{ 1500 struct malo_softc *sc = (struct malo_softc *) arg; 1501 struct ieee80211com *ic = &sc->malo_ic; 1502 1503 MALO_LOCK(sc); 1504 malo_init_locked(sc); 1505 MALO_UNLOCK(sc); 1506 1507 if (sc->malo_running) 1508 ieee80211_start_all(ic); /* start all vap's */ 1509} 1510 1511/* 1512 * Set the multicast filter contents into the hardware. 1513 */ 1514static void 1515malo_setmcastfilter(struct malo_softc *sc) 1516{ 1517 struct ieee80211com *ic = &sc->malo_ic; 1518 struct ieee80211vap *vap; 1519 uint8_t macs[IEEE80211_ADDR_LEN * MALO_HAL_MCAST_MAX]; 1520 uint8_t *mp; 1521 int nmc; 1522 1523 mp = macs; 1524 nmc = 0; 1525 1526 if (ic->ic_opmode == IEEE80211_M_MONITOR || ic->ic_allmulti > 0 || 1527 ic->ic_promisc > 0) 1528 goto all; 1529 1530 TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next) { 1531 struct ifnet *ifp; 1532 struct ifmultiaddr *ifma; 1533 1534 ifp = vap->iv_ifp; 1535 if_maddr_rlock(ifp); 1536 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1537 if (ifma->ifma_addr->sa_family != AF_LINK) 1538 continue; 1539 1540 if (nmc == MALO_HAL_MCAST_MAX) { 1541 ifp->if_flags |= IFF_ALLMULTI; 1542 if_maddr_runlock(ifp); 1543 goto all; 1544 } 1545 IEEE80211_ADDR_COPY(mp, 1546 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1547 1548 mp += IEEE80211_ADDR_LEN, nmc++; 1549 } 1550 if_maddr_runlock(ifp); 1551 } 1552 1553 malo_hal_setmcast(sc->malo_mh, nmc, macs); 1554 1555all: 1556 /* 1557 * XXX we don't know how to set the f/w for supporting 1558 * IFF_ALLMULTI | IFF_PROMISC cases 1559 */ 1560 return; 1561} 1562 1563static int 1564malo_mode_init(struct malo_softc *sc) 1565{ 1566 struct ieee80211com *ic = &sc->malo_ic; 1567 struct malo_hal *mh = sc->malo_mh; 1568 1569 malo_hal_setpromisc(mh, ic->ic_promisc > 0); 1570 malo_setmcastfilter(sc); 1571 1572 return ENXIO; 1573} 1574 1575static void 1576malo_tx_draintxq(struct malo_softc *sc, struct malo_txq *txq) 1577{ 1578 struct ieee80211_node *ni; 1579 struct malo_txbuf *bf; 1580 u_int ix; 1581 1582 /* 1583 * NB: this assumes output has been stopped and 1584 * we do not need to block malo_tx_tasklet 1585 */ 1586 for (ix = 0;; ix++) { 1587 MALO_TXQ_LOCK(txq); 1588 bf = STAILQ_FIRST(&txq->active); 1589 if (bf == NULL) { 1590 MALO_TXQ_UNLOCK(txq); 1591 break; 1592 } 1593 STAILQ_REMOVE_HEAD(&txq->active, bf_list); 1594 MALO_TXQ_UNLOCK(txq); 1595#ifdef MALO_DEBUG 1596 if (sc->malo_debug & MALO_DEBUG_RESET) { 1597 struct ieee80211com *ic = &sc->malo_ic; 1598 const struct malo_txrec *tr = 1599 mtod(bf->bf_m, const struct malo_txrec *); 1600 malo_printtxbuf(bf, txq->qnum, ix); 1601 ieee80211_dump_pkt(ic, (const uint8_t *)&tr->wh, 1602 bf->bf_m->m_len - sizeof(tr->fwlen), 0, -1); 1603 } 1604#endif /* MALO_DEBUG */ 1605 bus_dmamap_unload(sc->malo_dmat, bf->bf_dmamap); 1606 ni = bf->bf_node; 1607 bf->bf_node = NULL; 1608 if (ni != NULL) { 1609 /* 1610 * Reclaim node reference. 1611 */ 1612 ieee80211_free_node(ni); 1613 } 1614 m_freem(bf->bf_m); 1615 bf->bf_m = NULL; 1616 1617 MALO_TXQ_LOCK(txq); 1618 STAILQ_INSERT_TAIL(&txq->free, bf, bf_list); 1619 txq->nfree++; 1620 MALO_TXQ_UNLOCK(txq); 1621 } 1622} 1623 1624static void 1625malo_stop(struct malo_softc *sc) 1626{ 1627 struct malo_hal *mh = sc->malo_mh; 1628 int i; 1629 1630 DPRINTF(sc, MALO_DEBUG_ANY, "%s: invalid %u running %u\n", 1631 __func__, sc->malo_invalid, sc->malo_running); 1632 1633 MALO_LOCK_ASSERT(sc); 1634 1635 if (!sc->malo_running) 1636 return; 1637 1638 /* 1639 * Shutdown the hardware and driver: 1640 * disable interrupts 1641 * turn off the radio 1642 * drain and release tx queues 1643 * 1644 * Note that some of this work is not possible if the hardware 1645 * is gone (invalid). 1646 */ 1647 sc->malo_running = 0; 1648 callout_stop(&sc->malo_watchdog_timer); 1649 sc->malo_timer = 0; 1650 /* disable interrupt. */ 1651 malo_hal_intrset(mh, 0); 1652 /* turn off the radio. */ 1653 malo_hal_setradio(mh, 0, MHP_AUTO_PREAMBLE); 1654 1655 /* drain and release tx queues. */ 1656 for (i = 0; i < MALO_NUM_TX_QUEUES; i++) 1657 malo_tx_draintxq(sc, &sc->malo_txq[i]); 1658} 1659 1660static void 1661malo_parent(struct ieee80211com *ic) 1662{ 1663 struct malo_softc *sc = ic->ic_softc; 1664 int startall = 0; 1665 1666 MALO_LOCK(sc); 1667 if (ic->ic_nrunning > 0) { 1668 /* 1669 * Beware of being called during attach/detach 1670 * to reset promiscuous mode. In that case we 1671 * will still be marked UP but not RUNNING. 1672 * However trying to re-init the interface 1673 * is the wrong thing to do as we've already 1674 * torn down much of our state. There's 1675 * probably a better way to deal with this. 1676 */ 1677 if (!sc->malo_running && !sc->malo_invalid) { 1678 malo_init(sc); 1679 startall = 1; 1680 } 1681 /* 1682 * To avoid rescanning another access point, 1683 * do not call malo_init() here. Instead, 1684 * only reflect promisc mode settings. 1685 */ 1686 malo_mode_init(sc); 1687 } else if (sc->malo_running) 1688 malo_stop(sc); 1689 MALO_UNLOCK(sc); 1690 if (startall) 1691 ieee80211_start_all(ic); 1692} 1693 1694/* 1695 * Callback from the 802.11 layer to update the slot time 1696 * based on the current setting. We use it to notify the 1697 * firmware of ERP changes and the f/w takes care of things 1698 * like slot time and preamble. 1699 */ 1700static void 1701malo_updateslot(struct ieee80211com *ic) 1702{ 1703 struct malo_softc *sc = ic->ic_softc; 1704 struct malo_hal *mh = sc->malo_mh; 1705 int error; 1706 1707 /* NB: can be called early; suppress needless cmds */ 1708 if (!sc->malo_running) 1709 return; 1710 1711 DPRINTF(sc, MALO_DEBUG_RESET, 1712 "%s: chan %u MHz/flags 0x%x %s slot, (ic_flags 0x%x)\n", 1713 __func__, ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags, 1714 ic->ic_flags & IEEE80211_F_SHSLOT ? "short" : "long", ic->ic_flags); 1715 1716 if (ic->ic_flags & IEEE80211_F_SHSLOT) 1717 error = malo_hal_set_slot(mh, 1); 1718 else 1719 error = malo_hal_set_slot(mh, 0); 1720 1721 if (error != 0) 1722 device_printf(sc->malo_dev, "setting %s slot failed\n", 1723 ic->ic_flags & IEEE80211_F_SHSLOT ? "short" : "long"); 1724} 1725 1726static int 1727malo_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1728{ 1729 struct ieee80211com *ic = vap->iv_ic; 1730 struct malo_softc *sc = ic->ic_softc; 1731 struct malo_hal *mh = sc->malo_mh; 1732 int error; 1733 1734 DPRINTF(sc, MALO_DEBUG_STATE, "%s: %s -> %s\n", __func__, 1735 ieee80211_state_name[vap->iv_state], 1736 ieee80211_state_name[nstate]); 1737 1738 /* 1739 * Invoke the net80211 layer first so iv_bss is setup. 1740 */ 1741 error = MALO_VAP(vap)->malo_newstate(vap, nstate, arg); 1742 if (error != 0) 1743 return error; 1744 1745 if (nstate == IEEE80211_S_RUN && vap->iv_state != IEEE80211_S_RUN) { 1746 struct ieee80211_node *ni = vap->iv_bss; 1747 enum ieee80211_phymode mode = ieee80211_chan2mode(ni->ni_chan); 1748 const struct ieee80211_txparam *tp = &vap->iv_txparms[mode]; 1749 1750 DPRINTF(sc, MALO_DEBUG_STATE, 1751 "%s: %s(RUN): iv_flags 0x%08x bintvl %d bssid %s " 1752 "capinfo 0x%04x chan %d associd 0x%x mode %d rate %d\n", 1753 vap->iv_ifp->if_xname, __func__, vap->iv_flags, 1754 ni->ni_intval, ether_sprintf(ni->ni_bssid), ni->ni_capinfo, 1755 ieee80211_chan2ieee(ic, ic->ic_curchan), 1756 ni->ni_associd, mode, tp->ucastrate); 1757 1758 malo_hal_setradio(mh, 1, 1759 (ic->ic_flags & IEEE80211_F_SHPREAMBLE) ? 1760 MHP_SHORT_PREAMBLE : MHP_LONG_PREAMBLE); 1761 malo_hal_setassocid(sc->malo_mh, ni->ni_bssid, ni->ni_associd); 1762 malo_hal_set_rate(mh, mode, 1763 tp->ucastrate == IEEE80211_FIXED_RATE_NONE ? 1764 0 : malo_fix2rate(tp->ucastrate)); 1765 } 1766 return 0; 1767} 1768 1769static int 1770malo_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1771 const struct ieee80211_bpf_params *params) 1772{ 1773 struct ieee80211com *ic = ni->ni_ic; 1774 struct malo_softc *sc = ic->ic_softc; 1775 struct malo_txbuf *bf; 1776 struct malo_txq *txq; 1777 1778 if (!sc->malo_running || sc->malo_invalid) { 1779 m_freem(m); 1780 return ENETDOWN; 1781 } 1782 1783 /* 1784 * Grab a TX buffer and associated resources. Note that we depend 1785 * on the classification by the 802.11 layer to get to the right h/w 1786 * queue. Management frames must ALWAYS go on queue 1 but we 1787 * cannot just force that here because we may receive non-mgt frames. 1788 */ 1789 txq = &sc->malo_txq[0]; 1790 bf = malo_getbuf(sc, txq); 1791 if (bf == NULL) { 1792 m_freem(m); 1793 return ENOBUFS; 1794 } 1795 1796 /* 1797 * Pass the frame to the h/w for transmission. 1798 */ 1799 if (malo_tx_start(sc, ni, bf, m) != 0) { 1800 bf->bf_m = NULL; 1801 bf->bf_node = NULL; 1802 MALO_TXQ_LOCK(txq); 1803 STAILQ_INSERT_HEAD(&txq->free, bf, bf_list); 1804 txq->nfree++; 1805 MALO_TXQ_UNLOCK(txq); 1806 1807 return EIO; /* XXX */ 1808 } 1809 1810 /* 1811 * NB: We don't need to lock against tx done because this just 1812 * prods the firmware to check the transmit descriptors. The firmware 1813 * will also start fetching descriptors by itself if it notices 1814 * new ones are present when it goes to deliver a tx done interrupt 1815 * to the host. So if we race with tx done processing it's ok. 1816 * Delivering the kick here rather than in malo_tx_start is 1817 * an optimization to avoid poking the firmware for each packet. 1818 * 1819 * NB: the queue id isn't used so 0 is ok. 1820 */ 1821 malo_hal_txstart(sc->malo_mh, 0/*XXX*/); 1822 1823 return 0; 1824} 1825 1826static void 1827malo_sysctlattach(struct malo_softc *sc) 1828{ 1829#ifdef MALO_DEBUG 1830 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->malo_dev); 1831 struct sysctl_oid *tree = device_get_sysctl_tree(sc->malo_dev); 1832 1833 sc->malo_debug = malo_debug; 1834 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 1835 "debug", CTLFLAG_RW, &sc->malo_debug, 0, 1836 "control debugging printfs"); 1837#endif 1838} 1839 1840static void 1841malo_announce(struct malo_softc *sc) 1842{ 1843 1844 device_printf(sc->malo_dev, 1845 "versions [hw %d fw %d.%d.%d.%d] (regioncode %d)\n", 1846 sc->malo_hwspecs.hwversion, 1847 (sc->malo_hwspecs.fw_releasenum >> 24) & 0xff, 1848 (sc->malo_hwspecs.fw_releasenum >> 16) & 0xff, 1849 (sc->malo_hwspecs.fw_releasenum >> 8) & 0xff, 1850 (sc->malo_hwspecs.fw_releasenum >> 0) & 0xff, 1851 sc->malo_hwspecs.regioncode); 1852 1853 if (bootverbose || malo_rxbuf != MALO_RXBUF) 1854 device_printf(sc->malo_dev, 1855 "using %u rx buffers\n", malo_rxbuf); 1856 if (bootverbose || malo_txbuf != MALO_TXBUF) 1857 device_printf(sc->malo_dev, 1858 "using %u tx buffers\n", malo_txbuf); 1859} 1860 1861/* 1862 * Convert net80211 channel to a HAL channel. 1863 */ 1864static void 1865malo_mapchan(struct malo_hal_channel *hc, const struct ieee80211_channel *chan) 1866{ 1867 hc->channel = chan->ic_ieee; 1868 1869 *(uint32_t *)&hc->flags = 0; 1870 if (IEEE80211_IS_CHAN_2GHZ(chan)) 1871 hc->flags.freqband = MALO_FREQ_BAND_2DOT4GHZ; 1872} 1873 1874/* 1875 * Set/change channels. If the channel is really being changed, 1876 * it's done by reseting the chip. To accomplish this we must 1877 * first cleanup any pending DMA, then restart stuff after a la 1878 * malo_init. 1879 */ 1880static int 1881malo_chan_set(struct malo_softc *sc, struct ieee80211_channel *chan) 1882{ 1883 struct malo_hal *mh = sc->malo_mh; 1884 struct malo_hal_channel hchan; 1885 1886 DPRINTF(sc, MALO_DEBUG_RESET, "%s: chan %u MHz/flags 0x%x\n", 1887 __func__, chan->ic_freq, chan->ic_flags); 1888 1889 /* 1890 * Convert to a HAL channel description with the flags constrained 1891 * to reflect the current operating mode. 1892 */ 1893 malo_mapchan(&hchan, chan); 1894 malo_hal_intrset(mh, 0); /* disable interrupts */ 1895 malo_hal_setchannel(mh, &hchan); 1896 malo_hal_settxpower(mh, &hchan); 1897 1898 /* 1899 * Update internal state. 1900 */ 1901 sc->malo_tx_th.wt_chan_freq = htole16(chan->ic_freq); 1902 sc->malo_rx_th.wr_chan_freq = htole16(chan->ic_freq); 1903 if (IEEE80211_IS_CHAN_ANYG(chan)) { 1904 sc->malo_tx_th.wt_chan_flags = htole16(IEEE80211_CHAN_G); 1905 sc->malo_rx_th.wr_chan_flags = htole16(IEEE80211_CHAN_G); 1906 } else { 1907 sc->malo_tx_th.wt_chan_flags = htole16(IEEE80211_CHAN_B); 1908 sc->malo_rx_th.wr_chan_flags = htole16(IEEE80211_CHAN_B); 1909 } 1910 sc->malo_curchan = hchan; 1911 malo_hal_intrset(mh, sc->malo_imask); 1912 1913 return 0; 1914} 1915 1916static void 1917malo_scan_start(struct ieee80211com *ic) 1918{ 1919 struct malo_softc *sc = ic->ic_softc; 1920 1921 DPRINTF(sc, MALO_DEBUG_STATE, "%s\n", __func__); 1922} 1923 1924static void 1925malo_scan_end(struct ieee80211com *ic) 1926{ 1927 struct malo_softc *sc = ic->ic_softc; 1928 1929 DPRINTF(sc, MALO_DEBUG_STATE, "%s\n", __func__); 1930} 1931 1932static void 1933malo_set_channel(struct ieee80211com *ic) 1934{ 1935 struct malo_softc *sc = ic->ic_softc; 1936 1937 (void) malo_chan_set(sc, ic->ic_curchan); 1938} 1939 1940static void 1941malo_rx_proc(void *arg, int npending) 1942{ 1943 struct malo_softc *sc = arg; 1944 struct ieee80211com *ic = &sc->malo_ic; 1945 struct malo_rxbuf *bf; 1946 struct malo_rxdesc *ds; 1947 struct mbuf *m, *mnew; 1948 struct ieee80211_qosframe *wh; 1949 struct ieee80211_node *ni; 1950 int off, len, hdrlen, pktlen, rssi, ntodo; 1951 uint8_t *data, status; 1952 uint32_t readptr, writeptr; 1953 1954 DPRINTF(sc, MALO_DEBUG_RX_PROC, 1955 "%s: pending %u rdptr(0x%x) 0x%x wrptr(0x%x) 0x%x\n", 1956 __func__, npending, 1957 sc->malo_hwspecs.rxdesc_read, 1958 malo_bar0_read4(sc, sc->malo_hwspecs.rxdesc_read), 1959 sc->malo_hwspecs.rxdesc_write, 1960 malo_bar0_read4(sc, sc->malo_hwspecs.rxdesc_write)); 1961 1962 readptr = malo_bar0_read4(sc, sc->malo_hwspecs.rxdesc_read); 1963 writeptr = malo_bar0_read4(sc, sc->malo_hwspecs.rxdesc_write); 1964 if (readptr == writeptr) 1965 return; 1966 1967 bf = sc->malo_rxnext; 1968 for (ntodo = malo_rxquota; ntodo > 0 && readptr != writeptr; ntodo--) { 1969 if (bf == NULL) { 1970 bf = STAILQ_FIRST(&sc->malo_rxbuf); 1971 break; 1972 } 1973 ds = bf->bf_desc; 1974 if (bf->bf_m == NULL) { 1975 /* 1976 * If data allocation failed previously there 1977 * will be no buffer; try again to re-populate it. 1978 * Note the firmware will not advance to the next 1979 * descriptor with a dma buffer so we must mimic 1980 * this or we'll get out of sync. 1981 */ 1982 DPRINTF(sc, MALO_DEBUG_ANY, 1983 "%s: rx buf w/o dma memory\n", __func__); 1984 (void)malo_rxbuf_init(sc, bf); 1985 break; 1986 } 1987 MALO_RXDESC_SYNC(sc, ds, 1988 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1989 if (ds->rxcontrol != MALO_RXD_CTRL_DMA_OWN) 1990 break; 1991 1992 readptr = le32toh(ds->physnext); 1993 1994#ifdef MALO_DEBUG 1995 if (sc->malo_debug & MALO_DEBUG_RECV_DESC) 1996 malo_printrxbuf(bf, 0); 1997#endif 1998 status = ds->status; 1999 if (status & MALO_RXD_STATUS_DECRYPT_ERR_MASK) { 2000 counter_u64_add(ic->ic_ierrors, 1); 2001 goto rx_next; 2002 } 2003 /* 2004 * Sync the data buffer. 2005 */ 2006 len = le16toh(ds->pktlen); 2007 bus_dmamap_sync(sc->malo_dmat, bf->bf_dmamap, 2008 BUS_DMASYNC_POSTREAD); 2009 /* 2010 * The 802.11 header is provided all or in part at the front; 2011 * use it to calculate the true size of the header that we'll 2012 * construct below. We use this to figure out where to copy 2013 * payload prior to constructing the header. 2014 */ 2015 m = bf->bf_m; 2016 data = mtod(m, uint8_t *); 2017 hdrlen = ieee80211_anyhdrsize(data + sizeof(uint16_t)); 2018 off = sizeof(uint16_t) + sizeof(struct ieee80211_frame_addr4); 2019 2020 /* 2021 * Calculate RSSI. XXX wrong 2022 */ 2023 rssi = 2 * ((int) ds->snr - ds->nf); /* NB: .5 dBm */ 2024 if (rssi > 100) 2025 rssi = 100; 2026 2027 pktlen = hdrlen + (len - off); 2028 /* 2029 * NB: we know our frame is at least as large as 2030 * IEEE80211_MIN_LEN because there is a 4-address frame at 2031 * the front. Hence there's no need to vet the packet length. 2032 * If the frame in fact is too small it should be discarded 2033 * at the net80211 layer. 2034 */ 2035 2036 /* XXX don't need mbuf, just dma buffer */ 2037 mnew = malo_getrxmbuf(sc, bf); 2038 if (mnew == NULL) { 2039 counter_u64_add(ic->ic_ierrors, 1); 2040 goto rx_next; 2041 } 2042 /* 2043 * Attach the dma buffer to the mbuf; malo_rxbuf_init will 2044 * re-setup the rx descriptor using the replacement dma 2045 * buffer we just installed above. 2046 */ 2047 bf->bf_m = mnew; 2048 m->m_data += off - hdrlen; 2049 m->m_pkthdr.len = m->m_len = pktlen; 2050 2051 /* 2052 * Piece 802.11 header together. 2053 */ 2054 wh = mtod(m, struct ieee80211_qosframe *); 2055 /* NB: don't need to do this sometimes but ... */ 2056 /* XXX special case so we can memcpy after m_devget? */ 2057 ovbcopy(data + sizeof(uint16_t), wh, hdrlen); 2058 if (IEEE80211_QOS_HAS_SEQ(wh)) 2059 *(uint16_t *)ieee80211_getqos(wh) = ds->qosctrl; 2060 if (ieee80211_radiotap_active(ic)) { 2061 sc->malo_rx_th.wr_flags = 0; 2062 sc->malo_rx_th.wr_rate = ds->rate; 2063 sc->malo_rx_th.wr_antsignal = rssi; 2064 sc->malo_rx_th.wr_antnoise = ds->nf; 2065 } 2066#ifdef MALO_DEBUG 2067 if (IFF_DUMPPKTS_RECV(sc, wh)) { 2068 ieee80211_dump_pkt(ic, mtod(m, caddr_t), 2069 len, ds->rate, rssi); 2070 } 2071#endif 2072 /* dispatch */ 2073 ni = ieee80211_find_rxnode(ic, 2074 (struct ieee80211_frame_min *)wh); 2075 if (ni != NULL) { 2076 (void) ieee80211_input(ni, m, rssi, ds->nf); 2077 ieee80211_free_node(ni); 2078 } else 2079 (void) ieee80211_input_all(ic, m, rssi, ds->nf); 2080rx_next: 2081 /* NB: ignore ENOMEM so we process more descriptors */ 2082 (void) malo_rxbuf_init(sc, bf); 2083 bf = STAILQ_NEXT(bf, bf_list); 2084 } 2085 2086 malo_bar0_write4(sc, sc->malo_hwspecs.rxdesc_read, readptr); 2087 sc->malo_rxnext = bf; 2088 2089 if (mbufq_first(&sc->malo_snd) != NULL) 2090 malo_start(sc); 2091} 2092 2093/* 2094 * Reclaim all tx queue resources. 2095 */ 2096static void 2097malo_tx_cleanup(struct malo_softc *sc) 2098{ 2099 int i; 2100 2101 for (i = 0; i < MALO_NUM_TX_QUEUES; i++) 2102 malo_tx_cleanupq(sc, &sc->malo_txq[i]); 2103} 2104 2105int 2106malo_detach(struct malo_softc *sc) 2107{ 2108 struct ieee80211com *ic = &sc->malo_ic; 2109 2110 malo_stop(sc); 2111 2112 if (sc->malo_tq != NULL) { 2113 taskqueue_drain(sc->malo_tq, &sc->malo_rxtask); 2114 taskqueue_drain(sc->malo_tq, &sc->malo_txtask); 2115 taskqueue_free(sc->malo_tq); 2116 sc->malo_tq = NULL; 2117 } 2118 2119 /* 2120 * NB: the order of these is important: 2121 * o call the 802.11 layer before detaching the hal to 2122 * insure callbacks into the driver to delete global 2123 * key cache entries can be handled 2124 * o reclaim the tx queue data structures after calling 2125 * the 802.11 layer as we'll get called back to reclaim 2126 * node state and potentially want to use them 2127 * o to cleanup the tx queues the hal is called, so detach 2128 * it last 2129 * Other than that, it's straightforward... 2130 */ 2131 ieee80211_ifdetach(ic); 2132 callout_drain(&sc->malo_watchdog_timer); 2133 malo_dma_cleanup(sc); 2134 malo_tx_cleanup(sc); 2135 malo_hal_detach(sc->malo_mh); 2136 mbufq_drain(&sc->malo_snd); 2137 MALO_LOCK_DESTROY(sc); 2138 2139 return 0; 2140} 2141 2142void 2143malo_shutdown(struct malo_softc *sc) 2144{ 2145 2146 malo_stop(sc); 2147} 2148 2149void 2150malo_suspend(struct malo_softc *sc) 2151{ 2152 2153 malo_stop(sc); 2154} 2155 2156void 2157malo_resume(struct malo_softc *sc) 2158{ 2159 2160 if (sc->malo_ic.ic_nrunning > 0) 2161 malo_init(sc); 2162} 2163