if_jme.c revision 216549
1/*- 2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: head/sys/dev/jme/if_jme.c 216549 2010-12-18 23:24:59Z yongari $"); 30 31#include <sys/param.h> 32#include <sys/systm.h> 33#include <sys/bus.h> 34#include <sys/endian.h> 35#include <sys/kernel.h> 36#include <sys/malloc.h> 37#include <sys/mbuf.h> 38#include <sys/rman.h> 39#include <sys/module.h> 40#include <sys/proc.h> 41#include <sys/queue.h> 42#include <sys/socket.h> 43#include <sys/sockio.h> 44#include <sys/sysctl.h> 45#include <sys/taskqueue.h> 46 47#include <net/bpf.h> 48#include <net/if.h> 49#include <net/if_arp.h> 50#include <net/ethernet.h> 51#include <net/if_dl.h> 52#include <net/if_media.h> 53#include <net/if_types.h> 54#include <net/if_vlan_var.h> 55 56#include <netinet/in.h> 57#include <netinet/in_systm.h> 58#include <netinet/ip.h> 59#include <netinet/tcp.h> 60 61#include <dev/mii/mii.h> 62#include <dev/mii/miivar.h> 63 64#include <dev/pci/pcireg.h> 65#include <dev/pci/pcivar.h> 66 67#include <machine/bus.h> 68#include <machine/in_cksum.h> 69 70#include <dev/jme/if_jmereg.h> 71#include <dev/jme/if_jmevar.h> 72 73/* "device miibus" required. See GENERIC if you get errors here. */ 74#include "miibus_if.h" 75 76/* Define the following to disable printing Rx errors. */ 77#undef JME_SHOW_ERRORS 78 79#define JME_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 80 81MODULE_DEPEND(jme, pci, 1, 1, 1); 82MODULE_DEPEND(jme, ether, 1, 1, 1); 83MODULE_DEPEND(jme, miibus, 1, 1, 1); 84 85/* Tunables. */ 86static int msi_disable = 0; 87static int msix_disable = 0; 88TUNABLE_INT("hw.jme.msi_disable", &msi_disable); 89TUNABLE_INT("hw.jme.msix_disable", &msix_disable); 90 91/* 92 * Devices supported by this driver. 93 */ 94static struct jme_dev { 95 uint16_t jme_vendorid; 96 uint16_t jme_deviceid; 97 const char *jme_name; 98} jme_devs[] = { 99 { VENDORID_JMICRON, DEVICEID_JMC250, 100 "JMicron Inc, JMC250 Gigabit Ethernet" }, 101 { VENDORID_JMICRON, DEVICEID_JMC260, 102 "JMicron Inc, JMC260 Fast Ethernet" }, 103}; 104 105static int jme_miibus_readreg(device_t, int, int); 106static int jme_miibus_writereg(device_t, int, int, int); 107static void jme_miibus_statchg(device_t); 108static void jme_mediastatus(struct ifnet *, struct ifmediareq *); 109static int jme_mediachange(struct ifnet *); 110static int jme_probe(device_t); 111static int jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *); 112static int jme_eeprom_macaddr(struct jme_softc *); 113static void jme_reg_macaddr(struct jme_softc *); 114static void jme_map_intr_vector(struct jme_softc *); 115static int jme_attach(device_t); 116static int jme_detach(device_t); 117static void jme_sysctl_node(struct jme_softc *); 118static void jme_dmamap_cb(void *, bus_dma_segment_t *, int, int); 119static int jme_dma_alloc(struct jme_softc *); 120static void jme_dma_free(struct jme_softc *); 121static int jme_shutdown(device_t); 122static void jme_setlinkspeed(struct jme_softc *); 123static void jme_setwol(struct jme_softc *); 124static int jme_suspend(device_t); 125static int jme_resume(device_t); 126static int jme_encap(struct jme_softc *, struct mbuf **); 127static void jme_tx_task(void *, int); 128static void jme_start(struct ifnet *); 129static void jme_watchdog(struct jme_softc *); 130static int jme_ioctl(struct ifnet *, u_long, caddr_t); 131static void jme_mac_config(struct jme_softc *); 132static void jme_link_task(void *, int); 133static int jme_intr(void *); 134static void jme_int_task(void *, int); 135static void jme_txeof(struct jme_softc *); 136static __inline void jme_discard_rxbuf(struct jme_softc *, int); 137static void jme_rxeof(struct jme_softc *); 138static int jme_rxintr(struct jme_softc *, int); 139static void jme_tick(void *); 140static void jme_reset(struct jme_softc *); 141static void jme_init(void *); 142static void jme_init_locked(struct jme_softc *); 143static void jme_stop(struct jme_softc *); 144static void jme_stop_tx(struct jme_softc *); 145static void jme_stop_rx(struct jme_softc *); 146static int jme_init_rx_ring(struct jme_softc *); 147static void jme_init_tx_ring(struct jme_softc *); 148static void jme_init_ssb(struct jme_softc *); 149static int jme_newbuf(struct jme_softc *, struct jme_rxdesc *); 150static void jme_set_vlan(struct jme_softc *); 151static void jme_set_filter(struct jme_softc *); 152static void jme_stats_clear(struct jme_softc *); 153static void jme_stats_save(struct jme_softc *); 154static void jme_stats_update(struct jme_softc *); 155static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 156static int sysctl_hw_jme_tx_coal_to(SYSCTL_HANDLER_ARGS); 157static int sysctl_hw_jme_tx_coal_pkt(SYSCTL_HANDLER_ARGS); 158static int sysctl_hw_jme_rx_coal_to(SYSCTL_HANDLER_ARGS); 159static int sysctl_hw_jme_rx_coal_pkt(SYSCTL_HANDLER_ARGS); 160static int sysctl_hw_jme_proc_limit(SYSCTL_HANDLER_ARGS); 161 162 163static device_method_t jme_methods[] = { 164 /* Device interface. */ 165 DEVMETHOD(device_probe, jme_probe), 166 DEVMETHOD(device_attach, jme_attach), 167 DEVMETHOD(device_detach, jme_detach), 168 DEVMETHOD(device_shutdown, jme_shutdown), 169 DEVMETHOD(device_suspend, jme_suspend), 170 DEVMETHOD(device_resume, jme_resume), 171 172 /* MII interface. */ 173 DEVMETHOD(miibus_readreg, jme_miibus_readreg), 174 DEVMETHOD(miibus_writereg, jme_miibus_writereg), 175 DEVMETHOD(miibus_statchg, jme_miibus_statchg), 176 177 { NULL, NULL } 178}; 179 180static driver_t jme_driver = { 181 "jme", 182 jme_methods, 183 sizeof(struct jme_softc) 184}; 185 186static devclass_t jme_devclass; 187 188DRIVER_MODULE(jme, pci, jme_driver, jme_devclass, 0, 0); 189DRIVER_MODULE(miibus, jme, miibus_driver, miibus_devclass, 0, 0); 190 191static struct resource_spec jme_res_spec_mem[] = { 192 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 193 { -1, 0, 0 } 194}; 195 196static struct resource_spec jme_irq_spec_legacy[] = { 197 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 198 { -1, 0, 0 } 199}; 200 201static struct resource_spec jme_irq_spec_msi[] = { 202 { SYS_RES_IRQ, 1, RF_ACTIVE }, 203 { -1, 0, 0 } 204}; 205 206/* 207 * Read a PHY register on the MII of the JMC250. 208 */ 209static int 210jme_miibus_readreg(device_t dev, int phy, int reg) 211{ 212 struct jme_softc *sc; 213 uint32_t val; 214 int i; 215 216 sc = device_get_softc(dev); 217 218 /* For FPGA version, PHY address 0 should be ignored. */ 219 if ((sc->jme_flags & JME_FLAG_FPGA) != 0 && phy == 0) 220 return (0); 221 222 CSR_WRITE_4(sc, JME_SMI, SMI_OP_READ | SMI_OP_EXECUTE | 223 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg)); 224 for (i = JME_PHY_TIMEOUT; i > 0; i--) { 225 DELAY(1); 226 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0) 227 break; 228 } 229 230 if (i == 0) { 231 device_printf(sc->jme_dev, "phy read timeout : %d\n", reg); 232 return (0); 233 } 234 235 return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT); 236} 237 238/* 239 * Write a PHY register on the MII of the JMC250. 240 */ 241static int 242jme_miibus_writereg(device_t dev, int phy, int reg, int val) 243{ 244 struct jme_softc *sc; 245 int i; 246 247 sc = device_get_softc(dev); 248 249 /* For FPGA version, PHY address 0 should be ignored. */ 250 if ((sc->jme_flags & JME_FLAG_FPGA) != 0 && phy == 0) 251 return (0); 252 253 CSR_WRITE_4(sc, JME_SMI, SMI_OP_WRITE | SMI_OP_EXECUTE | 254 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) | 255 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg)); 256 for (i = JME_PHY_TIMEOUT; i > 0; i--) { 257 DELAY(1); 258 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0) 259 break; 260 } 261 262 if (i == 0) 263 device_printf(sc->jme_dev, "phy write timeout : %d\n", reg); 264 265 return (0); 266} 267 268/* 269 * Callback from MII layer when media changes. 270 */ 271static void 272jme_miibus_statchg(device_t dev) 273{ 274 struct jme_softc *sc; 275 276 sc = device_get_softc(dev); 277 taskqueue_enqueue(taskqueue_swi, &sc->jme_link_task); 278} 279 280/* 281 * Get the current interface media status. 282 */ 283static void 284jme_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 285{ 286 struct jme_softc *sc; 287 struct mii_data *mii; 288 289 sc = ifp->if_softc; 290 JME_LOCK(sc); 291 if ((ifp->if_flags & IFF_UP) == 0) { 292 JME_UNLOCK(sc); 293 return; 294 } 295 mii = device_get_softc(sc->jme_miibus); 296 297 mii_pollstat(mii); 298 ifmr->ifm_status = mii->mii_media_status; 299 ifmr->ifm_active = mii->mii_media_active; 300 JME_UNLOCK(sc); 301} 302 303/* 304 * Set hardware to newly-selected media. 305 */ 306static int 307jme_mediachange(struct ifnet *ifp) 308{ 309 struct jme_softc *sc; 310 struct mii_data *mii; 311 struct mii_softc *miisc; 312 int error; 313 314 sc = ifp->if_softc; 315 JME_LOCK(sc); 316 mii = device_get_softc(sc->jme_miibus); 317 if (mii->mii_instance != 0) { 318 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 319 mii_phy_reset(miisc); 320 } 321 error = mii_mediachg(mii); 322 JME_UNLOCK(sc); 323 324 return (error); 325} 326 327static int 328jme_probe(device_t dev) 329{ 330 struct jme_dev *sp; 331 int i; 332 uint16_t vendor, devid; 333 334 vendor = pci_get_vendor(dev); 335 devid = pci_get_device(dev); 336 sp = jme_devs; 337 for (i = 0; i < sizeof(jme_devs) / sizeof(jme_devs[0]); 338 i++, sp++) { 339 if (vendor == sp->jme_vendorid && 340 devid == sp->jme_deviceid) { 341 device_set_desc(dev, sp->jme_name); 342 return (BUS_PROBE_DEFAULT); 343 } 344 } 345 346 return (ENXIO); 347} 348 349static int 350jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val) 351{ 352 uint32_t reg; 353 int i; 354 355 *val = 0; 356 for (i = JME_TIMEOUT; i > 0; i--) { 357 reg = CSR_READ_4(sc, JME_SMBCSR); 358 if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE) 359 break; 360 DELAY(1); 361 } 362 363 if (i == 0) { 364 device_printf(sc->jme_dev, "EEPROM idle timeout!\n"); 365 return (ETIMEDOUT); 366 } 367 368 reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK; 369 CSR_WRITE_4(sc, JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER); 370 for (i = JME_TIMEOUT; i > 0; i--) { 371 DELAY(1); 372 reg = CSR_READ_4(sc, JME_SMBINTF); 373 if ((reg & SMBINTF_CMD_TRIGGER) == 0) 374 break; 375 } 376 377 if (i == 0) { 378 device_printf(sc->jme_dev, "EEPROM read timeout!\n"); 379 return (ETIMEDOUT); 380 } 381 382 reg = CSR_READ_4(sc, JME_SMBINTF); 383 *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT; 384 385 return (0); 386} 387 388static int 389jme_eeprom_macaddr(struct jme_softc *sc) 390{ 391 uint8_t eaddr[ETHER_ADDR_LEN]; 392 uint8_t fup, reg, val; 393 uint32_t offset; 394 int match; 395 396 offset = 0; 397 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 || 398 fup != JME_EEPROM_SIG0) 399 return (ENOENT); 400 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 || 401 fup != JME_EEPROM_SIG1) 402 return (ENOENT); 403 match = 0; 404 do { 405 if (jme_eeprom_read_byte(sc, offset, &fup) != 0) 406 break; 407 if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1) == 408 (fup & (JME_EEPROM_FUNC_MASK | JME_EEPROM_PAGE_MASK))) { 409 if (jme_eeprom_read_byte(sc, offset + 1, ®) != 0) 410 break; 411 if (reg >= JME_PAR0 && 412 reg < JME_PAR0 + ETHER_ADDR_LEN) { 413 if (jme_eeprom_read_byte(sc, offset + 2, 414 &val) != 0) 415 break; 416 eaddr[reg - JME_PAR0] = val; 417 match++; 418 } 419 } 420 /* Check for the end of EEPROM descriptor. */ 421 if ((fup & JME_EEPROM_DESC_END) == JME_EEPROM_DESC_END) 422 break; 423 /* Try next eeprom descriptor. */ 424 offset += JME_EEPROM_DESC_BYTES; 425 } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END); 426 427 if (match == ETHER_ADDR_LEN) { 428 bcopy(eaddr, sc->jme_eaddr, ETHER_ADDR_LEN); 429 return (0); 430 } 431 432 return (ENOENT); 433} 434 435static void 436jme_reg_macaddr(struct jme_softc *sc) 437{ 438 uint32_t par0, par1; 439 440 /* Read station address. */ 441 par0 = CSR_READ_4(sc, JME_PAR0); 442 par1 = CSR_READ_4(sc, JME_PAR1); 443 par1 &= 0xFFFF; 444 if ((par0 == 0 && par1 == 0) || 445 (par0 == 0xFFFFFFFF && par1 == 0xFFFF)) { 446 device_printf(sc->jme_dev, 447 "Failed to retrieve Ethernet address.\n"); 448 } else { 449 sc->jme_eaddr[0] = (par0 >> 0) & 0xFF; 450 sc->jme_eaddr[1] = (par0 >> 8) & 0xFF; 451 sc->jme_eaddr[2] = (par0 >> 16) & 0xFF; 452 sc->jme_eaddr[3] = (par0 >> 24) & 0xFF; 453 sc->jme_eaddr[4] = (par1 >> 0) & 0xFF; 454 sc->jme_eaddr[5] = (par1 >> 8) & 0xFF; 455 } 456} 457 458static void 459jme_map_intr_vector(struct jme_softc *sc) 460{ 461 uint32_t map[MSINUM_NUM_INTR_SOURCE / JME_MSI_MESSAGES]; 462 463 bzero(map, sizeof(map)); 464 465 /* Map Tx interrupts source to MSI/MSIX vector 2. */ 466 map[MSINUM_REG_INDEX(N_INTR_TXQ0_COMP)] = 467 MSINUM_INTR_SOURCE(2, N_INTR_TXQ0_COMP); 468 map[MSINUM_REG_INDEX(N_INTR_TXQ1_COMP)] |= 469 MSINUM_INTR_SOURCE(2, N_INTR_TXQ1_COMP); 470 map[MSINUM_REG_INDEX(N_INTR_TXQ2_COMP)] |= 471 MSINUM_INTR_SOURCE(2, N_INTR_TXQ2_COMP); 472 map[MSINUM_REG_INDEX(N_INTR_TXQ3_COMP)] |= 473 MSINUM_INTR_SOURCE(2, N_INTR_TXQ3_COMP); 474 map[MSINUM_REG_INDEX(N_INTR_TXQ4_COMP)] |= 475 MSINUM_INTR_SOURCE(2, N_INTR_TXQ4_COMP); 476 map[MSINUM_REG_INDEX(N_INTR_TXQ4_COMP)] |= 477 MSINUM_INTR_SOURCE(2, N_INTR_TXQ5_COMP); 478 map[MSINUM_REG_INDEX(N_INTR_TXQ6_COMP)] |= 479 MSINUM_INTR_SOURCE(2, N_INTR_TXQ6_COMP); 480 map[MSINUM_REG_INDEX(N_INTR_TXQ7_COMP)] |= 481 MSINUM_INTR_SOURCE(2, N_INTR_TXQ7_COMP); 482 map[MSINUM_REG_INDEX(N_INTR_TXQ_COAL)] |= 483 MSINUM_INTR_SOURCE(2, N_INTR_TXQ_COAL); 484 map[MSINUM_REG_INDEX(N_INTR_TXQ_COAL_TO)] |= 485 MSINUM_INTR_SOURCE(2, N_INTR_TXQ_COAL_TO); 486 487 /* Map Rx interrupts source to MSI/MSIX vector 1. */ 488 map[MSINUM_REG_INDEX(N_INTR_RXQ0_COMP)] = 489 MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COMP); 490 map[MSINUM_REG_INDEX(N_INTR_RXQ1_COMP)] = 491 MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COMP); 492 map[MSINUM_REG_INDEX(N_INTR_RXQ2_COMP)] = 493 MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COMP); 494 map[MSINUM_REG_INDEX(N_INTR_RXQ3_COMP)] = 495 MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COMP); 496 map[MSINUM_REG_INDEX(N_INTR_RXQ0_DESC_EMPTY)] = 497 MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_DESC_EMPTY); 498 map[MSINUM_REG_INDEX(N_INTR_RXQ1_DESC_EMPTY)] = 499 MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_DESC_EMPTY); 500 map[MSINUM_REG_INDEX(N_INTR_RXQ2_DESC_EMPTY)] = 501 MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_DESC_EMPTY); 502 map[MSINUM_REG_INDEX(N_INTR_RXQ3_DESC_EMPTY)] = 503 MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_DESC_EMPTY); 504 map[MSINUM_REG_INDEX(N_INTR_RXQ0_COAL)] = 505 MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COAL); 506 map[MSINUM_REG_INDEX(N_INTR_RXQ1_COAL)] = 507 MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COAL); 508 map[MSINUM_REG_INDEX(N_INTR_RXQ2_COAL)] = 509 MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COAL); 510 map[MSINUM_REG_INDEX(N_INTR_RXQ3_COAL)] = 511 MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COAL); 512 map[MSINUM_REG_INDEX(N_INTR_RXQ0_COAL_TO)] = 513 MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COAL_TO); 514 map[MSINUM_REG_INDEX(N_INTR_RXQ1_COAL_TO)] = 515 MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COAL_TO); 516 map[MSINUM_REG_INDEX(N_INTR_RXQ2_COAL_TO)] = 517 MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COAL_TO); 518 map[MSINUM_REG_INDEX(N_INTR_RXQ3_COAL_TO)] = 519 MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COAL_TO); 520 521 /* Map all other interrupts source to MSI/MSIX vector 0. */ 522 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 0, map[0]); 523 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 1, map[1]); 524 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 2, map[2]); 525 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 3, map[3]); 526} 527 528static int 529jme_attach(device_t dev) 530{ 531 struct jme_softc *sc; 532 struct ifnet *ifp; 533 struct mii_softc *miisc; 534 struct mii_data *mii; 535 uint32_t reg; 536 uint16_t burst; 537 int error, i, msic, msixc, pmc; 538 539 error = 0; 540 sc = device_get_softc(dev); 541 sc->jme_dev = dev; 542 543 mtx_init(&sc->jme_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 544 MTX_DEF); 545 callout_init_mtx(&sc->jme_tick_ch, &sc->jme_mtx, 0); 546 TASK_INIT(&sc->jme_int_task, 0, jme_int_task, sc); 547 TASK_INIT(&sc->jme_link_task, 0, jme_link_task, sc); 548 549 /* 550 * Map the device. JMC250 supports both memory mapped and I/O 551 * register space access. Because I/O register access should 552 * use different BARs to access registers it's waste of time 553 * to use I/O register spce access. JMC250 uses 16K to map 554 * entire memory space. 555 */ 556 pci_enable_busmaster(dev); 557 sc->jme_res_spec = jme_res_spec_mem; 558 sc->jme_irq_spec = jme_irq_spec_legacy; 559 error = bus_alloc_resources(dev, sc->jme_res_spec, sc->jme_res); 560 if (error != 0) { 561 device_printf(dev, "cannot allocate memory resources.\n"); 562 goto fail; 563 } 564 565 /* Allocate IRQ resources. */ 566 msixc = pci_msix_count(dev); 567 msic = pci_msi_count(dev); 568 if (bootverbose) { 569 device_printf(dev, "MSIX count : %d\n", msixc); 570 device_printf(dev, "MSI count : %d\n", msic); 571 } 572 573 /* Use 1 MSI/MSI-X. */ 574 if (msixc > 1) 575 msixc = 1; 576 if (msic > 1) 577 msic = 1; 578 /* Prefer MSIX over MSI. */ 579 if (msix_disable == 0 || msi_disable == 0) { 580 if (msix_disable == 0 && msixc > 0 && 581 pci_alloc_msix(dev, &msixc) == 0) { 582 if (msixc == 1) { 583 device_printf(dev, "Using %d MSIX messages.\n", 584 msixc); 585 sc->jme_flags |= JME_FLAG_MSIX; 586 sc->jme_irq_spec = jme_irq_spec_msi; 587 } else 588 pci_release_msi(dev); 589 } 590 if (msi_disable == 0 && (sc->jme_flags & JME_FLAG_MSIX) == 0 && 591 msic > 0 && pci_alloc_msi(dev, &msic) == 0) { 592 if (msic == 1) { 593 device_printf(dev, "Using %d MSI messages.\n", 594 msic); 595 sc->jme_flags |= JME_FLAG_MSI; 596 sc->jme_irq_spec = jme_irq_spec_msi; 597 } else 598 pci_release_msi(dev); 599 } 600 /* Map interrupt vector 0, 1 and 2. */ 601 if ((sc->jme_flags & JME_FLAG_MSI) != 0 || 602 (sc->jme_flags & JME_FLAG_MSIX) != 0) 603 jme_map_intr_vector(sc); 604 } 605 606 error = bus_alloc_resources(dev, sc->jme_irq_spec, sc->jme_irq); 607 if (error != 0) { 608 device_printf(dev, "cannot allocate IRQ resources.\n"); 609 goto fail; 610 } 611 612 sc->jme_rev = pci_get_device(dev); 613 if ((sc->jme_rev & DEVICEID_JMC2XX_MASK) == DEVICEID_JMC260) { 614 sc->jme_flags |= JME_FLAG_FASTETH; 615 sc->jme_flags |= JME_FLAG_NOJUMBO; 616 } 617 reg = CSR_READ_4(sc, JME_CHIPMODE); 618 sc->jme_chip_rev = (reg & CHIPMODE_REV_MASK) >> CHIPMODE_REV_SHIFT; 619 if (((reg & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) != 620 CHIPMODE_NOT_FPGA) 621 sc->jme_flags |= JME_FLAG_FPGA; 622 if (bootverbose) { 623 device_printf(dev, "PCI device revision : 0x%04x\n", 624 sc->jme_rev); 625 device_printf(dev, "Chip revision : 0x%02x\n", 626 sc->jme_chip_rev); 627 if ((sc->jme_flags & JME_FLAG_FPGA) != 0) 628 device_printf(dev, "FPGA revision : 0x%04x\n", 629 (reg & CHIPMODE_FPGA_REV_MASK) >> 630 CHIPMODE_FPGA_REV_SHIFT); 631 } 632 if (sc->jme_chip_rev == 0xFF) { 633 device_printf(dev, "Unknown chip revision : 0x%02x\n", 634 sc->jme_rev); 635 error = ENXIO; 636 goto fail; 637 } 638 639 if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 2) { 640 if ((sc->jme_rev & DEVICEID_JMC2XX_MASK) == DEVICEID_JMC260 && 641 CHIPMODE_REVFM(sc->jme_chip_rev) == 2) 642 sc->jme_flags |= JME_FLAG_DMA32BIT; 643 sc->jme_flags |= JME_FLAG_TXCLK; 644 sc->jme_flags |= JME_FLAG_HWMIB; 645 } 646 647 /* Reset the ethernet controller. */ 648 jme_reset(sc); 649 650 /* Get station address. */ 651 reg = CSR_READ_4(sc, JME_SMBCSR); 652 if ((reg & SMBCSR_EEPROM_PRESENT) != 0) 653 error = jme_eeprom_macaddr(sc); 654 if (error != 0 || (reg & SMBCSR_EEPROM_PRESENT) == 0) { 655 if (error != 0 && (bootverbose)) 656 device_printf(sc->jme_dev, 657 "ethernet hardware address not found in EEPROM.\n"); 658 jme_reg_macaddr(sc); 659 } 660 661 /* 662 * Save PHY address. 663 * Integrated JR0211 has fixed PHY address whereas FPGA version 664 * requires PHY probing to get correct PHY address. 665 */ 666 if ((sc->jme_flags & JME_FLAG_FPGA) == 0) { 667 sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) & 668 GPREG0_PHY_ADDR_MASK; 669 if (bootverbose) 670 device_printf(dev, "PHY is at address %d.\n", 671 sc->jme_phyaddr); 672 } else 673 sc->jme_phyaddr = 0; 674 675 /* Set max allowable DMA size. */ 676 if (pci_find_extcap(dev, PCIY_EXPRESS, &i) == 0) { 677 sc->jme_flags |= JME_FLAG_PCIE; 678 burst = pci_read_config(dev, i + 0x08, 2); 679 if (bootverbose) { 680 device_printf(dev, "Read request size : %d bytes.\n", 681 128 << ((burst >> 12) & 0x07)); 682 device_printf(dev, "TLP payload size : %d bytes.\n", 683 128 << ((burst >> 5) & 0x07)); 684 } 685 switch ((burst >> 12) & 0x07) { 686 case 0: 687 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_128; 688 break; 689 case 1: 690 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_256; 691 break; 692 default: 693 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512; 694 break; 695 } 696 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128; 697 } else { 698 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512; 699 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128; 700 } 701 /* Create coalescing sysctl node. */ 702 jme_sysctl_node(sc); 703 if ((error = jme_dma_alloc(sc) != 0)) 704 goto fail; 705 706 ifp = sc->jme_ifp = if_alloc(IFT_ETHER); 707 if (ifp == NULL) { 708 device_printf(dev, "cannot allocate ifnet structure.\n"); 709 error = ENXIO; 710 goto fail; 711 } 712 713 ifp->if_softc = sc; 714 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 715 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 716 ifp->if_ioctl = jme_ioctl; 717 ifp->if_start = jme_start; 718 ifp->if_init = jme_init; 719 ifp->if_snd.ifq_drv_maxlen = JME_TX_RING_CNT - 1; 720 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 721 IFQ_SET_READY(&ifp->if_snd); 722 /* JMC250 supports Tx/Rx checksum offload as well as TSO. */ 723 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4; 724 ifp->if_hwassist = JME_CSUM_FEATURES | CSUM_TSO; 725 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) { 726 sc->jme_flags |= JME_FLAG_PMCAP; 727 ifp->if_capabilities |= IFCAP_WOL_MAGIC; 728 } 729 ifp->if_capenable = ifp->if_capabilities; 730 731 /* Set up MII bus. */ 732 error = mii_attach(dev, &sc->jme_miibus, ifp, jme_mediachange, 733 jme_mediastatus, BMSR_DEFCAPMASK, 734 sc->jme_flags & JME_FLAG_FPGA ? MII_PHY_ANY : sc->jme_phyaddr, 735 MII_OFFSET_ANY, MIIF_DOPAUSE); 736 if (error != 0) { 737 device_printf(dev, "attaching PHYs failed\n"); 738 goto fail; 739 } 740 741 /* 742 * Force PHY to FPGA mode. 743 */ 744 if ((sc->jme_flags & JME_FLAG_FPGA) != 0) { 745 mii = device_get_softc(sc->jme_miibus); 746 if (mii->mii_instance != 0) { 747 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) { 748 if (miisc->mii_phy != 0) { 749 sc->jme_phyaddr = miisc->mii_phy; 750 break; 751 } 752 } 753 if (sc->jme_phyaddr != 0) { 754 device_printf(sc->jme_dev, 755 "FPGA PHY is at %d\n", sc->jme_phyaddr); 756 /* vendor magic. */ 757 jme_miibus_writereg(dev, sc->jme_phyaddr, 27, 758 0x0004); 759 } 760 } 761 } 762 763 ether_ifattach(ifp, sc->jme_eaddr); 764 765 /* VLAN capability setup */ 766 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 767 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO; 768 ifp->if_capenable = ifp->if_capabilities; 769 770 /* Tell the upper layer(s) we support long frames. */ 771 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 772 773 /* Create local taskq. */ 774 TASK_INIT(&sc->jme_tx_task, 1, jme_tx_task, ifp); 775 sc->jme_tq = taskqueue_create_fast("jme_taskq", M_WAITOK, 776 taskqueue_thread_enqueue, &sc->jme_tq); 777 if (sc->jme_tq == NULL) { 778 device_printf(dev, "could not create taskqueue.\n"); 779 ether_ifdetach(ifp); 780 error = ENXIO; 781 goto fail; 782 } 783 taskqueue_start_threads(&sc->jme_tq, 1, PI_NET, "%s taskq", 784 device_get_nameunit(sc->jme_dev)); 785 786 for (i = 0; i < 1; i++) { 787 error = bus_setup_intr(dev, sc->jme_irq[i], 788 INTR_TYPE_NET | INTR_MPSAFE, jme_intr, NULL, sc, 789 &sc->jme_intrhand[i]); 790 if (error != 0) 791 break; 792 } 793 794 if (error != 0) { 795 device_printf(dev, "could not set up interrupt handler.\n"); 796 taskqueue_free(sc->jme_tq); 797 sc->jme_tq = NULL; 798 ether_ifdetach(ifp); 799 goto fail; 800 } 801 802fail: 803 if (error != 0) 804 jme_detach(dev); 805 806 return (error); 807} 808 809static int 810jme_detach(device_t dev) 811{ 812 struct jme_softc *sc; 813 struct ifnet *ifp; 814 int i; 815 816 sc = device_get_softc(dev); 817 818 ifp = sc->jme_ifp; 819 if (device_is_attached(dev)) { 820 JME_LOCK(sc); 821 sc->jme_flags |= JME_FLAG_DETACH; 822 jme_stop(sc); 823 JME_UNLOCK(sc); 824 callout_drain(&sc->jme_tick_ch); 825 taskqueue_drain(sc->jme_tq, &sc->jme_int_task); 826 taskqueue_drain(sc->jme_tq, &sc->jme_tx_task); 827 taskqueue_drain(taskqueue_swi, &sc->jme_link_task); 828 ether_ifdetach(ifp); 829 } 830 831 if (sc->jme_tq != NULL) { 832 taskqueue_drain(sc->jme_tq, &sc->jme_int_task); 833 taskqueue_free(sc->jme_tq); 834 sc->jme_tq = NULL; 835 } 836 837 if (sc->jme_miibus != NULL) { 838 device_delete_child(dev, sc->jme_miibus); 839 sc->jme_miibus = NULL; 840 } 841 bus_generic_detach(dev); 842 jme_dma_free(sc); 843 844 if (ifp != NULL) { 845 if_free(ifp); 846 sc->jme_ifp = NULL; 847 } 848 849 for (i = 0; i < 1; i++) { 850 if (sc->jme_intrhand[i] != NULL) { 851 bus_teardown_intr(dev, sc->jme_irq[i], 852 sc->jme_intrhand[i]); 853 sc->jme_intrhand[i] = NULL; 854 } 855 } 856 857 if (sc->jme_irq[0] != NULL) 858 bus_release_resources(dev, sc->jme_irq_spec, sc->jme_irq); 859 if ((sc->jme_flags & (JME_FLAG_MSIX | JME_FLAG_MSI)) != 0) 860 pci_release_msi(dev); 861 if (sc->jme_res[0] != NULL) 862 bus_release_resources(dev, sc->jme_res_spec, sc->jme_res); 863 mtx_destroy(&sc->jme_mtx); 864 865 return (0); 866} 867 868#define JME_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 869 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 870 871static void 872jme_sysctl_node(struct jme_softc *sc) 873{ 874 struct sysctl_ctx_list *ctx; 875 struct sysctl_oid_list *child, *parent; 876 struct sysctl_oid *tree; 877 struct jme_hw_stats *stats; 878 int error; 879 880 stats = &sc->jme_stats; 881 ctx = device_get_sysctl_ctx(sc->jme_dev); 882 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->jme_dev)); 883 884 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "tx_coal_to", 885 CTLTYPE_INT | CTLFLAG_RW, &sc->jme_tx_coal_to, 0, 886 sysctl_hw_jme_tx_coal_to, "I", "jme tx coalescing timeout"); 887 888 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "tx_coal_pkt", 889 CTLTYPE_INT | CTLFLAG_RW, &sc->jme_tx_coal_pkt, 0, 890 sysctl_hw_jme_tx_coal_pkt, "I", "jme tx coalescing packet"); 891 892 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_coal_to", 893 CTLTYPE_INT | CTLFLAG_RW, &sc->jme_rx_coal_to, 0, 894 sysctl_hw_jme_rx_coal_to, "I", "jme rx coalescing timeout"); 895 896 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_coal_pkt", 897 CTLTYPE_INT | CTLFLAG_RW, &sc->jme_rx_coal_pkt, 0, 898 sysctl_hw_jme_rx_coal_pkt, "I", "jme rx coalescing packet"); 899 900 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 901 CTLTYPE_INT | CTLFLAG_RW, &sc->jme_process_limit, 0, 902 sysctl_hw_jme_proc_limit, "I", 903 "max number of Rx events to process"); 904 905 /* Pull in device tunables. */ 906 sc->jme_process_limit = JME_PROC_DEFAULT; 907 error = resource_int_value(device_get_name(sc->jme_dev), 908 device_get_unit(sc->jme_dev), "process_limit", 909 &sc->jme_process_limit); 910 if (error == 0) { 911 if (sc->jme_process_limit < JME_PROC_MIN || 912 sc->jme_process_limit > JME_PROC_MAX) { 913 device_printf(sc->jme_dev, 914 "process_limit value out of range; " 915 "using default: %d\n", JME_PROC_DEFAULT); 916 sc->jme_process_limit = JME_PROC_DEFAULT; 917 } 918 } 919 920 sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT; 921 error = resource_int_value(device_get_name(sc->jme_dev), 922 device_get_unit(sc->jme_dev), "tx_coal_to", &sc->jme_tx_coal_to); 923 if (error == 0) { 924 if (sc->jme_tx_coal_to < PCCTX_COAL_TO_MIN || 925 sc->jme_tx_coal_to > PCCTX_COAL_TO_MAX) { 926 device_printf(sc->jme_dev, 927 "tx_coal_to value out of range; " 928 "using default: %d\n", PCCTX_COAL_TO_DEFAULT); 929 sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT; 930 } 931 } 932 933 sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT; 934 error = resource_int_value(device_get_name(sc->jme_dev), 935 device_get_unit(sc->jme_dev), "tx_coal_pkt", &sc->jme_tx_coal_to); 936 if (error == 0) { 937 if (sc->jme_tx_coal_pkt < PCCTX_COAL_PKT_MIN || 938 sc->jme_tx_coal_pkt > PCCTX_COAL_PKT_MAX) { 939 device_printf(sc->jme_dev, 940 "tx_coal_pkt value out of range; " 941 "using default: %d\n", PCCTX_COAL_PKT_DEFAULT); 942 sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT; 943 } 944 } 945 946 sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT; 947 error = resource_int_value(device_get_name(sc->jme_dev), 948 device_get_unit(sc->jme_dev), "rx_coal_to", &sc->jme_rx_coal_to); 949 if (error == 0) { 950 if (sc->jme_rx_coal_to < PCCRX_COAL_TO_MIN || 951 sc->jme_rx_coal_to > PCCRX_COAL_TO_MAX) { 952 device_printf(sc->jme_dev, 953 "rx_coal_to value out of range; " 954 "using default: %d\n", PCCRX_COAL_TO_DEFAULT); 955 sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT; 956 } 957 } 958 959 sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT; 960 error = resource_int_value(device_get_name(sc->jme_dev), 961 device_get_unit(sc->jme_dev), "rx_coal_pkt", &sc->jme_rx_coal_to); 962 if (error == 0) { 963 if (sc->jme_rx_coal_pkt < PCCRX_COAL_PKT_MIN || 964 sc->jme_rx_coal_pkt > PCCRX_COAL_PKT_MAX) { 965 device_printf(sc->jme_dev, 966 "tx_coal_pkt value out of range; " 967 "using default: %d\n", PCCRX_COAL_PKT_DEFAULT); 968 sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT; 969 } 970 } 971 972 if ((sc->jme_flags & JME_FLAG_HWMIB) == 0) 973 return; 974 975 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 976 NULL, "JME statistics"); 977 parent = SYSCTL_CHILDREN(tree); 978 979 /* Rx statistics. */ 980 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 981 NULL, "Rx MAC statistics"); 982 child = SYSCTL_CHILDREN(tree); 983 JME_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 984 &stats->rx_good_frames, "Good frames"); 985 JME_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 986 &stats->rx_crc_errs, "CRC errors"); 987 JME_SYSCTL_STAT_ADD32(ctx, child, "mii_errs", 988 &stats->rx_mii_errs, "MII errors"); 989 JME_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 990 &stats->rx_fifo_oflows, "FIFO overflows"); 991 JME_SYSCTL_STAT_ADD32(ctx, child, "desc_empty", 992 &stats->rx_desc_empty, "Descriptor empty"); 993 JME_SYSCTL_STAT_ADD32(ctx, child, "bad_frames", 994 &stats->rx_bad_frames, "Bad frames"); 995 996 /* Tx statistics. */ 997 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 998 NULL, "Tx MAC statistics"); 999 child = SYSCTL_CHILDREN(tree); 1000 JME_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1001 &stats->tx_good_frames, "Good frames"); 1002 JME_SYSCTL_STAT_ADD32(ctx, child, "bad_frames", 1003 &stats->tx_bad_frames, "Bad frames"); 1004} 1005 1006#undef JME_SYSCTL_STAT_ADD32 1007 1008struct jme_dmamap_arg { 1009 bus_addr_t jme_busaddr; 1010}; 1011 1012static void 1013jme_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1014{ 1015 struct jme_dmamap_arg *ctx; 1016 1017 if (error != 0) 1018 return; 1019 1020 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1021 1022 ctx = (struct jme_dmamap_arg *)arg; 1023 ctx->jme_busaddr = segs[0].ds_addr; 1024} 1025 1026static int 1027jme_dma_alloc(struct jme_softc *sc) 1028{ 1029 struct jme_dmamap_arg ctx; 1030 struct jme_txdesc *txd; 1031 struct jme_rxdesc *rxd; 1032 bus_addr_t lowaddr, rx_ring_end, tx_ring_end; 1033 int error, i; 1034 1035 lowaddr = BUS_SPACE_MAXADDR; 1036 if ((sc->jme_flags & JME_FLAG_DMA32BIT) != 0) 1037 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1038 1039again: 1040 /* Create parent ring tag. */ 1041 error = bus_dma_tag_create(bus_get_dma_tag(sc->jme_dev),/* parent */ 1042 1, 0, /* algnmnt, boundary */ 1043 lowaddr, /* lowaddr */ 1044 BUS_SPACE_MAXADDR, /* highaddr */ 1045 NULL, NULL, /* filter, filterarg */ 1046 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1047 0, /* nsegments */ 1048 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1049 0, /* flags */ 1050 NULL, NULL, /* lockfunc, lockarg */ 1051 &sc->jme_cdata.jme_ring_tag); 1052 if (error != 0) { 1053 device_printf(sc->jme_dev, 1054 "could not create parent ring DMA tag.\n"); 1055 goto fail; 1056 } 1057 /* Create tag for Tx ring. */ 1058 error = bus_dma_tag_create(sc->jme_cdata.jme_ring_tag,/* parent */ 1059 JME_TX_RING_ALIGN, 0, /* algnmnt, boundary */ 1060 BUS_SPACE_MAXADDR, /* lowaddr */ 1061 BUS_SPACE_MAXADDR, /* highaddr */ 1062 NULL, NULL, /* filter, filterarg */ 1063 JME_TX_RING_SIZE, /* maxsize */ 1064 1, /* nsegments */ 1065 JME_TX_RING_SIZE, /* maxsegsize */ 1066 0, /* flags */ 1067 NULL, NULL, /* lockfunc, lockarg */ 1068 &sc->jme_cdata.jme_tx_ring_tag); 1069 if (error != 0) { 1070 device_printf(sc->jme_dev, 1071 "could not allocate Tx ring DMA tag.\n"); 1072 goto fail; 1073 } 1074 1075 /* Create tag for Rx ring. */ 1076 error = bus_dma_tag_create(sc->jme_cdata.jme_ring_tag,/* parent */ 1077 JME_RX_RING_ALIGN, 0, /* algnmnt, boundary */ 1078 lowaddr, /* lowaddr */ 1079 BUS_SPACE_MAXADDR, /* highaddr */ 1080 NULL, NULL, /* filter, filterarg */ 1081 JME_RX_RING_SIZE, /* maxsize */ 1082 1, /* nsegments */ 1083 JME_RX_RING_SIZE, /* maxsegsize */ 1084 0, /* flags */ 1085 NULL, NULL, /* lockfunc, lockarg */ 1086 &sc->jme_cdata.jme_rx_ring_tag); 1087 if (error != 0) { 1088 device_printf(sc->jme_dev, 1089 "could not allocate Rx ring DMA tag.\n"); 1090 goto fail; 1091 } 1092 1093 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1094 error = bus_dmamem_alloc(sc->jme_cdata.jme_tx_ring_tag, 1095 (void **)&sc->jme_rdata.jme_tx_ring, 1096 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1097 &sc->jme_cdata.jme_tx_ring_map); 1098 if (error != 0) { 1099 device_printf(sc->jme_dev, 1100 "could not allocate DMA'able memory for Tx ring.\n"); 1101 goto fail; 1102 } 1103 1104 ctx.jme_busaddr = 0; 1105 error = bus_dmamap_load(sc->jme_cdata.jme_tx_ring_tag, 1106 sc->jme_cdata.jme_tx_ring_map, sc->jme_rdata.jme_tx_ring, 1107 JME_TX_RING_SIZE, jme_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 1108 if (error != 0 || ctx.jme_busaddr == 0) { 1109 device_printf(sc->jme_dev, 1110 "could not load DMA'able memory for Tx ring.\n"); 1111 goto fail; 1112 } 1113 sc->jme_rdata.jme_tx_ring_paddr = ctx.jme_busaddr; 1114 1115 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 1116 error = bus_dmamem_alloc(sc->jme_cdata.jme_rx_ring_tag, 1117 (void **)&sc->jme_rdata.jme_rx_ring, 1118 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1119 &sc->jme_cdata.jme_rx_ring_map); 1120 if (error != 0) { 1121 device_printf(sc->jme_dev, 1122 "could not allocate DMA'able memory for Rx ring.\n"); 1123 goto fail; 1124 } 1125 1126 ctx.jme_busaddr = 0; 1127 error = bus_dmamap_load(sc->jme_cdata.jme_rx_ring_tag, 1128 sc->jme_cdata.jme_rx_ring_map, sc->jme_rdata.jme_rx_ring, 1129 JME_RX_RING_SIZE, jme_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 1130 if (error != 0 || ctx.jme_busaddr == 0) { 1131 device_printf(sc->jme_dev, 1132 "could not load DMA'able memory for Rx ring.\n"); 1133 goto fail; 1134 } 1135 sc->jme_rdata.jme_rx_ring_paddr = ctx.jme_busaddr; 1136 1137 if (lowaddr != BUS_SPACE_MAXADDR_32BIT) { 1138 /* Tx/Rx descriptor queue should reside within 4GB boundary. */ 1139 tx_ring_end = sc->jme_rdata.jme_tx_ring_paddr + 1140 JME_TX_RING_SIZE; 1141 rx_ring_end = sc->jme_rdata.jme_rx_ring_paddr + 1142 JME_RX_RING_SIZE; 1143 if ((JME_ADDR_HI(tx_ring_end) != 1144 JME_ADDR_HI(sc->jme_rdata.jme_tx_ring_paddr)) || 1145 (JME_ADDR_HI(rx_ring_end) != 1146 JME_ADDR_HI(sc->jme_rdata.jme_rx_ring_paddr))) { 1147 device_printf(sc->jme_dev, "4GB boundary crossed, " 1148 "switching to 32bit DMA address mode.\n"); 1149 jme_dma_free(sc); 1150 /* Limit DMA address space to 32bit and try again. */ 1151 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1152 goto again; 1153 } 1154 } 1155 1156 lowaddr = BUS_SPACE_MAXADDR; 1157 if ((sc->jme_flags & JME_FLAG_DMA32BIT) != 0) 1158 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1159 /* Create parent buffer tag. */ 1160 error = bus_dma_tag_create(bus_get_dma_tag(sc->jme_dev),/* parent */ 1161 1, 0, /* algnmnt, boundary */ 1162 lowaddr, /* lowaddr */ 1163 BUS_SPACE_MAXADDR, /* highaddr */ 1164 NULL, NULL, /* filter, filterarg */ 1165 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1166 0, /* nsegments */ 1167 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1168 0, /* flags */ 1169 NULL, NULL, /* lockfunc, lockarg */ 1170 &sc->jme_cdata.jme_buffer_tag); 1171 if (error != 0) { 1172 device_printf(sc->jme_dev, 1173 "could not create parent buffer DMA tag.\n"); 1174 goto fail; 1175 } 1176 1177 /* Create shadow status block tag. */ 1178 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */ 1179 JME_SSB_ALIGN, 0, /* algnmnt, boundary */ 1180 BUS_SPACE_MAXADDR, /* lowaddr */ 1181 BUS_SPACE_MAXADDR, /* highaddr */ 1182 NULL, NULL, /* filter, filterarg */ 1183 JME_SSB_SIZE, /* maxsize */ 1184 1, /* nsegments */ 1185 JME_SSB_SIZE, /* maxsegsize */ 1186 0, /* flags */ 1187 NULL, NULL, /* lockfunc, lockarg */ 1188 &sc->jme_cdata.jme_ssb_tag); 1189 if (error != 0) { 1190 device_printf(sc->jme_dev, 1191 "could not create shared status block DMA tag.\n"); 1192 goto fail; 1193 } 1194 1195 /* Create tag for Tx buffers. */ 1196 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */ 1197 1, 0, /* algnmnt, boundary */ 1198 BUS_SPACE_MAXADDR, /* lowaddr */ 1199 BUS_SPACE_MAXADDR, /* highaddr */ 1200 NULL, NULL, /* filter, filterarg */ 1201 JME_TSO_MAXSIZE, /* maxsize */ 1202 JME_MAXTXSEGS, /* nsegments */ 1203 JME_TSO_MAXSEGSIZE, /* maxsegsize */ 1204 0, /* flags */ 1205 NULL, NULL, /* lockfunc, lockarg */ 1206 &sc->jme_cdata.jme_tx_tag); 1207 if (error != 0) { 1208 device_printf(sc->jme_dev, "could not create Tx DMA tag.\n"); 1209 goto fail; 1210 } 1211 1212 /* Create tag for Rx buffers. */ 1213 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */ 1214 JME_RX_BUF_ALIGN, 0, /* algnmnt, boundary */ 1215 BUS_SPACE_MAXADDR, /* lowaddr */ 1216 BUS_SPACE_MAXADDR, /* highaddr */ 1217 NULL, NULL, /* filter, filterarg */ 1218 MCLBYTES, /* maxsize */ 1219 1, /* nsegments */ 1220 MCLBYTES, /* maxsegsize */ 1221 0, /* flags */ 1222 NULL, NULL, /* lockfunc, lockarg */ 1223 &sc->jme_cdata.jme_rx_tag); 1224 if (error != 0) { 1225 device_printf(sc->jme_dev, "could not create Rx DMA tag.\n"); 1226 goto fail; 1227 } 1228 1229 /* 1230 * Allocate DMA'able memory and load the DMA map for shared 1231 * status block. 1232 */ 1233 error = bus_dmamem_alloc(sc->jme_cdata.jme_ssb_tag, 1234 (void **)&sc->jme_rdata.jme_ssb_block, 1235 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1236 &sc->jme_cdata.jme_ssb_map); 1237 if (error != 0) { 1238 device_printf(sc->jme_dev, "could not allocate DMA'able " 1239 "memory for shared status block.\n"); 1240 goto fail; 1241 } 1242 1243 ctx.jme_busaddr = 0; 1244 error = bus_dmamap_load(sc->jme_cdata.jme_ssb_tag, 1245 sc->jme_cdata.jme_ssb_map, sc->jme_rdata.jme_ssb_block, 1246 JME_SSB_SIZE, jme_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 1247 if (error != 0 || ctx.jme_busaddr == 0) { 1248 device_printf(sc->jme_dev, "could not load DMA'able memory " 1249 "for shared status block.\n"); 1250 goto fail; 1251 } 1252 sc->jme_rdata.jme_ssb_block_paddr = ctx.jme_busaddr; 1253 1254 /* Create DMA maps for Tx buffers. */ 1255 for (i = 0; i < JME_TX_RING_CNT; i++) { 1256 txd = &sc->jme_cdata.jme_txdesc[i]; 1257 txd->tx_m = NULL; 1258 txd->tx_dmamap = NULL; 1259 error = bus_dmamap_create(sc->jme_cdata.jme_tx_tag, 0, 1260 &txd->tx_dmamap); 1261 if (error != 0) { 1262 device_printf(sc->jme_dev, 1263 "could not create Tx dmamap.\n"); 1264 goto fail; 1265 } 1266 } 1267 /* Create DMA maps for Rx buffers. */ 1268 if ((error = bus_dmamap_create(sc->jme_cdata.jme_rx_tag, 0, 1269 &sc->jme_cdata.jme_rx_sparemap)) != 0) { 1270 device_printf(sc->jme_dev, 1271 "could not create spare Rx dmamap.\n"); 1272 goto fail; 1273 } 1274 for (i = 0; i < JME_RX_RING_CNT; i++) { 1275 rxd = &sc->jme_cdata.jme_rxdesc[i]; 1276 rxd->rx_m = NULL; 1277 rxd->rx_dmamap = NULL; 1278 error = bus_dmamap_create(sc->jme_cdata.jme_rx_tag, 0, 1279 &rxd->rx_dmamap); 1280 if (error != 0) { 1281 device_printf(sc->jme_dev, 1282 "could not create Rx dmamap.\n"); 1283 goto fail; 1284 } 1285 } 1286 1287fail: 1288 return (error); 1289} 1290 1291static void 1292jme_dma_free(struct jme_softc *sc) 1293{ 1294 struct jme_txdesc *txd; 1295 struct jme_rxdesc *rxd; 1296 int i; 1297 1298 /* Tx ring */ 1299 if (sc->jme_cdata.jme_tx_ring_tag != NULL) { 1300 if (sc->jme_cdata.jme_tx_ring_map) 1301 bus_dmamap_unload(sc->jme_cdata.jme_tx_ring_tag, 1302 sc->jme_cdata.jme_tx_ring_map); 1303 if (sc->jme_cdata.jme_tx_ring_map && 1304 sc->jme_rdata.jme_tx_ring) 1305 bus_dmamem_free(sc->jme_cdata.jme_tx_ring_tag, 1306 sc->jme_rdata.jme_tx_ring, 1307 sc->jme_cdata.jme_tx_ring_map); 1308 sc->jme_rdata.jme_tx_ring = NULL; 1309 sc->jme_cdata.jme_tx_ring_map = NULL; 1310 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_ring_tag); 1311 sc->jme_cdata.jme_tx_ring_tag = NULL; 1312 } 1313 /* Rx ring */ 1314 if (sc->jme_cdata.jme_rx_ring_tag != NULL) { 1315 if (sc->jme_cdata.jme_rx_ring_map) 1316 bus_dmamap_unload(sc->jme_cdata.jme_rx_ring_tag, 1317 sc->jme_cdata.jme_rx_ring_map); 1318 if (sc->jme_cdata.jme_rx_ring_map && 1319 sc->jme_rdata.jme_rx_ring) 1320 bus_dmamem_free(sc->jme_cdata.jme_rx_ring_tag, 1321 sc->jme_rdata.jme_rx_ring, 1322 sc->jme_cdata.jme_rx_ring_map); 1323 sc->jme_rdata.jme_rx_ring = NULL; 1324 sc->jme_cdata.jme_rx_ring_map = NULL; 1325 bus_dma_tag_destroy(sc->jme_cdata.jme_rx_ring_tag); 1326 sc->jme_cdata.jme_rx_ring_tag = NULL; 1327 } 1328 /* Tx buffers */ 1329 if (sc->jme_cdata.jme_tx_tag != NULL) { 1330 for (i = 0; i < JME_TX_RING_CNT; i++) { 1331 txd = &sc->jme_cdata.jme_txdesc[i]; 1332 if (txd->tx_dmamap != NULL) { 1333 bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag, 1334 txd->tx_dmamap); 1335 txd->tx_dmamap = NULL; 1336 } 1337 } 1338 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag); 1339 sc->jme_cdata.jme_tx_tag = NULL; 1340 } 1341 /* Rx buffers */ 1342 if (sc->jme_cdata.jme_rx_tag != NULL) { 1343 for (i = 0; i < JME_RX_RING_CNT; i++) { 1344 rxd = &sc->jme_cdata.jme_rxdesc[i]; 1345 if (rxd->rx_dmamap != NULL) { 1346 bus_dmamap_destroy(sc->jme_cdata.jme_rx_tag, 1347 rxd->rx_dmamap); 1348 rxd->rx_dmamap = NULL; 1349 } 1350 } 1351 if (sc->jme_cdata.jme_rx_sparemap != NULL) { 1352 bus_dmamap_destroy(sc->jme_cdata.jme_rx_tag, 1353 sc->jme_cdata.jme_rx_sparemap); 1354 sc->jme_cdata.jme_rx_sparemap = NULL; 1355 } 1356 bus_dma_tag_destroy(sc->jme_cdata.jme_rx_tag); 1357 sc->jme_cdata.jme_rx_tag = NULL; 1358 } 1359 1360 /* Shared status block. */ 1361 if (sc->jme_cdata.jme_ssb_tag != NULL) { 1362 if (sc->jme_cdata.jme_ssb_map) 1363 bus_dmamap_unload(sc->jme_cdata.jme_ssb_tag, 1364 sc->jme_cdata.jme_ssb_map); 1365 if (sc->jme_cdata.jme_ssb_map && sc->jme_rdata.jme_ssb_block) 1366 bus_dmamem_free(sc->jme_cdata.jme_ssb_tag, 1367 sc->jme_rdata.jme_ssb_block, 1368 sc->jme_cdata.jme_ssb_map); 1369 sc->jme_rdata.jme_ssb_block = NULL; 1370 sc->jme_cdata.jme_ssb_map = NULL; 1371 bus_dma_tag_destroy(sc->jme_cdata.jme_ssb_tag); 1372 sc->jme_cdata.jme_ssb_tag = NULL; 1373 } 1374 1375 if (sc->jme_cdata.jme_buffer_tag != NULL) { 1376 bus_dma_tag_destroy(sc->jme_cdata.jme_buffer_tag); 1377 sc->jme_cdata.jme_buffer_tag = NULL; 1378 } 1379 if (sc->jme_cdata.jme_ring_tag != NULL) { 1380 bus_dma_tag_destroy(sc->jme_cdata.jme_ring_tag); 1381 sc->jme_cdata.jme_ring_tag = NULL; 1382 } 1383} 1384 1385/* 1386 * Make sure the interface is stopped at reboot time. 1387 */ 1388static int 1389jme_shutdown(device_t dev) 1390{ 1391 1392 return (jme_suspend(dev)); 1393} 1394 1395/* 1396 * Unlike other ethernet controllers, JMC250 requires 1397 * explicit resetting link speed to 10/100Mbps as gigabit 1398 * link will cunsume more power than 375mA. 1399 * Note, we reset the link speed to 10/100Mbps with 1400 * auto-negotiation but we don't know whether that operation 1401 * would succeed or not as we have no control after powering 1402 * off. If the renegotiation fail WOL may not work. Running 1403 * at 1Gbps draws more power than 375mA at 3.3V which is 1404 * specified in PCI specification and that would result in 1405 * complete shutdowning power to ethernet controller. 1406 * 1407 * TODO 1408 * Save current negotiated media speed/duplex/flow-control 1409 * to softc and restore the same link again after resuming. 1410 * PHY handling such as power down/resetting to 100Mbps 1411 * may be better handled in suspend method in phy driver. 1412 */ 1413static void 1414jme_setlinkspeed(struct jme_softc *sc) 1415{ 1416 struct mii_data *mii; 1417 int aneg, i; 1418 1419 JME_LOCK_ASSERT(sc); 1420 1421 mii = device_get_softc(sc->jme_miibus); 1422 mii_pollstat(mii); 1423 aneg = 0; 1424 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1425 switch IFM_SUBTYPE(mii->mii_media_active) { 1426 case IFM_10_T: 1427 case IFM_100_TX: 1428 return; 1429 case IFM_1000_T: 1430 aneg++; 1431 default: 1432 break; 1433 } 1434 } 1435 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_100T2CR, 0); 1436 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_ANAR, 1437 ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 1438 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR, 1439 BMCR_AUTOEN | BMCR_STARTNEG); 1440 DELAY(1000); 1441 if (aneg != 0) { 1442 /* Poll link state until jme(4) get a 10/100 link. */ 1443 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1444 mii_pollstat(mii); 1445 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1446 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1447 case IFM_10_T: 1448 case IFM_100_TX: 1449 jme_mac_config(sc); 1450 return; 1451 default: 1452 break; 1453 } 1454 } 1455 JME_UNLOCK(sc); 1456 pause("jmelnk", hz); 1457 JME_LOCK(sc); 1458 } 1459 if (i == MII_ANEGTICKS_GIGE) 1460 device_printf(sc->jme_dev, "establishing link failed, " 1461 "WOL may not work!"); 1462 } 1463 /* 1464 * No link, force MAC to have 100Mbps, full-duplex link. 1465 * This is the last resort and may/may not work. 1466 */ 1467 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1468 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1469 jme_mac_config(sc); 1470} 1471 1472static void 1473jme_setwol(struct jme_softc *sc) 1474{ 1475 struct ifnet *ifp; 1476 uint32_t gpr, pmcs; 1477 uint16_t pmstat; 1478 int pmc; 1479 1480 JME_LOCK_ASSERT(sc); 1481 1482 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) { 1483 /* Remove Tx MAC/offload clock to save more power. */ 1484 if ((sc->jme_flags & JME_FLAG_TXCLK) != 0) 1485 CSR_WRITE_4(sc, JME_GHC, CSR_READ_4(sc, JME_GHC) & 1486 ~(GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100 | 1487 GHC_TX_OFFLD_CLK_1000 | GHC_TX_MAC_CLK_1000)); 1488 /* No PME capability, PHY power down. */ 1489 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, 1490 MII_BMCR, BMCR_PDOWN); 1491 return; 1492 } 1493 1494 ifp = sc->jme_ifp; 1495 gpr = CSR_READ_4(sc, JME_GPREG0) & ~GPREG0_PME_ENB; 1496 pmcs = CSR_READ_4(sc, JME_PMCS); 1497 pmcs &= ~PMCS_WOL_ENB_MASK; 1498 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) { 1499 pmcs |= PMCS_MAGIC_FRAME | PMCS_MAGIC_FRAME_ENB; 1500 /* Enable PME message. */ 1501 gpr |= GPREG0_PME_ENB; 1502 /* For gigabit controllers, reset link speed to 10/100. */ 1503 if ((sc->jme_flags & JME_FLAG_FASTETH) == 0) 1504 jme_setlinkspeed(sc); 1505 } 1506 1507 CSR_WRITE_4(sc, JME_PMCS, pmcs); 1508 CSR_WRITE_4(sc, JME_GPREG0, gpr); 1509 /* Remove Tx MAC/offload clock to save more power. */ 1510 if ((sc->jme_flags & JME_FLAG_TXCLK) != 0) 1511 CSR_WRITE_4(sc, JME_GHC, CSR_READ_4(sc, JME_GHC) & 1512 ~(GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100 | 1513 GHC_TX_OFFLD_CLK_1000 | GHC_TX_MAC_CLK_1000)); 1514 /* Request PME. */ 1515 pmstat = pci_read_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, 2); 1516 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1517 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1518 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1519 pci_write_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1520 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 1521 /* No WOL, PHY power down. */ 1522 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, 1523 MII_BMCR, BMCR_PDOWN); 1524 } 1525} 1526 1527static int 1528jme_suspend(device_t dev) 1529{ 1530 struct jme_softc *sc; 1531 1532 sc = device_get_softc(dev); 1533 1534 JME_LOCK(sc); 1535 jme_stop(sc); 1536 jme_setwol(sc); 1537 JME_UNLOCK(sc); 1538 1539 return (0); 1540} 1541 1542static int 1543jme_resume(device_t dev) 1544{ 1545 struct jme_softc *sc; 1546 struct ifnet *ifp; 1547 uint16_t pmstat; 1548 int pmc; 1549 1550 sc = device_get_softc(dev); 1551 1552 JME_LOCK(sc); 1553 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) { 1554 pmstat = pci_read_config(sc->jme_dev, 1555 pmc + PCIR_POWER_STATUS, 2); 1556 /* Disable PME clear PME status. */ 1557 pmstat &= ~PCIM_PSTAT_PMEENABLE; 1558 pci_write_config(sc->jme_dev, 1559 pmc + PCIR_POWER_STATUS, pmstat, 2); 1560 } 1561 ifp = sc->jme_ifp; 1562 if ((ifp->if_flags & IFF_UP) != 0) { 1563 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1564 jme_init_locked(sc); 1565 } 1566 1567 JME_UNLOCK(sc); 1568 1569 return (0); 1570} 1571 1572static int 1573jme_encap(struct jme_softc *sc, struct mbuf **m_head) 1574{ 1575 struct jme_txdesc *txd; 1576 struct jme_desc *desc; 1577 struct mbuf *m; 1578 bus_dma_segment_t txsegs[JME_MAXTXSEGS]; 1579 int error, i, nsegs, prod; 1580 uint32_t cflags, tso_segsz; 1581 1582 JME_LOCK_ASSERT(sc); 1583 1584 M_ASSERTPKTHDR((*m_head)); 1585 1586 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1587 /* 1588 * Due to the adherence to NDIS specification JMC250 1589 * assumes upper stack computed TCP pseudo checksum 1590 * without including payload length. This breaks 1591 * checksum offload for TSO case so recompute TCP 1592 * pseudo checksum for JMC250. Hopefully this wouldn't 1593 * be much burden on modern CPUs. 1594 */ 1595 struct ether_header *eh; 1596 struct ip *ip; 1597 struct tcphdr *tcp; 1598 uint32_t ip_off, poff; 1599 1600 if (M_WRITABLE(*m_head) == 0) { 1601 /* Get a writable copy. */ 1602 m = m_dup(*m_head, M_DONTWAIT); 1603 m_freem(*m_head); 1604 if (m == NULL) { 1605 *m_head = NULL; 1606 return (ENOBUFS); 1607 } 1608 *m_head = m; 1609 } 1610 ip_off = sizeof(struct ether_header); 1611 m = m_pullup(*m_head, ip_off); 1612 if (m == NULL) { 1613 *m_head = NULL; 1614 return (ENOBUFS); 1615 } 1616 eh = mtod(m, struct ether_header *); 1617 /* Check the existence of VLAN tag. */ 1618 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1619 ip_off = sizeof(struct ether_vlan_header); 1620 m = m_pullup(m, ip_off); 1621 if (m == NULL) { 1622 *m_head = NULL; 1623 return (ENOBUFS); 1624 } 1625 } 1626 m = m_pullup(m, ip_off + sizeof(struct ip)); 1627 if (m == NULL) { 1628 *m_head = NULL; 1629 return (ENOBUFS); 1630 } 1631 ip = (struct ip *)(mtod(m, char *) + ip_off); 1632 poff = ip_off + (ip->ip_hl << 2); 1633 m = m_pullup(m, poff + sizeof(struct tcphdr)); 1634 if (m == NULL) { 1635 *m_head = NULL; 1636 return (ENOBUFS); 1637 } 1638 /* 1639 * Reset IP checksum and recompute TCP pseudo 1640 * checksum that NDIS specification requires. 1641 */ 1642 ip = (struct ip *)(mtod(m, char *) + ip_off); 1643 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1644 ip->ip_sum = 0; 1645 if (poff + (tcp->th_off << 2) == m->m_pkthdr.len) { 1646 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1647 ip->ip_dst.s_addr, 1648 htons((tcp->th_off << 2) + IPPROTO_TCP)); 1649 /* No need to TSO, force IP checksum offload. */ 1650 (*m_head)->m_pkthdr.csum_flags &= ~CSUM_TSO; 1651 (*m_head)->m_pkthdr.csum_flags |= CSUM_IP; 1652 } else 1653 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1654 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1655 *m_head = m; 1656 } 1657 1658 prod = sc->jme_cdata.jme_tx_prod; 1659 txd = &sc->jme_cdata.jme_txdesc[prod]; 1660 1661 error = bus_dmamap_load_mbuf_sg(sc->jme_cdata.jme_tx_tag, 1662 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); 1663 if (error == EFBIG) { 1664 m = m_collapse(*m_head, M_DONTWAIT, JME_MAXTXSEGS); 1665 if (m == NULL) { 1666 m_freem(*m_head); 1667 *m_head = NULL; 1668 return (ENOMEM); 1669 } 1670 *m_head = m; 1671 error = bus_dmamap_load_mbuf_sg(sc->jme_cdata.jme_tx_tag, 1672 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); 1673 if (error != 0) { 1674 m_freem(*m_head); 1675 *m_head = NULL; 1676 return (error); 1677 } 1678 } else if (error != 0) 1679 return (error); 1680 if (nsegs == 0) { 1681 m_freem(*m_head); 1682 *m_head = NULL; 1683 return (EIO); 1684 } 1685 1686 /* 1687 * Check descriptor overrun. Leave one free descriptor. 1688 * Since we always use 64bit address mode for transmitting, 1689 * each Tx request requires one more dummy descriptor. 1690 */ 1691 if (sc->jme_cdata.jme_tx_cnt + nsegs + 1 > JME_TX_RING_CNT - 1) { 1692 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap); 1693 return (ENOBUFS); 1694 } 1695 1696 m = *m_head; 1697 cflags = 0; 1698 tso_segsz = 0; 1699 /* Configure checksum offload and TSO. */ 1700 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1701 tso_segsz = (uint32_t)m->m_pkthdr.tso_segsz << 1702 JME_TD_MSS_SHIFT; 1703 cflags |= JME_TD_TSO; 1704 } else { 1705 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 1706 cflags |= JME_TD_IPCSUM; 1707 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 1708 cflags |= JME_TD_TCPCSUM; 1709 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 1710 cflags |= JME_TD_UDPCSUM; 1711 } 1712 /* Configure VLAN. */ 1713 if ((m->m_flags & M_VLANTAG) != 0) { 1714 cflags |= (m->m_pkthdr.ether_vtag & JME_TD_VLAN_MASK); 1715 cflags |= JME_TD_VLAN_TAG; 1716 } 1717 1718 desc = &sc->jme_rdata.jme_tx_ring[prod]; 1719 desc->flags = htole32(cflags); 1720 desc->buflen = htole32(tso_segsz); 1721 desc->addr_hi = htole32(m->m_pkthdr.len); 1722 desc->addr_lo = 0; 1723 sc->jme_cdata.jme_tx_cnt++; 1724 JME_DESC_INC(prod, JME_TX_RING_CNT); 1725 for (i = 0; i < nsegs; i++) { 1726 desc = &sc->jme_rdata.jme_tx_ring[prod]; 1727 desc->flags = htole32(JME_TD_OWN | JME_TD_64BIT); 1728 desc->buflen = htole32(txsegs[i].ds_len); 1729 desc->addr_hi = htole32(JME_ADDR_HI(txsegs[i].ds_addr)); 1730 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[i].ds_addr)); 1731 sc->jme_cdata.jme_tx_cnt++; 1732 JME_DESC_INC(prod, JME_TX_RING_CNT); 1733 } 1734 1735 /* Update producer index. */ 1736 sc->jme_cdata.jme_tx_prod = prod; 1737 /* 1738 * Finally request interrupt and give the first descriptor 1739 * owenership to hardware. 1740 */ 1741 desc = txd->tx_desc; 1742 desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR); 1743 1744 txd->tx_m = m; 1745 txd->tx_ndesc = nsegs + 1; 1746 1747 /* Sync descriptors. */ 1748 bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap, 1749 BUS_DMASYNC_PREWRITE); 1750 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag, 1751 sc->jme_cdata.jme_tx_ring_map, 1752 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1753 1754 return (0); 1755} 1756 1757static void 1758jme_tx_task(void *arg, int pending) 1759{ 1760 struct ifnet *ifp; 1761 1762 ifp = (struct ifnet *)arg; 1763 jme_start(ifp); 1764} 1765 1766static void 1767jme_start(struct ifnet *ifp) 1768{ 1769 struct jme_softc *sc; 1770 struct mbuf *m_head; 1771 int enq; 1772 1773 sc = ifp->if_softc; 1774 1775 JME_LOCK(sc); 1776 1777 if (sc->jme_cdata.jme_tx_cnt >= JME_TX_DESC_HIWAT) 1778 jme_txeof(sc); 1779 1780 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1781 IFF_DRV_RUNNING || (sc->jme_flags & JME_FLAG_LINK) == 0) { 1782 JME_UNLOCK(sc); 1783 return; 1784 } 1785 1786 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 1787 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1788 if (m_head == NULL) 1789 break; 1790 /* 1791 * Pack the data into the transmit ring. If we 1792 * don't have room, set the OACTIVE flag and wait 1793 * for the NIC to drain the ring. 1794 */ 1795 if (jme_encap(sc, &m_head)) { 1796 if (m_head == NULL) 1797 break; 1798 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1799 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1800 break; 1801 } 1802 1803 enq++; 1804 /* 1805 * If there's a BPF listener, bounce a copy of this frame 1806 * to him. 1807 */ 1808 ETHER_BPF_MTAP(ifp, m_head); 1809 } 1810 1811 if (enq > 0) { 1812 /* 1813 * Reading TXCSR takes very long time under heavy load 1814 * so cache TXCSR value and writes the ORed value with 1815 * the kick command to the TXCSR. This saves one register 1816 * access cycle. 1817 */ 1818 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB | 1819 TXCSR_TXQ_N_START(TXCSR_TXQ0)); 1820 /* Set a timeout in case the chip goes out to lunch. */ 1821 sc->jme_watchdog_timer = JME_TX_TIMEOUT; 1822 } 1823 1824 JME_UNLOCK(sc); 1825} 1826 1827static void 1828jme_watchdog(struct jme_softc *sc) 1829{ 1830 struct ifnet *ifp; 1831 1832 JME_LOCK_ASSERT(sc); 1833 1834 if (sc->jme_watchdog_timer == 0 || --sc->jme_watchdog_timer) 1835 return; 1836 1837 ifp = sc->jme_ifp; 1838 if ((sc->jme_flags & JME_FLAG_LINK) == 0) { 1839 if_printf(sc->jme_ifp, "watchdog timeout (missed link)\n"); 1840 ifp->if_oerrors++; 1841 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1842 jme_init_locked(sc); 1843 return; 1844 } 1845 jme_txeof(sc); 1846 if (sc->jme_cdata.jme_tx_cnt == 0) { 1847 if_printf(sc->jme_ifp, 1848 "watchdog timeout (missed Tx interrupts) -- recovering\n"); 1849 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1850 taskqueue_enqueue(sc->jme_tq, &sc->jme_tx_task); 1851 return; 1852 } 1853 1854 if_printf(sc->jme_ifp, "watchdog timeout\n"); 1855 ifp->if_oerrors++; 1856 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1857 jme_init_locked(sc); 1858 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1859 taskqueue_enqueue(sc->jme_tq, &sc->jme_tx_task); 1860} 1861 1862static int 1863jme_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1864{ 1865 struct jme_softc *sc; 1866 struct ifreq *ifr; 1867 struct mii_data *mii; 1868 uint32_t reg; 1869 int error, mask; 1870 1871 sc = ifp->if_softc; 1872 ifr = (struct ifreq *)data; 1873 error = 0; 1874 switch (cmd) { 1875 case SIOCSIFMTU: 1876 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > JME_JUMBO_MTU || 1877 ((sc->jme_flags & JME_FLAG_NOJUMBO) != 0 && 1878 ifr->ifr_mtu > JME_MAX_MTU)) { 1879 error = EINVAL; 1880 break; 1881 } 1882 1883 if (ifp->if_mtu != ifr->ifr_mtu) { 1884 /* 1885 * No special configuration is required when interface 1886 * MTU is changed but availability of TSO/Tx checksum 1887 * offload should be chcked against new MTU size as 1888 * FIFO size is just 2K. 1889 */ 1890 JME_LOCK(sc); 1891 if (ifr->ifr_mtu >= JME_TX_FIFO_SIZE) { 1892 ifp->if_capenable &= 1893 ~(IFCAP_TXCSUM | IFCAP_TSO4); 1894 ifp->if_hwassist &= 1895 ~(JME_CSUM_FEATURES | CSUM_TSO); 1896 VLAN_CAPABILITIES(ifp); 1897 } 1898 ifp->if_mtu = ifr->ifr_mtu; 1899 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1900 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1901 jme_init_locked(sc); 1902 } 1903 JME_UNLOCK(sc); 1904 } 1905 break; 1906 case SIOCSIFFLAGS: 1907 JME_LOCK(sc); 1908 if ((ifp->if_flags & IFF_UP) != 0) { 1909 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1910 if (((ifp->if_flags ^ sc->jme_if_flags) 1911 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1912 jme_set_filter(sc); 1913 } else { 1914 if ((sc->jme_flags & JME_FLAG_DETACH) == 0) 1915 jme_init_locked(sc); 1916 } 1917 } else { 1918 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1919 jme_stop(sc); 1920 } 1921 sc->jme_if_flags = ifp->if_flags; 1922 JME_UNLOCK(sc); 1923 break; 1924 case SIOCADDMULTI: 1925 case SIOCDELMULTI: 1926 JME_LOCK(sc); 1927 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1928 jme_set_filter(sc); 1929 JME_UNLOCK(sc); 1930 break; 1931 case SIOCSIFMEDIA: 1932 case SIOCGIFMEDIA: 1933 mii = device_get_softc(sc->jme_miibus); 1934 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1935 break; 1936 case SIOCSIFCAP: 1937 JME_LOCK(sc); 1938 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1939 if ((mask & IFCAP_TXCSUM) != 0 && 1940 ifp->if_mtu < JME_TX_FIFO_SIZE) { 1941 if ((IFCAP_TXCSUM & ifp->if_capabilities) != 0) { 1942 ifp->if_capenable ^= IFCAP_TXCSUM; 1943 if ((IFCAP_TXCSUM & ifp->if_capenable) != 0) 1944 ifp->if_hwassist |= JME_CSUM_FEATURES; 1945 else 1946 ifp->if_hwassist &= ~JME_CSUM_FEATURES; 1947 } 1948 } 1949 if ((mask & IFCAP_RXCSUM) != 0 && 1950 (IFCAP_RXCSUM & ifp->if_capabilities) != 0) { 1951 ifp->if_capenable ^= IFCAP_RXCSUM; 1952 reg = CSR_READ_4(sc, JME_RXMAC); 1953 reg &= ~RXMAC_CSUM_ENB; 1954 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1955 reg |= RXMAC_CSUM_ENB; 1956 CSR_WRITE_4(sc, JME_RXMAC, reg); 1957 } 1958 if ((mask & IFCAP_TSO4) != 0 && 1959 ifp->if_mtu < JME_TX_FIFO_SIZE) { 1960 if ((IFCAP_TSO4 & ifp->if_capabilities) != 0) { 1961 ifp->if_capenable ^= IFCAP_TSO4; 1962 if ((IFCAP_TSO4 & ifp->if_capenable) != 0) 1963 ifp->if_hwassist |= CSUM_TSO; 1964 else 1965 ifp->if_hwassist &= ~CSUM_TSO; 1966 } 1967 } 1968 if ((mask & IFCAP_WOL_MAGIC) != 0 && 1969 (IFCAP_WOL_MAGIC & ifp->if_capabilities) != 0) 1970 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 1971 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 1972 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 1973 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 1974 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 1975 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 1976 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 1977 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 1978 (IFCAP_VLAN_HWTAGGING & ifp->if_capabilities) != 0) { 1979 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1980 jme_set_vlan(sc); 1981 } 1982 JME_UNLOCK(sc); 1983 VLAN_CAPABILITIES(ifp); 1984 break; 1985 default: 1986 error = ether_ioctl(ifp, cmd, data); 1987 break; 1988 } 1989 1990 return (error); 1991} 1992 1993static void 1994jme_mac_config(struct jme_softc *sc) 1995{ 1996 struct mii_data *mii; 1997 uint32_t ghc, gpreg, rxmac, txmac, txpause; 1998 uint32_t txclk; 1999 2000 JME_LOCK_ASSERT(sc); 2001 2002 mii = device_get_softc(sc->jme_miibus); 2003 2004 CSR_WRITE_4(sc, JME_GHC, GHC_RESET); 2005 DELAY(10); 2006 CSR_WRITE_4(sc, JME_GHC, 0); 2007 ghc = 0; 2008 txclk = 0; 2009 rxmac = CSR_READ_4(sc, JME_RXMAC); 2010 rxmac &= ~RXMAC_FC_ENB; 2011 txmac = CSR_READ_4(sc, JME_TXMAC); 2012 txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST); 2013 txpause = CSR_READ_4(sc, JME_TXPFC); 2014 txpause &= ~TXPFC_PAUSE_ENB; 2015 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2016 ghc |= GHC_FULL_DUPLEX; 2017 rxmac &= ~RXMAC_COLL_DET_ENB; 2018 txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | 2019 TXMAC_BACKOFF | TXMAC_CARRIER_EXT | 2020 TXMAC_FRAME_BURST); 2021 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2022 txpause |= TXPFC_PAUSE_ENB; 2023 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2024 rxmac |= RXMAC_FC_ENB; 2025 /* Disable retry transmit timer/retry limit. */ 2026 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) & 2027 ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB)); 2028 } else { 2029 rxmac |= RXMAC_COLL_DET_ENB; 2030 txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF; 2031 /* Enable retry transmit timer/retry limit. */ 2032 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) | 2033 TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB); 2034 } 2035 /* Reprogram Tx/Rx MACs with resolved speed/duplex. */ 2036 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2037 case IFM_10_T: 2038 ghc |= GHC_SPEED_10; 2039 txclk |= GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100; 2040 break; 2041 case IFM_100_TX: 2042 ghc |= GHC_SPEED_100; 2043 txclk |= GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100; 2044 break; 2045 case IFM_1000_T: 2046 if ((sc->jme_flags & JME_FLAG_FASTETH) != 0) 2047 break; 2048 ghc |= GHC_SPEED_1000; 2049 txclk |= GHC_TX_OFFLD_CLK_1000 | GHC_TX_MAC_CLK_1000; 2050 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0) 2051 txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST; 2052 break; 2053 default: 2054 break; 2055 } 2056 if (sc->jme_rev == DEVICEID_JMC250 && 2057 sc->jme_chip_rev == DEVICEREVID_JMC250_A2) { 2058 /* 2059 * Workaround occasional packet loss issue of JMC250 A2 2060 * when it runs on half-duplex media. 2061 */ 2062 gpreg = CSR_READ_4(sc, JME_GPREG1); 2063 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 2064 gpreg &= ~GPREG1_HDPX_FIX; 2065 else 2066 gpreg |= GPREG1_HDPX_FIX; 2067 CSR_WRITE_4(sc, JME_GPREG1, gpreg); 2068 /* Workaround CRC errors at 100Mbps on JMC250 A2. */ 2069 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 2070 /* Extend interface FIFO depth. */ 2071 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, 2072 0x1B, 0x0000); 2073 } else { 2074 /* Select default interface FIFO depth. */ 2075 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, 2076 0x1B, 0x0004); 2077 } 2078 } 2079 if ((sc->jme_flags & JME_FLAG_TXCLK) != 0) 2080 ghc |= txclk; 2081 CSR_WRITE_4(sc, JME_GHC, ghc); 2082 CSR_WRITE_4(sc, JME_RXMAC, rxmac); 2083 CSR_WRITE_4(sc, JME_TXMAC, txmac); 2084 CSR_WRITE_4(sc, JME_TXPFC, txpause); 2085} 2086 2087static void 2088jme_link_task(void *arg, int pending) 2089{ 2090 struct jme_softc *sc; 2091 struct mii_data *mii; 2092 struct ifnet *ifp; 2093 struct jme_txdesc *txd; 2094 bus_addr_t paddr; 2095 int i; 2096 2097 sc = (struct jme_softc *)arg; 2098 2099 JME_LOCK(sc); 2100 mii = device_get_softc(sc->jme_miibus); 2101 ifp = sc->jme_ifp; 2102 if (mii == NULL || ifp == NULL || 2103 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2104 JME_UNLOCK(sc); 2105 return; 2106 } 2107 2108 sc->jme_flags &= ~JME_FLAG_LINK; 2109 if ((mii->mii_media_status & IFM_AVALID) != 0) { 2110 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2111 case IFM_10_T: 2112 case IFM_100_TX: 2113 sc->jme_flags |= JME_FLAG_LINK; 2114 break; 2115 case IFM_1000_T: 2116 if ((sc->jme_flags & JME_FLAG_FASTETH) != 0) 2117 break; 2118 sc->jme_flags |= JME_FLAG_LINK; 2119 break; 2120 default: 2121 break; 2122 } 2123 } 2124 2125 /* 2126 * Disabling Rx/Tx MACs have a side-effect of resetting 2127 * JME_TXNDA/JME_RXNDA register to the first address of 2128 * Tx/Rx descriptor address. So driver should reset its 2129 * internal procucer/consumer pointer and reclaim any 2130 * allocated resources. Note, just saving the value of 2131 * JME_TXNDA and JME_RXNDA registers before stopping MAC 2132 * and restoring JME_TXNDA/JME_RXNDA register is not 2133 * sufficient to make sure correct MAC state because 2134 * stopping MAC operation can take a while and hardware 2135 * might have updated JME_TXNDA/JME_RXNDA registers 2136 * during the stop operation. 2137 */ 2138 /* Block execution of task. */ 2139 taskqueue_block(sc->jme_tq); 2140 /* Disable interrupts and stop driver. */ 2141 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS); 2142 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2143 callout_stop(&sc->jme_tick_ch); 2144 sc->jme_watchdog_timer = 0; 2145 2146 /* Stop receiver/transmitter. */ 2147 jme_stop_rx(sc); 2148 jme_stop_tx(sc); 2149 2150 /* XXX Drain all queued tasks. */ 2151 JME_UNLOCK(sc); 2152 taskqueue_drain(sc->jme_tq, &sc->jme_int_task); 2153 taskqueue_drain(sc->jme_tq, &sc->jme_tx_task); 2154 JME_LOCK(sc); 2155 2156 jme_rxintr(sc, JME_RX_RING_CNT); 2157 if (sc->jme_cdata.jme_rxhead != NULL) 2158 m_freem(sc->jme_cdata.jme_rxhead); 2159 JME_RXCHAIN_RESET(sc); 2160 jme_txeof(sc); 2161 if (sc->jme_cdata.jme_tx_cnt != 0) { 2162 /* Remove queued packets for transmit. */ 2163 for (i = 0; i < JME_TX_RING_CNT; i++) { 2164 txd = &sc->jme_cdata.jme_txdesc[i]; 2165 if (txd->tx_m != NULL) { 2166 bus_dmamap_sync( 2167 sc->jme_cdata.jme_tx_tag, 2168 txd->tx_dmamap, 2169 BUS_DMASYNC_POSTWRITE); 2170 bus_dmamap_unload( 2171 sc->jme_cdata.jme_tx_tag, 2172 txd->tx_dmamap); 2173 m_freem(txd->tx_m); 2174 txd->tx_m = NULL; 2175 txd->tx_ndesc = 0; 2176 ifp->if_oerrors++; 2177 } 2178 } 2179 } 2180 2181 /* 2182 * Reuse configured Rx descriptors and reset 2183 * procuder/consumer index. 2184 */ 2185 sc->jme_cdata.jme_rx_cons = 0; 2186 sc->jme_morework = 0; 2187 jme_init_tx_ring(sc); 2188 /* Initialize shadow status block. */ 2189 jme_init_ssb(sc); 2190 2191 /* Program MAC with resolved speed/duplex/flow-control. */ 2192 if ((sc->jme_flags & JME_FLAG_LINK) != 0) { 2193 jme_mac_config(sc); 2194 jme_stats_clear(sc); 2195 2196 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr); 2197 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr); 2198 2199 /* Set Tx ring address to the hardware. */ 2200 paddr = JME_TX_RING_ADDR(sc, 0); 2201 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr)); 2202 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr)); 2203 2204 /* Set Rx ring address to the hardware. */ 2205 paddr = JME_RX_RING_ADDR(sc, 0); 2206 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr)); 2207 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr)); 2208 2209 /* Restart receiver/transmitter. */ 2210 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RX_ENB | 2211 RXCSR_RXQ_START); 2212 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB); 2213 } 2214 2215 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2216 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2217 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc); 2218 /* Unblock execution of task. */ 2219 taskqueue_unblock(sc->jme_tq); 2220 /* Reenable interrupts. */ 2221 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS); 2222 2223 JME_UNLOCK(sc); 2224} 2225 2226static int 2227jme_intr(void *arg) 2228{ 2229 struct jme_softc *sc; 2230 uint32_t status; 2231 2232 sc = (struct jme_softc *)arg; 2233 2234 status = CSR_READ_4(sc, JME_INTR_REQ_STATUS); 2235 if (status == 0 || status == 0xFFFFFFFF) 2236 return (FILTER_STRAY); 2237 /* Disable interrupts. */ 2238 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS); 2239 taskqueue_enqueue(sc->jme_tq, &sc->jme_int_task); 2240 2241 return (FILTER_HANDLED); 2242} 2243 2244static void 2245jme_int_task(void *arg, int pending) 2246{ 2247 struct jme_softc *sc; 2248 struct ifnet *ifp; 2249 uint32_t status; 2250 int more; 2251 2252 sc = (struct jme_softc *)arg; 2253 ifp = sc->jme_ifp; 2254 2255 status = CSR_READ_4(sc, JME_INTR_STATUS); 2256 if (sc->jme_morework != 0) { 2257 sc->jme_morework = 0; 2258 status |= INTR_RXQ_COAL | INTR_RXQ_COAL_TO; 2259 } 2260 if ((status & JME_INTRS) == 0 || status == 0xFFFFFFFF) 2261 goto done; 2262 /* Reset PCC counter/timer and Ack interrupts. */ 2263 status &= ~(INTR_TXQ_COMP | INTR_RXQ_COMP); 2264 if ((status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) != 0) 2265 status |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP; 2266 if ((status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0) 2267 status |= INTR_RXQ_COAL | INTR_RXQ_COAL_TO | INTR_RXQ_COMP; 2268 CSR_WRITE_4(sc, JME_INTR_STATUS, status); 2269 more = 0; 2270 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2271 if ((status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0) { 2272 more = jme_rxintr(sc, sc->jme_process_limit); 2273 if (more != 0) 2274 sc->jme_morework = 1; 2275 } 2276 if ((status & INTR_RXQ_DESC_EMPTY) != 0) { 2277 /* 2278 * Notify hardware availability of new Rx 2279 * buffers. 2280 * Reading RXCSR takes very long time under 2281 * heavy load so cache RXCSR value and writes 2282 * the ORed value with the kick command to 2283 * the RXCSR. This saves one register access 2284 * cycle. 2285 */ 2286 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | 2287 RXCSR_RX_ENB | RXCSR_RXQ_START); 2288 } 2289 /* 2290 * Reclaiming Tx buffers are deferred to make jme(4) run 2291 * without locks held. 2292 */ 2293 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2294 taskqueue_enqueue(sc->jme_tq, &sc->jme_tx_task); 2295 } 2296 2297 if (more != 0 || (CSR_READ_4(sc, JME_INTR_STATUS) & JME_INTRS) != 0) { 2298 taskqueue_enqueue(sc->jme_tq, &sc->jme_int_task); 2299 return; 2300 } 2301done: 2302 /* Reenable interrupts. */ 2303 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS); 2304} 2305 2306static void 2307jme_txeof(struct jme_softc *sc) 2308{ 2309 struct ifnet *ifp; 2310 struct jme_txdesc *txd; 2311 uint32_t status; 2312 int cons, nsegs; 2313 2314 JME_LOCK_ASSERT(sc); 2315 2316 ifp = sc->jme_ifp; 2317 2318 cons = sc->jme_cdata.jme_tx_cons; 2319 if (cons == sc->jme_cdata.jme_tx_prod) 2320 return; 2321 2322 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag, 2323 sc->jme_cdata.jme_tx_ring_map, 2324 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2325 2326 /* 2327 * Go through our Tx list and free mbufs for those 2328 * frames which have been transmitted. 2329 */ 2330 for (; cons != sc->jme_cdata.jme_tx_prod;) { 2331 txd = &sc->jme_cdata.jme_txdesc[cons]; 2332 status = le32toh(txd->tx_desc->flags); 2333 if ((status & JME_TD_OWN) == JME_TD_OWN) 2334 break; 2335 2336 if ((status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) != 0) 2337 ifp->if_oerrors++; 2338 else { 2339 ifp->if_opackets++; 2340 if ((status & JME_TD_COLLISION) != 0) 2341 ifp->if_collisions += 2342 le32toh(txd->tx_desc->buflen) & 2343 JME_TD_BUF_LEN_MASK; 2344 } 2345 /* 2346 * Only the first descriptor of multi-descriptor 2347 * transmission is updated so driver have to skip entire 2348 * chained buffers for the transmiited frame. In other 2349 * words, JME_TD_OWN bit is valid only at the first 2350 * descriptor of a multi-descriptor transmission. 2351 */ 2352 for (nsegs = 0; nsegs < txd->tx_ndesc; nsegs++) { 2353 sc->jme_rdata.jme_tx_ring[cons].flags = 0; 2354 JME_DESC_INC(cons, JME_TX_RING_CNT); 2355 } 2356 2357 /* Reclaim transferred mbufs. */ 2358 bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap, 2359 BUS_DMASYNC_POSTWRITE); 2360 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap); 2361 2362 KASSERT(txd->tx_m != NULL, 2363 ("%s: freeing NULL mbuf!\n", __func__)); 2364 m_freem(txd->tx_m); 2365 txd->tx_m = NULL; 2366 sc->jme_cdata.jme_tx_cnt -= txd->tx_ndesc; 2367 KASSERT(sc->jme_cdata.jme_tx_cnt >= 0, 2368 ("%s: Active Tx desc counter was garbled\n", __func__)); 2369 txd->tx_ndesc = 0; 2370 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2371 } 2372 sc->jme_cdata.jme_tx_cons = cons; 2373 /* Unarm watchog timer when there is no pending descriptors in queue. */ 2374 if (sc->jme_cdata.jme_tx_cnt == 0) 2375 sc->jme_watchdog_timer = 0; 2376 2377 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag, 2378 sc->jme_cdata.jme_tx_ring_map, 2379 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2380} 2381 2382static __inline void 2383jme_discard_rxbuf(struct jme_softc *sc, int cons) 2384{ 2385 struct jme_desc *desc; 2386 2387 desc = &sc->jme_rdata.jme_rx_ring[cons]; 2388 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT); 2389 desc->buflen = htole32(MCLBYTES); 2390} 2391 2392/* Receive a frame. */ 2393static void 2394jme_rxeof(struct jme_softc *sc) 2395{ 2396 struct ifnet *ifp; 2397 struct jme_desc *desc; 2398 struct jme_rxdesc *rxd; 2399 struct mbuf *mp, *m; 2400 uint32_t flags, status; 2401 int cons, count, nsegs; 2402 2403 ifp = sc->jme_ifp; 2404 2405 cons = sc->jme_cdata.jme_rx_cons; 2406 desc = &sc->jme_rdata.jme_rx_ring[cons]; 2407 flags = le32toh(desc->flags); 2408 status = le32toh(desc->buflen); 2409 nsegs = JME_RX_NSEGS(status); 2410 sc->jme_cdata.jme_rxlen = JME_RX_BYTES(status) - JME_RX_PAD_BYTES; 2411 if ((status & JME_RX_ERR_STAT) != 0) { 2412 ifp->if_ierrors++; 2413 jme_discard_rxbuf(sc, sc->jme_cdata.jme_rx_cons); 2414#ifdef JME_SHOW_ERRORS 2415 device_printf(sc->jme_dev, "%s : receive error = 0x%b\n", 2416 __func__, JME_RX_ERR(status), JME_RX_ERR_BITS); 2417#endif 2418 sc->jme_cdata.jme_rx_cons += nsegs; 2419 sc->jme_cdata.jme_rx_cons %= JME_RX_RING_CNT; 2420 return; 2421 } 2422 2423 for (count = 0; count < nsegs; count++, 2424 JME_DESC_INC(cons, JME_RX_RING_CNT)) { 2425 rxd = &sc->jme_cdata.jme_rxdesc[cons]; 2426 mp = rxd->rx_m; 2427 /* Add a new receive buffer to the ring. */ 2428 if (jme_newbuf(sc, rxd) != 0) { 2429 ifp->if_iqdrops++; 2430 /* Reuse buffer. */ 2431 for (; count < nsegs; count++) { 2432 jme_discard_rxbuf(sc, cons); 2433 JME_DESC_INC(cons, JME_RX_RING_CNT); 2434 } 2435 if (sc->jme_cdata.jme_rxhead != NULL) { 2436 m_freem(sc->jme_cdata.jme_rxhead); 2437 JME_RXCHAIN_RESET(sc); 2438 } 2439 break; 2440 } 2441 2442 /* 2443 * Assume we've received a full sized frame. 2444 * Actual size is fixed when we encounter the end of 2445 * multi-segmented frame. 2446 */ 2447 mp->m_len = MCLBYTES; 2448 2449 /* Chain received mbufs. */ 2450 if (sc->jme_cdata.jme_rxhead == NULL) { 2451 sc->jme_cdata.jme_rxhead = mp; 2452 sc->jme_cdata.jme_rxtail = mp; 2453 } else { 2454 /* 2455 * Receive processor can receive a maximum frame 2456 * size of 65535 bytes. 2457 */ 2458 mp->m_flags &= ~M_PKTHDR; 2459 sc->jme_cdata.jme_rxtail->m_next = mp; 2460 sc->jme_cdata.jme_rxtail = mp; 2461 } 2462 2463 if (count == nsegs - 1) { 2464 /* Last desc. for this frame. */ 2465 m = sc->jme_cdata.jme_rxhead; 2466 m->m_flags |= M_PKTHDR; 2467 m->m_pkthdr.len = sc->jme_cdata.jme_rxlen; 2468 if (nsegs > 1) { 2469 /* Set first mbuf size. */ 2470 m->m_len = MCLBYTES - JME_RX_PAD_BYTES; 2471 /* Set last mbuf size. */ 2472 mp->m_len = sc->jme_cdata.jme_rxlen - 2473 ((MCLBYTES - JME_RX_PAD_BYTES) + 2474 (MCLBYTES * (nsegs - 2))); 2475 } else 2476 m->m_len = sc->jme_cdata.jme_rxlen; 2477 m->m_pkthdr.rcvif = ifp; 2478 2479 /* 2480 * Account for 10bytes auto padding which is used 2481 * to align IP header on 32bit boundary. Also note, 2482 * CRC bytes is automatically removed by the 2483 * hardware. 2484 */ 2485 m->m_data += JME_RX_PAD_BYTES; 2486 2487 /* Set checksum information. */ 2488 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && 2489 (flags & JME_RD_IPV4) != 0) { 2490 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2491 if ((flags & JME_RD_IPCSUM) != 0) 2492 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2493 if (((flags & JME_RD_MORE_FRAG) == 0) && 2494 ((flags & (JME_RD_TCP | JME_RD_TCPCSUM)) == 2495 (JME_RD_TCP | JME_RD_TCPCSUM) || 2496 (flags & (JME_RD_UDP | JME_RD_UDPCSUM)) == 2497 (JME_RD_UDP | JME_RD_UDPCSUM))) { 2498 m->m_pkthdr.csum_flags |= 2499 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2500 m->m_pkthdr.csum_data = 0xffff; 2501 } 2502 } 2503 2504 /* Check for VLAN tagged packets. */ 2505 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 2506 (flags & JME_RD_VLAN_TAG) != 0) { 2507 m->m_pkthdr.ether_vtag = 2508 flags & JME_RD_VLAN_MASK; 2509 m->m_flags |= M_VLANTAG; 2510 } 2511 2512 ifp->if_ipackets++; 2513 /* Pass it on. */ 2514 (*ifp->if_input)(ifp, m); 2515 2516 /* Reset mbuf chains. */ 2517 JME_RXCHAIN_RESET(sc); 2518 } 2519 } 2520 2521 sc->jme_cdata.jme_rx_cons += nsegs; 2522 sc->jme_cdata.jme_rx_cons %= JME_RX_RING_CNT; 2523} 2524 2525static int 2526jme_rxintr(struct jme_softc *sc, int count) 2527{ 2528 struct jme_desc *desc; 2529 int nsegs, prog, pktlen; 2530 2531 bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag, 2532 sc->jme_cdata.jme_rx_ring_map, 2533 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2534 2535 for (prog = 0; count > 0; prog++) { 2536 desc = &sc->jme_rdata.jme_rx_ring[sc->jme_cdata.jme_rx_cons]; 2537 if ((le32toh(desc->flags) & JME_RD_OWN) == JME_RD_OWN) 2538 break; 2539 if ((le32toh(desc->buflen) & JME_RD_VALID) == 0) 2540 break; 2541 nsegs = JME_RX_NSEGS(le32toh(desc->buflen)); 2542 /* 2543 * Check number of segments against received bytes. 2544 * Non-matching value would indicate that hardware 2545 * is still trying to update Rx descriptors. I'm not 2546 * sure whether this check is needed. 2547 */ 2548 pktlen = JME_RX_BYTES(le32toh(desc->buflen)); 2549 if (nsegs != ((pktlen + (MCLBYTES - 1)) / MCLBYTES)) 2550 break; 2551 prog++; 2552 /* Received a frame. */ 2553 jme_rxeof(sc); 2554 count -= nsegs; 2555 } 2556 2557 if (prog > 0) 2558 bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag, 2559 sc->jme_cdata.jme_rx_ring_map, 2560 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2561 2562 return (count > 0 ? 0 : EAGAIN); 2563} 2564 2565static void 2566jme_tick(void *arg) 2567{ 2568 struct jme_softc *sc; 2569 struct mii_data *mii; 2570 2571 sc = (struct jme_softc *)arg; 2572 2573 JME_LOCK_ASSERT(sc); 2574 2575 mii = device_get_softc(sc->jme_miibus); 2576 mii_tick(mii); 2577 /* 2578 * Reclaim Tx buffers that have been completed. It's not 2579 * needed here but it would release allocated mbuf chains 2580 * faster and limit the maximum delay to a hz. 2581 */ 2582 jme_txeof(sc); 2583 jme_stats_update(sc); 2584 jme_watchdog(sc); 2585 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc); 2586} 2587 2588static void 2589jme_reset(struct jme_softc *sc) 2590{ 2591 2592 /* Stop receiver, transmitter. */ 2593 jme_stop_rx(sc); 2594 jme_stop_tx(sc); 2595 CSR_WRITE_4(sc, JME_GHC, GHC_RESET); 2596 DELAY(10); 2597 CSR_WRITE_4(sc, JME_GHC, 0); 2598} 2599 2600static void 2601jme_init(void *xsc) 2602{ 2603 struct jme_softc *sc; 2604 2605 sc = (struct jme_softc *)xsc; 2606 JME_LOCK(sc); 2607 jme_init_locked(sc); 2608 JME_UNLOCK(sc); 2609} 2610 2611static void 2612jme_init_locked(struct jme_softc *sc) 2613{ 2614 struct ifnet *ifp; 2615 struct mii_data *mii; 2616 uint8_t eaddr[ETHER_ADDR_LEN]; 2617 bus_addr_t paddr; 2618 uint32_t reg; 2619 int error; 2620 2621 JME_LOCK_ASSERT(sc); 2622 2623 ifp = sc->jme_ifp; 2624 mii = device_get_softc(sc->jme_miibus); 2625 2626 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2627 return; 2628 /* 2629 * Cancel any pending I/O. 2630 */ 2631 jme_stop(sc); 2632 2633 /* 2634 * Reset the chip to a known state. 2635 */ 2636 jme_reset(sc); 2637 2638 /* Init descriptors. */ 2639 error = jme_init_rx_ring(sc); 2640 if (error != 0) { 2641 device_printf(sc->jme_dev, 2642 "%s: initialization failed: no memory for Rx buffers.\n", 2643 __func__); 2644 jme_stop(sc); 2645 return; 2646 } 2647 jme_init_tx_ring(sc); 2648 /* Initialize shadow status block. */ 2649 jme_init_ssb(sc); 2650 2651 /* Reprogram the station address. */ 2652 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 2653 CSR_WRITE_4(sc, JME_PAR0, 2654 eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]); 2655 CSR_WRITE_4(sc, JME_PAR1, eaddr[5] << 8 | eaddr[4]); 2656 2657 /* 2658 * Configure Tx queue. 2659 * Tx priority queue weight value : 0 2660 * Tx FIFO threshold for processing next packet : 16QW 2661 * Maximum Tx DMA length : 512 2662 * Allow Tx DMA burst. 2663 */ 2664 sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0); 2665 sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN); 2666 sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW; 2667 sc->jme_txcsr |= sc->jme_tx_dma_size; 2668 sc->jme_txcsr |= TXCSR_DMA_BURST; 2669 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr); 2670 2671 /* Set Tx descriptor counter. */ 2672 CSR_WRITE_4(sc, JME_TXQDC, JME_TX_RING_CNT); 2673 2674 /* Set Tx ring address to the hardware. */ 2675 paddr = JME_TX_RING_ADDR(sc, 0); 2676 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr)); 2677 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr)); 2678 2679 /* Configure TxMAC parameters. */ 2680 reg = TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB; 2681 reg |= TXMAC_THRESH_1_PKT; 2682 reg |= TXMAC_CRC_ENB | TXMAC_PAD_ENB; 2683 CSR_WRITE_4(sc, JME_TXMAC, reg); 2684 2685 /* 2686 * Configure Rx queue. 2687 * FIFO full threshold for transmitting Tx pause packet : 128T 2688 * FIFO threshold for processing next packet : 128QW 2689 * Rx queue 0 select 2690 * Max Rx DMA length : 128 2691 * Rx descriptor retry : 32 2692 * Rx descriptor retry time gap : 256ns 2693 * Don't receive runt/bad frame. 2694 */ 2695 sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T; 2696 /* 2697 * Since Rx FIFO size is 4K bytes, receiving frames larger 2698 * than 4K bytes will suffer from Rx FIFO overruns. So 2699 * decrease FIFO threshold to reduce the FIFO overruns for 2700 * frames larger than 4000 bytes. 2701 * For best performance of standard MTU sized frames use 2702 * maximum allowable FIFO threshold, 128QW. Note these do 2703 * not hold on chip full mask verion >=2. For these 2704 * controllers 64QW and 128QW are not valid value. 2705 */ 2706 if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 2) 2707 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW; 2708 else { 2709 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 2710 ETHER_CRC_LEN) > JME_RX_FIFO_SIZE) 2711 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW; 2712 else 2713 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW; 2714 } 2715 sc->jme_rxcsr |= sc->jme_rx_dma_size | RXCSR_RXQ_N_SEL(RXCSR_RXQ0); 2716 sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT); 2717 sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK; 2718 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr); 2719 2720 /* Set Rx descriptor counter. */ 2721 CSR_WRITE_4(sc, JME_RXQDC, JME_RX_RING_CNT); 2722 2723 /* Set Rx ring address to the hardware. */ 2724 paddr = JME_RX_RING_ADDR(sc, 0); 2725 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr)); 2726 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr)); 2727 2728 /* Clear receive filter. */ 2729 CSR_WRITE_4(sc, JME_RXMAC, 0); 2730 /* Set up the receive filter. */ 2731 jme_set_filter(sc); 2732 jme_set_vlan(sc); 2733 2734 /* 2735 * Disable all WOL bits as WOL can interfere normal Rx 2736 * operation. Also clear WOL detection status bits. 2737 */ 2738 reg = CSR_READ_4(sc, JME_PMCS); 2739 reg &= ~PMCS_WOL_ENB_MASK; 2740 CSR_WRITE_4(sc, JME_PMCS, reg); 2741 2742 reg = CSR_READ_4(sc, JME_RXMAC); 2743 /* 2744 * Pad 10bytes right before received frame. This will greatly 2745 * help Rx performance on strict-alignment architectures as 2746 * it does not need to copy the frame to align the payload. 2747 */ 2748 reg |= RXMAC_PAD_10BYTES; 2749 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2750 reg |= RXMAC_CSUM_ENB; 2751 CSR_WRITE_4(sc, JME_RXMAC, reg); 2752 2753 /* Configure general purpose reg0 */ 2754 reg = CSR_READ_4(sc, JME_GPREG0); 2755 reg &= ~GPREG0_PCC_UNIT_MASK; 2756 /* Set PCC timer resolution to micro-seconds unit. */ 2757 reg |= GPREG0_PCC_UNIT_US; 2758 /* 2759 * Disable all shadow register posting as we have to read 2760 * JME_INTR_STATUS register in jme_int_task. Also it seems 2761 * that it's hard to synchronize interrupt status between 2762 * hardware and software with shadow posting due to 2763 * requirements of bus_dmamap_sync(9). 2764 */ 2765 reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS | 2766 GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS | 2767 GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS | 2768 GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS; 2769 /* Disable posting of DW0. */ 2770 reg &= ~GPREG0_POST_DW0_ENB; 2771 /* Clear PME message. */ 2772 reg &= ~GPREG0_PME_ENB; 2773 /* Set PHY address. */ 2774 reg &= ~GPREG0_PHY_ADDR_MASK; 2775 reg |= sc->jme_phyaddr; 2776 CSR_WRITE_4(sc, JME_GPREG0, reg); 2777 2778 /* Configure Tx queue 0 packet completion coalescing. */ 2779 reg = (sc->jme_tx_coal_to << PCCTX_COAL_TO_SHIFT) & 2780 PCCTX_COAL_TO_MASK; 2781 reg |= (sc->jme_tx_coal_pkt << PCCTX_COAL_PKT_SHIFT) & 2782 PCCTX_COAL_PKT_MASK; 2783 reg |= PCCTX_COAL_TXQ0; 2784 CSR_WRITE_4(sc, JME_PCCTX, reg); 2785 2786 /* Configure Rx queue 0 packet completion coalescing. */ 2787 reg = (sc->jme_rx_coal_to << PCCRX_COAL_TO_SHIFT) & 2788 PCCRX_COAL_TO_MASK; 2789 reg |= (sc->jme_rx_coal_pkt << PCCRX_COAL_PKT_SHIFT) & 2790 PCCRX_COAL_PKT_MASK; 2791 CSR_WRITE_4(sc, JME_PCCRX0, reg); 2792 2793 /* Configure shadow status block but don't enable posting. */ 2794 paddr = sc->jme_rdata.jme_ssb_block_paddr; 2795 CSR_WRITE_4(sc, JME_SHBASE_ADDR_HI, JME_ADDR_HI(paddr)); 2796 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, JME_ADDR_LO(paddr)); 2797 2798 /* Disable Timer 1 and Timer 2. */ 2799 CSR_WRITE_4(sc, JME_TIMER1, 0); 2800 CSR_WRITE_4(sc, JME_TIMER2, 0); 2801 2802 /* Configure retry transmit period, retry limit value. */ 2803 CSR_WRITE_4(sc, JME_TXTRHD, 2804 ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) & 2805 TXTRHD_RT_PERIOD_MASK) | 2806 ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) & 2807 TXTRHD_RT_LIMIT_SHIFT)); 2808 2809 /* Disable RSS. */ 2810 CSR_WRITE_4(sc, JME_RSSC, RSSC_DIS_RSS); 2811 2812 /* Initialize the interrupt mask. */ 2813 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS); 2814 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF); 2815 2816 /* 2817 * Enabling Tx/Rx DMA engines and Rx queue processing is 2818 * done after detection of valid link in jme_link_task. 2819 */ 2820 2821 sc->jme_flags &= ~JME_FLAG_LINK; 2822 /* Set the current media. */ 2823 mii_mediachg(mii); 2824 2825 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc); 2826 2827 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2828 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2829} 2830 2831static void 2832jme_stop(struct jme_softc *sc) 2833{ 2834 struct ifnet *ifp; 2835 struct jme_txdesc *txd; 2836 struct jme_rxdesc *rxd; 2837 int i; 2838 2839 JME_LOCK_ASSERT(sc); 2840 /* 2841 * Mark the interface down and cancel the watchdog timer. 2842 */ 2843 ifp = sc->jme_ifp; 2844 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2845 sc->jme_flags &= ~JME_FLAG_LINK; 2846 callout_stop(&sc->jme_tick_ch); 2847 sc->jme_watchdog_timer = 0; 2848 2849 /* 2850 * Disable interrupts. 2851 */ 2852 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS); 2853 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF); 2854 2855 /* Disable updating shadow status block. */ 2856 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, 2857 CSR_READ_4(sc, JME_SHBASE_ADDR_LO) & ~SHBASE_POST_ENB); 2858 2859 /* Stop receiver, transmitter. */ 2860 jme_stop_rx(sc); 2861 jme_stop_tx(sc); 2862 2863 /* Reclaim Rx/Tx buffers that have been completed. */ 2864 jme_rxintr(sc, JME_RX_RING_CNT); 2865 if (sc->jme_cdata.jme_rxhead != NULL) 2866 m_freem(sc->jme_cdata.jme_rxhead); 2867 JME_RXCHAIN_RESET(sc); 2868 jme_txeof(sc); 2869 /* 2870 * Free RX and TX mbufs still in the queues. 2871 */ 2872 for (i = 0; i < JME_RX_RING_CNT; i++) { 2873 rxd = &sc->jme_cdata.jme_rxdesc[i]; 2874 if (rxd->rx_m != NULL) { 2875 bus_dmamap_sync(sc->jme_cdata.jme_rx_tag, 2876 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2877 bus_dmamap_unload(sc->jme_cdata.jme_rx_tag, 2878 rxd->rx_dmamap); 2879 m_freem(rxd->rx_m); 2880 rxd->rx_m = NULL; 2881 } 2882 } 2883 for (i = 0; i < JME_TX_RING_CNT; i++) { 2884 txd = &sc->jme_cdata.jme_txdesc[i]; 2885 if (txd->tx_m != NULL) { 2886 bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, 2887 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2888 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, 2889 txd->tx_dmamap); 2890 m_freem(txd->tx_m); 2891 txd->tx_m = NULL; 2892 txd->tx_ndesc = 0; 2893 } 2894 } 2895 jme_stats_update(sc); 2896 jme_stats_save(sc); 2897} 2898 2899static void 2900jme_stop_tx(struct jme_softc *sc) 2901{ 2902 uint32_t reg; 2903 int i; 2904 2905 reg = CSR_READ_4(sc, JME_TXCSR); 2906 if ((reg & TXCSR_TX_ENB) == 0) 2907 return; 2908 reg &= ~TXCSR_TX_ENB; 2909 CSR_WRITE_4(sc, JME_TXCSR, reg); 2910 for (i = JME_TIMEOUT; i > 0; i--) { 2911 DELAY(1); 2912 if ((CSR_READ_4(sc, JME_TXCSR) & TXCSR_TX_ENB) == 0) 2913 break; 2914 } 2915 if (i == 0) 2916 device_printf(sc->jme_dev, "stopping transmitter timeout!\n"); 2917} 2918 2919static void 2920jme_stop_rx(struct jme_softc *sc) 2921{ 2922 uint32_t reg; 2923 int i; 2924 2925 reg = CSR_READ_4(sc, JME_RXCSR); 2926 if ((reg & RXCSR_RX_ENB) == 0) 2927 return; 2928 reg &= ~RXCSR_RX_ENB; 2929 CSR_WRITE_4(sc, JME_RXCSR, reg); 2930 for (i = JME_TIMEOUT; i > 0; i--) { 2931 DELAY(1); 2932 if ((CSR_READ_4(sc, JME_RXCSR) & RXCSR_RX_ENB) == 0) 2933 break; 2934 } 2935 if (i == 0) 2936 device_printf(sc->jme_dev, "stopping recevier timeout!\n"); 2937} 2938 2939static void 2940jme_init_tx_ring(struct jme_softc *sc) 2941{ 2942 struct jme_ring_data *rd; 2943 struct jme_txdesc *txd; 2944 int i; 2945 2946 sc->jme_cdata.jme_tx_prod = 0; 2947 sc->jme_cdata.jme_tx_cons = 0; 2948 sc->jme_cdata.jme_tx_cnt = 0; 2949 2950 rd = &sc->jme_rdata; 2951 bzero(rd->jme_tx_ring, JME_TX_RING_SIZE); 2952 for (i = 0; i < JME_TX_RING_CNT; i++) { 2953 txd = &sc->jme_cdata.jme_txdesc[i]; 2954 txd->tx_m = NULL; 2955 txd->tx_desc = &rd->jme_tx_ring[i]; 2956 txd->tx_ndesc = 0; 2957 } 2958 2959 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag, 2960 sc->jme_cdata.jme_tx_ring_map, 2961 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2962} 2963 2964static void 2965jme_init_ssb(struct jme_softc *sc) 2966{ 2967 struct jme_ring_data *rd; 2968 2969 rd = &sc->jme_rdata; 2970 bzero(rd->jme_ssb_block, JME_SSB_SIZE); 2971 bus_dmamap_sync(sc->jme_cdata.jme_ssb_tag, sc->jme_cdata.jme_ssb_map, 2972 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2973} 2974 2975static int 2976jme_init_rx_ring(struct jme_softc *sc) 2977{ 2978 struct jme_ring_data *rd; 2979 struct jme_rxdesc *rxd; 2980 int i; 2981 2982 sc->jme_cdata.jme_rx_cons = 0; 2983 JME_RXCHAIN_RESET(sc); 2984 sc->jme_morework = 0; 2985 2986 rd = &sc->jme_rdata; 2987 bzero(rd->jme_rx_ring, JME_RX_RING_SIZE); 2988 for (i = 0; i < JME_RX_RING_CNT; i++) { 2989 rxd = &sc->jme_cdata.jme_rxdesc[i]; 2990 rxd->rx_m = NULL; 2991 rxd->rx_desc = &rd->jme_rx_ring[i]; 2992 if (jme_newbuf(sc, rxd) != 0) 2993 return (ENOBUFS); 2994 } 2995 2996 bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag, 2997 sc->jme_cdata.jme_rx_ring_map, 2998 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2999 3000 return (0); 3001} 3002 3003static int 3004jme_newbuf(struct jme_softc *sc, struct jme_rxdesc *rxd) 3005{ 3006 struct jme_desc *desc; 3007 struct mbuf *m; 3008 bus_dma_segment_t segs[1]; 3009 bus_dmamap_t map; 3010 int nsegs; 3011 3012 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 3013 if (m == NULL) 3014 return (ENOBUFS); 3015 /* 3016 * JMC250 has 64bit boundary alignment limitation so jme(4) 3017 * takes advantage of 10 bytes padding feature of hardware 3018 * in order not to copy entire frame to align IP header on 3019 * 32bit boundary. 3020 */ 3021 m->m_len = m->m_pkthdr.len = MCLBYTES; 3022 3023 if (bus_dmamap_load_mbuf_sg(sc->jme_cdata.jme_rx_tag, 3024 sc->jme_cdata.jme_rx_sparemap, m, segs, &nsegs, 0) != 0) { 3025 m_freem(m); 3026 return (ENOBUFS); 3027 } 3028 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 3029 3030 if (rxd->rx_m != NULL) { 3031 bus_dmamap_sync(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap, 3032 BUS_DMASYNC_POSTREAD); 3033 bus_dmamap_unload(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap); 3034 } 3035 map = rxd->rx_dmamap; 3036 rxd->rx_dmamap = sc->jme_cdata.jme_rx_sparemap; 3037 sc->jme_cdata.jme_rx_sparemap = map; 3038 bus_dmamap_sync(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap, 3039 BUS_DMASYNC_PREREAD); 3040 rxd->rx_m = m; 3041 3042 desc = rxd->rx_desc; 3043 desc->buflen = htole32(segs[0].ds_len); 3044 desc->addr_lo = htole32(JME_ADDR_LO(segs[0].ds_addr)); 3045 desc->addr_hi = htole32(JME_ADDR_HI(segs[0].ds_addr)); 3046 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT); 3047 3048 return (0); 3049} 3050 3051static void 3052jme_set_vlan(struct jme_softc *sc) 3053{ 3054 struct ifnet *ifp; 3055 uint32_t reg; 3056 3057 JME_LOCK_ASSERT(sc); 3058 3059 ifp = sc->jme_ifp; 3060 reg = CSR_READ_4(sc, JME_RXMAC); 3061 reg &= ~RXMAC_VLAN_ENB; 3062 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3063 reg |= RXMAC_VLAN_ENB; 3064 CSR_WRITE_4(sc, JME_RXMAC, reg); 3065} 3066 3067static void 3068jme_set_filter(struct jme_softc *sc) 3069{ 3070 struct ifnet *ifp; 3071 struct ifmultiaddr *ifma; 3072 uint32_t crc; 3073 uint32_t mchash[2]; 3074 uint32_t rxcfg; 3075 3076 JME_LOCK_ASSERT(sc); 3077 3078 ifp = sc->jme_ifp; 3079 3080 rxcfg = CSR_READ_4(sc, JME_RXMAC); 3081 rxcfg &= ~ (RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST | 3082 RXMAC_ALLMULTI); 3083 /* Always accept frames destined to our station address. */ 3084 rxcfg |= RXMAC_UNICAST; 3085 if ((ifp->if_flags & IFF_BROADCAST) != 0) 3086 rxcfg |= RXMAC_BROADCAST; 3087 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3088 if ((ifp->if_flags & IFF_PROMISC) != 0) 3089 rxcfg |= RXMAC_PROMISC; 3090 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 3091 rxcfg |= RXMAC_ALLMULTI; 3092 CSR_WRITE_4(sc, JME_MAR0, 0xFFFFFFFF); 3093 CSR_WRITE_4(sc, JME_MAR1, 0xFFFFFFFF); 3094 CSR_WRITE_4(sc, JME_RXMAC, rxcfg); 3095 return; 3096 } 3097 3098 /* 3099 * Set up the multicast address filter by passing all multicast 3100 * addresses through a CRC generator, and then using the low-order 3101 * 6 bits as an index into the 64 bit multicast hash table. The 3102 * high order bits select the register, while the rest of the bits 3103 * select the bit within the register. 3104 */ 3105 rxcfg |= RXMAC_MULTICAST; 3106 bzero(mchash, sizeof(mchash)); 3107 3108 if_maddr_rlock(ifp); 3109 TAILQ_FOREACH(ifma, &sc->jme_ifp->if_multiaddrs, ifma_link) { 3110 if (ifma->ifma_addr->sa_family != AF_LINK) 3111 continue; 3112 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 3113 ifma->ifma_addr), ETHER_ADDR_LEN); 3114 3115 /* Just want the 6 least significant bits. */ 3116 crc &= 0x3f; 3117 3118 /* Set the corresponding bit in the hash table. */ 3119 mchash[crc >> 5] |= 1 << (crc & 0x1f); 3120 } 3121 if_maddr_runlock(ifp); 3122 3123 CSR_WRITE_4(sc, JME_MAR0, mchash[0]); 3124 CSR_WRITE_4(sc, JME_MAR1, mchash[1]); 3125 CSR_WRITE_4(sc, JME_RXMAC, rxcfg); 3126} 3127 3128static void 3129jme_stats_clear(struct jme_softc *sc) 3130{ 3131 3132 JME_LOCK_ASSERT(sc); 3133 3134 if ((sc->jme_flags & JME_FLAG_HWMIB) == 0) 3135 return; 3136 3137 /* Disable and clear counters. */ 3138 CSR_WRITE_4(sc, JME_STATCSR, 0xFFFFFFFF); 3139 /* Activate hw counters. */ 3140 CSR_WRITE_4(sc, JME_STATCSR, 0); 3141 CSR_READ_4(sc, JME_STATCSR); 3142 bzero(&sc->jme_stats, sizeof(struct jme_hw_stats)); 3143} 3144 3145static void 3146jme_stats_save(struct jme_softc *sc) 3147{ 3148 3149 JME_LOCK_ASSERT(sc); 3150 3151 if ((sc->jme_flags & JME_FLAG_HWMIB) == 0) 3152 return; 3153 /* Save current counters. */ 3154 bcopy(&sc->jme_stats, &sc->jme_ostats, sizeof(struct jme_hw_stats)); 3155 /* Disable and clear counters. */ 3156 CSR_WRITE_4(sc, JME_STATCSR, 0xFFFFFFFF); 3157} 3158 3159static void 3160jme_stats_update(struct jme_softc *sc) 3161{ 3162 struct jme_hw_stats *stat, *ostat; 3163 uint32_t reg; 3164 3165 JME_LOCK_ASSERT(sc); 3166 3167 if ((sc->jme_flags & JME_FLAG_HWMIB) == 0) 3168 return; 3169 stat = &sc->jme_stats; 3170 ostat = &sc->jme_ostats; 3171 stat->tx_good_frames = CSR_READ_4(sc, JME_STAT_TXGOOD); 3172 stat->rx_good_frames = CSR_READ_4(sc, JME_STAT_RXGOOD); 3173 reg = CSR_READ_4(sc, JME_STAT_CRCMII); 3174 stat->rx_crc_errs = (reg & STAT_RX_CRC_ERR_MASK) >> 3175 STAT_RX_CRC_ERR_SHIFT; 3176 stat->rx_mii_errs = (reg & STAT_RX_MII_ERR_MASK) >> 3177 STAT_RX_MII_ERR_SHIFT; 3178 reg = CSR_READ_4(sc, JME_STAT_RXERR); 3179 stat->rx_fifo_oflows = (reg & STAT_RXERR_OFLOW_MASK) >> 3180 STAT_RXERR_OFLOW_SHIFT; 3181 stat->rx_desc_empty = (reg & STAT_RXERR_MPTY_MASK) >> 3182 STAT_RXERR_MPTY_SHIFT; 3183 reg = CSR_READ_4(sc, JME_STAT_FAIL); 3184 stat->rx_bad_frames = (reg & STAT_FAIL_RX_MASK) >> STAT_FAIL_RX_SHIFT; 3185 stat->tx_bad_frames = (reg & STAT_FAIL_TX_MASK) >> STAT_FAIL_TX_SHIFT; 3186 3187 /* Account for previous counters. */ 3188 stat->rx_good_frames += ostat->rx_good_frames; 3189 stat->rx_crc_errs += ostat->rx_crc_errs; 3190 stat->rx_mii_errs += ostat->rx_mii_errs; 3191 stat->rx_fifo_oflows += ostat->rx_fifo_oflows; 3192 stat->rx_desc_empty += ostat->rx_desc_empty; 3193 stat->rx_bad_frames += ostat->rx_bad_frames; 3194 stat->tx_good_frames += ostat->tx_good_frames; 3195 stat->tx_bad_frames += ostat->tx_bad_frames; 3196} 3197 3198static int 3199sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3200{ 3201 int error, value; 3202 3203 if (arg1 == NULL) 3204 return (EINVAL); 3205 value = *(int *)arg1; 3206 error = sysctl_handle_int(oidp, &value, 0, req); 3207 if (error || req->newptr == NULL) 3208 return (error); 3209 if (value < low || value > high) 3210 return (EINVAL); 3211 *(int *)arg1 = value; 3212 3213 return (0); 3214} 3215 3216static int 3217sysctl_hw_jme_tx_coal_to(SYSCTL_HANDLER_ARGS) 3218{ 3219 return (sysctl_int_range(oidp, arg1, arg2, req, 3220 PCCTX_COAL_TO_MIN, PCCTX_COAL_TO_MAX)); 3221} 3222 3223static int 3224sysctl_hw_jme_tx_coal_pkt(SYSCTL_HANDLER_ARGS) 3225{ 3226 return (sysctl_int_range(oidp, arg1, arg2, req, 3227 PCCTX_COAL_PKT_MIN, PCCTX_COAL_PKT_MAX)); 3228} 3229 3230static int 3231sysctl_hw_jme_rx_coal_to(SYSCTL_HANDLER_ARGS) 3232{ 3233 return (sysctl_int_range(oidp, arg1, arg2, req, 3234 PCCRX_COAL_TO_MIN, PCCRX_COAL_TO_MAX)); 3235} 3236 3237static int 3238sysctl_hw_jme_rx_coal_pkt(SYSCTL_HANDLER_ARGS) 3239{ 3240 return (sysctl_int_range(oidp, arg1, arg2, req, 3241 PCCRX_COAL_PKT_MIN, PCCRX_COAL_PKT_MAX)); 3242} 3243 3244static int 3245sysctl_hw_jme_proc_limit(SYSCTL_HANDLER_ARGS) 3246{ 3247 return (sysctl_int_range(oidp, arg1, arg2, req, 3248 JME_PROC_MIN, JME_PROC_MAX)); 3249} 3250