if_jme.c revision 185596
1/*- 2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: head/sys/dev/jme/if_jme.c 185596 2008-12-04 01:58:40Z yongari $"); 30 31#include <sys/param.h> 32#include <sys/systm.h> 33#include <sys/bus.h> 34#include <sys/endian.h> 35#include <sys/kernel.h> 36#include <sys/malloc.h> 37#include <sys/mbuf.h> 38#include <sys/rman.h> 39#include <sys/module.h> 40#include <sys/proc.h> 41#include <sys/queue.h> 42#include <sys/socket.h> 43#include <sys/sockio.h> 44#include <sys/sysctl.h> 45#include <sys/taskqueue.h> 46 47#include <net/bpf.h> 48#include <net/if.h> 49#include <net/if_arp.h> 50#include <net/ethernet.h> 51#include <net/if_dl.h> 52#include <net/if_media.h> 53#include <net/if_types.h> 54#include <net/if_vlan_var.h> 55 56#include <netinet/in.h> 57#include <netinet/in_systm.h> 58#include <netinet/ip.h> 59#include <netinet/tcp.h> 60 61#include <dev/mii/mii.h> 62#include <dev/mii/miivar.h> 63 64#include <dev/pci/pcireg.h> 65#include <dev/pci/pcivar.h> 66 67#include <machine/atomic.h> 68#include <machine/bus.h> 69#include <machine/in_cksum.h> 70 71#include <dev/jme/if_jmereg.h> 72#include <dev/jme/if_jmevar.h> 73 74/* "device miibus" required. See GENERIC if you get errors here. */ 75#include "miibus_if.h" 76 77/* Define the following to disable printing Rx errors. */ 78#undef JME_SHOW_ERRORS 79 80#define JME_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 81 82MODULE_DEPEND(jme, pci, 1, 1, 1); 83MODULE_DEPEND(jme, ether, 1, 1, 1); 84MODULE_DEPEND(jme, miibus, 1, 1, 1); 85 86/* Tunables. */ 87static int msi_disable = 0; 88static int msix_disable = 0; 89TUNABLE_INT("hw.jme.msi_disable", &msi_disable); 90TUNABLE_INT("hw.jme.msix_disable", &msix_disable); 91 92/* 93 * Devices supported by this driver. 94 */ 95static struct jme_dev { 96 uint16_t jme_vendorid; 97 uint16_t jme_deviceid; 98 const char *jme_name; 99} jme_devs[] = { 100 { VENDORID_JMICRON, DEVICEID_JMC250, 101 "JMicron Inc, JMC250 Gigabit Ethernet" }, 102 { VENDORID_JMICRON, DEVICEID_JMC260, 103 "JMicron Inc, JMC260 Fast Ethernet" }, 104}; 105 106static int jme_miibus_readreg(device_t, int, int); 107static int jme_miibus_writereg(device_t, int, int, int); 108static void jme_miibus_statchg(device_t); 109static void jme_mediastatus(struct ifnet *, struct ifmediareq *); 110static int jme_mediachange(struct ifnet *); 111static int jme_probe(device_t); 112static int jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *); 113static int jme_eeprom_macaddr(struct jme_softc *); 114static void jme_reg_macaddr(struct jme_softc *); 115static void jme_map_intr_vector(struct jme_softc *); 116static int jme_attach(device_t); 117static int jme_detach(device_t); 118static void jme_sysctl_node(struct jme_softc *); 119static void jme_dmamap_cb(void *, bus_dma_segment_t *, int, int); 120static int jme_dma_alloc(struct jme_softc *); 121static void jme_dma_free(struct jme_softc *); 122static int jme_shutdown(device_t); 123static void jme_setlinkspeed(struct jme_softc *); 124static void jme_setwol(struct jme_softc *); 125static int jme_suspend(device_t); 126static int jme_resume(device_t); 127static int jme_encap(struct jme_softc *, struct mbuf **); 128static void jme_tx_task(void *, int); 129static void jme_start(struct ifnet *); 130static void jme_watchdog(struct jme_softc *); 131static int jme_ioctl(struct ifnet *, u_long, caddr_t); 132static void jme_mac_config(struct jme_softc *); 133static void jme_link_task(void *, int); 134static int jme_intr(void *); 135static void jme_int_task(void *, int); 136static void jme_txeof(struct jme_softc *); 137static __inline void jme_discard_rxbuf(struct jme_softc *, int); 138static void jme_rxeof(struct jme_softc *); 139static int jme_rxintr(struct jme_softc *, int); 140static void jme_tick(void *); 141static void jme_reset(struct jme_softc *); 142static void jme_init(void *); 143static void jme_init_locked(struct jme_softc *); 144static void jme_stop(struct jme_softc *); 145static void jme_stop_tx(struct jme_softc *); 146static void jme_stop_rx(struct jme_softc *); 147static int jme_init_rx_ring(struct jme_softc *); 148static void jme_init_tx_ring(struct jme_softc *); 149static void jme_init_ssb(struct jme_softc *); 150static int jme_newbuf(struct jme_softc *, struct jme_rxdesc *); 151static void jme_set_vlan(struct jme_softc *); 152static void jme_set_filter(struct jme_softc *); 153static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 154static int sysctl_hw_jme_tx_coal_to(SYSCTL_HANDLER_ARGS); 155static int sysctl_hw_jme_tx_coal_pkt(SYSCTL_HANDLER_ARGS); 156static int sysctl_hw_jme_rx_coal_to(SYSCTL_HANDLER_ARGS); 157static int sysctl_hw_jme_rx_coal_pkt(SYSCTL_HANDLER_ARGS); 158static int sysctl_hw_jme_proc_limit(SYSCTL_HANDLER_ARGS); 159 160 161static device_method_t jme_methods[] = { 162 /* Device interface. */ 163 DEVMETHOD(device_probe, jme_probe), 164 DEVMETHOD(device_attach, jme_attach), 165 DEVMETHOD(device_detach, jme_detach), 166 DEVMETHOD(device_shutdown, jme_shutdown), 167 DEVMETHOD(device_suspend, jme_suspend), 168 DEVMETHOD(device_resume, jme_resume), 169 170 /* MII interface. */ 171 DEVMETHOD(miibus_readreg, jme_miibus_readreg), 172 DEVMETHOD(miibus_writereg, jme_miibus_writereg), 173 DEVMETHOD(miibus_statchg, jme_miibus_statchg), 174 175 { NULL, NULL } 176}; 177 178static driver_t jme_driver = { 179 "jme", 180 jme_methods, 181 sizeof(struct jme_softc) 182}; 183 184static devclass_t jme_devclass; 185 186DRIVER_MODULE(jme, pci, jme_driver, jme_devclass, 0, 0); 187DRIVER_MODULE(miibus, jme, miibus_driver, miibus_devclass, 0, 0); 188 189static struct resource_spec jme_res_spec_mem[] = { 190 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 191 { -1, 0, 0 } 192}; 193 194static struct resource_spec jme_irq_spec_legacy[] = { 195 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 196 { -1, 0, 0 } 197}; 198 199static struct resource_spec jme_irq_spec_msi[] = { 200 { SYS_RES_IRQ, 1, RF_ACTIVE }, 201 { SYS_RES_IRQ, 2, RF_ACTIVE }, 202 { SYS_RES_IRQ, 3, RF_ACTIVE }, 203 { SYS_RES_IRQ, 4, RF_ACTIVE }, 204 { SYS_RES_IRQ, 5, RF_ACTIVE }, 205 { SYS_RES_IRQ, 6, RF_ACTIVE }, 206 { SYS_RES_IRQ, 7, RF_ACTIVE }, 207 { SYS_RES_IRQ, 8, RF_ACTIVE }, 208 { -1, 0, 0 } 209}; 210 211/* 212 * Read a PHY register on the MII of the JMC250. 213 */ 214static int 215jme_miibus_readreg(device_t dev, int phy, int reg) 216{ 217 struct jme_softc *sc; 218 uint32_t val; 219 int i; 220 221 sc = device_get_softc(dev); 222 223 /* For FPGA version, PHY address 0 should be ignored. */ 224 if ((sc->jme_flags & JME_FLAG_FPGA) != 0) { 225 if (phy == 0) 226 return (0); 227 } else { 228 if (sc->jme_phyaddr != phy) 229 return (0); 230 } 231 232 CSR_WRITE_4(sc, JME_SMI, SMI_OP_READ | SMI_OP_EXECUTE | 233 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg)); 234 for (i = JME_PHY_TIMEOUT; i > 0; i--) { 235 DELAY(1); 236 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0) 237 break; 238 } 239 240 if (i == 0) { 241 device_printf(sc->jme_dev, "phy read timeout : %d\n", reg); 242 return (0); 243 } 244 245 return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT); 246} 247 248/* 249 * Write a PHY register on the MII of the JMC250. 250 */ 251static int 252jme_miibus_writereg(device_t dev, int phy, int reg, int val) 253{ 254 struct jme_softc *sc; 255 int i; 256 257 sc = device_get_softc(dev); 258 259 /* For FPGA version, PHY address 0 should be ignored. */ 260 if ((sc->jme_flags & JME_FLAG_FPGA) != 0) { 261 if (phy == 0) 262 return (0); 263 } else { 264 if (sc->jme_phyaddr != phy) 265 return (0); 266 } 267 268 CSR_WRITE_4(sc, JME_SMI, SMI_OP_WRITE | SMI_OP_EXECUTE | 269 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) | 270 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg)); 271 for (i = JME_PHY_TIMEOUT; i > 0; i--) { 272 DELAY(1); 273 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0) 274 break; 275 } 276 277 if (i == 0) 278 device_printf(sc->jme_dev, "phy write timeout : %d\n", reg); 279 280 return (0); 281} 282 283/* 284 * Callback from MII layer when media changes. 285 */ 286static void 287jme_miibus_statchg(device_t dev) 288{ 289 struct jme_softc *sc; 290 291 sc = device_get_softc(dev); 292 taskqueue_enqueue(taskqueue_swi, &sc->jme_link_task); 293} 294 295/* 296 * Get the current interface media status. 297 */ 298static void 299jme_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 300{ 301 struct jme_softc *sc; 302 struct mii_data *mii; 303 304 sc = ifp->if_softc; 305 JME_LOCK(sc); 306 mii = device_get_softc(sc->jme_miibus); 307 308 mii_pollstat(mii); 309 ifmr->ifm_status = mii->mii_media_status; 310 ifmr->ifm_active = mii->mii_media_active; 311 JME_UNLOCK(sc); 312} 313 314/* 315 * Set hardware to newly-selected media. 316 */ 317static int 318jme_mediachange(struct ifnet *ifp) 319{ 320 struct jme_softc *sc; 321 struct mii_data *mii; 322 struct mii_softc *miisc; 323 int error; 324 325 sc = ifp->if_softc; 326 JME_LOCK(sc); 327 mii = device_get_softc(sc->jme_miibus); 328 if (mii->mii_instance != 0) { 329 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 330 mii_phy_reset(miisc); 331 } 332 error = mii_mediachg(mii); 333 JME_UNLOCK(sc); 334 335 return (error); 336} 337 338static int 339jme_probe(device_t dev) 340{ 341 struct jme_dev *sp; 342 int i; 343 uint16_t vendor, devid; 344 345 vendor = pci_get_vendor(dev); 346 devid = pci_get_device(dev); 347 sp = jme_devs; 348 for (i = 0; i < sizeof(jme_devs) / sizeof(jme_devs[0]); 349 i++, sp++) { 350 if (vendor == sp->jme_vendorid && 351 devid == sp->jme_deviceid) { 352 device_set_desc(dev, sp->jme_name); 353 return (BUS_PROBE_DEFAULT); 354 } 355 } 356 357 return (ENXIO); 358} 359 360static int 361jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val) 362{ 363 uint32_t reg; 364 int i; 365 366 *val = 0; 367 for (i = JME_TIMEOUT; i > 0; i--) { 368 reg = CSR_READ_4(sc, JME_SMBCSR); 369 if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE) 370 break; 371 DELAY(1); 372 } 373 374 if (i == 0) { 375 device_printf(sc->jme_dev, "EEPROM idle timeout!\n"); 376 return (ETIMEDOUT); 377 } 378 379 reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK; 380 CSR_WRITE_4(sc, JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER); 381 for (i = JME_TIMEOUT; i > 0; i--) { 382 DELAY(1); 383 reg = CSR_READ_4(sc, JME_SMBINTF); 384 if ((reg & SMBINTF_CMD_TRIGGER) == 0) 385 break; 386 } 387 388 if (i == 0) { 389 device_printf(sc->jme_dev, "EEPROM read timeout!\n"); 390 return (ETIMEDOUT); 391 } 392 393 reg = CSR_READ_4(sc, JME_SMBINTF); 394 *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT; 395 396 return (0); 397} 398 399static int 400jme_eeprom_macaddr(struct jme_softc *sc) 401{ 402 uint8_t eaddr[ETHER_ADDR_LEN]; 403 uint8_t fup, reg, val; 404 uint32_t offset; 405 int match; 406 407 offset = 0; 408 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 || 409 fup != JME_EEPROM_SIG0) 410 return (ENOENT); 411 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 || 412 fup != JME_EEPROM_SIG1) 413 return (ENOENT); 414 match = 0; 415 do { 416 if (jme_eeprom_read_byte(sc, offset, &fup) != 0) 417 break; 418 if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1) == 419 (fup & (JME_EEPROM_FUNC_MASK | JME_EEPROM_PAGE_MASK))) { 420 if (jme_eeprom_read_byte(sc, offset + 1, ®) != 0) 421 break; 422 if (reg >= JME_PAR0 && 423 reg < JME_PAR0 + ETHER_ADDR_LEN) { 424 if (jme_eeprom_read_byte(sc, offset + 2, 425 &val) != 0) 426 break; 427 eaddr[reg - JME_PAR0] = val; 428 match++; 429 } 430 } 431 /* Check for the end of EEPROM descriptor. */ 432 if ((fup & JME_EEPROM_DESC_END) == JME_EEPROM_DESC_END) 433 break; 434 /* Try next eeprom descriptor. */ 435 offset += JME_EEPROM_DESC_BYTES; 436 } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END); 437 438 if (match == ETHER_ADDR_LEN) { 439 bcopy(eaddr, sc->jme_eaddr, ETHER_ADDR_LEN); 440 return (0); 441 } 442 443 return (ENOENT); 444} 445 446static void 447jme_reg_macaddr(struct jme_softc *sc) 448{ 449 uint32_t par0, par1; 450 451 /* Read station address. */ 452 par0 = CSR_READ_4(sc, JME_PAR0); 453 par1 = CSR_READ_4(sc, JME_PAR1); 454 par1 &= 0xFFFF; 455 if ((par0 == 0 && par1 == 0) || 456 (par0 == 0xFFFFFFFF && par1 == 0xFFFF)) { 457 device_printf(sc->jme_dev, 458 "generating fake ethernet address.\n"); 459 par0 = arc4random(); 460 /* Set OUI to JMicron. */ 461 sc->jme_eaddr[0] = 0x00; 462 sc->jme_eaddr[1] = 0x1B; 463 sc->jme_eaddr[2] = 0x8C; 464 sc->jme_eaddr[3] = (par0 >> 16) & 0xff; 465 sc->jme_eaddr[4] = (par0 >> 8) & 0xff; 466 sc->jme_eaddr[5] = par0 & 0xff; 467 } else { 468 sc->jme_eaddr[0] = (par0 >> 0) & 0xFF; 469 sc->jme_eaddr[1] = (par0 >> 8) & 0xFF; 470 sc->jme_eaddr[2] = (par0 >> 16) & 0xFF; 471 sc->jme_eaddr[3] = (par0 >> 24) & 0xFF; 472 sc->jme_eaddr[4] = (par1 >> 0) & 0xFF; 473 sc->jme_eaddr[5] = (par1 >> 8) & 0xFF; 474 } 475} 476 477static void 478jme_map_intr_vector(struct jme_softc *sc) 479{ 480 uint32_t map[MSINUM_NUM_INTR_SOURCE / JME_MSI_MESSAGES]; 481 482 bzero(map, sizeof(map)); 483 484 /* Map Tx interrupts source to MSI/MSIX vector 2. */ 485 map[MSINUM_REG_INDEX(N_INTR_TXQ0_COMP)] = 486 MSINUM_INTR_SOURCE(2, N_INTR_TXQ0_COMP); 487 map[MSINUM_REG_INDEX(N_INTR_TXQ1_COMP)] |= 488 MSINUM_INTR_SOURCE(2, N_INTR_TXQ1_COMP); 489 map[MSINUM_REG_INDEX(N_INTR_TXQ2_COMP)] |= 490 MSINUM_INTR_SOURCE(2, N_INTR_TXQ2_COMP); 491 map[MSINUM_REG_INDEX(N_INTR_TXQ3_COMP)] |= 492 MSINUM_INTR_SOURCE(2, N_INTR_TXQ3_COMP); 493 map[MSINUM_REG_INDEX(N_INTR_TXQ4_COMP)] |= 494 MSINUM_INTR_SOURCE(2, N_INTR_TXQ4_COMP); 495 map[MSINUM_REG_INDEX(N_INTR_TXQ4_COMP)] |= 496 MSINUM_INTR_SOURCE(2, N_INTR_TXQ5_COMP); 497 map[MSINUM_REG_INDEX(N_INTR_TXQ6_COMP)] |= 498 MSINUM_INTR_SOURCE(2, N_INTR_TXQ6_COMP); 499 map[MSINUM_REG_INDEX(N_INTR_TXQ7_COMP)] |= 500 MSINUM_INTR_SOURCE(2, N_INTR_TXQ7_COMP); 501 map[MSINUM_REG_INDEX(N_INTR_TXQ_COAL)] |= 502 MSINUM_INTR_SOURCE(2, N_INTR_TXQ_COAL); 503 map[MSINUM_REG_INDEX(N_INTR_TXQ_COAL_TO)] |= 504 MSINUM_INTR_SOURCE(2, N_INTR_TXQ_COAL_TO); 505 506 /* Map Rx interrupts source to MSI/MSIX vector 1. */ 507 map[MSINUM_REG_INDEX(N_INTR_RXQ0_COMP)] = 508 MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COMP); 509 map[MSINUM_REG_INDEX(N_INTR_RXQ1_COMP)] = 510 MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COMP); 511 map[MSINUM_REG_INDEX(N_INTR_RXQ2_COMP)] = 512 MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COMP); 513 map[MSINUM_REG_INDEX(N_INTR_RXQ3_COMP)] = 514 MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COMP); 515 map[MSINUM_REG_INDEX(N_INTR_RXQ0_DESC_EMPTY)] = 516 MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_DESC_EMPTY); 517 map[MSINUM_REG_INDEX(N_INTR_RXQ1_DESC_EMPTY)] = 518 MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_DESC_EMPTY); 519 map[MSINUM_REG_INDEX(N_INTR_RXQ2_DESC_EMPTY)] = 520 MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_DESC_EMPTY); 521 map[MSINUM_REG_INDEX(N_INTR_RXQ3_DESC_EMPTY)] = 522 MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_DESC_EMPTY); 523 map[MSINUM_REG_INDEX(N_INTR_RXQ0_COAL)] = 524 MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COAL); 525 map[MSINUM_REG_INDEX(N_INTR_RXQ1_COAL)] = 526 MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COAL); 527 map[MSINUM_REG_INDEX(N_INTR_RXQ2_COAL)] = 528 MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COAL); 529 map[MSINUM_REG_INDEX(N_INTR_RXQ3_COAL)] = 530 MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COAL); 531 map[MSINUM_REG_INDEX(N_INTR_RXQ0_COAL_TO)] = 532 MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COAL_TO); 533 map[MSINUM_REG_INDEX(N_INTR_RXQ1_COAL_TO)] = 534 MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COAL_TO); 535 map[MSINUM_REG_INDEX(N_INTR_RXQ2_COAL_TO)] = 536 MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COAL_TO); 537 map[MSINUM_REG_INDEX(N_INTR_RXQ3_COAL_TO)] = 538 MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COAL_TO); 539 540 /* Map all other interrupts source to MSI/MSIX vector 0. */ 541 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 0, map[0]); 542 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 1, map[1]); 543 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 2, map[2]); 544 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 3, map[3]); 545} 546 547static int 548jme_attach(device_t dev) 549{ 550 struct jme_softc *sc; 551 struct ifnet *ifp; 552 struct mii_softc *miisc; 553 struct mii_data *mii; 554 uint32_t reg; 555 uint16_t burst; 556 int error, i, msic, msixc, pmc; 557 558 error = 0; 559 sc = device_get_softc(dev); 560 sc->jme_dev = dev; 561 562 mtx_init(&sc->jme_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 563 MTX_DEF); 564 callout_init_mtx(&sc->jme_tick_ch, &sc->jme_mtx, 0); 565 TASK_INIT(&sc->jme_int_task, 0, jme_int_task, sc); 566 TASK_INIT(&sc->jme_link_task, 0, jme_link_task, sc); 567 568 /* 569 * Map the device. JMC250 supports both memory mapped and I/O 570 * register space access. Because I/O register access should 571 * use different BARs to access registers it's waste of time 572 * to use I/O register spce access. JMC250 uses 16K to map 573 * entire memory space. 574 */ 575 pci_enable_busmaster(dev); 576 sc->jme_res_spec = jme_res_spec_mem; 577 sc->jme_irq_spec = jme_irq_spec_legacy; 578 error = bus_alloc_resources(dev, sc->jme_res_spec, sc->jme_res); 579 if (error != 0) { 580 device_printf(dev, "cannot allocate memory resources.\n"); 581 goto fail; 582 } 583 584 /* Allocate IRQ resources. */ 585 msixc = pci_msix_count(dev); 586 msic = pci_msi_count(dev); 587 if (bootverbose) { 588 device_printf(dev, "MSIX count : %d\n", msixc); 589 device_printf(dev, "MSI count : %d\n", msic); 590 } 591 592 /* Prefer MSIX over MSI. */ 593 if (msix_disable == 0 || msi_disable == 0) { 594 if (msix_disable == 0 && msixc == JME_MSIX_MESSAGES && 595 pci_alloc_msix(dev, &msixc) == 0) { 596 if (msic == JME_MSIX_MESSAGES) { 597 device_printf(dev, "Using %d MSIX messages.\n", 598 msixc); 599 sc->jme_flags |= JME_FLAG_MSIX; 600 sc->jme_irq_spec = jme_irq_spec_msi; 601 } else 602 pci_release_msi(dev); 603 } 604 if (msi_disable == 0 && (sc->jme_flags & JME_FLAG_MSIX) == 0 && 605 msic == JME_MSI_MESSAGES && 606 pci_alloc_msi(dev, &msic) == 0) { 607 if (msic == JME_MSI_MESSAGES) { 608 device_printf(dev, "Using %d MSI messages.\n", 609 msic); 610 sc->jme_flags |= JME_FLAG_MSI; 611 sc->jme_irq_spec = jme_irq_spec_msi; 612 } else 613 pci_release_msi(dev); 614 } 615 /* Map interrupt vector 0, 1 and 2. */ 616 if ((sc->jme_flags & JME_FLAG_MSI) != 0 || 617 (sc->jme_flags & JME_FLAG_MSIX) != 0) 618 jme_map_intr_vector(sc); 619 } 620 621 error = bus_alloc_resources(dev, sc->jme_irq_spec, sc->jme_irq); 622 if (error != 0) { 623 device_printf(dev, "cannot allocate IRQ resources.\n"); 624 goto fail; 625 } 626 627 sc->jme_rev = pci_get_device(dev); 628 if ((sc->jme_rev & DEVICEID_JMC2XX_MASK) == DEVICEID_JMC260) { 629 sc->jme_flags |= JME_FLAG_FASTETH; 630 sc->jme_flags |= JME_FLAG_NOJUMBO; 631 } 632 reg = CSR_READ_4(sc, JME_CHIPMODE); 633 sc->jme_chip_rev = (reg & CHIPMODE_REV_MASK) >> CHIPMODE_REV_SHIFT; 634 if (((reg & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) != 635 CHIPMODE_NOT_FPGA) 636 sc->jme_flags |= JME_FLAG_FPGA; 637 if (bootverbose) { 638 device_printf(dev, "PCI device revision : 0x%04x\n", 639 sc->jme_rev); 640 device_printf(dev, "Chip revision : 0x%02x\n", 641 sc->jme_chip_rev); 642 if ((sc->jme_flags & JME_FLAG_FPGA) != 0) 643 device_printf(dev, "FPGA revision : 0x%04x\n", 644 (reg & CHIPMODE_FPGA_REV_MASK) >> 645 CHIPMODE_FPGA_REV_SHIFT); 646 } 647 if (sc->jme_chip_rev == 0xFF) { 648 device_printf(dev, "Unknown chip revision : 0x%02x\n", 649 sc->jme_rev); 650 error = ENXIO; 651 goto fail; 652 } 653 654 if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 2) { 655 if ((sc->jme_rev & DEVICEID_JMC2XX_MASK) == DEVICEID_JMC260 && 656 CHIPMODE_REVFM(sc->jme_chip_rev) == 2) 657 sc->jme_flags |= JME_FLAG_DMA32BIT; 658 sc->jme_flags |= JME_FLAG_TXCLK; 659 } 660 661 /* Reset the ethernet controller. */ 662 jme_reset(sc); 663 664 /* Get station address. */ 665 reg = CSR_READ_4(sc, JME_SMBCSR); 666 if ((reg & SMBCSR_EEPROM_PRESENT) != 0) 667 error = jme_eeprom_macaddr(sc); 668 if (error != 0 || (reg & SMBCSR_EEPROM_PRESENT) == 0) { 669 if (error != 0 && (bootverbose)) 670 device_printf(sc->jme_dev, 671 "ethernet hardware address not found in EEPROM.\n"); 672 jme_reg_macaddr(sc); 673 } 674 675 /* 676 * Save PHY address. 677 * Integrated JR0211 has fixed PHY address whereas FPGA version 678 * requires PHY probing to get correct PHY address. 679 */ 680 if ((sc->jme_flags & JME_FLAG_FPGA) == 0) { 681 sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) & 682 GPREG0_PHY_ADDR_MASK; 683 if (bootverbose) 684 device_printf(dev, "PHY is at address %d.\n", 685 sc->jme_phyaddr); 686 } else 687 sc->jme_phyaddr = 0; 688 689 /* Set max allowable DMA size. */ 690 if (pci_find_extcap(dev, PCIY_EXPRESS, &i) == 0) { 691 sc->jme_flags |= JME_FLAG_PCIE; 692 burst = pci_read_config(dev, i + 0x08, 2); 693 if (bootverbose) { 694 device_printf(dev, "Read request size : %d bytes.\n", 695 128 << ((burst >> 12) & 0x07)); 696 device_printf(dev, "TLP payload size : %d bytes.\n", 697 128 << ((burst >> 5) & 0x07)); 698 } 699 switch ((burst >> 12) & 0x07) { 700 case 0: 701 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_128; 702 break; 703 case 1: 704 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_256; 705 break; 706 default: 707 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512; 708 break; 709 } 710 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128; 711 } else { 712 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512; 713 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128; 714 } 715 /* Create coalescing sysctl node. */ 716 jme_sysctl_node(sc); 717 if ((error = jme_dma_alloc(sc) != 0)) 718 goto fail; 719 720 ifp = sc->jme_ifp = if_alloc(IFT_ETHER); 721 if (ifp == NULL) { 722 device_printf(dev, "cannot allocate ifnet structure.\n"); 723 error = ENXIO; 724 goto fail; 725 } 726 727 ifp->if_softc = sc; 728 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 729 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 730 ifp->if_ioctl = jme_ioctl; 731 ifp->if_start = jme_start; 732 ifp->if_init = jme_init; 733 ifp->if_snd.ifq_drv_maxlen = JME_TX_RING_CNT - 1; 734 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 735 IFQ_SET_READY(&ifp->if_snd); 736 /* JMC250 supports Tx/Rx checksum offload as well as TSO. */ 737 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4; 738 ifp->if_hwassist = JME_CSUM_FEATURES | CSUM_TSO; 739 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) { 740 sc->jme_flags |= JME_FLAG_PMCAP; 741 ifp->if_capabilities |= IFCAP_WOL_MAGIC; 742 } 743 ifp->if_capenable = ifp->if_capabilities; 744 745 /* Set up MII bus. */ 746 if ((error = mii_phy_probe(dev, &sc->jme_miibus, jme_mediachange, 747 jme_mediastatus)) != 0) { 748 device_printf(dev, "no PHY found!\n"); 749 goto fail; 750 } 751 752 /* 753 * Force PHY to FPGA mode. 754 */ 755 if ((sc->jme_flags & JME_FLAG_FPGA) != 0) { 756 mii = device_get_softc(sc->jme_miibus); 757 if (mii->mii_instance != 0) { 758 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) { 759 if (miisc->mii_phy != 0) { 760 sc->jme_phyaddr = miisc->mii_phy; 761 break; 762 } 763 } 764 if (sc->jme_phyaddr != 0) { 765 device_printf(sc->jme_dev, 766 "FPGA PHY is at %d\n", sc->jme_phyaddr); 767 /* vendor magic. */ 768 jme_miibus_writereg(dev, sc->jme_phyaddr, 27, 769 0x0004); 770 } 771 } 772 } 773 774 ether_ifattach(ifp, sc->jme_eaddr); 775 776 /* VLAN capability setup */ 777 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 778 IFCAP_VLAN_HWCSUM; 779 ifp->if_capenable = ifp->if_capabilities; 780 781 /* Tell the upper layer(s) we support long frames. */ 782 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 783 784 /* Create local taskq. */ 785 TASK_INIT(&sc->jme_tx_task, 1, jme_tx_task, ifp); 786 sc->jme_tq = taskqueue_create_fast("jme_taskq", M_WAITOK, 787 taskqueue_thread_enqueue, &sc->jme_tq); 788 if (sc->jme_tq == NULL) { 789 device_printf(dev, "could not create taskqueue.\n"); 790 ether_ifdetach(ifp); 791 error = ENXIO; 792 goto fail; 793 } 794 taskqueue_start_threads(&sc->jme_tq, 1, PI_NET, "%s taskq", 795 device_get_nameunit(sc->jme_dev)); 796 797 if ((sc->jme_flags & JME_FLAG_MSIX) != 0) 798 msic = JME_MSIX_MESSAGES; 799 else if ((sc->jme_flags & JME_FLAG_MSI) != 0) 800 msic = JME_MSI_MESSAGES; 801 else 802 msic = 1; 803 for (i = 0; i < msic; i++) { 804 error = bus_setup_intr(dev, sc->jme_irq[i], 805 INTR_TYPE_NET | INTR_MPSAFE, jme_intr, NULL, sc, 806 &sc->jme_intrhand[i]); 807 if (error != 0) 808 break; 809 } 810 811 if (error != 0) { 812 device_printf(dev, "could not set up interrupt handler.\n"); 813 taskqueue_free(sc->jme_tq); 814 sc->jme_tq = NULL; 815 ether_ifdetach(ifp); 816 goto fail; 817 } 818 819fail: 820 if (error != 0) 821 jme_detach(dev); 822 823 return (error); 824} 825 826static int 827jme_detach(device_t dev) 828{ 829 struct jme_softc *sc; 830 struct ifnet *ifp; 831 int i, msic; 832 833 sc = device_get_softc(dev); 834 835 ifp = sc->jme_ifp; 836 if (device_is_attached(dev)) { 837 JME_LOCK(sc); 838 sc->jme_flags |= JME_FLAG_DETACH; 839 jme_stop(sc); 840 JME_UNLOCK(sc); 841 callout_drain(&sc->jme_tick_ch); 842 taskqueue_drain(sc->jme_tq, &sc->jme_int_task); 843 taskqueue_drain(sc->jme_tq, &sc->jme_tx_task); 844 taskqueue_drain(taskqueue_swi, &sc->jme_link_task); 845 ether_ifdetach(ifp); 846 } 847 848 if (sc->jme_tq != NULL) { 849 taskqueue_drain(sc->jme_tq, &sc->jme_int_task); 850 taskqueue_free(sc->jme_tq); 851 sc->jme_tq = NULL; 852 } 853 854 if (sc->jme_miibus != NULL) { 855 device_delete_child(dev, sc->jme_miibus); 856 sc->jme_miibus = NULL; 857 } 858 bus_generic_detach(dev); 859 jme_dma_free(sc); 860 861 if (ifp != NULL) { 862 if_free(ifp); 863 sc->jme_ifp = NULL; 864 } 865 866 msic = 1; 867 if ((sc->jme_flags & JME_FLAG_MSIX) != 0) 868 msic = JME_MSIX_MESSAGES; 869 else if ((sc->jme_flags & JME_FLAG_MSI) != 0) 870 msic = JME_MSI_MESSAGES; 871 else 872 msic = 1; 873 for (i = 0; i < msic; i++) { 874 if (sc->jme_intrhand[i] != NULL) { 875 bus_teardown_intr(dev, sc->jme_irq[i], 876 sc->jme_intrhand[i]); 877 sc->jme_intrhand[i] = NULL; 878 } 879 } 880 881 bus_release_resources(dev, sc->jme_irq_spec, sc->jme_irq); 882 if ((sc->jme_flags & (JME_FLAG_MSIX | JME_FLAG_MSI)) != 0) 883 pci_release_msi(dev); 884 bus_release_resources(dev, sc->jme_res_spec, sc->jme_res); 885 mtx_destroy(&sc->jme_mtx); 886 887 return (0); 888} 889 890static void 891jme_sysctl_node(struct jme_softc *sc) 892{ 893 int error; 894 895 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->jme_dev), 896 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->jme_dev)), OID_AUTO, 897 "tx_coal_to", CTLTYPE_INT | CTLFLAG_RW, &sc->jme_tx_coal_to, 898 0, sysctl_hw_jme_tx_coal_to, "I", "jme tx coalescing timeout"); 899 900 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->jme_dev), 901 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->jme_dev)), OID_AUTO, 902 "tx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW, &sc->jme_tx_coal_pkt, 903 0, sysctl_hw_jme_tx_coal_pkt, "I", "jme tx coalescing packet"); 904 905 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->jme_dev), 906 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->jme_dev)), OID_AUTO, 907 "rx_coal_to", CTLTYPE_INT | CTLFLAG_RW, &sc->jme_rx_coal_to, 908 0, sysctl_hw_jme_rx_coal_to, "I", "jme rx coalescing timeout"); 909 910 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->jme_dev), 911 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->jme_dev)), OID_AUTO, 912 "rx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW, &sc->jme_rx_coal_pkt, 913 0, sysctl_hw_jme_rx_coal_pkt, "I", "jme rx coalescing packet"); 914 915 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->jme_dev), 916 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->jme_dev)), OID_AUTO, 917 "process_limit", CTLTYPE_INT | CTLFLAG_RW, &sc->jme_process_limit, 918 0, sysctl_hw_jme_proc_limit, "I", 919 "max number of Rx events to process"); 920 921 /* Pull in device tunables. */ 922 sc->jme_process_limit = JME_PROC_DEFAULT; 923 error = resource_int_value(device_get_name(sc->jme_dev), 924 device_get_unit(sc->jme_dev), "process_limit", 925 &sc->jme_process_limit); 926 if (error == 0) { 927 if (sc->jme_process_limit < JME_PROC_MIN || 928 sc->jme_process_limit > JME_PROC_MAX) { 929 device_printf(sc->jme_dev, 930 "process_limit value out of range; " 931 "using default: %d\n", JME_PROC_DEFAULT); 932 sc->jme_process_limit = JME_PROC_DEFAULT; 933 } 934 } 935 936 sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT; 937 error = resource_int_value(device_get_name(sc->jme_dev), 938 device_get_unit(sc->jme_dev), "tx_coal_to", &sc->jme_tx_coal_to); 939 if (error == 0) { 940 if (sc->jme_tx_coal_to < PCCTX_COAL_TO_MIN || 941 sc->jme_tx_coal_to > PCCTX_COAL_TO_MAX) { 942 device_printf(sc->jme_dev, 943 "tx_coal_to value out of range; " 944 "using default: %d\n", PCCTX_COAL_TO_DEFAULT); 945 sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT; 946 } 947 } 948 949 sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT; 950 error = resource_int_value(device_get_name(sc->jme_dev), 951 device_get_unit(sc->jme_dev), "tx_coal_pkt", &sc->jme_tx_coal_to); 952 if (error == 0) { 953 if (sc->jme_tx_coal_pkt < PCCTX_COAL_PKT_MIN || 954 sc->jme_tx_coal_pkt > PCCTX_COAL_PKT_MAX) { 955 device_printf(sc->jme_dev, 956 "tx_coal_pkt value out of range; " 957 "using default: %d\n", PCCTX_COAL_PKT_DEFAULT); 958 sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT; 959 } 960 } 961 962 sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT; 963 error = resource_int_value(device_get_name(sc->jme_dev), 964 device_get_unit(sc->jme_dev), "rx_coal_to", &sc->jme_rx_coal_to); 965 if (error == 0) { 966 if (sc->jme_rx_coal_to < PCCRX_COAL_TO_MIN || 967 sc->jme_rx_coal_to > PCCRX_COAL_TO_MAX) { 968 device_printf(sc->jme_dev, 969 "rx_coal_to value out of range; " 970 "using default: %d\n", PCCRX_COAL_TO_DEFAULT); 971 sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT; 972 } 973 } 974 975 sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT; 976 error = resource_int_value(device_get_name(sc->jme_dev), 977 device_get_unit(sc->jme_dev), "rx_coal_pkt", &sc->jme_rx_coal_to); 978 if (error == 0) { 979 if (sc->jme_rx_coal_pkt < PCCRX_COAL_PKT_MIN || 980 sc->jme_rx_coal_pkt > PCCRX_COAL_PKT_MAX) { 981 device_printf(sc->jme_dev, 982 "tx_coal_pkt value out of range; " 983 "using default: %d\n", PCCRX_COAL_PKT_DEFAULT); 984 sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT; 985 } 986 } 987} 988 989struct jme_dmamap_arg { 990 bus_addr_t jme_busaddr; 991}; 992 993static void 994jme_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 995{ 996 struct jme_dmamap_arg *ctx; 997 998 if (error != 0) 999 return; 1000 1001 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1002 1003 ctx = (struct jme_dmamap_arg *)arg; 1004 ctx->jme_busaddr = segs[0].ds_addr; 1005} 1006 1007static int 1008jme_dma_alloc(struct jme_softc *sc) 1009{ 1010 struct jme_dmamap_arg ctx; 1011 struct jme_txdesc *txd; 1012 struct jme_rxdesc *rxd; 1013 bus_addr_t lowaddr, rx_ring_end, tx_ring_end; 1014 int error, i; 1015 1016 lowaddr = BUS_SPACE_MAXADDR; 1017 if ((sc->jme_flags & JME_FLAG_DMA32BIT) != 0) 1018 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1019 1020again: 1021 /* Create parent ring tag. */ 1022 error = bus_dma_tag_create(bus_get_dma_tag(sc->jme_dev),/* parent */ 1023 1, 0, /* algnmnt, boundary */ 1024 lowaddr, /* lowaddr */ 1025 BUS_SPACE_MAXADDR, /* highaddr */ 1026 NULL, NULL, /* filter, filterarg */ 1027 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1028 0, /* nsegments */ 1029 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1030 0, /* flags */ 1031 NULL, NULL, /* lockfunc, lockarg */ 1032 &sc->jme_cdata.jme_ring_tag); 1033 if (error != 0) { 1034 device_printf(sc->jme_dev, 1035 "could not create parent ring DMA tag.\n"); 1036 goto fail; 1037 } 1038 /* Create tag for Tx ring. */ 1039 error = bus_dma_tag_create(sc->jme_cdata.jme_ring_tag,/* parent */ 1040 JME_TX_RING_ALIGN, 0, /* algnmnt, boundary */ 1041 BUS_SPACE_MAXADDR, /* lowaddr */ 1042 BUS_SPACE_MAXADDR, /* highaddr */ 1043 NULL, NULL, /* filter, filterarg */ 1044 JME_TX_RING_SIZE, /* maxsize */ 1045 1, /* nsegments */ 1046 JME_TX_RING_SIZE, /* maxsegsize */ 1047 0, /* flags */ 1048 NULL, NULL, /* lockfunc, lockarg */ 1049 &sc->jme_cdata.jme_tx_ring_tag); 1050 if (error != 0) { 1051 device_printf(sc->jme_dev, 1052 "could not allocate Tx ring DMA tag.\n"); 1053 goto fail; 1054 } 1055 1056 /* Create tag for Rx ring. */ 1057 error = bus_dma_tag_create(sc->jme_cdata.jme_ring_tag,/* parent */ 1058 JME_RX_RING_ALIGN, 0, /* algnmnt, boundary */ 1059 lowaddr, /* lowaddr */ 1060 BUS_SPACE_MAXADDR, /* highaddr */ 1061 NULL, NULL, /* filter, filterarg */ 1062 JME_RX_RING_SIZE, /* maxsize */ 1063 1, /* nsegments */ 1064 JME_RX_RING_SIZE, /* maxsegsize */ 1065 0, /* flags */ 1066 NULL, NULL, /* lockfunc, lockarg */ 1067 &sc->jme_cdata.jme_rx_ring_tag); 1068 if (error != 0) { 1069 device_printf(sc->jme_dev, 1070 "could not allocate Rx ring DMA tag.\n"); 1071 goto fail; 1072 } 1073 1074 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1075 error = bus_dmamem_alloc(sc->jme_cdata.jme_tx_ring_tag, 1076 (void **)&sc->jme_rdata.jme_tx_ring, 1077 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1078 &sc->jme_cdata.jme_tx_ring_map); 1079 if (error != 0) { 1080 device_printf(sc->jme_dev, 1081 "could not allocate DMA'able memory for Tx ring.\n"); 1082 goto fail; 1083 } 1084 1085 ctx.jme_busaddr = 0; 1086 error = bus_dmamap_load(sc->jme_cdata.jme_tx_ring_tag, 1087 sc->jme_cdata.jme_tx_ring_map, sc->jme_rdata.jme_tx_ring, 1088 JME_TX_RING_SIZE, jme_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 1089 if (error != 0 || ctx.jme_busaddr == 0) { 1090 device_printf(sc->jme_dev, 1091 "could not load DMA'able memory for Tx ring.\n"); 1092 goto fail; 1093 } 1094 sc->jme_rdata.jme_tx_ring_paddr = ctx.jme_busaddr; 1095 1096 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 1097 error = bus_dmamem_alloc(sc->jme_cdata.jme_rx_ring_tag, 1098 (void **)&sc->jme_rdata.jme_rx_ring, 1099 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1100 &sc->jme_cdata.jme_rx_ring_map); 1101 if (error != 0) { 1102 device_printf(sc->jme_dev, 1103 "could not allocate DMA'able memory for Rx ring.\n"); 1104 goto fail; 1105 } 1106 1107 ctx.jme_busaddr = 0; 1108 error = bus_dmamap_load(sc->jme_cdata.jme_rx_ring_tag, 1109 sc->jme_cdata.jme_rx_ring_map, sc->jme_rdata.jme_rx_ring, 1110 JME_RX_RING_SIZE, jme_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 1111 if (error != 0 || ctx.jme_busaddr == 0) { 1112 device_printf(sc->jme_dev, 1113 "could not load DMA'able memory for Rx ring.\n"); 1114 goto fail; 1115 } 1116 sc->jme_rdata.jme_rx_ring_paddr = ctx.jme_busaddr; 1117 1118 if (lowaddr != BUS_SPACE_MAXADDR_32BIT) { 1119 /* Tx/Rx descriptor queue should reside within 4GB boundary. */ 1120 tx_ring_end = sc->jme_rdata.jme_tx_ring_paddr + 1121 JME_TX_RING_SIZE; 1122 rx_ring_end = sc->jme_rdata.jme_rx_ring_paddr + 1123 JME_RX_RING_SIZE; 1124 if ((JME_ADDR_HI(tx_ring_end) != 1125 JME_ADDR_HI(sc->jme_rdata.jme_tx_ring_paddr)) || 1126 (JME_ADDR_HI(rx_ring_end) != 1127 JME_ADDR_HI(sc->jme_rdata.jme_rx_ring_paddr))) { 1128 device_printf(sc->jme_dev, "4GB boundary crossed, " 1129 "switching to 32bit DMA address mode.\n"); 1130 jme_dma_free(sc); 1131 /* Limit DMA address space to 32bit and try again. */ 1132 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1133 goto again; 1134 } 1135 } 1136 1137 lowaddr = BUS_SPACE_MAXADDR; 1138 if ((sc->jme_flags & JME_FLAG_DMA32BIT) != 0) 1139 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1140 /* Create parent buffer tag. */ 1141 error = bus_dma_tag_create(bus_get_dma_tag(sc->jme_dev),/* parent */ 1142 1, 0, /* algnmnt, boundary */ 1143 lowaddr, /* lowaddr */ 1144 BUS_SPACE_MAXADDR, /* highaddr */ 1145 NULL, NULL, /* filter, filterarg */ 1146 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1147 0, /* nsegments */ 1148 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1149 0, /* flags */ 1150 NULL, NULL, /* lockfunc, lockarg */ 1151 &sc->jme_cdata.jme_buffer_tag); 1152 if (error != 0) { 1153 device_printf(sc->jme_dev, 1154 "could not create parent buffer DMA tag.\n"); 1155 goto fail; 1156 } 1157 1158 /* Create shadow status block tag. */ 1159 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */ 1160 JME_SSB_ALIGN, 0, /* algnmnt, boundary */ 1161 BUS_SPACE_MAXADDR, /* lowaddr */ 1162 BUS_SPACE_MAXADDR, /* highaddr */ 1163 NULL, NULL, /* filter, filterarg */ 1164 JME_SSB_SIZE, /* maxsize */ 1165 1, /* nsegments */ 1166 JME_SSB_SIZE, /* maxsegsize */ 1167 0, /* flags */ 1168 NULL, NULL, /* lockfunc, lockarg */ 1169 &sc->jme_cdata.jme_ssb_tag); 1170 if (error != 0) { 1171 device_printf(sc->jme_dev, 1172 "could not create shared status block DMA tag.\n"); 1173 goto fail; 1174 } 1175 1176 /* Create tag for Tx buffers. */ 1177 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */ 1178 1, 0, /* algnmnt, boundary */ 1179 BUS_SPACE_MAXADDR, /* lowaddr */ 1180 BUS_SPACE_MAXADDR, /* highaddr */ 1181 NULL, NULL, /* filter, filterarg */ 1182 JME_TSO_MAXSIZE, /* maxsize */ 1183 JME_MAXTXSEGS, /* nsegments */ 1184 JME_TSO_MAXSEGSIZE, /* maxsegsize */ 1185 0, /* flags */ 1186 NULL, NULL, /* lockfunc, lockarg */ 1187 &sc->jme_cdata.jme_tx_tag); 1188 if (error != 0) { 1189 device_printf(sc->jme_dev, "could not create Tx DMA tag.\n"); 1190 goto fail; 1191 } 1192 1193 /* Create tag for Rx buffers. */ 1194 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */ 1195 JME_RX_BUF_ALIGN, 0, /* algnmnt, boundary */ 1196 BUS_SPACE_MAXADDR, /* lowaddr */ 1197 BUS_SPACE_MAXADDR, /* highaddr */ 1198 NULL, NULL, /* filter, filterarg */ 1199 MCLBYTES, /* maxsize */ 1200 1, /* nsegments */ 1201 MCLBYTES, /* maxsegsize */ 1202 0, /* flags */ 1203 NULL, NULL, /* lockfunc, lockarg */ 1204 &sc->jme_cdata.jme_rx_tag); 1205 if (error != 0) { 1206 device_printf(sc->jme_dev, "could not create Rx DMA tag.\n"); 1207 goto fail; 1208 } 1209 1210 /* 1211 * Allocate DMA'able memory and load the DMA map for shared 1212 * status block. 1213 */ 1214 error = bus_dmamem_alloc(sc->jme_cdata.jme_ssb_tag, 1215 (void **)&sc->jme_rdata.jme_ssb_block, 1216 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1217 &sc->jme_cdata.jme_ssb_map); 1218 if (error != 0) { 1219 device_printf(sc->jme_dev, "could not allocate DMA'able " 1220 "memory for shared status block.\n"); 1221 goto fail; 1222 } 1223 1224 ctx.jme_busaddr = 0; 1225 error = bus_dmamap_load(sc->jme_cdata.jme_ssb_tag, 1226 sc->jme_cdata.jme_ssb_map, sc->jme_rdata.jme_ssb_block, 1227 JME_SSB_SIZE, jme_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 1228 if (error != 0 || ctx.jme_busaddr == 0) { 1229 device_printf(sc->jme_dev, "could not load DMA'able memory " 1230 "for shared status block.\n"); 1231 goto fail; 1232 } 1233 sc->jme_rdata.jme_ssb_block_paddr = ctx.jme_busaddr; 1234 1235 /* Create DMA maps for Tx buffers. */ 1236 for (i = 0; i < JME_TX_RING_CNT; i++) { 1237 txd = &sc->jme_cdata.jme_txdesc[i]; 1238 txd->tx_m = NULL; 1239 txd->tx_dmamap = NULL; 1240 error = bus_dmamap_create(sc->jme_cdata.jme_tx_tag, 0, 1241 &txd->tx_dmamap); 1242 if (error != 0) { 1243 device_printf(sc->jme_dev, 1244 "could not create Tx dmamap.\n"); 1245 goto fail; 1246 } 1247 } 1248 /* Create DMA maps for Rx buffers. */ 1249 if ((error = bus_dmamap_create(sc->jme_cdata.jme_rx_tag, 0, 1250 &sc->jme_cdata.jme_rx_sparemap)) != 0) { 1251 device_printf(sc->jme_dev, 1252 "could not create spare Rx dmamap.\n"); 1253 goto fail; 1254 } 1255 for (i = 0; i < JME_RX_RING_CNT; i++) { 1256 rxd = &sc->jme_cdata.jme_rxdesc[i]; 1257 rxd->rx_m = NULL; 1258 rxd->rx_dmamap = NULL; 1259 error = bus_dmamap_create(sc->jme_cdata.jme_rx_tag, 0, 1260 &rxd->rx_dmamap); 1261 if (error != 0) { 1262 device_printf(sc->jme_dev, 1263 "could not create Rx dmamap.\n"); 1264 goto fail; 1265 } 1266 } 1267 1268fail: 1269 return (error); 1270} 1271 1272static void 1273jme_dma_free(struct jme_softc *sc) 1274{ 1275 struct jme_txdesc *txd; 1276 struct jme_rxdesc *rxd; 1277 int i; 1278 1279 /* Tx ring */ 1280 if (sc->jme_cdata.jme_tx_ring_tag != NULL) { 1281 if (sc->jme_cdata.jme_tx_ring_map) 1282 bus_dmamap_unload(sc->jme_cdata.jme_tx_ring_tag, 1283 sc->jme_cdata.jme_tx_ring_map); 1284 if (sc->jme_cdata.jme_tx_ring_map && 1285 sc->jme_rdata.jme_tx_ring) 1286 bus_dmamem_free(sc->jme_cdata.jme_tx_ring_tag, 1287 sc->jme_rdata.jme_tx_ring, 1288 sc->jme_cdata.jme_tx_ring_map); 1289 sc->jme_rdata.jme_tx_ring = NULL; 1290 sc->jme_cdata.jme_tx_ring_map = NULL; 1291 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_ring_tag); 1292 sc->jme_cdata.jme_tx_ring_tag = NULL; 1293 } 1294 /* Rx ring */ 1295 if (sc->jme_cdata.jme_rx_ring_tag != NULL) { 1296 if (sc->jme_cdata.jme_rx_ring_map) 1297 bus_dmamap_unload(sc->jme_cdata.jme_rx_ring_tag, 1298 sc->jme_cdata.jme_rx_ring_map); 1299 if (sc->jme_cdata.jme_rx_ring_map && 1300 sc->jme_rdata.jme_rx_ring) 1301 bus_dmamem_free(sc->jme_cdata.jme_rx_ring_tag, 1302 sc->jme_rdata.jme_rx_ring, 1303 sc->jme_cdata.jme_rx_ring_map); 1304 sc->jme_rdata.jme_rx_ring = NULL; 1305 sc->jme_cdata.jme_rx_ring_map = NULL; 1306 bus_dma_tag_destroy(sc->jme_cdata.jme_rx_ring_tag); 1307 sc->jme_cdata.jme_rx_ring_tag = NULL; 1308 } 1309 /* Tx buffers */ 1310 if (sc->jme_cdata.jme_tx_tag != NULL) { 1311 for (i = 0; i < JME_TX_RING_CNT; i++) { 1312 txd = &sc->jme_cdata.jme_txdesc[i]; 1313 if (txd->tx_dmamap != NULL) { 1314 bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag, 1315 txd->tx_dmamap); 1316 txd->tx_dmamap = NULL; 1317 } 1318 } 1319 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag); 1320 sc->jme_cdata.jme_tx_tag = NULL; 1321 } 1322 /* Rx buffers */ 1323 if (sc->jme_cdata.jme_rx_tag != NULL) { 1324 for (i = 0; i < JME_RX_RING_CNT; i++) { 1325 rxd = &sc->jme_cdata.jme_rxdesc[i]; 1326 if (rxd->rx_dmamap != NULL) { 1327 bus_dmamap_destroy(sc->jme_cdata.jme_rx_tag, 1328 rxd->rx_dmamap); 1329 rxd->rx_dmamap = NULL; 1330 } 1331 } 1332 if (sc->jme_cdata.jme_rx_sparemap != NULL) { 1333 bus_dmamap_destroy(sc->jme_cdata.jme_rx_tag, 1334 sc->jme_cdata.jme_rx_sparemap); 1335 sc->jme_cdata.jme_rx_sparemap = NULL; 1336 } 1337 bus_dma_tag_destroy(sc->jme_cdata.jme_rx_tag); 1338 sc->jme_cdata.jme_rx_tag = NULL; 1339 } 1340 1341 /* Shared status block. */ 1342 if (sc->jme_cdata.jme_ssb_tag != NULL) { 1343 if (sc->jme_cdata.jme_ssb_map) 1344 bus_dmamap_unload(sc->jme_cdata.jme_ssb_tag, 1345 sc->jme_cdata.jme_ssb_map); 1346 if (sc->jme_cdata.jme_ssb_map && sc->jme_rdata.jme_ssb_block) 1347 bus_dmamem_free(sc->jme_cdata.jme_ssb_tag, 1348 sc->jme_rdata.jme_ssb_block, 1349 sc->jme_cdata.jme_ssb_map); 1350 sc->jme_rdata.jme_ssb_block = NULL; 1351 sc->jme_cdata.jme_ssb_map = NULL; 1352 bus_dma_tag_destroy(sc->jme_cdata.jme_ssb_tag); 1353 sc->jme_cdata.jme_ssb_tag = NULL; 1354 } 1355 1356 if (sc->jme_cdata.jme_buffer_tag != NULL) { 1357 bus_dma_tag_destroy(sc->jme_cdata.jme_buffer_tag); 1358 sc->jme_cdata.jme_buffer_tag = NULL; 1359 } 1360 if (sc->jme_cdata.jme_ring_tag != NULL) { 1361 bus_dma_tag_destroy(sc->jme_cdata.jme_ring_tag); 1362 sc->jme_cdata.jme_ring_tag = NULL; 1363 } 1364} 1365 1366/* 1367 * Make sure the interface is stopped at reboot time. 1368 */ 1369static int 1370jme_shutdown(device_t dev) 1371{ 1372 1373 return (jme_suspend(dev)); 1374} 1375 1376/* 1377 * Unlike other ethernet controllers, JMC250 requires 1378 * explicit resetting link speed to 10/100Mbps as gigabit 1379 * link will cunsume more power than 375mA. 1380 * Note, we reset the link speed to 10/100Mbps with 1381 * auto-negotiation but we don't know whether that operation 1382 * would succeed or not as we have no control after powering 1383 * off. If the renegotiation fail WOL may not work. Running 1384 * at 1Gbps draws more power than 375mA at 3.3V which is 1385 * specified in PCI specification and that would result in 1386 * complete shutdowning power to ethernet controller. 1387 * 1388 * TODO 1389 * Save current negotiated media speed/duplex/flow-control 1390 * to softc and restore the same link again after resuming. 1391 * PHY handling such as power down/resetting to 100Mbps 1392 * may be better handled in suspend method in phy driver. 1393 */ 1394static void 1395jme_setlinkspeed(struct jme_softc *sc) 1396{ 1397 struct mii_data *mii; 1398 int aneg, i; 1399 1400 JME_LOCK_ASSERT(sc); 1401 1402 mii = device_get_softc(sc->jme_miibus); 1403 mii_pollstat(mii); 1404 aneg = 0; 1405 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1406 switch IFM_SUBTYPE(mii->mii_media_active) { 1407 case IFM_10_T: 1408 case IFM_100_TX: 1409 return; 1410 case IFM_1000_T: 1411 aneg++; 1412 default: 1413 break; 1414 } 1415 } 1416 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_100T2CR, 0); 1417 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_ANAR, 1418 ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 1419 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR, 1420 BMCR_AUTOEN | BMCR_STARTNEG); 1421 DELAY(1000); 1422 if (aneg != 0) { 1423 /* Poll link state until jme(4) get a 10/100 link. */ 1424 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1425 mii_pollstat(mii); 1426 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1427 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1428 case IFM_10_T: 1429 case IFM_100_TX: 1430 jme_mac_config(sc); 1431 return; 1432 default: 1433 break; 1434 } 1435 } 1436 JME_UNLOCK(sc); 1437 pause("jmelnk", hz); 1438 JME_LOCK(sc); 1439 } 1440 if (i == MII_ANEGTICKS_GIGE) 1441 device_printf(sc->jme_dev, "establishing link failed, " 1442 "WOL may not work!"); 1443 } 1444 /* 1445 * No link, force MAC to have 100Mbps, full-duplex link. 1446 * This is the last resort and may/may not work. 1447 */ 1448 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1449 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1450 jme_mac_config(sc); 1451} 1452 1453static void 1454jme_setwol(struct jme_softc *sc) 1455{ 1456 struct ifnet *ifp; 1457 uint32_t gpr, pmcs; 1458 uint16_t pmstat; 1459 int pmc; 1460 1461 JME_LOCK_ASSERT(sc); 1462 1463 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) { 1464 /* Remove Tx MAC/offload clock to save more power. */ 1465 if ((sc->jme_flags & JME_FLAG_TXCLK) != 0) 1466 CSR_WRITE_4(sc, JME_GHC, CSR_READ_4(sc, JME_GHC) & 1467 ~(GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100 | 1468 GHC_TX_OFFLD_CLK_1000 | GHC_TX_MAC_CLK_1000)); 1469 /* No PME capability, PHY power down. */ 1470 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, 1471 MII_BMCR, BMCR_PDOWN); 1472 return; 1473 } 1474 1475 ifp = sc->jme_ifp; 1476 gpr = CSR_READ_4(sc, JME_GPREG0) & ~GPREG0_PME_ENB; 1477 pmcs = CSR_READ_4(sc, JME_PMCS); 1478 pmcs &= ~PMCS_WOL_ENB_MASK; 1479 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) { 1480 pmcs |= PMCS_MAGIC_FRAME | PMCS_MAGIC_FRAME_ENB; 1481 /* Enable PME message. */ 1482 gpr |= GPREG0_PME_ENB; 1483 /* For gigabit controllers, reset link speed to 10/100. */ 1484 if ((sc->jme_flags & JME_FLAG_FASTETH) == 0) 1485 jme_setlinkspeed(sc); 1486 } 1487 1488 CSR_WRITE_4(sc, JME_PMCS, pmcs); 1489 CSR_WRITE_4(sc, JME_GPREG0, gpr); 1490 /* Remove Tx MAC/offload clock to save more power. */ 1491 if ((sc->jme_flags & JME_FLAG_TXCLK) != 0) 1492 CSR_WRITE_4(sc, JME_GHC, CSR_READ_4(sc, JME_GHC) & 1493 ~(GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100 | 1494 GHC_TX_OFFLD_CLK_1000 | GHC_TX_MAC_CLK_1000)); 1495 /* Request PME. */ 1496 pmstat = pci_read_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, 2); 1497 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1498 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1499 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1500 pci_write_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1501 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 1502 /* No WOL, PHY power down. */ 1503 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, 1504 MII_BMCR, BMCR_PDOWN); 1505 } 1506} 1507 1508static int 1509jme_suspend(device_t dev) 1510{ 1511 struct jme_softc *sc; 1512 1513 sc = device_get_softc(dev); 1514 1515 JME_LOCK(sc); 1516 jme_stop(sc); 1517 jme_setwol(sc); 1518 JME_UNLOCK(sc); 1519 1520 return (0); 1521} 1522 1523static int 1524jme_resume(device_t dev) 1525{ 1526 struct jme_softc *sc; 1527 struct ifnet *ifp; 1528 uint16_t pmstat; 1529 int pmc; 1530 1531 sc = device_get_softc(dev); 1532 1533 JME_LOCK(sc); 1534 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) { 1535 pmstat = pci_read_config(sc->jme_dev, 1536 pmc + PCIR_POWER_STATUS, 2); 1537 /* Disable PME clear PME status. */ 1538 pmstat &= ~PCIM_PSTAT_PMEENABLE; 1539 pci_write_config(sc->jme_dev, 1540 pmc + PCIR_POWER_STATUS, pmstat, 2); 1541 } 1542 ifp = sc->jme_ifp; 1543 if ((ifp->if_flags & IFF_UP) != 0) 1544 jme_init_locked(sc); 1545 1546 JME_UNLOCK(sc); 1547 1548 return (0); 1549} 1550 1551static int 1552jme_encap(struct jme_softc *sc, struct mbuf **m_head) 1553{ 1554 struct jme_txdesc *txd; 1555 struct jme_desc *desc; 1556 struct mbuf *m; 1557 bus_dma_segment_t txsegs[JME_MAXTXSEGS]; 1558 int error, i, nsegs, prod; 1559 uint32_t cflags, tso_segsz; 1560 1561 JME_LOCK_ASSERT(sc); 1562 1563 M_ASSERTPKTHDR((*m_head)); 1564 1565 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1566 /* 1567 * Due to the adherence to NDIS specification JMC250 1568 * assumes upper stack computed TCP pseudo checksum 1569 * without including payload length. This breaks 1570 * checksum offload for TSO case so recompute TCP 1571 * pseudo checksum for JMC250. Hopefully this wouldn't 1572 * be much burden on modern CPUs. 1573 */ 1574 struct ether_header *eh; 1575 struct ip *ip; 1576 struct tcphdr *tcp; 1577 uint32_t ip_off, poff; 1578 1579 if (M_WRITABLE(*m_head) == 0) { 1580 /* Get a writable copy. */ 1581 m = m_dup(*m_head, M_DONTWAIT); 1582 m_freem(*m_head); 1583 if (m == NULL) { 1584 *m_head = NULL; 1585 return (ENOBUFS); 1586 } 1587 *m_head = m; 1588 } 1589 ip_off = sizeof(struct ether_header); 1590 m = m_pullup(*m_head, ip_off); 1591 if (m == NULL) { 1592 *m_head = NULL; 1593 return (ENOBUFS); 1594 } 1595 eh = mtod(m, struct ether_header *); 1596 /* Check the existence of VLAN tag. */ 1597 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1598 ip_off = sizeof(struct ether_vlan_header); 1599 m = m_pullup(m, ip_off); 1600 if (m == NULL) { 1601 *m_head = NULL; 1602 return (ENOBUFS); 1603 } 1604 } 1605 m = m_pullup(m, ip_off + sizeof(struct ip)); 1606 if (m == NULL) { 1607 *m_head = NULL; 1608 return (ENOBUFS); 1609 } 1610 ip = (struct ip *)(mtod(m, char *) + ip_off); 1611 poff = ip_off + (ip->ip_hl << 2); 1612 m = m_pullup(m, poff + sizeof(struct tcphdr)); 1613 if (m == NULL) { 1614 *m_head = NULL; 1615 return (ENOBUFS); 1616 } 1617 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1618 /* 1619 * Reset IP checksum and recompute TCP pseudo 1620 * checksum that NDIS specification requires. 1621 */ 1622 ip->ip_sum = 0; 1623 if (poff + (tcp->th_off << 2) == m->m_pkthdr.len) { 1624 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1625 ip->ip_dst.s_addr, 1626 htons((tcp->th_off << 2) + IPPROTO_TCP)); 1627 /* No need to TSO, force IP checksum offload. */ 1628 (*m_head)->m_pkthdr.csum_flags &= ~CSUM_TSO; 1629 (*m_head)->m_pkthdr.csum_flags |= CSUM_IP; 1630 } else 1631 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1632 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1633 *m_head = m; 1634 } 1635 1636 prod = sc->jme_cdata.jme_tx_prod; 1637 txd = &sc->jme_cdata.jme_txdesc[prod]; 1638 1639 error = bus_dmamap_load_mbuf_sg(sc->jme_cdata.jme_tx_tag, 1640 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); 1641 if (error == EFBIG) { 1642 m = m_collapse(*m_head, M_DONTWAIT, JME_MAXTXSEGS); 1643 if (m == NULL) { 1644 m_freem(*m_head); 1645 *m_head = NULL; 1646 return (ENOMEM); 1647 } 1648 *m_head = m; 1649 error = bus_dmamap_load_mbuf_sg(sc->jme_cdata.jme_tx_tag, 1650 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); 1651 if (error != 0) { 1652 m_freem(*m_head); 1653 *m_head = NULL; 1654 return (error); 1655 } 1656 } else if (error != 0) 1657 return (error); 1658 if (nsegs == 0) { 1659 m_freem(*m_head); 1660 *m_head = NULL; 1661 return (EIO); 1662 } 1663 1664 /* 1665 * Check descriptor overrun. Leave one free descriptor. 1666 * Since we always use 64bit address mode for transmitting, 1667 * each Tx request requires one more dummy descriptor. 1668 */ 1669 if (sc->jme_cdata.jme_tx_cnt + nsegs + 1 > JME_TX_RING_CNT - 1) { 1670 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap); 1671 return (ENOBUFS); 1672 } 1673 1674 m = *m_head; 1675 cflags = 0; 1676 tso_segsz = 0; 1677 /* Configure checksum offload and TSO. */ 1678 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1679 tso_segsz = (uint32_t)m->m_pkthdr.tso_segsz << 1680 JME_TD_MSS_SHIFT; 1681 cflags |= JME_TD_TSO; 1682 } else { 1683 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 1684 cflags |= JME_TD_IPCSUM; 1685 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 1686 cflags |= JME_TD_TCPCSUM; 1687 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 1688 cflags |= JME_TD_UDPCSUM; 1689 } 1690 /* Configure VLAN. */ 1691 if ((m->m_flags & M_VLANTAG) != 0) { 1692 cflags |= (m->m_pkthdr.ether_vtag & JME_TD_VLAN_MASK); 1693 cflags |= JME_TD_VLAN_TAG; 1694 } 1695 1696 desc = &sc->jme_rdata.jme_tx_ring[prod]; 1697 desc->flags = htole32(cflags); 1698 desc->buflen = htole32(tso_segsz); 1699 desc->addr_hi = htole32(m->m_pkthdr.len); 1700 desc->addr_lo = 0; 1701 sc->jme_cdata.jme_tx_cnt++; 1702 JME_DESC_INC(prod, JME_TX_RING_CNT); 1703 for (i = 0; i < nsegs; i++) { 1704 desc = &sc->jme_rdata.jme_tx_ring[prod]; 1705 desc->flags = htole32(JME_TD_OWN | JME_TD_64BIT); 1706 desc->buflen = htole32(txsegs[i].ds_len); 1707 desc->addr_hi = htole32(JME_ADDR_HI(txsegs[i].ds_addr)); 1708 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[i].ds_addr)); 1709 sc->jme_cdata.jme_tx_cnt++; 1710 JME_DESC_INC(prod, JME_TX_RING_CNT); 1711 } 1712 1713 /* Update producer index. */ 1714 sc->jme_cdata.jme_tx_prod = prod; 1715 /* 1716 * Finally request interrupt and give the first descriptor 1717 * owenership to hardware. 1718 */ 1719 desc = txd->tx_desc; 1720 desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR); 1721 1722 txd->tx_m = m; 1723 txd->tx_ndesc = nsegs + 1; 1724 1725 /* Sync descriptors. */ 1726 bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap, 1727 BUS_DMASYNC_PREWRITE); 1728 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag, 1729 sc->jme_cdata.jme_tx_ring_map, 1730 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1731 1732 return (0); 1733} 1734 1735static void 1736jme_tx_task(void *arg, int pending) 1737{ 1738 struct ifnet *ifp; 1739 1740 ifp = (struct ifnet *)arg; 1741 jme_start(ifp); 1742} 1743 1744static void 1745jme_start(struct ifnet *ifp) 1746{ 1747 struct jme_softc *sc; 1748 struct mbuf *m_head; 1749 int enq; 1750 1751 sc = ifp->if_softc; 1752 1753 JME_LOCK(sc); 1754 1755 if (sc->jme_cdata.jme_tx_cnt >= JME_TX_DESC_HIWAT) 1756 jme_txeof(sc); 1757 1758 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1759 IFF_DRV_RUNNING || (sc->jme_flags & JME_FLAG_LINK) == 0) { 1760 JME_UNLOCK(sc); 1761 return; 1762 } 1763 1764 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 1765 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1766 if (m_head == NULL) 1767 break; 1768 /* 1769 * Pack the data into the transmit ring. If we 1770 * don't have room, set the OACTIVE flag and wait 1771 * for the NIC to drain the ring. 1772 */ 1773 if (jme_encap(sc, &m_head)) { 1774 if (m_head == NULL) 1775 break; 1776 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1777 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1778 break; 1779 } 1780 1781 enq++; 1782 /* 1783 * If there's a BPF listener, bounce a copy of this frame 1784 * to him. 1785 */ 1786 ETHER_BPF_MTAP(ifp, m_head); 1787 } 1788 1789 if (enq > 0) { 1790 /* 1791 * Reading TXCSR takes very long time under heavy load 1792 * so cache TXCSR value and writes the ORed value with 1793 * the kick command to the TXCSR. This saves one register 1794 * access cycle. 1795 */ 1796 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB | 1797 TXCSR_TXQ_N_START(TXCSR_TXQ0)); 1798 /* Set a timeout in case the chip goes out to lunch. */ 1799 sc->jme_watchdog_timer = JME_TX_TIMEOUT; 1800 } 1801 1802 JME_UNLOCK(sc); 1803} 1804 1805static void 1806jme_watchdog(struct jme_softc *sc) 1807{ 1808 struct ifnet *ifp; 1809 1810 JME_LOCK_ASSERT(sc); 1811 1812 if (sc->jme_watchdog_timer == 0 || --sc->jme_watchdog_timer) 1813 return; 1814 1815 ifp = sc->jme_ifp; 1816 if ((sc->jme_flags & JME_FLAG_LINK) == 0) { 1817 if_printf(sc->jme_ifp, "watchdog timeout (missed link)\n"); 1818 ifp->if_oerrors++; 1819 jme_init_locked(sc); 1820 return; 1821 } 1822 jme_txeof(sc); 1823 if (sc->jme_cdata.jme_tx_cnt == 0) { 1824 if_printf(sc->jme_ifp, 1825 "watchdog timeout (missed Tx interrupts) -- recovering\n"); 1826 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1827 taskqueue_enqueue(sc->jme_tq, &sc->jme_tx_task); 1828 return; 1829 } 1830 1831 if_printf(sc->jme_ifp, "watchdog timeout\n"); 1832 ifp->if_oerrors++; 1833 jme_init_locked(sc); 1834 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1835 taskqueue_enqueue(sc->jme_tq, &sc->jme_tx_task); 1836} 1837 1838static int 1839jme_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1840{ 1841 struct jme_softc *sc; 1842 struct ifreq *ifr; 1843 struct mii_data *mii; 1844 uint32_t reg; 1845 int error, mask; 1846 1847 sc = ifp->if_softc; 1848 ifr = (struct ifreq *)data; 1849 error = 0; 1850 switch (cmd) { 1851 case SIOCSIFMTU: 1852 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > JME_JUMBO_MTU || 1853 ((sc->jme_flags & JME_FLAG_NOJUMBO) != 0 && 1854 ifr->ifr_mtu > JME_MAX_MTU)) { 1855 error = EINVAL; 1856 break; 1857 } 1858 1859 if (ifp->if_mtu != ifr->ifr_mtu) { 1860 /* 1861 * No special configuration is required when interface 1862 * MTU is changed but availability of TSO/Tx checksum 1863 * offload should be chcked against new MTU size as 1864 * FIFO size is just 2K. 1865 */ 1866 JME_LOCK(sc); 1867 if (ifr->ifr_mtu >= JME_TX_FIFO_SIZE) { 1868 ifp->if_capenable &= 1869 ~(IFCAP_TXCSUM | IFCAP_TSO4); 1870 ifp->if_hwassist &= 1871 ~(JME_CSUM_FEATURES | CSUM_TSO); 1872 VLAN_CAPABILITIES(ifp); 1873 } 1874 ifp->if_mtu = ifr->ifr_mtu; 1875 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1876 jme_init_locked(sc); 1877 JME_UNLOCK(sc); 1878 } 1879 break; 1880 case SIOCSIFFLAGS: 1881 JME_LOCK(sc); 1882 if ((ifp->if_flags & IFF_UP) != 0) { 1883 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1884 if (((ifp->if_flags ^ sc->jme_if_flags) 1885 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1886 jme_set_filter(sc); 1887 } else { 1888 if ((sc->jme_flags & JME_FLAG_DETACH) == 0) 1889 jme_init_locked(sc); 1890 } 1891 } else { 1892 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1893 jme_stop(sc); 1894 } 1895 sc->jme_if_flags = ifp->if_flags; 1896 JME_UNLOCK(sc); 1897 break; 1898 case SIOCADDMULTI: 1899 case SIOCDELMULTI: 1900 JME_LOCK(sc); 1901 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1902 jme_set_filter(sc); 1903 JME_UNLOCK(sc); 1904 break; 1905 case SIOCSIFMEDIA: 1906 case SIOCGIFMEDIA: 1907 mii = device_get_softc(sc->jme_miibus); 1908 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1909 break; 1910 case SIOCSIFCAP: 1911 JME_LOCK(sc); 1912 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1913 if ((mask & IFCAP_TXCSUM) != 0 && 1914 ifp->if_mtu < JME_TX_FIFO_SIZE) { 1915 if ((IFCAP_TXCSUM & ifp->if_capabilities) != 0) { 1916 ifp->if_capenable ^= IFCAP_TXCSUM; 1917 if ((IFCAP_TXCSUM & ifp->if_capenable) != 0) 1918 ifp->if_hwassist |= JME_CSUM_FEATURES; 1919 else 1920 ifp->if_hwassist &= ~JME_CSUM_FEATURES; 1921 } 1922 } 1923 if ((mask & IFCAP_RXCSUM) != 0 && 1924 (IFCAP_RXCSUM & ifp->if_capabilities) != 0) { 1925 ifp->if_capenable ^= IFCAP_RXCSUM; 1926 reg = CSR_READ_4(sc, JME_RXMAC); 1927 reg &= ~RXMAC_CSUM_ENB; 1928 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1929 reg |= RXMAC_CSUM_ENB; 1930 CSR_WRITE_4(sc, JME_RXMAC, reg); 1931 } 1932 if ((mask & IFCAP_TSO4) != 0 && 1933 ifp->if_mtu < JME_TX_FIFO_SIZE) { 1934 if ((IFCAP_TSO4 & ifp->if_capabilities) != 0) { 1935 ifp->if_capenable ^= IFCAP_TSO4; 1936 if ((IFCAP_TSO4 & ifp->if_capenable) != 0) 1937 ifp->if_hwassist |= CSUM_TSO; 1938 else 1939 ifp->if_hwassist &= ~CSUM_TSO; 1940 } 1941 } 1942 if ((mask & IFCAP_WOL_MAGIC) != 0 && 1943 (IFCAP_WOL_MAGIC & ifp->if_capabilities) != 0) 1944 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 1945 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 1946 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 1947 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 1948 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 1949 (IFCAP_VLAN_HWTAGGING & ifp->if_capabilities) != 0) { 1950 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1951 jme_set_vlan(sc); 1952 } 1953 JME_UNLOCK(sc); 1954 VLAN_CAPABILITIES(ifp); 1955 break; 1956 default: 1957 error = ether_ioctl(ifp, cmd, data); 1958 break; 1959 } 1960 1961 return (error); 1962} 1963 1964static void 1965jme_mac_config(struct jme_softc *sc) 1966{ 1967 struct mii_data *mii; 1968 uint32_t ghc, gpreg, rxmac, txmac, txpause; 1969 uint32_t txclk; 1970 1971 JME_LOCK_ASSERT(sc); 1972 1973 mii = device_get_softc(sc->jme_miibus); 1974 1975 CSR_WRITE_4(sc, JME_GHC, GHC_RESET); 1976 DELAY(10); 1977 CSR_WRITE_4(sc, JME_GHC, 0); 1978 ghc = 0; 1979 txclk = 0; 1980 rxmac = CSR_READ_4(sc, JME_RXMAC); 1981 rxmac &= ~RXMAC_FC_ENB; 1982 txmac = CSR_READ_4(sc, JME_TXMAC); 1983 txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST); 1984 txpause = CSR_READ_4(sc, JME_TXPFC); 1985 txpause &= ~TXPFC_PAUSE_ENB; 1986 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1987 ghc |= GHC_FULL_DUPLEX; 1988 rxmac &= ~RXMAC_COLL_DET_ENB; 1989 txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | 1990 TXMAC_BACKOFF | TXMAC_CARRIER_EXT | 1991 TXMAC_FRAME_BURST); 1992#ifdef notyet 1993 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1994 txpause |= TXPFC_PAUSE_ENB; 1995 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1996 rxmac |= RXMAC_FC_ENB; 1997#endif 1998 /* Disable retry transmit timer/retry limit. */ 1999 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) & 2000 ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB)); 2001 } else { 2002 rxmac |= RXMAC_COLL_DET_ENB; 2003 txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF; 2004 /* Enable retry transmit timer/retry limit. */ 2005 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) | 2006 TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB); 2007 } 2008 /* Reprogram Tx/Rx MACs with resolved speed/duplex. */ 2009 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2010 case IFM_10_T: 2011 ghc |= GHC_SPEED_10; 2012 txclk |= GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100; 2013 break; 2014 case IFM_100_TX: 2015 ghc |= GHC_SPEED_100; 2016 txclk |= GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100; 2017 break; 2018 case IFM_1000_T: 2019 if ((sc->jme_flags & JME_FLAG_FASTETH) != 0) 2020 break; 2021 ghc |= GHC_SPEED_1000; 2022 txclk |= GHC_TX_OFFLD_CLK_1000 | GHC_TX_MAC_CLK_1000; 2023 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0) 2024 txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST; 2025 break; 2026 default: 2027 break; 2028 } 2029 if (sc->jme_rev == DEVICEID_JMC250 && 2030 sc->jme_chip_rev == DEVICEREVID_JMC250_A2) { 2031 /* 2032 * Workaround occasional packet loss issue of JMC250 A2 2033 * when it runs on half-duplex media. 2034 */ 2035 gpreg = CSR_READ_4(sc, JME_GPREG1); 2036 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 2037 gpreg &= ~GPREG1_HDPX_FIX; 2038 else 2039 gpreg |= GPREG1_HDPX_FIX; 2040 CSR_WRITE_4(sc, JME_GPREG1, gpreg); 2041 /* Workaround CRC errors at 100Mbps on JMC250 A2. */ 2042 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 2043 /* Extend interface FIFO depth. */ 2044 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, 2045 0x1B, 0x0000); 2046 } else { 2047 /* Select default interface FIFO depth. */ 2048 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, 2049 0x1B, 0x0004); 2050 } 2051 } 2052 if ((sc->jme_flags & JME_FLAG_TXCLK) != 0) 2053 ghc |= txclk; 2054 CSR_WRITE_4(sc, JME_GHC, ghc); 2055 CSR_WRITE_4(sc, JME_RXMAC, rxmac); 2056 CSR_WRITE_4(sc, JME_TXMAC, txmac); 2057 CSR_WRITE_4(sc, JME_TXPFC, txpause); 2058} 2059 2060static void 2061jme_link_task(void *arg, int pending) 2062{ 2063 struct jme_softc *sc; 2064 struct mii_data *mii; 2065 struct ifnet *ifp; 2066 struct jme_txdesc *txd; 2067 bus_addr_t paddr; 2068 int i; 2069 2070 sc = (struct jme_softc *)arg; 2071 2072 JME_LOCK(sc); 2073 mii = device_get_softc(sc->jme_miibus); 2074 ifp = sc->jme_ifp; 2075 if (mii == NULL || ifp == NULL || 2076 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2077 JME_UNLOCK(sc); 2078 return; 2079 } 2080 2081 sc->jme_flags &= ~JME_FLAG_LINK; 2082 if ((mii->mii_media_status & IFM_AVALID) != 0) { 2083 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2084 case IFM_10_T: 2085 case IFM_100_TX: 2086 sc->jme_flags |= JME_FLAG_LINK; 2087 break; 2088 case IFM_1000_T: 2089 if ((sc->jme_flags & JME_FLAG_FASTETH) != 0) 2090 break; 2091 sc->jme_flags |= JME_FLAG_LINK; 2092 break; 2093 default: 2094 break; 2095 } 2096 } 2097 2098 /* 2099 * Disabling Rx/Tx MACs have a side-effect of resetting 2100 * JME_TXNDA/JME_RXNDA register to the first address of 2101 * Tx/Rx descriptor address. So driver should reset its 2102 * internal procucer/consumer pointer and reclaim any 2103 * allocated resources. Note, just saving the value of 2104 * JME_TXNDA and JME_RXNDA registers before stopping MAC 2105 * and restoring JME_TXNDA/JME_RXNDA register is not 2106 * sufficient to make sure correct MAC state because 2107 * stopping MAC operation can take a while and hardware 2108 * might have updated JME_TXNDA/JME_RXNDA registers 2109 * during the stop operation. 2110 */ 2111 /* Block execution of task. */ 2112 taskqueue_block(sc->jme_tq); 2113 /* Disable interrupts and stop driver. */ 2114 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS); 2115 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2116 callout_stop(&sc->jme_tick_ch); 2117 sc->jme_watchdog_timer = 0; 2118 2119 /* Stop receiver/transmitter. */ 2120 jme_stop_rx(sc); 2121 jme_stop_tx(sc); 2122 2123 /* XXX Drain all queued tasks. */ 2124 JME_UNLOCK(sc); 2125 taskqueue_drain(sc->jme_tq, &sc->jme_int_task); 2126 taskqueue_drain(sc->jme_tq, &sc->jme_tx_task); 2127 JME_LOCK(sc); 2128 2129 jme_rxintr(sc, JME_RX_RING_CNT); 2130 if (sc->jme_cdata.jme_rxhead != NULL) 2131 m_freem(sc->jme_cdata.jme_rxhead); 2132 JME_RXCHAIN_RESET(sc); 2133 jme_txeof(sc); 2134 if (sc->jme_cdata.jme_tx_cnt != 0) { 2135 /* Remove queued packets for transmit. */ 2136 for (i = 0; i < JME_TX_RING_CNT; i++) { 2137 txd = &sc->jme_cdata.jme_txdesc[i]; 2138 if (txd->tx_m != NULL) { 2139 bus_dmamap_sync( 2140 sc->jme_cdata.jme_tx_tag, 2141 txd->tx_dmamap, 2142 BUS_DMASYNC_POSTWRITE); 2143 bus_dmamap_unload( 2144 sc->jme_cdata.jme_tx_tag, 2145 txd->tx_dmamap); 2146 m_freem(txd->tx_m); 2147 txd->tx_m = NULL; 2148 txd->tx_ndesc = 0; 2149 ifp->if_oerrors++; 2150 } 2151 } 2152 } 2153 2154 /* 2155 * Reuse configured Rx descriptors and reset 2156 * procuder/consumer index. 2157 */ 2158 sc->jme_cdata.jme_rx_cons = 0; 2159 atomic_set_int(&sc->jme_morework, 0); 2160 jme_init_tx_ring(sc); 2161 /* Initialize shadow status block. */ 2162 jme_init_ssb(sc); 2163 2164 /* Program MAC with resolved speed/duplex/flow-control. */ 2165 if ((sc->jme_flags & JME_FLAG_LINK) != 0) { 2166 jme_mac_config(sc); 2167 2168 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr); 2169 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr); 2170 2171 /* Set Tx ring address to the hardware. */ 2172 paddr = JME_TX_RING_ADDR(sc, 0); 2173 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr)); 2174 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr)); 2175 2176 /* Set Rx ring address to the hardware. */ 2177 paddr = JME_RX_RING_ADDR(sc, 0); 2178 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr)); 2179 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr)); 2180 2181 /* Restart receiver/transmitter. */ 2182 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RX_ENB | 2183 RXCSR_RXQ_START); 2184 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB); 2185 } 2186 2187 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2188 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2189 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc); 2190 /* Unblock execution of task. */ 2191 taskqueue_unblock(sc->jme_tq); 2192 /* Reenable interrupts. */ 2193 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS); 2194 2195 JME_UNLOCK(sc); 2196} 2197 2198static int 2199jme_intr(void *arg) 2200{ 2201 struct jme_softc *sc; 2202 uint32_t status; 2203 2204 sc = (struct jme_softc *)arg; 2205 2206 status = CSR_READ_4(sc, JME_INTR_REQ_STATUS); 2207 if (status == 0 || status == 0xFFFFFFFF) 2208 return (FILTER_STRAY); 2209 /* Disable interrupts. */ 2210 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS); 2211 taskqueue_enqueue(sc->jme_tq, &sc->jme_int_task); 2212 2213 return (FILTER_HANDLED); 2214} 2215 2216static void 2217jme_int_task(void *arg, int pending) 2218{ 2219 struct jme_softc *sc; 2220 struct ifnet *ifp; 2221 uint32_t status; 2222 int more; 2223 2224 sc = (struct jme_softc *)arg; 2225 ifp = sc->jme_ifp; 2226 2227 status = CSR_READ_4(sc, JME_INTR_STATUS); 2228 more = atomic_readandclear_int(&sc->jme_morework); 2229 if (more != 0) { 2230 status |= INTR_RXQ_COAL | INTR_RXQ_COAL_TO; 2231 more = 0; 2232 } 2233 if ((status & JME_INTRS) == 0 || status == 0xFFFFFFFF) 2234 goto done; 2235 /* Reset PCC counter/timer and Ack interrupts. */ 2236 status &= ~(INTR_TXQ_COMP | INTR_RXQ_COMP); 2237 if ((status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) != 0) 2238 status |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP; 2239 if ((status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0) 2240 status |= INTR_RXQ_COAL | INTR_RXQ_COAL_TO | INTR_RXQ_COMP; 2241 CSR_WRITE_4(sc, JME_INTR_STATUS, status); 2242 more = 0; 2243 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2244 if ((status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0) { 2245 more = jme_rxintr(sc, sc->jme_process_limit); 2246 if (more != 0) 2247 atomic_set_int(&sc->jme_morework, 1); 2248 } 2249 if ((status & INTR_RXQ_DESC_EMPTY) != 0) { 2250 /* 2251 * Notify hardware availability of new Rx 2252 * buffers. 2253 * Reading RXCSR takes very long time under 2254 * heavy load so cache RXCSR value and writes 2255 * the ORed value with the kick command to 2256 * the RXCSR. This saves one register access 2257 * cycle. 2258 */ 2259 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | 2260 RXCSR_RX_ENB | RXCSR_RXQ_START); 2261 } 2262 /* 2263 * Reclaiming Tx buffers are deferred to make jme(4) run 2264 * without locks held. 2265 */ 2266 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2267 taskqueue_enqueue(sc->jme_tq, &sc->jme_tx_task); 2268 } 2269 2270 if (more != 0 || (CSR_READ_4(sc, JME_INTR_STATUS) & JME_INTRS) != 0) { 2271 taskqueue_enqueue(sc->jme_tq, &sc->jme_int_task); 2272 return; 2273 } 2274done: 2275 /* Reenable interrupts. */ 2276 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS); 2277} 2278 2279static void 2280jme_txeof(struct jme_softc *sc) 2281{ 2282 struct ifnet *ifp; 2283 struct jme_txdesc *txd; 2284 uint32_t status; 2285 int cons, nsegs; 2286 2287 JME_LOCK_ASSERT(sc); 2288 2289 ifp = sc->jme_ifp; 2290 2291 cons = sc->jme_cdata.jme_tx_cons; 2292 if (cons == sc->jme_cdata.jme_tx_prod) 2293 return; 2294 2295 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag, 2296 sc->jme_cdata.jme_tx_ring_map, 2297 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2298 2299 /* 2300 * Go through our Tx list and free mbufs for those 2301 * frames which have been transmitted. 2302 */ 2303 for (; cons != sc->jme_cdata.jme_tx_prod;) { 2304 txd = &sc->jme_cdata.jme_txdesc[cons]; 2305 status = le32toh(txd->tx_desc->flags); 2306 if ((status & JME_TD_OWN) == JME_TD_OWN) 2307 break; 2308 2309 if ((status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) != 0) 2310 ifp->if_oerrors++; 2311 else { 2312 ifp->if_opackets++; 2313 if ((status & JME_TD_COLLISION) != 0) 2314 ifp->if_collisions += 2315 le32toh(txd->tx_desc->buflen) & 2316 JME_TD_BUF_LEN_MASK; 2317 } 2318 /* 2319 * Only the first descriptor of multi-descriptor 2320 * transmission is updated so driver have to skip entire 2321 * chained buffers for the transmiited frame. In other 2322 * words, JME_TD_OWN bit is valid only at the first 2323 * descriptor of a multi-descriptor transmission. 2324 */ 2325 for (nsegs = 0; nsegs < txd->tx_ndesc; nsegs++) { 2326 sc->jme_rdata.jme_tx_ring[cons].flags = 0; 2327 JME_DESC_INC(cons, JME_TX_RING_CNT); 2328 } 2329 2330 /* Reclaim transferred mbufs. */ 2331 bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap, 2332 BUS_DMASYNC_POSTWRITE); 2333 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap); 2334 2335 KASSERT(txd->tx_m != NULL, 2336 ("%s: freeing NULL mbuf!\n", __func__)); 2337 m_freem(txd->tx_m); 2338 txd->tx_m = NULL; 2339 sc->jme_cdata.jme_tx_cnt -= txd->tx_ndesc; 2340 KASSERT(sc->jme_cdata.jme_tx_cnt >= 0, 2341 ("%s: Active Tx desc counter was garbled\n", __func__)); 2342 txd->tx_ndesc = 0; 2343 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2344 } 2345 sc->jme_cdata.jme_tx_cons = cons; 2346 /* Unarm watchog timer when there is no pending descriptors in queue. */ 2347 if (sc->jme_cdata.jme_tx_cnt == 0) 2348 sc->jme_watchdog_timer = 0; 2349 2350 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag, 2351 sc->jme_cdata.jme_tx_ring_map, 2352 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2353} 2354 2355static __inline void 2356jme_discard_rxbuf(struct jme_softc *sc, int cons) 2357{ 2358 struct jme_desc *desc; 2359 2360 desc = &sc->jme_rdata.jme_rx_ring[cons]; 2361 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT); 2362 desc->buflen = htole32(MCLBYTES); 2363} 2364 2365/* Receive a frame. */ 2366static void 2367jme_rxeof(struct jme_softc *sc) 2368{ 2369 struct ifnet *ifp; 2370 struct jme_desc *desc; 2371 struct jme_rxdesc *rxd; 2372 struct mbuf *mp, *m; 2373 uint32_t flags, status; 2374 int cons, count, nsegs; 2375 2376 ifp = sc->jme_ifp; 2377 2378 cons = sc->jme_cdata.jme_rx_cons; 2379 desc = &sc->jme_rdata.jme_rx_ring[cons]; 2380 flags = le32toh(desc->flags); 2381 status = le32toh(desc->buflen); 2382 nsegs = JME_RX_NSEGS(status); 2383 sc->jme_cdata.jme_rxlen = JME_RX_BYTES(status) - JME_RX_PAD_BYTES; 2384 if ((status & JME_RX_ERR_STAT) != 0) { 2385 ifp->if_ierrors++; 2386 jme_discard_rxbuf(sc, sc->jme_cdata.jme_rx_cons); 2387#ifdef JME_SHOW_ERRORS 2388 device_printf(sc->jme_dev, "%s : receive error = 0x%b\n", 2389 __func__, JME_RX_ERR(status), JME_RX_ERR_BITS); 2390#endif 2391 sc->jme_cdata.jme_rx_cons += nsegs; 2392 sc->jme_cdata.jme_rx_cons %= JME_RX_RING_CNT; 2393 return; 2394 } 2395 2396 for (count = 0; count < nsegs; count++, 2397 JME_DESC_INC(cons, JME_RX_RING_CNT)) { 2398 rxd = &sc->jme_cdata.jme_rxdesc[cons]; 2399 mp = rxd->rx_m; 2400 /* Add a new receive buffer to the ring. */ 2401 if (jme_newbuf(sc, rxd) != 0) { 2402 ifp->if_iqdrops++; 2403 /* Reuse buffer. */ 2404 for (; count < nsegs; count++) { 2405 jme_discard_rxbuf(sc, cons); 2406 JME_DESC_INC(cons, JME_RX_RING_CNT); 2407 } 2408 if (sc->jme_cdata.jme_rxhead != NULL) { 2409 m_freem(sc->jme_cdata.jme_rxhead); 2410 JME_RXCHAIN_RESET(sc); 2411 } 2412 break; 2413 } 2414 2415 /* 2416 * Assume we've received a full sized frame. 2417 * Actual size is fixed when we encounter the end of 2418 * multi-segmented frame. 2419 */ 2420 mp->m_len = MCLBYTES; 2421 2422 /* Chain received mbufs. */ 2423 if (sc->jme_cdata.jme_rxhead == NULL) { 2424 sc->jme_cdata.jme_rxhead = mp; 2425 sc->jme_cdata.jme_rxtail = mp; 2426 } else { 2427 /* 2428 * Receive processor can receive a maximum frame 2429 * size of 65535 bytes. 2430 */ 2431 mp->m_flags &= ~M_PKTHDR; 2432 sc->jme_cdata.jme_rxtail->m_next = mp; 2433 sc->jme_cdata.jme_rxtail = mp; 2434 } 2435 2436 if (count == nsegs - 1) { 2437 /* Last desc. for this frame. */ 2438 m = sc->jme_cdata.jme_rxhead; 2439 m->m_flags |= M_PKTHDR; 2440 m->m_pkthdr.len = sc->jme_cdata.jme_rxlen; 2441 if (nsegs > 1) { 2442 /* Set first mbuf size. */ 2443 m->m_len = MCLBYTES - JME_RX_PAD_BYTES; 2444 /* Set last mbuf size. */ 2445 mp->m_len = sc->jme_cdata.jme_rxlen - 2446 ((MCLBYTES - JME_RX_PAD_BYTES) + 2447 (MCLBYTES * (nsegs - 2))); 2448 } else 2449 m->m_len = sc->jme_cdata.jme_rxlen; 2450 m->m_pkthdr.rcvif = ifp; 2451 2452 /* 2453 * Account for 10bytes auto padding which is used 2454 * to align IP header on 32bit boundary. Also note, 2455 * CRC bytes is automatically removed by the 2456 * hardware. 2457 */ 2458 m->m_data += JME_RX_PAD_BYTES; 2459 2460 /* Set checksum information. */ 2461 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && 2462 (flags & JME_RD_IPV4) != 0) { 2463 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2464 if ((flags & JME_RD_IPCSUM) != 0) 2465 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2466 if (((flags & JME_RD_MORE_FRAG) == 0) && 2467 ((flags & (JME_RD_TCP | JME_RD_TCPCSUM)) == 2468 (JME_RD_TCP | JME_RD_TCPCSUM) || 2469 (flags & (JME_RD_UDP | JME_RD_UDPCSUM)) == 2470 (JME_RD_UDP | JME_RD_UDPCSUM))) { 2471 m->m_pkthdr.csum_flags |= 2472 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2473 m->m_pkthdr.csum_data = 0xffff; 2474 } 2475 } 2476 2477 /* Check for VLAN tagged packets. */ 2478 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 2479 (flags & JME_RD_VLAN_TAG) != 0) { 2480 m->m_pkthdr.ether_vtag = 2481 flags & JME_RD_VLAN_MASK; 2482 m->m_flags |= M_VLANTAG; 2483 } 2484 2485 ifp->if_ipackets++; 2486 /* Pass it on. */ 2487 (*ifp->if_input)(ifp, m); 2488 2489 /* Reset mbuf chains. */ 2490 JME_RXCHAIN_RESET(sc); 2491 } 2492 } 2493 2494 sc->jme_cdata.jme_rx_cons += nsegs; 2495 sc->jme_cdata.jme_rx_cons %= JME_RX_RING_CNT; 2496} 2497 2498static int 2499jme_rxintr(struct jme_softc *sc, int count) 2500{ 2501 struct jme_desc *desc; 2502 int nsegs, prog, pktlen; 2503 2504 bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag, 2505 sc->jme_cdata.jme_rx_ring_map, 2506 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2507 2508 for (prog = 0; count > 0; prog++) { 2509 desc = &sc->jme_rdata.jme_rx_ring[sc->jme_cdata.jme_rx_cons]; 2510 if ((le32toh(desc->flags) & JME_RD_OWN) == JME_RD_OWN) 2511 break; 2512 if ((le32toh(desc->buflen) & JME_RD_VALID) == 0) 2513 break; 2514 nsegs = JME_RX_NSEGS(le32toh(desc->buflen)); 2515 /* 2516 * Check number of segments against received bytes. 2517 * Non-matching value would indicate that hardware 2518 * is still trying to update Rx descriptors. I'm not 2519 * sure whether this check is needed. 2520 */ 2521 pktlen = JME_RX_BYTES(le32toh(desc->buflen)); 2522 if (nsegs != ((pktlen + (MCLBYTES - 1)) / MCLBYTES)) 2523 break; 2524 prog++; 2525 /* Received a frame. */ 2526 jme_rxeof(sc); 2527 count -= nsegs; 2528 } 2529 2530 if (prog > 0) 2531 bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag, 2532 sc->jme_cdata.jme_rx_ring_map, 2533 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2534 2535 return (count > 0 ? 0 : EAGAIN); 2536} 2537 2538static void 2539jme_tick(void *arg) 2540{ 2541 struct jme_softc *sc; 2542 struct mii_data *mii; 2543 2544 sc = (struct jme_softc *)arg; 2545 2546 JME_LOCK_ASSERT(sc); 2547 2548 mii = device_get_softc(sc->jme_miibus); 2549 mii_tick(mii); 2550 /* 2551 * Reclaim Tx buffers that have been completed. It's not 2552 * needed here but it would release allocated mbuf chains 2553 * faster and limit the maximum delay to a hz. 2554 */ 2555 jme_txeof(sc); 2556 jme_watchdog(sc); 2557 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc); 2558} 2559 2560static void 2561jme_reset(struct jme_softc *sc) 2562{ 2563 2564 /* Stop receiver, transmitter. */ 2565 jme_stop_rx(sc); 2566 jme_stop_tx(sc); 2567 CSR_WRITE_4(sc, JME_GHC, GHC_RESET); 2568 DELAY(10); 2569 CSR_WRITE_4(sc, JME_GHC, 0); 2570} 2571 2572static void 2573jme_init(void *xsc) 2574{ 2575 struct jme_softc *sc; 2576 2577 sc = (struct jme_softc *)xsc; 2578 JME_LOCK(sc); 2579 jme_init_locked(sc); 2580 JME_UNLOCK(sc); 2581} 2582 2583static void 2584jme_init_locked(struct jme_softc *sc) 2585{ 2586 struct ifnet *ifp; 2587 struct mii_data *mii; 2588 uint8_t eaddr[ETHER_ADDR_LEN]; 2589 bus_addr_t paddr; 2590 uint32_t reg; 2591 int error; 2592 2593 JME_LOCK_ASSERT(sc); 2594 2595 ifp = sc->jme_ifp; 2596 mii = device_get_softc(sc->jme_miibus); 2597 2598 /* 2599 * Cancel any pending I/O. 2600 */ 2601 jme_stop(sc); 2602 2603 /* 2604 * Reset the chip to a known state. 2605 */ 2606 jme_reset(sc); 2607 2608 /* Init descriptors. */ 2609 error = jme_init_rx_ring(sc); 2610 if (error != 0) { 2611 device_printf(sc->jme_dev, 2612 "%s: initialization failed: no memory for Rx buffers.\n", 2613 __func__); 2614 jme_stop(sc); 2615 return; 2616 } 2617 jme_init_tx_ring(sc); 2618 /* Initialize shadow status block. */ 2619 jme_init_ssb(sc); 2620 2621 /* Reprogram the station address. */ 2622 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 2623 CSR_WRITE_4(sc, JME_PAR0, 2624 eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]); 2625 CSR_WRITE_4(sc, JME_PAR1, eaddr[5] << 8 | eaddr[4]); 2626 2627 /* 2628 * Configure Tx queue. 2629 * Tx priority queue weight value : 0 2630 * Tx FIFO threshold for processing next packet : 16QW 2631 * Maximum Tx DMA length : 512 2632 * Allow Tx DMA burst. 2633 */ 2634 sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0); 2635 sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN); 2636 sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW; 2637 sc->jme_txcsr |= sc->jme_tx_dma_size; 2638 sc->jme_txcsr |= TXCSR_DMA_BURST; 2639 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr); 2640 2641 /* Set Tx descriptor counter. */ 2642 CSR_WRITE_4(sc, JME_TXQDC, JME_TX_RING_CNT); 2643 2644 /* Set Tx ring address to the hardware. */ 2645 paddr = JME_TX_RING_ADDR(sc, 0); 2646 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr)); 2647 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr)); 2648 2649 /* Configure TxMAC parameters. */ 2650 reg = TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB; 2651 reg |= TXMAC_THRESH_1_PKT; 2652 reg |= TXMAC_CRC_ENB | TXMAC_PAD_ENB; 2653 CSR_WRITE_4(sc, JME_TXMAC, reg); 2654 2655 /* 2656 * Configure Rx queue. 2657 * FIFO full threshold for transmitting Tx pause packet : 128T 2658 * FIFO threshold for processing next packet : 128QW 2659 * Rx queue 0 select 2660 * Max Rx DMA length : 128 2661 * Rx descriptor retry : 32 2662 * Rx descriptor retry time gap : 256ns 2663 * Don't receive runt/bad frame. 2664 */ 2665 sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T; 2666 /* 2667 * Since Rx FIFO size is 4K bytes, receiving frames larger 2668 * than 4K bytes will suffer from Rx FIFO overruns. So 2669 * decrease FIFO threshold to reduce the FIFO overruns for 2670 * frames larger than 4000 bytes. 2671 * For best performance of standard MTU sized frames use 2672 * maximum allowable FIFO threshold, 128QW. Note these do 2673 * not hold on chip full mask verion >=2. For these 2674 * controllers 64QW and 128QW are not valid value. 2675 */ 2676 if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 2) 2677 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW; 2678 else { 2679 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 2680 ETHER_CRC_LEN) > JME_RX_FIFO_SIZE) 2681 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW; 2682 else 2683 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW; 2684 } 2685 sc->jme_rxcsr |= sc->jme_rx_dma_size | RXCSR_RXQ_N_SEL(RXCSR_RXQ0); 2686 sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT); 2687 sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK; 2688 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr); 2689 2690 /* Set Rx descriptor counter. */ 2691 CSR_WRITE_4(sc, JME_RXQDC, JME_RX_RING_CNT); 2692 2693 /* Set Rx ring address to the hardware. */ 2694 paddr = JME_RX_RING_ADDR(sc, 0); 2695 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr)); 2696 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr)); 2697 2698 /* Clear receive filter. */ 2699 CSR_WRITE_4(sc, JME_RXMAC, 0); 2700 /* Set up the receive filter. */ 2701 jme_set_filter(sc); 2702 jme_set_vlan(sc); 2703 2704 /* 2705 * Disable all WOL bits as WOL can interfere normal Rx 2706 * operation. Also clear WOL detection status bits. 2707 */ 2708 reg = CSR_READ_4(sc, JME_PMCS); 2709 reg &= ~PMCS_WOL_ENB_MASK; 2710 CSR_WRITE_4(sc, JME_PMCS, reg); 2711 2712 reg = CSR_READ_4(sc, JME_RXMAC); 2713 /* 2714 * Pad 10bytes right before received frame. This will greatly 2715 * help Rx performance on strict-alignment architectures as 2716 * it does not need to copy the frame to align the payload. 2717 */ 2718 reg |= RXMAC_PAD_10BYTES; 2719 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2720 reg |= RXMAC_CSUM_ENB; 2721 CSR_WRITE_4(sc, JME_RXMAC, reg); 2722 2723 /* Configure general purpose reg0 */ 2724 reg = CSR_READ_4(sc, JME_GPREG0); 2725 reg &= ~GPREG0_PCC_UNIT_MASK; 2726 /* Set PCC timer resolution to micro-seconds unit. */ 2727 reg |= GPREG0_PCC_UNIT_US; 2728 /* 2729 * Disable all shadow register posting as we have to read 2730 * JME_INTR_STATUS register in jme_int_task. Also it seems 2731 * that it's hard to synchronize interrupt status between 2732 * hardware and software with shadow posting due to 2733 * requirements of bus_dmamap_sync(9). 2734 */ 2735 reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS | 2736 GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS | 2737 GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS | 2738 GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS; 2739 /* Disable posting of DW0. */ 2740 reg &= ~GPREG0_POST_DW0_ENB; 2741 /* Clear PME message. */ 2742 reg &= ~GPREG0_PME_ENB; 2743 /* Set PHY address. */ 2744 reg &= ~GPREG0_PHY_ADDR_MASK; 2745 reg |= sc->jme_phyaddr; 2746 CSR_WRITE_4(sc, JME_GPREG0, reg); 2747 2748 /* Configure Tx queue 0 packet completion coalescing. */ 2749 reg = (sc->jme_tx_coal_to << PCCTX_COAL_TO_SHIFT) & 2750 PCCTX_COAL_TO_MASK; 2751 reg |= (sc->jme_tx_coal_pkt << PCCTX_COAL_PKT_SHIFT) & 2752 PCCTX_COAL_PKT_MASK; 2753 reg |= PCCTX_COAL_TXQ0; 2754 CSR_WRITE_4(sc, JME_PCCTX, reg); 2755 2756 /* Configure Rx queue 0 packet completion coalescing. */ 2757 reg = (sc->jme_rx_coal_to << PCCRX_COAL_TO_SHIFT) & 2758 PCCRX_COAL_TO_MASK; 2759 reg |= (sc->jme_rx_coal_pkt << PCCRX_COAL_PKT_SHIFT) & 2760 PCCRX_COAL_PKT_MASK; 2761 CSR_WRITE_4(sc, JME_PCCRX0, reg); 2762 2763 /* Configure shadow status block but don't enable posting. */ 2764 paddr = sc->jme_rdata.jme_ssb_block_paddr; 2765 CSR_WRITE_4(sc, JME_SHBASE_ADDR_HI, JME_ADDR_HI(paddr)); 2766 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, JME_ADDR_LO(paddr)); 2767 2768 /* Disable Timer 1 and Timer 2. */ 2769 CSR_WRITE_4(sc, JME_TIMER1, 0); 2770 CSR_WRITE_4(sc, JME_TIMER2, 0); 2771 2772 /* Configure retry transmit period, retry limit value. */ 2773 CSR_WRITE_4(sc, JME_TXTRHD, 2774 ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) & 2775 TXTRHD_RT_PERIOD_MASK) | 2776 ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) & 2777 TXTRHD_RT_LIMIT_SHIFT)); 2778 2779 /* Disable RSS. */ 2780 CSR_WRITE_4(sc, JME_RSSC, RSSC_DIS_RSS); 2781 2782 /* Initialize the interrupt mask. */ 2783 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS); 2784 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF); 2785 2786 /* 2787 * Enabling Tx/Rx DMA engines and Rx queue processing is 2788 * done after detection of valid link in jme_link_task. 2789 */ 2790 2791 sc->jme_flags &= ~JME_FLAG_LINK; 2792 /* Set the current media. */ 2793 mii_mediachg(mii); 2794 2795 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc); 2796 2797 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2798 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2799} 2800 2801static void 2802jme_stop(struct jme_softc *sc) 2803{ 2804 struct ifnet *ifp; 2805 struct jme_txdesc *txd; 2806 struct jme_rxdesc *rxd; 2807 int i; 2808 2809 JME_LOCK_ASSERT(sc); 2810 /* 2811 * Mark the interface down and cancel the watchdog timer. 2812 */ 2813 ifp = sc->jme_ifp; 2814 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2815 sc->jme_flags &= ~JME_FLAG_LINK; 2816 callout_stop(&sc->jme_tick_ch); 2817 sc->jme_watchdog_timer = 0; 2818 2819 /* 2820 * Disable interrupts. 2821 */ 2822 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS); 2823 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF); 2824 2825 /* Disable updating shadow status block. */ 2826 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, 2827 CSR_READ_4(sc, JME_SHBASE_ADDR_LO) & ~SHBASE_POST_ENB); 2828 2829 /* Stop receiver, transmitter. */ 2830 jme_stop_rx(sc); 2831 jme_stop_tx(sc); 2832 2833 /* Reclaim Rx/Tx buffers that have been completed. */ 2834 jme_rxintr(sc, JME_RX_RING_CNT); 2835 if (sc->jme_cdata.jme_rxhead != NULL) 2836 m_freem(sc->jme_cdata.jme_rxhead); 2837 JME_RXCHAIN_RESET(sc); 2838 jme_txeof(sc); 2839 /* 2840 * Free RX and TX mbufs still in the queues. 2841 */ 2842 for (i = 0; i < JME_RX_RING_CNT; i++) { 2843 rxd = &sc->jme_cdata.jme_rxdesc[i]; 2844 if (rxd->rx_m != NULL) { 2845 bus_dmamap_sync(sc->jme_cdata.jme_rx_tag, 2846 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2847 bus_dmamap_unload(sc->jme_cdata.jme_rx_tag, 2848 rxd->rx_dmamap); 2849 m_freem(rxd->rx_m); 2850 rxd->rx_m = NULL; 2851 } 2852 } 2853 for (i = 0; i < JME_TX_RING_CNT; i++) { 2854 txd = &sc->jme_cdata.jme_txdesc[i]; 2855 if (txd->tx_m != NULL) { 2856 bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, 2857 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2858 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, 2859 txd->tx_dmamap); 2860 m_freem(txd->tx_m); 2861 txd->tx_m = NULL; 2862 txd->tx_ndesc = 0; 2863 } 2864 } 2865} 2866 2867static void 2868jme_stop_tx(struct jme_softc *sc) 2869{ 2870 uint32_t reg; 2871 int i; 2872 2873 reg = CSR_READ_4(sc, JME_TXCSR); 2874 if ((reg & TXCSR_TX_ENB) == 0) 2875 return; 2876 reg &= ~TXCSR_TX_ENB; 2877 CSR_WRITE_4(sc, JME_TXCSR, reg); 2878 for (i = JME_TIMEOUT; i > 0; i--) { 2879 DELAY(1); 2880 if ((CSR_READ_4(sc, JME_TXCSR) & TXCSR_TX_ENB) == 0) 2881 break; 2882 } 2883 if (i == 0) 2884 device_printf(sc->jme_dev, "stopping transmitter timeout!\n"); 2885} 2886 2887static void 2888jme_stop_rx(struct jme_softc *sc) 2889{ 2890 uint32_t reg; 2891 int i; 2892 2893 reg = CSR_READ_4(sc, JME_RXCSR); 2894 if ((reg & RXCSR_RX_ENB) == 0) 2895 return; 2896 reg &= ~RXCSR_RX_ENB; 2897 CSR_WRITE_4(sc, JME_RXCSR, reg); 2898 for (i = JME_TIMEOUT; i > 0; i--) { 2899 DELAY(1); 2900 if ((CSR_READ_4(sc, JME_RXCSR) & RXCSR_RX_ENB) == 0) 2901 break; 2902 } 2903 if (i == 0) 2904 device_printf(sc->jme_dev, "stopping recevier timeout!\n"); 2905} 2906 2907static void 2908jme_init_tx_ring(struct jme_softc *sc) 2909{ 2910 struct jme_ring_data *rd; 2911 struct jme_txdesc *txd; 2912 int i; 2913 2914 sc->jme_cdata.jme_tx_prod = 0; 2915 sc->jme_cdata.jme_tx_cons = 0; 2916 sc->jme_cdata.jme_tx_cnt = 0; 2917 2918 rd = &sc->jme_rdata; 2919 bzero(rd->jme_tx_ring, JME_TX_RING_SIZE); 2920 for (i = 0; i < JME_TX_RING_CNT; i++) { 2921 txd = &sc->jme_cdata.jme_txdesc[i]; 2922 txd->tx_m = NULL; 2923 txd->tx_desc = &rd->jme_tx_ring[i]; 2924 txd->tx_ndesc = 0; 2925 } 2926 2927 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag, 2928 sc->jme_cdata.jme_tx_ring_map, 2929 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2930} 2931 2932static void 2933jme_init_ssb(struct jme_softc *sc) 2934{ 2935 struct jme_ring_data *rd; 2936 2937 rd = &sc->jme_rdata; 2938 bzero(rd->jme_ssb_block, JME_SSB_SIZE); 2939 bus_dmamap_sync(sc->jme_cdata.jme_ssb_tag, sc->jme_cdata.jme_ssb_map, 2940 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2941} 2942 2943static int 2944jme_init_rx_ring(struct jme_softc *sc) 2945{ 2946 struct jme_ring_data *rd; 2947 struct jme_rxdesc *rxd; 2948 int i; 2949 2950 sc->jme_cdata.jme_rx_cons = 0; 2951 JME_RXCHAIN_RESET(sc); 2952 atomic_set_int(&sc->jme_morework, 0); 2953 2954 rd = &sc->jme_rdata; 2955 bzero(rd->jme_rx_ring, JME_RX_RING_SIZE); 2956 for (i = 0; i < JME_RX_RING_CNT; i++) { 2957 rxd = &sc->jme_cdata.jme_rxdesc[i]; 2958 rxd->rx_m = NULL; 2959 rxd->rx_desc = &rd->jme_rx_ring[i]; 2960 if (jme_newbuf(sc, rxd) != 0) 2961 return (ENOBUFS); 2962 } 2963 2964 bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag, 2965 sc->jme_cdata.jme_rx_ring_map, 2966 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2967 2968 return (0); 2969} 2970 2971static int 2972jme_newbuf(struct jme_softc *sc, struct jme_rxdesc *rxd) 2973{ 2974 struct jme_desc *desc; 2975 struct mbuf *m; 2976 bus_dma_segment_t segs[1]; 2977 bus_dmamap_t map; 2978 int nsegs; 2979 2980 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2981 if (m == NULL) 2982 return (ENOBUFS); 2983 /* 2984 * JMC250 has 64bit boundary alignment limitation so jme(4) 2985 * takes advantage of 10 bytes padding feature of hardware 2986 * in order not to copy entire frame to align IP header on 2987 * 32bit boundary. 2988 */ 2989 m->m_len = m->m_pkthdr.len = MCLBYTES; 2990 2991 if (bus_dmamap_load_mbuf_sg(sc->jme_cdata.jme_rx_tag, 2992 sc->jme_cdata.jme_rx_sparemap, m, segs, &nsegs, 0) != 0) { 2993 m_freem(m); 2994 return (ENOBUFS); 2995 } 2996 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 2997 2998 if (rxd->rx_m != NULL) { 2999 bus_dmamap_sync(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap, 3000 BUS_DMASYNC_POSTREAD); 3001 bus_dmamap_unload(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap); 3002 } 3003 map = rxd->rx_dmamap; 3004 rxd->rx_dmamap = sc->jme_cdata.jme_rx_sparemap; 3005 sc->jme_cdata.jme_rx_sparemap = map; 3006 bus_dmamap_sync(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap, 3007 BUS_DMASYNC_PREREAD); 3008 rxd->rx_m = m; 3009 3010 desc = rxd->rx_desc; 3011 desc->buflen = htole32(segs[0].ds_len); 3012 desc->addr_lo = htole32(JME_ADDR_LO(segs[0].ds_addr)); 3013 desc->addr_hi = htole32(JME_ADDR_HI(segs[0].ds_addr)); 3014 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT); 3015 3016 return (0); 3017} 3018 3019static void 3020jme_set_vlan(struct jme_softc *sc) 3021{ 3022 struct ifnet *ifp; 3023 uint32_t reg; 3024 3025 JME_LOCK_ASSERT(sc); 3026 3027 ifp = sc->jme_ifp; 3028 reg = CSR_READ_4(sc, JME_RXMAC); 3029 reg &= ~RXMAC_VLAN_ENB; 3030 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3031 reg |= RXMAC_VLAN_ENB; 3032 CSR_WRITE_4(sc, JME_RXMAC, reg); 3033} 3034 3035static void 3036jme_set_filter(struct jme_softc *sc) 3037{ 3038 struct ifnet *ifp; 3039 struct ifmultiaddr *ifma; 3040 uint32_t crc; 3041 uint32_t mchash[2]; 3042 uint32_t rxcfg; 3043 3044 JME_LOCK_ASSERT(sc); 3045 3046 ifp = sc->jme_ifp; 3047 3048 rxcfg = CSR_READ_4(sc, JME_RXMAC); 3049 rxcfg &= ~ (RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST | 3050 RXMAC_ALLMULTI); 3051 /* Always accept frames destined to our station address. */ 3052 rxcfg |= RXMAC_UNICAST; 3053 if ((ifp->if_flags & IFF_BROADCAST) != 0) 3054 rxcfg |= RXMAC_BROADCAST; 3055 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3056 if ((ifp->if_flags & IFF_PROMISC) != 0) 3057 rxcfg |= RXMAC_PROMISC; 3058 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 3059 rxcfg |= RXMAC_ALLMULTI; 3060 CSR_WRITE_4(sc, JME_MAR0, 0xFFFFFFFF); 3061 CSR_WRITE_4(sc, JME_MAR1, 0xFFFFFFFF); 3062 CSR_WRITE_4(sc, JME_RXMAC, rxcfg); 3063 return; 3064 } 3065 3066 /* 3067 * Set up the multicast address filter by passing all multicast 3068 * addresses through a CRC generator, and then using the low-order 3069 * 6 bits as an index into the 64 bit multicast hash table. The 3070 * high order bits select the register, while the rest of the bits 3071 * select the bit within the register. 3072 */ 3073 rxcfg |= RXMAC_MULTICAST; 3074 bzero(mchash, sizeof(mchash)); 3075 3076 IF_ADDR_LOCK(ifp); 3077 TAILQ_FOREACH(ifma, &sc->jme_ifp->if_multiaddrs, ifma_link) { 3078 if (ifma->ifma_addr->sa_family != AF_LINK) 3079 continue; 3080 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 3081 ifma->ifma_addr), ETHER_ADDR_LEN); 3082 3083 /* Just want the 6 least significant bits. */ 3084 crc &= 0x3f; 3085 3086 /* Set the corresponding bit in the hash table. */ 3087 mchash[crc >> 5] |= 1 << (crc & 0x1f); 3088 } 3089 IF_ADDR_UNLOCK(ifp); 3090 3091 CSR_WRITE_4(sc, JME_MAR0, mchash[0]); 3092 CSR_WRITE_4(sc, JME_MAR1, mchash[1]); 3093 CSR_WRITE_4(sc, JME_RXMAC, rxcfg); 3094} 3095 3096static int 3097sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3098{ 3099 int error, value; 3100 3101 if (arg1 == NULL) 3102 return (EINVAL); 3103 value = *(int *)arg1; 3104 error = sysctl_handle_int(oidp, &value, 0, req); 3105 if (error || req->newptr == NULL) 3106 return (error); 3107 if (value < low || value > high) 3108 return (EINVAL); 3109 *(int *)arg1 = value; 3110 3111 return (0); 3112} 3113 3114static int 3115sysctl_hw_jme_tx_coal_to(SYSCTL_HANDLER_ARGS) 3116{ 3117 return (sysctl_int_range(oidp, arg1, arg2, req, 3118 PCCTX_COAL_TO_MIN, PCCTX_COAL_TO_MAX)); 3119} 3120 3121static int 3122sysctl_hw_jme_tx_coal_pkt(SYSCTL_HANDLER_ARGS) 3123{ 3124 return (sysctl_int_range(oidp, arg1, arg2, req, 3125 PCCTX_COAL_PKT_MIN, PCCTX_COAL_PKT_MAX)); 3126} 3127 3128static int 3129sysctl_hw_jme_rx_coal_to(SYSCTL_HANDLER_ARGS) 3130{ 3131 return (sysctl_int_range(oidp, arg1, arg2, req, 3132 PCCRX_COAL_TO_MIN, PCCRX_COAL_TO_MAX)); 3133} 3134 3135static int 3136sysctl_hw_jme_rx_coal_pkt(SYSCTL_HANDLER_ARGS) 3137{ 3138 return (sysctl_int_range(oidp, arg1, arg2, req, 3139 PCCRX_COAL_PKT_MIN, PCCRX_COAL_PKT_MAX)); 3140} 3141 3142static int 3143sysctl_hw_jme_proc_limit(SYSCTL_HANDLER_ARGS) 3144{ 3145 return (sysctl_int_range(oidp, arg1, arg2, req, 3146 JME_PROC_MIN, JME_PROC_MAX)); 3147} 3148