i40e_adminq_cmd.h revision 299548
1266423Sjfv/****************************************************************************** 2266423Sjfv 3279033Sjfv Copyright (c) 2013-2015, Intel Corporation 4266423Sjfv All rights reserved. 5266423Sjfv 6266423Sjfv Redistribution and use in source and binary forms, with or without 7266423Sjfv modification, are permitted provided that the following conditions are met: 8266423Sjfv 9266423Sjfv 1. Redistributions of source code must retain the above copyright notice, 10266423Sjfv this list of conditions and the following disclaimer. 11266423Sjfv 12266423Sjfv 2. Redistributions in binary form must reproduce the above copyright 13266423Sjfv notice, this list of conditions and the following disclaimer in the 14266423Sjfv documentation and/or other materials provided with the distribution. 15266423Sjfv 16266423Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17266423Sjfv contributors may be used to endorse or promote products derived from 18266423Sjfv this software without specific prior written permission. 19266423Sjfv 20266423Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21266423Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22266423Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23266423Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24266423Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25266423Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26266423Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27266423Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28266423Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29266423Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30266423Sjfv POSSIBILITY OF SUCH DAMAGE. 31266423Sjfv 32266423Sjfv******************************************************************************/ 33266423Sjfv/*$FreeBSD: head/sys/dev/ixl/i40e_adminq_cmd.h 299548 2016-05-12 18:20:18Z erj $*/ 34266423Sjfv 35266423Sjfv#ifndef _I40E_ADMINQ_CMD_H_ 36266423Sjfv#define _I40E_ADMINQ_CMD_H_ 37266423Sjfv 38266423Sjfv/* This header file defines the i40e Admin Queue commands and is shared between 39266423Sjfv * i40e Firmware and Software. 40266423Sjfv * 41266423Sjfv * This file needs to comply with the Linux Kernel coding style. 42266423Sjfv */ 43266423Sjfv 44270346Sjfv#define I40E_FW_API_VERSION_MAJOR 0x0001 45284049Sjfv#define I40E_FW_API_VERSION_MINOR 0x0004 46266423Sjfv 47266423Sjfvstruct i40e_aq_desc { 48266423Sjfv __le16 flags; 49266423Sjfv __le16 opcode; 50266423Sjfv __le16 datalen; 51266423Sjfv __le16 retval; 52266423Sjfv __le32 cookie_high; 53266423Sjfv __le32 cookie_low; 54266423Sjfv union { 55266423Sjfv struct { 56266423Sjfv __le32 param0; 57266423Sjfv __le32 param1; 58266423Sjfv __le32 param2; 59266423Sjfv __le32 param3; 60266423Sjfv } internal; 61266423Sjfv struct { 62266423Sjfv __le32 param0; 63266423Sjfv __le32 param1; 64266423Sjfv __le32 addr_high; 65266423Sjfv __le32 addr_low; 66266423Sjfv } external; 67266423Sjfv u8 raw[16]; 68266423Sjfv } params; 69266423Sjfv}; 70266423Sjfv 71266423Sjfv/* Flags sub-structure 72266423Sjfv * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 73266423Sjfv * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 74266423Sjfv */ 75266423Sjfv 76266423Sjfv/* command flags and offsets*/ 77270346Sjfv#define I40E_AQ_FLAG_DD_SHIFT 0 78270346Sjfv#define I40E_AQ_FLAG_CMP_SHIFT 1 79270346Sjfv#define I40E_AQ_FLAG_ERR_SHIFT 2 80270346Sjfv#define I40E_AQ_FLAG_VFE_SHIFT 3 81270346Sjfv#define I40E_AQ_FLAG_LB_SHIFT 9 82270346Sjfv#define I40E_AQ_FLAG_RD_SHIFT 10 83270346Sjfv#define I40E_AQ_FLAG_VFC_SHIFT 11 84270346Sjfv#define I40E_AQ_FLAG_BUF_SHIFT 12 85270346Sjfv#define I40E_AQ_FLAG_SI_SHIFT 13 86270346Sjfv#define I40E_AQ_FLAG_EI_SHIFT 14 87270346Sjfv#define I40E_AQ_FLAG_FE_SHIFT 15 88266423Sjfv 89270346Sjfv#define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */ 90270346Sjfv#define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */ 91270346Sjfv#define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */ 92270346Sjfv#define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */ 93270346Sjfv#define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */ 94270346Sjfv#define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */ 95270346Sjfv#define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */ 96270346Sjfv#define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ 97270346Sjfv#define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */ 98270346Sjfv#define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */ 99270346Sjfv#define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */ 100266423Sjfv 101266423Sjfv/* error codes */ 102266423Sjfvenum i40e_admin_queue_err { 103270346Sjfv I40E_AQ_RC_OK = 0, /* success */ 104270346Sjfv I40E_AQ_RC_EPERM = 1, /* Operation not permitted */ 105270346Sjfv I40E_AQ_RC_ENOENT = 2, /* No such element */ 106270346Sjfv I40E_AQ_RC_ESRCH = 3, /* Bad opcode */ 107270346Sjfv I40E_AQ_RC_EINTR = 4, /* operation interrupted */ 108270346Sjfv I40E_AQ_RC_EIO = 5, /* I/O error */ 109270346Sjfv I40E_AQ_RC_ENXIO = 6, /* No such resource */ 110270346Sjfv I40E_AQ_RC_E2BIG = 7, /* Arg too long */ 111270346Sjfv I40E_AQ_RC_EAGAIN = 8, /* Try again */ 112270346Sjfv I40E_AQ_RC_ENOMEM = 9, /* Out of memory */ 113270346Sjfv I40E_AQ_RC_EACCES = 10, /* Permission denied */ 114270346Sjfv I40E_AQ_RC_EFAULT = 11, /* Bad address */ 115270346Sjfv I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */ 116270346Sjfv I40E_AQ_RC_EEXIST = 13, /* object already exists */ 117270346Sjfv I40E_AQ_RC_EINVAL = 14, /* Invalid argument */ 118270346Sjfv I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 119270346Sjfv I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */ 120270346Sjfv I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */ 121270346Sjfv I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */ 122270346Sjfv I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 123270346Sjfv I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 124270346Sjfv I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 125270346Sjfv I40E_AQ_RC_EFBIG = 22, /* File too large */ 126266423Sjfv}; 127266423Sjfv 128266423Sjfv/* Admin Queue command opcodes */ 129266423Sjfvenum i40e_admin_queue_opc { 130266423Sjfv /* aq commands */ 131270346Sjfv i40e_aqc_opc_get_version = 0x0001, 132270346Sjfv i40e_aqc_opc_driver_version = 0x0002, 133270346Sjfv i40e_aqc_opc_queue_shutdown = 0x0003, 134270346Sjfv i40e_aqc_opc_set_pf_context = 0x0004, 135266423Sjfv 136266423Sjfv /* resource ownership */ 137270346Sjfv i40e_aqc_opc_request_resource = 0x0008, 138270346Sjfv i40e_aqc_opc_release_resource = 0x0009, 139266423Sjfv 140270346Sjfv i40e_aqc_opc_list_func_capabilities = 0x000A, 141270346Sjfv i40e_aqc_opc_list_dev_capabilities = 0x000B, 142266423Sjfv 143266423Sjfv /* LAA */ 144270346Sjfv i40e_aqc_opc_mac_address_read = 0x0107, 145270346Sjfv i40e_aqc_opc_mac_address_write = 0x0108, 146266423Sjfv 147266423Sjfv /* PXE */ 148270346Sjfv i40e_aqc_opc_clear_pxe_mode = 0x0110, 149266423Sjfv 150266423Sjfv /* internal switch commands */ 151270346Sjfv i40e_aqc_opc_get_switch_config = 0x0200, 152270346Sjfv i40e_aqc_opc_add_statistics = 0x0201, 153270346Sjfv i40e_aqc_opc_remove_statistics = 0x0202, 154270346Sjfv i40e_aqc_opc_set_port_parameters = 0x0203, 155270346Sjfv i40e_aqc_opc_get_switch_resource_alloc = 0x0204, 156266423Sjfv 157270346Sjfv i40e_aqc_opc_add_vsi = 0x0210, 158270346Sjfv i40e_aqc_opc_update_vsi_parameters = 0x0211, 159270346Sjfv i40e_aqc_opc_get_vsi_parameters = 0x0212, 160266423Sjfv 161270346Sjfv i40e_aqc_opc_add_pv = 0x0220, 162270346Sjfv i40e_aqc_opc_update_pv_parameters = 0x0221, 163270346Sjfv i40e_aqc_opc_get_pv_parameters = 0x0222, 164266423Sjfv 165270346Sjfv i40e_aqc_opc_add_veb = 0x0230, 166270346Sjfv i40e_aqc_opc_update_veb_parameters = 0x0231, 167270346Sjfv i40e_aqc_opc_get_veb_parameters = 0x0232, 168266423Sjfv 169270346Sjfv i40e_aqc_opc_delete_element = 0x0243, 170266423Sjfv 171270346Sjfv i40e_aqc_opc_add_macvlan = 0x0250, 172270346Sjfv i40e_aqc_opc_remove_macvlan = 0x0251, 173270346Sjfv i40e_aqc_opc_add_vlan = 0x0252, 174270346Sjfv i40e_aqc_opc_remove_vlan = 0x0253, 175270346Sjfv i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254, 176270346Sjfv i40e_aqc_opc_add_tag = 0x0255, 177270346Sjfv i40e_aqc_opc_remove_tag = 0x0256, 178270346Sjfv i40e_aqc_opc_add_multicast_etag = 0x0257, 179270346Sjfv i40e_aqc_opc_remove_multicast_etag = 0x0258, 180270346Sjfv i40e_aqc_opc_update_tag = 0x0259, 181270346Sjfv i40e_aqc_opc_add_control_packet_filter = 0x025A, 182270346Sjfv i40e_aqc_opc_remove_control_packet_filter = 0x025B, 183270346Sjfv i40e_aqc_opc_add_cloud_filters = 0x025C, 184270346Sjfv i40e_aqc_opc_remove_cloud_filters = 0x025D, 185266423Sjfv 186270346Sjfv i40e_aqc_opc_add_mirror_rule = 0x0260, 187270346Sjfv i40e_aqc_opc_delete_mirror_rule = 0x0261, 188266423Sjfv 189266423Sjfv /* DCB commands */ 190270346Sjfv i40e_aqc_opc_dcb_ignore_pfc = 0x0301, 191270346Sjfv i40e_aqc_opc_dcb_updated = 0x0302, 192266423Sjfv 193266423Sjfv /* TX scheduler */ 194270346Sjfv i40e_aqc_opc_configure_vsi_bw_limit = 0x0400, 195270346Sjfv i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406, 196270346Sjfv i40e_aqc_opc_configure_vsi_tc_bw = 0x0407, 197270346Sjfv i40e_aqc_opc_query_vsi_bw_config = 0x0408, 198270346Sjfv i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A, 199270346Sjfv i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410, 200266423Sjfv 201270346Sjfv i40e_aqc_opc_enable_switching_comp_ets = 0x0413, 202270346Sjfv i40e_aqc_opc_modify_switching_comp_ets = 0x0414, 203270346Sjfv i40e_aqc_opc_disable_switching_comp_ets = 0x0415, 204270346Sjfv i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, 205270346Sjfv i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417, 206270346Sjfv i40e_aqc_opc_query_switching_comp_ets_config = 0x0418, 207270346Sjfv i40e_aqc_opc_query_port_ets_config = 0x0419, 208270346Sjfv i40e_aqc_opc_query_switching_comp_bw_config = 0x041A, 209270346Sjfv i40e_aqc_opc_suspend_port_tx = 0x041B, 210270346Sjfv i40e_aqc_opc_resume_port_tx = 0x041C, 211270346Sjfv i40e_aqc_opc_configure_partition_bw = 0x041D, 212266423Sjfv 213266423Sjfv /* hmc */ 214270346Sjfv i40e_aqc_opc_query_hmc_resource_profile = 0x0500, 215270346Sjfv i40e_aqc_opc_set_hmc_resource_profile = 0x0501, 216266423Sjfv 217266423Sjfv /* phy commands*/ 218270346Sjfv i40e_aqc_opc_get_phy_abilities = 0x0600, 219270346Sjfv i40e_aqc_opc_set_phy_config = 0x0601, 220270346Sjfv i40e_aqc_opc_set_mac_config = 0x0603, 221270346Sjfv i40e_aqc_opc_set_link_restart_an = 0x0605, 222270346Sjfv i40e_aqc_opc_get_link_status = 0x0607, 223270346Sjfv i40e_aqc_opc_set_phy_int_mask = 0x0613, 224270346Sjfv i40e_aqc_opc_get_local_advt_reg = 0x0614, 225270346Sjfv i40e_aqc_opc_set_local_advt_reg = 0x0615, 226270346Sjfv i40e_aqc_opc_get_partner_advt = 0x0616, 227270346Sjfv i40e_aqc_opc_set_lb_modes = 0x0618, 228270346Sjfv i40e_aqc_opc_get_phy_wol_caps = 0x0621, 229270346Sjfv i40e_aqc_opc_set_phy_debug = 0x0622, 230270346Sjfv i40e_aqc_opc_upload_ext_phy_fm = 0x0625, 231266423Sjfv 232266423Sjfv /* NVM commands */ 233270346Sjfv i40e_aqc_opc_nvm_read = 0x0701, 234270346Sjfv i40e_aqc_opc_nvm_erase = 0x0702, 235270346Sjfv i40e_aqc_opc_nvm_update = 0x0703, 236270346Sjfv i40e_aqc_opc_nvm_config_read = 0x0704, 237270346Sjfv i40e_aqc_opc_nvm_config_write = 0x0705, 238284049Sjfv i40e_aqc_opc_oem_post_update = 0x0720, 239266423Sjfv 240266423Sjfv /* virtualization commands */ 241270346Sjfv i40e_aqc_opc_send_msg_to_pf = 0x0801, 242270346Sjfv i40e_aqc_opc_send_msg_to_vf = 0x0802, 243270346Sjfv i40e_aqc_opc_send_msg_to_peer = 0x0803, 244266423Sjfv 245266423Sjfv /* alternate structure */ 246270346Sjfv i40e_aqc_opc_alternate_write = 0x0900, 247270346Sjfv i40e_aqc_opc_alternate_write_indirect = 0x0901, 248270346Sjfv i40e_aqc_opc_alternate_read = 0x0902, 249270346Sjfv i40e_aqc_opc_alternate_read_indirect = 0x0903, 250270346Sjfv i40e_aqc_opc_alternate_write_done = 0x0904, 251270346Sjfv i40e_aqc_opc_alternate_set_mode = 0x0905, 252270346Sjfv i40e_aqc_opc_alternate_clear_port = 0x0906, 253266423Sjfv 254266423Sjfv /* LLDP commands */ 255270346Sjfv i40e_aqc_opc_lldp_get_mib = 0x0A00, 256270346Sjfv i40e_aqc_opc_lldp_update_mib = 0x0A01, 257270346Sjfv i40e_aqc_opc_lldp_add_tlv = 0x0A02, 258270346Sjfv i40e_aqc_opc_lldp_update_tlv = 0x0A03, 259270346Sjfv i40e_aqc_opc_lldp_delete_tlv = 0x0A04, 260270346Sjfv i40e_aqc_opc_lldp_stop = 0x0A05, 261270346Sjfv i40e_aqc_opc_lldp_start = 0x0A06, 262277082Sjfv i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07, 263277082Sjfv i40e_aqc_opc_lldp_set_local_mib = 0x0A08, 264277082Sjfv i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09, 265266423Sjfv 266266423Sjfv /* Tunnel commands */ 267270346Sjfv i40e_aqc_opc_add_udp_tunnel = 0x0B00, 268270346Sjfv i40e_aqc_opc_del_udp_tunnel = 0x0B01, 269266423Sjfv 270266423Sjfv /* Async Events */ 271270346Sjfv i40e_aqc_opc_event_lan_overflow = 0x1001, 272266423Sjfv 273266423Sjfv /* OEM commands */ 274270346Sjfv i40e_aqc_opc_oem_parameter_change = 0xFE00, 275270346Sjfv i40e_aqc_opc_oem_device_status_change = 0xFE01, 276277082Sjfv i40e_aqc_opc_oem_ocsd_initialize = 0xFE02, 277277082Sjfv i40e_aqc_opc_oem_ocbb_initialize = 0xFE03, 278266423Sjfv 279266423Sjfv /* debug commands */ 280270346Sjfv i40e_aqc_opc_debug_read_reg = 0xFF03, 281270346Sjfv i40e_aqc_opc_debug_write_reg = 0xFF04, 282270346Sjfv i40e_aqc_opc_debug_modify_reg = 0xFF07, 283270346Sjfv i40e_aqc_opc_debug_dump_internals = 0xFF08, 284266423Sjfv}; 285266423Sjfv 286266423Sjfv/* command structures and indirect data structures */ 287266423Sjfv 288266423Sjfv/* Structure naming conventions: 289266423Sjfv * - no suffix for direct command descriptor structures 290266423Sjfv * - _data for indirect sent data 291266423Sjfv * - _resp for indirect return data (data which is both will use _data) 292266423Sjfv * - _completion for direct return data 293266423Sjfv * - _element_ for repeated elements (may also be _data or _resp) 294266423Sjfv * 295266423Sjfv * Command structures are expected to overlay the params.raw member of the basic 296266423Sjfv * descriptor, and as such cannot exceed 16 bytes in length. 297266423Sjfv */ 298266423Sjfv 299266423Sjfv/* This macro is used to generate a compilation error if a structure 300266423Sjfv * is not exactly the correct length. It gives a divide by zero error if the 301266423Sjfv * structure is not of the correct size, otherwise it creates an enum that is 302266423Sjfv * never used. 303266423Sjfv */ 304266423Sjfv#define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \ 305266423Sjfv { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) } 306266423Sjfv 307266423Sjfv/* This macro is used extensively to ensure that command structures are 16 308266423Sjfv * bytes in length as they have to map to the raw array of that size. 309266423Sjfv */ 310270346Sjfv#define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X) 311266423Sjfv 312266423Sjfv/* internal (0x00XX) commands */ 313266423Sjfv 314266423Sjfv/* Get version (direct 0x0001) */ 315266423Sjfvstruct i40e_aqc_get_version { 316266423Sjfv __le32 rom_ver; 317266423Sjfv __le32 fw_build; 318266423Sjfv __le16 fw_major; 319266423Sjfv __le16 fw_minor; 320266423Sjfv __le16 api_major; 321266423Sjfv __le16 api_minor; 322266423Sjfv}; 323266423Sjfv 324266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_get_version); 325266423Sjfv 326266423Sjfv/* Send driver version (indirect 0x0002) */ 327266423Sjfvstruct i40e_aqc_driver_version { 328270346Sjfv u8 driver_major_ver; 329270346Sjfv u8 driver_minor_ver; 330270346Sjfv u8 driver_build_ver; 331270346Sjfv u8 driver_subbuild_ver; 332270346Sjfv u8 reserved[4]; 333270346Sjfv __le32 address_high; 334270346Sjfv __le32 address_low; 335266423Sjfv}; 336266423Sjfv 337266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version); 338266423Sjfv 339266423Sjfv/* Queue Shutdown (direct 0x0003) */ 340266423Sjfvstruct i40e_aqc_queue_shutdown { 341270346Sjfv __le32 driver_unloading; 342270346Sjfv#define I40E_AQ_DRIVER_UNLOADING 0x1 343270346Sjfv u8 reserved[12]; 344266423Sjfv}; 345266423Sjfv 346266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); 347266423Sjfv 348266423Sjfv/* Set PF context (0x0004, direct) */ 349266423Sjfvstruct i40e_aqc_set_pf_context { 350266423Sjfv u8 pf_id; 351266423Sjfv u8 reserved[15]; 352266423Sjfv}; 353266423Sjfv 354266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context); 355266423Sjfv 356266423Sjfv/* Request resource ownership (direct 0x0008) 357266423Sjfv * Release resource ownership (direct 0x0009) 358266423Sjfv */ 359270346Sjfv#define I40E_AQ_RESOURCE_NVM 1 360270346Sjfv#define I40E_AQ_RESOURCE_SDP 2 361270346Sjfv#define I40E_AQ_RESOURCE_ACCESS_READ 1 362270346Sjfv#define I40E_AQ_RESOURCE_ACCESS_WRITE 2 363270346Sjfv#define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000 364270346Sjfv#define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000 365266423Sjfv 366266423Sjfvstruct i40e_aqc_request_resource { 367270346Sjfv __le16 resource_id; 368270346Sjfv __le16 access_type; 369270346Sjfv __le32 timeout; 370270346Sjfv __le32 resource_number; 371270346Sjfv u8 reserved[4]; 372266423Sjfv}; 373266423Sjfv 374266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource); 375266423Sjfv 376266423Sjfv/* Get function capabilities (indirect 0x000A) 377266423Sjfv * Get device capabilities (indirect 0x000B) 378266423Sjfv */ 379266423Sjfvstruct i40e_aqc_list_capabilites { 380266423Sjfv u8 command_flags; 381270346Sjfv#define I40E_AQ_LIST_CAP_PF_INDEX_EN 1 382266423Sjfv u8 pf_index; 383266423Sjfv u8 reserved[2]; 384266423Sjfv __le32 count; 385266423Sjfv __le32 addr_high; 386266423Sjfv __le32 addr_low; 387266423Sjfv}; 388266423Sjfv 389266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites); 390266423Sjfv 391266423Sjfvstruct i40e_aqc_list_capabilities_element_resp { 392270346Sjfv __le16 id; 393270346Sjfv u8 major_rev; 394270346Sjfv u8 minor_rev; 395270346Sjfv __le32 number; 396270346Sjfv __le32 logical_id; 397270346Sjfv __le32 phys_id; 398270346Sjfv u8 reserved[16]; 399266423Sjfv}; 400266423Sjfv 401266423Sjfv/* list of caps */ 402266423Sjfv 403270346Sjfv#define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001 404270346Sjfv#define I40E_AQ_CAP_ID_MNG_MODE 0x0002 405270346Sjfv#define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003 406270346Sjfv#define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004 407270346Sjfv#define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005 408270346Sjfv#define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006 409299548Serj#define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008 410270346Sjfv#define I40E_AQ_CAP_ID_SRIOV 0x0012 411270346Sjfv#define I40E_AQ_CAP_ID_VF 0x0013 412270346Sjfv#define I40E_AQ_CAP_ID_VMDQ 0x0014 413270346Sjfv#define I40E_AQ_CAP_ID_8021QBG 0x0015 414270346Sjfv#define I40E_AQ_CAP_ID_8021QBR 0x0016 415270346Sjfv#define I40E_AQ_CAP_ID_VSI 0x0017 416270346Sjfv#define I40E_AQ_CAP_ID_DCB 0x0018 417270346Sjfv#define I40E_AQ_CAP_ID_FCOE 0x0021 418277082Sjfv#define I40E_AQ_CAP_ID_ISCSI 0x0022 419270346Sjfv#define I40E_AQ_CAP_ID_RSS 0x0040 420270346Sjfv#define I40E_AQ_CAP_ID_RXQ 0x0041 421270346Sjfv#define I40E_AQ_CAP_ID_TXQ 0x0042 422270346Sjfv#define I40E_AQ_CAP_ID_MSIX 0x0043 423270346Sjfv#define I40E_AQ_CAP_ID_VF_MSIX 0x0044 424270346Sjfv#define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 425270346Sjfv#define I40E_AQ_CAP_ID_1588 0x0046 426270346Sjfv#define I40E_AQ_CAP_ID_IWARP 0x0051 427270346Sjfv#define I40E_AQ_CAP_ID_LED 0x0061 428270346Sjfv#define I40E_AQ_CAP_ID_SDP 0x0062 429270346Sjfv#define I40E_AQ_CAP_ID_MDIO 0x0063 430299548Serj#define I40E_AQ_CAP_ID_WSR_PROT 0x0064 431270346Sjfv#define I40E_AQ_CAP_ID_FLEX10 0x00F1 432270346Sjfv#define I40E_AQ_CAP_ID_CEM 0x00F2 433266423Sjfv 434266423Sjfv/* Set CPPM Configuration (direct 0x0103) */ 435266423Sjfvstruct i40e_aqc_cppm_configuration { 436270346Sjfv __le16 command_flags; 437270346Sjfv#define I40E_AQ_CPPM_EN_LTRC 0x0800 438270346Sjfv#define I40E_AQ_CPPM_EN_DMCTH 0x1000 439270346Sjfv#define I40E_AQ_CPPM_EN_DMCTLX 0x2000 440270346Sjfv#define I40E_AQ_CPPM_EN_HPTC 0x4000 441270346Sjfv#define I40E_AQ_CPPM_EN_DMARC 0x8000 442270346Sjfv __le16 ttlx; 443270346Sjfv __le32 dmacr; 444270346Sjfv __le16 dmcth; 445270346Sjfv u8 hptc; 446270346Sjfv u8 reserved; 447270346Sjfv __le32 pfltrc; 448266423Sjfv}; 449266423Sjfv 450266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration); 451266423Sjfv 452266423Sjfv/* Set ARP Proxy command / response (indirect 0x0104) */ 453266423Sjfvstruct i40e_aqc_arp_proxy_data { 454270346Sjfv __le16 command_flags; 455270346Sjfv#define I40E_AQ_ARP_INIT_IPV4 0x0008 456270346Sjfv#define I40E_AQ_ARP_UNSUP_CTL 0x0010 457270346Sjfv#define I40E_AQ_ARP_ENA 0x0020 458270346Sjfv#define I40E_AQ_ARP_ADD_IPV4 0x0040 459270346Sjfv#define I40E_AQ_ARP_DEL_IPV4 0x0080 460270346Sjfv __le16 table_id; 461270346Sjfv __le32 pfpm_proxyfc; 462270346Sjfv __le32 ip_addr; 463270346Sjfv u8 mac_addr[6]; 464277082Sjfv u8 reserved[2]; 465266423Sjfv}; 466266423Sjfv 467277082SjfvI40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data); 468277082Sjfv 469266423Sjfv/* Set NS Proxy Table Entry Command (indirect 0x0105) */ 470266423Sjfvstruct i40e_aqc_ns_proxy_data { 471270346Sjfv __le16 table_idx_mac_addr_0; 472270346Sjfv __le16 table_idx_mac_addr_1; 473270346Sjfv __le16 table_idx_ipv6_0; 474270346Sjfv __le16 table_idx_ipv6_1; 475270346Sjfv __le16 control; 476270346Sjfv#define I40E_AQ_NS_PROXY_ADD_0 0x0100 477270346Sjfv#define I40E_AQ_NS_PROXY_DEL_0 0x0200 478270346Sjfv#define I40E_AQ_NS_PROXY_ADD_1 0x0400 479270346Sjfv#define I40E_AQ_NS_PROXY_DEL_1 0x0800 480270346Sjfv#define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x1000 481270346Sjfv#define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x2000 482270346Sjfv#define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x4000 483270346Sjfv#define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x8000 484270346Sjfv#define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0001 485270346Sjfv#define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0002 486270346Sjfv#define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0004 487270346Sjfv u8 mac_addr_0[6]; 488270346Sjfv u8 mac_addr_1[6]; 489270346Sjfv u8 local_mac_addr[6]; 490270346Sjfv u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */ 491270346Sjfv u8 ipv6_addr_1[16]; 492266423Sjfv}; 493266423Sjfv 494277082SjfvI40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data); 495277082Sjfv 496266423Sjfv/* Manage LAA Command (0x0106) - obsolete */ 497266423Sjfvstruct i40e_aqc_mng_laa { 498266423Sjfv __le16 command_flags; 499270346Sjfv#define I40E_AQ_LAA_FLAG_WR 0x8000 500270346Sjfv u8 reserved[2]; 501270346Sjfv __le32 sal; 502270346Sjfv __le16 sah; 503270346Sjfv u8 reserved2[6]; 504266423Sjfv}; 505266423Sjfv 506277082SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa); 507277082Sjfv 508266423Sjfv/* Manage MAC Address Read Command (indirect 0x0107) */ 509266423Sjfvstruct i40e_aqc_mac_address_read { 510266423Sjfv __le16 command_flags; 511270346Sjfv#define I40E_AQC_LAN_ADDR_VALID 0x10 512270346Sjfv#define I40E_AQC_SAN_ADDR_VALID 0x20 513270346Sjfv#define I40E_AQC_PORT_ADDR_VALID 0x40 514270346Sjfv#define I40E_AQC_WOL_ADDR_VALID 0x80 515284049Sjfv#define I40E_AQC_MC_MAG_EN_VALID 0x100 516284049Sjfv#define I40E_AQC_ADDR_VALID_MASK 0x1F0 517270346Sjfv u8 reserved[6]; 518270346Sjfv __le32 addr_high; 519270346Sjfv __le32 addr_low; 520266423Sjfv}; 521266423Sjfv 522266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read); 523266423Sjfv 524266423Sjfvstruct i40e_aqc_mac_address_read_data { 525266423Sjfv u8 pf_lan_mac[6]; 526266423Sjfv u8 pf_san_mac[6]; 527266423Sjfv u8 port_mac[6]; 528266423Sjfv u8 pf_wol_mac[6]; 529266423Sjfv}; 530266423Sjfv 531266423SjfvI40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data); 532266423Sjfv 533266423Sjfv/* Manage MAC Address Write Command (0x0108) */ 534266423Sjfvstruct i40e_aqc_mac_address_write { 535270346Sjfv __le16 command_flags; 536270346Sjfv#define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 537270346Sjfv#define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 538270346Sjfv#define I40E_AQC_WRITE_TYPE_PORT 0x8000 539284049Sjfv#define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000 540284049Sjfv#define I40E_AQC_WRITE_TYPE_MASK 0xC000 541284049Sjfv 542270346Sjfv __le16 mac_sah; 543270346Sjfv __le32 mac_sal; 544270346Sjfv u8 reserved[8]; 545266423Sjfv}; 546266423Sjfv 547266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write); 548266423Sjfv 549266423Sjfv/* PXE commands (0x011x) */ 550266423Sjfv 551266423Sjfv/* Clear PXE Command and response (direct 0x0110) */ 552266423Sjfvstruct i40e_aqc_clear_pxe { 553266423Sjfv u8 rx_cnt; 554266423Sjfv u8 reserved[15]; 555266423Sjfv}; 556266423Sjfv 557266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe); 558266423Sjfv 559266423Sjfv/* Switch configuration commands (0x02xx) */ 560266423Sjfv 561266423Sjfv/* Used by many indirect commands that only pass an seid and a buffer in the 562266423Sjfv * command 563266423Sjfv */ 564266423Sjfvstruct i40e_aqc_switch_seid { 565270346Sjfv __le16 seid; 566270346Sjfv u8 reserved[6]; 567270346Sjfv __le32 addr_high; 568270346Sjfv __le32 addr_low; 569266423Sjfv}; 570266423Sjfv 571266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid); 572266423Sjfv 573266423Sjfv/* Get Switch Configuration command (indirect 0x0200) 574266423Sjfv * uses i40e_aqc_switch_seid for the descriptor 575266423Sjfv */ 576266423Sjfvstruct i40e_aqc_get_switch_config_header_resp { 577270346Sjfv __le16 num_reported; 578270346Sjfv __le16 num_total; 579270346Sjfv u8 reserved[12]; 580266423Sjfv}; 581266423Sjfv 582277082SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp); 583277082Sjfv 584266423Sjfvstruct i40e_aqc_switch_config_element_resp { 585270346Sjfv u8 element_type; 586270346Sjfv#define I40E_AQ_SW_ELEM_TYPE_MAC 1 587270346Sjfv#define I40E_AQ_SW_ELEM_TYPE_PF 2 588270346Sjfv#define I40E_AQ_SW_ELEM_TYPE_VF 3 589270346Sjfv#define I40E_AQ_SW_ELEM_TYPE_EMP 4 590270346Sjfv#define I40E_AQ_SW_ELEM_TYPE_BMC 5 591270346Sjfv#define I40E_AQ_SW_ELEM_TYPE_PV 16 592270346Sjfv#define I40E_AQ_SW_ELEM_TYPE_VEB 17 593270346Sjfv#define I40E_AQ_SW_ELEM_TYPE_PA 18 594270346Sjfv#define I40E_AQ_SW_ELEM_TYPE_VSI 19 595270346Sjfv u8 revision; 596270346Sjfv#define I40E_AQ_SW_ELEM_REV_1 1 597270346Sjfv __le16 seid; 598270346Sjfv __le16 uplink_seid; 599270346Sjfv __le16 downlink_seid; 600270346Sjfv u8 reserved[3]; 601270346Sjfv u8 connection_type; 602270346Sjfv#define I40E_AQ_CONN_TYPE_REGULAR 0x1 603270346Sjfv#define I40E_AQ_CONN_TYPE_DEFAULT 0x2 604270346Sjfv#define I40E_AQ_CONN_TYPE_CASCADED 0x3 605270346Sjfv __le16 scheduler_id; 606270346Sjfv __le16 element_info; 607266423Sjfv}; 608266423Sjfv 609277082SjfvI40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp); 610277082Sjfv 611266423Sjfv/* Get Switch Configuration (indirect 0x0200) 612266423Sjfv * an array of elements are returned in the response buffer 613266423Sjfv * the first in the array is the header, remainder are elements 614266423Sjfv */ 615266423Sjfvstruct i40e_aqc_get_switch_config_resp { 616270346Sjfv struct i40e_aqc_get_switch_config_header_resp header; 617270346Sjfv struct i40e_aqc_switch_config_element_resp element[1]; 618266423Sjfv}; 619266423Sjfv 620277082SjfvI40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp); 621277082Sjfv 622266423Sjfv/* Add Statistics (direct 0x0201) 623266423Sjfv * Remove Statistics (direct 0x0202) 624266423Sjfv */ 625266423Sjfvstruct i40e_aqc_add_remove_statistics { 626270346Sjfv __le16 seid; 627270346Sjfv __le16 vlan; 628270346Sjfv __le16 stat_index; 629270346Sjfv u8 reserved[10]; 630266423Sjfv}; 631266423Sjfv 632266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics); 633266423Sjfv 634266423Sjfv/* Set Port Parameters command (direct 0x0203) */ 635266423Sjfvstruct i40e_aqc_set_port_parameters { 636270346Sjfv __le16 command_flags; 637270346Sjfv#define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1 638270346Sjfv#define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */ 639270346Sjfv#define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4 640270346Sjfv __le16 bad_frame_vsi; 641270346Sjfv __le16 default_seid; /* reserved for command */ 642270346Sjfv u8 reserved[10]; 643266423Sjfv}; 644266423Sjfv 645266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters); 646266423Sjfv 647266423Sjfv/* Get Switch Resource Allocation (indirect 0x0204) */ 648266423Sjfvstruct i40e_aqc_get_switch_resource_alloc { 649270346Sjfv u8 num_entries; /* reserved for command */ 650270346Sjfv u8 reserved[7]; 651270346Sjfv __le32 addr_high; 652270346Sjfv __le32 addr_low; 653266423Sjfv}; 654266423Sjfv 655266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc); 656266423Sjfv 657266423Sjfv/* expect an array of these structs in the response buffer */ 658266423Sjfvstruct i40e_aqc_switch_resource_alloc_element_resp { 659270346Sjfv u8 resource_type; 660270346Sjfv#define I40E_AQ_RESOURCE_TYPE_VEB 0x0 661270346Sjfv#define I40E_AQ_RESOURCE_TYPE_VSI 0x1 662270346Sjfv#define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2 663270346Sjfv#define I40E_AQ_RESOURCE_TYPE_STAG 0x3 664270346Sjfv#define I40E_AQ_RESOURCE_TYPE_ETAG 0x4 665270346Sjfv#define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5 666270346Sjfv#define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6 667270346Sjfv#define I40E_AQ_RESOURCE_TYPE_VLAN 0x7 668270346Sjfv#define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8 669270346Sjfv#define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9 670270346Sjfv#define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA 671270346Sjfv#define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB 672270346Sjfv#define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC 673270346Sjfv#define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD 674270346Sjfv#define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF 675270346Sjfv#define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10 676270346Sjfv#define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11 677270346Sjfv#define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12 678270346Sjfv#define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13 679270346Sjfv u8 reserved1; 680270346Sjfv __le16 guaranteed; 681270346Sjfv __le16 total; 682270346Sjfv __le16 used; 683270346Sjfv __le16 total_unalloced; 684270346Sjfv u8 reserved2[6]; 685266423Sjfv}; 686266423Sjfv 687277082SjfvI40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp); 688277082Sjfv 689266423Sjfv/* Add VSI (indirect 0x0210) 690266423Sjfv * this indirect command uses struct i40e_aqc_vsi_properties_data 691266423Sjfv * as the indirect buffer (128 bytes) 692266423Sjfv * 693266423Sjfv * Update VSI (indirect 0x211) 694266423Sjfv * uses the same data structure as Add VSI 695266423Sjfv * 696266423Sjfv * Get VSI (indirect 0x0212) 697266423Sjfv * uses the same completion and data structure as Add VSI 698266423Sjfv */ 699266423Sjfvstruct i40e_aqc_add_get_update_vsi { 700270346Sjfv __le16 uplink_seid; 701270346Sjfv u8 connection_type; 702270346Sjfv#define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1 703270346Sjfv#define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2 704270346Sjfv#define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3 705270346Sjfv u8 reserved1; 706270346Sjfv u8 vf_id; 707270346Sjfv u8 reserved2; 708270346Sjfv __le16 vsi_flags; 709270346Sjfv#define I40E_AQ_VSI_TYPE_SHIFT 0x0 710270346Sjfv#define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT) 711270346Sjfv#define I40E_AQ_VSI_TYPE_VF 0x0 712270346Sjfv#define I40E_AQ_VSI_TYPE_VMDQ2 0x1 713270346Sjfv#define I40E_AQ_VSI_TYPE_PF 0x2 714270346Sjfv#define I40E_AQ_VSI_TYPE_EMP_MNG 0x3 715270346Sjfv#define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4 716270346Sjfv __le32 addr_high; 717270346Sjfv __le32 addr_low; 718266423Sjfv}; 719266423Sjfv 720266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi); 721266423Sjfv 722266423Sjfvstruct i40e_aqc_add_get_update_vsi_completion { 723266423Sjfv __le16 seid; 724266423Sjfv __le16 vsi_number; 725266423Sjfv __le16 vsi_used; 726266423Sjfv __le16 vsi_free; 727266423Sjfv __le32 addr_high; 728266423Sjfv __le32 addr_low; 729266423Sjfv}; 730266423Sjfv 731266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion); 732266423Sjfv 733266423Sjfvstruct i40e_aqc_vsi_properties_data { 734266423Sjfv /* first 96 byte are written by SW */ 735270346Sjfv __le16 valid_sections; 736270346Sjfv#define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001 737270346Sjfv#define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002 738270346Sjfv#define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004 739270346Sjfv#define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008 740270346Sjfv#define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010 741270346Sjfv#define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020 742270346Sjfv#define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040 743270346Sjfv#define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080 744270346Sjfv#define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100 745270346Sjfv#define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200 746266423Sjfv /* switch section */ 747270346Sjfv __le16 switch_id; /* 12bit id combined with flags below */ 748270346Sjfv#define I40E_AQ_VSI_SW_ID_SHIFT 0x0000 749270346Sjfv#define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT) 750270346Sjfv#define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000 751270346Sjfv#define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000 752270346Sjfv#define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000 753270346Sjfv u8 sw_reserved[2]; 754266423Sjfv /* security section */ 755270346Sjfv u8 sec_flags; 756270346Sjfv#define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01 757270346Sjfv#define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02 758270346Sjfv#define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04 759270346Sjfv u8 sec_reserved; 760266423Sjfv /* VLAN section */ 761270346Sjfv __le16 pvid; /* VLANS include priority bits */ 762270346Sjfv __le16 fcoe_pvid; 763270346Sjfv u8 port_vlan_flags; 764270346Sjfv#define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00 765270346Sjfv#define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ 766270346Sjfv I40E_AQ_VSI_PVLAN_MODE_SHIFT) 767270346Sjfv#define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01 768270346Sjfv#define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02 769270346Sjfv#define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03 770270346Sjfv#define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04 771270346Sjfv#define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03 772270346Sjfv#define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \ 773270346Sjfv I40E_AQ_VSI_PVLAN_EMOD_SHIFT) 774270346Sjfv#define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0 775270346Sjfv#define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08 776270346Sjfv#define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10 777270346Sjfv#define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 778270346Sjfv u8 pvlan_reserved[3]; 779266423Sjfv /* ingress egress up sections */ 780270346Sjfv __le32 ingress_table; /* bitmap, 3 bits per up */ 781270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0 782270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \ 783270346Sjfv I40E_AQ_VSI_UP_TABLE_UP0_SHIFT) 784270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3 785270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \ 786270346Sjfv I40E_AQ_VSI_UP_TABLE_UP1_SHIFT) 787270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6 788270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \ 789270346Sjfv I40E_AQ_VSI_UP_TABLE_UP2_SHIFT) 790270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9 791270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \ 792270346Sjfv I40E_AQ_VSI_UP_TABLE_UP3_SHIFT) 793270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12 794270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \ 795270346Sjfv I40E_AQ_VSI_UP_TABLE_UP4_SHIFT) 796270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15 797270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \ 798270346Sjfv I40E_AQ_VSI_UP_TABLE_UP5_SHIFT) 799270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18 800270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \ 801270346Sjfv I40E_AQ_VSI_UP_TABLE_UP6_SHIFT) 802270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21 803270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \ 804270346Sjfv I40E_AQ_VSI_UP_TABLE_UP7_SHIFT) 805270346Sjfv __le32 egress_table; /* same defines as for ingress table */ 806266423Sjfv /* cascaded PV section */ 807270346Sjfv __le16 cas_pv_tag; 808270346Sjfv u8 cas_pv_flags; 809270346Sjfv#define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00 810270346Sjfv#define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \ 811270346Sjfv I40E_AQ_VSI_CAS_PV_TAGX_SHIFT) 812270346Sjfv#define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00 813270346Sjfv#define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01 814270346Sjfv#define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02 815270346Sjfv#define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10 816270346Sjfv#define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20 817270346Sjfv#define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40 818270346Sjfv u8 cas_pv_reserved; 819266423Sjfv /* queue mapping section */ 820270346Sjfv __le16 mapping_flags; 821270346Sjfv#define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0 822270346Sjfv#define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1 823270346Sjfv __le16 queue_mapping[16]; 824270346Sjfv#define I40E_AQ_VSI_QUEUE_SHIFT 0x0 825270346Sjfv#define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT) 826270346Sjfv __le16 tc_mapping[8]; 827270346Sjfv#define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 828270346Sjfv#define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ 829270346Sjfv I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) 830270346Sjfv#define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 831270346Sjfv#define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ 832270346Sjfv I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT) 833266423Sjfv /* queueing option section */ 834270346Sjfv u8 queueing_opt_flags; 835270346Sjfv#define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10 836270346Sjfv#define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 837270346Sjfv u8 queueing_opt_reserved[3]; 838266423Sjfv /* scheduler section */ 839270346Sjfv u8 up_enable_bits; 840270346Sjfv u8 sched_reserved; 841266423Sjfv /* outer up section */ 842270346Sjfv __le32 outer_up_table; /* same structure and defines as ingress table */ 843270346Sjfv u8 cmd_reserved[8]; 844266423Sjfv /* last 32 bytes are written by FW */ 845270346Sjfv __le16 qs_handle[8]; 846266423Sjfv#define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF 847270346Sjfv __le16 stat_counter_idx; 848270346Sjfv __le16 sched_id; 849270346Sjfv u8 resp_reserved[12]; 850266423Sjfv}; 851266423Sjfv 852266423SjfvI40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data); 853266423Sjfv 854266423Sjfv/* Add Port Virtualizer (direct 0x0220) 855266423Sjfv * also used for update PV (direct 0x0221) but only flags are used 856266423Sjfv * (IS_CTRL_PORT only works on add PV) 857266423Sjfv */ 858266423Sjfvstruct i40e_aqc_add_update_pv { 859270346Sjfv __le16 command_flags; 860270346Sjfv#define I40E_AQC_PV_FLAG_PV_TYPE 0x1 861270346Sjfv#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2 862270346Sjfv#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4 863270346Sjfv#define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8 864270346Sjfv __le16 uplink_seid; 865270346Sjfv __le16 connected_seid; 866270346Sjfv u8 reserved[10]; 867266423Sjfv}; 868266423Sjfv 869266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv); 870266423Sjfv 871266423Sjfvstruct i40e_aqc_add_update_pv_completion { 872266423Sjfv /* reserved for update; for add also encodes error if rc == ENOSPC */ 873270346Sjfv __le16 pv_seid; 874270346Sjfv#define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1 875270346Sjfv#define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2 876270346Sjfv#define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4 877270346Sjfv#define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8 878270346Sjfv u8 reserved[14]; 879266423Sjfv}; 880266423Sjfv 881266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion); 882266423Sjfv 883266423Sjfv/* Get PV Params (direct 0x0222) 884266423Sjfv * uses i40e_aqc_switch_seid for the descriptor 885266423Sjfv */ 886266423Sjfv 887266423Sjfvstruct i40e_aqc_get_pv_params_completion { 888270346Sjfv __le16 seid; 889270346Sjfv __le16 default_stag; 890270346Sjfv __le16 pv_flags; /* same flags as add_pv */ 891270346Sjfv#define I40E_AQC_GET_PV_PV_TYPE 0x1 892270346Sjfv#define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2 893270346Sjfv#define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4 894270346Sjfv u8 reserved[8]; 895270346Sjfv __le16 default_port_seid; 896266423Sjfv}; 897266423Sjfv 898266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion); 899266423Sjfv 900266423Sjfv/* Add VEB (direct 0x0230) */ 901266423Sjfvstruct i40e_aqc_add_veb { 902270346Sjfv __le16 uplink_seid; 903270346Sjfv __le16 downlink_seid; 904270346Sjfv __le16 veb_flags; 905270346Sjfv#define I40E_AQC_ADD_VEB_FLOATING 0x1 906270346Sjfv#define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1 907270346Sjfv#define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \ 908266423Sjfv I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT) 909270346Sjfv#define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2 910270346Sjfv#define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4 911270346Sjfv#define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 912270346Sjfv u8 enable_tcs; 913270346Sjfv u8 reserved[9]; 914266423Sjfv}; 915266423Sjfv 916266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb); 917266423Sjfv 918266423Sjfvstruct i40e_aqc_add_veb_completion { 919270346Sjfv u8 reserved[6]; 920270346Sjfv __le16 switch_seid; 921266423Sjfv /* also encodes error if rc == ENOSPC; codes are the same as add_pv */ 922270346Sjfv __le16 veb_seid; 923270346Sjfv#define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1 924270346Sjfv#define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2 925270346Sjfv#define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4 926270346Sjfv#define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8 927270346Sjfv __le16 statistic_index; 928270346Sjfv __le16 vebs_used; 929270346Sjfv __le16 vebs_free; 930266423Sjfv}; 931266423Sjfv 932266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion); 933266423Sjfv 934266423Sjfv/* Get VEB Parameters (direct 0x0232) 935266423Sjfv * uses i40e_aqc_switch_seid for the descriptor 936266423Sjfv */ 937266423Sjfvstruct i40e_aqc_get_veb_parameters_completion { 938270346Sjfv __le16 seid; 939270346Sjfv __le16 switch_id; 940270346Sjfv __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */ 941270346Sjfv __le16 statistic_index; 942270346Sjfv __le16 vebs_used; 943270346Sjfv __le16 vebs_free; 944270346Sjfv u8 reserved[4]; 945266423Sjfv}; 946266423Sjfv 947266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion); 948266423Sjfv 949266423Sjfv/* Delete Element (direct 0x0243) 950266423Sjfv * uses the generic i40e_aqc_switch_seid 951266423Sjfv */ 952266423Sjfv 953266423Sjfv/* Add MAC-VLAN (indirect 0x0250) */ 954266423Sjfv 955266423Sjfv/* used for the command for most vlan commands */ 956266423Sjfvstruct i40e_aqc_macvlan { 957270346Sjfv __le16 num_addresses; 958270346Sjfv __le16 seid[3]; 959270346Sjfv#define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0 960270346Sjfv#define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \ 961266423Sjfv I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 962270346Sjfv#define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000 963270346Sjfv __le32 addr_high; 964270346Sjfv __le32 addr_low; 965266423Sjfv}; 966266423Sjfv 967266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan); 968266423Sjfv 969266423Sjfv/* indirect data for command and response */ 970266423Sjfvstruct i40e_aqc_add_macvlan_element_data { 971270346Sjfv u8 mac_addr[6]; 972270346Sjfv __le16 vlan_tag; 973270346Sjfv __le16 flags; 974270346Sjfv#define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001 975270346Sjfv#define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002 976270346Sjfv#define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004 977270346Sjfv#define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008 978270346Sjfv __le16 queue_number; 979270346Sjfv#define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0 980270346Sjfv#define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \ 981266423Sjfv I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 982266423Sjfv /* response section */ 983270346Sjfv u8 match_method; 984270346Sjfv#define I40E_AQC_MM_PERFECT_MATCH 0x01 985270346Sjfv#define I40E_AQC_MM_HASH_MATCH 0x02 986270346Sjfv#define I40E_AQC_MM_ERR_NO_RES 0xFF 987270346Sjfv u8 reserved1[3]; 988266423Sjfv}; 989266423Sjfv 990266423Sjfvstruct i40e_aqc_add_remove_macvlan_completion { 991266423Sjfv __le16 perfect_mac_used; 992266423Sjfv __le16 perfect_mac_free; 993266423Sjfv __le16 unicast_hash_free; 994266423Sjfv __le16 multicast_hash_free; 995266423Sjfv __le32 addr_high; 996266423Sjfv __le32 addr_low; 997266423Sjfv}; 998266423Sjfv 999266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion); 1000266423Sjfv 1001266423Sjfv/* Remove MAC-VLAN (indirect 0x0251) 1002266423Sjfv * uses i40e_aqc_macvlan for the descriptor 1003266423Sjfv * data points to an array of num_addresses of elements 1004266423Sjfv */ 1005266423Sjfv 1006266423Sjfvstruct i40e_aqc_remove_macvlan_element_data { 1007270346Sjfv u8 mac_addr[6]; 1008270346Sjfv __le16 vlan_tag; 1009270346Sjfv u8 flags; 1010270346Sjfv#define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01 1011270346Sjfv#define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02 1012270346Sjfv#define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08 1013270346Sjfv#define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10 1014270346Sjfv u8 reserved[3]; 1015266423Sjfv /* reply section */ 1016270346Sjfv u8 error_code; 1017270346Sjfv#define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0 1018270346Sjfv#define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF 1019270346Sjfv u8 reply_reserved[3]; 1020266423Sjfv}; 1021266423Sjfv 1022266423Sjfv/* Add VLAN (indirect 0x0252) 1023266423Sjfv * Remove VLAN (indirect 0x0253) 1024266423Sjfv * use the generic i40e_aqc_macvlan for the command 1025266423Sjfv */ 1026266423Sjfvstruct i40e_aqc_add_remove_vlan_element_data { 1027270346Sjfv __le16 vlan_tag; 1028270346Sjfv u8 vlan_flags; 1029266423Sjfv/* flags for add VLAN */ 1030270346Sjfv#define I40E_AQC_ADD_VLAN_LOCAL 0x1 1031270346Sjfv#define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1 1032270346Sjfv#define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT) 1033270346Sjfv#define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0 1034270346Sjfv#define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2 1035270346Sjfv#define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4 1036270346Sjfv#define I40E_AQC_VLAN_PTYPE_SHIFT 3 1037270346Sjfv#define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT) 1038270346Sjfv#define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0 1039270346Sjfv#define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8 1040270346Sjfv#define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10 1041270346Sjfv#define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18 1042266423Sjfv/* flags for remove VLAN */ 1043270346Sjfv#define I40E_AQC_REMOVE_VLAN_ALL 0x1 1044270346Sjfv u8 reserved; 1045270346Sjfv u8 result; 1046266423Sjfv/* flags for add VLAN */ 1047270346Sjfv#define I40E_AQC_ADD_VLAN_SUCCESS 0x0 1048270346Sjfv#define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE 1049270346Sjfv#define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF 1050266423Sjfv/* flags for remove VLAN */ 1051270346Sjfv#define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0 1052270346Sjfv#define I40E_AQC_REMOVE_VLAN_FAIL 0xFF 1053270346Sjfv u8 reserved1[3]; 1054266423Sjfv}; 1055266423Sjfv 1056266423Sjfvstruct i40e_aqc_add_remove_vlan_completion { 1057270346Sjfv u8 reserved[4]; 1058270346Sjfv __le16 vlans_used; 1059270346Sjfv __le16 vlans_free; 1060270346Sjfv __le32 addr_high; 1061270346Sjfv __le32 addr_low; 1062266423Sjfv}; 1063266423Sjfv 1064266423Sjfv/* Set VSI Promiscuous Modes (direct 0x0254) */ 1065266423Sjfvstruct i40e_aqc_set_vsi_promiscuous_modes { 1066270346Sjfv __le16 promiscuous_flags; 1067270346Sjfv __le16 valid_flags; 1068266423Sjfv/* flags used for both fields above */ 1069270346Sjfv#define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01 1070270346Sjfv#define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02 1071270346Sjfv#define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04 1072270346Sjfv#define I40E_AQC_SET_VSI_DEFAULT 0x08 1073270346Sjfv#define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10 1074270346Sjfv __le16 seid; 1075270346Sjfv#define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF 1076270346Sjfv __le16 vlan_tag; 1077284049Sjfv#define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF 1078270346Sjfv#define I40E_AQC_SET_VSI_VLAN_VALID 0x8000 1079270346Sjfv u8 reserved[8]; 1080266423Sjfv}; 1081266423Sjfv 1082266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes); 1083266423Sjfv 1084266423Sjfv/* Add S/E-tag command (direct 0x0255) 1085266423Sjfv * Uses generic i40e_aqc_add_remove_tag_completion for completion 1086266423Sjfv */ 1087266423Sjfvstruct i40e_aqc_add_tag { 1088270346Sjfv __le16 flags; 1089270346Sjfv#define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001 1090270346Sjfv __le16 seid; 1091270346Sjfv#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0 1092270346Sjfv#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1093266423Sjfv I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT) 1094270346Sjfv __le16 tag; 1095270346Sjfv __le16 queue_number; 1096270346Sjfv u8 reserved[8]; 1097266423Sjfv}; 1098266423Sjfv 1099266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag); 1100266423Sjfv 1101266423Sjfvstruct i40e_aqc_add_remove_tag_completion { 1102270346Sjfv u8 reserved[12]; 1103270346Sjfv __le16 tags_used; 1104270346Sjfv __le16 tags_free; 1105266423Sjfv}; 1106266423Sjfv 1107266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion); 1108266423Sjfv 1109266423Sjfv/* Remove S/E-tag command (direct 0x0256) 1110266423Sjfv * Uses generic i40e_aqc_add_remove_tag_completion for completion 1111266423Sjfv */ 1112266423Sjfvstruct i40e_aqc_remove_tag { 1113270346Sjfv __le16 seid; 1114270346Sjfv#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0 1115270346Sjfv#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1116266423Sjfv I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT) 1117270346Sjfv __le16 tag; 1118270346Sjfv u8 reserved[12]; 1119266423Sjfv}; 1120266423Sjfv 1121277082SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag); 1122277082Sjfv 1123266423Sjfv/* Add multicast E-Tag (direct 0x0257) 1124266423Sjfv * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields 1125266423Sjfv * and no external data 1126266423Sjfv */ 1127266423Sjfvstruct i40e_aqc_add_remove_mcast_etag { 1128270346Sjfv __le16 pv_seid; 1129270346Sjfv __le16 etag; 1130270346Sjfv u8 num_unicast_etags; 1131270346Sjfv u8 reserved[3]; 1132270346Sjfv __le32 addr_high; /* address of array of 2-byte s-tags */ 1133270346Sjfv __le32 addr_low; 1134266423Sjfv}; 1135266423Sjfv 1136266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag); 1137266423Sjfv 1138266423Sjfvstruct i40e_aqc_add_remove_mcast_etag_completion { 1139270346Sjfv u8 reserved[4]; 1140270346Sjfv __le16 mcast_etags_used; 1141270346Sjfv __le16 mcast_etags_free; 1142270346Sjfv __le32 addr_high; 1143270346Sjfv __le32 addr_low; 1144266423Sjfv 1145266423Sjfv}; 1146266423Sjfv 1147266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion); 1148266423Sjfv 1149266423Sjfv/* Update S/E-Tag (direct 0x0259) */ 1150266423Sjfvstruct i40e_aqc_update_tag { 1151270346Sjfv __le16 seid; 1152270346Sjfv#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0 1153270346Sjfv#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1154266423Sjfv I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT) 1155270346Sjfv __le16 old_tag; 1156270346Sjfv __le16 new_tag; 1157270346Sjfv u8 reserved[10]; 1158266423Sjfv}; 1159266423Sjfv 1160266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag); 1161266423Sjfv 1162266423Sjfvstruct i40e_aqc_update_tag_completion { 1163270346Sjfv u8 reserved[12]; 1164270346Sjfv __le16 tags_used; 1165270346Sjfv __le16 tags_free; 1166266423Sjfv}; 1167266423Sjfv 1168266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion); 1169266423Sjfv 1170266423Sjfv/* Add Control Packet filter (direct 0x025A) 1171266423Sjfv * Remove Control Packet filter (direct 0x025B) 1172266423Sjfv * uses the i40e_aqc_add_oveb_cloud, 1173266423Sjfv * and the generic direct completion structure 1174266423Sjfv */ 1175266423Sjfvstruct i40e_aqc_add_remove_control_packet_filter { 1176270346Sjfv u8 mac[6]; 1177270346Sjfv __le16 etype; 1178270346Sjfv __le16 flags; 1179270346Sjfv#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001 1180270346Sjfv#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002 1181270346Sjfv#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004 1182270346Sjfv#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008 1183270346Sjfv#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000 1184270346Sjfv __le16 seid; 1185270346Sjfv#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0 1186270346Sjfv#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \ 1187266423Sjfv I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT) 1188270346Sjfv __le16 queue; 1189270346Sjfv u8 reserved[2]; 1190266423Sjfv}; 1191266423Sjfv 1192266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter); 1193266423Sjfv 1194266423Sjfvstruct i40e_aqc_add_remove_control_packet_filter_completion { 1195270346Sjfv __le16 mac_etype_used; 1196270346Sjfv __le16 etype_used; 1197270346Sjfv __le16 mac_etype_free; 1198270346Sjfv __le16 etype_free; 1199270346Sjfv u8 reserved[8]; 1200266423Sjfv}; 1201266423Sjfv 1202266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion); 1203266423Sjfv 1204266423Sjfv/* Add Cloud filters (indirect 0x025C) 1205266423Sjfv * Remove Cloud filters (indirect 0x025D) 1206266423Sjfv * uses the i40e_aqc_add_remove_cloud_filters, 1207266423Sjfv * and the generic indirect completion structure 1208266423Sjfv */ 1209266423Sjfvstruct i40e_aqc_add_remove_cloud_filters { 1210270346Sjfv u8 num_filters; 1211270346Sjfv u8 reserved; 1212270346Sjfv __le16 seid; 1213270346Sjfv#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0 1214270346Sjfv#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \ 1215266423Sjfv I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT) 1216270346Sjfv u8 reserved2[4]; 1217270346Sjfv __le32 addr_high; 1218270346Sjfv __le32 addr_low; 1219266423Sjfv}; 1220266423Sjfv 1221266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters); 1222266423Sjfv 1223266423Sjfvstruct i40e_aqc_add_remove_cloud_filters_element_data { 1224270346Sjfv u8 outer_mac[6]; 1225270346Sjfv u8 inner_mac[6]; 1226270346Sjfv __le16 inner_vlan; 1227266423Sjfv union { 1228266423Sjfv struct { 1229266423Sjfv u8 reserved[12]; 1230266423Sjfv u8 data[4]; 1231266423Sjfv } v4; 1232266423Sjfv struct { 1233266423Sjfv u8 data[16]; 1234266423Sjfv } v6; 1235266423Sjfv } ipaddr; 1236270346Sjfv __le16 flags; 1237270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0 1238277082Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \ 1239266423Sjfv I40E_AQC_ADD_CLOUD_FILTER_SHIFT) 1240266423Sjfv/* 0x0000 reserved */ 1241270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001 1242266423Sjfv/* 0x0002 reserved */ 1243270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003 1244270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004 1245266423Sjfv/* 0x0005 reserved */ 1246270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006 1247266423Sjfv/* 0x0007 reserved */ 1248266423Sjfv/* 0x0008 reserved */ 1249270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009 1250270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A 1251270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B 1252270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C 1253266423Sjfv 1254270346Sjfv#define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080 1255270346Sjfv#define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6 1256270346Sjfv#define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0 1257270346Sjfv#define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0 1258270346Sjfv#define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100 1259266423Sjfv 1260270346Sjfv#define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9 1261270346Sjfv#define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00 1262270346Sjfv#define I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN 0 1263270346Sjfv#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1 1264270346Sjfv#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NGE 2 1265270346Sjfv#define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3 1266266423Sjfv 1267270346Sjfv __le32 tenant_id; 1268270346Sjfv u8 reserved[4]; 1269270346Sjfv __le16 queue_number; 1270270346Sjfv#define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0 1271277082Sjfv#define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \ 1272270346Sjfv I40E_AQC_ADD_CLOUD_QUEUE_SHIFT) 1273270346Sjfv u8 reserved2[14]; 1274266423Sjfv /* response section */ 1275270346Sjfv u8 allocation_result; 1276270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0 1277270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF 1278270346Sjfv u8 response_reserved[7]; 1279266423Sjfv}; 1280266423Sjfv 1281266423Sjfvstruct i40e_aqc_remove_cloud_filters_completion { 1282266423Sjfv __le16 perfect_ovlan_used; 1283266423Sjfv __le16 perfect_ovlan_free; 1284266423Sjfv __le16 vlan_used; 1285266423Sjfv __le16 vlan_free; 1286266423Sjfv __le32 addr_high; 1287266423Sjfv __le32 addr_low; 1288266423Sjfv}; 1289266423Sjfv 1290266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion); 1291266423Sjfv 1292266423Sjfv/* Add Mirror Rule (indirect or direct 0x0260) 1293266423Sjfv * Delete Mirror Rule (indirect or direct 0x0261) 1294266423Sjfv * note: some rule types (4,5) do not use an external buffer. 1295266423Sjfv * take care to set the flags correctly. 1296266423Sjfv */ 1297266423Sjfvstruct i40e_aqc_add_delete_mirror_rule { 1298266423Sjfv __le16 seid; 1299266423Sjfv __le16 rule_type; 1300270346Sjfv#define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0 1301270346Sjfv#define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \ 1302266423Sjfv I40E_AQC_MIRROR_RULE_TYPE_SHIFT) 1303270346Sjfv#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1 1304270346Sjfv#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2 1305270346Sjfv#define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3 1306270346Sjfv#define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4 1307270346Sjfv#define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5 1308266423Sjfv __le16 num_entries; 1309266423Sjfv __le16 destination; /* VSI for add, rule id for delete */ 1310266423Sjfv __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */ 1311266423Sjfv __le32 addr_low; 1312266423Sjfv}; 1313266423Sjfv 1314266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule); 1315266423Sjfv 1316266423Sjfvstruct i40e_aqc_add_delete_mirror_rule_completion { 1317270346Sjfv u8 reserved[2]; 1318270346Sjfv __le16 rule_id; /* only used on add */ 1319270346Sjfv __le16 mirror_rules_used; 1320270346Sjfv __le16 mirror_rules_free; 1321270346Sjfv __le32 addr_high; 1322270346Sjfv __le32 addr_low; 1323266423Sjfv}; 1324266423Sjfv 1325266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion); 1326266423Sjfv 1327266423Sjfv/* DCB 0x03xx*/ 1328266423Sjfv 1329266423Sjfv/* PFC Ignore (direct 0x0301) 1330266423Sjfv * the command and response use the same descriptor structure 1331266423Sjfv */ 1332266423Sjfvstruct i40e_aqc_pfc_ignore { 1333270346Sjfv u8 tc_bitmap; 1334270346Sjfv u8 command_flags; /* unused on response */ 1335270346Sjfv#define I40E_AQC_PFC_IGNORE_SET 0x80 1336270346Sjfv#define I40E_AQC_PFC_IGNORE_CLEAR 0x0 1337270346Sjfv u8 reserved[14]; 1338266423Sjfv}; 1339266423Sjfv 1340266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore); 1341266423Sjfv 1342266423Sjfv/* DCB Update (direct 0x0302) uses the i40e_aq_desc structure 1343266423Sjfv * with no parameters 1344266423Sjfv */ 1345266423Sjfv 1346266423Sjfv/* TX scheduler 0x04xx */ 1347266423Sjfv 1348266423Sjfv/* Almost all the indirect commands use 1349266423Sjfv * this generic struct to pass the SEID in param0 1350266423Sjfv */ 1351266423Sjfvstruct i40e_aqc_tx_sched_ind { 1352270346Sjfv __le16 vsi_seid; 1353270346Sjfv u8 reserved[6]; 1354270346Sjfv __le32 addr_high; 1355270346Sjfv __le32 addr_low; 1356266423Sjfv}; 1357266423Sjfv 1358266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind); 1359266423Sjfv 1360266423Sjfv/* Several commands respond with a set of queue set handles */ 1361266423Sjfvstruct i40e_aqc_qs_handles_resp { 1362266423Sjfv __le16 qs_handles[8]; 1363266423Sjfv}; 1364266423Sjfv 1365266423Sjfv/* Configure VSI BW limits (direct 0x0400) */ 1366266423Sjfvstruct i40e_aqc_configure_vsi_bw_limit { 1367270346Sjfv __le16 vsi_seid; 1368270346Sjfv u8 reserved[2]; 1369270346Sjfv __le16 credit; 1370270346Sjfv u8 reserved1[2]; 1371270346Sjfv u8 max_credit; /* 0-3, limit = 2^max */ 1372270346Sjfv u8 reserved2[7]; 1373266423Sjfv}; 1374266423Sjfv 1375266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit); 1376266423Sjfv 1377266423Sjfv/* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406) 1378266423Sjfv * responds with i40e_aqc_qs_handles_resp 1379266423Sjfv */ 1380266423Sjfvstruct i40e_aqc_configure_vsi_ets_sla_bw_data { 1381270346Sjfv u8 tc_valid_bits; 1382270346Sjfv u8 reserved[15]; 1383270346Sjfv __le16 tc_bw_credits[8]; /* FW writesback QS handles here */ 1384266423Sjfv 1385266423Sjfv /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1386270346Sjfv __le16 tc_bw_max[2]; 1387270346Sjfv u8 reserved1[28]; 1388266423Sjfv}; 1389266423Sjfv 1390277082SjfvI40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data); 1391277082Sjfv 1392266423Sjfv/* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407) 1393266423Sjfv * responds with i40e_aqc_qs_handles_resp 1394266423Sjfv */ 1395266423Sjfvstruct i40e_aqc_configure_vsi_tc_bw_data { 1396270346Sjfv u8 tc_valid_bits; 1397270346Sjfv u8 reserved[3]; 1398270346Sjfv u8 tc_bw_credits[8]; 1399270346Sjfv u8 reserved1[4]; 1400270346Sjfv __le16 qs_handles[8]; 1401266423Sjfv}; 1402266423Sjfv 1403277082SjfvI40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data); 1404277082Sjfv 1405266423Sjfv/* Query vsi bw configuration (indirect 0x0408) */ 1406266423Sjfvstruct i40e_aqc_query_vsi_bw_config_resp { 1407270346Sjfv u8 tc_valid_bits; 1408270346Sjfv u8 tc_suspended_bits; 1409270346Sjfv u8 reserved[14]; 1410270346Sjfv __le16 qs_handles[8]; 1411270346Sjfv u8 reserved1[4]; 1412270346Sjfv __le16 port_bw_limit; 1413270346Sjfv u8 reserved2[2]; 1414270346Sjfv u8 max_bw; /* 0-3, limit = 2^max */ 1415270346Sjfv u8 reserved3[23]; 1416266423Sjfv}; 1417266423Sjfv 1418277082SjfvI40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp); 1419277082Sjfv 1420266423Sjfv/* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */ 1421266423Sjfvstruct i40e_aqc_query_vsi_ets_sla_config_resp { 1422270346Sjfv u8 tc_valid_bits; 1423270346Sjfv u8 reserved[3]; 1424270346Sjfv u8 share_credits[8]; 1425270346Sjfv __le16 credits[8]; 1426266423Sjfv 1427266423Sjfv /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1428270346Sjfv __le16 tc_bw_max[2]; 1429266423Sjfv}; 1430266423Sjfv 1431277082SjfvI40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp); 1432277082Sjfv 1433266423Sjfv/* Configure Switching Component Bandwidth Limit (direct 0x0410) */ 1434266423Sjfvstruct i40e_aqc_configure_switching_comp_bw_limit { 1435270346Sjfv __le16 seid; 1436270346Sjfv u8 reserved[2]; 1437270346Sjfv __le16 credit; 1438270346Sjfv u8 reserved1[2]; 1439270346Sjfv u8 max_bw; /* 0-3, limit = 2^max */ 1440270346Sjfv u8 reserved2[7]; 1441266423Sjfv}; 1442266423Sjfv 1443266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit); 1444266423Sjfv 1445266423Sjfv/* Enable Physical Port ETS (indirect 0x0413) 1446266423Sjfv * Modify Physical Port ETS (indirect 0x0414) 1447266423Sjfv * Disable Physical Port ETS (indirect 0x0415) 1448266423Sjfv */ 1449266423Sjfvstruct i40e_aqc_configure_switching_comp_ets_data { 1450270346Sjfv u8 reserved[4]; 1451270346Sjfv u8 tc_valid_bits; 1452270346Sjfv u8 seepage; 1453270346Sjfv#define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1 1454270346Sjfv u8 tc_strict_priority_flags; 1455270346Sjfv u8 reserved1[17]; 1456270346Sjfv u8 tc_bw_share_credits[8]; 1457270346Sjfv u8 reserved2[96]; 1458266423Sjfv}; 1459266423Sjfv 1460277082SjfvI40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data); 1461277082Sjfv 1462266423Sjfv/* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ 1463266423Sjfvstruct i40e_aqc_configure_switching_comp_ets_bw_limit_data { 1464270346Sjfv u8 tc_valid_bits; 1465270346Sjfv u8 reserved[15]; 1466270346Sjfv __le16 tc_bw_credit[8]; 1467266423Sjfv 1468266423Sjfv /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1469270346Sjfv __le16 tc_bw_max[2]; 1470270346Sjfv u8 reserved1[28]; 1471266423Sjfv}; 1472266423Sjfv 1473277082SjfvI40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_switching_comp_ets_bw_limit_data); 1474277082Sjfv 1475266423Sjfv/* Configure Switching Component Bandwidth Allocation per Tc 1476266423Sjfv * (indirect 0x0417) 1477266423Sjfv */ 1478266423Sjfvstruct i40e_aqc_configure_switching_comp_bw_config_data { 1479270346Sjfv u8 tc_valid_bits; 1480270346Sjfv u8 reserved[2]; 1481270346Sjfv u8 absolute_credits; /* bool */ 1482270346Sjfv u8 tc_bw_share_credits[8]; 1483270346Sjfv u8 reserved1[20]; 1484266423Sjfv}; 1485266423Sjfv 1486277082SjfvI40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data); 1487277082Sjfv 1488266423Sjfv/* Query Switching Component Configuration (indirect 0x0418) */ 1489266423Sjfvstruct i40e_aqc_query_switching_comp_ets_config_resp { 1490270346Sjfv u8 tc_valid_bits; 1491270346Sjfv u8 reserved[35]; 1492270346Sjfv __le16 port_bw_limit; 1493270346Sjfv u8 reserved1[2]; 1494270346Sjfv u8 tc_bw_max; /* 0-3, limit = 2^max */ 1495270346Sjfv u8 reserved2[23]; 1496266423Sjfv}; 1497266423Sjfv 1498277082SjfvI40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp); 1499277082Sjfv 1500266423Sjfv/* Query PhysicalPort ETS Configuration (indirect 0x0419) */ 1501266423Sjfvstruct i40e_aqc_query_port_ets_config_resp { 1502270346Sjfv u8 reserved[4]; 1503270346Sjfv u8 tc_valid_bits; 1504270346Sjfv u8 reserved1; 1505270346Sjfv u8 tc_strict_priority_bits; 1506270346Sjfv u8 reserved2; 1507270346Sjfv u8 tc_bw_share_credits[8]; 1508270346Sjfv __le16 tc_bw_limits[8]; 1509266423Sjfv 1510266423Sjfv /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */ 1511270346Sjfv __le16 tc_bw_max[2]; 1512270346Sjfv u8 reserved3[32]; 1513266423Sjfv}; 1514266423Sjfv 1515277082SjfvI40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp); 1516277082Sjfv 1517266423Sjfv/* Query Switching Component Bandwidth Allocation per Traffic Type 1518266423Sjfv * (indirect 0x041A) 1519266423Sjfv */ 1520266423Sjfvstruct i40e_aqc_query_switching_comp_bw_config_resp { 1521270346Sjfv u8 tc_valid_bits; 1522270346Sjfv u8 reserved[2]; 1523270346Sjfv u8 absolute_credits_enable; /* bool */ 1524270346Sjfv u8 tc_bw_share_credits[8]; 1525270346Sjfv __le16 tc_bw_limits[8]; 1526266423Sjfv 1527266423Sjfv /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1528270346Sjfv __le16 tc_bw_max[2]; 1529266423Sjfv}; 1530266423Sjfv 1531277082SjfvI40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp); 1532277082Sjfv 1533266423Sjfv/* Suspend/resume port TX traffic 1534266423Sjfv * (direct 0x041B and 0x041C) uses the generic SEID struct 1535266423Sjfv */ 1536266423Sjfv 1537266423Sjfv/* Configure partition BW 1538266423Sjfv * (indirect 0x041D) 1539266423Sjfv */ 1540266423Sjfvstruct i40e_aqc_configure_partition_bw_data { 1541270346Sjfv __le16 pf_valid_bits; 1542270346Sjfv u8 min_bw[16]; /* guaranteed bandwidth */ 1543270346Sjfv u8 max_bw[16]; /* bandwidth limit */ 1544266423Sjfv}; 1545266423Sjfv 1546277082SjfvI40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data); 1547277082Sjfv 1548266423Sjfv/* Get and set the active HMC resource profile and status. 1549266423Sjfv * (direct 0x0500) and (direct 0x0501) 1550266423Sjfv */ 1551266423Sjfvstruct i40e_aq_get_set_hmc_resource_profile { 1552270346Sjfv u8 pm_profile; 1553270346Sjfv u8 pe_vf_enabled; 1554270346Sjfv u8 reserved[14]; 1555266423Sjfv}; 1556266423Sjfv 1557266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile); 1558266423Sjfv 1559266423Sjfvenum i40e_aq_hmc_profile { 1560266423Sjfv /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */ 1561270346Sjfv I40E_HMC_PROFILE_DEFAULT = 1, 1562270346Sjfv I40E_HMC_PROFILE_FAVOR_VF = 2, 1563270346Sjfv I40E_HMC_PROFILE_EQUAL = 3, 1564266423Sjfv}; 1565266423Sjfv 1566270346Sjfv#define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK 0xF 1567270346Sjfv#define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK 0x3F 1568266423Sjfv 1569266423Sjfv/* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */ 1570266423Sjfv 1571266423Sjfv/* set in param0 for get phy abilities to report qualified modules */ 1572270346Sjfv#define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001 1573270346Sjfv#define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002 1574266423Sjfv 1575266423Sjfvenum i40e_aq_phy_type { 1576266423Sjfv I40E_PHY_TYPE_SGMII = 0x0, 1577266423Sjfv I40E_PHY_TYPE_1000BASE_KX = 0x1, 1578266423Sjfv I40E_PHY_TYPE_10GBASE_KX4 = 0x2, 1579266423Sjfv I40E_PHY_TYPE_10GBASE_KR = 0x3, 1580266423Sjfv I40E_PHY_TYPE_40GBASE_KR4 = 0x4, 1581266423Sjfv I40E_PHY_TYPE_XAUI = 0x5, 1582266423Sjfv I40E_PHY_TYPE_XFI = 0x6, 1583266423Sjfv I40E_PHY_TYPE_SFI = 0x7, 1584266423Sjfv I40E_PHY_TYPE_XLAUI = 0x8, 1585266423Sjfv I40E_PHY_TYPE_XLPPI = 0x9, 1586266423Sjfv I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA, 1587266423Sjfv I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB, 1588266423Sjfv I40E_PHY_TYPE_10GBASE_AOC = 0xC, 1589266423Sjfv I40E_PHY_TYPE_40GBASE_AOC = 0xD, 1590266423Sjfv I40E_PHY_TYPE_100BASE_TX = 0x11, 1591266423Sjfv I40E_PHY_TYPE_1000BASE_T = 0x12, 1592266423Sjfv I40E_PHY_TYPE_10GBASE_T = 0x13, 1593266423Sjfv I40E_PHY_TYPE_10GBASE_SR = 0x14, 1594266423Sjfv I40E_PHY_TYPE_10GBASE_LR = 0x15, 1595266423Sjfv I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16, 1596266423Sjfv I40E_PHY_TYPE_10GBASE_CR1 = 0x17, 1597266423Sjfv I40E_PHY_TYPE_40GBASE_CR4 = 0x18, 1598266423Sjfv I40E_PHY_TYPE_40GBASE_SR4 = 0x19, 1599266423Sjfv I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, 1600266423Sjfv I40E_PHY_TYPE_1000BASE_SX = 0x1B, 1601266423Sjfv I40E_PHY_TYPE_1000BASE_LX = 0x1C, 1602266423Sjfv I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, 1603266423Sjfv I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, 1604266423Sjfv I40E_PHY_TYPE_MAX 1605266423Sjfv}; 1606266423Sjfv 1607266423Sjfv#define I40E_LINK_SPEED_100MB_SHIFT 0x1 1608266423Sjfv#define I40E_LINK_SPEED_1000MB_SHIFT 0x2 1609266423Sjfv#define I40E_LINK_SPEED_10GB_SHIFT 0x3 1610266423Sjfv#define I40E_LINK_SPEED_40GB_SHIFT 0x4 1611266423Sjfv#define I40E_LINK_SPEED_20GB_SHIFT 0x5 1612266423Sjfv 1613266423Sjfvenum i40e_aq_link_speed { 1614266423Sjfv I40E_LINK_SPEED_UNKNOWN = 0, 1615266423Sjfv I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT), 1616266423Sjfv I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT), 1617266423Sjfv I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT), 1618266423Sjfv I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT), 1619266423Sjfv I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT) 1620266423Sjfv}; 1621266423Sjfv 1622266423Sjfvstruct i40e_aqc_module_desc { 1623266423Sjfv u8 oui[3]; 1624266423Sjfv u8 reserved1; 1625266423Sjfv u8 part_number[16]; 1626266423Sjfv u8 revision[4]; 1627266423Sjfv u8 reserved2[8]; 1628266423Sjfv}; 1629266423Sjfv 1630277082SjfvI40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc); 1631277082Sjfv 1632266423Sjfvstruct i40e_aq_get_phy_abilities_resp { 1633270346Sjfv __le32 phy_type; /* bitmap using the above enum for offsets */ 1634270346Sjfv u8 link_speed; /* bitmap using the above enum bit patterns */ 1635270346Sjfv u8 abilities; 1636270346Sjfv#define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01 1637270346Sjfv#define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02 1638270346Sjfv#define I40E_AQ_PHY_FLAG_LOW_POWER 0x04 1639270346Sjfv#define I40E_AQ_PHY_LINK_ENABLED 0x08 1640270346Sjfv#define I40E_AQ_PHY_AN_ENABLED 0x10 1641270346Sjfv#define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20 1642270346Sjfv __le16 eee_capability; 1643270346Sjfv#define I40E_AQ_EEE_100BASE_TX 0x0002 1644270346Sjfv#define I40E_AQ_EEE_1000BASE_T 0x0004 1645270346Sjfv#define I40E_AQ_EEE_10GBASE_T 0x0008 1646270346Sjfv#define I40E_AQ_EEE_1000BASE_KX 0x0010 1647270346Sjfv#define I40E_AQ_EEE_10GBASE_KX4 0x0020 1648270346Sjfv#define I40E_AQ_EEE_10GBASE_KR 0x0040 1649270346Sjfv __le32 eeer_val; 1650270346Sjfv u8 d3_lpan; 1651270346Sjfv#define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 1652270346Sjfv u8 reserved[3]; 1653270346Sjfv u8 phy_id[4]; 1654270346Sjfv u8 module_type[3]; 1655270346Sjfv u8 qualified_module_count; 1656270346Sjfv#define I40E_AQ_PHY_MAX_QMS 16 1657270346Sjfv struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; 1658266423Sjfv}; 1659266423Sjfv 1660277082SjfvI40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp); 1661277082Sjfv 1662266423Sjfv/* Set PHY Config (direct 0x0601) */ 1663266423Sjfvstruct i40e_aq_set_phy_config { /* same bits as above in all */ 1664270346Sjfv __le32 phy_type; 1665270346Sjfv u8 link_speed; 1666270346Sjfv u8 abilities; 1667266423Sjfv/* bits 0-2 use the values from get_phy_abilities_resp */ 1668266423Sjfv#define I40E_AQ_PHY_ENABLE_LINK 0x08 1669266423Sjfv#define I40E_AQ_PHY_ENABLE_AN 0x10 1670266423Sjfv#define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20 1671270346Sjfv __le16 eee_capability; 1672270346Sjfv __le32 eeer; 1673270346Sjfv u8 low_power_ctrl; 1674270346Sjfv u8 reserved[3]; 1675266423Sjfv}; 1676266423Sjfv 1677266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); 1678266423Sjfv 1679266423Sjfv/* Set MAC Config command data structure (direct 0x0603) */ 1680266423Sjfvstruct i40e_aq_set_mac_config { 1681270346Sjfv __le16 max_frame_size; 1682270346Sjfv u8 params; 1683270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04 1684270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78 1685270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3 1686270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0 1687270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF 1688270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9 1689270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8 1690270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7 1691270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6 1692270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5 1693270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4 1694270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3 1695270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2 1696270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1 1697270346Sjfv u8 tx_timer_priority; /* bitmap */ 1698270346Sjfv __le16 tx_timer_value; 1699270346Sjfv __le16 fc_refresh_threshold; 1700270346Sjfv u8 reserved[8]; 1701266423Sjfv}; 1702266423Sjfv 1703266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config); 1704266423Sjfv 1705266423Sjfv/* Restart Auto-Negotiation (direct 0x605) */ 1706266423Sjfvstruct i40e_aqc_set_link_restart_an { 1707270346Sjfv u8 command; 1708270346Sjfv#define I40E_AQ_PHY_RESTART_AN 0x02 1709270346Sjfv#define I40E_AQ_PHY_LINK_ENABLE 0x04 1710270346Sjfv u8 reserved[15]; 1711266423Sjfv}; 1712266423Sjfv 1713266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an); 1714266423Sjfv 1715266423Sjfv/* Get Link Status cmd & response data structure (direct 0x0607) */ 1716266423Sjfvstruct i40e_aqc_get_link_status { 1717270346Sjfv __le16 command_flags; /* only field set on command */ 1718270346Sjfv#define I40E_AQ_LSE_MASK 0x3 1719270346Sjfv#define I40E_AQ_LSE_NOP 0x0 1720270346Sjfv#define I40E_AQ_LSE_DISABLE 0x2 1721270346Sjfv#define I40E_AQ_LSE_ENABLE 0x3 1722266423Sjfv/* only response uses this flag */ 1723270346Sjfv#define I40E_AQ_LSE_IS_ENABLED 0x1 1724270346Sjfv u8 phy_type; /* i40e_aq_phy_type */ 1725270346Sjfv u8 link_speed; /* i40e_aq_link_speed */ 1726270346Sjfv u8 link_info; 1727284049Sjfv#define I40E_AQ_LINK_UP 0x01 /* obsolete */ 1728284049Sjfv#define I40E_AQ_LINK_UP_FUNCTION 0x01 1729270346Sjfv#define I40E_AQ_LINK_FAULT 0x02 1730270346Sjfv#define I40E_AQ_LINK_FAULT_TX 0x04 1731270346Sjfv#define I40E_AQ_LINK_FAULT_RX 0x08 1732270346Sjfv#define I40E_AQ_LINK_FAULT_REMOTE 0x10 1733284049Sjfv#define I40E_AQ_LINK_UP_PORT 0x20 1734270346Sjfv#define I40E_AQ_MEDIA_AVAILABLE 0x40 1735270346Sjfv#define I40E_AQ_SIGNAL_DETECT 0x80 1736270346Sjfv u8 an_info; 1737270346Sjfv#define I40E_AQ_AN_COMPLETED 0x01 1738270346Sjfv#define I40E_AQ_LP_AN_ABILITY 0x02 1739270346Sjfv#define I40E_AQ_PD_FAULT 0x04 1740270346Sjfv#define I40E_AQ_FEC_EN 0x08 1741270346Sjfv#define I40E_AQ_PHY_LOW_POWER 0x10 1742270346Sjfv#define I40E_AQ_LINK_PAUSE_TX 0x20 1743270346Sjfv#define I40E_AQ_LINK_PAUSE_RX 0x40 1744270346Sjfv#define I40E_AQ_QUALIFIED_MODULE 0x80 1745270346Sjfv u8 ext_info; 1746270346Sjfv#define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01 1747270346Sjfv#define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02 1748270346Sjfv#define I40E_AQ_LINK_TX_SHIFT 0x02 1749270346Sjfv#define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT) 1750270346Sjfv#define I40E_AQ_LINK_TX_ACTIVE 0x00 1751270346Sjfv#define I40E_AQ_LINK_TX_DRAINED 0x01 1752270346Sjfv#define I40E_AQ_LINK_TX_FLUSHED 0x03 1753270346Sjfv#define I40E_AQ_LINK_FORCED_40G 0x10 1754270346Sjfv u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ 1755270346Sjfv __le16 max_frame_size; 1756270346Sjfv u8 config; 1757270346Sjfv#define I40E_AQ_CONFIG_CRC_ENA 0x04 1758270346Sjfv#define I40E_AQ_CONFIG_PACING_MASK 0x78 1759270346Sjfv u8 reserved[5]; 1760266423Sjfv}; 1761266423Sjfv 1762266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status); 1763266423Sjfv 1764266423Sjfv/* Set event mask command (direct 0x613) */ 1765266423Sjfvstruct i40e_aqc_set_phy_int_mask { 1766270346Sjfv u8 reserved[8]; 1767270346Sjfv __le16 event_mask; 1768270346Sjfv#define I40E_AQ_EVENT_LINK_UPDOWN 0x0002 1769270346Sjfv#define I40E_AQ_EVENT_MEDIA_NA 0x0004 1770270346Sjfv#define I40E_AQ_EVENT_LINK_FAULT 0x0008 1771270346Sjfv#define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010 1772270346Sjfv#define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020 1773270346Sjfv#define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040 1774270346Sjfv#define I40E_AQ_EVENT_AN_COMPLETED 0x0080 1775270346Sjfv#define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100 1776270346Sjfv#define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200 1777270346Sjfv u8 reserved1[6]; 1778266423Sjfv}; 1779266423Sjfv 1780266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask); 1781266423Sjfv 1782266423Sjfv/* Get Local AN advt register (direct 0x0614) 1783266423Sjfv * Set Local AN advt register (direct 0x0615) 1784266423Sjfv * Get Link Partner AN advt register (direct 0x0616) 1785266423Sjfv */ 1786266423Sjfvstruct i40e_aqc_an_advt_reg { 1787270346Sjfv __le32 local_an_reg0; 1788270346Sjfv __le16 local_an_reg1; 1789270346Sjfv u8 reserved[10]; 1790266423Sjfv}; 1791266423Sjfv 1792266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg); 1793266423Sjfv 1794266423Sjfv/* Set Loopback mode (0x0618) */ 1795266423Sjfvstruct i40e_aqc_set_lb_mode { 1796270346Sjfv __le16 lb_mode; 1797270346Sjfv#define I40E_AQ_LB_PHY_LOCAL 0x01 1798270346Sjfv#define I40E_AQ_LB_PHY_REMOTE 0x02 1799270346Sjfv#define I40E_AQ_LB_MAC_LOCAL 0x04 1800270346Sjfv u8 reserved[14]; 1801266423Sjfv}; 1802266423Sjfv 1803266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode); 1804266423Sjfv 1805266423Sjfv/* Set PHY Debug command (0x0622) */ 1806266423Sjfvstruct i40e_aqc_set_phy_debug { 1807270346Sjfv u8 command_flags; 1808266423Sjfv#define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02 1809266423Sjfv#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2 1810270346Sjfv#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \ 1811270346Sjfv I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT) 1812266423Sjfv#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00 1813266423Sjfv#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01 1814266423Sjfv#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02 1815266423Sjfv#define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10 1816270346Sjfv u8 reserved[15]; 1817266423Sjfv}; 1818266423Sjfv 1819266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); 1820266423Sjfv 1821266423Sjfvenum i40e_aq_phy_reg_type { 1822270346Sjfv I40E_AQC_PHY_REG_INTERNAL = 0x1, 1823270346Sjfv I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, 1824270346Sjfv I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3 1825266423Sjfv}; 1826266423Sjfv 1827266423Sjfv/* NVM Read command (indirect 0x0701) 1828266423Sjfv * NVM Erase commands (direct 0x0702) 1829266423Sjfv * NVM Update commands (indirect 0x0703) 1830266423Sjfv */ 1831266423Sjfvstruct i40e_aqc_nvm_update { 1832270346Sjfv u8 command_flags; 1833270346Sjfv#define I40E_AQ_NVM_LAST_CMD 0x01 1834270346Sjfv#define I40E_AQ_NVM_FLASH_ONLY 0x80 1835270346Sjfv u8 module_pointer; 1836270346Sjfv __le16 length; 1837270346Sjfv __le32 offset; 1838270346Sjfv __le32 addr_high; 1839270346Sjfv __le32 addr_low; 1840266423Sjfv}; 1841266423Sjfv 1842266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); 1843266423Sjfv 1844266423Sjfv/* NVM Config Read (indirect 0x0704) */ 1845266423Sjfvstruct i40e_aqc_nvm_config_read { 1846270346Sjfv __le16 cmd_flags; 1847277082Sjfv#define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1 1848277082Sjfv#define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0 1849277082Sjfv#define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1 1850270346Sjfv __le16 element_count; 1851277082Sjfv __le16 element_id; /* Feature/field ID */ 1852277082Sjfv __le16 element_id_msw; /* MSWord of field ID */ 1853270346Sjfv __le32 address_high; 1854270346Sjfv __le32 address_low; 1855266423Sjfv}; 1856266423Sjfv 1857266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read); 1858266423Sjfv 1859266423Sjfv/* NVM Config Write (indirect 0x0705) */ 1860266423Sjfvstruct i40e_aqc_nvm_config_write { 1861270346Sjfv __le16 cmd_flags; 1862270346Sjfv __le16 element_count; 1863270346Sjfv u8 reserved[4]; 1864270346Sjfv __le32 address_high; 1865270346Sjfv __le32 address_low; 1866266423Sjfv}; 1867266423Sjfv 1868266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write); 1869266423Sjfv 1870277082Sjfv/* Used for 0x0704 as well as for 0x0705 commands */ 1871277082Sjfv#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1 1872277082Sjfv#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT) 1873277082Sjfv#define I40E_AQ_ANVM_FEATURE 0 1874277082Sjfv#define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT) 1875266423Sjfvstruct i40e_aqc_nvm_config_data_feature { 1876266423Sjfv __le16 feature_id; 1877277082Sjfv#define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01 1878277082Sjfv#define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08 1879277082Sjfv#define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10 1880266423Sjfv __le16 feature_options; 1881266423Sjfv __le16 feature_selection; 1882266423Sjfv}; 1883266423Sjfv 1884277082SjfvI40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature); 1885277082Sjfv 1886266423Sjfvstruct i40e_aqc_nvm_config_data_immediate_field { 1887277082Sjfv __le32 field_id; 1888277082Sjfv __le32 field_value; 1889266423Sjfv __le16 field_options; 1890277082Sjfv __le16 reserved; 1891266423Sjfv}; 1892266423Sjfv 1893277082SjfvI40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field); 1894277082Sjfv 1895284049Sjfv/* OEM Post Update (indirect 0x0720) 1896284049Sjfv * no command data struct used 1897284049Sjfv */ 1898284049Sjfv struct i40e_aqc_nvm_oem_post_update { 1899284049Sjfv#define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01 1900284049Sjfv u8 sel_data; 1901284049Sjfv u8 reserved[7]; 1902284049Sjfv}; 1903284049Sjfv 1904284049SjfvI40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update); 1905284049Sjfv 1906284049Sjfvstruct i40e_aqc_nvm_oem_post_update_buffer { 1907284049Sjfv u8 str_len; 1908284049Sjfv u8 dev_addr; 1909284049Sjfv __le16 eeprom_addr; 1910284049Sjfv u8 data[36]; 1911284049Sjfv}; 1912284049Sjfv 1913284049SjfvI40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer); 1914284049Sjfv 1915266423Sjfv/* Send to PF command (indirect 0x0801) id is only used by PF 1916266423Sjfv * Send to VF command (indirect 0x0802) id is only used by PF 1917266423Sjfv * Send to Peer PF command (indirect 0x0803) 1918266423Sjfv */ 1919266423Sjfvstruct i40e_aqc_pf_vf_message { 1920270346Sjfv __le32 id; 1921270346Sjfv u8 reserved[4]; 1922270346Sjfv __le32 addr_high; 1923270346Sjfv __le32 addr_low; 1924266423Sjfv}; 1925266423Sjfv 1926266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); 1927266423Sjfv 1928266423Sjfv/* Alternate structure */ 1929266423Sjfv 1930266423Sjfv/* Direct write (direct 0x0900) 1931266423Sjfv * Direct read (direct 0x0902) 1932266423Sjfv */ 1933266423Sjfvstruct i40e_aqc_alternate_write { 1934266423Sjfv __le32 address0; 1935266423Sjfv __le32 data0; 1936266423Sjfv __le32 address1; 1937266423Sjfv __le32 data1; 1938266423Sjfv}; 1939266423Sjfv 1940266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write); 1941266423Sjfv 1942266423Sjfv/* Indirect write (indirect 0x0901) 1943266423Sjfv * Indirect read (indirect 0x0903) 1944266423Sjfv */ 1945266423Sjfv 1946266423Sjfvstruct i40e_aqc_alternate_ind_write { 1947266423Sjfv __le32 address; 1948266423Sjfv __le32 length; 1949266423Sjfv __le32 addr_high; 1950266423Sjfv __le32 addr_low; 1951266423Sjfv}; 1952266423Sjfv 1953266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write); 1954266423Sjfv 1955266423Sjfv/* Done alternate write (direct 0x0904) 1956266423Sjfv * uses i40e_aq_desc 1957266423Sjfv */ 1958266423Sjfvstruct i40e_aqc_alternate_write_done { 1959270346Sjfv __le16 cmd_flags; 1960266423Sjfv#define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1 1961266423Sjfv#define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0 1962266423Sjfv#define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1 1963266423Sjfv#define I40E_AQ_ALTERNATE_RESET_NEEDED 2 1964270346Sjfv u8 reserved[14]; 1965266423Sjfv}; 1966266423Sjfv 1967266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done); 1968266423Sjfv 1969266423Sjfv/* Set OEM mode (direct 0x0905) */ 1970266423Sjfvstruct i40e_aqc_alternate_set_mode { 1971270346Sjfv __le32 mode; 1972266423Sjfv#define I40E_AQ_ALTERNATE_MODE_NONE 0 1973266423Sjfv#define I40E_AQ_ALTERNATE_MODE_OEM 1 1974270346Sjfv u8 reserved[12]; 1975266423Sjfv}; 1976266423Sjfv 1977266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode); 1978266423Sjfv 1979266423Sjfv/* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */ 1980266423Sjfv 1981266423Sjfv/* async events 0x10xx */ 1982266423Sjfv 1983266423Sjfv/* Lan Queue Overflow Event (direct, 0x1001) */ 1984266423Sjfvstruct i40e_aqc_lan_overflow { 1985270346Sjfv __le32 prtdcb_rupto; 1986270346Sjfv __le32 otx_ctl; 1987270346Sjfv u8 reserved[8]; 1988266423Sjfv}; 1989266423Sjfv 1990266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow); 1991266423Sjfv 1992266423Sjfv/* Get LLDP MIB (indirect 0x0A00) */ 1993266423Sjfvstruct i40e_aqc_lldp_get_mib { 1994270346Sjfv u8 type; 1995270346Sjfv u8 reserved1; 1996270346Sjfv#define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3 1997270346Sjfv#define I40E_AQ_LLDP_MIB_LOCAL 0x0 1998270346Sjfv#define I40E_AQ_LLDP_MIB_REMOTE 0x1 1999270346Sjfv#define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2 2000270346Sjfv#define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC 2001270346Sjfv#define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2 2002270346Sjfv#define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0 2003270346Sjfv#define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1 2004270346Sjfv#define I40E_AQ_LLDP_TX_SHIFT 0x4 2005270346Sjfv#define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT) 2006266423Sjfv/* TX pause flags use I40E_AQ_LINK_TX_* above */ 2007270346Sjfv __le16 local_len; 2008270346Sjfv __le16 remote_len; 2009270346Sjfv u8 reserved2[2]; 2010270346Sjfv __le32 addr_high; 2011270346Sjfv __le32 addr_low; 2012266423Sjfv}; 2013266423Sjfv 2014266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib); 2015266423Sjfv 2016266423Sjfv/* Configure LLDP MIB Change Event (direct 0x0A01) 2017266423Sjfv * also used for the event (with type in the command field) 2018266423Sjfv */ 2019266423Sjfvstruct i40e_aqc_lldp_update_mib { 2020270346Sjfv u8 command; 2021270346Sjfv#define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 2022270346Sjfv#define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1 2023270346Sjfv u8 reserved[7]; 2024270346Sjfv __le32 addr_high; 2025270346Sjfv __le32 addr_low; 2026266423Sjfv}; 2027266423Sjfv 2028266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib); 2029266423Sjfv 2030266423Sjfv/* Add LLDP TLV (indirect 0x0A02) 2031266423Sjfv * Delete LLDP TLV (indirect 0x0A04) 2032266423Sjfv */ 2033266423Sjfvstruct i40e_aqc_lldp_add_tlv { 2034270346Sjfv u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2035270346Sjfv u8 reserved1[1]; 2036270346Sjfv __le16 len; 2037270346Sjfv u8 reserved2[4]; 2038270346Sjfv __le32 addr_high; 2039270346Sjfv __le32 addr_low; 2040266423Sjfv}; 2041266423Sjfv 2042266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv); 2043266423Sjfv 2044266423Sjfv/* Update LLDP TLV (indirect 0x0A03) */ 2045266423Sjfvstruct i40e_aqc_lldp_update_tlv { 2046270346Sjfv u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2047270346Sjfv u8 reserved; 2048270346Sjfv __le16 old_len; 2049270346Sjfv __le16 new_offset; 2050270346Sjfv __le16 new_len; 2051270346Sjfv __le32 addr_high; 2052270346Sjfv __le32 addr_low; 2053266423Sjfv}; 2054266423Sjfv 2055266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv); 2056266423Sjfv 2057266423Sjfv/* Stop LLDP (direct 0x0A05) */ 2058266423Sjfvstruct i40e_aqc_lldp_stop { 2059270346Sjfv u8 command; 2060270346Sjfv#define I40E_AQ_LLDP_AGENT_STOP 0x0 2061270346Sjfv#define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1 2062270346Sjfv u8 reserved[15]; 2063266423Sjfv}; 2064266423Sjfv 2065266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop); 2066266423Sjfv 2067266423Sjfv/* Start LLDP (direct 0x0A06) */ 2068266423Sjfv 2069266423Sjfvstruct i40e_aqc_lldp_start { 2070270346Sjfv u8 command; 2071270346Sjfv#define I40E_AQ_LLDP_AGENT_START 0x1 2072270346Sjfv u8 reserved[15]; 2073266423Sjfv}; 2074266423Sjfv 2075266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start); 2076266423Sjfv 2077277082Sjfv/* Get CEE DCBX Oper Config (0x0A07) 2078277082Sjfv * uses the generic descriptor struct 2079277082Sjfv * returns below as indirect response 2080266423Sjfv */ 2081266423Sjfv 2082277082Sjfv#define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0 2083277082Sjfv#define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT) 2084277082Sjfv#define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3 2085277082Sjfv#define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT) 2086277082Sjfv#define I40E_AQC_CEE_APP_FIP_SHIFT 0x8 2087277082Sjfv#define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2088284049Sjfv 2089277082Sjfv#define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0 2090277082Sjfv#define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT) 2091277082Sjfv#define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3 2092277082Sjfv#define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT) 2093277082Sjfv#define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8 2094277082Sjfv#define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT) 2095284049Sjfv#define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8 2096284049Sjfv#define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT) 2097284049Sjfv#define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB 2098284049Sjfv#define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT) 2099284049Sjfv#define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10 2100284049Sjfv#define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT) 2101284049Sjfv 2102284049Sjfv/* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with 2103284049Sjfv * word boundary layout issues, which the Linux compilers silently deal 2104284049Sjfv * with by adding padding, making the actual struct larger than designed. 2105284049Sjfv * However, the FW compiler for the NIC is less lenient and complains 2106284049Sjfv * about the struct. Hence, the struct defined here has an extra byte in 2107284049Sjfv * fields reserved3 and reserved4 to directly acknowledge that padding, 2108284049Sjfv * and the new length is used in the length check macro. 2109284049Sjfv */ 2110277082Sjfvstruct i40e_aqc_get_cee_dcb_cfg_v1_resp { 2111277082Sjfv u8 reserved1; 2112277082Sjfv u8 oper_num_tc; 2113277082Sjfv u8 oper_prio_tc[4]; 2114277082Sjfv u8 reserved2; 2115277082Sjfv u8 oper_tc_bw[8]; 2116277082Sjfv u8 oper_pfc_en; 2117284049Sjfv u8 reserved3[2]; 2118277082Sjfv __le16 oper_app_prio; 2119284049Sjfv u8 reserved4[2]; 2120277082Sjfv __le16 tlv_status; 2121277082Sjfv}; 2122277082Sjfv 2123277082SjfvI40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp); 2124277082Sjfv 2125277082Sjfvstruct i40e_aqc_get_cee_dcb_cfg_resp { 2126277082Sjfv u8 oper_num_tc; 2127277082Sjfv u8 oper_prio_tc[4]; 2128277082Sjfv u8 oper_tc_bw[8]; 2129277082Sjfv u8 oper_pfc_en; 2130277082Sjfv __le16 oper_app_prio; 2131277082Sjfv __le32 tlv_status; 2132277082Sjfv u8 reserved[12]; 2133277082Sjfv}; 2134277082Sjfv 2135277082SjfvI40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp); 2136277082Sjfv 2137277082Sjfv/* Set Local LLDP MIB (indirect 0x0A08) 2138277082Sjfv * Used to replace the local MIB of a given LLDP agent. e.g. DCBx 2139277082Sjfv */ 2140277082Sjfvstruct i40e_aqc_lldp_set_local_mib { 2141277082Sjfv#define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0 2142299545Serj#define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \ 2143299545Serj SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT) 2144299545Serj#define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0 2145299545Serj#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1) 2146299545Serj#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK (1 << \ 2147299545Serj SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT) 2148299545Serj#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1 2149277082Sjfv u8 type; 2150277082Sjfv u8 reserved0; 2151277082Sjfv __le16 length; 2152277082Sjfv u8 reserved1[4]; 2153277082Sjfv __le32 address_high; 2154277082Sjfv __le32 address_low; 2155277082Sjfv}; 2156277082Sjfv 2157277082SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib); 2158277082Sjfv 2159299547Serjstruct i40e_aqc_lldp_set_local_mib_resp { 2160299547Serj#define SET_LOCAL_MIB_RESP_EVENT_TRIGGERED_MASK 0x01 2161299547Serj u8 status; 2162299547Serj u8 reserved[15]; 2163299547Serj}; 2164299547Serj 2165299547SerjI40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_lldp_set_local_mib_resp); 2166299547Serj 2167277082Sjfv/* Stop/Start LLDP Agent (direct 0x0A09) 2168277082Sjfv * Used for stopping/starting specific LLDP agent. e.g. DCBx 2169277082Sjfv */ 2170277082Sjfvstruct i40e_aqc_lldp_stop_start_specific_agent { 2171277082Sjfv#define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0 2172277082Sjfv#define I40E_AQC_START_SPECIFIC_AGENT_MASK (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT) 2173277082Sjfv u8 command; 2174277082Sjfv u8 reserved[15]; 2175277082Sjfv}; 2176277082Sjfv 2177277082SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent); 2178277082Sjfv 2179266423Sjfv/* Add Udp Tunnel command and completion (direct 0x0B00) */ 2180266423Sjfvstruct i40e_aqc_add_udp_tunnel { 2181270346Sjfv __le16 udp_port; 2182270346Sjfv u8 reserved0[3]; 2183270346Sjfv u8 protocol_type; 2184266423Sjfv#define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00 2185266423Sjfv#define I40E_AQC_TUNNEL_TYPE_NGE 0x01 2186266423Sjfv#define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10 2187270346Sjfv u8 reserved1[10]; 2188266423Sjfv}; 2189266423Sjfv 2190266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel); 2191266423Sjfv 2192266423Sjfvstruct i40e_aqc_add_udp_tunnel_completion { 2193266423Sjfv __le16 udp_port; 2194266423Sjfv u8 filter_entry_index; 2195266423Sjfv u8 multiple_pfs; 2196270346Sjfv#define I40E_AQC_SINGLE_PF 0x0 2197270346Sjfv#define I40E_AQC_MULTIPLE_PFS 0x1 2198266423Sjfv u8 total_filters; 2199266423Sjfv u8 reserved[11]; 2200266423Sjfv}; 2201266423Sjfv 2202266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion); 2203266423Sjfv 2204266423Sjfv/* remove UDP Tunnel command (0x0B01) */ 2205266423Sjfvstruct i40e_aqc_remove_udp_tunnel { 2206270346Sjfv u8 reserved[2]; 2207270346Sjfv u8 index; /* 0 to 15 */ 2208270346Sjfv u8 reserved2[13]; 2209266423Sjfv}; 2210266423Sjfv 2211266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel); 2212266423Sjfv 2213266423Sjfvstruct i40e_aqc_del_udp_tunnel_completion { 2214270346Sjfv __le16 udp_port; 2215270346Sjfv u8 index; /* 0 to 15 */ 2216270346Sjfv u8 multiple_pfs; 2217270346Sjfv u8 total_filters_used; 2218270346Sjfv u8 reserved1[11]; 2219266423Sjfv}; 2220266423Sjfv 2221266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion); 2222266423Sjfv 2223266423Sjfv/* tunnel key structure 0x0B10 */ 2224266423Sjfv 2225266423Sjfvstruct i40e_aqc_tunnel_key_structure { 2226266423Sjfv u8 key1_off; 2227266423Sjfv u8 key2_off; 2228266423Sjfv u8 key1_len; /* 0 to 15 */ 2229266423Sjfv u8 key2_len; /* 0 to 15 */ 2230266423Sjfv u8 flags; 2231270346Sjfv#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 2232266423Sjfv/* response flags */ 2233270346Sjfv#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 2234270346Sjfv#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 2235270346Sjfv#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 2236266423Sjfv u8 network_key_index; 2237266423Sjfv#define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0 2238266423Sjfv#define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1 2239266423Sjfv#define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2 2240266423Sjfv#define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3 2241266423Sjfv u8 reserved[10]; 2242266423Sjfv}; 2243266423Sjfv 2244266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure); 2245266423Sjfv 2246266423Sjfv/* OEM mode commands (direct 0xFE0x) */ 2247266423Sjfvstruct i40e_aqc_oem_param_change { 2248270346Sjfv __le32 param_type; 2249270346Sjfv#define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0 2250270346Sjfv#define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1 2251270346Sjfv#define I40E_AQ_OEM_PARAM_MAC 2 2252270346Sjfv __le32 param_value1; 2253277082Sjfv __le16 param_value2; 2254277082Sjfv u8 reserved[6]; 2255266423Sjfv}; 2256266423Sjfv 2257266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change); 2258266423Sjfv 2259266423Sjfvstruct i40e_aqc_oem_state_change { 2260270346Sjfv __le32 state; 2261270346Sjfv#define I40E_AQ_OEM_STATE_LINK_DOWN 0x0 2262270346Sjfv#define I40E_AQ_OEM_STATE_LINK_UP 0x1 2263270346Sjfv u8 reserved[12]; 2264266423Sjfv}; 2265266423Sjfv 2266266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change); 2267266423Sjfv 2268277082Sjfv/* Initialize OCSD (0xFE02, direct) */ 2269277082Sjfvstruct i40e_aqc_opc_oem_ocsd_initialize { 2270277082Sjfv u8 type_status; 2271277082Sjfv u8 reserved1[3]; 2272277082Sjfv __le32 ocsd_memory_block_addr_high; 2273277082Sjfv __le32 ocsd_memory_block_addr_low; 2274277082Sjfv __le32 requested_update_interval; 2275277082Sjfv}; 2276277082Sjfv 2277277082SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize); 2278277082Sjfv 2279277082Sjfv/* Initialize OCBB (0xFE03, direct) */ 2280277082Sjfvstruct i40e_aqc_opc_oem_ocbb_initialize { 2281277082Sjfv u8 type_status; 2282277082Sjfv u8 reserved1[3]; 2283277082Sjfv __le32 ocbb_memory_block_addr_high; 2284277082Sjfv __le32 ocbb_memory_block_addr_low; 2285277082Sjfv u8 reserved2[4]; 2286277082Sjfv}; 2287277082Sjfv 2288277082SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize); 2289277082Sjfv 2290266423Sjfv/* debug commands */ 2291266423Sjfv 2292266423Sjfv/* get device id (0xFF00) uses the generic structure */ 2293266423Sjfv 2294266423Sjfv/* set test more (0xFF01, internal) */ 2295266423Sjfv 2296266423Sjfvstruct i40e_acq_set_test_mode { 2297270346Sjfv u8 mode; 2298270346Sjfv#define I40E_AQ_TEST_PARTIAL 0 2299270346Sjfv#define I40E_AQ_TEST_FULL 1 2300270346Sjfv#define I40E_AQ_TEST_NVM 2 2301270346Sjfv u8 reserved[3]; 2302270346Sjfv u8 command; 2303270346Sjfv#define I40E_AQ_TEST_OPEN 0 2304270346Sjfv#define I40E_AQ_TEST_CLOSE 1 2305270346Sjfv#define I40E_AQ_TEST_INC 2 2306270346Sjfv u8 reserved2[3]; 2307270346Sjfv __le32 address_high; 2308270346Sjfv __le32 address_low; 2309266423Sjfv}; 2310266423Sjfv 2311266423SjfvI40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode); 2312266423Sjfv 2313266423Sjfv/* Debug Read Register command (0xFF03) 2314266423Sjfv * Debug Write Register command (0xFF04) 2315266423Sjfv */ 2316266423Sjfvstruct i40e_aqc_debug_reg_read_write { 2317266423Sjfv __le32 reserved; 2318266423Sjfv __le32 address; 2319266423Sjfv __le32 value_high; 2320266423Sjfv __le32 value_low; 2321266423Sjfv}; 2322266423Sjfv 2323266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write); 2324266423Sjfv 2325266423Sjfv/* Scatter/gather Reg Read (indirect 0xFF05) 2326266423Sjfv * Scatter/gather Reg Write (indirect 0xFF06) 2327266423Sjfv */ 2328266423Sjfv 2329266423Sjfv/* i40e_aq_desc is used for the command */ 2330266423Sjfvstruct i40e_aqc_debug_reg_sg_element_data { 2331266423Sjfv __le32 address; 2332266423Sjfv __le32 value; 2333266423Sjfv}; 2334266423Sjfv 2335266423Sjfv/* Debug Modify register (direct 0xFF07) */ 2336266423Sjfvstruct i40e_aqc_debug_modify_reg { 2337266423Sjfv __le32 address; 2338266423Sjfv __le32 value; 2339266423Sjfv __le32 clear_mask; 2340266423Sjfv __le32 set_mask; 2341266423Sjfv}; 2342266423Sjfv 2343266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg); 2344266423Sjfv 2345266423Sjfv/* dump internal data (0xFF08, indirect) */ 2346266423Sjfv 2347266423Sjfv#define I40E_AQ_CLUSTER_ID_AUX 0 2348266423Sjfv#define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1 2349266423Sjfv#define I40E_AQ_CLUSTER_ID_TXSCHED 2 2350266423Sjfv#define I40E_AQ_CLUSTER_ID_HMC 3 2351266423Sjfv#define I40E_AQ_CLUSTER_ID_MAC0 4 2352266423Sjfv#define I40E_AQ_CLUSTER_ID_MAC1 5 2353266423Sjfv#define I40E_AQ_CLUSTER_ID_MAC2 6 2354266423Sjfv#define I40E_AQ_CLUSTER_ID_MAC3 7 2355266423Sjfv#define I40E_AQ_CLUSTER_ID_DCB 8 2356266423Sjfv#define I40E_AQ_CLUSTER_ID_EMP_MEM 9 2357266423Sjfv#define I40E_AQ_CLUSTER_ID_PKT_BUF 10 2358266423Sjfv#define I40E_AQ_CLUSTER_ID_ALTRAM 11 2359266423Sjfv 2360266423Sjfvstruct i40e_aqc_debug_dump_internals { 2361270346Sjfv u8 cluster_id; 2362270346Sjfv u8 table_id; 2363270346Sjfv __le16 data_size; 2364270346Sjfv __le32 idx; 2365270346Sjfv __le32 address_high; 2366270346Sjfv __le32 address_low; 2367266423Sjfv}; 2368266423Sjfv 2369266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals); 2370266423Sjfv 2371266423Sjfvstruct i40e_aqc_debug_modify_internals { 2372270346Sjfv u8 cluster_id; 2373270346Sjfv u8 cluster_specific_params[7]; 2374270346Sjfv __le32 address_high; 2375270346Sjfv __le32 address_low; 2376266423Sjfv}; 2377266423Sjfv 2378266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals); 2379266423Sjfv 2380299547Serj#endif /* _I40E_ADMINQ_CMD_H_ */ 2381