i40e_adminq_cmd.h revision 299548
1/****************************************************************************** 2 3 Copyright (c) 2013-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: head/sys/dev/ixl/i40e_adminq_cmd.h 299548 2016-05-12 18:20:18Z erj $*/ 34 35#ifndef _I40E_ADMINQ_CMD_H_ 36#define _I40E_ADMINQ_CMD_H_ 37 38/* This header file defines the i40e Admin Queue commands and is shared between 39 * i40e Firmware and Software. 40 * 41 * This file needs to comply with the Linux Kernel coding style. 42 */ 43 44#define I40E_FW_API_VERSION_MAJOR 0x0001 45#define I40E_FW_API_VERSION_MINOR 0x0004 46 47struct i40e_aq_desc { 48 __le16 flags; 49 __le16 opcode; 50 __le16 datalen; 51 __le16 retval; 52 __le32 cookie_high; 53 __le32 cookie_low; 54 union { 55 struct { 56 __le32 param0; 57 __le32 param1; 58 __le32 param2; 59 __le32 param3; 60 } internal; 61 struct { 62 __le32 param0; 63 __le32 param1; 64 __le32 addr_high; 65 __le32 addr_low; 66 } external; 67 u8 raw[16]; 68 } params; 69}; 70 71/* Flags sub-structure 72 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 73 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 74 */ 75 76/* command flags and offsets*/ 77#define I40E_AQ_FLAG_DD_SHIFT 0 78#define I40E_AQ_FLAG_CMP_SHIFT 1 79#define I40E_AQ_FLAG_ERR_SHIFT 2 80#define I40E_AQ_FLAG_VFE_SHIFT 3 81#define I40E_AQ_FLAG_LB_SHIFT 9 82#define I40E_AQ_FLAG_RD_SHIFT 10 83#define I40E_AQ_FLAG_VFC_SHIFT 11 84#define I40E_AQ_FLAG_BUF_SHIFT 12 85#define I40E_AQ_FLAG_SI_SHIFT 13 86#define I40E_AQ_FLAG_EI_SHIFT 14 87#define I40E_AQ_FLAG_FE_SHIFT 15 88 89#define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */ 90#define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */ 91#define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */ 92#define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */ 93#define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */ 94#define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */ 95#define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */ 96#define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ 97#define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */ 98#define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */ 99#define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */ 100 101/* error codes */ 102enum i40e_admin_queue_err { 103 I40E_AQ_RC_OK = 0, /* success */ 104 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */ 105 I40E_AQ_RC_ENOENT = 2, /* No such element */ 106 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */ 107 I40E_AQ_RC_EINTR = 4, /* operation interrupted */ 108 I40E_AQ_RC_EIO = 5, /* I/O error */ 109 I40E_AQ_RC_ENXIO = 6, /* No such resource */ 110 I40E_AQ_RC_E2BIG = 7, /* Arg too long */ 111 I40E_AQ_RC_EAGAIN = 8, /* Try again */ 112 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */ 113 I40E_AQ_RC_EACCES = 10, /* Permission denied */ 114 I40E_AQ_RC_EFAULT = 11, /* Bad address */ 115 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */ 116 I40E_AQ_RC_EEXIST = 13, /* object already exists */ 117 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */ 118 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 119 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */ 120 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */ 121 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */ 122 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 123 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 124 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 125 I40E_AQ_RC_EFBIG = 22, /* File too large */ 126}; 127 128/* Admin Queue command opcodes */ 129enum i40e_admin_queue_opc { 130 /* aq commands */ 131 i40e_aqc_opc_get_version = 0x0001, 132 i40e_aqc_opc_driver_version = 0x0002, 133 i40e_aqc_opc_queue_shutdown = 0x0003, 134 i40e_aqc_opc_set_pf_context = 0x0004, 135 136 /* resource ownership */ 137 i40e_aqc_opc_request_resource = 0x0008, 138 i40e_aqc_opc_release_resource = 0x0009, 139 140 i40e_aqc_opc_list_func_capabilities = 0x000A, 141 i40e_aqc_opc_list_dev_capabilities = 0x000B, 142 143 /* LAA */ 144 i40e_aqc_opc_mac_address_read = 0x0107, 145 i40e_aqc_opc_mac_address_write = 0x0108, 146 147 /* PXE */ 148 i40e_aqc_opc_clear_pxe_mode = 0x0110, 149 150 /* internal switch commands */ 151 i40e_aqc_opc_get_switch_config = 0x0200, 152 i40e_aqc_opc_add_statistics = 0x0201, 153 i40e_aqc_opc_remove_statistics = 0x0202, 154 i40e_aqc_opc_set_port_parameters = 0x0203, 155 i40e_aqc_opc_get_switch_resource_alloc = 0x0204, 156 157 i40e_aqc_opc_add_vsi = 0x0210, 158 i40e_aqc_opc_update_vsi_parameters = 0x0211, 159 i40e_aqc_opc_get_vsi_parameters = 0x0212, 160 161 i40e_aqc_opc_add_pv = 0x0220, 162 i40e_aqc_opc_update_pv_parameters = 0x0221, 163 i40e_aqc_opc_get_pv_parameters = 0x0222, 164 165 i40e_aqc_opc_add_veb = 0x0230, 166 i40e_aqc_opc_update_veb_parameters = 0x0231, 167 i40e_aqc_opc_get_veb_parameters = 0x0232, 168 169 i40e_aqc_opc_delete_element = 0x0243, 170 171 i40e_aqc_opc_add_macvlan = 0x0250, 172 i40e_aqc_opc_remove_macvlan = 0x0251, 173 i40e_aqc_opc_add_vlan = 0x0252, 174 i40e_aqc_opc_remove_vlan = 0x0253, 175 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254, 176 i40e_aqc_opc_add_tag = 0x0255, 177 i40e_aqc_opc_remove_tag = 0x0256, 178 i40e_aqc_opc_add_multicast_etag = 0x0257, 179 i40e_aqc_opc_remove_multicast_etag = 0x0258, 180 i40e_aqc_opc_update_tag = 0x0259, 181 i40e_aqc_opc_add_control_packet_filter = 0x025A, 182 i40e_aqc_opc_remove_control_packet_filter = 0x025B, 183 i40e_aqc_opc_add_cloud_filters = 0x025C, 184 i40e_aqc_opc_remove_cloud_filters = 0x025D, 185 186 i40e_aqc_opc_add_mirror_rule = 0x0260, 187 i40e_aqc_opc_delete_mirror_rule = 0x0261, 188 189 /* DCB commands */ 190 i40e_aqc_opc_dcb_ignore_pfc = 0x0301, 191 i40e_aqc_opc_dcb_updated = 0x0302, 192 193 /* TX scheduler */ 194 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400, 195 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406, 196 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407, 197 i40e_aqc_opc_query_vsi_bw_config = 0x0408, 198 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A, 199 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410, 200 201 i40e_aqc_opc_enable_switching_comp_ets = 0x0413, 202 i40e_aqc_opc_modify_switching_comp_ets = 0x0414, 203 i40e_aqc_opc_disable_switching_comp_ets = 0x0415, 204 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, 205 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417, 206 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418, 207 i40e_aqc_opc_query_port_ets_config = 0x0419, 208 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A, 209 i40e_aqc_opc_suspend_port_tx = 0x041B, 210 i40e_aqc_opc_resume_port_tx = 0x041C, 211 i40e_aqc_opc_configure_partition_bw = 0x041D, 212 213 /* hmc */ 214 i40e_aqc_opc_query_hmc_resource_profile = 0x0500, 215 i40e_aqc_opc_set_hmc_resource_profile = 0x0501, 216 217 /* phy commands*/ 218 i40e_aqc_opc_get_phy_abilities = 0x0600, 219 i40e_aqc_opc_set_phy_config = 0x0601, 220 i40e_aqc_opc_set_mac_config = 0x0603, 221 i40e_aqc_opc_set_link_restart_an = 0x0605, 222 i40e_aqc_opc_get_link_status = 0x0607, 223 i40e_aqc_opc_set_phy_int_mask = 0x0613, 224 i40e_aqc_opc_get_local_advt_reg = 0x0614, 225 i40e_aqc_opc_set_local_advt_reg = 0x0615, 226 i40e_aqc_opc_get_partner_advt = 0x0616, 227 i40e_aqc_opc_set_lb_modes = 0x0618, 228 i40e_aqc_opc_get_phy_wol_caps = 0x0621, 229 i40e_aqc_opc_set_phy_debug = 0x0622, 230 i40e_aqc_opc_upload_ext_phy_fm = 0x0625, 231 232 /* NVM commands */ 233 i40e_aqc_opc_nvm_read = 0x0701, 234 i40e_aqc_opc_nvm_erase = 0x0702, 235 i40e_aqc_opc_nvm_update = 0x0703, 236 i40e_aqc_opc_nvm_config_read = 0x0704, 237 i40e_aqc_opc_nvm_config_write = 0x0705, 238 i40e_aqc_opc_oem_post_update = 0x0720, 239 240 /* virtualization commands */ 241 i40e_aqc_opc_send_msg_to_pf = 0x0801, 242 i40e_aqc_opc_send_msg_to_vf = 0x0802, 243 i40e_aqc_opc_send_msg_to_peer = 0x0803, 244 245 /* alternate structure */ 246 i40e_aqc_opc_alternate_write = 0x0900, 247 i40e_aqc_opc_alternate_write_indirect = 0x0901, 248 i40e_aqc_opc_alternate_read = 0x0902, 249 i40e_aqc_opc_alternate_read_indirect = 0x0903, 250 i40e_aqc_opc_alternate_write_done = 0x0904, 251 i40e_aqc_opc_alternate_set_mode = 0x0905, 252 i40e_aqc_opc_alternate_clear_port = 0x0906, 253 254 /* LLDP commands */ 255 i40e_aqc_opc_lldp_get_mib = 0x0A00, 256 i40e_aqc_opc_lldp_update_mib = 0x0A01, 257 i40e_aqc_opc_lldp_add_tlv = 0x0A02, 258 i40e_aqc_opc_lldp_update_tlv = 0x0A03, 259 i40e_aqc_opc_lldp_delete_tlv = 0x0A04, 260 i40e_aqc_opc_lldp_stop = 0x0A05, 261 i40e_aqc_opc_lldp_start = 0x0A06, 262 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07, 263 i40e_aqc_opc_lldp_set_local_mib = 0x0A08, 264 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09, 265 266 /* Tunnel commands */ 267 i40e_aqc_opc_add_udp_tunnel = 0x0B00, 268 i40e_aqc_opc_del_udp_tunnel = 0x0B01, 269 270 /* Async Events */ 271 i40e_aqc_opc_event_lan_overflow = 0x1001, 272 273 /* OEM commands */ 274 i40e_aqc_opc_oem_parameter_change = 0xFE00, 275 i40e_aqc_opc_oem_device_status_change = 0xFE01, 276 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02, 277 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03, 278 279 /* debug commands */ 280 i40e_aqc_opc_debug_read_reg = 0xFF03, 281 i40e_aqc_opc_debug_write_reg = 0xFF04, 282 i40e_aqc_opc_debug_modify_reg = 0xFF07, 283 i40e_aqc_opc_debug_dump_internals = 0xFF08, 284}; 285 286/* command structures and indirect data structures */ 287 288/* Structure naming conventions: 289 * - no suffix for direct command descriptor structures 290 * - _data for indirect sent data 291 * - _resp for indirect return data (data which is both will use _data) 292 * - _completion for direct return data 293 * - _element_ for repeated elements (may also be _data or _resp) 294 * 295 * Command structures are expected to overlay the params.raw member of the basic 296 * descriptor, and as such cannot exceed 16 bytes in length. 297 */ 298 299/* This macro is used to generate a compilation error if a structure 300 * is not exactly the correct length. It gives a divide by zero error if the 301 * structure is not of the correct size, otherwise it creates an enum that is 302 * never used. 303 */ 304#define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \ 305 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) } 306 307/* This macro is used extensively to ensure that command structures are 16 308 * bytes in length as they have to map to the raw array of that size. 309 */ 310#define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X) 311 312/* internal (0x00XX) commands */ 313 314/* Get version (direct 0x0001) */ 315struct i40e_aqc_get_version { 316 __le32 rom_ver; 317 __le32 fw_build; 318 __le16 fw_major; 319 __le16 fw_minor; 320 __le16 api_major; 321 __le16 api_minor; 322}; 323 324I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version); 325 326/* Send driver version (indirect 0x0002) */ 327struct i40e_aqc_driver_version { 328 u8 driver_major_ver; 329 u8 driver_minor_ver; 330 u8 driver_build_ver; 331 u8 driver_subbuild_ver; 332 u8 reserved[4]; 333 __le32 address_high; 334 __le32 address_low; 335}; 336 337I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version); 338 339/* Queue Shutdown (direct 0x0003) */ 340struct i40e_aqc_queue_shutdown { 341 __le32 driver_unloading; 342#define I40E_AQ_DRIVER_UNLOADING 0x1 343 u8 reserved[12]; 344}; 345 346I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); 347 348/* Set PF context (0x0004, direct) */ 349struct i40e_aqc_set_pf_context { 350 u8 pf_id; 351 u8 reserved[15]; 352}; 353 354I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context); 355 356/* Request resource ownership (direct 0x0008) 357 * Release resource ownership (direct 0x0009) 358 */ 359#define I40E_AQ_RESOURCE_NVM 1 360#define I40E_AQ_RESOURCE_SDP 2 361#define I40E_AQ_RESOURCE_ACCESS_READ 1 362#define I40E_AQ_RESOURCE_ACCESS_WRITE 2 363#define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000 364#define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000 365 366struct i40e_aqc_request_resource { 367 __le16 resource_id; 368 __le16 access_type; 369 __le32 timeout; 370 __le32 resource_number; 371 u8 reserved[4]; 372}; 373 374I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource); 375 376/* Get function capabilities (indirect 0x000A) 377 * Get device capabilities (indirect 0x000B) 378 */ 379struct i40e_aqc_list_capabilites { 380 u8 command_flags; 381#define I40E_AQ_LIST_CAP_PF_INDEX_EN 1 382 u8 pf_index; 383 u8 reserved[2]; 384 __le32 count; 385 __le32 addr_high; 386 __le32 addr_low; 387}; 388 389I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites); 390 391struct i40e_aqc_list_capabilities_element_resp { 392 __le16 id; 393 u8 major_rev; 394 u8 minor_rev; 395 __le32 number; 396 __le32 logical_id; 397 __le32 phys_id; 398 u8 reserved[16]; 399}; 400 401/* list of caps */ 402 403#define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001 404#define I40E_AQ_CAP_ID_MNG_MODE 0x0002 405#define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003 406#define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004 407#define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005 408#define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006 409#define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008 410#define I40E_AQ_CAP_ID_SRIOV 0x0012 411#define I40E_AQ_CAP_ID_VF 0x0013 412#define I40E_AQ_CAP_ID_VMDQ 0x0014 413#define I40E_AQ_CAP_ID_8021QBG 0x0015 414#define I40E_AQ_CAP_ID_8021QBR 0x0016 415#define I40E_AQ_CAP_ID_VSI 0x0017 416#define I40E_AQ_CAP_ID_DCB 0x0018 417#define I40E_AQ_CAP_ID_FCOE 0x0021 418#define I40E_AQ_CAP_ID_ISCSI 0x0022 419#define I40E_AQ_CAP_ID_RSS 0x0040 420#define I40E_AQ_CAP_ID_RXQ 0x0041 421#define I40E_AQ_CAP_ID_TXQ 0x0042 422#define I40E_AQ_CAP_ID_MSIX 0x0043 423#define I40E_AQ_CAP_ID_VF_MSIX 0x0044 424#define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 425#define I40E_AQ_CAP_ID_1588 0x0046 426#define I40E_AQ_CAP_ID_IWARP 0x0051 427#define I40E_AQ_CAP_ID_LED 0x0061 428#define I40E_AQ_CAP_ID_SDP 0x0062 429#define I40E_AQ_CAP_ID_MDIO 0x0063 430#define I40E_AQ_CAP_ID_WSR_PROT 0x0064 431#define I40E_AQ_CAP_ID_FLEX10 0x00F1 432#define I40E_AQ_CAP_ID_CEM 0x00F2 433 434/* Set CPPM Configuration (direct 0x0103) */ 435struct i40e_aqc_cppm_configuration { 436 __le16 command_flags; 437#define I40E_AQ_CPPM_EN_LTRC 0x0800 438#define I40E_AQ_CPPM_EN_DMCTH 0x1000 439#define I40E_AQ_CPPM_EN_DMCTLX 0x2000 440#define I40E_AQ_CPPM_EN_HPTC 0x4000 441#define I40E_AQ_CPPM_EN_DMARC 0x8000 442 __le16 ttlx; 443 __le32 dmacr; 444 __le16 dmcth; 445 u8 hptc; 446 u8 reserved; 447 __le32 pfltrc; 448}; 449 450I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration); 451 452/* Set ARP Proxy command / response (indirect 0x0104) */ 453struct i40e_aqc_arp_proxy_data { 454 __le16 command_flags; 455#define I40E_AQ_ARP_INIT_IPV4 0x0008 456#define I40E_AQ_ARP_UNSUP_CTL 0x0010 457#define I40E_AQ_ARP_ENA 0x0020 458#define I40E_AQ_ARP_ADD_IPV4 0x0040 459#define I40E_AQ_ARP_DEL_IPV4 0x0080 460 __le16 table_id; 461 __le32 pfpm_proxyfc; 462 __le32 ip_addr; 463 u8 mac_addr[6]; 464 u8 reserved[2]; 465}; 466 467I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data); 468 469/* Set NS Proxy Table Entry Command (indirect 0x0105) */ 470struct i40e_aqc_ns_proxy_data { 471 __le16 table_idx_mac_addr_0; 472 __le16 table_idx_mac_addr_1; 473 __le16 table_idx_ipv6_0; 474 __le16 table_idx_ipv6_1; 475 __le16 control; 476#define I40E_AQ_NS_PROXY_ADD_0 0x0100 477#define I40E_AQ_NS_PROXY_DEL_0 0x0200 478#define I40E_AQ_NS_PROXY_ADD_1 0x0400 479#define I40E_AQ_NS_PROXY_DEL_1 0x0800 480#define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x1000 481#define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x2000 482#define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x4000 483#define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x8000 484#define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0001 485#define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0002 486#define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0004 487 u8 mac_addr_0[6]; 488 u8 mac_addr_1[6]; 489 u8 local_mac_addr[6]; 490 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */ 491 u8 ipv6_addr_1[16]; 492}; 493 494I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data); 495 496/* Manage LAA Command (0x0106) - obsolete */ 497struct i40e_aqc_mng_laa { 498 __le16 command_flags; 499#define I40E_AQ_LAA_FLAG_WR 0x8000 500 u8 reserved[2]; 501 __le32 sal; 502 __le16 sah; 503 u8 reserved2[6]; 504}; 505 506I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa); 507 508/* Manage MAC Address Read Command (indirect 0x0107) */ 509struct i40e_aqc_mac_address_read { 510 __le16 command_flags; 511#define I40E_AQC_LAN_ADDR_VALID 0x10 512#define I40E_AQC_SAN_ADDR_VALID 0x20 513#define I40E_AQC_PORT_ADDR_VALID 0x40 514#define I40E_AQC_WOL_ADDR_VALID 0x80 515#define I40E_AQC_MC_MAG_EN_VALID 0x100 516#define I40E_AQC_ADDR_VALID_MASK 0x1F0 517 u8 reserved[6]; 518 __le32 addr_high; 519 __le32 addr_low; 520}; 521 522I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read); 523 524struct i40e_aqc_mac_address_read_data { 525 u8 pf_lan_mac[6]; 526 u8 pf_san_mac[6]; 527 u8 port_mac[6]; 528 u8 pf_wol_mac[6]; 529}; 530 531I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data); 532 533/* Manage MAC Address Write Command (0x0108) */ 534struct i40e_aqc_mac_address_write { 535 __le16 command_flags; 536#define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 537#define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 538#define I40E_AQC_WRITE_TYPE_PORT 0x8000 539#define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000 540#define I40E_AQC_WRITE_TYPE_MASK 0xC000 541 542 __le16 mac_sah; 543 __le32 mac_sal; 544 u8 reserved[8]; 545}; 546 547I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write); 548 549/* PXE commands (0x011x) */ 550 551/* Clear PXE Command and response (direct 0x0110) */ 552struct i40e_aqc_clear_pxe { 553 u8 rx_cnt; 554 u8 reserved[15]; 555}; 556 557I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe); 558 559/* Switch configuration commands (0x02xx) */ 560 561/* Used by many indirect commands that only pass an seid and a buffer in the 562 * command 563 */ 564struct i40e_aqc_switch_seid { 565 __le16 seid; 566 u8 reserved[6]; 567 __le32 addr_high; 568 __le32 addr_low; 569}; 570 571I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid); 572 573/* Get Switch Configuration command (indirect 0x0200) 574 * uses i40e_aqc_switch_seid for the descriptor 575 */ 576struct i40e_aqc_get_switch_config_header_resp { 577 __le16 num_reported; 578 __le16 num_total; 579 u8 reserved[12]; 580}; 581 582I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp); 583 584struct i40e_aqc_switch_config_element_resp { 585 u8 element_type; 586#define I40E_AQ_SW_ELEM_TYPE_MAC 1 587#define I40E_AQ_SW_ELEM_TYPE_PF 2 588#define I40E_AQ_SW_ELEM_TYPE_VF 3 589#define I40E_AQ_SW_ELEM_TYPE_EMP 4 590#define I40E_AQ_SW_ELEM_TYPE_BMC 5 591#define I40E_AQ_SW_ELEM_TYPE_PV 16 592#define I40E_AQ_SW_ELEM_TYPE_VEB 17 593#define I40E_AQ_SW_ELEM_TYPE_PA 18 594#define I40E_AQ_SW_ELEM_TYPE_VSI 19 595 u8 revision; 596#define I40E_AQ_SW_ELEM_REV_1 1 597 __le16 seid; 598 __le16 uplink_seid; 599 __le16 downlink_seid; 600 u8 reserved[3]; 601 u8 connection_type; 602#define I40E_AQ_CONN_TYPE_REGULAR 0x1 603#define I40E_AQ_CONN_TYPE_DEFAULT 0x2 604#define I40E_AQ_CONN_TYPE_CASCADED 0x3 605 __le16 scheduler_id; 606 __le16 element_info; 607}; 608 609I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp); 610 611/* Get Switch Configuration (indirect 0x0200) 612 * an array of elements are returned in the response buffer 613 * the first in the array is the header, remainder are elements 614 */ 615struct i40e_aqc_get_switch_config_resp { 616 struct i40e_aqc_get_switch_config_header_resp header; 617 struct i40e_aqc_switch_config_element_resp element[1]; 618}; 619 620I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp); 621 622/* Add Statistics (direct 0x0201) 623 * Remove Statistics (direct 0x0202) 624 */ 625struct i40e_aqc_add_remove_statistics { 626 __le16 seid; 627 __le16 vlan; 628 __le16 stat_index; 629 u8 reserved[10]; 630}; 631 632I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics); 633 634/* Set Port Parameters command (direct 0x0203) */ 635struct i40e_aqc_set_port_parameters { 636 __le16 command_flags; 637#define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1 638#define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */ 639#define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4 640 __le16 bad_frame_vsi; 641 __le16 default_seid; /* reserved for command */ 642 u8 reserved[10]; 643}; 644 645I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters); 646 647/* Get Switch Resource Allocation (indirect 0x0204) */ 648struct i40e_aqc_get_switch_resource_alloc { 649 u8 num_entries; /* reserved for command */ 650 u8 reserved[7]; 651 __le32 addr_high; 652 __le32 addr_low; 653}; 654 655I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc); 656 657/* expect an array of these structs in the response buffer */ 658struct i40e_aqc_switch_resource_alloc_element_resp { 659 u8 resource_type; 660#define I40E_AQ_RESOURCE_TYPE_VEB 0x0 661#define I40E_AQ_RESOURCE_TYPE_VSI 0x1 662#define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2 663#define I40E_AQ_RESOURCE_TYPE_STAG 0x3 664#define I40E_AQ_RESOURCE_TYPE_ETAG 0x4 665#define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5 666#define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6 667#define I40E_AQ_RESOURCE_TYPE_VLAN 0x7 668#define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8 669#define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9 670#define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA 671#define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB 672#define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC 673#define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD 674#define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF 675#define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10 676#define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11 677#define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12 678#define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13 679 u8 reserved1; 680 __le16 guaranteed; 681 __le16 total; 682 __le16 used; 683 __le16 total_unalloced; 684 u8 reserved2[6]; 685}; 686 687I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp); 688 689/* Add VSI (indirect 0x0210) 690 * this indirect command uses struct i40e_aqc_vsi_properties_data 691 * as the indirect buffer (128 bytes) 692 * 693 * Update VSI (indirect 0x211) 694 * uses the same data structure as Add VSI 695 * 696 * Get VSI (indirect 0x0212) 697 * uses the same completion and data structure as Add VSI 698 */ 699struct i40e_aqc_add_get_update_vsi { 700 __le16 uplink_seid; 701 u8 connection_type; 702#define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1 703#define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2 704#define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3 705 u8 reserved1; 706 u8 vf_id; 707 u8 reserved2; 708 __le16 vsi_flags; 709#define I40E_AQ_VSI_TYPE_SHIFT 0x0 710#define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT) 711#define I40E_AQ_VSI_TYPE_VF 0x0 712#define I40E_AQ_VSI_TYPE_VMDQ2 0x1 713#define I40E_AQ_VSI_TYPE_PF 0x2 714#define I40E_AQ_VSI_TYPE_EMP_MNG 0x3 715#define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4 716 __le32 addr_high; 717 __le32 addr_low; 718}; 719 720I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi); 721 722struct i40e_aqc_add_get_update_vsi_completion { 723 __le16 seid; 724 __le16 vsi_number; 725 __le16 vsi_used; 726 __le16 vsi_free; 727 __le32 addr_high; 728 __le32 addr_low; 729}; 730 731I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion); 732 733struct i40e_aqc_vsi_properties_data { 734 /* first 96 byte are written by SW */ 735 __le16 valid_sections; 736#define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001 737#define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002 738#define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004 739#define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008 740#define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010 741#define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020 742#define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040 743#define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080 744#define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100 745#define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200 746 /* switch section */ 747 __le16 switch_id; /* 12bit id combined with flags below */ 748#define I40E_AQ_VSI_SW_ID_SHIFT 0x0000 749#define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT) 750#define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000 751#define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000 752#define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000 753 u8 sw_reserved[2]; 754 /* security section */ 755 u8 sec_flags; 756#define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01 757#define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02 758#define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04 759 u8 sec_reserved; 760 /* VLAN section */ 761 __le16 pvid; /* VLANS include priority bits */ 762 __le16 fcoe_pvid; 763 u8 port_vlan_flags; 764#define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00 765#define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ 766 I40E_AQ_VSI_PVLAN_MODE_SHIFT) 767#define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01 768#define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02 769#define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03 770#define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04 771#define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03 772#define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \ 773 I40E_AQ_VSI_PVLAN_EMOD_SHIFT) 774#define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0 775#define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08 776#define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10 777#define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 778 u8 pvlan_reserved[3]; 779 /* ingress egress up sections */ 780 __le32 ingress_table; /* bitmap, 3 bits per up */ 781#define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0 782#define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \ 783 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT) 784#define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3 785#define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \ 786 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT) 787#define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6 788#define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \ 789 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT) 790#define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9 791#define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \ 792 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT) 793#define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12 794#define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \ 795 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT) 796#define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15 797#define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \ 798 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT) 799#define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18 800#define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \ 801 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT) 802#define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21 803#define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \ 804 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT) 805 __le32 egress_table; /* same defines as for ingress table */ 806 /* cascaded PV section */ 807 __le16 cas_pv_tag; 808 u8 cas_pv_flags; 809#define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00 810#define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \ 811 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT) 812#define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00 813#define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01 814#define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02 815#define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10 816#define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20 817#define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40 818 u8 cas_pv_reserved; 819 /* queue mapping section */ 820 __le16 mapping_flags; 821#define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0 822#define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1 823 __le16 queue_mapping[16]; 824#define I40E_AQ_VSI_QUEUE_SHIFT 0x0 825#define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT) 826 __le16 tc_mapping[8]; 827#define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 828#define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ 829 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) 830#define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 831#define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ 832 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT) 833 /* queueing option section */ 834 u8 queueing_opt_flags; 835#define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10 836#define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 837 u8 queueing_opt_reserved[3]; 838 /* scheduler section */ 839 u8 up_enable_bits; 840 u8 sched_reserved; 841 /* outer up section */ 842 __le32 outer_up_table; /* same structure and defines as ingress table */ 843 u8 cmd_reserved[8]; 844 /* last 32 bytes are written by FW */ 845 __le16 qs_handle[8]; 846#define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF 847 __le16 stat_counter_idx; 848 __le16 sched_id; 849 u8 resp_reserved[12]; 850}; 851 852I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data); 853 854/* Add Port Virtualizer (direct 0x0220) 855 * also used for update PV (direct 0x0221) but only flags are used 856 * (IS_CTRL_PORT only works on add PV) 857 */ 858struct i40e_aqc_add_update_pv { 859 __le16 command_flags; 860#define I40E_AQC_PV_FLAG_PV_TYPE 0x1 861#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2 862#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4 863#define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8 864 __le16 uplink_seid; 865 __le16 connected_seid; 866 u8 reserved[10]; 867}; 868 869I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv); 870 871struct i40e_aqc_add_update_pv_completion { 872 /* reserved for update; for add also encodes error if rc == ENOSPC */ 873 __le16 pv_seid; 874#define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1 875#define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2 876#define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4 877#define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8 878 u8 reserved[14]; 879}; 880 881I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion); 882 883/* Get PV Params (direct 0x0222) 884 * uses i40e_aqc_switch_seid for the descriptor 885 */ 886 887struct i40e_aqc_get_pv_params_completion { 888 __le16 seid; 889 __le16 default_stag; 890 __le16 pv_flags; /* same flags as add_pv */ 891#define I40E_AQC_GET_PV_PV_TYPE 0x1 892#define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2 893#define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4 894 u8 reserved[8]; 895 __le16 default_port_seid; 896}; 897 898I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion); 899 900/* Add VEB (direct 0x0230) */ 901struct i40e_aqc_add_veb { 902 __le16 uplink_seid; 903 __le16 downlink_seid; 904 __le16 veb_flags; 905#define I40E_AQC_ADD_VEB_FLOATING 0x1 906#define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1 907#define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \ 908 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT) 909#define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2 910#define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4 911#define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 912 u8 enable_tcs; 913 u8 reserved[9]; 914}; 915 916I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb); 917 918struct i40e_aqc_add_veb_completion { 919 u8 reserved[6]; 920 __le16 switch_seid; 921 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */ 922 __le16 veb_seid; 923#define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1 924#define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2 925#define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4 926#define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8 927 __le16 statistic_index; 928 __le16 vebs_used; 929 __le16 vebs_free; 930}; 931 932I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion); 933 934/* Get VEB Parameters (direct 0x0232) 935 * uses i40e_aqc_switch_seid for the descriptor 936 */ 937struct i40e_aqc_get_veb_parameters_completion { 938 __le16 seid; 939 __le16 switch_id; 940 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */ 941 __le16 statistic_index; 942 __le16 vebs_used; 943 __le16 vebs_free; 944 u8 reserved[4]; 945}; 946 947I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion); 948 949/* Delete Element (direct 0x0243) 950 * uses the generic i40e_aqc_switch_seid 951 */ 952 953/* Add MAC-VLAN (indirect 0x0250) */ 954 955/* used for the command for most vlan commands */ 956struct i40e_aqc_macvlan { 957 __le16 num_addresses; 958 __le16 seid[3]; 959#define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0 960#define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \ 961 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 962#define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000 963 __le32 addr_high; 964 __le32 addr_low; 965}; 966 967I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan); 968 969/* indirect data for command and response */ 970struct i40e_aqc_add_macvlan_element_data { 971 u8 mac_addr[6]; 972 __le16 vlan_tag; 973 __le16 flags; 974#define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001 975#define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002 976#define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004 977#define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008 978 __le16 queue_number; 979#define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0 980#define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \ 981 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 982 /* response section */ 983 u8 match_method; 984#define I40E_AQC_MM_PERFECT_MATCH 0x01 985#define I40E_AQC_MM_HASH_MATCH 0x02 986#define I40E_AQC_MM_ERR_NO_RES 0xFF 987 u8 reserved1[3]; 988}; 989 990struct i40e_aqc_add_remove_macvlan_completion { 991 __le16 perfect_mac_used; 992 __le16 perfect_mac_free; 993 __le16 unicast_hash_free; 994 __le16 multicast_hash_free; 995 __le32 addr_high; 996 __le32 addr_low; 997}; 998 999I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion); 1000 1001/* Remove MAC-VLAN (indirect 0x0251) 1002 * uses i40e_aqc_macvlan for the descriptor 1003 * data points to an array of num_addresses of elements 1004 */ 1005 1006struct i40e_aqc_remove_macvlan_element_data { 1007 u8 mac_addr[6]; 1008 __le16 vlan_tag; 1009 u8 flags; 1010#define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01 1011#define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02 1012#define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08 1013#define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10 1014 u8 reserved[3]; 1015 /* reply section */ 1016 u8 error_code; 1017#define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0 1018#define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF 1019 u8 reply_reserved[3]; 1020}; 1021 1022/* Add VLAN (indirect 0x0252) 1023 * Remove VLAN (indirect 0x0253) 1024 * use the generic i40e_aqc_macvlan for the command 1025 */ 1026struct i40e_aqc_add_remove_vlan_element_data { 1027 __le16 vlan_tag; 1028 u8 vlan_flags; 1029/* flags for add VLAN */ 1030#define I40E_AQC_ADD_VLAN_LOCAL 0x1 1031#define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1 1032#define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT) 1033#define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0 1034#define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2 1035#define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4 1036#define I40E_AQC_VLAN_PTYPE_SHIFT 3 1037#define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT) 1038#define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0 1039#define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8 1040#define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10 1041#define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18 1042/* flags for remove VLAN */ 1043#define I40E_AQC_REMOVE_VLAN_ALL 0x1 1044 u8 reserved; 1045 u8 result; 1046/* flags for add VLAN */ 1047#define I40E_AQC_ADD_VLAN_SUCCESS 0x0 1048#define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE 1049#define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF 1050/* flags for remove VLAN */ 1051#define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0 1052#define I40E_AQC_REMOVE_VLAN_FAIL 0xFF 1053 u8 reserved1[3]; 1054}; 1055 1056struct i40e_aqc_add_remove_vlan_completion { 1057 u8 reserved[4]; 1058 __le16 vlans_used; 1059 __le16 vlans_free; 1060 __le32 addr_high; 1061 __le32 addr_low; 1062}; 1063 1064/* Set VSI Promiscuous Modes (direct 0x0254) */ 1065struct i40e_aqc_set_vsi_promiscuous_modes { 1066 __le16 promiscuous_flags; 1067 __le16 valid_flags; 1068/* flags used for both fields above */ 1069#define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01 1070#define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02 1071#define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04 1072#define I40E_AQC_SET_VSI_DEFAULT 0x08 1073#define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10 1074 __le16 seid; 1075#define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF 1076 __le16 vlan_tag; 1077#define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF 1078#define I40E_AQC_SET_VSI_VLAN_VALID 0x8000 1079 u8 reserved[8]; 1080}; 1081 1082I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes); 1083 1084/* Add S/E-tag command (direct 0x0255) 1085 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1086 */ 1087struct i40e_aqc_add_tag { 1088 __le16 flags; 1089#define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001 1090 __le16 seid; 1091#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0 1092#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1093 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT) 1094 __le16 tag; 1095 __le16 queue_number; 1096 u8 reserved[8]; 1097}; 1098 1099I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag); 1100 1101struct i40e_aqc_add_remove_tag_completion { 1102 u8 reserved[12]; 1103 __le16 tags_used; 1104 __le16 tags_free; 1105}; 1106 1107I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion); 1108 1109/* Remove S/E-tag command (direct 0x0256) 1110 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1111 */ 1112struct i40e_aqc_remove_tag { 1113 __le16 seid; 1114#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0 1115#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1116 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT) 1117 __le16 tag; 1118 u8 reserved[12]; 1119}; 1120 1121I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag); 1122 1123/* Add multicast E-Tag (direct 0x0257) 1124 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields 1125 * and no external data 1126 */ 1127struct i40e_aqc_add_remove_mcast_etag { 1128 __le16 pv_seid; 1129 __le16 etag; 1130 u8 num_unicast_etags; 1131 u8 reserved[3]; 1132 __le32 addr_high; /* address of array of 2-byte s-tags */ 1133 __le32 addr_low; 1134}; 1135 1136I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag); 1137 1138struct i40e_aqc_add_remove_mcast_etag_completion { 1139 u8 reserved[4]; 1140 __le16 mcast_etags_used; 1141 __le16 mcast_etags_free; 1142 __le32 addr_high; 1143 __le32 addr_low; 1144 1145}; 1146 1147I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion); 1148 1149/* Update S/E-Tag (direct 0x0259) */ 1150struct i40e_aqc_update_tag { 1151 __le16 seid; 1152#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0 1153#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1154 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT) 1155 __le16 old_tag; 1156 __le16 new_tag; 1157 u8 reserved[10]; 1158}; 1159 1160I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag); 1161 1162struct i40e_aqc_update_tag_completion { 1163 u8 reserved[12]; 1164 __le16 tags_used; 1165 __le16 tags_free; 1166}; 1167 1168I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion); 1169 1170/* Add Control Packet filter (direct 0x025A) 1171 * Remove Control Packet filter (direct 0x025B) 1172 * uses the i40e_aqc_add_oveb_cloud, 1173 * and the generic direct completion structure 1174 */ 1175struct i40e_aqc_add_remove_control_packet_filter { 1176 u8 mac[6]; 1177 __le16 etype; 1178 __le16 flags; 1179#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001 1180#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002 1181#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004 1182#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008 1183#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000 1184 __le16 seid; 1185#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0 1186#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \ 1187 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT) 1188 __le16 queue; 1189 u8 reserved[2]; 1190}; 1191 1192I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter); 1193 1194struct i40e_aqc_add_remove_control_packet_filter_completion { 1195 __le16 mac_etype_used; 1196 __le16 etype_used; 1197 __le16 mac_etype_free; 1198 __le16 etype_free; 1199 u8 reserved[8]; 1200}; 1201 1202I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion); 1203 1204/* Add Cloud filters (indirect 0x025C) 1205 * Remove Cloud filters (indirect 0x025D) 1206 * uses the i40e_aqc_add_remove_cloud_filters, 1207 * and the generic indirect completion structure 1208 */ 1209struct i40e_aqc_add_remove_cloud_filters { 1210 u8 num_filters; 1211 u8 reserved; 1212 __le16 seid; 1213#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0 1214#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \ 1215 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT) 1216 u8 reserved2[4]; 1217 __le32 addr_high; 1218 __le32 addr_low; 1219}; 1220 1221I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters); 1222 1223struct i40e_aqc_add_remove_cloud_filters_element_data { 1224 u8 outer_mac[6]; 1225 u8 inner_mac[6]; 1226 __le16 inner_vlan; 1227 union { 1228 struct { 1229 u8 reserved[12]; 1230 u8 data[4]; 1231 } v4; 1232 struct { 1233 u8 data[16]; 1234 } v6; 1235 } ipaddr; 1236 __le16 flags; 1237#define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0 1238#define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \ 1239 I40E_AQC_ADD_CLOUD_FILTER_SHIFT) 1240/* 0x0000 reserved */ 1241#define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001 1242/* 0x0002 reserved */ 1243#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003 1244#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004 1245/* 0x0005 reserved */ 1246#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006 1247/* 0x0007 reserved */ 1248/* 0x0008 reserved */ 1249#define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009 1250#define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A 1251#define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B 1252#define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C 1253 1254#define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080 1255#define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6 1256#define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0 1257#define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0 1258#define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100 1259 1260#define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9 1261#define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00 1262#define I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN 0 1263#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1 1264#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NGE 2 1265#define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3 1266 1267 __le32 tenant_id; 1268 u8 reserved[4]; 1269 __le16 queue_number; 1270#define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0 1271#define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \ 1272 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT) 1273 u8 reserved2[14]; 1274 /* response section */ 1275 u8 allocation_result; 1276#define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0 1277#define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF 1278 u8 response_reserved[7]; 1279}; 1280 1281struct i40e_aqc_remove_cloud_filters_completion { 1282 __le16 perfect_ovlan_used; 1283 __le16 perfect_ovlan_free; 1284 __le16 vlan_used; 1285 __le16 vlan_free; 1286 __le32 addr_high; 1287 __le32 addr_low; 1288}; 1289 1290I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion); 1291 1292/* Add Mirror Rule (indirect or direct 0x0260) 1293 * Delete Mirror Rule (indirect or direct 0x0261) 1294 * note: some rule types (4,5) do not use an external buffer. 1295 * take care to set the flags correctly. 1296 */ 1297struct i40e_aqc_add_delete_mirror_rule { 1298 __le16 seid; 1299 __le16 rule_type; 1300#define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0 1301#define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \ 1302 I40E_AQC_MIRROR_RULE_TYPE_SHIFT) 1303#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1 1304#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2 1305#define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3 1306#define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4 1307#define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5 1308 __le16 num_entries; 1309 __le16 destination; /* VSI for add, rule id for delete */ 1310 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */ 1311 __le32 addr_low; 1312}; 1313 1314I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule); 1315 1316struct i40e_aqc_add_delete_mirror_rule_completion { 1317 u8 reserved[2]; 1318 __le16 rule_id; /* only used on add */ 1319 __le16 mirror_rules_used; 1320 __le16 mirror_rules_free; 1321 __le32 addr_high; 1322 __le32 addr_low; 1323}; 1324 1325I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion); 1326 1327/* DCB 0x03xx*/ 1328 1329/* PFC Ignore (direct 0x0301) 1330 * the command and response use the same descriptor structure 1331 */ 1332struct i40e_aqc_pfc_ignore { 1333 u8 tc_bitmap; 1334 u8 command_flags; /* unused on response */ 1335#define I40E_AQC_PFC_IGNORE_SET 0x80 1336#define I40E_AQC_PFC_IGNORE_CLEAR 0x0 1337 u8 reserved[14]; 1338}; 1339 1340I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore); 1341 1342/* DCB Update (direct 0x0302) uses the i40e_aq_desc structure 1343 * with no parameters 1344 */ 1345 1346/* TX scheduler 0x04xx */ 1347 1348/* Almost all the indirect commands use 1349 * this generic struct to pass the SEID in param0 1350 */ 1351struct i40e_aqc_tx_sched_ind { 1352 __le16 vsi_seid; 1353 u8 reserved[6]; 1354 __le32 addr_high; 1355 __le32 addr_low; 1356}; 1357 1358I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind); 1359 1360/* Several commands respond with a set of queue set handles */ 1361struct i40e_aqc_qs_handles_resp { 1362 __le16 qs_handles[8]; 1363}; 1364 1365/* Configure VSI BW limits (direct 0x0400) */ 1366struct i40e_aqc_configure_vsi_bw_limit { 1367 __le16 vsi_seid; 1368 u8 reserved[2]; 1369 __le16 credit; 1370 u8 reserved1[2]; 1371 u8 max_credit; /* 0-3, limit = 2^max */ 1372 u8 reserved2[7]; 1373}; 1374 1375I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit); 1376 1377/* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406) 1378 * responds with i40e_aqc_qs_handles_resp 1379 */ 1380struct i40e_aqc_configure_vsi_ets_sla_bw_data { 1381 u8 tc_valid_bits; 1382 u8 reserved[15]; 1383 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */ 1384 1385 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1386 __le16 tc_bw_max[2]; 1387 u8 reserved1[28]; 1388}; 1389 1390I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data); 1391 1392/* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407) 1393 * responds with i40e_aqc_qs_handles_resp 1394 */ 1395struct i40e_aqc_configure_vsi_tc_bw_data { 1396 u8 tc_valid_bits; 1397 u8 reserved[3]; 1398 u8 tc_bw_credits[8]; 1399 u8 reserved1[4]; 1400 __le16 qs_handles[8]; 1401}; 1402 1403I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data); 1404 1405/* Query vsi bw configuration (indirect 0x0408) */ 1406struct i40e_aqc_query_vsi_bw_config_resp { 1407 u8 tc_valid_bits; 1408 u8 tc_suspended_bits; 1409 u8 reserved[14]; 1410 __le16 qs_handles[8]; 1411 u8 reserved1[4]; 1412 __le16 port_bw_limit; 1413 u8 reserved2[2]; 1414 u8 max_bw; /* 0-3, limit = 2^max */ 1415 u8 reserved3[23]; 1416}; 1417 1418I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp); 1419 1420/* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */ 1421struct i40e_aqc_query_vsi_ets_sla_config_resp { 1422 u8 tc_valid_bits; 1423 u8 reserved[3]; 1424 u8 share_credits[8]; 1425 __le16 credits[8]; 1426 1427 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1428 __le16 tc_bw_max[2]; 1429}; 1430 1431I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp); 1432 1433/* Configure Switching Component Bandwidth Limit (direct 0x0410) */ 1434struct i40e_aqc_configure_switching_comp_bw_limit { 1435 __le16 seid; 1436 u8 reserved[2]; 1437 __le16 credit; 1438 u8 reserved1[2]; 1439 u8 max_bw; /* 0-3, limit = 2^max */ 1440 u8 reserved2[7]; 1441}; 1442 1443I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit); 1444 1445/* Enable Physical Port ETS (indirect 0x0413) 1446 * Modify Physical Port ETS (indirect 0x0414) 1447 * Disable Physical Port ETS (indirect 0x0415) 1448 */ 1449struct i40e_aqc_configure_switching_comp_ets_data { 1450 u8 reserved[4]; 1451 u8 tc_valid_bits; 1452 u8 seepage; 1453#define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1 1454 u8 tc_strict_priority_flags; 1455 u8 reserved1[17]; 1456 u8 tc_bw_share_credits[8]; 1457 u8 reserved2[96]; 1458}; 1459 1460I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data); 1461 1462/* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ 1463struct i40e_aqc_configure_switching_comp_ets_bw_limit_data { 1464 u8 tc_valid_bits; 1465 u8 reserved[15]; 1466 __le16 tc_bw_credit[8]; 1467 1468 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1469 __le16 tc_bw_max[2]; 1470 u8 reserved1[28]; 1471}; 1472 1473I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_switching_comp_ets_bw_limit_data); 1474 1475/* Configure Switching Component Bandwidth Allocation per Tc 1476 * (indirect 0x0417) 1477 */ 1478struct i40e_aqc_configure_switching_comp_bw_config_data { 1479 u8 tc_valid_bits; 1480 u8 reserved[2]; 1481 u8 absolute_credits; /* bool */ 1482 u8 tc_bw_share_credits[8]; 1483 u8 reserved1[20]; 1484}; 1485 1486I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data); 1487 1488/* Query Switching Component Configuration (indirect 0x0418) */ 1489struct i40e_aqc_query_switching_comp_ets_config_resp { 1490 u8 tc_valid_bits; 1491 u8 reserved[35]; 1492 __le16 port_bw_limit; 1493 u8 reserved1[2]; 1494 u8 tc_bw_max; /* 0-3, limit = 2^max */ 1495 u8 reserved2[23]; 1496}; 1497 1498I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp); 1499 1500/* Query PhysicalPort ETS Configuration (indirect 0x0419) */ 1501struct i40e_aqc_query_port_ets_config_resp { 1502 u8 reserved[4]; 1503 u8 tc_valid_bits; 1504 u8 reserved1; 1505 u8 tc_strict_priority_bits; 1506 u8 reserved2; 1507 u8 tc_bw_share_credits[8]; 1508 __le16 tc_bw_limits[8]; 1509 1510 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */ 1511 __le16 tc_bw_max[2]; 1512 u8 reserved3[32]; 1513}; 1514 1515I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp); 1516 1517/* Query Switching Component Bandwidth Allocation per Traffic Type 1518 * (indirect 0x041A) 1519 */ 1520struct i40e_aqc_query_switching_comp_bw_config_resp { 1521 u8 tc_valid_bits; 1522 u8 reserved[2]; 1523 u8 absolute_credits_enable; /* bool */ 1524 u8 tc_bw_share_credits[8]; 1525 __le16 tc_bw_limits[8]; 1526 1527 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1528 __le16 tc_bw_max[2]; 1529}; 1530 1531I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp); 1532 1533/* Suspend/resume port TX traffic 1534 * (direct 0x041B and 0x041C) uses the generic SEID struct 1535 */ 1536 1537/* Configure partition BW 1538 * (indirect 0x041D) 1539 */ 1540struct i40e_aqc_configure_partition_bw_data { 1541 __le16 pf_valid_bits; 1542 u8 min_bw[16]; /* guaranteed bandwidth */ 1543 u8 max_bw[16]; /* bandwidth limit */ 1544}; 1545 1546I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data); 1547 1548/* Get and set the active HMC resource profile and status. 1549 * (direct 0x0500) and (direct 0x0501) 1550 */ 1551struct i40e_aq_get_set_hmc_resource_profile { 1552 u8 pm_profile; 1553 u8 pe_vf_enabled; 1554 u8 reserved[14]; 1555}; 1556 1557I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile); 1558 1559enum i40e_aq_hmc_profile { 1560 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */ 1561 I40E_HMC_PROFILE_DEFAULT = 1, 1562 I40E_HMC_PROFILE_FAVOR_VF = 2, 1563 I40E_HMC_PROFILE_EQUAL = 3, 1564}; 1565 1566#define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK 0xF 1567#define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK 0x3F 1568 1569/* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */ 1570 1571/* set in param0 for get phy abilities to report qualified modules */ 1572#define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001 1573#define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002 1574 1575enum i40e_aq_phy_type { 1576 I40E_PHY_TYPE_SGMII = 0x0, 1577 I40E_PHY_TYPE_1000BASE_KX = 0x1, 1578 I40E_PHY_TYPE_10GBASE_KX4 = 0x2, 1579 I40E_PHY_TYPE_10GBASE_KR = 0x3, 1580 I40E_PHY_TYPE_40GBASE_KR4 = 0x4, 1581 I40E_PHY_TYPE_XAUI = 0x5, 1582 I40E_PHY_TYPE_XFI = 0x6, 1583 I40E_PHY_TYPE_SFI = 0x7, 1584 I40E_PHY_TYPE_XLAUI = 0x8, 1585 I40E_PHY_TYPE_XLPPI = 0x9, 1586 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA, 1587 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB, 1588 I40E_PHY_TYPE_10GBASE_AOC = 0xC, 1589 I40E_PHY_TYPE_40GBASE_AOC = 0xD, 1590 I40E_PHY_TYPE_100BASE_TX = 0x11, 1591 I40E_PHY_TYPE_1000BASE_T = 0x12, 1592 I40E_PHY_TYPE_10GBASE_T = 0x13, 1593 I40E_PHY_TYPE_10GBASE_SR = 0x14, 1594 I40E_PHY_TYPE_10GBASE_LR = 0x15, 1595 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16, 1596 I40E_PHY_TYPE_10GBASE_CR1 = 0x17, 1597 I40E_PHY_TYPE_40GBASE_CR4 = 0x18, 1598 I40E_PHY_TYPE_40GBASE_SR4 = 0x19, 1599 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, 1600 I40E_PHY_TYPE_1000BASE_SX = 0x1B, 1601 I40E_PHY_TYPE_1000BASE_LX = 0x1C, 1602 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, 1603 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, 1604 I40E_PHY_TYPE_MAX 1605}; 1606 1607#define I40E_LINK_SPEED_100MB_SHIFT 0x1 1608#define I40E_LINK_SPEED_1000MB_SHIFT 0x2 1609#define I40E_LINK_SPEED_10GB_SHIFT 0x3 1610#define I40E_LINK_SPEED_40GB_SHIFT 0x4 1611#define I40E_LINK_SPEED_20GB_SHIFT 0x5 1612 1613enum i40e_aq_link_speed { 1614 I40E_LINK_SPEED_UNKNOWN = 0, 1615 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT), 1616 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT), 1617 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT), 1618 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT), 1619 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT) 1620}; 1621 1622struct i40e_aqc_module_desc { 1623 u8 oui[3]; 1624 u8 reserved1; 1625 u8 part_number[16]; 1626 u8 revision[4]; 1627 u8 reserved2[8]; 1628}; 1629 1630I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc); 1631 1632struct i40e_aq_get_phy_abilities_resp { 1633 __le32 phy_type; /* bitmap using the above enum for offsets */ 1634 u8 link_speed; /* bitmap using the above enum bit patterns */ 1635 u8 abilities; 1636#define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01 1637#define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02 1638#define I40E_AQ_PHY_FLAG_LOW_POWER 0x04 1639#define I40E_AQ_PHY_LINK_ENABLED 0x08 1640#define I40E_AQ_PHY_AN_ENABLED 0x10 1641#define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20 1642 __le16 eee_capability; 1643#define I40E_AQ_EEE_100BASE_TX 0x0002 1644#define I40E_AQ_EEE_1000BASE_T 0x0004 1645#define I40E_AQ_EEE_10GBASE_T 0x0008 1646#define I40E_AQ_EEE_1000BASE_KX 0x0010 1647#define I40E_AQ_EEE_10GBASE_KX4 0x0020 1648#define I40E_AQ_EEE_10GBASE_KR 0x0040 1649 __le32 eeer_val; 1650 u8 d3_lpan; 1651#define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 1652 u8 reserved[3]; 1653 u8 phy_id[4]; 1654 u8 module_type[3]; 1655 u8 qualified_module_count; 1656#define I40E_AQ_PHY_MAX_QMS 16 1657 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; 1658}; 1659 1660I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp); 1661 1662/* Set PHY Config (direct 0x0601) */ 1663struct i40e_aq_set_phy_config { /* same bits as above in all */ 1664 __le32 phy_type; 1665 u8 link_speed; 1666 u8 abilities; 1667/* bits 0-2 use the values from get_phy_abilities_resp */ 1668#define I40E_AQ_PHY_ENABLE_LINK 0x08 1669#define I40E_AQ_PHY_ENABLE_AN 0x10 1670#define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20 1671 __le16 eee_capability; 1672 __le32 eeer; 1673 u8 low_power_ctrl; 1674 u8 reserved[3]; 1675}; 1676 1677I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); 1678 1679/* Set MAC Config command data structure (direct 0x0603) */ 1680struct i40e_aq_set_mac_config { 1681 __le16 max_frame_size; 1682 u8 params; 1683#define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04 1684#define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78 1685#define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3 1686#define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0 1687#define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF 1688#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9 1689#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8 1690#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7 1691#define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6 1692#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5 1693#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4 1694#define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3 1695#define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2 1696#define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1 1697 u8 tx_timer_priority; /* bitmap */ 1698 __le16 tx_timer_value; 1699 __le16 fc_refresh_threshold; 1700 u8 reserved[8]; 1701}; 1702 1703I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config); 1704 1705/* Restart Auto-Negotiation (direct 0x605) */ 1706struct i40e_aqc_set_link_restart_an { 1707 u8 command; 1708#define I40E_AQ_PHY_RESTART_AN 0x02 1709#define I40E_AQ_PHY_LINK_ENABLE 0x04 1710 u8 reserved[15]; 1711}; 1712 1713I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an); 1714 1715/* Get Link Status cmd & response data structure (direct 0x0607) */ 1716struct i40e_aqc_get_link_status { 1717 __le16 command_flags; /* only field set on command */ 1718#define I40E_AQ_LSE_MASK 0x3 1719#define I40E_AQ_LSE_NOP 0x0 1720#define I40E_AQ_LSE_DISABLE 0x2 1721#define I40E_AQ_LSE_ENABLE 0x3 1722/* only response uses this flag */ 1723#define I40E_AQ_LSE_IS_ENABLED 0x1 1724 u8 phy_type; /* i40e_aq_phy_type */ 1725 u8 link_speed; /* i40e_aq_link_speed */ 1726 u8 link_info; 1727#define I40E_AQ_LINK_UP 0x01 /* obsolete */ 1728#define I40E_AQ_LINK_UP_FUNCTION 0x01 1729#define I40E_AQ_LINK_FAULT 0x02 1730#define I40E_AQ_LINK_FAULT_TX 0x04 1731#define I40E_AQ_LINK_FAULT_RX 0x08 1732#define I40E_AQ_LINK_FAULT_REMOTE 0x10 1733#define I40E_AQ_LINK_UP_PORT 0x20 1734#define I40E_AQ_MEDIA_AVAILABLE 0x40 1735#define I40E_AQ_SIGNAL_DETECT 0x80 1736 u8 an_info; 1737#define I40E_AQ_AN_COMPLETED 0x01 1738#define I40E_AQ_LP_AN_ABILITY 0x02 1739#define I40E_AQ_PD_FAULT 0x04 1740#define I40E_AQ_FEC_EN 0x08 1741#define I40E_AQ_PHY_LOW_POWER 0x10 1742#define I40E_AQ_LINK_PAUSE_TX 0x20 1743#define I40E_AQ_LINK_PAUSE_RX 0x40 1744#define I40E_AQ_QUALIFIED_MODULE 0x80 1745 u8 ext_info; 1746#define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01 1747#define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02 1748#define I40E_AQ_LINK_TX_SHIFT 0x02 1749#define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT) 1750#define I40E_AQ_LINK_TX_ACTIVE 0x00 1751#define I40E_AQ_LINK_TX_DRAINED 0x01 1752#define I40E_AQ_LINK_TX_FLUSHED 0x03 1753#define I40E_AQ_LINK_FORCED_40G 0x10 1754 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ 1755 __le16 max_frame_size; 1756 u8 config; 1757#define I40E_AQ_CONFIG_CRC_ENA 0x04 1758#define I40E_AQ_CONFIG_PACING_MASK 0x78 1759 u8 reserved[5]; 1760}; 1761 1762I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status); 1763 1764/* Set event mask command (direct 0x613) */ 1765struct i40e_aqc_set_phy_int_mask { 1766 u8 reserved[8]; 1767 __le16 event_mask; 1768#define I40E_AQ_EVENT_LINK_UPDOWN 0x0002 1769#define I40E_AQ_EVENT_MEDIA_NA 0x0004 1770#define I40E_AQ_EVENT_LINK_FAULT 0x0008 1771#define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010 1772#define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020 1773#define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040 1774#define I40E_AQ_EVENT_AN_COMPLETED 0x0080 1775#define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100 1776#define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200 1777 u8 reserved1[6]; 1778}; 1779 1780I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask); 1781 1782/* Get Local AN advt register (direct 0x0614) 1783 * Set Local AN advt register (direct 0x0615) 1784 * Get Link Partner AN advt register (direct 0x0616) 1785 */ 1786struct i40e_aqc_an_advt_reg { 1787 __le32 local_an_reg0; 1788 __le16 local_an_reg1; 1789 u8 reserved[10]; 1790}; 1791 1792I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg); 1793 1794/* Set Loopback mode (0x0618) */ 1795struct i40e_aqc_set_lb_mode { 1796 __le16 lb_mode; 1797#define I40E_AQ_LB_PHY_LOCAL 0x01 1798#define I40E_AQ_LB_PHY_REMOTE 0x02 1799#define I40E_AQ_LB_MAC_LOCAL 0x04 1800 u8 reserved[14]; 1801}; 1802 1803I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode); 1804 1805/* Set PHY Debug command (0x0622) */ 1806struct i40e_aqc_set_phy_debug { 1807 u8 command_flags; 1808#define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02 1809#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2 1810#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \ 1811 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT) 1812#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00 1813#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01 1814#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02 1815#define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10 1816 u8 reserved[15]; 1817}; 1818 1819I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); 1820 1821enum i40e_aq_phy_reg_type { 1822 I40E_AQC_PHY_REG_INTERNAL = 0x1, 1823 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, 1824 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3 1825}; 1826 1827/* NVM Read command (indirect 0x0701) 1828 * NVM Erase commands (direct 0x0702) 1829 * NVM Update commands (indirect 0x0703) 1830 */ 1831struct i40e_aqc_nvm_update { 1832 u8 command_flags; 1833#define I40E_AQ_NVM_LAST_CMD 0x01 1834#define I40E_AQ_NVM_FLASH_ONLY 0x80 1835 u8 module_pointer; 1836 __le16 length; 1837 __le32 offset; 1838 __le32 addr_high; 1839 __le32 addr_low; 1840}; 1841 1842I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); 1843 1844/* NVM Config Read (indirect 0x0704) */ 1845struct i40e_aqc_nvm_config_read { 1846 __le16 cmd_flags; 1847#define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1 1848#define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0 1849#define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1 1850 __le16 element_count; 1851 __le16 element_id; /* Feature/field ID */ 1852 __le16 element_id_msw; /* MSWord of field ID */ 1853 __le32 address_high; 1854 __le32 address_low; 1855}; 1856 1857I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read); 1858 1859/* NVM Config Write (indirect 0x0705) */ 1860struct i40e_aqc_nvm_config_write { 1861 __le16 cmd_flags; 1862 __le16 element_count; 1863 u8 reserved[4]; 1864 __le32 address_high; 1865 __le32 address_low; 1866}; 1867 1868I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write); 1869 1870/* Used for 0x0704 as well as for 0x0705 commands */ 1871#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1 1872#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT) 1873#define I40E_AQ_ANVM_FEATURE 0 1874#define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT) 1875struct i40e_aqc_nvm_config_data_feature { 1876 __le16 feature_id; 1877#define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01 1878#define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08 1879#define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10 1880 __le16 feature_options; 1881 __le16 feature_selection; 1882}; 1883 1884I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature); 1885 1886struct i40e_aqc_nvm_config_data_immediate_field { 1887 __le32 field_id; 1888 __le32 field_value; 1889 __le16 field_options; 1890 __le16 reserved; 1891}; 1892 1893I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field); 1894 1895/* OEM Post Update (indirect 0x0720) 1896 * no command data struct used 1897 */ 1898 struct i40e_aqc_nvm_oem_post_update { 1899#define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01 1900 u8 sel_data; 1901 u8 reserved[7]; 1902}; 1903 1904I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update); 1905 1906struct i40e_aqc_nvm_oem_post_update_buffer { 1907 u8 str_len; 1908 u8 dev_addr; 1909 __le16 eeprom_addr; 1910 u8 data[36]; 1911}; 1912 1913I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer); 1914 1915/* Send to PF command (indirect 0x0801) id is only used by PF 1916 * Send to VF command (indirect 0x0802) id is only used by PF 1917 * Send to Peer PF command (indirect 0x0803) 1918 */ 1919struct i40e_aqc_pf_vf_message { 1920 __le32 id; 1921 u8 reserved[4]; 1922 __le32 addr_high; 1923 __le32 addr_low; 1924}; 1925 1926I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); 1927 1928/* Alternate structure */ 1929 1930/* Direct write (direct 0x0900) 1931 * Direct read (direct 0x0902) 1932 */ 1933struct i40e_aqc_alternate_write { 1934 __le32 address0; 1935 __le32 data0; 1936 __le32 address1; 1937 __le32 data1; 1938}; 1939 1940I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write); 1941 1942/* Indirect write (indirect 0x0901) 1943 * Indirect read (indirect 0x0903) 1944 */ 1945 1946struct i40e_aqc_alternate_ind_write { 1947 __le32 address; 1948 __le32 length; 1949 __le32 addr_high; 1950 __le32 addr_low; 1951}; 1952 1953I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write); 1954 1955/* Done alternate write (direct 0x0904) 1956 * uses i40e_aq_desc 1957 */ 1958struct i40e_aqc_alternate_write_done { 1959 __le16 cmd_flags; 1960#define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1 1961#define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0 1962#define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1 1963#define I40E_AQ_ALTERNATE_RESET_NEEDED 2 1964 u8 reserved[14]; 1965}; 1966 1967I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done); 1968 1969/* Set OEM mode (direct 0x0905) */ 1970struct i40e_aqc_alternate_set_mode { 1971 __le32 mode; 1972#define I40E_AQ_ALTERNATE_MODE_NONE 0 1973#define I40E_AQ_ALTERNATE_MODE_OEM 1 1974 u8 reserved[12]; 1975}; 1976 1977I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode); 1978 1979/* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */ 1980 1981/* async events 0x10xx */ 1982 1983/* Lan Queue Overflow Event (direct, 0x1001) */ 1984struct i40e_aqc_lan_overflow { 1985 __le32 prtdcb_rupto; 1986 __le32 otx_ctl; 1987 u8 reserved[8]; 1988}; 1989 1990I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow); 1991 1992/* Get LLDP MIB (indirect 0x0A00) */ 1993struct i40e_aqc_lldp_get_mib { 1994 u8 type; 1995 u8 reserved1; 1996#define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3 1997#define I40E_AQ_LLDP_MIB_LOCAL 0x0 1998#define I40E_AQ_LLDP_MIB_REMOTE 0x1 1999#define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2 2000#define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC 2001#define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2 2002#define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0 2003#define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1 2004#define I40E_AQ_LLDP_TX_SHIFT 0x4 2005#define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT) 2006/* TX pause flags use I40E_AQ_LINK_TX_* above */ 2007 __le16 local_len; 2008 __le16 remote_len; 2009 u8 reserved2[2]; 2010 __le32 addr_high; 2011 __le32 addr_low; 2012}; 2013 2014I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib); 2015 2016/* Configure LLDP MIB Change Event (direct 0x0A01) 2017 * also used for the event (with type in the command field) 2018 */ 2019struct i40e_aqc_lldp_update_mib { 2020 u8 command; 2021#define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 2022#define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1 2023 u8 reserved[7]; 2024 __le32 addr_high; 2025 __le32 addr_low; 2026}; 2027 2028I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib); 2029 2030/* Add LLDP TLV (indirect 0x0A02) 2031 * Delete LLDP TLV (indirect 0x0A04) 2032 */ 2033struct i40e_aqc_lldp_add_tlv { 2034 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2035 u8 reserved1[1]; 2036 __le16 len; 2037 u8 reserved2[4]; 2038 __le32 addr_high; 2039 __le32 addr_low; 2040}; 2041 2042I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv); 2043 2044/* Update LLDP TLV (indirect 0x0A03) */ 2045struct i40e_aqc_lldp_update_tlv { 2046 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2047 u8 reserved; 2048 __le16 old_len; 2049 __le16 new_offset; 2050 __le16 new_len; 2051 __le32 addr_high; 2052 __le32 addr_low; 2053}; 2054 2055I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv); 2056 2057/* Stop LLDP (direct 0x0A05) */ 2058struct i40e_aqc_lldp_stop { 2059 u8 command; 2060#define I40E_AQ_LLDP_AGENT_STOP 0x0 2061#define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1 2062 u8 reserved[15]; 2063}; 2064 2065I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop); 2066 2067/* Start LLDP (direct 0x0A06) */ 2068 2069struct i40e_aqc_lldp_start { 2070 u8 command; 2071#define I40E_AQ_LLDP_AGENT_START 0x1 2072 u8 reserved[15]; 2073}; 2074 2075I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start); 2076 2077/* Get CEE DCBX Oper Config (0x0A07) 2078 * uses the generic descriptor struct 2079 * returns below as indirect response 2080 */ 2081 2082#define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0 2083#define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT) 2084#define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3 2085#define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT) 2086#define I40E_AQC_CEE_APP_FIP_SHIFT 0x8 2087#define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2088 2089#define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0 2090#define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT) 2091#define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3 2092#define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT) 2093#define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8 2094#define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT) 2095#define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8 2096#define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT) 2097#define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB 2098#define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT) 2099#define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10 2100#define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT) 2101 2102/* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with 2103 * word boundary layout issues, which the Linux compilers silently deal 2104 * with by adding padding, making the actual struct larger than designed. 2105 * However, the FW compiler for the NIC is less lenient and complains 2106 * about the struct. Hence, the struct defined here has an extra byte in 2107 * fields reserved3 and reserved4 to directly acknowledge that padding, 2108 * and the new length is used in the length check macro. 2109 */ 2110struct i40e_aqc_get_cee_dcb_cfg_v1_resp { 2111 u8 reserved1; 2112 u8 oper_num_tc; 2113 u8 oper_prio_tc[4]; 2114 u8 reserved2; 2115 u8 oper_tc_bw[8]; 2116 u8 oper_pfc_en; 2117 u8 reserved3[2]; 2118 __le16 oper_app_prio; 2119 u8 reserved4[2]; 2120 __le16 tlv_status; 2121}; 2122 2123I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp); 2124 2125struct i40e_aqc_get_cee_dcb_cfg_resp { 2126 u8 oper_num_tc; 2127 u8 oper_prio_tc[4]; 2128 u8 oper_tc_bw[8]; 2129 u8 oper_pfc_en; 2130 __le16 oper_app_prio; 2131 __le32 tlv_status; 2132 u8 reserved[12]; 2133}; 2134 2135I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp); 2136 2137/* Set Local LLDP MIB (indirect 0x0A08) 2138 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx 2139 */ 2140struct i40e_aqc_lldp_set_local_mib { 2141#define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0 2142#define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \ 2143 SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT) 2144#define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0 2145#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1) 2146#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK (1 << \ 2147 SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT) 2148#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1 2149 u8 type; 2150 u8 reserved0; 2151 __le16 length; 2152 u8 reserved1[4]; 2153 __le32 address_high; 2154 __le32 address_low; 2155}; 2156 2157I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib); 2158 2159struct i40e_aqc_lldp_set_local_mib_resp { 2160#define SET_LOCAL_MIB_RESP_EVENT_TRIGGERED_MASK 0x01 2161 u8 status; 2162 u8 reserved[15]; 2163}; 2164 2165I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_lldp_set_local_mib_resp); 2166 2167/* Stop/Start LLDP Agent (direct 0x0A09) 2168 * Used for stopping/starting specific LLDP agent. e.g. DCBx 2169 */ 2170struct i40e_aqc_lldp_stop_start_specific_agent { 2171#define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0 2172#define I40E_AQC_START_SPECIFIC_AGENT_MASK (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT) 2173 u8 command; 2174 u8 reserved[15]; 2175}; 2176 2177I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent); 2178 2179/* Add Udp Tunnel command and completion (direct 0x0B00) */ 2180struct i40e_aqc_add_udp_tunnel { 2181 __le16 udp_port; 2182 u8 reserved0[3]; 2183 u8 protocol_type; 2184#define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00 2185#define I40E_AQC_TUNNEL_TYPE_NGE 0x01 2186#define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10 2187 u8 reserved1[10]; 2188}; 2189 2190I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel); 2191 2192struct i40e_aqc_add_udp_tunnel_completion { 2193 __le16 udp_port; 2194 u8 filter_entry_index; 2195 u8 multiple_pfs; 2196#define I40E_AQC_SINGLE_PF 0x0 2197#define I40E_AQC_MULTIPLE_PFS 0x1 2198 u8 total_filters; 2199 u8 reserved[11]; 2200}; 2201 2202I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion); 2203 2204/* remove UDP Tunnel command (0x0B01) */ 2205struct i40e_aqc_remove_udp_tunnel { 2206 u8 reserved[2]; 2207 u8 index; /* 0 to 15 */ 2208 u8 reserved2[13]; 2209}; 2210 2211I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel); 2212 2213struct i40e_aqc_del_udp_tunnel_completion { 2214 __le16 udp_port; 2215 u8 index; /* 0 to 15 */ 2216 u8 multiple_pfs; 2217 u8 total_filters_used; 2218 u8 reserved1[11]; 2219}; 2220 2221I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion); 2222 2223/* tunnel key structure 0x0B10 */ 2224 2225struct i40e_aqc_tunnel_key_structure { 2226 u8 key1_off; 2227 u8 key2_off; 2228 u8 key1_len; /* 0 to 15 */ 2229 u8 key2_len; /* 0 to 15 */ 2230 u8 flags; 2231#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 2232/* response flags */ 2233#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 2234#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 2235#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 2236 u8 network_key_index; 2237#define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0 2238#define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1 2239#define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2 2240#define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3 2241 u8 reserved[10]; 2242}; 2243 2244I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure); 2245 2246/* OEM mode commands (direct 0xFE0x) */ 2247struct i40e_aqc_oem_param_change { 2248 __le32 param_type; 2249#define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0 2250#define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1 2251#define I40E_AQ_OEM_PARAM_MAC 2 2252 __le32 param_value1; 2253 __le16 param_value2; 2254 u8 reserved[6]; 2255}; 2256 2257I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change); 2258 2259struct i40e_aqc_oem_state_change { 2260 __le32 state; 2261#define I40E_AQ_OEM_STATE_LINK_DOWN 0x0 2262#define I40E_AQ_OEM_STATE_LINK_UP 0x1 2263 u8 reserved[12]; 2264}; 2265 2266I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change); 2267 2268/* Initialize OCSD (0xFE02, direct) */ 2269struct i40e_aqc_opc_oem_ocsd_initialize { 2270 u8 type_status; 2271 u8 reserved1[3]; 2272 __le32 ocsd_memory_block_addr_high; 2273 __le32 ocsd_memory_block_addr_low; 2274 __le32 requested_update_interval; 2275}; 2276 2277I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize); 2278 2279/* Initialize OCBB (0xFE03, direct) */ 2280struct i40e_aqc_opc_oem_ocbb_initialize { 2281 u8 type_status; 2282 u8 reserved1[3]; 2283 __le32 ocbb_memory_block_addr_high; 2284 __le32 ocbb_memory_block_addr_low; 2285 u8 reserved2[4]; 2286}; 2287 2288I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize); 2289 2290/* debug commands */ 2291 2292/* get device id (0xFF00) uses the generic structure */ 2293 2294/* set test more (0xFF01, internal) */ 2295 2296struct i40e_acq_set_test_mode { 2297 u8 mode; 2298#define I40E_AQ_TEST_PARTIAL 0 2299#define I40E_AQ_TEST_FULL 1 2300#define I40E_AQ_TEST_NVM 2 2301 u8 reserved[3]; 2302 u8 command; 2303#define I40E_AQ_TEST_OPEN 0 2304#define I40E_AQ_TEST_CLOSE 1 2305#define I40E_AQ_TEST_INC 2 2306 u8 reserved2[3]; 2307 __le32 address_high; 2308 __le32 address_low; 2309}; 2310 2311I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode); 2312 2313/* Debug Read Register command (0xFF03) 2314 * Debug Write Register command (0xFF04) 2315 */ 2316struct i40e_aqc_debug_reg_read_write { 2317 __le32 reserved; 2318 __le32 address; 2319 __le32 value_high; 2320 __le32 value_low; 2321}; 2322 2323I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write); 2324 2325/* Scatter/gather Reg Read (indirect 0xFF05) 2326 * Scatter/gather Reg Write (indirect 0xFF06) 2327 */ 2328 2329/* i40e_aq_desc is used for the command */ 2330struct i40e_aqc_debug_reg_sg_element_data { 2331 __le32 address; 2332 __le32 value; 2333}; 2334 2335/* Debug Modify register (direct 0xFF07) */ 2336struct i40e_aqc_debug_modify_reg { 2337 __le32 address; 2338 __le32 value; 2339 __le32 clear_mask; 2340 __le32 set_mask; 2341}; 2342 2343I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg); 2344 2345/* dump internal data (0xFF08, indirect) */ 2346 2347#define I40E_AQ_CLUSTER_ID_AUX 0 2348#define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1 2349#define I40E_AQ_CLUSTER_ID_TXSCHED 2 2350#define I40E_AQ_CLUSTER_ID_HMC 3 2351#define I40E_AQ_CLUSTER_ID_MAC0 4 2352#define I40E_AQ_CLUSTER_ID_MAC1 5 2353#define I40E_AQ_CLUSTER_ID_MAC2 6 2354#define I40E_AQ_CLUSTER_ID_MAC3 7 2355#define I40E_AQ_CLUSTER_ID_DCB 8 2356#define I40E_AQ_CLUSTER_ID_EMP_MEM 9 2357#define I40E_AQ_CLUSTER_ID_PKT_BUF 10 2358#define I40E_AQ_CLUSTER_ID_ALTRAM 11 2359 2360struct i40e_aqc_debug_dump_internals { 2361 u8 cluster_id; 2362 u8 table_id; 2363 __le16 data_size; 2364 __le32 idx; 2365 __le32 address_high; 2366 __le32 address_low; 2367}; 2368 2369I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals); 2370 2371struct i40e_aqc_debug_modify_internals { 2372 u8 cluster_id; 2373 u8 cluster_specific_params[7]; 2374 __le32 address_high; 2375 __le32 address_low; 2376}; 2377 2378I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals); 2379 2380#endif /* _I40E_ADMINQ_CMD_H_ */ 2381