ixgbe_phy.c revision 280182
1179055Sjfv/****************************************************************************** 2171384Sjfv 3280182Sjfv Copyright (c) 2001-2014, Intel Corporation 4171384Sjfv All rights reserved. 5171384Sjfv 6171384Sjfv Redistribution and use in source and binary forms, with or without 7171384Sjfv modification, are permitted provided that the following conditions are met: 8171384Sjfv 9171384Sjfv 1. Redistributions of source code must retain the above copyright notice, 10171384Sjfv this list of conditions and the following disclaimer. 11171384Sjfv 12171384Sjfv 2. Redistributions in binary form must reproduce the above copyright 13171384Sjfv notice, this list of conditions and the following disclaimer in the 14171384Sjfv documentation and/or other materials provided with the distribution. 15171384Sjfv 16171384Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17171384Sjfv contributors may be used to endorse or promote products derived from 18171384Sjfv this software without specific prior written permission. 19171384Sjfv 20171384Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21171384Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22171384Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23171384Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24171384Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25171384Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26171384Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27171384Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28171384Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29171384Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30171384Sjfv POSSIBILITY OF SUCH DAMAGE. 31171384Sjfv 32179055Sjfv******************************************************************************/ 33179055Sjfv/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_phy.c 280182 2015-03-17 18:32:28Z jfv $*/ 34171384Sjfv 35171384Sjfv#include "ixgbe_api.h" 36171384Sjfv#include "ixgbe_common.h" 37171384Sjfv#include "ixgbe_phy.h" 38171384Sjfv 39190873Sjfvstatic void ixgbe_i2c_start(struct ixgbe_hw *hw); 40190873Sjfvstatic void ixgbe_i2c_stop(struct ixgbe_hw *hw); 41190873Sjfvstatic s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data); 42190873Sjfvstatic s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data); 43190873Sjfvstatic s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw); 44190873Sjfvstatic s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data); 45190873Sjfvstatic s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data); 46230775Sjfvstatic void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 47190873Sjfvstatic void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 48190873Sjfvstatic s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data); 49280182Sjfvstatic bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl); 50247822Sjfvstatic s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 51247822Sjfv u8 *sff8472_data); 52190873Sjfv 53171384Sjfv/** 54280182Sjfv * ixgbe_out_i2c_byte_ack - Send I2C byte with ack 55280182Sjfv * @hw: pointer to the hardware structure 56280182Sjfv * @byte: byte to send 57280182Sjfv * 58280182Sjfv * Returns an error code on error. 59280182Sjfv */ 60280182Sjfvstatic s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte) 61280182Sjfv{ 62280182Sjfv s32 status; 63280182Sjfv 64280182Sjfv status = ixgbe_clock_out_i2c_byte(hw, byte); 65280182Sjfv if (status) 66280182Sjfv return status; 67280182Sjfv return ixgbe_get_i2c_ack(hw); 68280182Sjfv} 69280182Sjfv 70280182Sjfv/** 71280182Sjfv * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack 72280182Sjfv * @hw: pointer to the hardware structure 73280182Sjfv * @byte: pointer to a u8 to receive the byte 74280182Sjfv * 75280182Sjfv * Returns an error code on error. 76280182Sjfv */ 77280182Sjfvstatic s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte) 78280182Sjfv{ 79280182Sjfv s32 status; 80280182Sjfv 81280182Sjfv status = ixgbe_clock_in_i2c_byte(hw, byte); 82280182Sjfv if (status) 83280182Sjfv return status; 84280182Sjfv /* ACK */ 85280182Sjfv return ixgbe_clock_out_i2c_bit(hw, FALSE); 86280182Sjfv} 87280182Sjfv 88280182Sjfv/** 89280182Sjfv * ixgbe_ones_comp_byte_add - Perform one's complement addition 90280182Sjfv * @add1 - addend 1 91280182Sjfv * @add2 - addend 2 92280182Sjfv * 93280182Sjfv * Returns one's complement 8-bit sum. 94280182Sjfv */ 95280182Sjfvstatic u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2) 96280182Sjfv{ 97280182Sjfv u16 sum = add1 + add2; 98280182Sjfv 99280182Sjfv sum = (sum & 0xFF) + (sum >> 8); 100280182Sjfv return sum & 0xFF; 101280182Sjfv} 102280182Sjfv 103280182Sjfv/** 104280182Sjfv * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation 105280182Sjfv * @hw: pointer to the hardware structure 106280182Sjfv * @addr: I2C bus address to read from 107280182Sjfv * @reg: I2C device register to read from 108280182Sjfv * @val: pointer to location to receive read value 109280182Sjfv * 110280182Sjfv * Returns an error code on error. 111280182Sjfv */ 112280182Sjfvstatic s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr, 113280182Sjfv u16 reg, u16 *val) 114280182Sjfv{ 115280182Sjfv u32 swfw_mask = hw->phy.phy_semaphore_mask; 116280182Sjfv int max_retry = 10; 117280182Sjfv int retry = 0; 118280182Sjfv u8 csum_byte; 119280182Sjfv u8 high_bits; 120280182Sjfv u8 low_bits; 121280182Sjfv u8 reg_high; 122280182Sjfv u8 csum; 123280182Sjfv 124280182Sjfv reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */ 125280182Sjfv csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 126280182Sjfv csum = ~csum; 127280182Sjfv do { 128280182Sjfv if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 129280182Sjfv return IXGBE_ERR_SWFW_SYNC; 130280182Sjfv ixgbe_i2c_start(hw); 131280182Sjfv /* Device Address and write indication */ 132280182Sjfv if (ixgbe_out_i2c_byte_ack(hw, addr)) 133280182Sjfv goto fail; 134280182Sjfv /* Write bits 14:8 */ 135280182Sjfv if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 136280182Sjfv goto fail; 137280182Sjfv /* Write bits 7:0 */ 138280182Sjfv if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 139280182Sjfv goto fail; 140280182Sjfv /* Write csum */ 141280182Sjfv if (ixgbe_out_i2c_byte_ack(hw, csum)) 142280182Sjfv goto fail; 143280182Sjfv /* Re-start condition */ 144280182Sjfv ixgbe_i2c_start(hw); 145280182Sjfv /* Device Address and read indication */ 146280182Sjfv if (ixgbe_out_i2c_byte_ack(hw, addr | 1)) 147280182Sjfv goto fail; 148280182Sjfv /* Get upper bits */ 149280182Sjfv if (ixgbe_in_i2c_byte_ack(hw, &high_bits)) 150280182Sjfv goto fail; 151280182Sjfv /* Get low bits */ 152280182Sjfv if (ixgbe_in_i2c_byte_ack(hw, &low_bits)) 153280182Sjfv goto fail; 154280182Sjfv /* Get csum */ 155280182Sjfv if (ixgbe_clock_in_i2c_byte(hw, &csum_byte)) 156280182Sjfv goto fail; 157280182Sjfv /* NACK */ 158280182Sjfv if (ixgbe_clock_out_i2c_bit(hw, FALSE)) 159280182Sjfv goto fail; 160280182Sjfv ixgbe_i2c_stop(hw); 161280182Sjfv hw->mac.ops.release_swfw_sync(hw, swfw_mask); 162280182Sjfv *val = (high_bits << 8) | low_bits; 163280182Sjfv return 0; 164280182Sjfv 165280182Sjfvfail: 166280182Sjfv ixgbe_i2c_bus_clear(hw); 167280182Sjfv hw->mac.ops.release_swfw_sync(hw, swfw_mask); 168280182Sjfv retry++; 169280182Sjfv if (retry < max_retry) 170280182Sjfv DEBUGOUT("I2C byte read combined error - Retrying.\n"); 171280182Sjfv else 172280182Sjfv DEBUGOUT("I2C byte read combined error.\n"); 173280182Sjfv } while (retry < max_retry); 174280182Sjfv 175280182Sjfv return IXGBE_ERR_I2C; 176280182Sjfv} 177280182Sjfv 178280182Sjfv/** 179280182Sjfv * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation 180280182Sjfv * @hw: pointer to the hardware structure 181280182Sjfv * @addr: I2C bus address to write to 182280182Sjfv * @reg: I2C device register to write to 183280182Sjfv * @val: value to write 184280182Sjfv * 185280182Sjfv * Returns an error code on error. 186280182Sjfv */ 187280182Sjfvstatic s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw, 188280182Sjfv u8 addr, u16 reg, u16 val) 189280182Sjfv{ 190280182Sjfv int max_retry = 1; 191280182Sjfv int retry = 0; 192280182Sjfv u8 reg_high; 193280182Sjfv u8 csum; 194280182Sjfv 195280182Sjfv reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */ 196280182Sjfv csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 197280182Sjfv csum = ixgbe_ones_comp_byte_add(csum, val >> 8); 198280182Sjfv csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF); 199280182Sjfv csum = ~csum; 200280182Sjfv do { 201280182Sjfv ixgbe_i2c_start(hw); 202280182Sjfv /* Device Address and write indication */ 203280182Sjfv if (ixgbe_out_i2c_byte_ack(hw, addr)) 204280182Sjfv goto fail; 205280182Sjfv /* Write bits 14:8 */ 206280182Sjfv if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 207280182Sjfv goto fail; 208280182Sjfv /* Write bits 7:0 */ 209280182Sjfv if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 210280182Sjfv goto fail; 211280182Sjfv /* Write data 15:8 */ 212280182Sjfv if (ixgbe_out_i2c_byte_ack(hw, val >> 8)) 213280182Sjfv goto fail; 214280182Sjfv /* Write data 7:0 */ 215280182Sjfv if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF)) 216280182Sjfv goto fail; 217280182Sjfv /* Write csum */ 218280182Sjfv if (ixgbe_out_i2c_byte_ack(hw, csum)) 219280182Sjfv goto fail; 220280182Sjfv ixgbe_i2c_stop(hw); 221280182Sjfv return 0; 222280182Sjfv 223280182Sjfvfail: 224280182Sjfv ixgbe_i2c_bus_clear(hw); 225280182Sjfv retry++; 226280182Sjfv if (retry < max_retry) 227280182Sjfv DEBUGOUT("I2C byte write combined error - Retrying.\n"); 228280182Sjfv else 229280182Sjfv DEBUGOUT("I2C byte write combined error.\n"); 230280182Sjfv } while (retry < max_retry); 231280182Sjfv 232280182Sjfv return IXGBE_ERR_I2C; 233280182Sjfv} 234280182Sjfv 235280182Sjfv/** 236179055Sjfv * ixgbe_init_phy_ops_generic - Inits PHY function ptrs 237179055Sjfv * @hw: pointer to the hardware structure 238179055Sjfv * 239179055Sjfv * Initialize the function pointers. 240171384Sjfv **/ 241179055Sjfvs32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw) 242171384Sjfv{ 243179055Sjfv struct ixgbe_phy_info *phy = &hw->phy; 244171384Sjfv 245200239Sjfv DEBUGFUNC("ixgbe_init_phy_ops_generic"); 246200239Sjfv 247179055Sjfv /* PHY */ 248280182Sjfv phy->ops.identify = ixgbe_identify_phy_generic; 249280182Sjfv phy->ops.reset = ixgbe_reset_phy_generic; 250280182Sjfv phy->ops.read_reg = ixgbe_read_phy_reg_generic; 251280182Sjfv phy->ops.write_reg = ixgbe_write_phy_reg_generic; 252280182Sjfv phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi; 253280182Sjfv phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi; 254280182Sjfv phy->ops.setup_link = ixgbe_setup_phy_link_generic; 255280182Sjfv phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic; 256179055Sjfv phy->ops.check_link = NULL; 257200239Sjfv phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic; 258280182Sjfv phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic; 259280182Sjfv phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic; 260280182Sjfv phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic; 261280182Sjfv phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic; 262280182Sjfv phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic; 263280182Sjfv phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear; 264280182Sjfv phy->ops.identify_sfp = ixgbe_identify_module_generic; 265185352Sjfv phy->sfp_type = ixgbe_sfp_type_unknown; 266280182Sjfv phy->ops.read_i2c_combined = ixgbe_read_i2c_combined_generic; 267280182Sjfv phy->ops.write_i2c_combined = ixgbe_write_i2c_combined_generic; 268280182Sjfv phy->ops.check_overtemp = ixgbe_tn_check_overtemp; 269171384Sjfv return IXGBE_SUCCESS; 270171384Sjfv} 271171384Sjfv 272171384Sjfv/** 273171384Sjfv * ixgbe_identify_phy_generic - Get physical layer module 274171384Sjfv * @hw: pointer to hardware structure 275171384Sjfv * 276171384Sjfv * Determines the physical layer module found on the current adapter. 277171384Sjfv **/ 278171384Sjfvs32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) 279171384Sjfv{ 280171384Sjfv s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 281171384Sjfv u32 phy_addr; 282190873Sjfv u16 ext_ability = 0; 283171384Sjfv 284200239Sjfv DEBUGFUNC("ixgbe_identify_phy_generic"); 285200239Sjfv 286280182Sjfv if (!hw->phy.phy_semaphore_mask) { 287280182Sjfv if (hw->bus.lan_id) 288280182Sjfv hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 289280182Sjfv else 290280182Sjfv hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 291280182Sjfv } 292280182Sjfv 293179055Sjfv if (hw->phy.type == ixgbe_phy_unknown) { 294179055Sjfv for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { 295179055Sjfv if (ixgbe_validate_phy_addr(hw, phy_addr)) { 296179055Sjfv hw->phy.addr = phy_addr; 297179055Sjfv ixgbe_get_phy_id(hw); 298179055Sjfv hw->phy.type = 299230775Sjfv ixgbe_get_phy_type_from_id(hw->phy.id); 300190873Sjfv 301190873Sjfv if (hw->phy.type == ixgbe_phy_unknown) { 302190873Sjfv hw->phy.ops.read_reg(hw, 303190873Sjfv IXGBE_MDIO_PHY_EXT_ABILITY, 304230775Sjfv IXGBE_MDIO_PMA_PMD_DEV_TYPE, 305230775Sjfv &ext_ability); 306190873Sjfv if (ext_ability & 307215911Sjfv (IXGBE_MDIO_PHY_10GBASET_ABILITY | 308215911Sjfv IXGBE_MDIO_PHY_1000BASET_ABILITY)) 309190873Sjfv hw->phy.type = 310230775Sjfv ixgbe_phy_cu_unknown; 311190873Sjfv else 312190873Sjfv hw->phy.type = 313230775Sjfv ixgbe_phy_generic; 314190873Sjfv } 315190873Sjfv 316179055Sjfv status = IXGBE_SUCCESS; 317179055Sjfv break; 318179055Sjfv } 319171384Sjfv } 320280182Sjfv 321280182Sjfv /* Certain media types do not have a phy so an address will not 322280182Sjfv * be found and the code will take this path. Caller has to 323280182Sjfv * decide if it is an error or not. 324280182Sjfv */ 325251964Sjfv if (status != IXGBE_SUCCESS) { 326190873Sjfv hw->phy.addr = 0; 327251964Sjfv } 328179055Sjfv } else { 329179055Sjfv status = IXGBE_SUCCESS; 330171384Sjfv } 331179055Sjfv 332171384Sjfv return status; 333171384Sjfv} 334171384Sjfv 335171384Sjfv/** 336280182Sjfv * ixgbe_check_reset_blocked - check status of MNG FW veto bit 337280182Sjfv * @hw: pointer to the hardware structure 338280182Sjfv * 339280182Sjfv * This function checks the MMNGC.MNG_VETO bit to see if there are 340280182Sjfv * any constraints on link from manageability. For MAC's that don't 341280182Sjfv * have this bit just return faluse since the link can not be blocked 342280182Sjfv * via this method. 343280182Sjfv **/ 344280182Sjfvs32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw) 345280182Sjfv{ 346280182Sjfv u32 mmngc; 347280182Sjfv 348280182Sjfv DEBUGFUNC("ixgbe_check_reset_blocked"); 349280182Sjfv 350280182Sjfv /* If we don't have this bit, it can't be blocking */ 351280182Sjfv if (hw->mac.type == ixgbe_mac_82598EB) 352280182Sjfv return FALSE; 353280182Sjfv 354280182Sjfv mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC); 355280182Sjfv if (mmngc & IXGBE_MMNGC_MNG_VETO) { 356280182Sjfv ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, 357280182Sjfv "MNG_VETO bit detected.\n"); 358280182Sjfv return TRUE; 359280182Sjfv } 360280182Sjfv 361280182Sjfv return FALSE; 362280182Sjfv} 363280182Sjfv 364280182Sjfv/** 365171384Sjfv * ixgbe_validate_phy_addr - Determines phy address is valid 366171384Sjfv * @hw: pointer to hardware structure 367171384Sjfv * 368171384Sjfv **/ 369171384Sjfvbool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr) 370171384Sjfv{ 371171384Sjfv u16 phy_id = 0; 372171384Sjfv bool valid = FALSE; 373171384Sjfv 374200239Sjfv DEBUGFUNC("ixgbe_validate_phy_addr"); 375200239Sjfv 376171384Sjfv hw->phy.addr = phy_addr; 377179055Sjfv hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 378230775Sjfv IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id); 379171384Sjfv 380171384Sjfv if (phy_id != 0xFFFF && phy_id != 0x0) 381171384Sjfv valid = TRUE; 382171384Sjfv 383171384Sjfv return valid; 384171384Sjfv} 385171384Sjfv 386171384Sjfv/** 387171384Sjfv * ixgbe_get_phy_id - Get the phy type 388171384Sjfv * @hw: pointer to hardware structure 389171384Sjfv * 390171384Sjfv **/ 391171384Sjfvs32 ixgbe_get_phy_id(struct ixgbe_hw *hw) 392171384Sjfv{ 393171384Sjfv u32 status; 394171384Sjfv u16 phy_id_high = 0; 395171384Sjfv u16 phy_id_low = 0; 396171384Sjfv 397200239Sjfv DEBUGFUNC("ixgbe_get_phy_id"); 398200239Sjfv 399179055Sjfv status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 400230775Sjfv IXGBE_MDIO_PMA_PMD_DEV_TYPE, 401230775Sjfv &phy_id_high); 402171384Sjfv 403171384Sjfv if (status == IXGBE_SUCCESS) { 404171384Sjfv hw->phy.id = (u32)(phy_id_high << 16); 405179055Sjfv status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW, 406230775Sjfv IXGBE_MDIO_PMA_PMD_DEV_TYPE, 407230775Sjfv &phy_id_low); 408171384Sjfv hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); 409171384Sjfv hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); 410171384Sjfv } 411171384Sjfv return status; 412171384Sjfv} 413171384Sjfv 414171384Sjfv/** 415171384Sjfv * ixgbe_get_phy_type_from_id - Get the phy type 416171384Sjfv * @hw: pointer to hardware structure 417171384Sjfv * 418171384Sjfv **/ 419171384Sjfvenum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) 420171384Sjfv{ 421171384Sjfv enum ixgbe_phy_type phy_type; 422171384Sjfv 423200239Sjfv DEBUGFUNC("ixgbe_get_phy_type_from_id"); 424200239Sjfv 425171384Sjfv switch (phy_id) { 426179055Sjfv case TN1010_PHY_ID: 427179055Sjfv phy_type = ixgbe_phy_tn; 428179055Sjfv break; 429280182Sjfv case X550_PHY_ID: 430230775Sjfv case X540_PHY_ID: 431190873Sjfv phy_type = ixgbe_phy_aq; 432190873Sjfv break; 433171384Sjfv case QT2022_PHY_ID: 434171384Sjfv phy_type = ixgbe_phy_qt; 435171384Sjfv break; 436185352Sjfv case ATH_PHY_ID: 437185352Sjfv phy_type = ixgbe_phy_nl; 438185352Sjfv break; 439280182Sjfv case X557_PHY_ID: 440280182Sjfv phy_type = ixgbe_phy_x550em_ext_t; 441280182Sjfv break; 442171384Sjfv default: 443171384Sjfv phy_type = ixgbe_phy_unknown; 444171384Sjfv break; 445171384Sjfv } 446171384Sjfv 447179055Sjfv DEBUGOUT1("phy type found is %d\n", phy_type); 448171384Sjfv return phy_type; 449171384Sjfv} 450171384Sjfv 451171384Sjfv/** 452171384Sjfv * ixgbe_reset_phy_generic - Performs a PHY reset 453171384Sjfv * @hw: pointer to hardware structure 454171384Sjfv **/ 455171384Sjfvs32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 456171384Sjfv{ 457190873Sjfv u32 i; 458190873Sjfv u16 ctrl = 0; 459190873Sjfv s32 status = IXGBE_SUCCESS; 460190873Sjfv 461200239Sjfv DEBUGFUNC("ixgbe_reset_phy_generic"); 462200239Sjfv 463190873Sjfv if (hw->phy.type == ixgbe_phy_unknown) 464190873Sjfv status = ixgbe_identify_phy_generic(hw); 465190873Sjfv 466190873Sjfv if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none) 467190873Sjfv goto out; 468190873Sjfv 469215911Sjfv /* Don't reset PHY if it's shut down due to overtemp. */ 470215911Sjfv if (!hw->phy.reset_if_overtemp && 471215911Sjfv (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw))) 472215911Sjfv goto out; 473215911Sjfv 474280182Sjfv /* Blocked by MNG FW so bail */ 475280182Sjfv if (ixgbe_check_reset_blocked(hw)) 476280182Sjfv goto out; 477280182Sjfv 478171384Sjfv /* 479171384Sjfv * Perform soft PHY reset to the PHY_XS. 480171384Sjfv * This will cause a soft reset to the PHY 481171384Sjfv */ 482190873Sjfv hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 483230775Sjfv IXGBE_MDIO_PHY_XS_DEV_TYPE, 484230775Sjfv IXGBE_MDIO_PHY_XS_RESET); 485190873Sjfv 486205720Sjfv /* 487205720Sjfv * Poll for reset bit to self-clear indicating reset is complete. 488205720Sjfv * Some PHYs could take up to 3 seconds to complete and need about 489205720Sjfv * 1.7 usec delay after the reset is complete. 490205720Sjfv */ 491205720Sjfv for (i = 0; i < 30; i++) { 492205720Sjfv msec_delay(100); 493190873Sjfv hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 494230775Sjfv IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl); 495205720Sjfv if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) { 496205720Sjfv usec_delay(2); 497190873Sjfv break; 498205720Sjfv } 499190873Sjfv } 500190873Sjfv 501190873Sjfv if (ctrl & IXGBE_MDIO_PHY_XS_RESET) { 502190873Sjfv status = IXGBE_ERR_RESET_FAILED; 503251964Sjfv ERROR_REPORT1(IXGBE_ERROR_POLLING, 504251964Sjfv "PHY reset polling failed to complete.\n"); 505190873Sjfv } 506190873Sjfv 507190873Sjfvout: 508190873Sjfv return status; 509171384Sjfv} 510171384Sjfv 511171384Sjfv/** 512251964Sjfv * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without 513251964Sjfv * the SWFW lock 514251964Sjfv * @hw: pointer to hardware structure 515251964Sjfv * @reg_addr: 32 bit address of PHY register to read 516251964Sjfv * @phy_data: Pointer to read data from PHY register 517251964Sjfv **/ 518251964Sjfvs32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 519251964Sjfv u16 *phy_data) 520251964Sjfv{ 521251964Sjfv u32 i, data, command; 522251964Sjfv 523251964Sjfv /* Setup and write the address cycle command */ 524251964Sjfv command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 525251964Sjfv (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 526251964Sjfv (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 527251964Sjfv (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 528251964Sjfv 529251964Sjfv IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 530251964Sjfv 531251964Sjfv /* 532251964Sjfv * Check every 10 usec to see if the address cycle completed. 533251964Sjfv * The MDI Command bit will clear when the operation is 534251964Sjfv * complete 535251964Sjfv */ 536251964Sjfv for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 537251964Sjfv usec_delay(10); 538251964Sjfv 539251964Sjfv command = IXGBE_READ_REG(hw, IXGBE_MSCA); 540251964Sjfv if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 541251964Sjfv break; 542251964Sjfv } 543251964Sjfv 544251964Sjfv 545251964Sjfv if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 546251964Sjfv ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n"); 547251964Sjfv return IXGBE_ERR_PHY; 548251964Sjfv } 549251964Sjfv 550251964Sjfv /* 551251964Sjfv * Address cycle complete, setup and write the read 552251964Sjfv * command 553251964Sjfv */ 554251964Sjfv command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 555251964Sjfv (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 556251964Sjfv (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 557251964Sjfv (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); 558251964Sjfv 559251964Sjfv IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 560251964Sjfv 561251964Sjfv /* 562251964Sjfv * Check every 10 usec to see if the address cycle 563251964Sjfv * completed. The MDI Command bit will clear when the 564251964Sjfv * operation is complete 565251964Sjfv */ 566251964Sjfv for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 567251964Sjfv usec_delay(10); 568251964Sjfv 569251964Sjfv command = IXGBE_READ_REG(hw, IXGBE_MSCA); 570251964Sjfv if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 571251964Sjfv break; 572251964Sjfv } 573251964Sjfv 574251964Sjfv if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 575251964Sjfv ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n"); 576251964Sjfv return IXGBE_ERR_PHY; 577251964Sjfv } 578251964Sjfv 579251964Sjfv /* 580251964Sjfv * Read operation is complete. Get the data 581251964Sjfv * from MSRWD 582251964Sjfv */ 583251964Sjfv data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 584251964Sjfv data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 585251964Sjfv *phy_data = (u16)(data); 586251964Sjfv 587251964Sjfv return IXGBE_SUCCESS; 588251964Sjfv} 589251964Sjfv 590251964Sjfv/** 591171384Sjfv * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register 592251964Sjfv * using the SWFW lock - this function is needed in most cases 593171384Sjfv * @hw: pointer to hardware structure 594171384Sjfv * @reg_addr: 32 bit address of PHY register to read 595171384Sjfv * @phy_data: Pointer to read data from PHY register 596171384Sjfv **/ 597171384Sjfvs32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 598230775Sjfv u32 device_type, u16 *phy_data) 599171384Sjfv{ 600251964Sjfv s32 status; 601280182Sjfv u32 gssr = hw->phy.phy_semaphore_mask; 602171384Sjfv 603200239Sjfv DEBUGFUNC("ixgbe_read_phy_reg_generic"); 604200239Sjfv 605251964Sjfv if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) { 606251964Sjfv status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type, 607251964Sjfv phy_data); 608251964Sjfv hw->mac.ops.release_swfw_sync(hw, gssr); 609251964Sjfv } else { 610171384Sjfv status = IXGBE_ERR_SWFW_SYNC; 611251964Sjfv } 612171384Sjfv 613251964Sjfv return status; 614251964Sjfv} 615171384Sjfv 616251964Sjfv/** 617251964Sjfv * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register 618251964Sjfv * without SWFW lock 619251964Sjfv * @hw: pointer to hardware structure 620251964Sjfv * @reg_addr: 32 bit PHY register to write 621251964Sjfv * @device_type: 5 bit device type 622251964Sjfv * @phy_data: Data to write to the PHY register 623251964Sjfv **/ 624251964Sjfvs32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, 625251964Sjfv u32 device_type, u16 phy_data) 626251964Sjfv{ 627251964Sjfv u32 i, command; 628171384Sjfv 629251964Sjfv /* Put the data in the MDI single read and write data register*/ 630251964Sjfv IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); 631171384Sjfv 632251964Sjfv /* Setup and write the address cycle command */ 633251964Sjfv command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 634251964Sjfv (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 635251964Sjfv (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 636251964Sjfv (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 637171384Sjfv 638251964Sjfv IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 639171384Sjfv 640251964Sjfv /* 641251964Sjfv * Check every 10 usec to see if the address cycle completed. 642251964Sjfv * The MDI Command bit will clear when the operation is 643251964Sjfv * complete 644251964Sjfv */ 645251964Sjfv for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 646251964Sjfv usec_delay(10); 647171384Sjfv 648251964Sjfv command = IXGBE_READ_REG(hw, IXGBE_MSCA); 649251964Sjfv if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 650251964Sjfv break; 651251964Sjfv } 652171384Sjfv 653251964Sjfv if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 654251964Sjfv ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n"); 655251964Sjfv return IXGBE_ERR_PHY; 656251964Sjfv } 657171384Sjfv 658251964Sjfv /* 659251964Sjfv * Address cycle complete, setup and write the write 660251964Sjfv * command 661251964Sjfv */ 662251964Sjfv command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 663251964Sjfv (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 664251964Sjfv (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 665251964Sjfv (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); 666171384Sjfv 667251964Sjfv IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 668171384Sjfv 669251964Sjfv /* 670251964Sjfv * Check every 10 usec to see if the address cycle 671251964Sjfv * completed. The MDI Command bit will clear when the 672251964Sjfv * operation is complete 673251964Sjfv */ 674251964Sjfv for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 675251964Sjfv usec_delay(10); 676171384Sjfv 677251964Sjfv command = IXGBE_READ_REG(hw, IXGBE_MSCA); 678251964Sjfv if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 679251964Sjfv break; 680251964Sjfv } 681171384Sjfv 682251964Sjfv if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 683251964Sjfv ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n"); 684251964Sjfv return IXGBE_ERR_PHY; 685171384Sjfv } 686179055Sjfv 687251964Sjfv return IXGBE_SUCCESS; 688171384Sjfv} 689171384Sjfv 690171384Sjfv/** 691171384Sjfv * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register 692251964Sjfv * using SWFW lock- this function is needed in most cases 693171384Sjfv * @hw: pointer to hardware structure 694171384Sjfv * @reg_addr: 32 bit PHY register to write 695171384Sjfv * @device_type: 5 bit device type 696171384Sjfv * @phy_data: Data to write to the PHY register 697171384Sjfv **/ 698171384Sjfvs32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 699230775Sjfv u32 device_type, u16 phy_data) 700171384Sjfv{ 701251964Sjfv s32 status; 702280182Sjfv u32 gssr = hw->phy.phy_semaphore_mask; 703171384Sjfv 704200239Sjfv DEBUGFUNC("ixgbe_write_phy_reg_generic"); 705200239Sjfv 706251964Sjfv if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) { 707251964Sjfv status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type, 708251964Sjfv phy_data); 709251964Sjfv hw->mac.ops.release_swfw_sync(hw, gssr); 710251964Sjfv } else { 711171384Sjfv status = IXGBE_ERR_SWFW_SYNC; 712171384Sjfv } 713171384Sjfv 714171384Sjfv return status; 715171384Sjfv} 716171384Sjfv 717171384Sjfv/** 718280182Sjfv * ixgbe_setup_phy_link_generic - Set and restart auto-neg 719215911Sjfv * @hw: pointer to hardware structure 720171384Sjfv * 721280182Sjfv * Restart auto-negotiation and PHY and waits for completion. 722171384Sjfv **/ 723179055Sjfvs32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 724171384Sjfv{ 725194875Sjfv s32 status = IXGBE_SUCCESS; 726179055Sjfv u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 727200239Sjfv bool autoneg = FALSE; 728200239Sjfv ixgbe_link_speed speed; 729179055Sjfv 730200239Sjfv DEBUGFUNC("ixgbe_setup_phy_link_generic"); 731179055Sjfv 732200239Sjfv ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 733179055Sjfv 734200239Sjfv if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 735200239Sjfv /* Set or unset auto-negotiation 10G advertisement */ 736200239Sjfv hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 737230775Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 738230775Sjfv &autoneg_reg); 739179055Sjfv 740200239Sjfv autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 741200239Sjfv if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 742200239Sjfv autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 743200239Sjfv 744200239Sjfv hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 745230775Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 746230775Sjfv autoneg_reg); 747200239Sjfv } 748200239Sjfv 749280182Sjfv if (hw->mac.type == ixgbe_mac_X550) { 750280182Sjfv if (speed & IXGBE_LINK_SPEED_5GB_FULL) { 751280182Sjfv /* Set or unset auto-negotiation 1G advertisement */ 752280182Sjfv hw->phy.ops.read_reg(hw, 753280182Sjfv IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 754280182Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 755280182Sjfv &autoneg_reg); 756280182Sjfv 757280182Sjfv autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE; 758280182Sjfv if (hw->phy.autoneg_advertised & 759280182Sjfv IXGBE_LINK_SPEED_5GB_FULL) 760280182Sjfv autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE; 761280182Sjfv 762280182Sjfv hw->phy.ops.write_reg(hw, 763280182Sjfv IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 764280182Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 765280182Sjfv autoneg_reg); 766280182Sjfv } 767280182Sjfv 768280182Sjfv if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) { 769280182Sjfv /* Set or unset auto-negotiation 1G advertisement */ 770280182Sjfv hw->phy.ops.read_reg(hw, 771280182Sjfv IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 772280182Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 773280182Sjfv &autoneg_reg); 774280182Sjfv 775280182Sjfv autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE; 776280182Sjfv if (hw->phy.autoneg_advertised & 777280182Sjfv IXGBE_LINK_SPEED_2_5GB_FULL) 778280182Sjfv autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE; 779280182Sjfv 780280182Sjfv hw->phy.ops.write_reg(hw, 781280182Sjfv IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 782280182Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 783280182Sjfv autoneg_reg); 784280182Sjfv } 785280182Sjfv } 786280182Sjfv 787200239Sjfv if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 788200239Sjfv /* Set or unset auto-negotiation 1G advertisement */ 789200239Sjfv hw->phy.ops.read_reg(hw, 790230775Sjfv IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 791230775Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 792230775Sjfv &autoneg_reg); 793200239Sjfv 794200239Sjfv autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE; 795200239Sjfv if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 796200239Sjfv autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE; 797200239Sjfv 798200239Sjfv hw->phy.ops.write_reg(hw, 799230775Sjfv IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 800230775Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 801230775Sjfv autoneg_reg); 802200239Sjfv } 803200239Sjfv 804200239Sjfv if (speed & IXGBE_LINK_SPEED_100_FULL) { 805200239Sjfv /* Set or unset auto-negotiation 100M advertisement */ 806200239Sjfv hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 807230775Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 808230775Sjfv &autoneg_reg); 809200239Sjfv 810230775Sjfv autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE | 811230775Sjfv IXGBE_MII_100BASE_T_ADVERTISE_HALF); 812200239Sjfv if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 813200239Sjfv autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 814200239Sjfv 815200239Sjfv hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 816230775Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 817230775Sjfv autoneg_reg); 818200239Sjfv } 819200239Sjfv 820280182Sjfv /* Blocked by MNG FW so don't reset PHY */ 821280182Sjfv if (ixgbe_check_reset_blocked(hw)) 822280182Sjfv return status; 823280182Sjfv 824280182Sjfv /* Restart PHY auto-negotiation. */ 825179055Sjfv hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 826230775Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 827179055Sjfv 828179055Sjfv autoneg_reg |= IXGBE_MII_RESTART; 829179055Sjfv 830179055Sjfv hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 831230775Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 832179055Sjfv 833179055Sjfv return status; 834171384Sjfv} 835171384Sjfv 836171384Sjfv/** 837179055Sjfv * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities 838171384Sjfv * @hw: pointer to hardware structure 839179055Sjfv * @speed: new link speed 840179055Sjfv **/ 841179055Sjfvs32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 842230775Sjfv ixgbe_link_speed speed, 843230775Sjfv bool autoneg_wait_to_complete) 844179055Sjfv{ 845247822Sjfv UNREFERENCED_1PARAMETER(autoneg_wait_to_complete); 846179055Sjfv 847200239Sjfv DEBUGFUNC("ixgbe_setup_phy_link_speed_generic"); 848200239Sjfv 849179055Sjfv /* 850179055Sjfv * Clear autoneg_advertised and set new values based on input link 851179055Sjfv * speed. 852179055Sjfv */ 853179055Sjfv hw->phy.autoneg_advertised = 0; 854179055Sjfv 855185352Sjfv if (speed & IXGBE_LINK_SPEED_10GB_FULL) 856179055Sjfv hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 857185352Sjfv 858280182Sjfv if (speed & IXGBE_LINK_SPEED_5GB_FULL) 859280182Sjfv hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL; 860280182Sjfv 861280182Sjfv if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) 862280182Sjfv hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL; 863280182Sjfv 864185352Sjfv if (speed & IXGBE_LINK_SPEED_1GB_FULL) 865179055Sjfv hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 866179055Sjfv 867190873Sjfv if (speed & IXGBE_LINK_SPEED_100_FULL) 868190873Sjfv hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 869190873Sjfv 870179055Sjfv /* Setup link based on the new speed settings */ 871179055Sjfv hw->phy.ops.setup_link(hw); 872179055Sjfv 873179055Sjfv return IXGBE_SUCCESS; 874179055Sjfv} 875179055Sjfv 876179055Sjfv/** 877190873Sjfv * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities 878190873Sjfv * @hw: pointer to hardware structure 879190873Sjfv * @speed: pointer to link speed 880190873Sjfv * @autoneg: boolean auto-negotiation value 881190873Sjfv * 882280182Sjfv * Determines the supported link capabilities by reading the PHY auto 883280182Sjfv * negotiation register. 884190873Sjfv **/ 885190873Sjfvs32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 886230775Sjfv ixgbe_link_speed *speed, 887230775Sjfv bool *autoneg) 888190873Sjfv{ 889280182Sjfv s32 status; 890190873Sjfv u16 speed_ability; 891190873Sjfv 892200239Sjfv DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic"); 893200239Sjfv 894190873Sjfv *speed = 0; 895190873Sjfv *autoneg = TRUE; 896190873Sjfv 897190873Sjfv status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY, 898230775Sjfv IXGBE_MDIO_PMA_PMD_DEV_TYPE, 899230775Sjfv &speed_ability); 900190873Sjfv 901190873Sjfv if (status == IXGBE_SUCCESS) { 902190873Sjfv if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G) 903190873Sjfv *speed |= IXGBE_LINK_SPEED_10GB_FULL; 904190873Sjfv if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G) 905190873Sjfv *speed |= IXGBE_LINK_SPEED_1GB_FULL; 906190873Sjfv if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M) 907190873Sjfv *speed |= IXGBE_LINK_SPEED_100_FULL; 908190873Sjfv } 909190873Sjfv 910280182Sjfv /* Internal PHY does not support 100 Mbps */ 911280182Sjfv if (hw->mac.type == ixgbe_mac_X550EM_x) 912280182Sjfv *speed &= ~IXGBE_LINK_SPEED_100_FULL; 913280182Sjfv 914280182Sjfv if (hw->mac.type == ixgbe_mac_X550) { 915280182Sjfv *speed |= IXGBE_LINK_SPEED_2_5GB_FULL; 916280182Sjfv *speed |= IXGBE_LINK_SPEED_5GB_FULL; 917280182Sjfv } 918280182Sjfv 919190873Sjfv return status; 920190873Sjfv} 921190873Sjfv 922190873Sjfv/** 923179055Sjfv * ixgbe_check_phy_link_tnx - Determine link and speed status 924179055Sjfv * @hw: pointer to hardware structure 925171384Sjfv * 926179055Sjfv * Reads the VS1 register to determine if link is up and the current speed for 927171384Sjfv * the PHY. 928171384Sjfv **/ 929179055Sjfvs32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 930230775Sjfv bool *link_up) 931171384Sjfv{ 932179055Sjfv s32 status = IXGBE_SUCCESS; 933179055Sjfv u32 time_out; 934179055Sjfv u32 max_time_out = 10; 935179055Sjfv u16 phy_link = 0; 936179055Sjfv u16 phy_speed = 0; 937179055Sjfv u16 phy_data = 0; 938179055Sjfv 939200239Sjfv DEBUGFUNC("ixgbe_check_phy_link_tnx"); 940200239Sjfv 941179055Sjfv /* Initialize speed and link to default case */ 942179055Sjfv *link_up = FALSE; 943179055Sjfv *speed = IXGBE_LINK_SPEED_10GB_FULL; 944179055Sjfv 945179055Sjfv /* 946179055Sjfv * Check current speed and link status of the PHY register. 947179055Sjfv * This is a vendor specific register and may have to 948179055Sjfv * be changed for other copper PHYs. 949179055Sjfv */ 950179055Sjfv for (time_out = 0; time_out < max_time_out; time_out++) { 951179055Sjfv usec_delay(10); 952179055Sjfv status = hw->phy.ops.read_reg(hw, 953230775Sjfv IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS, 954230775Sjfv IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 955230775Sjfv &phy_data); 956230775Sjfv phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; 957179055Sjfv phy_speed = phy_data & 958230775Sjfv IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; 959179055Sjfv if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { 960179055Sjfv *link_up = TRUE; 961179055Sjfv if (phy_speed == 962179055Sjfv IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) 963179055Sjfv *speed = IXGBE_LINK_SPEED_1GB_FULL; 964179055Sjfv break; 965179055Sjfv } 966179055Sjfv } 967179055Sjfv 968179055Sjfv return status; 969171384Sjfv} 970171384Sjfv 971171384Sjfv/** 972280182Sjfv * ixgbe_setup_phy_link_tnx - Set and restart auto-neg 973200239Sjfv * @hw: pointer to hardware structure 974200239Sjfv * 975280182Sjfv * Restart auto-negotiation and PHY and waits for completion. 976200239Sjfv **/ 977200239Sjfvs32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) 978200239Sjfv{ 979200239Sjfv s32 status = IXGBE_SUCCESS; 980200239Sjfv u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 981200239Sjfv bool autoneg = FALSE; 982200239Sjfv ixgbe_link_speed speed; 983200239Sjfv 984200239Sjfv DEBUGFUNC("ixgbe_setup_phy_link_tnx"); 985200239Sjfv 986200239Sjfv ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 987200239Sjfv 988200239Sjfv if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 989200239Sjfv /* Set or unset auto-negotiation 10G advertisement */ 990200239Sjfv hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 991230775Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 992230775Sjfv &autoneg_reg); 993200239Sjfv 994200239Sjfv autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 995200239Sjfv if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 996200239Sjfv autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 997200239Sjfv 998200239Sjfv hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 999230775Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1000230775Sjfv autoneg_reg); 1001200239Sjfv } 1002200239Sjfv 1003200239Sjfv if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 1004200239Sjfv /* Set or unset auto-negotiation 1G advertisement */ 1005200239Sjfv hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1006230775Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1007230775Sjfv &autoneg_reg); 1008200239Sjfv 1009200239Sjfv autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1010200239Sjfv if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 1011200239Sjfv autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1012200239Sjfv 1013200239Sjfv hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1014230775Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1015230775Sjfv autoneg_reg); 1016200239Sjfv } 1017200239Sjfv 1018200239Sjfv if (speed & IXGBE_LINK_SPEED_100_FULL) { 1019200239Sjfv /* Set or unset auto-negotiation 100M advertisement */ 1020200239Sjfv hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 1021230775Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1022230775Sjfv &autoneg_reg); 1023200239Sjfv 1024200239Sjfv autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE; 1025200239Sjfv if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 1026200239Sjfv autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 1027200239Sjfv 1028200239Sjfv hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 1029230775Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1030230775Sjfv autoneg_reg); 1031200239Sjfv } 1032200239Sjfv 1033280182Sjfv /* Blocked by MNG FW so don't reset PHY */ 1034280182Sjfv if (ixgbe_check_reset_blocked(hw)) 1035280182Sjfv return status; 1036280182Sjfv 1037280182Sjfv /* Restart PHY auto-negotiation. */ 1038200239Sjfv hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 1039230775Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 1040200239Sjfv 1041200239Sjfv autoneg_reg |= IXGBE_MII_RESTART; 1042200239Sjfv 1043200239Sjfv hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 1044230775Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 1045200239Sjfv 1046200239Sjfv return status; 1047200239Sjfv} 1048200239Sjfv 1049200239Sjfv/** 1050179055Sjfv * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version 1051171384Sjfv * @hw: pointer to hardware structure 1052179055Sjfv * @firmware_version: pointer to the PHY Firmware Version 1053171384Sjfv **/ 1054179055Sjfvs32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, 1055230775Sjfv u16 *firmware_version) 1056171384Sjfv{ 1057280182Sjfv s32 status; 1058179055Sjfv 1059200239Sjfv DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx"); 1060200239Sjfv 1061179055Sjfv status = hw->phy.ops.read_reg(hw, TNX_FW_REV, 1062230775Sjfv IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1063230775Sjfv firmware_version); 1064179055Sjfv 1065179055Sjfv return status; 1066171384Sjfv} 1067171384Sjfv 1068185352Sjfv/** 1069200239Sjfv * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version 1070190873Sjfv * @hw: pointer to hardware structure 1071190873Sjfv * @firmware_version: pointer to the PHY Firmware Version 1072190873Sjfv **/ 1073200239Sjfvs32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, 1074230775Sjfv u16 *firmware_version) 1075190873Sjfv{ 1076280182Sjfv s32 status; 1077190873Sjfv 1078200239Sjfv DEBUGFUNC("ixgbe_get_phy_firmware_version_generic"); 1079200239Sjfv 1080190873Sjfv status = hw->phy.ops.read_reg(hw, AQ_FW_REV, 1081230775Sjfv IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1082230775Sjfv firmware_version); 1083190873Sjfv 1084190873Sjfv return status; 1085190873Sjfv} 1086190873Sjfv 1087190873Sjfv/** 1088185352Sjfv * ixgbe_reset_phy_nl - Performs a PHY reset 1089185352Sjfv * @hw: pointer to hardware structure 1090185352Sjfv **/ 1091185352Sjfvs32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) 1092185352Sjfv{ 1093185352Sjfv u16 phy_offset, control, eword, edata, block_crc; 1094185352Sjfv bool end_data = FALSE; 1095185352Sjfv u16 list_offset, data_offset; 1096185352Sjfv u16 phy_data = 0; 1097185352Sjfv s32 ret_val = IXGBE_SUCCESS; 1098185352Sjfv u32 i; 1099185352Sjfv 1100200239Sjfv DEBUGFUNC("ixgbe_reset_phy_nl"); 1101200239Sjfv 1102280182Sjfv /* Blocked by MNG FW so bail */ 1103280182Sjfv if (ixgbe_check_reset_blocked(hw)) 1104280182Sjfv goto out; 1105280182Sjfv 1106185352Sjfv hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1107230775Sjfv IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 1108185352Sjfv 1109185352Sjfv /* reset the PHY and poll for completion */ 1110185352Sjfv hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1111230775Sjfv IXGBE_MDIO_PHY_XS_DEV_TYPE, 1112230775Sjfv (phy_data | IXGBE_MDIO_PHY_XS_RESET)); 1113185352Sjfv 1114185352Sjfv for (i = 0; i < 100; i++) { 1115185352Sjfv hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1116230775Sjfv IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 1117185352Sjfv if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0) 1118185352Sjfv break; 1119185352Sjfv msec_delay(10); 1120185352Sjfv } 1121185352Sjfv 1122185352Sjfv if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) { 1123185352Sjfv DEBUGOUT("PHY reset did not complete.\n"); 1124185352Sjfv ret_val = IXGBE_ERR_PHY; 1125185352Sjfv goto out; 1126185352Sjfv } 1127185352Sjfv 1128185352Sjfv /* Get init offsets */ 1129185352Sjfv ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 1130230775Sjfv &data_offset); 1131185352Sjfv if (ret_val != IXGBE_SUCCESS) 1132185352Sjfv goto out; 1133185352Sjfv 1134185352Sjfv ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); 1135185352Sjfv data_offset++; 1136185352Sjfv while (!end_data) { 1137185352Sjfv /* 1138185352Sjfv * Read control word from PHY init contents offset 1139185352Sjfv */ 1140185352Sjfv ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); 1141251964Sjfv if (ret_val) 1142251964Sjfv goto err_eeprom; 1143185352Sjfv control = (eword & IXGBE_CONTROL_MASK_NL) >> 1144230775Sjfv IXGBE_CONTROL_SHIFT_NL; 1145185352Sjfv edata = eword & IXGBE_DATA_MASK_NL; 1146185352Sjfv switch (control) { 1147185352Sjfv case IXGBE_DELAY_NL: 1148185352Sjfv data_offset++; 1149185352Sjfv DEBUGOUT1("DELAY: %d MS\n", edata); 1150185352Sjfv msec_delay(edata); 1151185352Sjfv break; 1152185352Sjfv case IXGBE_DATA_NL: 1153230775Sjfv DEBUGOUT("DATA:\n"); 1154185352Sjfv data_offset++; 1155251964Sjfv ret_val = hw->eeprom.ops.read(hw, data_offset, 1156251964Sjfv &phy_offset); 1157251964Sjfv if (ret_val) 1158251964Sjfv goto err_eeprom; 1159251964Sjfv data_offset++; 1160185352Sjfv for (i = 0; i < edata; i++) { 1161251964Sjfv ret_val = hw->eeprom.ops.read(hw, data_offset, 1162251964Sjfv &eword); 1163251964Sjfv if (ret_val) 1164251964Sjfv goto err_eeprom; 1165185352Sjfv hw->phy.ops.write_reg(hw, phy_offset, 1166230775Sjfv IXGBE_TWINAX_DEV, eword); 1167185352Sjfv DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword, 1168230775Sjfv phy_offset); 1169185352Sjfv data_offset++; 1170185352Sjfv phy_offset++; 1171185352Sjfv } 1172185352Sjfv break; 1173185352Sjfv case IXGBE_CONTROL_NL: 1174185352Sjfv data_offset++; 1175230775Sjfv DEBUGOUT("CONTROL:\n"); 1176185352Sjfv if (edata == IXGBE_CONTROL_EOL_NL) { 1177185352Sjfv DEBUGOUT("EOL\n"); 1178185352Sjfv end_data = TRUE; 1179185352Sjfv } else if (edata == IXGBE_CONTROL_SOL_NL) { 1180185352Sjfv DEBUGOUT("SOL\n"); 1181185352Sjfv } else { 1182185352Sjfv DEBUGOUT("Bad control value\n"); 1183185352Sjfv ret_val = IXGBE_ERR_PHY; 1184185352Sjfv goto out; 1185185352Sjfv } 1186185352Sjfv break; 1187185352Sjfv default: 1188185352Sjfv DEBUGOUT("Bad control type\n"); 1189185352Sjfv ret_val = IXGBE_ERR_PHY; 1190185352Sjfv goto out; 1191185352Sjfv } 1192185352Sjfv } 1193185352Sjfv 1194185352Sjfvout: 1195185352Sjfv return ret_val; 1196251964Sjfv 1197251964Sjfverr_eeprom: 1198251964Sjfv ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1199251964Sjfv "eeprom read at offset %d failed", data_offset); 1200251964Sjfv return IXGBE_ERR_PHY; 1201185352Sjfv} 1202185352Sjfv 1203185352Sjfv/** 1204230775Sjfv * ixgbe_identify_module_generic - Identifies module type 1205230775Sjfv * @hw: pointer to hardware structure 1206230775Sjfv * 1207230775Sjfv * Determines HW type and calls appropriate function. 1208230775Sjfv **/ 1209230775Sjfvs32 ixgbe_identify_module_generic(struct ixgbe_hw *hw) 1210230775Sjfv{ 1211230775Sjfv s32 status = IXGBE_ERR_SFP_NOT_PRESENT; 1212230775Sjfv 1213230775Sjfv DEBUGFUNC("ixgbe_identify_module_generic"); 1214230775Sjfv 1215230775Sjfv switch (hw->mac.ops.get_media_type(hw)) { 1216230775Sjfv case ixgbe_media_type_fiber: 1217230775Sjfv status = ixgbe_identify_sfp_module_generic(hw); 1218230775Sjfv break; 1219230775Sjfv 1220280182Sjfv case ixgbe_media_type_fiber_qsfp: 1221280182Sjfv status = ixgbe_identify_qsfp_module_generic(hw); 1222280182Sjfv break; 1223230775Sjfv 1224230775Sjfv default: 1225230775Sjfv hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1226230775Sjfv status = IXGBE_ERR_SFP_NOT_PRESENT; 1227230775Sjfv break; 1228230775Sjfv } 1229230775Sjfv 1230230775Sjfv return status; 1231230775Sjfv} 1232230775Sjfv 1233230775Sjfv/** 1234185352Sjfv * ixgbe_identify_sfp_module_generic - Identifies SFP modules 1235185352Sjfv * @hw: pointer to hardware structure 1236185352Sjfv * 1237185352Sjfv * Searches for and identifies the SFP module and assigns appropriate PHY type. 1238185352Sjfv **/ 1239185352Sjfvs32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) 1240185352Sjfv{ 1241185352Sjfv s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1242185352Sjfv u32 vendor_oui = 0; 1243190873Sjfv enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1244185352Sjfv u8 identifier = 0; 1245185352Sjfv u8 comp_codes_1g = 0; 1246185352Sjfv u8 comp_codes_10g = 0; 1247190873Sjfv u8 oui_bytes[3] = {0, 0, 0}; 1248194875Sjfv u8 cable_tech = 0; 1249205720Sjfv u8 cable_spec = 0; 1250190873Sjfv u16 enforce_sfp = 0; 1251185352Sjfv 1252200239Sjfv DEBUGFUNC("ixgbe_identify_sfp_module_generic"); 1253200239Sjfv 1254194875Sjfv if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) { 1255194875Sjfv hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1256194875Sjfv status = IXGBE_ERR_SFP_NOT_PRESENT; 1257194875Sjfv goto out; 1258215911Sjfv } 1259194875Sjfv 1260280182Sjfv /* LAN ID is needed for I2C access */ 1261280182Sjfv hw->mac.ops.set_lan_id(hw); 1262280182Sjfv 1263215911Sjfv status = hw->phy.ops.read_i2c_eeprom(hw, 1264230775Sjfv IXGBE_SFF_IDENTIFIER, 1265230775Sjfv &identifier); 1266185352Sjfv 1267247822Sjfv if (status != IXGBE_SUCCESS) 1268215911Sjfv goto err_read_i2c_eeprom; 1269185352Sjfv 1270194875Sjfv if (identifier != IXGBE_SFF_IDENTIFIER_SFP) { 1271194875Sjfv hw->phy.type = ixgbe_phy_sfp_unsupported; 1272194875Sjfv status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1273194875Sjfv } else { 1274215911Sjfv status = hw->phy.ops.read_i2c_eeprom(hw, 1275230775Sjfv IXGBE_SFF_1GBE_COMP_CODES, 1276230775Sjfv &comp_codes_1g); 1277185352Sjfv 1278247822Sjfv if (status != IXGBE_SUCCESS) 1279215911Sjfv goto err_read_i2c_eeprom; 1280215911Sjfv 1281215911Sjfv status = hw->phy.ops.read_i2c_eeprom(hw, 1282230775Sjfv IXGBE_SFF_10GBE_COMP_CODES, 1283230775Sjfv &comp_codes_10g); 1284215911Sjfv 1285247822Sjfv if (status != IXGBE_SUCCESS) 1286215911Sjfv goto err_read_i2c_eeprom; 1287215911Sjfv status = hw->phy.ops.read_i2c_eeprom(hw, 1288230775Sjfv IXGBE_SFF_CABLE_TECHNOLOGY, 1289230775Sjfv &cable_tech); 1290215911Sjfv 1291247822Sjfv if (status != IXGBE_SUCCESS) 1292215911Sjfv goto err_read_i2c_eeprom; 1293215911Sjfv 1294185352Sjfv /* ID Module 1295185352Sjfv * ========= 1296185352Sjfv * 0 SFP_DA_CU 1297185352Sjfv * 1 SFP_SR 1298185352Sjfv * 2 SFP_LR 1299190873Sjfv * 3 SFP_DA_CORE0 - 82599-specific 1300190873Sjfv * 4 SFP_DA_CORE1 - 82599-specific 1301190873Sjfv * 5 SFP_SR/LR_CORE0 - 82599-specific 1302190873Sjfv * 6 SFP_SR/LR_CORE1 - 82599-specific 1303205720Sjfv * 7 SFP_act_lmt_DA_CORE0 - 82599-specific 1304205720Sjfv * 8 SFP_act_lmt_DA_CORE1 - 82599-specific 1305215911Sjfv * 9 SFP_1g_cu_CORE0 - 82599-specific 1306215911Sjfv * 10 SFP_1g_cu_CORE1 - 82599-specific 1307238149Sjfv * 11 SFP_1g_sx_CORE0 - 82599-specific 1308238149Sjfv * 12 SFP_1g_sx_CORE1 - 82599-specific 1309185352Sjfv */ 1310190873Sjfv if (hw->mac.type == ixgbe_mac_82598EB) { 1311194875Sjfv if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1312190873Sjfv hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 1313190873Sjfv else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1314190873Sjfv hw->phy.sfp_type = ixgbe_sfp_type_sr; 1315190873Sjfv else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1316190873Sjfv hw->phy.sfp_type = ixgbe_sfp_type_lr; 1317190873Sjfv else 1318190873Sjfv hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1319280182Sjfv } else { 1320205720Sjfv if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) { 1321190873Sjfv if (hw->bus.lan_id == 0) 1322190873Sjfv hw->phy.sfp_type = 1323230775Sjfv ixgbe_sfp_type_da_cu_core0; 1324190873Sjfv else 1325190873Sjfv hw->phy.sfp_type = 1326230775Sjfv ixgbe_sfp_type_da_cu_core1; 1327205720Sjfv } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) { 1328205720Sjfv hw->phy.ops.read_i2c_eeprom( 1329205720Sjfv hw, IXGBE_SFF_CABLE_SPEC_COMP, 1330205720Sjfv &cable_spec); 1331205720Sjfv if (cable_spec & 1332215911Sjfv IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) { 1333205720Sjfv if (hw->bus.lan_id == 0) 1334205720Sjfv hw->phy.sfp_type = 1335205720Sjfv ixgbe_sfp_type_da_act_lmt_core0; 1336205720Sjfv else 1337205720Sjfv hw->phy.sfp_type = 1338205720Sjfv ixgbe_sfp_type_da_act_lmt_core1; 1339215911Sjfv } else { 1340190873Sjfv hw->phy.sfp_type = 1341230775Sjfv ixgbe_sfp_type_unknown; 1342215911Sjfv } 1343205720Sjfv } else if (comp_codes_10g & 1344205720Sjfv (IXGBE_SFF_10GBASESR_CAPABLE | 1345215911Sjfv IXGBE_SFF_10GBASELR_CAPABLE)) { 1346190873Sjfv if (hw->bus.lan_id == 0) 1347190873Sjfv hw->phy.sfp_type = 1348230775Sjfv ixgbe_sfp_type_srlr_core0; 1349190873Sjfv else 1350190873Sjfv hw->phy.sfp_type = 1351230775Sjfv ixgbe_sfp_type_srlr_core1; 1352215911Sjfv } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) { 1353215911Sjfv if (hw->bus.lan_id == 0) 1354215911Sjfv hw->phy.sfp_type = 1355215911Sjfv ixgbe_sfp_type_1g_cu_core0; 1356215911Sjfv else 1357215911Sjfv hw->phy.sfp_type = 1358215911Sjfv ixgbe_sfp_type_1g_cu_core1; 1359238149Sjfv } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) { 1360238149Sjfv if (hw->bus.lan_id == 0) 1361238149Sjfv hw->phy.sfp_type = 1362238149Sjfv ixgbe_sfp_type_1g_sx_core0; 1363238149Sjfv else 1364238149Sjfv hw->phy.sfp_type = 1365238149Sjfv ixgbe_sfp_type_1g_sx_core1; 1366205720Sjfv } else { 1367190873Sjfv hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1368205720Sjfv } 1369190873Sjfv } 1370185352Sjfv 1371190873Sjfv if (hw->phy.sfp_type != stored_sfp_type) 1372190873Sjfv hw->phy.sfp_setup_needed = TRUE; 1373190873Sjfv 1374185352Sjfv /* Determine if the SFP+ PHY is dual speed or not. */ 1375194875Sjfv hw->phy.multispeed_fiber = FALSE; 1376190873Sjfv if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1377190873Sjfv (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1378190873Sjfv ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1379190873Sjfv (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1380185352Sjfv hw->phy.multispeed_fiber = TRUE; 1381200239Sjfv 1382185352Sjfv /* Determine PHY vendor */ 1383190873Sjfv if (hw->phy.type != ixgbe_phy_nl) { 1384185352Sjfv hw->phy.id = identifier; 1385215911Sjfv status = hw->phy.ops.read_i2c_eeprom(hw, 1386230775Sjfv IXGBE_SFF_VENDOR_OUI_BYTE0, 1387230775Sjfv &oui_bytes[0]); 1388215911Sjfv 1389247822Sjfv if (status != IXGBE_SUCCESS) 1390215911Sjfv goto err_read_i2c_eeprom; 1391215911Sjfv 1392215911Sjfv status = hw->phy.ops.read_i2c_eeprom(hw, 1393230775Sjfv IXGBE_SFF_VENDOR_OUI_BYTE1, 1394230775Sjfv &oui_bytes[1]); 1395215911Sjfv 1396247822Sjfv if (status != IXGBE_SUCCESS) 1397215911Sjfv goto err_read_i2c_eeprom; 1398215911Sjfv 1399215911Sjfv status = hw->phy.ops.read_i2c_eeprom(hw, 1400230775Sjfv IXGBE_SFF_VENDOR_OUI_BYTE2, 1401230775Sjfv &oui_bytes[2]); 1402185352Sjfv 1403247822Sjfv if (status != IXGBE_SUCCESS) 1404215911Sjfv goto err_read_i2c_eeprom; 1405215911Sjfv 1406185352Sjfv vendor_oui = 1407215911Sjfv ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1408215911Sjfv (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1409215911Sjfv (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1410185352Sjfv 1411185352Sjfv switch (vendor_oui) { 1412185352Sjfv case IXGBE_SFF_VENDOR_OUI_TYCO: 1413194875Sjfv if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1414205720Sjfv hw->phy.type = 1415230775Sjfv ixgbe_phy_sfp_passive_tyco; 1416185352Sjfv break; 1417185352Sjfv case IXGBE_SFF_VENDOR_OUI_FTL: 1418205720Sjfv if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1419205720Sjfv hw->phy.type = ixgbe_phy_sfp_ftl_active; 1420205720Sjfv else 1421205720Sjfv hw->phy.type = ixgbe_phy_sfp_ftl; 1422185352Sjfv break; 1423185352Sjfv case IXGBE_SFF_VENDOR_OUI_AVAGO: 1424185352Sjfv hw->phy.type = ixgbe_phy_sfp_avago; 1425185352Sjfv break; 1426190873Sjfv case IXGBE_SFF_VENDOR_OUI_INTEL: 1427190873Sjfv hw->phy.type = ixgbe_phy_sfp_intel; 1428190873Sjfv break; 1429185352Sjfv default: 1430194875Sjfv if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1431205720Sjfv hw->phy.type = 1432230775Sjfv ixgbe_phy_sfp_passive_unknown; 1433205720Sjfv else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1434205720Sjfv hw->phy.type = 1435205720Sjfv ixgbe_phy_sfp_active_unknown; 1436185352Sjfv else 1437185352Sjfv hw->phy.type = ixgbe_phy_sfp_unknown; 1438185352Sjfv break; 1439185352Sjfv } 1440185352Sjfv } 1441190873Sjfv 1442205720Sjfv /* Allow any DA cable vendor */ 1443205720Sjfv if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE | 1444205720Sjfv IXGBE_SFF_DA_ACTIVE_CABLE)) { 1445194875Sjfv status = IXGBE_SUCCESS; 1446194875Sjfv goto out; 1447194875Sjfv } 1448194875Sjfv 1449215911Sjfv /* Verify supported 1G SFP modules */ 1450215911Sjfv if (comp_codes_10g == 0 && 1451215911Sjfv !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1452238149Sjfv hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1453251964Sjfv hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1454238149Sjfv hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1455190873Sjfv hw->phy.type = ixgbe_phy_sfp_unsupported; 1456190873Sjfv status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1457190873Sjfv goto out; 1458190873Sjfv } 1459194875Sjfv 1460194875Sjfv /* Anything else 82598-based is supported */ 1461194875Sjfv if (hw->mac.type == ixgbe_mac_82598EB) { 1462190873Sjfv status = IXGBE_SUCCESS; 1463190873Sjfv goto out; 1464190873Sjfv } 1465190873Sjfv 1466190873Sjfv ixgbe_get_device_caps(hw, &enforce_sfp); 1467215911Sjfv if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) && 1468251964Sjfv !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1469251964Sjfv hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1470251964Sjfv hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1471251964Sjfv hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1472190873Sjfv /* Make sure we're a supported PHY type */ 1473190873Sjfv if (hw->phy.type == ixgbe_phy_sfp_intel) { 1474190873Sjfv status = IXGBE_SUCCESS; 1475190873Sjfv } else { 1476247056Sdes if (hw->allow_unsupported_sfp == TRUE) { 1477247056Sdes EWARN(hw, "WARNING: Intel (R) Network " 1478247056Sdes "Connections are quality tested " 1479247056Sdes "using Intel (R) Ethernet Optics." 1480247056Sdes " Using untested modules is not " 1481247056Sdes "supported and may cause unstable" 1482247056Sdes " operation or damage to the " 1483247056Sdes "module or the adapter. Intel " 1484247056Sdes "Corporation is not responsible " 1485247056Sdes "for any harm caused by using " 1486247056Sdes "untested modules.\n", status); 1487247056Sdes status = IXGBE_SUCCESS; 1488247056Sdes } else { 1489247056Sdes DEBUGOUT("SFP+ module not supported\n"); 1490247056Sdes hw->phy.type = 1491247056Sdes ixgbe_phy_sfp_unsupported; 1492247056Sdes status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1493247056Sdes } 1494190873Sjfv } 1495190873Sjfv } else { 1496190873Sjfv status = IXGBE_SUCCESS; 1497190873Sjfv } 1498185352Sjfv } 1499185352Sjfv 1500185352Sjfvout: 1501185352Sjfv return status; 1502215911Sjfv 1503215911Sjfverr_read_i2c_eeprom: 1504215911Sjfv hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1505215911Sjfv if (hw->phy.type != ixgbe_phy_nl) { 1506215911Sjfv hw->phy.id = 0; 1507215911Sjfv hw->phy.type = ixgbe_phy_unknown; 1508215911Sjfv } 1509215911Sjfv return IXGBE_ERR_SFP_NOT_PRESENT; 1510185352Sjfv} 1511185352Sjfv 1512280182Sjfv/** 1513280182Sjfv * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type 1514280182Sjfv * @hw: pointer to hardware structure 1515280182Sjfv * 1516280182Sjfv * Determines physical layer capabilities of the current SFP. 1517280182Sjfv */ 1518280182Sjfvs32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw) 1519280182Sjfv{ 1520280182Sjfv u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1521280182Sjfv u8 comp_codes_10g = 0; 1522280182Sjfv u8 comp_codes_1g = 0; 1523230775Sjfv 1524280182Sjfv DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic"); 1525230775Sjfv 1526280182Sjfv hw->phy.ops.identify_sfp(hw); 1527280182Sjfv if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1528280182Sjfv return physical_layer; 1529280182Sjfv 1530280182Sjfv switch (hw->phy.type) { 1531280182Sjfv case ixgbe_phy_sfp_passive_tyco: 1532280182Sjfv case ixgbe_phy_sfp_passive_unknown: 1533280182Sjfv case ixgbe_phy_qsfp_passive_unknown: 1534280182Sjfv physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1535280182Sjfv break; 1536280182Sjfv case ixgbe_phy_sfp_ftl_active: 1537280182Sjfv case ixgbe_phy_sfp_active_unknown: 1538280182Sjfv case ixgbe_phy_qsfp_active_unknown: 1539280182Sjfv physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA; 1540280182Sjfv break; 1541280182Sjfv case ixgbe_phy_sfp_avago: 1542280182Sjfv case ixgbe_phy_sfp_ftl: 1543280182Sjfv case ixgbe_phy_sfp_intel: 1544280182Sjfv case ixgbe_phy_sfp_unknown: 1545280182Sjfv hw->phy.ops.read_i2c_eeprom(hw, 1546280182Sjfv IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g); 1547280182Sjfv hw->phy.ops.read_i2c_eeprom(hw, 1548280182Sjfv IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g); 1549280182Sjfv if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1550280182Sjfv physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1551280182Sjfv else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1552280182Sjfv physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1553280182Sjfv else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) 1554280182Sjfv physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T; 1555280182Sjfv else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) 1556280182Sjfv physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX; 1557280182Sjfv break; 1558280182Sjfv case ixgbe_phy_qsfp_intel: 1559280182Sjfv case ixgbe_phy_qsfp_unknown: 1560280182Sjfv hw->phy.ops.read_i2c_eeprom(hw, 1561280182Sjfv IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g); 1562280182Sjfv if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1563280182Sjfv physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1564280182Sjfv else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1565280182Sjfv physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1566280182Sjfv break; 1567280182Sjfv default: 1568280182Sjfv break; 1569280182Sjfv } 1570280182Sjfv 1571280182Sjfv return physical_layer; 1572280182Sjfv} 1573280182Sjfv 1574185352Sjfv/** 1575280182Sjfv * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules 1576280182Sjfv * @hw: pointer to hardware structure 1577280182Sjfv * 1578280182Sjfv * Searches for and identifies the QSFP module and assigns appropriate PHY type 1579280182Sjfv **/ 1580280182Sjfvs32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw) 1581280182Sjfv{ 1582280182Sjfv s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1583280182Sjfv u32 vendor_oui = 0; 1584280182Sjfv enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1585280182Sjfv u8 identifier = 0; 1586280182Sjfv u8 comp_codes_1g = 0; 1587280182Sjfv u8 comp_codes_10g = 0; 1588280182Sjfv u8 oui_bytes[3] = {0, 0, 0}; 1589280182Sjfv u16 enforce_sfp = 0; 1590280182Sjfv u8 connector = 0; 1591280182Sjfv u8 cable_length = 0; 1592280182Sjfv u8 device_tech = 0; 1593280182Sjfv bool active_cable = FALSE; 1594280182Sjfv 1595280182Sjfv DEBUGFUNC("ixgbe_identify_qsfp_module_generic"); 1596280182Sjfv 1597280182Sjfv if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) { 1598280182Sjfv hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1599280182Sjfv status = IXGBE_ERR_SFP_NOT_PRESENT; 1600280182Sjfv goto out; 1601280182Sjfv } 1602280182Sjfv 1603280182Sjfv status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER, 1604280182Sjfv &identifier); 1605280182Sjfv 1606280182Sjfv if (status != IXGBE_SUCCESS) 1607280182Sjfv goto err_read_i2c_eeprom; 1608280182Sjfv 1609280182Sjfv if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) { 1610280182Sjfv hw->phy.type = ixgbe_phy_sfp_unsupported; 1611280182Sjfv status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1612280182Sjfv goto out; 1613280182Sjfv } 1614280182Sjfv 1615280182Sjfv hw->phy.id = identifier; 1616280182Sjfv 1617280182Sjfv /* LAN ID is needed for sfp_type determination */ 1618280182Sjfv hw->mac.ops.set_lan_id(hw); 1619280182Sjfv 1620280182Sjfv status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP, 1621280182Sjfv &comp_codes_10g); 1622280182Sjfv 1623280182Sjfv if (status != IXGBE_SUCCESS) 1624280182Sjfv goto err_read_i2c_eeprom; 1625280182Sjfv 1626280182Sjfv status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP, 1627280182Sjfv &comp_codes_1g); 1628280182Sjfv 1629280182Sjfv if (status != IXGBE_SUCCESS) 1630280182Sjfv goto err_read_i2c_eeprom; 1631280182Sjfv 1632280182Sjfv if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) { 1633280182Sjfv hw->phy.type = ixgbe_phy_qsfp_passive_unknown; 1634280182Sjfv if (hw->bus.lan_id == 0) 1635280182Sjfv hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0; 1636280182Sjfv else 1637280182Sjfv hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1; 1638280182Sjfv } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1639280182Sjfv IXGBE_SFF_10GBASELR_CAPABLE)) { 1640280182Sjfv if (hw->bus.lan_id == 0) 1641280182Sjfv hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0; 1642280182Sjfv else 1643280182Sjfv hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1; 1644280182Sjfv } else { 1645280182Sjfv if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE) 1646280182Sjfv active_cable = TRUE; 1647280182Sjfv 1648280182Sjfv if (!active_cable) { 1649280182Sjfv /* check for active DA cables that pre-date 1650280182Sjfv * SFF-8436 v3.6 */ 1651280182Sjfv hw->phy.ops.read_i2c_eeprom(hw, 1652280182Sjfv IXGBE_SFF_QSFP_CONNECTOR, 1653280182Sjfv &connector); 1654280182Sjfv 1655280182Sjfv hw->phy.ops.read_i2c_eeprom(hw, 1656280182Sjfv IXGBE_SFF_QSFP_CABLE_LENGTH, 1657280182Sjfv &cable_length); 1658280182Sjfv 1659280182Sjfv hw->phy.ops.read_i2c_eeprom(hw, 1660280182Sjfv IXGBE_SFF_QSFP_DEVICE_TECH, 1661280182Sjfv &device_tech); 1662280182Sjfv 1663280182Sjfv if ((connector == 1664280182Sjfv IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) && 1665280182Sjfv (cable_length > 0) && 1666280182Sjfv ((device_tech >> 4) == 1667280182Sjfv IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL)) 1668280182Sjfv active_cable = TRUE; 1669280182Sjfv } 1670280182Sjfv 1671280182Sjfv if (active_cable) { 1672280182Sjfv hw->phy.type = ixgbe_phy_qsfp_active_unknown; 1673280182Sjfv if (hw->bus.lan_id == 0) 1674280182Sjfv hw->phy.sfp_type = 1675280182Sjfv ixgbe_sfp_type_da_act_lmt_core0; 1676280182Sjfv else 1677280182Sjfv hw->phy.sfp_type = 1678280182Sjfv ixgbe_sfp_type_da_act_lmt_core1; 1679280182Sjfv } else { 1680280182Sjfv /* unsupported module type */ 1681280182Sjfv hw->phy.type = ixgbe_phy_sfp_unsupported; 1682280182Sjfv status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1683280182Sjfv goto out; 1684280182Sjfv } 1685280182Sjfv } 1686280182Sjfv 1687280182Sjfv if (hw->phy.sfp_type != stored_sfp_type) 1688280182Sjfv hw->phy.sfp_setup_needed = TRUE; 1689280182Sjfv 1690280182Sjfv /* Determine if the QSFP+ PHY is dual speed or not. */ 1691280182Sjfv hw->phy.multispeed_fiber = FALSE; 1692280182Sjfv if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1693280182Sjfv (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1694280182Sjfv ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1695280182Sjfv (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1696280182Sjfv hw->phy.multispeed_fiber = TRUE; 1697280182Sjfv 1698280182Sjfv /* Determine PHY vendor for optical modules */ 1699280182Sjfv if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1700280182Sjfv IXGBE_SFF_10GBASELR_CAPABLE)) { 1701280182Sjfv status = hw->phy.ops.read_i2c_eeprom(hw, 1702280182Sjfv IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0, 1703280182Sjfv &oui_bytes[0]); 1704280182Sjfv 1705280182Sjfv if (status != IXGBE_SUCCESS) 1706280182Sjfv goto err_read_i2c_eeprom; 1707280182Sjfv 1708280182Sjfv status = hw->phy.ops.read_i2c_eeprom(hw, 1709280182Sjfv IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1, 1710280182Sjfv &oui_bytes[1]); 1711280182Sjfv 1712280182Sjfv if (status != IXGBE_SUCCESS) 1713280182Sjfv goto err_read_i2c_eeprom; 1714280182Sjfv 1715280182Sjfv status = hw->phy.ops.read_i2c_eeprom(hw, 1716280182Sjfv IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2, 1717280182Sjfv &oui_bytes[2]); 1718280182Sjfv 1719280182Sjfv if (status != IXGBE_SUCCESS) 1720280182Sjfv goto err_read_i2c_eeprom; 1721280182Sjfv 1722280182Sjfv vendor_oui = 1723280182Sjfv ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1724280182Sjfv (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1725280182Sjfv (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1726280182Sjfv 1727280182Sjfv if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL) 1728280182Sjfv hw->phy.type = ixgbe_phy_qsfp_intel; 1729280182Sjfv else 1730280182Sjfv hw->phy.type = ixgbe_phy_qsfp_unknown; 1731280182Sjfv 1732280182Sjfv ixgbe_get_device_caps(hw, &enforce_sfp); 1733280182Sjfv if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) { 1734280182Sjfv /* Make sure we're a supported PHY type */ 1735280182Sjfv if (hw->phy.type == ixgbe_phy_qsfp_intel) { 1736280182Sjfv status = IXGBE_SUCCESS; 1737280182Sjfv } else { 1738280182Sjfv if (hw->allow_unsupported_sfp == TRUE) { 1739280182Sjfv EWARN(hw, "WARNING: Intel (R) Network " 1740280182Sjfv "Connections are quality tested " 1741280182Sjfv "using Intel (R) Ethernet Optics." 1742280182Sjfv " Using untested modules is not " 1743280182Sjfv "supported and may cause unstable" 1744280182Sjfv " operation or damage to the " 1745280182Sjfv "module or the adapter. Intel " 1746280182Sjfv "Corporation is not responsible " 1747280182Sjfv "for any harm caused by using " 1748280182Sjfv "untested modules.\n", status); 1749280182Sjfv status = IXGBE_SUCCESS; 1750280182Sjfv } else { 1751280182Sjfv DEBUGOUT("QSFP module not supported\n"); 1752280182Sjfv hw->phy.type = 1753280182Sjfv ixgbe_phy_sfp_unsupported; 1754280182Sjfv status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1755280182Sjfv } 1756280182Sjfv } 1757280182Sjfv } else { 1758280182Sjfv status = IXGBE_SUCCESS; 1759280182Sjfv } 1760280182Sjfv } 1761280182Sjfv 1762280182Sjfvout: 1763280182Sjfv return status; 1764280182Sjfv 1765280182Sjfverr_read_i2c_eeprom: 1766280182Sjfv hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1767280182Sjfv hw->phy.id = 0; 1768280182Sjfv hw->phy.type = ixgbe_phy_unknown; 1769280182Sjfv 1770280182Sjfv return IXGBE_ERR_SFP_NOT_PRESENT; 1771280182Sjfv} 1772280182Sjfv 1773280182Sjfv 1774280182Sjfv/** 1775185352Sjfv * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence 1776185352Sjfv * @hw: pointer to hardware structure 1777185352Sjfv * @list_offset: offset to the SFP ID list 1778185352Sjfv * @data_offset: offset to the SFP data block 1779185352Sjfv * 1780185352Sjfv * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if 1781185352Sjfv * so it returns the offsets to the phy init sequence block. 1782185352Sjfv **/ 1783185352Sjfvs32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 1784230775Sjfv u16 *list_offset, 1785230775Sjfv u16 *data_offset) 1786185352Sjfv{ 1787185352Sjfv u16 sfp_id; 1788205720Sjfv u16 sfp_type = hw->phy.sfp_type; 1789185352Sjfv 1790200239Sjfv DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets"); 1791200239Sjfv 1792185352Sjfv if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 1793185352Sjfv return IXGBE_ERR_SFP_NOT_SUPPORTED; 1794185352Sjfv 1795185352Sjfv if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1796185352Sjfv return IXGBE_ERR_SFP_NOT_PRESENT; 1797185352Sjfv 1798185352Sjfv if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && 1799185352Sjfv (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) 1800185352Sjfv return IXGBE_ERR_SFP_NOT_SUPPORTED; 1801185352Sjfv 1802215911Sjfv /* 1803215911Sjfv * Limiting active cables and 1G Phys must be initialized as 1804215911Sjfv * SR modules 1805215911Sjfv */ 1806215911Sjfv if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 || 1807238149Sjfv sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1808238149Sjfv sfp_type == ixgbe_sfp_type_1g_sx_core0) 1809205720Sjfv sfp_type = ixgbe_sfp_type_srlr_core0; 1810215911Sjfv else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 || 1811238149Sjfv sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1812238149Sjfv sfp_type == ixgbe_sfp_type_1g_sx_core1) 1813205720Sjfv sfp_type = ixgbe_sfp_type_srlr_core1; 1814205720Sjfv 1815185352Sjfv /* Read offset to PHY init contents */ 1816251964Sjfv if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) { 1817251964Sjfv ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1818251964Sjfv "eeprom read at offset %d failed", 1819251964Sjfv IXGBE_PHY_INIT_OFFSET_NL); 1820251964Sjfv return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1821251964Sjfv } 1822185352Sjfv 1823185352Sjfv if ((!*list_offset) || (*list_offset == 0xFFFF)) 1824190873Sjfv return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1825185352Sjfv 1826185352Sjfv /* Shift offset to first ID word */ 1827185352Sjfv (*list_offset)++; 1828185352Sjfv 1829185352Sjfv /* 1830185352Sjfv * Find the matching SFP ID in the EEPROM 1831185352Sjfv * and program the init sequence 1832185352Sjfv */ 1833251964Sjfv if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1834251964Sjfv goto err_phy; 1835185352Sjfv 1836185352Sjfv while (sfp_id != IXGBE_PHY_INIT_END_NL) { 1837205720Sjfv if (sfp_id == sfp_type) { 1838185352Sjfv (*list_offset)++; 1839251964Sjfv if (hw->eeprom.ops.read(hw, *list_offset, data_offset)) 1840251964Sjfv goto err_phy; 1841185352Sjfv if ((!*data_offset) || (*data_offset == 0xFFFF)) { 1842185352Sjfv DEBUGOUT("SFP+ module not supported\n"); 1843185352Sjfv return IXGBE_ERR_SFP_NOT_SUPPORTED; 1844185352Sjfv } else { 1845185352Sjfv break; 1846185352Sjfv } 1847185352Sjfv } else { 1848185352Sjfv (*list_offset) += 2; 1849185352Sjfv if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1850251964Sjfv goto err_phy; 1851185352Sjfv } 1852185352Sjfv } 1853185352Sjfv 1854185352Sjfv if (sfp_id == IXGBE_PHY_INIT_END_NL) { 1855185352Sjfv DEBUGOUT("No matching SFP+ module found\n"); 1856185352Sjfv return IXGBE_ERR_SFP_NOT_SUPPORTED; 1857185352Sjfv } 1858185352Sjfv 1859185352Sjfv return IXGBE_SUCCESS; 1860251964Sjfv 1861251964Sjfverr_phy: 1862251964Sjfv ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1863251964Sjfv "eeprom read at offset %d failed", *list_offset); 1864251964Sjfv return IXGBE_ERR_PHY; 1865185352Sjfv} 1866185352Sjfv 1867190873Sjfv/** 1868190873Sjfv * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface 1869190873Sjfv * @hw: pointer to hardware structure 1870190873Sjfv * @byte_offset: EEPROM byte offset to read 1871190873Sjfv * @eeprom_data: value read 1872190873Sjfv * 1873190873Sjfv * Performs byte read operation to SFP module's EEPROM over I2C interface. 1874190873Sjfv **/ 1875190873Sjfvs32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1876230775Sjfv u8 *eeprom_data) 1877190873Sjfv{ 1878190873Sjfv DEBUGFUNC("ixgbe_read_i2c_eeprom_generic"); 1879190873Sjfv 1880190873Sjfv return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1881230775Sjfv IXGBE_I2C_EEPROM_DEV_ADDR, 1882230775Sjfv eeprom_data); 1883190873Sjfv} 1884190873Sjfv 1885190873Sjfv/** 1886247822Sjfv * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface 1887247822Sjfv * @hw: pointer to hardware structure 1888247822Sjfv * @byte_offset: byte offset at address 0xA2 1889247822Sjfv * @eeprom_data: value read 1890247822Sjfv * 1891247822Sjfv * Performs byte read operation to SFP module's SFF-8472 data over I2C 1892247822Sjfv **/ 1893247822Sjfvstatic s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 1894247822Sjfv u8 *sff8472_data) 1895247822Sjfv{ 1896247822Sjfv return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1897247822Sjfv IXGBE_I2C_EEPROM_DEV_ADDR2, 1898247822Sjfv sff8472_data); 1899247822Sjfv} 1900247822Sjfv 1901247822Sjfv/** 1902190873Sjfv * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface 1903190873Sjfv * @hw: pointer to hardware structure 1904190873Sjfv * @byte_offset: EEPROM byte offset to write 1905190873Sjfv * @eeprom_data: value to write 1906190873Sjfv * 1907190873Sjfv * Performs byte write operation to SFP module's EEPROM over I2C interface. 1908190873Sjfv **/ 1909190873Sjfvs32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1910230775Sjfv u8 eeprom_data) 1911190873Sjfv{ 1912190873Sjfv DEBUGFUNC("ixgbe_write_i2c_eeprom_generic"); 1913190873Sjfv 1914190873Sjfv return hw->phy.ops.write_i2c_byte(hw, byte_offset, 1915230775Sjfv IXGBE_I2C_EEPROM_DEV_ADDR, 1916230775Sjfv eeprom_data); 1917190873Sjfv} 1918190873Sjfv 1919190873Sjfv/** 1920280182Sjfv * ixgbe_is_sfp_probe - Returns TRUE if SFP is being detected 1921280182Sjfv * @hw: pointer to hardware structure 1922280182Sjfv * @offset: eeprom offset to be read 1923280182Sjfv * @addr: I2C address to be read 1924280182Sjfv */ 1925280182Sjfvstatic bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr) 1926280182Sjfv{ 1927280182Sjfv if (addr == IXGBE_I2C_EEPROM_DEV_ADDR && 1928280182Sjfv offset == IXGBE_SFF_IDENTIFIER && 1929280182Sjfv hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1930280182Sjfv return TRUE; 1931280182Sjfv return FALSE; 1932280182Sjfv} 1933280182Sjfv 1934280182Sjfv/** 1935190873Sjfv * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C 1936190873Sjfv * @hw: pointer to hardware structure 1937190873Sjfv * @byte_offset: byte offset to read 1938190873Sjfv * @data: value read 1939190873Sjfv * 1940190873Sjfv * Performs byte read operation to SFP module's EEPROM over I2C interface at 1941230775Sjfv * a specified device address. 1942190873Sjfv **/ 1943190873Sjfvs32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 1944230775Sjfv u8 dev_addr, u8 *data) 1945190873Sjfv{ 1946280182Sjfv s32 status; 1947194875Sjfv u32 max_retry = 10; 1948190873Sjfv u32 retry = 0; 1949280182Sjfv u32 swfw_mask = hw->phy.phy_semaphore_mask; 1950190873Sjfv bool nack = 1; 1951230775Sjfv *data = 0; 1952190873Sjfv 1953190873Sjfv DEBUGFUNC("ixgbe_read_i2c_byte_generic"); 1954190873Sjfv 1955280182Sjfv if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr)) 1956280182Sjfv max_retry = IXGBE_SFP_DETECT_RETRIES; 1957190873Sjfv 1958190873Sjfv do { 1959280182Sjfv if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 1960280182Sjfv return IXGBE_ERR_SWFW_SYNC; 1961194875Sjfv 1962190873Sjfv ixgbe_i2c_start(hw); 1963190873Sjfv 1964190873Sjfv /* Device Address and write indication */ 1965190873Sjfv status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 1966190873Sjfv if (status != IXGBE_SUCCESS) 1967190873Sjfv goto fail; 1968190873Sjfv 1969190873Sjfv status = ixgbe_get_i2c_ack(hw); 1970190873Sjfv if (status != IXGBE_SUCCESS) 1971190873Sjfv goto fail; 1972190873Sjfv 1973190873Sjfv status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 1974190873Sjfv if (status != IXGBE_SUCCESS) 1975190873Sjfv goto fail; 1976190873Sjfv 1977190873Sjfv status = ixgbe_get_i2c_ack(hw); 1978190873Sjfv if (status != IXGBE_SUCCESS) 1979190873Sjfv goto fail; 1980190873Sjfv 1981190873Sjfv ixgbe_i2c_start(hw); 1982190873Sjfv 1983190873Sjfv /* Device Address and read indication */ 1984190873Sjfv status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 1985190873Sjfv if (status != IXGBE_SUCCESS) 1986190873Sjfv goto fail; 1987190873Sjfv 1988190873Sjfv status = ixgbe_get_i2c_ack(hw); 1989190873Sjfv if (status != IXGBE_SUCCESS) 1990190873Sjfv goto fail; 1991190873Sjfv 1992190873Sjfv status = ixgbe_clock_in_i2c_byte(hw, data); 1993190873Sjfv if (status != IXGBE_SUCCESS) 1994190873Sjfv goto fail; 1995190873Sjfv 1996190873Sjfv status = ixgbe_clock_out_i2c_bit(hw, nack); 1997190873Sjfv if (status != IXGBE_SUCCESS) 1998190873Sjfv goto fail; 1999190873Sjfv 2000190873Sjfv ixgbe_i2c_stop(hw); 2001280182Sjfv hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2002280182Sjfv return IXGBE_SUCCESS; 2003190873Sjfv 2004190873Sjfvfail: 2005247822Sjfv ixgbe_i2c_bus_clear(hw); 2006230775Sjfv hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2007194875Sjfv msec_delay(100); 2008190873Sjfv retry++; 2009190873Sjfv if (retry < max_retry) 2010190873Sjfv DEBUGOUT("I2C byte read error - Retrying.\n"); 2011190873Sjfv else 2012190873Sjfv DEBUGOUT("I2C byte read error.\n"); 2013190873Sjfv 2014190873Sjfv } while (retry < max_retry); 2015190873Sjfv 2016190873Sjfv return status; 2017190873Sjfv} 2018190873Sjfv 2019190873Sjfv/** 2020190873Sjfv * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C 2021190873Sjfv * @hw: pointer to hardware structure 2022190873Sjfv * @byte_offset: byte offset to write 2023190873Sjfv * @data: value to write 2024190873Sjfv * 2025190873Sjfv * Performs byte write operation to SFP module's EEPROM over I2C interface at 2026190873Sjfv * a specified device address. 2027190873Sjfv **/ 2028190873Sjfvs32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 2029230775Sjfv u8 dev_addr, u8 data) 2030190873Sjfv{ 2031190873Sjfv s32 status = IXGBE_SUCCESS; 2032190873Sjfv u32 max_retry = 1; 2033190873Sjfv u32 retry = 0; 2034280182Sjfv u32 swfw_mask = hw->phy.phy_semaphore_mask; 2035190873Sjfv 2036190873Sjfv DEBUGFUNC("ixgbe_write_i2c_byte_generic"); 2037190873Sjfv 2038230775Sjfv if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) { 2039190873Sjfv status = IXGBE_ERR_SWFW_SYNC; 2040190873Sjfv goto write_byte_out; 2041190873Sjfv } 2042190873Sjfv 2043190873Sjfv do { 2044190873Sjfv ixgbe_i2c_start(hw); 2045190873Sjfv 2046190873Sjfv status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 2047190873Sjfv if (status != IXGBE_SUCCESS) 2048190873Sjfv goto fail; 2049190873Sjfv 2050190873Sjfv status = ixgbe_get_i2c_ack(hw); 2051190873Sjfv if (status != IXGBE_SUCCESS) 2052190873Sjfv goto fail; 2053190873Sjfv 2054190873Sjfv status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 2055190873Sjfv if (status != IXGBE_SUCCESS) 2056190873Sjfv goto fail; 2057190873Sjfv 2058190873Sjfv status = ixgbe_get_i2c_ack(hw); 2059190873Sjfv if (status != IXGBE_SUCCESS) 2060190873Sjfv goto fail; 2061190873Sjfv 2062190873Sjfv status = ixgbe_clock_out_i2c_byte(hw, data); 2063190873Sjfv if (status != IXGBE_SUCCESS) 2064190873Sjfv goto fail; 2065190873Sjfv 2066190873Sjfv status = ixgbe_get_i2c_ack(hw); 2067190873Sjfv if (status != IXGBE_SUCCESS) 2068190873Sjfv goto fail; 2069190873Sjfv 2070190873Sjfv ixgbe_i2c_stop(hw); 2071280182Sjfv hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2072280182Sjfv return IXGBE_SUCCESS; 2073190873Sjfv 2074190873Sjfvfail: 2075190873Sjfv ixgbe_i2c_bus_clear(hw); 2076190873Sjfv retry++; 2077190873Sjfv if (retry < max_retry) 2078190873Sjfv DEBUGOUT("I2C byte write error - Retrying.\n"); 2079190873Sjfv else 2080190873Sjfv DEBUGOUT("I2C byte write error.\n"); 2081190873Sjfv } while (retry < max_retry); 2082190873Sjfv 2083230775Sjfv hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2084190873Sjfv 2085190873Sjfvwrite_byte_out: 2086190873Sjfv return status; 2087190873Sjfv} 2088190873Sjfv 2089190873Sjfv/** 2090190873Sjfv * ixgbe_i2c_start - Sets I2C start condition 2091190873Sjfv * @hw: pointer to hardware structure 2092190873Sjfv * 2093190873Sjfv * Sets I2C start condition (High -> Low on SDA while SCL is High) 2094280182Sjfv * Set bit-bang mode on X550 hardware. 2095190873Sjfv **/ 2096190873Sjfvstatic void ixgbe_i2c_start(struct ixgbe_hw *hw) 2097190873Sjfv{ 2098280182Sjfv u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2099190873Sjfv 2100190873Sjfv DEBUGFUNC("ixgbe_i2c_start"); 2101190873Sjfv 2102280182Sjfv i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw); 2103280182Sjfv 2104190873Sjfv /* Start condition must begin with data and clock high */ 2105190873Sjfv ixgbe_set_i2c_data(hw, &i2cctl, 1); 2106190873Sjfv ixgbe_raise_i2c_clk(hw, &i2cctl); 2107190873Sjfv 2108190873Sjfv /* Setup time for start condition (4.7us) */ 2109190873Sjfv usec_delay(IXGBE_I2C_T_SU_STA); 2110190873Sjfv 2111190873Sjfv ixgbe_set_i2c_data(hw, &i2cctl, 0); 2112190873Sjfv 2113190873Sjfv /* Hold time for start condition (4us) */ 2114190873Sjfv usec_delay(IXGBE_I2C_T_HD_STA); 2115190873Sjfv 2116190873Sjfv ixgbe_lower_i2c_clk(hw, &i2cctl); 2117190873Sjfv 2118190873Sjfv /* Minimum low period of clock is 4.7 us */ 2119190873Sjfv usec_delay(IXGBE_I2C_T_LOW); 2120190873Sjfv 2121190873Sjfv} 2122190873Sjfv 2123190873Sjfv/** 2124190873Sjfv * ixgbe_i2c_stop - Sets I2C stop condition 2125190873Sjfv * @hw: pointer to hardware structure 2126190873Sjfv * 2127190873Sjfv * Sets I2C stop condition (Low -> High on SDA while SCL is High) 2128280182Sjfv * Disables bit-bang mode and negates data output enable on X550 2129280182Sjfv * hardware. 2130190873Sjfv **/ 2131190873Sjfvstatic void ixgbe_i2c_stop(struct ixgbe_hw *hw) 2132190873Sjfv{ 2133280182Sjfv u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2134280182Sjfv u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2135280182Sjfv u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2136280182Sjfv u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw); 2137190873Sjfv 2138190873Sjfv DEBUGFUNC("ixgbe_i2c_stop"); 2139190873Sjfv 2140190873Sjfv /* Stop condition must begin with data low and clock high */ 2141190873Sjfv ixgbe_set_i2c_data(hw, &i2cctl, 0); 2142190873Sjfv ixgbe_raise_i2c_clk(hw, &i2cctl); 2143190873Sjfv 2144190873Sjfv /* Setup time for stop condition (4us) */ 2145190873Sjfv usec_delay(IXGBE_I2C_T_SU_STO); 2146190873Sjfv 2147190873Sjfv ixgbe_set_i2c_data(hw, &i2cctl, 1); 2148190873Sjfv 2149190873Sjfv /* bus free time between stop and start (4.7us)*/ 2150190873Sjfv usec_delay(IXGBE_I2C_T_BUF); 2151280182Sjfv 2152280182Sjfv if (bb_en_bit || data_oe_bit || clk_oe_bit) { 2153280182Sjfv i2cctl &= ~bb_en_bit; 2154280182Sjfv i2cctl |= data_oe_bit | clk_oe_bit; 2155280182Sjfv IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2156280182Sjfv IXGBE_WRITE_FLUSH(hw); 2157280182Sjfv } 2158190873Sjfv} 2159190873Sjfv 2160190873Sjfv/** 2161190873Sjfv * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C 2162190873Sjfv * @hw: pointer to hardware structure 2163190873Sjfv * @data: data byte to clock in 2164190873Sjfv * 2165190873Sjfv * Clocks in one byte data via I2C data/clock 2166190873Sjfv **/ 2167190873Sjfvstatic s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data) 2168190873Sjfv{ 2169190873Sjfv s32 i; 2170190873Sjfv bool bit = 0; 2171190873Sjfv 2172190873Sjfv DEBUGFUNC("ixgbe_clock_in_i2c_byte"); 2173190873Sjfv 2174280182Sjfv *data = 0; 2175190873Sjfv for (i = 7; i >= 0; i--) { 2176230775Sjfv ixgbe_clock_in_i2c_bit(hw, &bit); 2177215911Sjfv *data |= bit << i; 2178190873Sjfv } 2179190873Sjfv 2180230775Sjfv return IXGBE_SUCCESS; 2181190873Sjfv} 2182190873Sjfv 2183190873Sjfv/** 2184190873Sjfv * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C 2185190873Sjfv * @hw: pointer to hardware structure 2186190873Sjfv * @data: data byte clocked out 2187190873Sjfv * 2188190873Sjfv * Clocks out one byte data via I2C data/clock 2189190873Sjfv **/ 2190190873Sjfvstatic s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data) 2191190873Sjfv{ 2192190873Sjfv s32 status = IXGBE_SUCCESS; 2193190873Sjfv s32 i; 2194190873Sjfv u32 i2cctl; 2195280182Sjfv bool bit; 2196190873Sjfv 2197190873Sjfv DEBUGFUNC("ixgbe_clock_out_i2c_byte"); 2198190873Sjfv 2199190873Sjfv for (i = 7; i >= 0; i--) { 2200190873Sjfv bit = (data >> i) & 0x1; 2201190873Sjfv status = ixgbe_clock_out_i2c_bit(hw, bit); 2202190873Sjfv 2203190873Sjfv if (status != IXGBE_SUCCESS) 2204190873Sjfv break; 2205190873Sjfv } 2206190873Sjfv 2207190873Sjfv /* Release SDA line (set high) */ 2208280182Sjfv i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2209280182Sjfv i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2210280182Sjfv i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2211280182Sjfv IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2212230775Sjfv IXGBE_WRITE_FLUSH(hw); 2213190873Sjfv 2214190873Sjfv return status; 2215190873Sjfv} 2216190873Sjfv 2217190873Sjfv/** 2218190873Sjfv * ixgbe_get_i2c_ack - Polls for I2C ACK 2219190873Sjfv * @hw: pointer to hardware structure 2220190873Sjfv * 2221190873Sjfv * Clocks in/out one bit via I2C data/clock 2222190873Sjfv **/ 2223190873Sjfvstatic s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw) 2224190873Sjfv{ 2225280182Sjfv u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2226230775Sjfv s32 status = IXGBE_SUCCESS; 2227190873Sjfv u32 i = 0; 2228280182Sjfv u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2229190873Sjfv u32 timeout = 10; 2230190873Sjfv bool ack = 1; 2231190873Sjfv 2232190873Sjfv DEBUGFUNC("ixgbe_get_i2c_ack"); 2233190873Sjfv 2234280182Sjfv if (data_oe_bit) { 2235280182Sjfv i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2236280182Sjfv i2cctl |= data_oe_bit; 2237280182Sjfv IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2238280182Sjfv IXGBE_WRITE_FLUSH(hw); 2239280182Sjfv } 2240230775Sjfv ixgbe_raise_i2c_clk(hw, &i2cctl); 2241190873Sjfv 2242190873Sjfv /* Minimum high period of clock is 4us */ 2243190873Sjfv usec_delay(IXGBE_I2C_T_HIGH); 2244190873Sjfv 2245190873Sjfv /* Poll for ACK. Note that ACK in I2C spec is 2246190873Sjfv * transition from 1 to 0 */ 2247190873Sjfv for (i = 0; i < timeout; i++) { 2248280182Sjfv i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2249280182Sjfv ack = ixgbe_get_i2c_data(hw, &i2cctl); 2250190873Sjfv 2251190873Sjfv usec_delay(1); 2252280182Sjfv if (!ack) 2253190873Sjfv break; 2254190873Sjfv } 2255190873Sjfv 2256280182Sjfv if (ack) { 2257280182Sjfv DEBUGOUT("I2C ack was not received.\n"); 2258190873Sjfv status = IXGBE_ERR_I2C; 2259190873Sjfv } 2260190873Sjfv 2261190873Sjfv ixgbe_lower_i2c_clk(hw, &i2cctl); 2262190873Sjfv 2263190873Sjfv /* Minimum low period of clock is 4.7 us */ 2264190873Sjfv usec_delay(IXGBE_I2C_T_LOW); 2265190873Sjfv 2266190873Sjfv return status; 2267190873Sjfv} 2268190873Sjfv 2269190873Sjfv/** 2270190873Sjfv * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 2271190873Sjfv * @hw: pointer to hardware structure 2272190873Sjfv * @data: read data value 2273190873Sjfv * 2274190873Sjfv * Clocks in one bit via I2C data/clock 2275190873Sjfv **/ 2276190873Sjfvstatic s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data) 2277190873Sjfv{ 2278280182Sjfv u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2279280182Sjfv u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2280190873Sjfv 2281200239Sjfv DEBUGFUNC("ixgbe_clock_in_i2c_bit"); 2282200239Sjfv 2283280182Sjfv if (data_oe_bit) { 2284280182Sjfv i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2285280182Sjfv i2cctl |= data_oe_bit; 2286280182Sjfv IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2287280182Sjfv IXGBE_WRITE_FLUSH(hw); 2288280182Sjfv } 2289230775Sjfv ixgbe_raise_i2c_clk(hw, &i2cctl); 2290190873Sjfv 2291190873Sjfv /* Minimum high period of clock is 4us */ 2292190873Sjfv usec_delay(IXGBE_I2C_T_HIGH); 2293190873Sjfv 2294280182Sjfv i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2295280182Sjfv *data = ixgbe_get_i2c_data(hw, &i2cctl); 2296190873Sjfv 2297190873Sjfv ixgbe_lower_i2c_clk(hw, &i2cctl); 2298190873Sjfv 2299190873Sjfv /* Minimum low period of clock is 4.7 us */ 2300190873Sjfv usec_delay(IXGBE_I2C_T_LOW); 2301190873Sjfv 2302230775Sjfv return IXGBE_SUCCESS; 2303190873Sjfv} 2304190873Sjfv 2305190873Sjfv/** 2306190873Sjfv * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 2307190873Sjfv * @hw: pointer to hardware structure 2308190873Sjfv * @data: data value to write 2309190873Sjfv * 2310190873Sjfv * Clocks out one bit via I2C data/clock 2311190873Sjfv **/ 2312190873Sjfvstatic s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data) 2313190873Sjfv{ 2314190873Sjfv s32 status; 2315280182Sjfv u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2316190873Sjfv 2317200239Sjfv DEBUGFUNC("ixgbe_clock_out_i2c_bit"); 2318200239Sjfv 2319190873Sjfv status = ixgbe_set_i2c_data(hw, &i2cctl, data); 2320190873Sjfv if (status == IXGBE_SUCCESS) { 2321230775Sjfv ixgbe_raise_i2c_clk(hw, &i2cctl); 2322190873Sjfv 2323190873Sjfv /* Minimum high period of clock is 4us */ 2324190873Sjfv usec_delay(IXGBE_I2C_T_HIGH); 2325190873Sjfv 2326190873Sjfv ixgbe_lower_i2c_clk(hw, &i2cctl); 2327190873Sjfv 2328190873Sjfv /* Minimum low period of clock is 4.7 us. 2329190873Sjfv * This also takes care of the data hold time. 2330190873Sjfv */ 2331190873Sjfv usec_delay(IXGBE_I2C_T_LOW); 2332190873Sjfv } else { 2333190873Sjfv status = IXGBE_ERR_I2C; 2334251964Sjfv ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2335251964Sjfv "I2C data was not set to %X\n", data); 2336190873Sjfv } 2337190873Sjfv 2338190873Sjfv return status; 2339190873Sjfv} 2340280182Sjfv 2341190873Sjfv/** 2342190873Sjfv * ixgbe_raise_i2c_clk - Raises the I2C SCL clock 2343190873Sjfv * @hw: pointer to hardware structure 2344190873Sjfv * @i2cctl: Current value of I2CCTL register 2345190873Sjfv * 2346190873Sjfv * Raises the I2C clock line '0'->'1' 2347280182Sjfv * Negates the I2C clock output enable on X550 hardware. 2348190873Sjfv **/ 2349230775Sjfvstatic void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2350190873Sjfv{ 2351280182Sjfv u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2352238149Sjfv u32 i = 0; 2353238149Sjfv u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT; 2354238149Sjfv u32 i2cctl_r = 0; 2355238149Sjfv 2356200239Sjfv DEBUGFUNC("ixgbe_raise_i2c_clk"); 2357200239Sjfv 2358280182Sjfv if (clk_oe_bit) { 2359280182Sjfv *i2cctl |= clk_oe_bit; 2360280182Sjfv IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2361280182Sjfv } 2362280182Sjfv 2363238149Sjfv for (i = 0; i < timeout; i++) { 2364280182Sjfv *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw); 2365190873Sjfv 2366280182Sjfv IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2367238149Sjfv IXGBE_WRITE_FLUSH(hw); 2368238149Sjfv /* SCL rise time (1000ns) */ 2369238149Sjfv usec_delay(IXGBE_I2C_T_RISE); 2370190873Sjfv 2371280182Sjfv i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2372280182Sjfv if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw)) 2373238149Sjfv break; 2374238149Sjfv } 2375190873Sjfv} 2376190873Sjfv 2377190873Sjfv/** 2378190873Sjfv * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock 2379190873Sjfv * @hw: pointer to hardware structure 2380190873Sjfv * @i2cctl: Current value of I2CCTL register 2381190873Sjfv * 2382190873Sjfv * Lowers the I2C clock line '1'->'0' 2383280182Sjfv * Asserts the I2C clock output enable on X550 hardware. 2384190873Sjfv **/ 2385190873Sjfvstatic void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2386190873Sjfv{ 2387200239Sjfv DEBUGFUNC("ixgbe_lower_i2c_clk"); 2388200239Sjfv 2389280182Sjfv *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw)); 2390280182Sjfv *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2391190873Sjfv 2392280182Sjfv IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2393230775Sjfv IXGBE_WRITE_FLUSH(hw); 2394190873Sjfv 2395190873Sjfv /* SCL fall time (300ns) */ 2396190873Sjfv usec_delay(IXGBE_I2C_T_FALL); 2397190873Sjfv} 2398190873Sjfv 2399190873Sjfv/** 2400190873Sjfv * ixgbe_set_i2c_data - Sets the I2C data bit 2401190873Sjfv * @hw: pointer to hardware structure 2402190873Sjfv * @i2cctl: Current value of I2CCTL register 2403190873Sjfv * @data: I2C data value (0 or 1) to set 2404190873Sjfv * 2405190873Sjfv * Sets the I2C data bit 2406280182Sjfv * Asserts the I2C data output enable on X550 hardware. 2407190873Sjfv **/ 2408190873Sjfvstatic s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data) 2409190873Sjfv{ 2410280182Sjfv u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2411190873Sjfv s32 status = IXGBE_SUCCESS; 2412190873Sjfv 2413200239Sjfv DEBUGFUNC("ixgbe_set_i2c_data"); 2414200239Sjfv 2415190873Sjfv if (data) 2416280182Sjfv *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2417190873Sjfv else 2418280182Sjfv *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw)); 2419280182Sjfv *i2cctl &= ~data_oe_bit; 2420190873Sjfv 2421280182Sjfv IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2422230775Sjfv IXGBE_WRITE_FLUSH(hw); 2423190873Sjfv 2424190873Sjfv /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 2425190873Sjfv usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); 2426190873Sjfv 2427280182Sjfv if (!data) /* Can't verify data in this case */ 2428280182Sjfv return IXGBE_SUCCESS; 2429280182Sjfv if (data_oe_bit) { 2430280182Sjfv *i2cctl |= data_oe_bit; 2431280182Sjfv IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2432280182Sjfv IXGBE_WRITE_FLUSH(hw); 2433280182Sjfv } 2434280182Sjfv 2435190873Sjfv /* Verify data was set correctly */ 2436280182Sjfv *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2437280182Sjfv if (data != ixgbe_get_i2c_data(hw, i2cctl)) { 2438190873Sjfv status = IXGBE_ERR_I2C; 2439251964Sjfv ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2440251964Sjfv "Error - I2C data was not set to %X.\n", 2441251964Sjfv data); 2442190873Sjfv } 2443190873Sjfv 2444190873Sjfv return status; 2445190873Sjfv} 2446190873Sjfv 2447190873Sjfv/** 2448190873Sjfv * ixgbe_get_i2c_data - Reads the I2C SDA data bit 2449190873Sjfv * @hw: pointer to hardware structure 2450190873Sjfv * @i2cctl: Current value of I2CCTL register 2451190873Sjfv * 2452190873Sjfv * Returns the I2C data bit value 2453280182Sjfv * Negates the I2C data output enable on X550 hardware. 2454190873Sjfv **/ 2455280182Sjfvstatic bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl) 2456190873Sjfv{ 2457280182Sjfv u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2458190873Sjfv bool data; 2459190873Sjfv 2460200239Sjfv DEBUGFUNC("ixgbe_get_i2c_data"); 2461200239Sjfv 2462280182Sjfv if (data_oe_bit) { 2463280182Sjfv *i2cctl |= data_oe_bit; 2464280182Sjfv IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2465280182Sjfv IXGBE_WRITE_FLUSH(hw); 2466280182Sjfv usec_delay(IXGBE_I2C_T_FALL); 2467280182Sjfv } 2468280182Sjfv 2469280182Sjfv if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw)) 2470190873Sjfv data = 1; 2471190873Sjfv else 2472190873Sjfv data = 0; 2473190873Sjfv 2474190873Sjfv return data; 2475190873Sjfv} 2476190873Sjfv 2477190873Sjfv/** 2478190873Sjfv * ixgbe_i2c_bus_clear - Clears the I2C bus 2479190873Sjfv * @hw: pointer to hardware structure 2480190873Sjfv * 2481190873Sjfv * Clears the I2C bus by sending nine clock pulses. 2482190873Sjfv * Used when data line is stuck low. 2483190873Sjfv **/ 2484190873Sjfvvoid ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) 2485190873Sjfv{ 2486280182Sjfv u32 i2cctl; 2487190873Sjfv u32 i; 2488190873Sjfv 2489190873Sjfv DEBUGFUNC("ixgbe_i2c_bus_clear"); 2490190873Sjfv 2491190873Sjfv ixgbe_i2c_start(hw); 2492280182Sjfv i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2493190873Sjfv 2494190873Sjfv ixgbe_set_i2c_data(hw, &i2cctl, 1); 2495190873Sjfv 2496190873Sjfv for (i = 0; i < 9; i++) { 2497190873Sjfv ixgbe_raise_i2c_clk(hw, &i2cctl); 2498190873Sjfv 2499190873Sjfv /* Min high period of clock is 4us */ 2500190873Sjfv usec_delay(IXGBE_I2C_T_HIGH); 2501190873Sjfv 2502190873Sjfv ixgbe_lower_i2c_clk(hw, &i2cctl); 2503190873Sjfv 2504190873Sjfv /* Min low period of clock is 4.7us*/ 2505190873Sjfv usec_delay(IXGBE_I2C_T_LOW); 2506190873Sjfv } 2507190873Sjfv 2508190873Sjfv ixgbe_i2c_start(hw); 2509190873Sjfv 2510190873Sjfv /* Put the i2c bus back to default state */ 2511190873Sjfv ixgbe_i2c_stop(hw); 2512190873Sjfv} 2513205720Sjfv 2514205720Sjfv/** 2515238149Sjfv * ixgbe_tn_check_overtemp - Checks if an overtemp occurred. 2516205720Sjfv * @hw: pointer to hardware structure 2517205720Sjfv * 2518205720Sjfv * Checks if the LASI temp alarm status was triggered due to overtemp 2519205720Sjfv **/ 2520205720Sjfvs32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw) 2521205720Sjfv{ 2522205720Sjfv s32 status = IXGBE_SUCCESS; 2523205720Sjfv u16 phy_data = 0; 2524205720Sjfv 2525205720Sjfv DEBUGFUNC("ixgbe_tn_check_overtemp"); 2526205720Sjfv 2527205720Sjfv if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM) 2528205720Sjfv goto out; 2529205720Sjfv 2530205720Sjfv /* Check that the LASI temp alarm status was triggered */ 2531205720Sjfv hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG, 2532205720Sjfv IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data); 2533205720Sjfv 2534205720Sjfv if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM)) 2535205720Sjfv goto out; 2536205720Sjfv 2537205720Sjfv status = IXGBE_ERR_OVERTEMP; 2538251964Sjfv ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature"); 2539205720Sjfvout: 2540205720Sjfv return status; 2541205720Sjfv} 2542280182Sjfv 2543280182Sjfv/** 2544280182Sjfv * ixgbe_set_copper_phy_power - Control power for copper phy 2545280182Sjfv * @hw: pointer to hardware structure 2546280182Sjfv * @on: TRUE for on, FALSE for off 2547280182Sjfv */ 2548280182Sjfvs32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on) 2549280182Sjfv{ 2550280182Sjfv u32 status; 2551280182Sjfv u16 reg; 2552280182Sjfv 2553280182Sjfv status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2554280182Sjfv IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2555280182Sjfv ®); 2556280182Sjfv if (status) 2557280182Sjfv return status; 2558280182Sjfv 2559280182Sjfv if (on) { 2560280182Sjfv reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2561280182Sjfv } else { 2562280182Sjfv if (ixgbe_check_reset_blocked(hw)) 2563280182Sjfv return 0; 2564280182Sjfv reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2565280182Sjfv } 2566280182Sjfv 2567280182Sjfv status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2568280182Sjfv IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2569280182Sjfv reg); 2570280182Sjfv return status; 2571280182Sjfv} 2572