1/****************************************************************************** 2 3 Copyright (c) 2001-2017, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: stable/11/sys/dev/ixgbe/ixgbe_phy.c 320897 2017-07-11 21:25:07Z erj $*/ 34 35#include "ixgbe_api.h" 36#include "ixgbe_common.h" 37#include "ixgbe_phy.h" 38 39static void ixgbe_i2c_start(struct ixgbe_hw *hw); 40static void ixgbe_i2c_stop(struct ixgbe_hw *hw); 41static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data); 42static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data); 43static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw); 44static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data); 45static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data); 46static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 47static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 48static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data); 49static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl); 50static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 51 u8 *sff8472_data); 52 53/** 54 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack 55 * @hw: pointer to the hardware structure 56 * @byte: byte to send 57 * 58 * Returns an error code on error. 59 */ 60static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte) 61{ 62 s32 status; 63 64 status = ixgbe_clock_out_i2c_byte(hw, byte); 65 if (status) 66 return status; 67 return ixgbe_get_i2c_ack(hw); 68} 69 70/** 71 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack 72 * @hw: pointer to the hardware structure 73 * @byte: pointer to a u8 to receive the byte 74 * 75 * Returns an error code on error. 76 */ 77static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte) 78{ 79 s32 status; 80 81 status = ixgbe_clock_in_i2c_byte(hw, byte); 82 if (status) 83 return status; 84 /* ACK */ 85 return ixgbe_clock_out_i2c_bit(hw, FALSE); 86} 87 88/** 89 * ixgbe_ones_comp_byte_add - Perform one's complement addition 90 * @add1 - addend 1 91 * @add2 - addend 2 92 * 93 * Returns one's complement 8-bit sum. 94 */ 95static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2) 96{ 97 u16 sum = add1 + add2; 98 99 sum = (sum & 0xFF) + (sum >> 8); 100 return sum & 0xFF; 101} 102 103/** 104 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation 105 * @hw: pointer to the hardware structure 106 * @addr: I2C bus address to read from 107 * @reg: I2C device register to read from 108 * @val: pointer to location to receive read value 109 * @lock: TRUE if to take and release semaphore 110 * 111 * Returns an error code on error. 112 */ 113s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg, 114 u16 *val, bool lock) 115{ 116 u32 swfw_mask = hw->phy.phy_semaphore_mask; 117 int max_retry = 3; 118 int retry = 0; 119 u8 csum_byte; 120 u8 high_bits; 121 u8 low_bits; 122 u8 reg_high; 123 u8 csum; 124 125 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */ 126 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 127 csum = ~csum; 128 do { 129 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 130 return IXGBE_ERR_SWFW_SYNC; 131 ixgbe_i2c_start(hw); 132 /* Device Address and write indication */ 133 if (ixgbe_out_i2c_byte_ack(hw, addr)) 134 goto fail; 135 /* Write bits 14:8 */ 136 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 137 goto fail; 138 /* Write bits 7:0 */ 139 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 140 goto fail; 141 /* Write csum */ 142 if (ixgbe_out_i2c_byte_ack(hw, csum)) 143 goto fail; 144 /* Re-start condition */ 145 ixgbe_i2c_start(hw); 146 /* Device Address and read indication */ 147 if (ixgbe_out_i2c_byte_ack(hw, addr | 1)) 148 goto fail; 149 /* Get upper bits */ 150 if (ixgbe_in_i2c_byte_ack(hw, &high_bits)) 151 goto fail; 152 /* Get low bits */ 153 if (ixgbe_in_i2c_byte_ack(hw, &low_bits)) 154 goto fail; 155 /* Get csum */ 156 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte)) 157 goto fail; 158 /* NACK */ 159 if (ixgbe_clock_out_i2c_bit(hw, FALSE)) 160 goto fail; 161 ixgbe_i2c_stop(hw); 162 if (lock) 163 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 164 *val = (high_bits << 8) | low_bits; 165 return 0; 166 167fail: 168 ixgbe_i2c_bus_clear(hw); 169 if (lock) 170 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 171 retry++; 172 if (retry < max_retry) 173 DEBUGOUT("I2C byte read combined error - Retrying.\n"); 174 else 175 DEBUGOUT("I2C byte read combined error.\n"); 176 } while (retry < max_retry); 177 178 return IXGBE_ERR_I2C; 179} 180 181/** 182 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation 183 * @hw: pointer to the hardware structure 184 * @addr: I2C bus address to write to 185 * @reg: I2C device register to write to 186 * @val: value to write 187 * @lock: TRUE if to take and release semaphore 188 * 189 * Returns an error code on error. 190 */ 191s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg, 192 u16 val, bool lock) 193{ 194 u32 swfw_mask = hw->phy.phy_semaphore_mask; 195 int max_retry = 1; 196 int retry = 0; 197 u8 reg_high; 198 u8 csum; 199 200 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */ 201 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 202 csum = ixgbe_ones_comp_byte_add(csum, val >> 8); 203 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF); 204 csum = ~csum; 205 do { 206 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 207 return IXGBE_ERR_SWFW_SYNC; 208 ixgbe_i2c_start(hw); 209 /* Device Address and write indication */ 210 if (ixgbe_out_i2c_byte_ack(hw, addr)) 211 goto fail; 212 /* Write bits 14:8 */ 213 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 214 goto fail; 215 /* Write bits 7:0 */ 216 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 217 goto fail; 218 /* Write data 15:8 */ 219 if (ixgbe_out_i2c_byte_ack(hw, val >> 8)) 220 goto fail; 221 /* Write data 7:0 */ 222 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF)) 223 goto fail; 224 /* Write csum */ 225 if (ixgbe_out_i2c_byte_ack(hw, csum)) 226 goto fail; 227 ixgbe_i2c_stop(hw); 228 if (lock) 229 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 230 return 0; 231 232fail: 233 ixgbe_i2c_bus_clear(hw); 234 if (lock) 235 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 236 retry++; 237 if (retry < max_retry) 238 DEBUGOUT("I2C byte write combined error - Retrying.\n"); 239 else 240 DEBUGOUT("I2C byte write combined error.\n"); 241 } while (retry < max_retry); 242 243 return IXGBE_ERR_I2C; 244} 245 246/** 247 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs 248 * @hw: pointer to the hardware structure 249 * 250 * Initialize the function pointers. 251 **/ 252s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw) 253{ 254 struct ixgbe_phy_info *phy = &hw->phy; 255 256 DEBUGFUNC("ixgbe_init_phy_ops_generic"); 257 258 /* PHY */ 259 phy->ops.identify = ixgbe_identify_phy_generic; 260 phy->ops.reset = ixgbe_reset_phy_generic; 261 phy->ops.read_reg = ixgbe_read_phy_reg_generic; 262 phy->ops.write_reg = ixgbe_write_phy_reg_generic; 263 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi; 264 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi; 265 phy->ops.setup_link = ixgbe_setup_phy_link_generic; 266 phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic; 267 phy->ops.check_link = NULL; 268 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic; 269 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic; 270 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic; 271 phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic; 272 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic; 273 phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic; 274 phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear; 275 phy->ops.identify_sfp = ixgbe_identify_module_generic; 276 phy->sfp_type = ixgbe_sfp_type_unknown; 277 phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked; 278 phy->ops.write_i2c_byte_unlocked = 279 ixgbe_write_i2c_byte_generic_unlocked; 280 phy->ops.check_overtemp = ixgbe_tn_check_overtemp; 281 return IXGBE_SUCCESS; 282} 283 284/** 285 * ixgbe_probe_phy - Probe a single address for a PHY 286 * @hw: pointer to hardware structure 287 * @phy_addr: PHY address to probe 288 * 289 * Returns TRUE if PHY found 290 */ 291static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr) 292{ 293 u16 ext_ability = 0; 294 295 if (!ixgbe_validate_phy_addr(hw, phy_addr)) { 296 DEBUGOUT1("Unable to validate PHY address 0x%04X\n", 297 phy_addr); 298 return FALSE; 299 } 300 301 if (ixgbe_get_phy_id(hw)) 302 return FALSE; 303 304 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id); 305 306 if (hw->phy.type == ixgbe_phy_unknown) { 307 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 308 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 309 if (ext_ability & 310 (IXGBE_MDIO_PHY_10GBASET_ABILITY | 311 IXGBE_MDIO_PHY_1000BASET_ABILITY)) 312 hw->phy.type = ixgbe_phy_cu_unknown; 313 else 314 hw->phy.type = ixgbe_phy_generic; 315 } 316 317 return TRUE; 318} 319 320/** 321 * ixgbe_identify_phy_generic - Get physical layer module 322 * @hw: pointer to hardware structure 323 * 324 * Determines the physical layer module found on the current adapter. 325 **/ 326s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) 327{ 328 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 329 u16 phy_addr; 330 331 DEBUGFUNC("ixgbe_identify_phy_generic"); 332 333 if (!hw->phy.phy_semaphore_mask) { 334 if (hw->bus.lan_id) 335 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 336 else 337 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 338 } 339 340 if (hw->phy.type != ixgbe_phy_unknown) 341 return IXGBE_SUCCESS; 342 343 if (hw->phy.nw_mng_if_sel) { 344 phy_addr = (hw->phy.nw_mng_if_sel & 345 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >> 346 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT; 347 if (ixgbe_probe_phy(hw, phy_addr)) 348 return IXGBE_SUCCESS; 349 else 350 return IXGBE_ERR_PHY_ADDR_INVALID; 351 } 352 353 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { 354 if (ixgbe_probe_phy(hw, phy_addr)) { 355 status = IXGBE_SUCCESS; 356 break; 357 } 358 } 359 360 /* Certain media types do not have a phy so an address will not 361 * be found and the code will take this path. Caller has to 362 * decide if it is an error or not. 363 */ 364 if (status != IXGBE_SUCCESS) 365 hw->phy.addr = 0; 366 367 return status; 368} 369 370/** 371 * ixgbe_check_reset_blocked - check status of MNG FW veto bit 372 * @hw: pointer to the hardware structure 373 * 374 * This function checks the MMNGC.MNG_VETO bit to see if there are 375 * any constraints on link from manageability. For MAC's that don't 376 * have this bit just return faluse since the link can not be blocked 377 * via this method. 378 **/ 379s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw) 380{ 381 u32 mmngc; 382 383 DEBUGFUNC("ixgbe_check_reset_blocked"); 384 385 /* If we don't have this bit, it can't be blocking */ 386 if (hw->mac.type == ixgbe_mac_82598EB) 387 return FALSE; 388 389 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC); 390 if (mmngc & IXGBE_MMNGC_MNG_VETO) { 391 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, 392 "MNG_VETO bit detected.\n"); 393 return TRUE; 394 } 395 396 return FALSE; 397} 398 399/** 400 * ixgbe_validate_phy_addr - Determines phy address is valid 401 * @hw: pointer to hardware structure 402 * 403 **/ 404bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr) 405{ 406 u16 phy_id = 0; 407 bool valid = FALSE; 408 409 DEBUGFUNC("ixgbe_validate_phy_addr"); 410 411 hw->phy.addr = phy_addr; 412 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 413 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id); 414 415 if (phy_id != 0xFFFF && phy_id != 0x0) 416 valid = TRUE; 417 418 DEBUGOUT1("PHY ID HIGH is 0x%04X\n", phy_id); 419 420 return valid; 421} 422 423/** 424 * ixgbe_get_phy_id - Get the phy type 425 * @hw: pointer to hardware structure 426 * 427 **/ 428s32 ixgbe_get_phy_id(struct ixgbe_hw *hw) 429{ 430 u32 status; 431 u16 phy_id_high = 0; 432 u16 phy_id_low = 0; 433 434 DEBUGFUNC("ixgbe_get_phy_id"); 435 436 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 437 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 438 &phy_id_high); 439 440 if (status == IXGBE_SUCCESS) { 441 hw->phy.id = (u32)(phy_id_high << 16); 442 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW, 443 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 444 &phy_id_low); 445 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); 446 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); 447 } 448 DEBUGOUT2("PHY_ID_HIGH 0x%04X, PHY_ID_LOW 0x%04X\n", 449 phy_id_high, phy_id_low); 450 451 return status; 452} 453 454/** 455 * ixgbe_get_phy_type_from_id - Get the phy type 456 * @phy_id: PHY ID information 457 * 458 **/ 459enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) 460{ 461 enum ixgbe_phy_type phy_type; 462 463 DEBUGFUNC("ixgbe_get_phy_type_from_id"); 464 465 switch (phy_id) { 466 case TN1010_PHY_ID: 467 phy_type = ixgbe_phy_tn; 468 break; 469 case X550_PHY_ID2: 470 case X550_PHY_ID3: 471 case X540_PHY_ID: 472 phy_type = ixgbe_phy_aq; 473 break; 474 case QT2022_PHY_ID: 475 phy_type = ixgbe_phy_qt; 476 break; 477 case ATH_PHY_ID: 478 phy_type = ixgbe_phy_nl; 479 break; 480 case X557_PHY_ID: 481 case X557_PHY_ID2: 482 phy_type = ixgbe_phy_x550em_ext_t; 483 break; 484 case IXGBE_M88E1500_E_PHY_ID: 485 case IXGBE_M88E1543_E_PHY_ID: 486 phy_type = ixgbe_phy_ext_1g_t; 487 break; 488 default: 489 phy_type = ixgbe_phy_unknown; 490 break; 491 } 492 return phy_type; 493} 494 495/** 496 * ixgbe_reset_phy_generic - Performs a PHY reset 497 * @hw: pointer to hardware structure 498 **/ 499s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 500{ 501 u32 i; 502 u16 ctrl = 0; 503 s32 status = IXGBE_SUCCESS; 504 505 DEBUGFUNC("ixgbe_reset_phy_generic"); 506 507 if (hw->phy.type == ixgbe_phy_unknown) 508 status = ixgbe_identify_phy_generic(hw); 509 510 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none) 511 goto out; 512 513 /* Don't reset PHY if it's shut down due to overtemp. */ 514 if (!hw->phy.reset_if_overtemp && 515 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw))) 516 goto out; 517 518 /* Blocked by MNG FW so bail */ 519 if (ixgbe_check_reset_blocked(hw)) 520 goto out; 521 522 /* 523 * Perform soft PHY reset to the PHY_XS. 524 * This will cause a soft reset to the PHY 525 */ 526 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 527 IXGBE_MDIO_PHY_XS_DEV_TYPE, 528 IXGBE_MDIO_PHY_XS_RESET); 529 530 /* 531 * Poll for reset bit to self-clear indicating reset is complete. 532 * Some PHYs could take up to 3 seconds to complete and need about 533 * 1.7 usec delay after the reset is complete. 534 */ 535 for (i = 0; i < 30; i++) { 536 msec_delay(100); 537 if (hw->phy.type == ixgbe_phy_x550em_ext_t) { 538 status = hw->phy.ops.read_reg(hw, 539 IXGBE_MDIO_TX_VENDOR_ALARMS_3, 540 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 541 &ctrl); 542 if (status != IXGBE_SUCCESS) 543 return status; 544 545 if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) { 546 usec_delay(2); 547 break; 548 } 549 } else { 550 status = hw->phy.ops.read_reg(hw, 551 IXGBE_MDIO_PHY_XS_CONTROL, 552 IXGBE_MDIO_PHY_XS_DEV_TYPE, 553 &ctrl); 554 if (status != IXGBE_SUCCESS) 555 return status; 556 557 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) { 558 usec_delay(2); 559 break; 560 } 561 } 562 } 563 564 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) { 565 status = IXGBE_ERR_RESET_FAILED; 566 ERROR_REPORT1(IXGBE_ERROR_POLLING, 567 "PHY reset polling failed to complete.\n"); 568 } 569 570out: 571 return status; 572} 573 574/** 575 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without 576 * the SWFW lock 577 * @hw: pointer to hardware structure 578 * @reg_addr: 32 bit address of PHY register to read 579 * @phy_data: Pointer to read data from PHY register 580 **/ 581s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 582 u16 *phy_data) 583{ 584 u32 i, data, command; 585 586 /* Setup and write the address cycle command */ 587 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 588 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 589 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 590 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 591 592 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 593 594 /* 595 * Check every 10 usec to see if the address cycle completed. 596 * The MDI Command bit will clear when the operation is 597 * complete 598 */ 599 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 600 usec_delay(10); 601 602 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 603 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 604 break; 605 } 606 607 608 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 609 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n"); 610 DEBUGOUT("PHY address command did not complete, returning IXGBE_ERR_PHY\n"); 611 return IXGBE_ERR_PHY; 612 } 613 614 /* 615 * Address cycle complete, setup and write the read 616 * command 617 */ 618 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 619 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 620 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 621 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); 622 623 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 624 625 /* 626 * Check every 10 usec to see if the address cycle 627 * completed. The MDI Command bit will clear when the 628 * operation is complete 629 */ 630 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 631 usec_delay(10); 632 633 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 634 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 635 break; 636 } 637 638 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 639 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n"); 640 DEBUGOUT("PHY read command didn't complete, returning IXGBE_ERR_PHY\n"); 641 return IXGBE_ERR_PHY; 642 } 643 644 /* 645 * Read operation is complete. Get the data 646 * from MSRWD 647 */ 648 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 649 data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 650 *phy_data = (u16)(data); 651 652 return IXGBE_SUCCESS; 653} 654 655/** 656 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register 657 * using the SWFW lock - this function is needed in most cases 658 * @hw: pointer to hardware structure 659 * @reg_addr: 32 bit address of PHY register to read 660 * @phy_data: Pointer to read data from PHY register 661 **/ 662s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 663 u32 device_type, u16 *phy_data) 664{ 665 s32 status; 666 u32 gssr = hw->phy.phy_semaphore_mask; 667 668 DEBUGFUNC("ixgbe_read_phy_reg_generic"); 669 670 if (hw->mac.ops.acquire_swfw_sync(hw, gssr)) 671 return IXGBE_ERR_SWFW_SYNC; 672 673 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data); 674 675 hw->mac.ops.release_swfw_sync(hw, gssr); 676 677 return status; 678} 679 680/** 681 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register 682 * without SWFW lock 683 * @hw: pointer to hardware structure 684 * @reg_addr: 32 bit PHY register to write 685 * @device_type: 5 bit device type 686 * @phy_data: Data to write to the PHY register 687 **/ 688s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, 689 u32 device_type, u16 phy_data) 690{ 691 u32 i, command; 692 693 /* Put the data in the MDI single read and write data register*/ 694 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); 695 696 /* Setup and write the address cycle command */ 697 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 698 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 699 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 700 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 701 702 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 703 704 /* 705 * Check every 10 usec to see if the address cycle completed. 706 * The MDI Command bit will clear when the operation is 707 * complete 708 */ 709 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 710 usec_delay(10); 711 712 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 713 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 714 break; 715 } 716 717 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 718 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n"); 719 return IXGBE_ERR_PHY; 720 } 721 722 /* 723 * Address cycle complete, setup and write the write 724 * command 725 */ 726 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 727 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 728 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 729 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); 730 731 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 732 733 /* 734 * Check every 10 usec to see if the address cycle 735 * completed. The MDI Command bit will clear when the 736 * operation is complete 737 */ 738 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 739 usec_delay(10); 740 741 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 742 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 743 break; 744 } 745 746 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 747 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n"); 748 return IXGBE_ERR_PHY; 749 } 750 751 return IXGBE_SUCCESS; 752} 753 754/** 755 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register 756 * using SWFW lock- this function is needed in most cases 757 * @hw: pointer to hardware structure 758 * @reg_addr: 32 bit PHY register to write 759 * @device_type: 5 bit device type 760 * @phy_data: Data to write to the PHY register 761 **/ 762s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 763 u32 device_type, u16 phy_data) 764{ 765 s32 status; 766 u32 gssr = hw->phy.phy_semaphore_mask; 767 768 DEBUGFUNC("ixgbe_write_phy_reg_generic"); 769 770 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) { 771 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type, 772 phy_data); 773 hw->mac.ops.release_swfw_sync(hw, gssr); 774 } else { 775 status = IXGBE_ERR_SWFW_SYNC; 776 } 777 778 return status; 779} 780 781/** 782 * ixgbe_setup_phy_link_generic - Set and restart auto-neg 783 * @hw: pointer to hardware structure 784 * 785 * Restart auto-negotiation and PHY and waits for completion. 786 **/ 787s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 788{ 789 s32 status = IXGBE_SUCCESS; 790 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 791 bool autoneg = FALSE; 792 ixgbe_link_speed speed; 793 794 DEBUGFUNC("ixgbe_setup_phy_link_generic"); 795 796 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 797 798 /* Set or unset auto-negotiation 10G advertisement */ 799 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 800 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 801 &autoneg_reg); 802 803 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 804 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) && 805 (speed & IXGBE_LINK_SPEED_10GB_FULL)) 806 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 807 808 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 809 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 810 autoneg_reg); 811 812 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 813 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 814 &autoneg_reg); 815 816 if (hw->mac.type == ixgbe_mac_X550) { 817 /* Set or unset auto-negotiation 5G advertisement */ 818 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE; 819 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) && 820 (speed & IXGBE_LINK_SPEED_5GB_FULL)) 821 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE; 822 823 /* Set or unset auto-negotiation 2.5G advertisement */ 824 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE; 825 if ((hw->phy.autoneg_advertised & 826 IXGBE_LINK_SPEED_2_5GB_FULL) && 827 (speed & IXGBE_LINK_SPEED_2_5GB_FULL)) 828 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE; 829 } 830 831 /* Set or unset auto-negotiation 1G advertisement */ 832 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE; 833 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) && 834 (speed & IXGBE_LINK_SPEED_1GB_FULL)) 835 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE; 836 837 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 838 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 839 autoneg_reg); 840 841 /* Set or unset auto-negotiation 100M advertisement */ 842 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 843 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 844 &autoneg_reg); 845 846 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE | 847 IXGBE_MII_100BASE_T_ADVERTISE_HALF); 848 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) && 849 (speed & IXGBE_LINK_SPEED_100_FULL)) 850 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 851 852 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 853 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 854 autoneg_reg); 855 856 /* Blocked by MNG FW so don't reset PHY */ 857 if (ixgbe_check_reset_blocked(hw)) 858 return status; 859 860 /* Restart PHY auto-negotiation. */ 861 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 862 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 863 864 autoneg_reg |= IXGBE_MII_RESTART; 865 866 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 867 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 868 869 return status; 870} 871 872/** 873 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities 874 * @hw: pointer to hardware structure 875 * @speed: new link speed 876 **/ 877s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 878 ixgbe_link_speed speed, 879 bool autoneg_wait_to_complete) 880{ 881 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete); 882 883 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic"); 884 885 /* 886 * Clear autoneg_advertised and set new values based on input link 887 * speed. 888 */ 889 hw->phy.autoneg_advertised = 0; 890 891 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 892 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 893 894 if (speed & IXGBE_LINK_SPEED_5GB_FULL) 895 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL; 896 897 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) 898 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL; 899 900 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 901 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 902 903 if (speed & IXGBE_LINK_SPEED_100_FULL) 904 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 905 906 if (speed & IXGBE_LINK_SPEED_10_FULL) 907 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL; 908 909 /* Setup link based on the new speed settings */ 910 ixgbe_setup_phy_link(hw); 911 912 return IXGBE_SUCCESS; 913} 914 915/** 916 * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy 917 * @hw: pointer to hardware structure 918 * 919 * Determines the supported link capabilities by reading the PHY auto 920 * negotiation register. 921 **/ 922static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw) 923{ 924 s32 status; 925 u16 speed_ability; 926 927 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY, 928 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 929 &speed_ability); 930 if (status) 931 return status; 932 933 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G) 934 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL; 935 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G) 936 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL; 937 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M) 938 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL; 939 940 switch (hw->mac.type) { 941 case ixgbe_mac_X550: 942 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL; 943 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL; 944 break; 945 case ixgbe_mac_X550EM_x: 946 case ixgbe_mac_X550EM_a: 947 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL; 948 break; 949 default: 950 break; 951 } 952 953 return status; 954} 955 956/** 957 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities 958 * @hw: pointer to hardware structure 959 * @speed: pointer to link speed 960 * @autoneg: boolean auto-negotiation value 961 **/ 962s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 963 ixgbe_link_speed *speed, 964 bool *autoneg) 965{ 966 s32 status = IXGBE_SUCCESS; 967 968 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic"); 969 970 *autoneg = TRUE; 971 if (!hw->phy.speeds_supported) 972 status = ixgbe_get_copper_speeds_supported(hw); 973 974 *speed = hw->phy.speeds_supported; 975 return status; 976} 977 978/** 979 * ixgbe_check_phy_link_tnx - Determine link and speed status 980 * @hw: pointer to hardware structure 981 * 982 * Reads the VS1 register to determine if link is up and the current speed for 983 * the PHY. 984 **/ 985s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 986 bool *link_up) 987{ 988 s32 status = IXGBE_SUCCESS; 989 u32 time_out; 990 u32 max_time_out = 10; 991 u16 phy_link = 0; 992 u16 phy_speed = 0; 993 u16 phy_data = 0; 994 995 DEBUGFUNC("ixgbe_check_phy_link_tnx"); 996 997 /* Initialize speed and link to default case */ 998 *link_up = FALSE; 999 *speed = IXGBE_LINK_SPEED_10GB_FULL; 1000 1001 /* 1002 * Check current speed and link status of the PHY register. 1003 * This is a vendor specific register and may have to 1004 * be changed for other copper PHYs. 1005 */ 1006 for (time_out = 0; time_out < max_time_out; time_out++) { 1007 usec_delay(10); 1008 status = hw->phy.ops.read_reg(hw, 1009 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS, 1010 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1011 &phy_data); 1012 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; 1013 phy_speed = phy_data & 1014 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; 1015 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { 1016 *link_up = TRUE; 1017 if (phy_speed == 1018 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) 1019 *speed = IXGBE_LINK_SPEED_1GB_FULL; 1020 break; 1021 } 1022 } 1023 1024 return status; 1025} 1026 1027/** 1028 * ixgbe_setup_phy_link_tnx - Set and restart auto-neg 1029 * @hw: pointer to hardware structure 1030 * 1031 * Restart auto-negotiation and PHY and waits for completion. 1032 **/ 1033s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) 1034{ 1035 s32 status = IXGBE_SUCCESS; 1036 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 1037 bool autoneg = FALSE; 1038 ixgbe_link_speed speed; 1039 1040 DEBUGFUNC("ixgbe_setup_phy_link_tnx"); 1041 1042 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 1043 1044 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 1045 /* Set or unset auto-negotiation 10G advertisement */ 1046 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 1047 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1048 &autoneg_reg); 1049 1050 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 1051 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 1052 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 1053 1054 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 1055 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1056 autoneg_reg); 1057 } 1058 1059 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 1060 /* Set or unset auto-negotiation 1G advertisement */ 1061 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1062 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1063 &autoneg_reg); 1064 1065 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1066 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 1067 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1068 1069 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1070 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1071 autoneg_reg); 1072 } 1073 1074 if (speed & IXGBE_LINK_SPEED_100_FULL) { 1075 /* Set or unset auto-negotiation 100M advertisement */ 1076 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 1077 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1078 &autoneg_reg); 1079 1080 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE; 1081 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 1082 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 1083 1084 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 1085 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1086 autoneg_reg); 1087 } 1088 1089 /* Blocked by MNG FW so don't reset PHY */ 1090 if (ixgbe_check_reset_blocked(hw)) 1091 return status; 1092 1093 /* Restart PHY auto-negotiation. */ 1094 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 1095 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 1096 1097 autoneg_reg |= IXGBE_MII_RESTART; 1098 1099 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 1100 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 1101 1102 return status; 1103} 1104 1105/** 1106 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version 1107 * @hw: pointer to hardware structure 1108 * @firmware_version: pointer to the PHY Firmware Version 1109 **/ 1110s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, 1111 u16 *firmware_version) 1112{ 1113 s32 status; 1114 1115 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx"); 1116 1117 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, 1118 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1119 firmware_version); 1120 1121 return status; 1122} 1123 1124/** 1125 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version 1126 * @hw: pointer to hardware structure 1127 * @firmware_version: pointer to the PHY Firmware Version 1128 **/ 1129s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, 1130 u16 *firmware_version) 1131{ 1132 s32 status; 1133 1134 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic"); 1135 1136 status = hw->phy.ops.read_reg(hw, AQ_FW_REV, 1137 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1138 firmware_version); 1139 1140 return status; 1141} 1142 1143/** 1144 * ixgbe_reset_phy_nl - Performs a PHY reset 1145 * @hw: pointer to hardware structure 1146 **/ 1147s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) 1148{ 1149 u16 phy_offset, control, eword, edata, block_crc; 1150 bool end_data = FALSE; 1151 u16 list_offset, data_offset; 1152 u16 phy_data = 0; 1153 s32 ret_val = IXGBE_SUCCESS; 1154 u32 i; 1155 1156 DEBUGFUNC("ixgbe_reset_phy_nl"); 1157 1158 /* Blocked by MNG FW so bail */ 1159 if (ixgbe_check_reset_blocked(hw)) 1160 goto out; 1161 1162 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1163 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 1164 1165 /* reset the PHY and poll for completion */ 1166 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1167 IXGBE_MDIO_PHY_XS_DEV_TYPE, 1168 (phy_data | IXGBE_MDIO_PHY_XS_RESET)); 1169 1170 for (i = 0; i < 100; i++) { 1171 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1172 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 1173 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0) 1174 break; 1175 msec_delay(10); 1176 } 1177 1178 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) { 1179 DEBUGOUT("PHY reset did not complete.\n"); 1180 ret_val = IXGBE_ERR_PHY; 1181 goto out; 1182 } 1183 1184 /* Get init offsets */ 1185 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 1186 &data_offset); 1187 if (ret_val != IXGBE_SUCCESS) 1188 goto out; 1189 1190 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); 1191 data_offset++; 1192 while (!end_data) { 1193 /* 1194 * Read control word from PHY init contents offset 1195 */ 1196 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); 1197 if (ret_val) 1198 goto err_eeprom; 1199 control = (eword & IXGBE_CONTROL_MASK_NL) >> 1200 IXGBE_CONTROL_SHIFT_NL; 1201 edata = eword & IXGBE_DATA_MASK_NL; 1202 switch (control) { 1203 case IXGBE_DELAY_NL: 1204 data_offset++; 1205 DEBUGOUT1("DELAY: %d MS\n", edata); 1206 msec_delay(edata); 1207 break; 1208 case IXGBE_DATA_NL: 1209 DEBUGOUT("DATA:\n"); 1210 data_offset++; 1211 ret_val = hw->eeprom.ops.read(hw, data_offset, 1212 &phy_offset); 1213 if (ret_val) 1214 goto err_eeprom; 1215 data_offset++; 1216 for (i = 0; i < edata; i++) { 1217 ret_val = hw->eeprom.ops.read(hw, data_offset, 1218 &eword); 1219 if (ret_val) 1220 goto err_eeprom; 1221 hw->phy.ops.write_reg(hw, phy_offset, 1222 IXGBE_TWINAX_DEV, eword); 1223 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword, 1224 phy_offset); 1225 data_offset++; 1226 phy_offset++; 1227 } 1228 break; 1229 case IXGBE_CONTROL_NL: 1230 data_offset++; 1231 DEBUGOUT("CONTROL:\n"); 1232 if (edata == IXGBE_CONTROL_EOL_NL) { 1233 DEBUGOUT("EOL\n"); 1234 end_data = TRUE; 1235 } else if (edata == IXGBE_CONTROL_SOL_NL) { 1236 DEBUGOUT("SOL\n"); 1237 } else { 1238 DEBUGOUT("Bad control value\n"); 1239 ret_val = IXGBE_ERR_PHY; 1240 goto out; 1241 } 1242 break; 1243 default: 1244 DEBUGOUT("Bad control type\n"); 1245 ret_val = IXGBE_ERR_PHY; 1246 goto out; 1247 } 1248 } 1249 1250out: 1251 return ret_val; 1252 1253err_eeprom: 1254 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1255 "eeprom read at offset %d failed", data_offset); 1256 return IXGBE_ERR_PHY; 1257} 1258 1259/** 1260 * ixgbe_identify_module_generic - Identifies module type 1261 * @hw: pointer to hardware structure 1262 * 1263 * Determines HW type and calls appropriate function. 1264 **/ 1265s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw) 1266{ 1267 s32 status = IXGBE_ERR_SFP_NOT_PRESENT; 1268 1269 DEBUGFUNC("ixgbe_identify_module_generic"); 1270 1271 switch (hw->mac.ops.get_media_type(hw)) { 1272 case ixgbe_media_type_fiber: 1273 status = ixgbe_identify_sfp_module_generic(hw); 1274 break; 1275 1276 case ixgbe_media_type_fiber_qsfp: 1277 status = ixgbe_identify_qsfp_module_generic(hw); 1278 break; 1279 1280 default: 1281 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1282 status = IXGBE_ERR_SFP_NOT_PRESENT; 1283 break; 1284 } 1285 1286 return status; 1287} 1288 1289/** 1290 * ixgbe_identify_sfp_module_generic - Identifies SFP modules 1291 * @hw: pointer to hardware structure 1292 * 1293 * Searches for and identifies the SFP module and assigns appropriate PHY type. 1294 **/ 1295s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) 1296{ 1297 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1298 u32 vendor_oui = 0; 1299 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1300 u8 identifier = 0; 1301 u8 comp_codes_1g = 0; 1302 u8 comp_codes_10g = 0; 1303 u8 oui_bytes[3] = {0, 0, 0}; 1304 u8 cable_tech = 0; 1305 u8 cable_spec = 0; 1306 u16 enforce_sfp = 0; 1307 1308 DEBUGFUNC("ixgbe_identify_sfp_module_generic"); 1309 1310 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) { 1311 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1312 status = IXGBE_ERR_SFP_NOT_PRESENT; 1313 goto out; 1314 } 1315 1316 /* LAN ID is needed for I2C access */ 1317 hw->mac.ops.set_lan_id(hw); 1318 1319 status = hw->phy.ops.read_i2c_eeprom(hw, 1320 IXGBE_SFF_IDENTIFIER, 1321 &identifier); 1322 1323 if (status != IXGBE_SUCCESS) 1324 goto err_read_i2c_eeprom; 1325 1326 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) { 1327 hw->phy.type = ixgbe_phy_sfp_unsupported; 1328 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1329 } else { 1330 status = hw->phy.ops.read_i2c_eeprom(hw, 1331 IXGBE_SFF_1GBE_COMP_CODES, 1332 &comp_codes_1g); 1333 1334 if (status != IXGBE_SUCCESS) 1335 goto err_read_i2c_eeprom; 1336 1337 status = hw->phy.ops.read_i2c_eeprom(hw, 1338 IXGBE_SFF_10GBE_COMP_CODES, 1339 &comp_codes_10g); 1340 1341 if (status != IXGBE_SUCCESS) 1342 goto err_read_i2c_eeprom; 1343 status = hw->phy.ops.read_i2c_eeprom(hw, 1344 IXGBE_SFF_CABLE_TECHNOLOGY, 1345 &cable_tech); 1346 1347 if (status != IXGBE_SUCCESS) 1348 goto err_read_i2c_eeprom; 1349 1350 /* ID Module 1351 * ========= 1352 * 0 SFP_DA_CU 1353 * 1 SFP_SR 1354 * 2 SFP_LR 1355 * 3 SFP_DA_CORE0 - 82599-specific 1356 * 4 SFP_DA_CORE1 - 82599-specific 1357 * 5 SFP_SR/LR_CORE0 - 82599-specific 1358 * 6 SFP_SR/LR_CORE1 - 82599-specific 1359 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific 1360 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific 1361 * 9 SFP_1g_cu_CORE0 - 82599-specific 1362 * 10 SFP_1g_cu_CORE1 - 82599-specific 1363 * 11 SFP_1g_sx_CORE0 - 82599-specific 1364 * 12 SFP_1g_sx_CORE1 - 82599-specific 1365 */ 1366 if (hw->mac.type == ixgbe_mac_82598EB) { 1367 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1368 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 1369 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1370 hw->phy.sfp_type = ixgbe_sfp_type_sr; 1371 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1372 hw->phy.sfp_type = ixgbe_sfp_type_lr; 1373 else 1374 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1375 } else { 1376 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) { 1377 if (hw->bus.lan_id == 0) 1378 hw->phy.sfp_type = 1379 ixgbe_sfp_type_da_cu_core0; 1380 else 1381 hw->phy.sfp_type = 1382 ixgbe_sfp_type_da_cu_core1; 1383 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) { 1384 hw->phy.ops.read_i2c_eeprom( 1385 hw, IXGBE_SFF_CABLE_SPEC_COMP, 1386 &cable_spec); 1387 if (cable_spec & 1388 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) { 1389 if (hw->bus.lan_id == 0) 1390 hw->phy.sfp_type = 1391 ixgbe_sfp_type_da_act_lmt_core0; 1392 else 1393 hw->phy.sfp_type = 1394 ixgbe_sfp_type_da_act_lmt_core1; 1395 } else { 1396 hw->phy.sfp_type = 1397 ixgbe_sfp_type_unknown; 1398 } 1399 } else if (comp_codes_10g & 1400 (IXGBE_SFF_10GBASESR_CAPABLE | 1401 IXGBE_SFF_10GBASELR_CAPABLE)) { 1402 if (hw->bus.lan_id == 0) 1403 hw->phy.sfp_type = 1404 ixgbe_sfp_type_srlr_core0; 1405 else 1406 hw->phy.sfp_type = 1407 ixgbe_sfp_type_srlr_core1; 1408 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) { 1409 if (hw->bus.lan_id == 0) 1410 hw->phy.sfp_type = 1411 ixgbe_sfp_type_1g_cu_core0; 1412 else 1413 hw->phy.sfp_type = 1414 ixgbe_sfp_type_1g_cu_core1; 1415 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) { 1416 if (hw->bus.lan_id == 0) 1417 hw->phy.sfp_type = 1418 ixgbe_sfp_type_1g_sx_core0; 1419 else 1420 hw->phy.sfp_type = 1421 ixgbe_sfp_type_1g_sx_core1; 1422 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) { 1423 if (hw->bus.lan_id == 0) 1424 hw->phy.sfp_type = 1425 ixgbe_sfp_type_1g_lx_core0; 1426 else 1427 hw->phy.sfp_type = 1428 ixgbe_sfp_type_1g_lx_core1; 1429 } else { 1430 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1431 } 1432 } 1433 1434 if (hw->phy.sfp_type != stored_sfp_type) 1435 hw->phy.sfp_setup_needed = TRUE; 1436 1437 /* Determine if the SFP+ PHY is dual speed or not. */ 1438 hw->phy.multispeed_fiber = FALSE; 1439 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1440 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1441 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1442 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1443 hw->phy.multispeed_fiber = TRUE; 1444 1445 /* Determine PHY vendor */ 1446 if (hw->phy.type != ixgbe_phy_nl) { 1447 hw->phy.id = identifier; 1448 status = hw->phy.ops.read_i2c_eeprom(hw, 1449 IXGBE_SFF_VENDOR_OUI_BYTE0, 1450 &oui_bytes[0]); 1451 1452 if (status != IXGBE_SUCCESS) 1453 goto err_read_i2c_eeprom; 1454 1455 status = hw->phy.ops.read_i2c_eeprom(hw, 1456 IXGBE_SFF_VENDOR_OUI_BYTE1, 1457 &oui_bytes[1]); 1458 1459 if (status != IXGBE_SUCCESS) 1460 goto err_read_i2c_eeprom; 1461 1462 status = hw->phy.ops.read_i2c_eeprom(hw, 1463 IXGBE_SFF_VENDOR_OUI_BYTE2, 1464 &oui_bytes[2]); 1465 1466 if (status != IXGBE_SUCCESS) 1467 goto err_read_i2c_eeprom; 1468 1469 vendor_oui = 1470 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1471 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1472 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1473 1474 switch (vendor_oui) { 1475 case IXGBE_SFF_VENDOR_OUI_TYCO: 1476 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1477 hw->phy.type = 1478 ixgbe_phy_sfp_passive_tyco; 1479 break; 1480 case IXGBE_SFF_VENDOR_OUI_FTL: 1481 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1482 hw->phy.type = ixgbe_phy_sfp_ftl_active; 1483 else 1484 hw->phy.type = ixgbe_phy_sfp_ftl; 1485 break; 1486 case IXGBE_SFF_VENDOR_OUI_AVAGO: 1487 hw->phy.type = ixgbe_phy_sfp_avago; 1488 break; 1489 case IXGBE_SFF_VENDOR_OUI_INTEL: 1490 hw->phy.type = ixgbe_phy_sfp_intel; 1491 break; 1492 default: 1493 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1494 hw->phy.type = 1495 ixgbe_phy_sfp_passive_unknown; 1496 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1497 hw->phy.type = 1498 ixgbe_phy_sfp_active_unknown; 1499 else 1500 hw->phy.type = ixgbe_phy_sfp_unknown; 1501 break; 1502 } 1503 } 1504 1505 /* Allow any DA cable vendor */ 1506 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE | 1507 IXGBE_SFF_DA_ACTIVE_CABLE)) { 1508 status = IXGBE_SUCCESS; 1509 goto out; 1510 } 1511 1512 /* Verify supported 1G SFP modules */ 1513 if (comp_codes_10g == 0 && 1514 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1515 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1516 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1517 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1518 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1519 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1520 hw->phy.type = ixgbe_phy_sfp_unsupported; 1521 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1522 goto out; 1523 } 1524 1525 /* Anything else 82598-based is supported */ 1526 if (hw->mac.type == ixgbe_mac_82598EB) { 1527 status = IXGBE_SUCCESS; 1528 goto out; 1529 } 1530 1531 ixgbe_get_device_caps(hw, &enforce_sfp); 1532 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) && 1533 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1534 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1535 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1536 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1537 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1538 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1539 /* Make sure we're a supported PHY type */ 1540 if (hw->phy.type == ixgbe_phy_sfp_intel) { 1541 status = IXGBE_SUCCESS; 1542 } else { 1543 if (hw->allow_unsupported_sfp == TRUE) { 1544 EWARN(hw, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n"); 1545 status = IXGBE_SUCCESS; 1546 } else { 1547 DEBUGOUT("SFP+ module not supported\n"); 1548 hw->phy.type = 1549 ixgbe_phy_sfp_unsupported; 1550 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1551 } 1552 } 1553 } else { 1554 status = IXGBE_SUCCESS; 1555 } 1556 } 1557 1558out: 1559 return status; 1560 1561err_read_i2c_eeprom: 1562 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1563 if (hw->phy.type != ixgbe_phy_nl) { 1564 hw->phy.id = 0; 1565 hw->phy.type = ixgbe_phy_unknown; 1566 } 1567 return IXGBE_ERR_SFP_NOT_PRESENT; 1568} 1569 1570/** 1571 * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type 1572 * @hw: pointer to hardware structure 1573 * 1574 * Determines physical layer capabilities of the current SFP. 1575 */ 1576u64 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw) 1577{ 1578 u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1579 u8 comp_codes_10g = 0; 1580 u8 comp_codes_1g = 0; 1581 1582 DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic"); 1583 1584 hw->phy.ops.identify_sfp(hw); 1585 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1586 return physical_layer; 1587 1588 switch (hw->phy.type) { 1589 case ixgbe_phy_sfp_passive_tyco: 1590 case ixgbe_phy_sfp_passive_unknown: 1591 case ixgbe_phy_qsfp_passive_unknown: 1592 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1593 break; 1594 case ixgbe_phy_sfp_ftl_active: 1595 case ixgbe_phy_sfp_active_unknown: 1596 case ixgbe_phy_qsfp_active_unknown: 1597 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA; 1598 break; 1599 case ixgbe_phy_sfp_avago: 1600 case ixgbe_phy_sfp_ftl: 1601 case ixgbe_phy_sfp_intel: 1602 case ixgbe_phy_sfp_unknown: 1603 hw->phy.ops.read_i2c_eeprom(hw, 1604 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g); 1605 hw->phy.ops.read_i2c_eeprom(hw, 1606 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g); 1607 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1608 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1609 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1610 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1611 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) 1612 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T; 1613 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) 1614 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX; 1615 break; 1616 case ixgbe_phy_qsfp_intel: 1617 case ixgbe_phy_qsfp_unknown: 1618 hw->phy.ops.read_i2c_eeprom(hw, 1619 IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g); 1620 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1621 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1622 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1623 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1624 break; 1625 default: 1626 break; 1627 } 1628 1629 return physical_layer; 1630} 1631 1632/** 1633 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules 1634 * @hw: pointer to hardware structure 1635 * 1636 * Searches for and identifies the QSFP module and assigns appropriate PHY type 1637 **/ 1638s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw) 1639{ 1640 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1641 u32 vendor_oui = 0; 1642 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1643 u8 identifier = 0; 1644 u8 comp_codes_1g = 0; 1645 u8 comp_codes_10g = 0; 1646 u8 oui_bytes[3] = {0, 0, 0}; 1647 u16 enforce_sfp = 0; 1648 u8 connector = 0; 1649 u8 cable_length = 0; 1650 u8 device_tech = 0; 1651 bool active_cable = FALSE; 1652 1653 DEBUGFUNC("ixgbe_identify_qsfp_module_generic"); 1654 1655 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) { 1656 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1657 status = IXGBE_ERR_SFP_NOT_PRESENT; 1658 goto out; 1659 } 1660 1661 /* LAN ID is needed for I2C access */ 1662 hw->mac.ops.set_lan_id(hw); 1663 1664 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER, 1665 &identifier); 1666 1667 if (status != IXGBE_SUCCESS) 1668 goto err_read_i2c_eeprom; 1669 1670 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) { 1671 hw->phy.type = ixgbe_phy_sfp_unsupported; 1672 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1673 goto out; 1674 } 1675 1676 hw->phy.id = identifier; 1677 1678 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP, 1679 &comp_codes_10g); 1680 1681 if (status != IXGBE_SUCCESS) 1682 goto err_read_i2c_eeprom; 1683 1684 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP, 1685 &comp_codes_1g); 1686 1687 if (status != IXGBE_SUCCESS) 1688 goto err_read_i2c_eeprom; 1689 1690 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) { 1691 hw->phy.type = ixgbe_phy_qsfp_passive_unknown; 1692 if (hw->bus.lan_id == 0) 1693 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0; 1694 else 1695 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1; 1696 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1697 IXGBE_SFF_10GBASELR_CAPABLE)) { 1698 if (hw->bus.lan_id == 0) 1699 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0; 1700 else 1701 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1; 1702 } else { 1703 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE) 1704 active_cable = TRUE; 1705 1706 if (!active_cable) { 1707 /* check for active DA cables that pre-date 1708 * SFF-8436 v3.6 */ 1709 hw->phy.ops.read_i2c_eeprom(hw, 1710 IXGBE_SFF_QSFP_CONNECTOR, 1711 &connector); 1712 1713 hw->phy.ops.read_i2c_eeprom(hw, 1714 IXGBE_SFF_QSFP_CABLE_LENGTH, 1715 &cable_length); 1716 1717 hw->phy.ops.read_i2c_eeprom(hw, 1718 IXGBE_SFF_QSFP_DEVICE_TECH, 1719 &device_tech); 1720 1721 if ((connector == 1722 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) && 1723 (cable_length > 0) && 1724 ((device_tech >> 4) == 1725 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL)) 1726 active_cable = TRUE; 1727 } 1728 1729 if (active_cable) { 1730 hw->phy.type = ixgbe_phy_qsfp_active_unknown; 1731 if (hw->bus.lan_id == 0) 1732 hw->phy.sfp_type = 1733 ixgbe_sfp_type_da_act_lmt_core0; 1734 else 1735 hw->phy.sfp_type = 1736 ixgbe_sfp_type_da_act_lmt_core1; 1737 } else { 1738 /* unsupported module type */ 1739 hw->phy.type = ixgbe_phy_sfp_unsupported; 1740 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1741 goto out; 1742 } 1743 } 1744 1745 if (hw->phy.sfp_type != stored_sfp_type) 1746 hw->phy.sfp_setup_needed = TRUE; 1747 1748 /* Determine if the QSFP+ PHY is dual speed or not. */ 1749 hw->phy.multispeed_fiber = FALSE; 1750 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1751 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1752 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1753 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1754 hw->phy.multispeed_fiber = TRUE; 1755 1756 /* Determine PHY vendor for optical modules */ 1757 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1758 IXGBE_SFF_10GBASELR_CAPABLE)) { 1759 status = hw->phy.ops.read_i2c_eeprom(hw, 1760 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0, 1761 &oui_bytes[0]); 1762 1763 if (status != IXGBE_SUCCESS) 1764 goto err_read_i2c_eeprom; 1765 1766 status = hw->phy.ops.read_i2c_eeprom(hw, 1767 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1, 1768 &oui_bytes[1]); 1769 1770 if (status != IXGBE_SUCCESS) 1771 goto err_read_i2c_eeprom; 1772 1773 status = hw->phy.ops.read_i2c_eeprom(hw, 1774 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2, 1775 &oui_bytes[2]); 1776 1777 if (status != IXGBE_SUCCESS) 1778 goto err_read_i2c_eeprom; 1779 1780 vendor_oui = 1781 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1782 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1783 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1784 1785 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL) 1786 hw->phy.type = ixgbe_phy_qsfp_intel; 1787 else 1788 hw->phy.type = ixgbe_phy_qsfp_unknown; 1789 1790 ixgbe_get_device_caps(hw, &enforce_sfp); 1791 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) { 1792 /* Make sure we're a supported PHY type */ 1793 if (hw->phy.type == ixgbe_phy_qsfp_intel) { 1794 status = IXGBE_SUCCESS; 1795 } else { 1796 if (hw->allow_unsupported_sfp == TRUE) { 1797 EWARN(hw, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n"); 1798 status = IXGBE_SUCCESS; 1799 } else { 1800 DEBUGOUT("QSFP module not supported\n"); 1801 hw->phy.type = 1802 ixgbe_phy_sfp_unsupported; 1803 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1804 } 1805 } 1806 } else { 1807 status = IXGBE_SUCCESS; 1808 } 1809 } 1810 1811out: 1812 return status; 1813 1814err_read_i2c_eeprom: 1815 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1816 hw->phy.id = 0; 1817 hw->phy.type = ixgbe_phy_unknown; 1818 1819 return IXGBE_ERR_SFP_NOT_PRESENT; 1820} 1821 1822/** 1823 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence 1824 * @hw: pointer to hardware structure 1825 * @list_offset: offset to the SFP ID list 1826 * @data_offset: offset to the SFP data block 1827 * 1828 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if 1829 * so it returns the offsets to the phy init sequence block. 1830 **/ 1831s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 1832 u16 *list_offset, 1833 u16 *data_offset) 1834{ 1835 u16 sfp_id; 1836 u16 sfp_type = hw->phy.sfp_type; 1837 1838 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets"); 1839 1840 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 1841 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1842 1843 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1844 return IXGBE_ERR_SFP_NOT_PRESENT; 1845 1846 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && 1847 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) 1848 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1849 1850 /* 1851 * Limiting active cables and 1G Phys must be initialized as 1852 * SR modules 1853 */ 1854 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 || 1855 sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1856 sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1857 sfp_type == ixgbe_sfp_type_1g_sx_core0) 1858 sfp_type = ixgbe_sfp_type_srlr_core0; 1859 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 || 1860 sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1861 sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1862 sfp_type == ixgbe_sfp_type_1g_sx_core1) 1863 sfp_type = ixgbe_sfp_type_srlr_core1; 1864 1865 /* Read offset to PHY init contents */ 1866 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) { 1867 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1868 "eeprom read at offset %d failed", 1869 IXGBE_PHY_INIT_OFFSET_NL); 1870 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1871 } 1872 1873 if ((!*list_offset) || (*list_offset == 0xFFFF)) 1874 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1875 1876 /* Shift offset to first ID word */ 1877 (*list_offset)++; 1878 1879 /* 1880 * Find the matching SFP ID in the EEPROM 1881 * and program the init sequence 1882 */ 1883 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1884 goto err_phy; 1885 1886 while (sfp_id != IXGBE_PHY_INIT_END_NL) { 1887 if (sfp_id == sfp_type) { 1888 (*list_offset)++; 1889 if (hw->eeprom.ops.read(hw, *list_offset, data_offset)) 1890 goto err_phy; 1891 if ((!*data_offset) || (*data_offset == 0xFFFF)) { 1892 DEBUGOUT("SFP+ module not supported\n"); 1893 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1894 } else { 1895 break; 1896 } 1897 } else { 1898 (*list_offset) += 2; 1899 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1900 goto err_phy; 1901 } 1902 } 1903 1904 if (sfp_id == IXGBE_PHY_INIT_END_NL) { 1905 DEBUGOUT("No matching SFP+ module found\n"); 1906 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1907 } 1908 1909 return IXGBE_SUCCESS; 1910 1911err_phy: 1912 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1913 "eeprom read at offset %d failed", *list_offset); 1914 return IXGBE_ERR_PHY; 1915} 1916 1917/** 1918 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface 1919 * @hw: pointer to hardware structure 1920 * @byte_offset: EEPROM byte offset to read 1921 * @eeprom_data: value read 1922 * 1923 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1924 **/ 1925s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1926 u8 *eeprom_data) 1927{ 1928 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic"); 1929 1930 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1931 IXGBE_I2C_EEPROM_DEV_ADDR, 1932 eeprom_data); 1933} 1934 1935/** 1936 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface 1937 * @hw: pointer to hardware structure 1938 * @byte_offset: byte offset at address 0xA2 1939 * @eeprom_data: value read 1940 * 1941 * Performs byte read operation to SFP module's SFF-8472 data over I2C 1942 **/ 1943static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 1944 u8 *sff8472_data) 1945{ 1946 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1947 IXGBE_I2C_EEPROM_DEV_ADDR2, 1948 sff8472_data); 1949} 1950 1951/** 1952 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface 1953 * @hw: pointer to hardware structure 1954 * @byte_offset: EEPROM byte offset to write 1955 * @eeprom_data: value to write 1956 * 1957 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1958 **/ 1959s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1960 u8 eeprom_data) 1961{ 1962 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic"); 1963 1964 return hw->phy.ops.write_i2c_byte(hw, byte_offset, 1965 IXGBE_I2C_EEPROM_DEV_ADDR, 1966 eeprom_data); 1967} 1968 1969/** 1970 * ixgbe_is_sfp_probe - Returns TRUE if SFP is being detected 1971 * @hw: pointer to hardware structure 1972 * @offset: eeprom offset to be read 1973 * @addr: I2C address to be read 1974 */ 1975static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr) 1976{ 1977 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR && 1978 offset == IXGBE_SFF_IDENTIFIER && 1979 hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1980 return TRUE; 1981 return FALSE; 1982} 1983 1984/** 1985 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C 1986 * @hw: pointer to hardware structure 1987 * @byte_offset: byte offset to read 1988 * @data: value read 1989 * @lock: TRUE if to take and release semaphore 1990 * 1991 * Performs byte read operation to SFP module's EEPROM over I2C interface at 1992 * a specified device address. 1993 **/ 1994static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, 1995 u8 dev_addr, u8 *data, bool lock) 1996{ 1997 s32 status; 1998 u32 max_retry = 10; 1999 u32 retry = 0; 2000 u32 swfw_mask = hw->phy.phy_semaphore_mask; 2001 bool nack = 1; 2002 *data = 0; 2003 2004 DEBUGFUNC("ixgbe_read_i2c_byte_generic"); 2005 2006 if (hw->mac.type >= ixgbe_mac_X550) 2007 max_retry = 3; 2008 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr)) 2009 max_retry = IXGBE_SFP_DETECT_RETRIES; 2010 2011 do { 2012 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 2013 return IXGBE_ERR_SWFW_SYNC; 2014 2015 ixgbe_i2c_start(hw); 2016 2017 /* Device Address and write indication */ 2018 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 2019 if (status != IXGBE_SUCCESS) 2020 goto fail; 2021 2022 status = ixgbe_get_i2c_ack(hw); 2023 if (status != IXGBE_SUCCESS) 2024 goto fail; 2025 2026 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 2027 if (status != IXGBE_SUCCESS) 2028 goto fail; 2029 2030 status = ixgbe_get_i2c_ack(hw); 2031 if (status != IXGBE_SUCCESS) 2032 goto fail; 2033 2034 ixgbe_i2c_start(hw); 2035 2036 /* Device Address and read indication */ 2037 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 2038 if (status != IXGBE_SUCCESS) 2039 goto fail; 2040 2041 status = ixgbe_get_i2c_ack(hw); 2042 if (status != IXGBE_SUCCESS) 2043 goto fail; 2044 2045 status = ixgbe_clock_in_i2c_byte(hw, data); 2046 if (status != IXGBE_SUCCESS) 2047 goto fail; 2048 2049 status = ixgbe_clock_out_i2c_bit(hw, nack); 2050 if (status != IXGBE_SUCCESS) 2051 goto fail; 2052 2053 ixgbe_i2c_stop(hw); 2054 if (lock) 2055 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2056 return IXGBE_SUCCESS; 2057 2058fail: 2059 ixgbe_i2c_bus_clear(hw); 2060 if (lock) { 2061 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2062 msec_delay(100); 2063 } 2064 retry++; 2065 if (retry < max_retry) 2066 DEBUGOUT("I2C byte read error - Retrying.\n"); 2067 else 2068 DEBUGOUT("I2C byte read error.\n"); 2069 2070 } while (retry < max_retry); 2071 2072 return status; 2073} 2074 2075/** 2076 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C 2077 * @hw: pointer to hardware structure 2078 * @byte_offset: byte offset to read 2079 * @data: value read 2080 * 2081 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2082 * a specified device address. 2083 **/ 2084s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 2085 u8 dev_addr, u8 *data) 2086{ 2087 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2088 data, TRUE); 2089} 2090 2091/** 2092 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C 2093 * @hw: pointer to hardware structure 2094 * @byte_offset: byte offset to read 2095 * @data: value read 2096 * 2097 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2098 * a specified device address. 2099 **/ 2100s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 2101 u8 dev_addr, u8 *data) 2102{ 2103 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2104 data, FALSE); 2105} 2106 2107/** 2108 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C 2109 * @hw: pointer to hardware structure 2110 * @byte_offset: byte offset to write 2111 * @data: value to write 2112 * @lock: TRUE if to take and release semaphore 2113 * 2114 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2115 * a specified device address. 2116 **/ 2117static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, 2118 u8 dev_addr, u8 data, bool lock) 2119{ 2120 s32 status; 2121 u32 max_retry = 1; 2122 u32 retry = 0; 2123 u32 swfw_mask = hw->phy.phy_semaphore_mask; 2124 2125 DEBUGFUNC("ixgbe_write_i2c_byte_generic"); 2126 2127 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 2128 IXGBE_SUCCESS) 2129 return IXGBE_ERR_SWFW_SYNC; 2130 2131 do { 2132 ixgbe_i2c_start(hw); 2133 2134 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 2135 if (status != IXGBE_SUCCESS) 2136 goto fail; 2137 2138 status = ixgbe_get_i2c_ack(hw); 2139 if (status != IXGBE_SUCCESS) 2140 goto fail; 2141 2142 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 2143 if (status != IXGBE_SUCCESS) 2144 goto fail; 2145 2146 status = ixgbe_get_i2c_ack(hw); 2147 if (status != IXGBE_SUCCESS) 2148 goto fail; 2149 2150 status = ixgbe_clock_out_i2c_byte(hw, data); 2151 if (status != IXGBE_SUCCESS) 2152 goto fail; 2153 2154 status = ixgbe_get_i2c_ack(hw); 2155 if (status != IXGBE_SUCCESS) 2156 goto fail; 2157 2158 ixgbe_i2c_stop(hw); 2159 if (lock) 2160 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2161 return IXGBE_SUCCESS; 2162 2163fail: 2164 ixgbe_i2c_bus_clear(hw); 2165 retry++; 2166 if (retry < max_retry) 2167 DEBUGOUT("I2C byte write error - Retrying.\n"); 2168 else 2169 DEBUGOUT("I2C byte write error.\n"); 2170 } while (retry < max_retry); 2171 2172 if (lock) 2173 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2174 2175 return status; 2176} 2177 2178/** 2179 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C 2180 * @hw: pointer to hardware structure 2181 * @byte_offset: byte offset to write 2182 * @data: value to write 2183 * 2184 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2185 * a specified device address. 2186 **/ 2187s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 2188 u8 dev_addr, u8 data) 2189{ 2190 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2191 data, TRUE); 2192} 2193 2194/** 2195 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C 2196 * @hw: pointer to hardware structure 2197 * @byte_offset: byte offset to write 2198 * @data: value to write 2199 * 2200 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2201 * a specified device address. 2202 **/ 2203s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 2204 u8 dev_addr, u8 data) 2205{ 2206 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2207 data, FALSE); 2208} 2209 2210/** 2211 * ixgbe_i2c_start - Sets I2C start condition 2212 * @hw: pointer to hardware structure 2213 * 2214 * Sets I2C start condition (High -> Low on SDA while SCL is High) 2215 * Set bit-bang mode on X550 hardware. 2216 **/ 2217static void ixgbe_i2c_start(struct ixgbe_hw *hw) 2218{ 2219 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2220 2221 DEBUGFUNC("ixgbe_i2c_start"); 2222 2223 i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw); 2224 2225 /* Start condition must begin with data and clock high */ 2226 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2227 ixgbe_raise_i2c_clk(hw, &i2cctl); 2228 2229 /* Setup time for start condition (4.7us) */ 2230 usec_delay(IXGBE_I2C_T_SU_STA); 2231 2232 ixgbe_set_i2c_data(hw, &i2cctl, 0); 2233 2234 /* Hold time for start condition (4us) */ 2235 usec_delay(IXGBE_I2C_T_HD_STA); 2236 2237 ixgbe_lower_i2c_clk(hw, &i2cctl); 2238 2239 /* Minimum low period of clock is 4.7 us */ 2240 usec_delay(IXGBE_I2C_T_LOW); 2241 2242} 2243 2244/** 2245 * ixgbe_i2c_stop - Sets I2C stop condition 2246 * @hw: pointer to hardware structure 2247 * 2248 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 2249 * Disables bit-bang mode and negates data output enable on X550 2250 * hardware. 2251 **/ 2252static void ixgbe_i2c_stop(struct ixgbe_hw *hw) 2253{ 2254 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2255 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2256 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2257 u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw); 2258 2259 DEBUGFUNC("ixgbe_i2c_stop"); 2260 2261 /* Stop condition must begin with data low and clock high */ 2262 ixgbe_set_i2c_data(hw, &i2cctl, 0); 2263 ixgbe_raise_i2c_clk(hw, &i2cctl); 2264 2265 /* Setup time for stop condition (4us) */ 2266 usec_delay(IXGBE_I2C_T_SU_STO); 2267 2268 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2269 2270 /* bus free time between stop and start (4.7us)*/ 2271 usec_delay(IXGBE_I2C_T_BUF); 2272 2273 if (bb_en_bit || data_oe_bit || clk_oe_bit) { 2274 i2cctl &= ~bb_en_bit; 2275 i2cctl |= data_oe_bit | clk_oe_bit; 2276 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2277 IXGBE_WRITE_FLUSH(hw); 2278 } 2279} 2280 2281/** 2282 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C 2283 * @hw: pointer to hardware structure 2284 * @data: data byte to clock in 2285 * 2286 * Clocks in one byte data via I2C data/clock 2287 **/ 2288static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data) 2289{ 2290 s32 i; 2291 bool bit = 0; 2292 2293 DEBUGFUNC("ixgbe_clock_in_i2c_byte"); 2294 2295 *data = 0; 2296 for (i = 7; i >= 0; i--) { 2297 ixgbe_clock_in_i2c_bit(hw, &bit); 2298 *data |= bit << i; 2299 } 2300 2301 return IXGBE_SUCCESS; 2302} 2303 2304/** 2305 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C 2306 * @hw: pointer to hardware structure 2307 * @data: data byte clocked out 2308 * 2309 * Clocks out one byte data via I2C data/clock 2310 **/ 2311static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data) 2312{ 2313 s32 status = IXGBE_SUCCESS; 2314 s32 i; 2315 u32 i2cctl; 2316 bool bit; 2317 2318 DEBUGFUNC("ixgbe_clock_out_i2c_byte"); 2319 2320 for (i = 7; i >= 0; i--) { 2321 bit = (data >> i) & 0x1; 2322 status = ixgbe_clock_out_i2c_bit(hw, bit); 2323 2324 if (status != IXGBE_SUCCESS) 2325 break; 2326 } 2327 2328 /* Release SDA line (set high) */ 2329 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2330 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2331 i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2332 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2333 IXGBE_WRITE_FLUSH(hw); 2334 2335 return status; 2336} 2337 2338/** 2339 * ixgbe_get_i2c_ack - Polls for I2C ACK 2340 * @hw: pointer to hardware structure 2341 * 2342 * Clocks in/out one bit via I2C data/clock 2343 **/ 2344static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw) 2345{ 2346 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2347 s32 status = IXGBE_SUCCESS; 2348 u32 i = 0; 2349 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2350 u32 timeout = 10; 2351 bool ack = 1; 2352 2353 DEBUGFUNC("ixgbe_get_i2c_ack"); 2354 2355 if (data_oe_bit) { 2356 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2357 i2cctl |= data_oe_bit; 2358 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2359 IXGBE_WRITE_FLUSH(hw); 2360 } 2361 ixgbe_raise_i2c_clk(hw, &i2cctl); 2362 2363 /* Minimum high period of clock is 4us */ 2364 usec_delay(IXGBE_I2C_T_HIGH); 2365 2366 /* Poll for ACK. Note that ACK in I2C spec is 2367 * transition from 1 to 0 */ 2368 for (i = 0; i < timeout; i++) { 2369 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2370 ack = ixgbe_get_i2c_data(hw, &i2cctl); 2371 2372 usec_delay(1); 2373 if (!ack) 2374 break; 2375 } 2376 2377 if (ack) { 2378 DEBUGOUT("I2C ack was not received.\n"); 2379 status = IXGBE_ERR_I2C; 2380 } 2381 2382 ixgbe_lower_i2c_clk(hw, &i2cctl); 2383 2384 /* Minimum low period of clock is 4.7 us */ 2385 usec_delay(IXGBE_I2C_T_LOW); 2386 2387 return status; 2388} 2389 2390/** 2391 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 2392 * @hw: pointer to hardware structure 2393 * @data: read data value 2394 * 2395 * Clocks in one bit via I2C data/clock 2396 **/ 2397static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data) 2398{ 2399 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2400 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2401 2402 DEBUGFUNC("ixgbe_clock_in_i2c_bit"); 2403 2404 if (data_oe_bit) { 2405 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2406 i2cctl |= data_oe_bit; 2407 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2408 IXGBE_WRITE_FLUSH(hw); 2409 } 2410 ixgbe_raise_i2c_clk(hw, &i2cctl); 2411 2412 /* Minimum high period of clock is 4us */ 2413 usec_delay(IXGBE_I2C_T_HIGH); 2414 2415 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2416 *data = ixgbe_get_i2c_data(hw, &i2cctl); 2417 2418 ixgbe_lower_i2c_clk(hw, &i2cctl); 2419 2420 /* Minimum low period of clock is 4.7 us */ 2421 usec_delay(IXGBE_I2C_T_LOW); 2422 2423 return IXGBE_SUCCESS; 2424} 2425 2426/** 2427 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 2428 * @hw: pointer to hardware structure 2429 * @data: data value to write 2430 * 2431 * Clocks out one bit via I2C data/clock 2432 **/ 2433static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data) 2434{ 2435 s32 status; 2436 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2437 2438 DEBUGFUNC("ixgbe_clock_out_i2c_bit"); 2439 2440 status = ixgbe_set_i2c_data(hw, &i2cctl, data); 2441 if (status == IXGBE_SUCCESS) { 2442 ixgbe_raise_i2c_clk(hw, &i2cctl); 2443 2444 /* Minimum high period of clock is 4us */ 2445 usec_delay(IXGBE_I2C_T_HIGH); 2446 2447 ixgbe_lower_i2c_clk(hw, &i2cctl); 2448 2449 /* Minimum low period of clock is 4.7 us. 2450 * This also takes care of the data hold time. 2451 */ 2452 usec_delay(IXGBE_I2C_T_LOW); 2453 } else { 2454 status = IXGBE_ERR_I2C; 2455 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2456 "I2C data was not set to %X\n", data); 2457 } 2458 2459 return status; 2460} 2461 2462/** 2463 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock 2464 * @hw: pointer to hardware structure 2465 * @i2cctl: Current value of I2CCTL register 2466 * 2467 * Raises the I2C clock line '0'->'1' 2468 * Negates the I2C clock output enable on X550 hardware. 2469 **/ 2470static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2471{ 2472 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2473 u32 i = 0; 2474 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT; 2475 u32 i2cctl_r = 0; 2476 2477 DEBUGFUNC("ixgbe_raise_i2c_clk"); 2478 2479 if (clk_oe_bit) { 2480 *i2cctl |= clk_oe_bit; 2481 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2482 } 2483 2484 for (i = 0; i < timeout; i++) { 2485 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw); 2486 2487 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2488 IXGBE_WRITE_FLUSH(hw); 2489 /* SCL rise time (1000ns) */ 2490 usec_delay(IXGBE_I2C_T_RISE); 2491 2492 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2493 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw)) 2494 break; 2495 } 2496} 2497 2498/** 2499 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock 2500 * @hw: pointer to hardware structure 2501 * @i2cctl: Current value of I2CCTL register 2502 * 2503 * Lowers the I2C clock line '1'->'0' 2504 * Asserts the I2C clock output enable on X550 hardware. 2505 **/ 2506static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2507{ 2508 DEBUGFUNC("ixgbe_lower_i2c_clk"); 2509 2510 *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw)); 2511 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2512 2513 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2514 IXGBE_WRITE_FLUSH(hw); 2515 2516 /* SCL fall time (300ns) */ 2517 usec_delay(IXGBE_I2C_T_FALL); 2518} 2519 2520/** 2521 * ixgbe_set_i2c_data - Sets the I2C data bit 2522 * @hw: pointer to hardware structure 2523 * @i2cctl: Current value of I2CCTL register 2524 * @data: I2C data value (0 or 1) to set 2525 * 2526 * Sets the I2C data bit 2527 * Asserts the I2C data output enable on X550 hardware. 2528 **/ 2529static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data) 2530{ 2531 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2532 s32 status = IXGBE_SUCCESS; 2533 2534 DEBUGFUNC("ixgbe_set_i2c_data"); 2535 2536 if (data) 2537 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2538 else 2539 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw)); 2540 *i2cctl &= ~data_oe_bit; 2541 2542 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2543 IXGBE_WRITE_FLUSH(hw); 2544 2545 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 2546 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); 2547 2548 if (!data) /* Can't verify data in this case */ 2549 return IXGBE_SUCCESS; 2550 if (data_oe_bit) { 2551 *i2cctl |= data_oe_bit; 2552 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2553 IXGBE_WRITE_FLUSH(hw); 2554 } 2555 2556 /* Verify data was set correctly */ 2557 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2558 if (data != ixgbe_get_i2c_data(hw, i2cctl)) { 2559 status = IXGBE_ERR_I2C; 2560 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2561 "Error - I2C data was not set to %X.\n", 2562 data); 2563 } 2564 2565 return status; 2566} 2567 2568/** 2569 * ixgbe_get_i2c_data - Reads the I2C SDA data bit 2570 * @hw: pointer to hardware structure 2571 * @i2cctl: Current value of I2CCTL register 2572 * 2573 * Returns the I2C data bit value 2574 * Negates the I2C data output enable on X550 hardware. 2575 **/ 2576static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl) 2577{ 2578 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2579 bool data; 2580 2581 DEBUGFUNC("ixgbe_get_i2c_data"); 2582 2583 if (data_oe_bit) { 2584 *i2cctl |= data_oe_bit; 2585 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2586 IXGBE_WRITE_FLUSH(hw); 2587 usec_delay(IXGBE_I2C_T_FALL); 2588 } 2589 2590 if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw)) 2591 data = 1; 2592 else 2593 data = 0; 2594 2595 return data; 2596} 2597 2598/** 2599 * ixgbe_i2c_bus_clear - Clears the I2C bus 2600 * @hw: pointer to hardware structure 2601 * 2602 * Clears the I2C bus by sending nine clock pulses. 2603 * Used when data line is stuck low. 2604 **/ 2605void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) 2606{ 2607 u32 i2cctl; 2608 u32 i; 2609 2610 DEBUGFUNC("ixgbe_i2c_bus_clear"); 2611 2612 ixgbe_i2c_start(hw); 2613 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2614 2615 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2616 2617 for (i = 0; i < 9; i++) { 2618 ixgbe_raise_i2c_clk(hw, &i2cctl); 2619 2620 /* Min high period of clock is 4us */ 2621 usec_delay(IXGBE_I2C_T_HIGH); 2622 2623 ixgbe_lower_i2c_clk(hw, &i2cctl); 2624 2625 /* Min low period of clock is 4.7us*/ 2626 usec_delay(IXGBE_I2C_T_LOW); 2627 } 2628 2629 ixgbe_i2c_start(hw); 2630 2631 /* Put the i2c bus back to default state */ 2632 ixgbe_i2c_stop(hw); 2633} 2634 2635/** 2636 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred. 2637 * @hw: pointer to hardware structure 2638 * 2639 * Checks if the LASI temp alarm status was triggered due to overtemp 2640 **/ 2641s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw) 2642{ 2643 s32 status = IXGBE_SUCCESS; 2644 u16 phy_data = 0; 2645 2646 DEBUGFUNC("ixgbe_tn_check_overtemp"); 2647 2648 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM) 2649 goto out; 2650 2651 /* Check that the LASI temp alarm status was triggered */ 2652 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG, 2653 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data); 2654 2655 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM)) 2656 goto out; 2657 2658 status = IXGBE_ERR_OVERTEMP; 2659 ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature"); 2660out: 2661 return status; 2662} 2663 2664/** 2665 * ixgbe_set_copper_phy_power - Control power for copper phy 2666 * @hw: pointer to hardware structure 2667 * @on: TRUE for on, FALSE for off 2668 */ 2669s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on) 2670{ 2671 u32 status; 2672 u16 reg; 2673 2674 if (!on && ixgbe_mng_present(hw)) 2675 return 0; 2676 2677 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2678 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2679 ®); 2680 if (status) 2681 return status; 2682 2683 if (on) { 2684 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2685 } else { 2686 if (ixgbe_check_reset_blocked(hw)) 2687 return 0; 2688 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2689 } 2690 2691 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2692 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2693 reg); 2694 return status; 2695} 2696