ixgbe_phy.c revision 251964
1179055Sjfv/****************************************************************************** 2171384Sjfv 3247822Sjfv Copyright (c) 2001-2013, Intel Corporation 4171384Sjfv All rights reserved. 5171384Sjfv 6171384Sjfv Redistribution and use in source and binary forms, with or without 7171384Sjfv modification, are permitted provided that the following conditions are met: 8171384Sjfv 9171384Sjfv 1. Redistributions of source code must retain the above copyright notice, 10171384Sjfv this list of conditions and the following disclaimer. 11171384Sjfv 12171384Sjfv 2. Redistributions in binary form must reproduce the above copyright 13171384Sjfv notice, this list of conditions and the following disclaimer in the 14171384Sjfv documentation and/or other materials provided with the distribution. 15171384Sjfv 16171384Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17171384Sjfv contributors may be used to endorse or promote products derived from 18171384Sjfv this software without specific prior written permission. 19171384Sjfv 20171384Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21171384Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22171384Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23171384Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24171384Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25171384Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26171384Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27171384Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28171384Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29171384Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30171384Sjfv POSSIBILITY OF SUCH DAMAGE. 31171384Sjfv 32179055Sjfv******************************************************************************/ 33179055Sjfv/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_phy.c 251964 2013-06-18 21:28:19Z jfv $*/ 34171384Sjfv 35171384Sjfv#include "ixgbe_api.h" 36171384Sjfv#include "ixgbe_common.h" 37171384Sjfv#include "ixgbe_phy.h" 38171384Sjfv 39190873Sjfvstatic void ixgbe_i2c_start(struct ixgbe_hw *hw); 40190873Sjfvstatic void ixgbe_i2c_stop(struct ixgbe_hw *hw); 41190873Sjfvstatic s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data); 42190873Sjfvstatic s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data); 43190873Sjfvstatic s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw); 44190873Sjfvstatic s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data); 45190873Sjfvstatic s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data); 46230775Sjfvstatic void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 47190873Sjfvstatic void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 48190873Sjfvstatic s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data); 49190873Sjfvstatic bool ixgbe_get_i2c_data(u32 *i2cctl); 50247822Sjfvstatic s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 51247822Sjfv u8 *sff8472_data); 52190873Sjfv 53171384Sjfv/** 54179055Sjfv * ixgbe_init_phy_ops_generic - Inits PHY function ptrs 55179055Sjfv * @hw: pointer to the hardware structure 56179055Sjfv * 57179055Sjfv * Initialize the function pointers. 58171384Sjfv **/ 59179055Sjfvs32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw) 60171384Sjfv{ 61179055Sjfv struct ixgbe_phy_info *phy = &hw->phy; 62171384Sjfv 63200239Sjfv DEBUGFUNC("ixgbe_init_phy_ops_generic"); 64200239Sjfv 65179055Sjfv /* PHY */ 66179055Sjfv phy->ops.identify = &ixgbe_identify_phy_generic; 67179055Sjfv phy->ops.reset = &ixgbe_reset_phy_generic; 68179055Sjfv phy->ops.read_reg = &ixgbe_read_phy_reg_generic; 69179055Sjfv phy->ops.write_reg = &ixgbe_write_phy_reg_generic; 70251964Sjfv phy->ops.read_reg_mdi = &ixgbe_read_phy_reg_mdi; 71251964Sjfv phy->ops.write_reg_mdi = &ixgbe_write_phy_reg_mdi; 72179055Sjfv phy->ops.setup_link = &ixgbe_setup_phy_link_generic; 73179055Sjfv phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic; 74179055Sjfv phy->ops.check_link = NULL; 75200239Sjfv phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic; 76190873Sjfv phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_generic; 77190873Sjfv phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_generic; 78247822Sjfv phy->ops.read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic; 79190873Sjfv phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic; 80190873Sjfv phy->ops.write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic; 81190873Sjfv phy->ops.i2c_bus_clear = &ixgbe_i2c_bus_clear; 82230775Sjfv phy->ops.identify_sfp = &ixgbe_identify_module_generic; 83185352Sjfv phy->sfp_type = ixgbe_sfp_type_unknown; 84205720Sjfv phy->ops.check_overtemp = &ixgbe_tn_check_overtemp; 85171384Sjfv return IXGBE_SUCCESS; 86171384Sjfv} 87171384Sjfv 88171384Sjfv/** 89171384Sjfv * ixgbe_identify_phy_generic - Get physical layer module 90171384Sjfv * @hw: pointer to hardware structure 91171384Sjfv * 92171384Sjfv * Determines the physical layer module found on the current adapter. 93171384Sjfv **/ 94171384Sjfvs32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) 95171384Sjfv{ 96171384Sjfv s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 97171384Sjfv u32 phy_addr; 98190873Sjfv u16 ext_ability = 0; 99171384Sjfv 100200239Sjfv DEBUGFUNC("ixgbe_identify_phy_generic"); 101200239Sjfv 102179055Sjfv if (hw->phy.type == ixgbe_phy_unknown) { 103179055Sjfv for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { 104179055Sjfv if (ixgbe_validate_phy_addr(hw, phy_addr)) { 105179055Sjfv hw->phy.addr = phy_addr; 106179055Sjfv ixgbe_get_phy_id(hw); 107179055Sjfv hw->phy.type = 108230775Sjfv ixgbe_get_phy_type_from_id(hw->phy.id); 109190873Sjfv 110190873Sjfv if (hw->phy.type == ixgbe_phy_unknown) { 111190873Sjfv hw->phy.ops.read_reg(hw, 112190873Sjfv IXGBE_MDIO_PHY_EXT_ABILITY, 113230775Sjfv IXGBE_MDIO_PMA_PMD_DEV_TYPE, 114230775Sjfv &ext_ability); 115190873Sjfv if (ext_ability & 116215911Sjfv (IXGBE_MDIO_PHY_10GBASET_ABILITY | 117215911Sjfv IXGBE_MDIO_PHY_1000BASET_ABILITY)) 118190873Sjfv hw->phy.type = 119230775Sjfv ixgbe_phy_cu_unknown; 120190873Sjfv else 121190873Sjfv hw->phy.type = 122230775Sjfv ixgbe_phy_generic; 123190873Sjfv } 124190873Sjfv 125179055Sjfv status = IXGBE_SUCCESS; 126179055Sjfv break; 127179055Sjfv } 128171384Sjfv } 129215911Sjfv /* clear value if nothing found */ 130251964Sjfv if (status != IXGBE_SUCCESS) { 131190873Sjfv hw->phy.addr = 0; 132251964Sjfv ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, 133251964Sjfv "Could not identify valid PHY address"); 134251964Sjfv } 135179055Sjfv } else { 136179055Sjfv status = IXGBE_SUCCESS; 137171384Sjfv } 138179055Sjfv 139171384Sjfv return status; 140171384Sjfv} 141171384Sjfv 142171384Sjfv/** 143171384Sjfv * ixgbe_validate_phy_addr - Determines phy address is valid 144171384Sjfv * @hw: pointer to hardware structure 145171384Sjfv * 146171384Sjfv **/ 147171384Sjfvbool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr) 148171384Sjfv{ 149171384Sjfv u16 phy_id = 0; 150171384Sjfv bool valid = FALSE; 151171384Sjfv 152200239Sjfv DEBUGFUNC("ixgbe_validate_phy_addr"); 153200239Sjfv 154171384Sjfv hw->phy.addr = phy_addr; 155179055Sjfv hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 156230775Sjfv IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id); 157171384Sjfv 158171384Sjfv if (phy_id != 0xFFFF && phy_id != 0x0) 159171384Sjfv valid = TRUE; 160171384Sjfv 161171384Sjfv return valid; 162171384Sjfv} 163171384Sjfv 164171384Sjfv/** 165171384Sjfv * ixgbe_get_phy_id - Get the phy type 166171384Sjfv * @hw: pointer to hardware structure 167171384Sjfv * 168171384Sjfv **/ 169171384Sjfvs32 ixgbe_get_phy_id(struct ixgbe_hw *hw) 170171384Sjfv{ 171171384Sjfv u32 status; 172171384Sjfv u16 phy_id_high = 0; 173171384Sjfv u16 phy_id_low = 0; 174171384Sjfv 175200239Sjfv DEBUGFUNC("ixgbe_get_phy_id"); 176200239Sjfv 177179055Sjfv status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 178230775Sjfv IXGBE_MDIO_PMA_PMD_DEV_TYPE, 179230775Sjfv &phy_id_high); 180171384Sjfv 181171384Sjfv if (status == IXGBE_SUCCESS) { 182171384Sjfv hw->phy.id = (u32)(phy_id_high << 16); 183179055Sjfv status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW, 184230775Sjfv IXGBE_MDIO_PMA_PMD_DEV_TYPE, 185230775Sjfv &phy_id_low); 186171384Sjfv hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); 187171384Sjfv hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); 188171384Sjfv } 189171384Sjfv return status; 190171384Sjfv} 191171384Sjfv 192171384Sjfv/** 193171384Sjfv * ixgbe_get_phy_type_from_id - Get the phy type 194171384Sjfv * @hw: pointer to hardware structure 195171384Sjfv * 196171384Sjfv **/ 197171384Sjfvenum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) 198171384Sjfv{ 199171384Sjfv enum ixgbe_phy_type phy_type; 200171384Sjfv 201200239Sjfv DEBUGFUNC("ixgbe_get_phy_type_from_id"); 202200239Sjfv 203171384Sjfv switch (phy_id) { 204179055Sjfv case TN1010_PHY_ID: 205179055Sjfv phy_type = ixgbe_phy_tn; 206179055Sjfv break; 207230775Sjfv case X540_PHY_ID: 208190873Sjfv phy_type = ixgbe_phy_aq; 209190873Sjfv break; 210171384Sjfv case QT2022_PHY_ID: 211171384Sjfv phy_type = ixgbe_phy_qt; 212171384Sjfv break; 213185352Sjfv case ATH_PHY_ID: 214185352Sjfv phy_type = ixgbe_phy_nl; 215185352Sjfv break; 216171384Sjfv default: 217171384Sjfv phy_type = ixgbe_phy_unknown; 218171384Sjfv break; 219171384Sjfv } 220171384Sjfv 221179055Sjfv DEBUGOUT1("phy type found is %d\n", phy_type); 222171384Sjfv return phy_type; 223171384Sjfv} 224171384Sjfv 225171384Sjfv/** 226171384Sjfv * ixgbe_reset_phy_generic - Performs a PHY reset 227171384Sjfv * @hw: pointer to hardware structure 228171384Sjfv **/ 229171384Sjfvs32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 230171384Sjfv{ 231190873Sjfv u32 i; 232190873Sjfv u16 ctrl = 0; 233190873Sjfv s32 status = IXGBE_SUCCESS; 234190873Sjfv 235200239Sjfv DEBUGFUNC("ixgbe_reset_phy_generic"); 236200239Sjfv 237190873Sjfv if (hw->phy.type == ixgbe_phy_unknown) 238190873Sjfv status = ixgbe_identify_phy_generic(hw); 239190873Sjfv 240190873Sjfv if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none) 241190873Sjfv goto out; 242190873Sjfv 243215911Sjfv /* Don't reset PHY if it's shut down due to overtemp. */ 244215911Sjfv if (!hw->phy.reset_if_overtemp && 245215911Sjfv (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw))) 246215911Sjfv goto out; 247215911Sjfv 248171384Sjfv /* 249171384Sjfv * Perform soft PHY reset to the PHY_XS. 250171384Sjfv * This will cause a soft reset to the PHY 251171384Sjfv */ 252190873Sjfv hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 253230775Sjfv IXGBE_MDIO_PHY_XS_DEV_TYPE, 254230775Sjfv IXGBE_MDIO_PHY_XS_RESET); 255190873Sjfv 256205720Sjfv /* 257205720Sjfv * Poll for reset bit to self-clear indicating reset is complete. 258205720Sjfv * Some PHYs could take up to 3 seconds to complete and need about 259205720Sjfv * 1.7 usec delay after the reset is complete. 260205720Sjfv */ 261205720Sjfv for (i = 0; i < 30; i++) { 262205720Sjfv msec_delay(100); 263190873Sjfv hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 264230775Sjfv IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl); 265205720Sjfv if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) { 266205720Sjfv usec_delay(2); 267190873Sjfv break; 268205720Sjfv } 269190873Sjfv } 270190873Sjfv 271190873Sjfv if (ctrl & IXGBE_MDIO_PHY_XS_RESET) { 272190873Sjfv status = IXGBE_ERR_RESET_FAILED; 273251964Sjfv ERROR_REPORT1(IXGBE_ERROR_POLLING, 274251964Sjfv "PHY reset polling failed to complete.\n"); 275190873Sjfv } 276190873Sjfv 277190873Sjfvout: 278190873Sjfv return status; 279171384Sjfv} 280171384Sjfv 281171384Sjfv/** 282251964Sjfv * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without 283251964Sjfv * the SWFW lock 284251964Sjfv * @hw: pointer to hardware structure 285251964Sjfv * @reg_addr: 32 bit address of PHY register to read 286251964Sjfv * @phy_data: Pointer to read data from PHY register 287251964Sjfv **/ 288251964Sjfvs32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 289251964Sjfv u16 *phy_data) 290251964Sjfv{ 291251964Sjfv u32 i, data, command; 292251964Sjfv 293251964Sjfv /* Setup and write the address cycle command */ 294251964Sjfv command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 295251964Sjfv (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 296251964Sjfv (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 297251964Sjfv (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 298251964Sjfv 299251964Sjfv IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 300251964Sjfv 301251964Sjfv /* 302251964Sjfv * Check every 10 usec to see if the address cycle completed. 303251964Sjfv * The MDI Command bit will clear when the operation is 304251964Sjfv * complete 305251964Sjfv */ 306251964Sjfv for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 307251964Sjfv usec_delay(10); 308251964Sjfv 309251964Sjfv command = IXGBE_READ_REG(hw, IXGBE_MSCA); 310251964Sjfv if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 311251964Sjfv break; 312251964Sjfv } 313251964Sjfv 314251964Sjfv 315251964Sjfv if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 316251964Sjfv ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n"); 317251964Sjfv return IXGBE_ERR_PHY; 318251964Sjfv } 319251964Sjfv 320251964Sjfv /* 321251964Sjfv * Address cycle complete, setup and write the read 322251964Sjfv * command 323251964Sjfv */ 324251964Sjfv command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 325251964Sjfv (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 326251964Sjfv (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 327251964Sjfv (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); 328251964Sjfv 329251964Sjfv IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 330251964Sjfv 331251964Sjfv /* 332251964Sjfv * Check every 10 usec to see if the address cycle 333251964Sjfv * completed. The MDI Command bit will clear when the 334251964Sjfv * operation is complete 335251964Sjfv */ 336251964Sjfv for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 337251964Sjfv usec_delay(10); 338251964Sjfv 339251964Sjfv command = IXGBE_READ_REG(hw, IXGBE_MSCA); 340251964Sjfv if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 341251964Sjfv break; 342251964Sjfv } 343251964Sjfv 344251964Sjfv if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 345251964Sjfv ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n"); 346251964Sjfv return IXGBE_ERR_PHY; 347251964Sjfv } 348251964Sjfv 349251964Sjfv /* 350251964Sjfv * Read operation is complete. Get the data 351251964Sjfv * from MSRWD 352251964Sjfv */ 353251964Sjfv data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 354251964Sjfv data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 355251964Sjfv *phy_data = (u16)(data); 356251964Sjfv 357251964Sjfv return IXGBE_SUCCESS; 358251964Sjfv} 359251964Sjfv 360251964Sjfv/** 361171384Sjfv * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register 362251964Sjfv * using the SWFW lock - this function is needed in most cases 363171384Sjfv * @hw: pointer to hardware structure 364171384Sjfv * @reg_addr: 32 bit address of PHY register to read 365171384Sjfv * @phy_data: Pointer to read data from PHY register 366171384Sjfv **/ 367171384Sjfvs32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 368230775Sjfv u32 device_type, u16 *phy_data) 369171384Sjfv{ 370251964Sjfv s32 status; 371171384Sjfv u16 gssr; 372171384Sjfv 373200239Sjfv DEBUGFUNC("ixgbe_read_phy_reg_generic"); 374200239Sjfv 375171384Sjfv if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 376171384Sjfv gssr = IXGBE_GSSR_PHY1_SM; 377171384Sjfv else 378171384Sjfv gssr = IXGBE_GSSR_PHY0_SM; 379171384Sjfv 380251964Sjfv if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) { 381251964Sjfv status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type, 382251964Sjfv phy_data); 383251964Sjfv hw->mac.ops.release_swfw_sync(hw, gssr); 384251964Sjfv } else { 385171384Sjfv status = IXGBE_ERR_SWFW_SYNC; 386251964Sjfv } 387171384Sjfv 388251964Sjfv return status; 389251964Sjfv} 390171384Sjfv 391251964Sjfv/** 392251964Sjfv * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register 393251964Sjfv * without SWFW lock 394251964Sjfv * @hw: pointer to hardware structure 395251964Sjfv * @reg_addr: 32 bit PHY register to write 396251964Sjfv * @device_type: 5 bit device type 397251964Sjfv * @phy_data: Data to write to the PHY register 398251964Sjfv **/ 399251964Sjfvs32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, 400251964Sjfv u32 device_type, u16 phy_data) 401251964Sjfv{ 402251964Sjfv u32 i, command; 403171384Sjfv 404251964Sjfv /* Put the data in the MDI single read and write data register*/ 405251964Sjfv IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); 406171384Sjfv 407251964Sjfv /* Setup and write the address cycle command */ 408251964Sjfv command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 409251964Sjfv (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 410251964Sjfv (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 411251964Sjfv (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 412171384Sjfv 413251964Sjfv IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 414171384Sjfv 415251964Sjfv /* 416251964Sjfv * Check every 10 usec to see if the address cycle completed. 417251964Sjfv * The MDI Command bit will clear when the operation is 418251964Sjfv * complete 419251964Sjfv */ 420251964Sjfv for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 421251964Sjfv usec_delay(10); 422171384Sjfv 423251964Sjfv command = IXGBE_READ_REG(hw, IXGBE_MSCA); 424251964Sjfv if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 425251964Sjfv break; 426251964Sjfv } 427171384Sjfv 428251964Sjfv if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 429251964Sjfv ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n"); 430251964Sjfv return IXGBE_ERR_PHY; 431251964Sjfv } 432171384Sjfv 433251964Sjfv /* 434251964Sjfv * Address cycle complete, setup and write the write 435251964Sjfv * command 436251964Sjfv */ 437251964Sjfv command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 438251964Sjfv (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 439251964Sjfv (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 440251964Sjfv (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); 441171384Sjfv 442251964Sjfv IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 443171384Sjfv 444251964Sjfv /* 445251964Sjfv * Check every 10 usec to see if the address cycle 446251964Sjfv * completed. The MDI Command bit will clear when the 447251964Sjfv * operation is complete 448251964Sjfv */ 449251964Sjfv for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 450251964Sjfv usec_delay(10); 451171384Sjfv 452251964Sjfv command = IXGBE_READ_REG(hw, IXGBE_MSCA); 453251964Sjfv if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 454251964Sjfv break; 455251964Sjfv } 456171384Sjfv 457251964Sjfv if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 458251964Sjfv ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n"); 459251964Sjfv return IXGBE_ERR_PHY; 460171384Sjfv } 461179055Sjfv 462251964Sjfv return IXGBE_SUCCESS; 463171384Sjfv} 464171384Sjfv 465171384Sjfv/** 466171384Sjfv * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register 467251964Sjfv * using SWFW lock- this function is needed in most cases 468171384Sjfv * @hw: pointer to hardware structure 469171384Sjfv * @reg_addr: 32 bit PHY register to write 470171384Sjfv * @device_type: 5 bit device type 471171384Sjfv * @phy_data: Data to write to the PHY register 472171384Sjfv **/ 473171384Sjfvs32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 474230775Sjfv u32 device_type, u16 phy_data) 475171384Sjfv{ 476251964Sjfv s32 status; 477171384Sjfv u16 gssr; 478171384Sjfv 479200239Sjfv DEBUGFUNC("ixgbe_write_phy_reg_generic"); 480200239Sjfv 481171384Sjfv if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 482171384Sjfv gssr = IXGBE_GSSR_PHY1_SM; 483171384Sjfv else 484171384Sjfv gssr = IXGBE_GSSR_PHY0_SM; 485171384Sjfv 486251964Sjfv if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) { 487251964Sjfv status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type, 488251964Sjfv phy_data); 489251964Sjfv hw->mac.ops.release_swfw_sync(hw, gssr); 490251964Sjfv } else { 491171384Sjfv status = IXGBE_ERR_SWFW_SYNC; 492171384Sjfv } 493171384Sjfv 494171384Sjfv return status; 495171384Sjfv} 496171384Sjfv 497171384Sjfv/** 498215911Sjfv * ixgbe_setup_phy_link_generic - Set and restart autoneg 499215911Sjfv * @hw: pointer to hardware structure 500171384Sjfv * 501215911Sjfv * Restart autonegotiation and PHY and waits for completion. 502171384Sjfv **/ 503179055Sjfvs32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 504171384Sjfv{ 505194875Sjfv s32 status = IXGBE_SUCCESS; 506179055Sjfv u32 time_out; 507179055Sjfv u32 max_time_out = 10; 508179055Sjfv u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 509200239Sjfv bool autoneg = FALSE; 510200239Sjfv ixgbe_link_speed speed; 511179055Sjfv 512200239Sjfv DEBUGFUNC("ixgbe_setup_phy_link_generic"); 513179055Sjfv 514200239Sjfv ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 515179055Sjfv 516200239Sjfv if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 517200239Sjfv /* Set or unset auto-negotiation 10G advertisement */ 518200239Sjfv hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 519230775Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 520230775Sjfv &autoneg_reg); 521179055Sjfv 522200239Sjfv autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 523200239Sjfv if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 524200239Sjfv autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 525200239Sjfv 526200239Sjfv hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 527230775Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 528230775Sjfv autoneg_reg); 529200239Sjfv } 530200239Sjfv 531200239Sjfv if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 532200239Sjfv /* Set or unset auto-negotiation 1G advertisement */ 533200239Sjfv hw->phy.ops.read_reg(hw, 534230775Sjfv IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 535230775Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 536230775Sjfv &autoneg_reg); 537200239Sjfv 538200239Sjfv autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE; 539200239Sjfv if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 540200239Sjfv autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE; 541200239Sjfv 542200239Sjfv hw->phy.ops.write_reg(hw, 543230775Sjfv IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 544230775Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 545230775Sjfv autoneg_reg); 546200239Sjfv } 547200239Sjfv 548200239Sjfv if (speed & IXGBE_LINK_SPEED_100_FULL) { 549200239Sjfv /* Set or unset auto-negotiation 100M advertisement */ 550200239Sjfv hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 551230775Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 552230775Sjfv &autoneg_reg); 553200239Sjfv 554230775Sjfv autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE | 555230775Sjfv IXGBE_MII_100BASE_T_ADVERTISE_HALF); 556200239Sjfv if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 557200239Sjfv autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 558200239Sjfv 559200239Sjfv hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 560230775Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 561230775Sjfv autoneg_reg); 562200239Sjfv } 563200239Sjfv 564179055Sjfv /* Restart PHY autonegotiation and wait for completion */ 565179055Sjfv hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 566230775Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 567179055Sjfv 568179055Sjfv autoneg_reg |= IXGBE_MII_RESTART; 569179055Sjfv 570179055Sjfv hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 571230775Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 572179055Sjfv 573179055Sjfv /* Wait for autonegotiation to finish */ 574179055Sjfv for (time_out = 0; time_out < max_time_out; time_out++) { 575179055Sjfv usec_delay(10); 576179055Sjfv /* Restart PHY autonegotiation and wait for completion */ 577179055Sjfv status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 578230775Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 579230775Sjfv &autoneg_reg); 580179055Sjfv 581179055Sjfv autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE; 582230775Sjfv if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) 583179055Sjfv break; 584179055Sjfv } 585179055Sjfv 586200239Sjfv if (time_out == max_time_out) { 587179055Sjfv status = IXGBE_ERR_LINK_SETUP; 588251964Sjfv ERROR_REPORT1(IXGBE_ERROR_POLLING, 589251964Sjfv "PHY autonegotiation time out"); 590200239Sjfv } 591179055Sjfv 592179055Sjfv return status; 593171384Sjfv} 594171384Sjfv 595171384Sjfv/** 596179055Sjfv * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities 597171384Sjfv * @hw: pointer to hardware structure 598179055Sjfv * @speed: new link speed 599179055Sjfv **/ 600179055Sjfvs32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 601230775Sjfv ixgbe_link_speed speed, 602230775Sjfv bool autoneg_wait_to_complete) 603179055Sjfv{ 604247822Sjfv UNREFERENCED_1PARAMETER(autoneg_wait_to_complete); 605179055Sjfv 606200239Sjfv DEBUGFUNC("ixgbe_setup_phy_link_speed_generic"); 607200239Sjfv 608179055Sjfv /* 609179055Sjfv * Clear autoneg_advertised and set new values based on input link 610179055Sjfv * speed. 611179055Sjfv */ 612179055Sjfv hw->phy.autoneg_advertised = 0; 613179055Sjfv 614185352Sjfv if (speed & IXGBE_LINK_SPEED_10GB_FULL) 615179055Sjfv hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 616185352Sjfv 617185352Sjfv if (speed & IXGBE_LINK_SPEED_1GB_FULL) 618179055Sjfv hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 619179055Sjfv 620190873Sjfv if (speed & IXGBE_LINK_SPEED_100_FULL) 621190873Sjfv hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 622190873Sjfv 623179055Sjfv /* Setup link based on the new speed settings */ 624179055Sjfv hw->phy.ops.setup_link(hw); 625179055Sjfv 626179055Sjfv return IXGBE_SUCCESS; 627179055Sjfv} 628179055Sjfv 629179055Sjfv/** 630190873Sjfv * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities 631190873Sjfv * @hw: pointer to hardware structure 632190873Sjfv * @speed: pointer to link speed 633190873Sjfv * @autoneg: boolean auto-negotiation value 634190873Sjfv * 635190873Sjfv * Determines the link capabilities by reading the AUTOC register. 636190873Sjfv **/ 637190873Sjfvs32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 638230775Sjfv ixgbe_link_speed *speed, 639230775Sjfv bool *autoneg) 640190873Sjfv{ 641190873Sjfv s32 status = IXGBE_ERR_LINK_SETUP; 642190873Sjfv u16 speed_ability; 643190873Sjfv 644200239Sjfv DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic"); 645200239Sjfv 646190873Sjfv *speed = 0; 647190873Sjfv *autoneg = TRUE; 648190873Sjfv 649190873Sjfv status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY, 650230775Sjfv IXGBE_MDIO_PMA_PMD_DEV_TYPE, 651230775Sjfv &speed_ability); 652190873Sjfv 653190873Sjfv if (status == IXGBE_SUCCESS) { 654190873Sjfv if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G) 655190873Sjfv *speed |= IXGBE_LINK_SPEED_10GB_FULL; 656190873Sjfv if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G) 657190873Sjfv *speed |= IXGBE_LINK_SPEED_1GB_FULL; 658190873Sjfv if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M) 659190873Sjfv *speed |= IXGBE_LINK_SPEED_100_FULL; 660190873Sjfv } 661190873Sjfv 662190873Sjfv return status; 663190873Sjfv} 664190873Sjfv 665190873Sjfv/** 666179055Sjfv * ixgbe_check_phy_link_tnx - Determine link and speed status 667179055Sjfv * @hw: pointer to hardware structure 668171384Sjfv * 669179055Sjfv * Reads the VS1 register to determine if link is up and the current speed for 670171384Sjfv * the PHY. 671171384Sjfv **/ 672179055Sjfvs32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 673230775Sjfv bool *link_up) 674171384Sjfv{ 675179055Sjfv s32 status = IXGBE_SUCCESS; 676179055Sjfv u32 time_out; 677179055Sjfv u32 max_time_out = 10; 678179055Sjfv u16 phy_link = 0; 679179055Sjfv u16 phy_speed = 0; 680179055Sjfv u16 phy_data = 0; 681179055Sjfv 682200239Sjfv DEBUGFUNC("ixgbe_check_phy_link_tnx"); 683200239Sjfv 684179055Sjfv /* Initialize speed and link to default case */ 685179055Sjfv *link_up = FALSE; 686179055Sjfv *speed = IXGBE_LINK_SPEED_10GB_FULL; 687179055Sjfv 688179055Sjfv /* 689179055Sjfv * Check current speed and link status of the PHY register. 690179055Sjfv * This is a vendor specific register and may have to 691179055Sjfv * be changed for other copper PHYs. 692179055Sjfv */ 693179055Sjfv for (time_out = 0; time_out < max_time_out; time_out++) { 694179055Sjfv usec_delay(10); 695179055Sjfv status = hw->phy.ops.read_reg(hw, 696230775Sjfv IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS, 697230775Sjfv IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 698230775Sjfv &phy_data); 699230775Sjfv phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; 700179055Sjfv phy_speed = phy_data & 701230775Sjfv IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; 702179055Sjfv if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { 703179055Sjfv *link_up = TRUE; 704179055Sjfv if (phy_speed == 705179055Sjfv IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) 706179055Sjfv *speed = IXGBE_LINK_SPEED_1GB_FULL; 707179055Sjfv break; 708179055Sjfv } 709179055Sjfv } 710179055Sjfv 711179055Sjfv return status; 712171384Sjfv} 713171384Sjfv 714171384Sjfv/** 715200239Sjfv * ixgbe_setup_phy_link_tnx - Set and restart autoneg 716200239Sjfv * @hw: pointer to hardware structure 717200239Sjfv * 718200239Sjfv * Restart autonegotiation and PHY and waits for completion. 719200239Sjfv **/ 720200239Sjfvs32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) 721200239Sjfv{ 722200239Sjfv s32 status = IXGBE_SUCCESS; 723200239Sjfv u32 time_out; 724200239Sjfv u32 max_time_out = 10; 725200239Sjfv u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 726200239Sjfv bool autoneg = FALSE; 727200239Sjfv ixgbe_link_speed speed; 728200239Sjfv 729200239Sjfv DEBUGFUNC("ixgbe_setup_phy_link_tnx"); 730200239Sjfv 731200239Sjfv ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 732200239Sjfv 733200239Sjfv if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 734200239Sjfv /* Set or unset auto-negotiation 10G advertisement */ 735200239Sjfv hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 736230775Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 737230775Sjfv &autoneg_reg); 738200239Sjfv 739200239Sjfv autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 740200239Sjfv if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 741200239Sjfv autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 742200239Sjfv 743200239Sjfv hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 744230775Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 745230775Sjfv autoneg_reg); 746200239Sjfv } 747200239Sjfv 748200239Sjfv if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 749200239Sjfv /* Set or unset auto-negotiation 1G advertisement */ 750200239Sjfv hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 751230775Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 752230775Sjfv &autoneg_reg); 753200239Sjfv 754200239Sjfv autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 755200239Sjfv if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 756200239Sjfv autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 757200239Sjfv 758200239Sjfv hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 759230775Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 760230775Sjfv autoneg_reg); 761200239Sjfv } 762200239Sjfv 763200239Sjfv if (speed & IXGBE_LINK_SPEED_100_FULL) { 764200239Sjfv /* Set or unset auto-negotiation 100M advertisement */ 765200239Sjfv hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 766230775Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 767230775Sjfv &autoneg_reg); 768200239Sjfv 769200239Sjfv autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE; 770200239Sjfv if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 771200239Sjfv autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 772200239Sjfv 773200239Sjfv hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 774230775Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 775230775Sjfv autoneg_reg); 776200239Sjfv } 777200239Sjfv 778200239Sjfv /* Restart PHY autonegotiation and wait for completion */ 779200239Sjfv hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 780230775Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 781200239Sjfv 782200239Sjfv autoneg_reg |= IXGBE_MII_RESTART; 783200239Sjfv 784200239Sjfv hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 785230775Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 786200239Sjfv 787200239Sjfv /* Wait for autonegotiation to finish */ 788200239Sjfv for (time_out = 0; time_out < max_time_out; time_out++) { 789200239Sjfv usec_delay(10); 790200239Sjfv /* Restart PHY autonegotiation and wait for completion */ 791200239Sjfv status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 792230775Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 793230775Sjfv &autoneg_reg); 794200239Sjfv 795200239Sjfv autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE; 796230775Sjfv if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) 797200239Sjfv break; 798200239Sjfv } 799200239Sjfv 800200239Sjfv if (time_out == max_time_out) { 801200239Sjfv status = IXGBE_ERR_LINK_SETUP; 802200239Sjfv DEBUGOUT("ixgbe_setup_phy_link_tnx: time out"); 803200239Sjfv } 804200239Sjfv 805200239Sjfv return status; 806200239Sjfv} 807200239Sjfv 808200239Sjfv/** 809179055Sjfv * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version 810171384Sjfv * @hw: pointer to hardware structure 811179055Sjfv * @firmware_version: pointer to the PHY Firmware Version 812171384Sjfv **/ 813179055Sjfvs32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, 814230775Sjfv u16 *firmware_version) 815171384Sjfv{ 816179055Sjfv s32 status = IXGBE_SUCCESS; 817179055Sjfv 818200239Sjfv DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx"); 819200239Sjfv 820179055Sjfv status = hw->phy.ops.read_reg(hw, TNX_FW_REV, 821230775Sjfv IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 822230775Sjfv firmware_version); 823179055Sjfv 824179055Sjfv return status; 825171384Sjfv} 826171384Sjfv 827185352Sjfv/** 828200239Sjfv * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version 829190873Sjfv * @hw: pointer to hardware structure 830190873Sjfv * @firmware_version: pointer to the PHY Firmware Version 831190873Sjfv **/ 832200239Sjfvs32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, 833230775Sjfv u16 *firmware_version) 834190873Sjfv{ 835190873Sjfv s32 status = IXGBE_SUCCESS; 836190873Sjfv 837200239Sjfv DEBUGFUNC("ixgbe_get_phy_firmware_version_generic"); 838200239Sjfv 839190873Sjfv status = hw->phy.ops.read_reg(hw, AQ_FW_REV, 840230775Sjfv IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 841230775Sjfv firmware_version); 842190873Sjfv 843190873Sjfv return status; 844190873Sjfv} 845190873Sjfv 846190873Sjfv/** 847185352Sjfv * ixgbe_reset_phy_nl - Performs a PHY reset 848185352Sjfv * @hw: pointer to hardware structure 849185352Sjfv **/ 850185352Sjfvs32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) 851185352Sjfv{ 852185352Sjfv u16 phy_offset, control, eword, edata, block_crc; 853185352Sjfv bool end_data = FALSE; 854185352Sjfv u16 list_offset, data_offset; 855185352Sjfv u16 phy_data = 0; 856185352Sjfv s32 ret_val = IXGBE_SUCCESS; 857185352Sjfv u32 i; 858185352Sjfv 859200239Sjfv DEBUGFUNC("ixgbe_reset_phy_nl"); 860200239Sjfv 861185352Sjfv hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 862230775Sjfv IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 863185352Sjfv 864185352Sjfv /* reset the PHY and poll for completion */ 865185352Sjfv hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 866230775Sjfv IXGBE_MDIO_PHY_XS_DEV_TYPE, 867230775Sjfv (phy_data | IXGBE_MDIO_PHY_XS_RESET)); 868185352Sjfv 869185352Sjfv for (i = 0; i < 100; i++) { 870185352Sjfv hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 871230775Sjfv IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 872185352Sjfv if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0) 873185352Sjfv break; 874185352Sjfv msec_delay(10); 875185352Sjfv } 876185352Sjfv 877185352Sjfv if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) { 878185352Sjfv DEBUGOUT("PHY reset did not complete.\n"); 879185352Sjfv ret_val = IXGBE_ERR_PHY; 880185352Sjfv goto out; 881185352Sjfv } 882185352Sjfv 883185352Sjfv /* Get init offsets */ 884185352Sjfv ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 885230775Sjfv &data_offset); 886185352Sjfv if (ret_val != IXGBE_SUCCESS) 887185352Sjfv goto out; 888185352Sjfv 889185352Sjfv ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); 890185352Sjfv data_offset++; 891185352Sjfv while (!end_data) { 892185352Sjfv /* 893185352Sjfv * Read control word from PHY init contents offset 894185352Sjfv */ 895185352Sjfv ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); 896251964Sjfv if (ret_val) 897251964Sjfv goto err_eeprom; 898185352Sjfv control = (eword & IXGBE_CONTROL_MASK_NL) >> 899230775Sjfv IXGBE_CONTROL_SHIFT_NL; 900185352Sjfv edata = eword & IXGBE_DATA_MASK_NL; 901185352Sjfv switch (control) { 902185352Sjfv case IXGBE_DELAY_NL: 903185352Sjfv data_offset++; 904185352Sjfv DEBUGOUT1("DELAY: %d MS\n", edata); 905185352Sjfv msec_delay(edata); 906185352Sjfv break; 907185352Sjfv case IXGBE_DATA_NL: 908230775Sjfv DEBUGOUT("DATA:\n"); 909185352Sjfv data_offset++; 910251964Sjfv ret_val = hw->eeprom.ops.read(hw, data_offset, 911251964Sjfv &phy_offset); 912251964Sjfv if (ret_val) 913251964Sjfv goto err_eeprom; 914251964Sjfv data_offset++; 915185352Sjfv for (i = 0; i < edata; i++) { 916251964Sjfv ret_val = hw->eeprom.ops.read(hw, data_offset, 917251964Sjfv &eword); 918251964Sjfv if (ret_val) 919251964Sjfv goto err_eeprom; 920185352Sjfv hw->phy.ops.write_reg(hw, phy_offset, 921230775Sjfv IXGBE_TWINAX_DEV, eword); 922185352Sjfv DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword, 923230775Sjfv phy_offset); 924185352Sjfv data_offset++; 925185352Sjfv phy_offset++; 926185352Sjfv } 927185352Sjfv break; 928185352Sjfv case IXGBE_CONTROL_NL: 929185352Sjfv data_offset++; 930230775Sjfv DEBUGOUT("CONTROL:\n"); 931185352Sjfv if (edata == IXGBE_CONTROL_EOL_NL) { 932185352Sjfv DEBUGOUT("EOL\n"); 933185352Sjfv end_data = TRUE; 934185352Sjfv } else if (edata == IXGBE_CONTROL_SOL_NL) { 935185352Sjfv DEBUGOUT("SOL\n"); 936185352Sjfv } else { 937185352Sjfv DEBUGOUT("Bad control value\n"); 938185352Sjfv ret_val = IXGBE_ERR_PHY; 939185352Sjfv goto out; 940185352Sjfv } 941185352Sjfv break; 942185352Sjfv default: 943185352Sjfv DEBUGOUT("Bad control type\n"); 944185352Sjfv ret_val = IXGBE_ERR_PHY; 945185352Sjfv goto out; 946185352Sjfv } 947185352Sjfv } 948185352Sjfv 949185352Sjfvout: 950185352Sjfv return ret_val; 951251964Sjfv 952251964Sjfverr_eeprom: 953251964Sjfv ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 954251964Sjfv "eeprom read at offset %d failed", data_offset); 955251964Sjfv return IXGBE_ERR_PHY; 956185352Sjfv} 957185352Sjfv 958185352Sjfv/** 959230775Sjfv * ixgbe_identify_module_generic - Identifies module type 960230775Sjfv * @hw: pointer to hardware structure 961230775Sjfv * 962230775Sjfv * Determines HW type and calls appropriate function. 963230775Sjfv **/ 964230775Sjfvs32 ixgbe_identify_module_generic(struct ixgbe_hw *hw) 965230775Sjfv{ 966230775Sjfv s32 status = IXGBE_ERR_SFP_NOT_PRESENT; 967230775Sjfv 968230775Sjfv DEBUGFUNC("ixgbe_identify_module_generic"); 969230775Sjfv 970230775Sjfv switch (hw->mac.ops.get_media_type(hw)) { 971230775Sjfv case ixgbe_media_type_fiber: 972230775Sjfv status = ixgbe_identify_sfp_module_generic(hw); 973230775Sjfv break; 974230775Sjfv 975230775Sjfv 976230775Sjfv default: 977230775Sjfv hw->phy.sfp_type = ixgbe_sfp_type_not_present; 978230775Sjfv status = IXGBE_ERR_SFP_NOT_PRESENT; 979230775Sjfv break; 980230775Sjfv } 981230775Sjfv 982230775Sjfv return status; 983230775Sjfv} 984230775Sjfv 985230775Sjfv/** 986185352Sjfv * ixgbe_identify_sfp_module_generic - Identifies SFP modules 987185352Sjfv * @hw: pointer to hardware structure 988185352Sjfv * 989185352Sjfv * Searches for and identifies the SFP module and assigns appropriate PHY type. 990185352Sjfv **/ 991185352Sjfvs32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) 992185352Sjfv{ 993185352Sjfv s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 994185352Sjfv u32 vendor_oui = 0; 995190873Sjfv enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 996185352Sjfv u8 identifier = 0; 997185352Sjfv u8 comp_codes_1g = 0; 998185352Sjfv u8 comp_codes_10g = 0; 999190873Sjfv u8 oui_bytes[3] = {0, 0, 0}; 1000194875Sjfv u8 cable_tech = 0; 1001205720Sjfv u8 cable_spec = 0; 1002190873Sjfv u16 enforce_sfp = 0; 1003185352Sjfv 1004200239Sjfv DEBUGFUNC("ixgbe_identify_sfp_module_generic"); 1005200239Sjfv 1006194875Sjfv if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) { 1007194875Sjfv hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1008194875Sjfv status = IXGBE_ERR_SFP_NOT_PRESENT; 1009194875Sjfv goto out; 1010215911Sjfv } 1011194875Sjfv 1012215911Sjfv status = hw->phy.ops.read_i2c_eeprom(hw, 1013230775Sjfv IXGBE_SFF_IDENTIFIER, 1014230775Sjfv &identifier); 1015185352Sjfv 1016247822Sjfv if (status != IXGBE_SUCCESS) 1017215911Sjfv goto err_read_i2c_eeprom; 1018185352Sjfv 1019190873Sjfv /* LAN ID is needed for sfp_type determination */ 1020190873Sjfv hw->mac.ops.set_lan_id(hw); 1021190873Sjfv 1022194875Sjfv if (identifier != IXGBE_SFF_IDENTIFIER_SFP) { 1023194875Sjfv hw->phy.type = ixgbe_phy_sfp_unsupported; 1024194875Sjfv status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1025194875Sjfv } else { 1026215911Sjfv status = hw->phy.ops.read_i2c_eeprom(hw, 1027230775Sjfv IXGBE_SFF_1GBE_COMP_CODES, 1028230775Sjfv &comp_codes_1g); 1029185352Sjfv 1030247822Sjfv if (status != IXGBE_SUCCESS) 1031215911Sjfv goto err_read_i2c_eeprom; 1032215911Sjfv 1033215911Sjfv status = hw->phy.ops.read_i2c_eeprom(hw, 1034230775Sjfv IXGBE_SFF_10GBE_COMP_CODES, 1035230775Sjfv &comp_codes_10g); 1036215911Sjfv 1037247822Sjfv if (status != IXGBE_SUCCESS) 1038215911Sjfv goto err_read_i2c_eeprom; 1039215911Sjfv status = hw->phy.ops.read_i2c_eeprom(hw, 1040230775Sjfv IXGBE_SFF_CABLE_TECHNOLOGY, 1041230775Sjfv &cable_tech); 1042215911Sjfv 1043247822Sjfv if (status != IXGBE_SUCCESS) 1044215911Sjfv goto err_read_i2c_eeprom; 1045215911Sjfv 1046185352Sjfv /* ID Module 1047185352Sjfv * ========= 1048185352Sjfv * 0 SFP_DA_CU 1049185352Sjfv * 1 SFP_SR 1050185352Sjfv * 2 SFP_LR 1051190873Sjfv * 3 SFP_DA_CORE0 - 82599-specific 1052190873Sjfv * 4 SFP_DA_CORE1 - 82599-specific 1053190873Sjfv * 5 SFP_SR/LR_CORE0 - 82599-specific 1054190873Sjfv * 6 SFP_SR/LR_CORE1 - 82599-specific 1055205720Sjfv * 7 SFP_act_lmt_DA_CORE0 - 82599-specific 1056205720Sjfv * 8 SFP_act_lmt_DA_CORE1 - 82599-specific 1057215911Sjfv * 9 SFP_1g_cu_CORE0 - 82599-specific 1058215911Sjfv * 10 SFP_1g_cu_CORE1 - 82599-specific 1059238149Sjfv * 11 SFP_1g_sx_CORE0 - 82599-specific 1060238149Sjfv * 12 SFP_1g_sx_CORE1 - 82599-specific 1061185352Sjfv */ 1062190873Sjfv if (hw->mac.type == ixgbe_mac_82598EB) { 1063194875Sjfv if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1064190873Sjfv hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 1065190873Sjfv else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1066190873Sjfv hw->phy.sfp_type = ixgbe_sfp_type_sr; 1067190873Sjfv else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1068190873Sjfv hw->phy.sfp_type = ixgbe_sfp_type_lr; 1069190873Sjfv else 1070190873Sjfv hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1071190873Sjfv } else if (hw->mac.type == ixgbe_mac_82599EB) { 1072205720Sjfv if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) { 1073190873Sjfv if (hw->bus.lan_id == 0) 1074190873Sjfv hw->phy.sfp_type = 1075230775Sjfv ixgbe_sfp_type_da_cu_core0; 1076190873Sjfv else 1077190873Sjfv hw->phy.sfp_type = 1078230775Sjfv ixgbe_sfp_type_da_cu_core1; 1079205720Sjfv } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) { 1080205720Sjfv hw->phy.ops.read_i2c_eeprom( 1081205720Sjfv hw, IXGBE_SFF_CABLE_SPEC_COMP, 1082205720Sjfv &cable_spec); 1083205720Sjfv if (cable_spec & 1084215911Sjfv IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) { 1085205720Sjfv if (hw->bus.lan_id == 0) 1086205720Sjfv hw->phy.sfp_type = 1087205720Sjfv ixgbe_sfp_type_da_act_lmt_core0; 1088205720Sjfv else 1089205720Sjfv hw->phy.sfp_type = 1090205720Sjfv ixgbe_sfp_type_da_act_lmt_core1; 1091215911Sjfv } else { 1092190873Sjfv hw->phy.sfp_type = 1093230775Sjfv ixgbe_sfp_type_unknown; 1094215911Sjfv } 1095205720Sjfv } else if (comp_codes_10g & 1096205720Sjfv (IXGBE_SFF_10GBASESR_CAPABLE | 1097215911Sjfv IXGBE_SFF_10GBASELR_CAPABLE)) { 1098190873Sjfv if (hw->bus.lan_id == 0) 1099190873Sjfv hw->phy.sfp_type = 1100230775Sjfv ixgbe_sfp_type_srlr_core0; 1101190873Sjfv else 1102190873Sjfv hw->phy.sfp_type = 1103230775Sjfv ixgbe_sfp_type_srlr_core1; 1104215911Sjfv } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) { 1105215911Sjfv if (hw->bus.lan_id == 0) 1106215911Sjfv hw->phy.sfp_type = 1107215911Sjfv ixgbe_sfp_type_1g_cu_core0; 1108215911Sjfv else 1109215911Sjfv hw->phy.sfp_type = 1110215911Sjfv ixgbe_sfp_type_1g_cu_core1; 1111238149Sjfv } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) { 1112238149Sjfv if (hw->bus.lan_id == 0) 1113238149Sjfv hw->phy.sfp_type = 1114238149Sjfv ixgbe_sfp_type_1g_sx_core0; 1115238149Sjfv else 1116238149Sjfv hw->phy.sfp_type = 1117238149Sjfv ixgbe_sfp_type_1g_sx_core1; 1118205720Sjfv } else { 1119190873Sjfv hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1120205720Sjfv } 1121190873Sjfv } 1122185352Sjfv 1123190873Sjfv if (hw->phy.sfp_type != stored_sfp_type) 1124190873Sjfv hw->phy.sfp_setup_needed = TRUE; 1125190873Sjfv 1126185352Sjfv /* Determine if the SFP+ PHY is dual speed or not. */ 1127194875Sjfv hw->phy.multispeed_fiber = FALSE; 1128190873Sjfv if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1129190873Sjfv (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1130190873Sjfv ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1131190873Sjfv (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1132185352Sjfv hw->phy.multispeed_fiber = TRUE; 1133200239Sjfv 1134185352Sjfv /* Determine PHY vendor */ 1135190873Sjfv if (hw->phy.type != ixgbe_phy_nl) { 1136185352Sjfv hw->phy.id = identifier; 1137215911Sjfv status = hw->phy.ops.read_i2c_eeprom(hw, 1138230775Sjfv IXGBE_SFF_VENDOR_OUI_BYTE0, 1139230775Sjfv &oui_bytes[0]); 1140215911Sjfv 1141247822Sjfv if (status != IXGBE_SUCCESS) 1142215911Sjfv goto err_read_i2c_eeprom; 1143215911Sjfv 1144215911Sjfv status = hw->phy.ops.read_i2c_eeprom(hw, 1145230775Sjfv IXGBE_SFF_VENDOR_OUI_BYTE1, 1146230775Sjfv &oui_bytes[1]); 1147215911Sjfv 1148247822Sjfv if (status != IXGBE_SUCCESS) 1149215911Sjfv goto err_read_i2c_eeprom; 1150215911Sjfv 1151215911Sjfv status = hw->phy.ops.read_i2c_eeprom(hw, 1152230775Sjfv IXGBE_SFF_VENDOR_OUI_BYTE2, 1153230775Sjfv &oui_bytes[2]); 1154185352Sjfv 1155247822Sjfv if (status != IXGBE_SUCCESS) 1156215911Sjfv goto err_read_i2c_eeprom; 1157215911Sjfv 1158185352Sjfv vendor_oui = 1159215911Sjfv ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1160215911Sjfv (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1161215911Sjfv (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1162185352Sjfv 1163185352Sjfv switch (vendor_oui) { 1164185352Sjfv case IXGBE_SFF_VENDOR_OUI_TYCO: 1165194875Sjfv if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1166205720Sjfv hw->phy.type = 1167230775Sjfv ixgbe_phy_sfp_passive_tyco; 1168185352Sjfv break; 1169185352Sjfv case IXGBE_SFF_VENDOR_OUI_FTL: 1170205720Sjfv if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1171205720Sjfv hw->phy.type = ixgbe_phy_sfp_ftl_active; 1172205720Sjfv else 1173205720Sjfv hw->phy.type = ixgbe_phy_sfp_ftl; 1174185352Sjfv break; 1175185352Sjfv case IXGBE_SFF_VENDOR_OUI_AVAGO: 1176185352Sjfv hw->phy.type = ixgbe_phy_sfp_avago; 1177185352Sjfv break; 1178190873Sjfv case IXGBE_SFF_VENDOR_OUI_INTEL: 1179190873Sjfv hw->phy.type = ixgbe_phy_sfp_intel; 1180190873Sjfv break; 1181185352Sjfv default: 1182194875Sjfv if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1183205720Sjfv hw->phy.type = 1184230775Sjfv ixgbe_phy_sfp_passive_unknown; 1185205720Sjfv else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1186205720Sjfv hw->phy.type = 1187205720Sjfv ixgbe_phy_sfp_active_unknown; 1188185352Sjfv else 1189185352Sjfv hw->phy.type = ixgbe_phy_sfp_unknown; 1190185352Sjfv break; 1191185352Sjfv } 1192185352Sjfv } 1193190873Sjfv 1194205720Sjfv /* Allow any DA cable vendor */ 1195205720Sjfv if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE | 1196205720Sjfv IXGBE_SFF_DA_ACTIVE_CABLE)) { 1197194875Sjfv status = IXGBE_SUCCESS; 1198194875Sjfv goto out; 1199194875Sjfv } 1200194875Sjfv 1201215911Sjfv /* Verify supported 1G SFP modules */ 1202215911Sjfv if (comp_codes_10g == 0 && 1203215911Sjfv !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1204238149Sjfv hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1205251964Sjfv hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1206238149Sjfv hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1207190873Sjfv hw->phy.type = ixgbe_phy_sfp_unsupported; 1208190873Sjfv status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1209190873Sjfv goto out; 1210190873Sjfv } 1211194875Sjfv 1212194875Sjfv /* Anything else 82598-based is supported */ 1213194875Sjfv if (hw->mac.type == ixgbe_mac_82598EB) { 1214190873Sjfv status = IXGBE_SUCCESS; 1215190873Sjfv goto out; 1216190873Sjfv } 1217190873Sjfv 1218190873Sjfv ixgbe_get_device_caps(hw, &enforce_sfp); 1219215911Sjfv if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) && 1220251964Sjfv !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1221251964Sjfv hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1222251964Sjfv hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1223251964Sjfv hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1224190873Sjfv /* Make sure we're a supported PHY type */ 1225190873Sjfv if (hw->phy.type == ixgbe_phy_sfp_intel) { 1226190873Sjfv status = IXGBE_SUCCESS; 1227190873Sjfv } else { 1228247056Sdes if (hw->allow_unsupported_sfp == TRUE) { 1229247056Sdes EWARN(hw, "WARNING: Intel (R) Network " 1230247056Sdes "Connections are quality tested " 1231247056Sdes "using Intel (R) Ethernet Optics." 1232247056Sdes " Using untested modules is not " 1233247056Sdes "supported and may cause unstable" 1234247056Sdes " operation or damage to the " 1235247056Sdes "module or the adapter. Intel " 1236247056Sdes "Corporation is not responsible " 1237247056Sdes "for any harm caused by using " 1238247056Sdes "untested modules.\n", status); 1239247056Sdes status = IXGBE_SUCCESS; 1240247056Sdes } else { 1241247056Sdes DEBUGOUT("SFP+ module not supported\n"); 1242247056Sdes hw->phy.type = 1243247056Sdes ixgbe_phy_sfp_unsupported; 1244247056Sdes status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1245247056Sdes } 1246190873Sjfv } 1247190873Sjfv } else { 1248190873Sjfv status = IXGBE_SUCCESS; 1249190873Sjfv } 1250185352Sjfv } 1251185352Sjfv 1252185352Sjfvout: 1253185352Sjfv return status; 1254215911Sjfv 1255215911Sjfverr_read_i2c_eeprom: 1256215911Sjfv hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1257215911Sjfv if (hw->phy.type != ixgbe_phy_nl) { 1258215911Sjfv hw->phy.id = 0; 1259215911Sjfv hw->phy.type = ixgbe_phy_unknown; 1260215911Sjfv } 1261215911Sjfv return IXGBE_ERR_SFP_NOT_PRESENT; 1262185352Sjfv} 1263185352Sjfv 1264230775Sjfv 1265230775Sjfv 1266185352Sjfv/** 1267185352Sjfv * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence 1268185352Sjfv * @hw: pointer to hardware structure 1269185352Sjfv * @list_offset: offset to the SFP ID list 1270185352Sjfv * @data_offset: offset to the SFP data block 1271185352Sjfv * 1272185352Sjfv * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if 1273185352Sjfv * so it returns the offsets to the phy init sequence block. 1274185352Sjfv **/ 1275185352Sjfvs32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 1276230775Sjfv u16 *list_offset, 1277230775Sjfv u16 *data_offset) 1278185352Sjfv{ 1279185352Sjfv u16 sfp_id; 1280205720Sjfv u16 sfp_type = hw->phy.sfp_type; 1281185352Sjfv 1282200239Sjfv DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets"); 1283200239Sjfv 1284185352Sjfv if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 1285185352Sjfv return IXGBE_ERR_SFP_NOT_SUPPORTED; 1286185352Sjfv 1287185352Sjfv if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1288185352Sjfv return IXGBE_ERR_SFP_NOT_PRESENT; 1289185352Sjfv 1290185352Sjfv if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && 1291185352Sjfv (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) 1292185352Sjfv return IXGBE_ERR_SFP_NOT_SUPPORTED; 1293185352Sjfv 1294215911Sjfv /* 1295215911Sjfv * Limiting active cables and 1G Phys must be initialized as 1296215911Sjfv * SR modules 1297215911Sjfv */ 1298215911Sjfv if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 || 1299238149Sjfv sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1300238149Sjfv sfp_type == ixgbe_sfp_type_1g_sx_core0) 1301205720Sjfv sfp_type = ixgbe_sfp_type_srlr_core0; 1302215911Sjfv else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 || 1303238149Sjfv sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1304238149Sjfv sfp_type == ixgbe_sfp_type_1g_sx_core1) 1305205720Sjfv sfp_type = ixgbe_sfp_type_srlr_core1; 1306205720Sjfv 1307185352Sjfv /* Read offset to PHY init contents */ 1308251964Sjfv if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) { 1309251964Sjfv ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1310251964Sjfv "eeprom read at offset %d failed", 1311251964Sjfv IXGBE_PHY_INIT_OFFSET_NL); 1312251964Sjfv return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1313251964Sjfv } 1314185352Sjfv 1315185352Sjfv if ((!*list_offset) || (*list_offset == 0xFFFF)) 1316190873Sjfv return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1317185352Sjfv 1318185352Sjfv /* Shift offset to first ID word */ 1319185352Sjfv (*list_offset)++; 1320185352Sjfv 1321185352Sjfv /* 1322185352Sjfv * Find the matching SFP ID in the EEPROM 1323185352Sjfv * and program the init sequence 1324185352Sjfv */ 1325251964Sjfv if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1326251964Sjfv goto err_phy; 1327185352Sjfv 1328185352Sjfv while (sfp_id != IXGBE_PHY_INIT_END_NL) { 1329205720Sjfv if (sfp_id == sfp_type) { 1330185352Sjfv (*list_offset)++; 1331251964Sjfv if (hw->eeprom.ops.read(hw, *list_offset, data_offset)) 1332251964Sjfv goto err_phy; 1333185352Sjfv if ((!*data_offset) || (*data_offset == 0xFFFF)) { 1334185352Sjfv DEBUGOUT("SFP+ module not supported\n"); 1335185352Sjfv return IXGBE_ERR_SFP_NOT_SUPPORTED; 1336185352Sjfv } else { 1337185352Sjfv break; 1338185352Sjfv } 1339185352Sjfv } else { 1340185352Sjfv (*list_offset) += 2; 1341185352Sjfv if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1342251964Sjfv goto err_phy; 1343185352Sjfv } 1344185352Sjfv } 1345185352Sjfv 1346185352Sjfv if (sfp_id == IXGBE_PHY_INIT_END_NL) { 1347185352Sjfv DEBUGOUT("No matching SFP+ module found\n"); 1348185352Sjfv return IXGBE_ERR_SFP_NOT_SUPPORTED; 1349185352Sjfv } 1350185352Sjfv 1351185352Sjfv return IXGBE_SUCCESS; 1352251964Sjfv 1353251964Sjfverr_phy: 1354251964Sjfv ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1355251964Sjfv "eeprom read at offset %d failed", *list_offset); 1356251964Sjfv return IXGBE_ERR_PHY; 1357185352Sjfv} 1358185352Sjfv 1359190873Sjfv/** 1360190873Sjfv * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface 1361190873Sjfv * @hw: pointer to hardware structure 1362190873Sjfv * @byte_offset: EEPROM byte offset to read 1363190873Sjfv * @eeprom_data: value read 1364190873Sjfv * 1365190873Sjfv * Performs byte read operation to SFP module's EEPROM over I2C interface. 1366190873Sjfv **/ 1367190873Sjfvs32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1368230775Sjfv u8 *eeprom_data) 1369190873Sjfv{ 1370190873Sjfv DEBUGFUNC("ixgbe_read_i2c_eeprom_generic"); 1371190873Sjfv 1372190873Sjfv return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1373230775Sjfv IXGBE_I2C_EEPROM_DEV_ADDR, 1374230775Sjfv eeprom_data); 1375190873Sjfv} 1376190873Sjfv 1377190873Sjfv/** 1378247822Sjfv * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface 1379247822Sjfv * @hw: pointer to hardware structure 1380247822Sjfv * @byte_offset: byte offset at address 0xA2 1381247822Sjfv * @eeprom_data: value read 1382247822Sjfv * 1383247822Sjfv * Performs byte read operation to SFP module's SFF-8472 data over I2C 1384247822Sjfv **/ 1385247822Sjfvstatic s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 1386247822Sjfv u8 *sff8472_data) 1387247822Sjfv{ 1388247822Sjfv return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1389247822Sjfv IXGBE_I2C_EEPROM_DEV_ADDR2, 1390247822Sjfv sff8472_data); 1391247822Sjfv} 1392247822Sjfv 1393247822Sjfv/** 1394190873Sjfv * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface 1395190873Sjfv * @hw: pointer to hardware structure 1396190873Sjfv * @byte_offset: EEPROM byte offset to write 1397190873Sjfv * @eeprom_data: value to write 1398190873Sjfv * 1399190873Sjfv * Performs byte write operation to SFP module's EEPROM over I2C interface. 1400190873Sjfv **/ 1401190873Sjfvs32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1402230775Sjfv u8 eeprom_data) 1403190873Sjfv{ 1404190873Sjfv DEBUGFUNC("ixgbe_write_i2c_eeprom_generic"); 1405190873Sjfv 1406190873Sjfv return hw->phy.ops.write_i2c_byte(hw, byte_offset, 1407230775Sjfv IXGBE_I2C_EEPROM_DEV_ADDR, 1408230775Sjfv eeprom_data); 1409190873Sjfv} 1410190873Sjfv 1411190873Sjfv/** 1412190873Sjfv * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C 1413190873Sjfv * @hw: pointer to hardware structure 1414190873Sjfv * @byte_offset: byte offset to read 1415190873Sjfv * @data: value read 1416190873Sjfv * 1417190873Sjfv * Performs byte read operation to SFP module's EEPROM over I2C interface at 1418230775Sjfv * a specified device address. 1419190873Sjfv **/ 1420190873Sjfvs32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 1421230775Sjfv u8 dev_addr, u8 *data) 1422190873Sjfv{ 1423190873Sjfv s32 status = IXGBE_SUCCESS; 1424194875Sjfv u32 max_retry = 10; 1425190873Sjfv u32 retry = 0; 1426190873Sjfv u16 swfw_mask = 0; 1427190873Sjfv bool nack = 1; 1428230775Sjfv *data = 0; 1429190873Sjfv 1430190873Sjfv DEBUGFUNC("ixgbe_read_i2c_byte_generic"); 1431190873Sjfv 1432190873Sjfv if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 1433190873Sjfv swfw_mask = IXGBE_GSSR_PHY1_SM; 1434190873Sjfv else 1435190873Sjfv swfw_mask = IXGBE_GSSR_PHY0_SM; 1436190873Sjfv 1437190873Sjfv do { 1438230775Sjfv if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) 1439230775Sjfv != IXGBE_SUCCESS) { 1440194875Sjfv status = IXGBE_ERR_SWFW_SYNC; 1441194875Sjfv goto read_byte_out; 1442194875Sjfv } 1443194875Sjfv 1444190873Sjfv ixgbe_i2c_start(hw); 1445190873Sjfv 1446190873Sjfv /* Device Address and write indication */ 1447190873Sjfv status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 1448190873Sjfv if (status != IXGBE_SUCCESS) 1449190873Sjfv goto fail; 1450190873Sjfv 1451190873Sjfv status = ixgbe_get_i2c_ack(hw); 1452190873Sjfv if (status != IXGBE_SUCCESS) 1453190873Sjfv goto fail; 1454190873Sjfv 1455190873Sjfv status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 1456190873Sjfv if (status != IXGBE_SUCCESS) 1457190873Sjfv goto fail; 1458190873Sjfv 1459190873Sjfv status = ixgbe_get_i2c_ack(hw); 1460190873Sjfv if (status != IXGBE_SUCCESS) 1461190873Sjfv goto fail; 1462190873Sjfv 1463190873Sjfv ixgbe_i2c_start(hw); 1464190873Sjfv 1465190873Sjfv /* Device Address and read indication */ 1466190873Sjfv status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 1467190873Sjfv if (status != IXGBE_SUCCESS) 1468190873Sjfv goto fail; 1469190873Sjfv 1470190873Sjfv status = ixgbe_get_i2c_ack(hw); 1471190873Sjfv if (status != IXGBE_SUCCESS) 1472190873Sjfv goto fail; 1473190873Sjfv 1474190873Sjfv status = ixgbe_clock_in_i2c_byte(hw, data); 1475190873Sjfv if (status != IXGBE_SUCCESS) 1476190873Sjfv goto fail; 1477190873Sjfv 1478190873Sjfv status = ixgbe_clock_out_i2c_bit(hw, nack); 1479190873Sjfv if (status != IXGBE_SUCCESS) 1480190873Sjfv goto fail; 1481190873Sjfv 1482190873Sjfv ixgbe_i2c_stop(hw); 1483190873Sjfv break; 1484190873Sjfv 1485190873Sjfvfail: 1486247822Sjfv ixgbe_i2c_bus_clear(hw); 1487230775Sjfv hw->mac.ops.release_swfw_sync(hw, swfw_mask); 1488194875Sjfv msec_delay(100); 1489190873Sjfv retry++; 1490190873Sjfv if (retry < max_retry) 1491190873Sjfv DEBUGOUT("I2C byte read error - Retrying.\n"); 1492190873Sjfv else 1493190873Sjfv DEBUGOUT("I2C byte read error.\n"); 1494190873Sjfv 1495190873Sjfv } while (retry < max_retry); 1496190873Sjfv 1497230775Sjfv hw->mac.ops.release_swfw_sync(hw, swfw_mask); 1498190873Sjfv 1499190873Sjfvread_byte_out: 1500190873Sjfv return status; 1501190873Sjfv} 1502190873Sjfv 1503190873Sjfv/** 1504190873Sjfv * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C 1505190873Sjfv * @hw: pointer to hardware structure 1506190873Sjfv * @byte_offset: byte offset to write 1507190873Sjfv * @data: value to write 1508190873Sjfv * 1509190873Sjfv * Performs byte write operation to SFP module's EEPROM over I2C interface at 1510190873Sjfv * a specified device address. 1511190873Sjfv **/ 1512190873Sjfvs32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 1513230775Sjfv u8 dev_addr, u8 data) 1514190873Sjfv{ 1515190873Sjfv s32 status = IXGBE_SUCCESS; 1516190873Sjfv u32 max_retry = 1; 1517190873Sjfv u32 retry = 0; 1518190873Sjfv u16 swfw_mask = 0; 1519190873Sjfv 1520190873Sjfv DEBUGFUNC("ixgbe_write_i2c_byte_generic"); 1521190873Sjfv 1522190873Sjfv if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) 1523190873Sjfv swfw_mask = IXGBE_GSSR_PHY1_SM; 1524190873Sjfv else 1525190873Sjfv swfw_mask = IXGBE_GSSR_PHY0_SM; 1526190873Sjfv 1527230775Sjfv if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) { 1528190873Sjfv status = IXGBE_ERR_SWFW_SYNC; 1529190873Sjfv goto write_byte_out; 1530190873Sjfv } 1531190873Sjfv 1532190873Sjfv do { 1533190873Sjfv ixgbe_i2c_start(hw); 1534190873Sjfv 1535190873Sjfv status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 1536190873Sjfv if (status != IXGBE_SUCCESS) 1537190873Sjfv goto fail; 1538190873Sjfv 1539190873Sjfv status = ixgbe_get_i2c_ack(hw); 1540190873Sjfv if (status != IXGBE_SUCCESS) 1541190873Sjfv goto fail; 1542190873Sjfv 1543190873Sjfv status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 1544190873Sjfv if (status != IXGBE_SUCCESS) 1545190873Sjfv goto fail; 1546190873Sjfv 1547190873Sjfv status = ixgbe_get_i2c_ack(hw); 1548190873Sjfv if (status != IXGBE_SUCCESS) 1549190873Sjfv goto fail; 1550190873Sjfv 1551190873Sjfv status = ixgbe_clock_out_i2c_byte(hw, data); 1552190873Sjfv if (status != IXGBE_SUCCESS) 1553190873Sjfv goto fail; 1554190873Sjfv 1555190873Sjfv status = ixgbe_get_i2c_ack(hw); 1556190873Sjfv if (status != IXGBE_SUCCESS) 1557190873Sjfv goto fail; 1558190873Sjfv 1559190873Sjfv ixgbe_i2c_stop(hw); 1560190873Sjfv break; 1561190873Sjfv 1562190873Sjfvfail: 1563190873Sjfv ixgbe_i2c_bus_clear(hw); 1564190873Sjfv retry++; 1565190873Sjfv if (retry < max_retry) 1566190873Sjfv DEBUGOUT("I2C byte write error - Retrying.\n"); 1567190873Sjfv else 1568190873Sjfv DEBUGOUT("I2C byte write error.\n"); 1569190873Sjfv } while (retry < max_retry); 1570190873Sjfv 1571230775Sjfv hw->mac.ops.release_swfw_sync(hw, swfw_mask); 1572190873Sjfv 1573190873Sjfvwrite_byte_out: 1574190873Sjfv return status; 1575190873Sjfv} 1576190873Sjfv 1577190873Sjfv/** 1578190873Sjfv * ixgbe_i2c_start - Sets I2C start condition 1579190873Sjfv * @hw: pointer to hardware structure 1580190873Sjfv * 1581190873Sjfv * Sets I2C start condition (High -> Low on SDA while SCL is High) 1582190873Sjfv **/ 1583190873Sjfvstatic void ixgbe_i2c_start(struct ixgbe_hw *hw) 1584190873Sjfv{ 1585190873Sjfv u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1586190873Sjfv 1587190873Sjfv DEBUGFUNC("ixgbe_i2c_start"); 1588190873Sjfv 1589190873Sjfv /* Start condition must begin with data and clock high */ 1590190873Sjfv ixgbe_set_i2c_data(hw, &i2cctl, 1); 1591190873Sjfv ixgbe_raise_i2c_clk(hw, &i2cctl); 1592190873Sjfv 1593190873Sjfv /* Setup time for start condition (4.7us) */ 1594190873Sjfv usec_delay(IXGBE_I2C_T_SU_STA); 1595190873Sjfv 1596190873Sjfv ixgbe_set_i2c_data(hw, &i2cctl, 0); 1597190873Sjfv 1598190873Sjfv /* Hold time for start condition (4us) */ 1599190873Sjfv usec_delay(IXGBE_I2C_T_HD_STA); 1600190873Sjfv 1601190873Sjfv ixgbe_lower_i2c_clk(hw, &i2cctl); 1602190873Sjfv 1603190873Sjfv /* Minimum low period of clock is 4.7 us */ 1604190873Sjfv usec_delay(IXGBE_I2C_T_LOW); 1605190873Sjfv 1606190873Sjfv} 1607190873Sjfv 1608190873Sjfv/** 1609190873Sjfv * ixgbe_i2c_stop - Sets I2C stop condition 1610190873Sjfv * @hw: pointer to hardware structure 1611190873Sjfv * 1612190873Sjfv * Sets I2C stop condition (Low -> High on SDA while SCL is High) 1613190873Sjfv **/ 1614190873Sjfvstatic void ixgbe_i2c_stop(struct ixgbe_hw *hw) 1615190873Sjfv{ 1616190873Sjfv u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1617190873Sjfv 1618190873Sjfv DEBUGFUNC("ixgbe_i2c_stop"); 1619190873Sjfv 1620190873Sjfv /* Stop condition must begin with data low and clock high */ 1621190873Sjfv ixgbe_set_i2c_data(hw, &i2cctl, 0); 1622190873Sjfv ixgbe_raise_i2c_clk(hw, &i2cctl); 1623190873Sjfv 1624190873Sjfv /* Setup time for stop condition (4us) */ 1625190873Sjfv usec_delay(IXGBE_I2C_T_SU_STO); 1626190873Sjfv 1627190873Sjfv ixgbe_set_i2c_data(hw, &i2cctl, 1); 1628190873Sjfv 1629190873Sjfv /* bus free time between stop and start (4.7us)*/ 1630190873Sjfv usec_delay(IXGBE_I2C_T_BUF); 1631190873Sjfv} 1632190873Sjfv 1633190873Sjfv/** 1634190873Sjfv * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C 1635190873Sjfv * @hw: pointer to hardware structure 1636190873Sjfv * @data: data byte to clock in 1637190873Sjfv * 1638190873Sjfv * Clocks in one byte data via I2C data/clock 1639190873Sjfv **/ 1640190873Sjfvstatic s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data) 1641190873Sjfv{ 1642190873Sjfv s32 i; 1643190873Sjfv bool bit = 0; 1644190873Sjfv 1645190873Sjfv DEBUGFUNC("ixgbe_clock_in_i2c_byte"); 1646190873Sjfv 1647190873Sjfv for (i = 7; i >= 0; i--) { 1648230775Sjfv ixgbe_clock_in_i2c_bit(hw, &bit); 1649215911Sjfv *data |= bit << i; 1650190873Sjfv } 1651190873Sjfv 1652230775Sjfv return IXGBE_SUCCESS; 1653190873Sjfv} 1654190873Sjfv 1655190873Sjfv/** 1656190873Sjfv * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C 1657190873Sjfv * @hw: pointer to hardware structure 1658190873Sjfv * @data: data byte clocked out 1659190873Sjfv * 1660190873Sjfv * Clocks out one byte data via I2C data/clock 1661190873Sjfv **/ 1662190873Sjfvstatic s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data) 1663190873Sjfv{ 1664190873Sjfv s32 status = IXGBE_SUCCESS; 1665190873Sjfv s32 i; 1666190873Sjfv u32 i2cctl; 1667190873Sjfv bool bit = 0; 1668190873Sjfv 1669190873Sjfv DEBUGFUNC("ixgbe_clock_out_i2c_byte"); 1670190873Sjfv 1671190873Sjfv for (i = 7; i >= 0; i--) { 1672190873Sjfv bit = (data >> i) & 0x1; 1673190873Sjfv status = ixgbe_clock_out_i2c_bit(hw, bit); 1674190873Sjfv 1675190873Sjfv if (status != IXGBE_SUCCESS) 1676190873Sjfv break; 1677190873Sjfv } 1678190873Sjfv 1679190873Sjfv /* Release SDA line (set high) */ 1680190873Sjfv i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1681190873Sjfv i2cctl |= IXGBE_I2C_DATA_OUT; 1682190873Sjfv IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl); 1683230775Sjfv IXGBE_WRITE_FLUSH(hw); 1684190873Sjfv 1685190873Sjfv return status; 1686190873Sjfv} 1687190873Sjfv 1688190873Sjfv/** 1689190873Sjfv * ixgbe_get_i2c_ack - Polls for I2C ACK 1690190873Sjfv * @hw: pointer to hardware structure 1691190873Sjfv * 1692190873Sjfv * Clocks in/out one bit via I2C data/clock 1693190873Sjfv **/ 1694190873Sjfvstatic s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw) 1695190873Sjfv{ 1696230775Sjfv s32 status = IXGBE_SUCCESS; 1697190873Sjfv u32 i = 0; 1698190873Sjfv u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1699190873Sjfv u32 timeout = 10; 1700190873Sjfv bool ack = 1; 1701190873Sjfv 1702190873Sjfv DEBUGFUNC("ixgbe_get_i2c_ack"); 1703190873Sjfv 1704230775Sjfv ixgbe_raise_i2c_clk(hw, &i2cctl); 1705190873Sjfv 1706190873Sjfv 1707190873Sjfv /* Minimum high period of clock is 4us */ 1708190873Sjfv usec_delay(IXGBE_I2C_T_HIGH); 1709190873Sjfv 1710190873Sjfv /* Poll for ACK. Note that ACK in I2C spec is 1711190873Sjfv * transition from 1 to 0 */ 1712190873Sjfv for (i = 0; i < timeout; i++) { 1713190873Sjfv i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1714190873Sjfv ack = ixgbe_get_i2c_data(&i2cctl); 1715190873Sjfv 1716190873Sjfv usec_delay(1); 1717190873Sjfv if (ack == 0) 1718190873Sjfv break; 1719190873Sjfv } 1720190873Sjfv 1721190873Sjfv if (ack == 1) { 1722251964Sjfv ERROR_REPORT1(IXGBE_ERROR_POLLING, 1723251964Sjfv "I2C ack was not received.\n"); 1724190873Sjfv status = IXGBE_ERR_I2C; 1725190873Sjfv } 1726190873Sjfv 1727190873Sjfv ixgbe_lower_i2c_clk(hw, &i2cctl); 1728190873Sjfv 1729190873Sjfv /* Minimum low period of clock is 4.7 us */ 1730190873Sjfv usec_delay(IXGBE_I2C_T_LOW); 1731190873Sjfv 1732190873Sjfv return status; 1733190873Sjfv} 1734190873Sjfv 1735190873Sjfv/** 1736190873Sjfv * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 1737190873Sjfv * @hw: pointer to hardware structure 1738190873Sjfv * @data: read data value 1739190873Sjfv * 1740190873Sjfv * Clocks in one bit via I2C data/clock 1741190873Sjfv **/ 1742190873Sjfvstatic s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data) 1743190873Sjfv{ 1744190873Sjfv u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1745190873Sjfv 1746200239Sjfv DEBUGFUNC("ixgbe_clock_in_i2c_bit"); 1747200239Sjfv 1748230775Sjfv ixgbe_raise_i2c_clk(hw, &i2cctl); 1749190873Sjfv 1750190873Sjfv /* Minimum high period of clock is 4us */ 1751190873Sjfv usec_delay(IXGBE_I2C_T_HIGH); 1752190873Sjfv 1753190873Sjfv i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1754190873Sjfv *data = ixgbe_get_i2c_data(&i2cctl); 1755190873Sjfv 1756190873Sjfv ixgbe_lower_i2c_clk(hw, &i2cctl); 1757190873Sjfv 1758190873Sjfv /* Minimum low period of clock is 4.7 us */ 1759190873Sjfv usec_delay(IXGBE_I2C_T_LOW); 1760190873Sjfv 1761230775Sjfv return IXGBE_SUCCESS; 1762190873Sjfv} 1763190873Sjfv 1764190873Sjfv/** 1765190873Sjfv * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 1766190873Sjfv * @hw: pointer to hardware structure 1767190873Sjfv * @data: data value to write 1768190873Sjfv * 1769190873Sjfv * Clocks out one bit via I2C data/clock 1770190873Sjfv **/ 1771190873Sjfvstatic s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data) 1772190873Sjfv{ 1773190873Sjfv s32 status; 1774190873Sjfv u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1775190873Sjfv 1776200239Sjfv DEBUGFUNC("ixgbe_clock_out_i2c_bit"); 1777200239Sjfv 1778190873Sjfv status = ixgbe_set_i2c_data(hw, &i2cctl, data); 1779190873Sjfv if (status == IXGBE_SUCCESS) { 1780230775Sjfv ixgbe_raise_i2c_clk(hw, &i2cctl); 1781190873Sjfv 1782190873Sjfv /* Minimum high period of clock is 4us */ 1783190873Sjfv usec_delay(IXGBE_I2C_T_HIGH); 1784190873Sjfv 1785190873Sjfv ixgbe_lower_i2c_clk(hw, &i2cctl); 1786190873Sjfv 1787190873Sjfv /* Minimum low period of clock is 4.7 us. 1788190873Sjfv * This also takes care of the data hold time. 1789190873Sjfv */ 1790190873Sjfv usec_delay(IXGBE_I2C_T_LOW); 1791190873Sjfv } else { 1792190873Sjfv status = IXGBE_ERR_I2C; 1793251964Sjfv ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1794251964Sjfv "I2C data was not set to %X\n", data); 1795190873Sjfv } 1796190873Sjfv 1797190873Sjfv return status; 1798190873Sjfv} 1799190873Sjfv/** 1800190873Sjfv * ixgbe_raise_i2c_clk - Raises the I2C SCL clock 1801190873Sjfv * @hw: pointer to hardware structure 1802190873Sjfv * @i2cctl: Current value of I2CCTL register 1803190873Sjfv * 1804190873Sjfv * Raises the I2C clock line '0'->'1' 1805190873Sjfv **/ 1806230775Sjfvstatic void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 1807190873Sjfv{ 1808238149Sjfv u32 i = 0; 1809238149Sjfv u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT; 1810238149Sjfv u32 i2cctl_r = 0; 1811238149Sjfv 1812200239Sjfv DEBUGFUNC("ixgbe_raise_i2c_clk"); 1813200239Sjfv 1814238149Sjfv for (i = 0; i < timeout; i++) { 1815238149Sjfv *i2cctl |= IXGBE_I2C_CLK_OUT; 1816190873Sjfv 1817238149Sjfv IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1818238149Sjfv IXGBE_WRITE_FLUSH(hw); 1819238149Sjfv /* SCL rise time (1000ns) */ 1820238149Sjfv usec_delay(IXGBE_I2C_T_RISE); 1821190873Sjfv 1822238149Sjfv i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1823238149Sjfv if (i2cctl_r & IXGBE_I2C_CLK_IN) 1824238149Sjfv break; 1825238149Sjfv } 1826190873Sjfv} 1827190873Sjfv 1828190873Sjfv/** 1829190873Sjfv * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock 1830190873Sjfv * @hw: pointer to hardware structure 1831190873Sjfv * @i2cctl: Current value of I2CCTL register 1832190873Sjfv * 1833190873Sjfv * Lowers the I2C clock line '1'->'0' 1834190873Sjfv **/ 1835190873Sjfvstatic void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 1836190873Sjfv{ 1837190873Sjfv 1838200239Sjfv DEBUGFUNC("ixgbe_lower_i2c_clk"); 1839200239Sjfv 1840190873Sjfv *i2cctl &= ~IXGBE_I2C_CLK_OUT; 1841190873Sjfv 1842190873Sjfv IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1843230775Sjfv IXGBE_WRITE_FLUSH(hw); 1844190873Sjfv 1845190873Sjfv /* SCL fall time (300ns) */ 1846190873Sjfv usec_delay(IXGBE_I2C_T_FALL); 1847190873Sjfv} 1848190873Sjfv 1849190873Sjfv/** 1850190873Sjfv * ixgbe_set_i2c_data - Sets the I2C data bit 1851190873Sjfv * @hw: pointer to hardware structure 1852190873Sjfv * @i2cctl: Current value of I2CCTL register 1853190873Sjfv * @data: I2C data value (0 or 1) to set 1854190873Sjfv * 1855190873Sjfv * Sets the I2C data bit 1856190873Sjfv **/ 1857190873Sjfvstatic s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data) 1858190873Sjfv{ 1859190873Sjfv s32 status = IXGBE_SUCCESS; 1860190873Sjfv 1861200239Sjfv DEBUGFUNC("ixgbe_set_i2c_data"); 1862200239Sjfv 1863190873Sjfv if (data) 1864190873Sjfv *i2cctl |= IXGBE_I2C_DATA_OUT; 1865190873Sjfv else 1866190873Sjfv *i2cctl &= ~IXGBE_I2C_DATA_OUT; 1867190873Sjfv 1868190873Sjfv IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); 1869230775Sjfv IXGBE_WRITE_FLUSH(hw); 1870190873Sjfv 1871190873Sjfv /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 1872190873Sjfv usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); 1873190873Sjfv 1874190873Sjfv /* Verify data was set correctly */ 1875190873Sjfv *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1876190873Sjfv if (data != ixgbe_get_i2c_data(i2cctl)) { 1877190873Sjfv status = IXGBE_ERR_I2C; 1878251964Sjfv ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1879251964Sjfv "Error - I2C data was not set to %X.\n", 1880251964Sjfv data); 1881190873Sjfv } 1882190873Sjfv 1883190873Sjfv return status; 1884190873Sjfv} 1885190873Sjfv 1886190873Sjfv/** 1887190873Sjfv * ixgbe_get_i2c_data - Reads the I2C SDA data bit 1888190873Sjfv * @hw: pointer to hardware structure 1889190873Sjfv * @i2cctl: Current value of I2CCTL register 1890190873Sjfv * 1891190873Sjfv * Returns the I2C data bit value 1892190873Sjfv **/ 1893190873Sjfvstatic bool ixgbe_get_i2c_data(u32 *i2cctl) 1894190873Sjfv{ 1895190873Sjfv bool data; 1896190873Sjfv 1897200239Sjfv DEBUGFUNC("ixgbe_get_i2c_data"); 1898200239Sjfv 1899190873Sjfv if (*i2cctl & IXGBE_I2C_DATA_IN) 1900190873Sjfv data = 1; 1901190873Sjfv else 1902190873Sjfv data = 0; 1903190873Sjfv 1904190873Sjfv return data; 1905190873Sjfv} 1906190873Sjfv 1907190873Sjfv/** 1908190873Sjfv * ixgbe_i2c_bus_clear - Clears the I2C bus 1909190873Sjfv * @hw: pointer to hardware structure 1910190873Sjfv * 1911190873Sjfv * Clears the I2C bus by sending nine clock pulses. 1912190873Sjfv * Used when data line is stuck low. 1913190873Sjfv **/ 1914190873Sjfvvoid ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) 1915190873Sjfv{ 1916190873Sjfv u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1917190873Sjfv u32 i; 1918190873Sjfv 1919190873Sjfv DEBUGFUNC("ixgbe_i2c_bus_clear"); 1920190873Sjfv 1921190873Sjfv ixgbe_i2c_start(hw); 1922190873Sjfv 1923190873Sjfv ixgbe_set_i2c_data(hw, &i2cctl, 1); 1924190873Sjfv 1925190873Sjfv for (i = 0; i < 9; i++) { 1926190873Sjfv ixgbe_raise_i2c_clk(hw, &i2cctl); 1927190873Sjfv 1928190873Sjfv /* Min high period of clock is 4us */ 1929190873Sjfv usec_delay(IXGBE_I2C_T_HIGH); 1930190873Sjfv 1931190873Sjfv ixgbe_lower_i2c_clk(hw, &i2cctl); 1932190873Sjfv 1933190873Sjfv /* Min low period of clock is 4.7us*/ 1934190873Sjfv usec_delay(IXGBE_I2C_T_LOW); 1935190873Sjfv } 1936190873Sjfv 1937190873Sjfv ixgbe_i2c_start(hw); 1938190873Sjfv 1939190873Sjfv /* Put the i2c bus back to default state */ 1940190873Sjfv ixgbe_i2c_stop(hw); 1941190873Sjfv} 1942205720Sjfv 1943205720Sjfv/** 1944238149Sjfv * ixgbe_tn_check_overtemp - Checks if an overtemp occurred. 1945205720Sjfv * @hw: pointer to hardware structure 1946205720Sjfv * 1947205720Sjfv * Checks if the LASI temp alarm status was triggered due to overtemp 1948205720Sjfv **/ 1949205720Sjfvs32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw) 1950205720Sjfv{ 1951205720Sjfv s32 status = IXGBE_SUCCESS; 1952205720Sjfv u16 phy_data = 0; 1953205720Sjfv 1954205720Sjfv DEBUGFUNC("ixgbe_tn_check_overtemp"); 1955205720Sjfv 1956205720Sjfv if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM) 1957205720Sjfv goto out; 1958205720Sjfv 1959205720Sjfv /* Check that the LASI temp alarm status was triggered */ 1960205720Sjfv hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG, 1961205720Sjfv IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data); 1962205720Sjfv 1963205720Sjfv if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM)) 1964205720Sjfv goto out; 1965205720Sjfv 1966205720Sjfv status = IXGBE_ERR_OVERTEMP; 1967251964Sjfv ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature"); 1968205720Sjfvout: 1969205720Sjfv return status; 1970205720Sjfv} 1971