1179055Sjfv/****************************************************************************** 2171384Sjfv 3320897Serj Copyright (c) 2001-2017, Intel Corporation 4171384Sjfv All rights reserved. 5320897Serj 6320897Serj Redistribution and use in source and binary forms, with or without 7171384Sjfv modification, are permitted provided that the following conditions are met: 8320897Serj 9320897Serj 1. Redistributions of source code must retain the above copyright notice, 10171384Sjfv this list of conditions and the following disclaimer. 11320897Serj 12320897Serj 2. Redistributions in binary form must reproduce the above copyright 13320897Serj notice, this list of conditions and the following disclaimer in the 14171384Sjfv documentation and/or other materials provided with the distribution. 15320897Serj 16320897Serj 3. Neither the name of the Intel Corporation nor the names of its 17320897Serj contributors may be used to endorse or promote products derived from 18171384Sjfv this software without specific prior written permission. 19320897Serj 20171384Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21320897Serj AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22320897Serj IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23320897Serj ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24320897Serj LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25320897Serj CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26320897Serj SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27320897Serj INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28320897Serj CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29171384Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30171384Sjfv POSSIBILITY OF SUCH DAMAGE. 31171384Sjfv 32179055Sjfv******************************************************************************/ 33179055Sjfv/*$FreeBSD: stable/11/sys/dev/ixgbe/ixgbe_phy.c 320897 2017-07-11 21:25:07Z erj $*/ 34171384Sjfv 35171384Sjfv#include "ixgbe_api.h" 36171384Sjfv#include "ixgbe_common.h" 37171384Sjfv#include "ixgbe_phy.h" 38171384Sjfv 39190873Sjfvstatic void ixgbe_i2c_start(struct ixgbe_hw *hw); 40190873Sjfvstatic void ixgbe_i2c_stop(struct ixgbe_hw *hw); 41190873Sjfvstatic s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data); 42190873Sjfvstatic s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data); 43190873Sjfvstatic s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw); 44190873Sjfvstatic s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data); 45190873Sjfvstatic s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data); 46230775Sjfvstatic void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 47190873Sjfvstatic void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 48190873Sjfvstatic s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data); 49280182Sjfvstatic bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl); 50247822Sjfvstatic s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 51247822Sjfv u8 *sff8472_data); 52190873Sjfv 53171384Sjfv/** 54280182Sjfv * ixgbe_out_i2c_byte_ack - Send I2C byte with ack 55280182Sjfv * @hw: pointer to the hardware structure 56280182Sjfv * @byte: byte to send 57280182Sjfv * 58280182Sjfv * Returns an error code on error. 59280182Sjfv */ 60280182Sjfvstatic s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte) 61280182Sjfv{ 62280182Sjfv s32 status; 63280182Sjfv 64280182Sjfv status = ixgbe_clock_out_i2c_byte(hw, byte); 65280182Sjfv if (status) 66280182Sjfv return status; 67280182Sjfv return ixgbe_get_i2c_ack(hw); 68280182Sjfv} 69280182Sjfv 70280182Sjfv/** 71280182Sjfv * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack 72280182Sjfv * @hw: pointer to the hardware structure 73280182Sjfv * @byte: pointer to a u8 to receive the byte 74280182Sjfv * 75280182Sjfv * Returns an error code on error. 76280182Sjfv */ 77280182Sjfvstatic s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte) 78280182Sjfv{ 79280182Sjfv s32 status; 80280182Sjfv 81280182Sjfv status = ixgbe_clock_in_i2c_byte(hw, byte); 82280182Sjfv if (status) 83280182Sjfv return status; 84280182Sjfv /* ACK */ 85280182Sjfv return ixgbe_clock_out_i2c_bit(hw, FALSE); 86280182Sjfv} 87280182Sjfv 88280182Sjfv/** 89280182Sjfv * ixgbe_ones_comp_byte_add - Perform one's complement addition 90280182Sjfv * @add1 - addend 1 91280182Sjfv * @add2 - addend 2 92280182Sjfv * 93280182Sjfv * Returns one's complement 8-bit sum. 94280182Sjfv */ 95280182Sjfvstatic u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2) 96280182Sjfv{ 97280182Sjfv u16 sum = add1 + add2; 98280182Sjfv 99280182Sjfv sum = (sum & 0xFF) + (sum >> 8); 100280182Sjfv return sum & 0xFF; 101280182Sjfv} 102280182Sjfv 103280182Sjfv/** 104282289Serj * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation 105280182Sjfv * @hw: pointer to the hardware structure 106280182Sjfv * @addr: I2C bus address to read from 107280182Sjfv * @reg: I2C device register to read from 108280182Sjfv * @val: pointer to location to receive read value 109282289Serj * @lock: TRUE if to take and release semaphore 110280182Sjfv * 111280182Sjfv * Returns an error code on error. 112280182Sjfv */ 113320897Serjs32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg, 114320897Serj u16 *val, bool lock) 115280182Sjfv{ 116280182Sjfv u32 swfw_mask = hw->phy.phy_semaphore_mask; 117320897Serj int max_retry = 3; 118280182Sjfv int retry = 0; 119280182Sjfv u8 csum_byte; 120280182Sjfv u8 high_bits; 121280182Sjfv u8 low_bits; 122280182Sjfv u8 reg_high; 123280182Sjfv u8 csum; 124280182Sjfv 125280182Sjfv reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */ 126280182Sjfv csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 127280182Sjfv csum = ~csum; 128280182Sjfv do { 129282289Serj if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 130280182Sjfv return IXGBE_ERR_SWFW_SYNC; 131280182Sjfv ixgbe_i2c_start(hw); 132280182Sjfv /* Device Address and write indication */ 133280182Sjfv if (ixgbe_out_i2c_byte_ack(hw, addr)) 134280182Sjfv goto fail; 135280182Sjfv /* Write bits 14:8 */ 136280182Sjfv if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 137280182Sjfv goto fail; 138280182Sjfv /* Write bits 7:0 */ 139280182Sjfv if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 140280182Sjfv goto fail; 141280182Sjfv /* Write csum */ 142280182Sjfv if (ixgbe_out_i2c_byte_ack(hw, csum)) 143280182Sjfv goto fail; 144280182Sjfv /* Re-start condition */ 145280182Sjfv ixgbe_i2c_start(hw); 146280182Sjfv /* Device Address and read indication */ 147280182Sjfv if (ixgbe_out_i2c_byte_ack(hw, addr | 1)) 148280182Sjfv goto fail; 149280182Sjfv /* Get upper bits */ 150280182Sjfv if (ixgbe_in_i2c_byte_ack(hw, &high_bits)) 151280182Sjfv goto fail; 152280182Sjfv /* Get low bits */ 153280182Sjfv if (ixgbe_in_i2c_byte_ack(hw, &low_bits)) 154280182Sjfv goto fail; 155280182Sjfv /* Get csum */ 156280182Sjfv if (ixgbe_clock_in_i2c_byte(hw, &csum_byte)) 157280182Sjfv goto fail; 158280182Sjfv /* NACK */ 159280182Sjfv if (ixgbe_clock_out_i2c_bit(hw, FALSE)) 160280182Sjfv goto fail; 161280182Sjfv ixgbe_i2c_stop(hw); 162282289Serj if (lock) 163282289Serj hw->mac.ops.release_swfw_sync(hw, swfw_mask); 164280182Sjfv *val = (high_bits << 8) | low_bits; 165280182Sjfv return 0; 166280182Sjfv 167280182Sjfvfail: 168280182Sjfv ixgbe_i2c_bus_clear(hw); 169282289Serj if (lock) 170282289Serj hw->mac.ops.release_swfw_sync(hw, swfw_mask); 171280182Sjfv retry++; 172280182Sjfv if (retry < max_retry) 173280182Sjfv DEBUGOUT("I2C byte read combined error - Retrying.\n"); 174280182Sjfv else 175280182Sjfv DEBUGOUT("I2C byte read combined error.\n"); 176280182Sjfv } while (retry < max_retry); 177280182Sjfv 178280182Sjfv return IXGBE_ERR_I2C; 179280182Sjfv} 180280182Sjfv 181280182Sjfv/** 182282289Serj * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation 183282289Serj * @hw: pointer to the hardware structure 184280182Sjfv * @addr: I2C bus address to write to 185280182Sjfv * @reg: I2C device register to write to 186280182Sjfv * @val: value to write 187282289Serj * @lock: TRUE if to take and release semaphore 188280182Sjfv * 189280182Sjfv * Returns an error code on error. 190280182Sjfv */ 191320897Serjs32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg, 192320897Serj u16 val, bool lock) 193280182Sjfv{ 194282289Serj u32 swfw_mask = hw->phy.phy_semaphore_mask; 195280182Sjfv int max_retry = 1; 196280182Sjfv int retry = 0; 197280182Sjfv u8 reg_high; 198280182Sjfv u8 csum; 199280182Sjfv 200280182Sjfv reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */ 201280182Sjfv csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 202280182Sjfv csum = ixgbe_ones_comp_byte_add(csum, val >> 8); 203280182Sjfv csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF); 204280182Sjfv csum = ~csum; 205280182Sjfv do { 206282289Serj if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 207282289Serj return IXGBE_ERR_SWFW_SYNC; 208280182Sjfv ixgbe_i2c_start(hw); 209280182Sjfv /* Device Address and write indication */ 210280182Sjfv if (ixgbe_out_i2c_byte_ack(hw, addr)) 211280182Sjfv goto fail; 212280182Sjfv /* Write bits 14:8 */ 213280182Sjfv if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 214280182Sjfv goto fail; 215280182Sjfv /* Write bits 7:0 */ 216280182Sjfv if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 217280182Sjfv goto fail; 218280182Sjfv /* Write data 15:8 */ 219280182Sjfv if (ixgbe_out_i2c_byte_ack(hw, val >> 8)) 220280182Sjfv goto fail; 221280182Sjfv /* Write data 7:0 */ 222280182Sjfv if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF)) 223280182Sjfv goto fail; 224280182Sjfv /* Write csum */ 225280182Sjfv if (ixgbe_out_i2c_byte_ack(hw, csum)) 226280182Sjfv goto fail; 227280182Sjfv ixgbe_i2c_stop(hw); 228282289Serj if (lock) 229282289Serj hw->mac.ops.release_swfw_sync(hw, swfw_mask); 230280182Sjfv return 0; 231280182Sjfv 232280182Sjfvfail: 233280182Sjfv ixgbe_i2c_bus_clear(hw); 234282289Serj if (lock) 235282289Serj hw->mac.ops.release_swfw_sync(hw, swfw_mask); 236280182Sjfv retry++; 237280182Sjfv if (retry < max_retry) 238280182Sjfv DEBUGOUT("I2C byte write combined error - Retrying.\n"); 239280182Sjfv else 240280182Sjfv DEBUGOUT("I2C byte write combined error.\n"); 241280182Sjfv } while (retry < max_retry); 242280182Sjfv 243280182Sjfv return IXGBE_ERR_I2C; 244280182Sjfv} 245280182Sjfv 246280182Sjfv/** 247179055Sjfv * ixgbe_init_phy_ops_generic - Inits PHY function ptrs 248179055Sjfv * @hw: pointer to the hardware structure 249179055Sjfv * 250179055Sjfv * Initialize the function pointers. 251171384Sjfv **/ 252179055Sjfvs32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw) 253171384Sjfv{ 254179055Sjfv struct ixgbe_phy_info *phy = &hw->phy; 255171384Sjfv 256200239Sjfv DEBUGFUNC("ixgbe_init_phy_ops_generic"); 257200239Sjfv 258179055Sjfv /* PHY */ 259280182Sjfv phy->ops.identify = ixgbe_identify_phy_generic; 260280182Sjfv phy->ops.reset = ixgbe_reset_phy_generic; 261280182Sjfv phy->ops.read_reg = ixgbe_read_phy_reg_generic; 262280182Sjfv phy->ops.write_reg = ixgbe_write_phy_reg_generic; 263280182Sjfv phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi; 264280182Sjfv phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi; 265280182Sjfv phy->ops.setup_link = ixgbe_setup_phy_link_generic; 266280182Sjfv phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic; 267179055Sjfv phy->ops.check_link = NULL; 268200239Sjfv phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic; 269280182Sjfv phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic; 270280182Sjfv phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic; 271280182Sjfv phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic; 272280182Sjfv phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic; 273280182Sjfv phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic; 274280182Sjfv phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear; 275280182Sjfv phy->ops.identify_sfp = ixgbe_identify_module_generic; 276185352Sjfv phy->sfp_type = ixgbe_sfp_type_unknown; 277282289Serj phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked; 278282289Serj phy->ops.write_i2c_byte_unlocked = 279282289Serj ixgbe_write_i2c_byte_generic_unlocked; 280280182Sjfv phy->ops.check_overtemp = ixgbe_tn_check_overtemp; 281171384Sjfv return IXGBE_SUCCESS; 282171384Sjfv} 283171384Sjfv 284171384Sjfv/** 285320897Serj * ixgbe_probe_phy - Probe a single address for a PHY 286320897Serj * @hw: pointer to hardware structure 287320897Serj * @phy_addr: PHY address to probe 288320897Serj * 289320897Serj * Returns TRUE if PHY found 290320897Serj */ 291320897Serjstatic bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr) 292320897Serj{ 293320897Serj u16 ext_ability = 0; 294320897Serj 295320897Serj if (!ixgbe_validate_phy_addr(hw, phy_addr)) { 296320897Serj DEBUGOUT1("Unable to validate PHY address 0x%04X\n", 297320897Serj phy_addr); 298320897Serj return FALSE; 299320897Serj } 300320897Serj 301320897Serj if (ixgbe_get_phy_id(hw)) 302320897Serj return FALSE; 303320897Serj 304320897Serj hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id); 305320897Serj 306320897Serj if (hw->phy.type == ixgbe_phy_unknown) { 307320897Serj hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 308320897Serj IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 309320897Serj if (ext_ability & 310320897Serj (IXGBE_MDIO_PHY_10GBASET_ABILITY | 311320897Serj IXGBE_MDIO_PHY_1000BASET_ABILITY)) 312320897Serj hw->phy.type = ixgbe_phy_cu_unknown; 313320897Serj else 314320897Serj hw->phy.type = ixgbe_phy_generic; 315320897Serj } 316320897Serj 317320897Serj return TRUE; 318320897Serj} 319320897Serj 320320897Serj/** 321171384Sjfv * ixgbe_identify_phy_generic - Get physical layer module 322171384Sjfv * @hw: pointer to hardware structure 323171384Sjfv * 324171384Sjfv * Determines the physical layer module found on the current adapter. 325171384Sjfv **/ 326171384Sjfvs32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) 327171384Sjfv{ 328171384Sjfv s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 329320897Serj u16 phy_addr; 330171384Sjfv 331200239Sjfv DEBUGFUNC("ixgbe_identify_phy_generic"); 332200239Sjfv 333280182Sjfv if (!hw->phy.phy_semaphore_mask) { 334280182Sjfv if (hw->bus.lan_id) 335280182Sjfv hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 336280182Sjfv else 337280182Sjfv hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 338280182Sjfv } 339280182Sjfv 340320897Serj if (hw->phy.type != ixgbe_phy_unknown) 341320897Serj return IXGBE_SUCCESS; 342190873Sjfv 343320897Serj if (hw->phy.nw_mng_if_sel) { 344320897Serj phy_addr = (hw->phy.nw_mng_if_sel & 345320897Serj IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >> 346320897Serj IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT; 347320897Serj if (ixgbe_probe_phy(hw, phy_addr)) 348320897Serj return IXGBE_SUCCESS; 349320897Serj else 350320897Serj return IXGBE_ERR_PHY_ADDR_INVALID; 351320897Serj } 352190873Sjfv 353320897Serj for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { 354320897Serj if (ixgbe_probe_phy(hw, phy_addr)) { 355320897Serj status = IXGBE_SUCCESS; 356320897Serj break; 357171384Sjfv } 358171384Sjfv } 359179055Sjfv 360320897Serj /* Certain media types do not have a phy so an address will not 361320897Serj * be found and the code will take this path. Caller has to 362320897Serj * decide if it is an error or not. 363320897Serj */ 364320897Serj if (status != IXGBE_SUCCESS) 365320897Serj hw->phy.addr = 0; 366320897Serj 367171384Sjfv return status; 368171384Sjfv} 369171384Sjfv 370171384Sjfv/** 371280182Sjfv * ixgbe_check_reset_blocked - check status of MNG FW veto bit 372280182Sjfv * @hw: pointer to the hardware structure 373280182Sjfv * 374280182Sjfv * This function checks the MMNGC.MNG_VETO bit to see if there are 375280182Sjfv * any constraints on link from manageability. For MAC's that don't 376280182Sjfv * have this bit just return faluse since the link can not be blocked 377280182Sjfv * via this method. 378280182Sjfv **/ 379280182Sjfvs32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw) 380280182Sjfv{ 381280182Sjfv u32 mmngc; 382280182Sjfv 383280182Sjfv DEBUGFUNC("ixgbe_check_reset_blocked"); 384280182Sjfv 385280182Sjfv /* If we don't have this bit, it can't be blocking */ 386280182Sjfv if (hw->mac.type == ixgbe_mac_82598EB) 387280182Sjfv return FALSE; 388280182Sjfv 389280182Sjfv mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC); 390280182Sjfv if (mmngc & IXGBE_MMNGC_MNG_VETO) { 391280182Sjfv ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, 392280182Sjfv "MNG_VETO bit detected.\n"); 393280182Sjfv return TRUE; 394280182Sjfv } 395280182Sjfv 396280182Sjfv return FALSE; 397280182Sjfv} 398280182Sjfv 399280182Sjfv/** 400171384Sjfv * ixgbe_validate_phy_addr - Determines phy address is valid 401171384Sjfv * @hw: pointer to hardware structure 402171384Sjfv * 403171384Sjfv **/ 404171384Sjfvbool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr) 405171384Sjfv{ 406171384Sjfv u16 phy_id = 0; 407171384Sjfv bool valid = FALSE; 408171384Sjfv 409200239Sjfv DEBUGFUNC("ixgbe_validate_phy_addr"); 410200239Sjfv 411171384Sjfv hw->phy.addr = phy_addr; 412179055Sjfv hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 413230775Sjfv IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id); 414171384Sjfv 415171384Sjfv if (phy_id != 0xFFFF && phy_id != 0x0) 416171384Sjfv valid = TRUE; 417171384Sjfv 418320897Serj DEBUGOUT1("PHY ID HIGH is 0x%04X\n", phy_id); 419320897Serj 420171384Sjfv return valid; 421171384Sjfv} 422171384Sjfv 423171384Sjfv/** 424171384Sjfv * ixgbe_get_phy_id - Get the phy type 425171384Sjfv * @hw: pointer to hardware structure 426171384Sjfv * 427171384Sjfv **/ 428171384Sjfvs32 ixgbe_get_phy_id(struct ixgbe_hw *hw) 429171384Sjfv{ 430171384Sjfv u32 status; 431171384Sjfv u16 phy_id_high = 0; 432171384Sjfv u16 phy_id_low = 0; 433171384Sjfv 434200239Sjfv DEBUGFUNC("ixgbe_get_phy_id"); 435200239Sjfv 436179055Sjfv status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 437230775Sjfv IXGBE_MDIO_PMA_PMD_DEV_TYPE, 438230775Sjfv &phy_id_high); 439171384Sjfv 440171384Sjfv if (status == IXGBE_SUCCESS) { 441171384Sjfv hw->phy.id = (u32)(phy_id_high << 16); 442179055Sjfv status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW, 443230775Sjfv IXGBE_MDIO_PMA_PMD_DEV_TYPE, 444230775Sjfv &phy_id_low); 445171384Sjfv hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); 446171384Sjfv hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); 447171384Sjfv } 448320897Serj DEBUGOUT2("PHY_ID_HIGH 0x%04X, PHY_ID_LOW 0x%04X\n", 449320897Serj phy_id_high, phy_id_low); 450320897Serj 451171384Sjfv return status; 452171384Sjfv} 453171384Sjfv 454171384Sjfv/** 455171384Sjfv * ixgbe_get_phy_type_from_id - Get the phy type 456320897Serj * @phy_id: PHY ID information 457171384Sjfv * 458171384Sjfv **/ 459171384Sjfvenum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) 460171384Sjfv{ 461171384Sjfv enum ixgbe_phy_type phy_type; 462171384Sjfv 463200239Sjfv DEBUGFUNC("ixgbe_get_phy_type_from_id"); 464200239Sjfv 465171384Sjfv switch (phy_id) { 466179055Sjfv case TN1010_PHY_ID: 467179055Sjfv phy_type = ixgbe_phy_tn; 468179055Sjfv break; 469292674Ssbruno case X550_PHY_ID2: 470292674Ssbruno case X550_PHY_ID3: 471230775Sjfv case X540_PHY_ID: 472190873Sjfv phy_type = ixgbe_phy_aq; 473190873Sjfv break; 474171384Sjfv case QT2022_PHY_ID: 475171384Sjfv phy_type = ixgbe_phy_qt; 476171384Sjfv break; 477185352Sjfv case ATH_PHY_ID: 478185352Sjfv phy_type = ixgbe_phy_nl; 479185352Sjfv break; 480280182Sjfv case X557_PHY_ID: 481320897Serj case X557_PHY_ID2: 482280182Sjfv phy_type = ixgbe_phy_x550em_ext_t; 483280182Sjfv break; 484320897Serj case IXGBE_M88E1500_E_PHY_ID: 485320897Serj case IXGBE_M88E1543_E_PHY_ID: 486320897Serj phy_type = ixgbe_phy_ext_1g_t; 487320897Serj break; 488171384Sjfv default: 489171384Sjfv phy_type = ixgbe_phy_unknown; 490171384Sjfv break; 491171384Sjfv } 492171384Sjfv return phy_type; 493171384Sjfv} 494171384Sjfv 495171384Sjfv/** 496171384Sjfv * ixgbe_reset_phy_generic - Performs a PHY reset 497171384Sjfv * @hw: pointer to hardware structure 498171384Sjfv **/ 499171384Sjfvs32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 500171384Sjfv{ 501190873Sjfv u32 i; 502190873Sjfv u16 ctrl = 0; 503190873Sjfv s32 status = IXGBE_SUCCESS; 504190873Sjfv 505200239Sjfv DEBUGFUNC("ixgbe_reset_phy_generic"); 506200239Sjfv 507190873Sjfv if (hw->phy.type == ixgbe_phy_unknown) 508190873Sjfv status = ixgbe_identify_phy_generic(hw); 509190873Sjfv 510190873Sjfv if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none) 511190873Sjfv goto out; 512190873Sjfv 513215911Sjfv /* Don't reset PHY if it's shut down due to overtemp. */ 514215911Sjfv if (!hw->phy.reset_if_overtemp && 515215911Sjfv (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw))) 516215911Sjfv goto out; 517215911Sjfv 518280182Sjfv /* Blocked by MNG FW so bail */ 519280182Sjfv if (ixgbe_check_reset_blocked(hw)) 520280182Sjfv goto out; 521280182Sjfv 522171384Sjfv /* 523171384Sjfv * Perform soft PHY reset to the PHY_XS. 524171384Sjfv * This will cause a soft reset to the PHY 525171384Sjfv */ 526190873Sjfv hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 527230775Sjfv IXGBE_MDIO_PHY_XS_DEV_TYPE, 528230775Sjfv IXGBE_MDIO_PHY_XS_RESET); 529190873Sjfv 530205720Sjfv /* 531205720Sjfv * Poll for reset bit to self-clear indicating reset is complete. 532205720Sjfv * Some PHYs could take up to 3 seconds to complete and need about 533205720Sjfv * 1.7 usec delay after the reset is complete. 534205720Sjfv */ 535205720Sjfv for (i = 0; i < 30; i++) { 536205720Sjfv msec_delay(100); 537320897Serj if (hw->phy.type == ixgbe_phy_x550em_ext_t) { 538320897Serj status = hw->phy.ops.read_reg(hw, 539320897Serj IXGBE_MDIO_TX_VENDOR_ALARMS_3, 540320897Serj IXGBE_MDIO_PMA_PMD_DEV_TYPE, 541320897Serj &ctrl); 542320897Serj if (status != IXGBE_SUCCESS) 543320897Serj return status; 544320897Serj 545320897Serj if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) { 546320897Serj usec_delay(2); 547320897Serj break; 548320897Serj } 549320897Serj } else { 550320897Serj status = hw->phy.ops.read_reg(hw, 551320897Serj IXGBE_MDIO_PHY_XS_CONTROL, 552320897Serj IXGBE_MDIO_PHY_XS_DEV_TYPE, 553320897Serj &ctrl); 554320897Serj if (status != IXGBE_SUCCESS) 555320897Serj return status; 556320897Serj 557320897Serj if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) { 558320897Serj usec_delay(2); 559320897Serj break; 560320897Serj } 561205720Sjfv } 562190873Sjfv } 563190873Sjfv 564190873Sjfv if (ctrl & IXGBE_MDIO_PHY_XS_RESET) { 565190873Sjfv status = IXGBE_ERR_RESET_FAILED; 566251964Sjfv ERROR_REPORT1(IXGBE_ERROR_POLLING, 567251964Sjfv "PHY reset polling failed to complete.\n"); 568190873Sjfv } 569190873Sjfv 570190873Sjfvout: 571190873Sjfv return status; 572171384Sjfv} 573171384Sjfv 574171384Sjfv/** 575251964Sjfv * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without 576251964Sjfv * the SWFW lock 577251964Sjfv * @hw: pointer to hardware structure 578251964Sjfv * @reg_addr: 32 bit address of PHY register to read 579251964Sjfv * @phy_data: Pointer to read data from PHY register 580251964Sjfv **/ 581251964Sjfvs32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 582320897Serj u16 *phy_data) 583251964Sjfv{ 584251964Sjfv u32 i, data, command; 585251964Sjfv 586251964Sjfv /* Setup and write the address cycle command */ 587251964Sjfv command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 588251964Sjfv (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 589251964Sjfv (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 590251964Sjfv (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 591251964Sjfv 592251964Sjfv IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 593251964Sjfv 594251964Sjfv /* 595251964Sjfv * Check every 10 usec to see if the address cycle completed. 596251964Sjfv * The MDI Command bit will clear when the operation is 597251964Sjfv * complete 598251964Sjfv */ 599251964Sjfv for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 600251964Sjfv usec_delay(10); 601251964Sjfv 602251964Sjfv command = IXGBE_READ_REG(hw, IXGBE_MSCA); 603251964Sjfv if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 604320897Serj break; 605251964Sjfv } 606251964Sjfv 607251964Sjfv 608251964Sjfv if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 609251964Sjfv ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n"); 610320897Serj DEBUGOUT("PHY address command did not complete, returning IXGBE_ERR_PHY\n"); 611251964Sjfv return IXGBE_ERR_PHY; 612251964Sjfv } 613251964Sjfv 614251964Sjfv /* 615251964Sjfv * Address cycle complete, setup and write the read 616251964Sjfv * command 617251964Sjfv */ 618251964Sjfv command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 619251964Sjfv (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 620251964Sjfv (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 621251964Sjfv (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); 622251964Sjfv 623251964Sjfv IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 624251964Sjfv 625251964Sjfv /* 626251964Sjfv * Check every 10 usec to see if the address cycle 627251964Sjfv * completed. The MDI Command bit will clear when the 628251964Sjfv * operation is complete 629251964Sjfv */ 630251964Sjfv for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 631251964Sjfv usec_delay(10); 632251964Sjfv 633251964Sjfv command = IXGBE_READ_REG(hw, IXGBE_MSCA); 634251964Sjfv if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 635251964Sjfv break; 636251964Sjfv } 637251964Sjfv 638251964Sjfv if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 639251964Sjfv ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n"); 640320897Serj DEBUGOUT("PHY read command didn't complete, returning IXGBE_ERR_PHY\n"); 641251964Sjfv return IXGBE_ERR_PHY; 642251964Sjfv } 643251964Sjfv 644251964Sjfv /* 645251964Sjfv * Read operation is complete. Get the data 646251964Sjfv * from MSRWD 647251964Sjfv */ 648251964Sjfv data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 649251964Sjfv data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 650251964Sjfv *phy_data = (u16)(data); 651251964Sjfv 652251964Sjfv return IXGBE_SUCCESS; 653251964Sjfv} 654251964Sjfv 655251964Sjfv/** 656171384Sjfv * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register 657251964Sjfv * using the SWFW lock - this function is needed in most cases 658171384Sjfv * @hw: pointer to hardware structure 659171384Sjfv * @reg_addr: 32 bit address of PHY register to read 660171384Sjfv * @phy_data: Pointer to read data from PHY register 661171384Sjfv **/ 662171384Sjfvs32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 663230775Sjfv u32 device_type, u16 *phy_data) 664171384Sjfv{ 665251964Sjfv s32 status; 666280182Sjfv u32 gssr = hw->phy.phy_semaphore_mask; 667171384Sjfv 668200239Sjfv DEBUGFUNC("ixgbe_read_phy_reg_generic"); 669200239Sjfv 670320897Serj if (hw->mac.ops.acquire_swfw_sync(hw, gssr)) 671320897Serj return IXGBE_ERR_SWFW_SYNC; 672171384Sjfv 673320897Serj status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data); 674320897Serj 675320897Serj hw->mac.ops.release_swfw_sync(hw, gssr); 676320897Serj 677251964Sjfv return status; 678251964Sjfv} 679171384Sjfv 680251964Sjfv/** 681251964Sjfv * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register 682251964Sjfv * without SWFW lock 683251964Sjfv * @hw: pointer to hardware structure 684251964Sjfv * @reg_addr: 32 bit PHY register to write 685251964Sjfv * @device_type: 5 bit device type 686251964Sjfv * @phy_data: Data to write to the PHY register 687251964Sjfv **/ 688251964Sjfvs32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, 689251964Sjfv u32 device_type, u16 phy_data) 690251964Sjfv{ 691251964Sjfv u32 i, command; 692171384Sjfv 693251964Sjfv /* Put the data in the MDI single read and write data register*/ 694251964Sjfv IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); 695171384Sjfv 696251964Sjfv /* Setup and write the address cycle command */ 697251964Sjfv command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 698251964Sjfv (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 699251964Sjfv (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 700251964Sjfv (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 701171384Sjfv 702251964Sjfv IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 703171384Sjfv 704251964Sjfv /* 705251964Sjfv * Check every 10 usec to see if the address cycle completed. 706251964Sjfv * The MDI Command bit will clear when the operation is 707251964Sjfv * complete 708251964Sjfv */ 709251964Sjfv for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 710251964Sjfv usec_delay(10); 711171384Sjfv 712251964Sjfv command = IXGBE_READ_REG(hw, IXGBE_MSCA); 713251964Sjfv if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 714251964Sjfv break; 715251964Sjfv } 716171384Sjfv 717251964Sjfv if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 718251964Sjfv ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n"); 719251964Sjfv return IXGBE_ERR_PHY; 720251964Sjfv } 721171384Sjfv 722251964Sjfv /* 723251964Sjfv * Address cycle complete, setup and write the write 724251964Sjfv * command 725251964Sjfv */ 726251964Sjfv command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 727251964Sjfv (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 728251964Sjfv (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 729251964Sjfv (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); 730171384Sjfv 731251964Sjfv IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 732171384Sjfv 733251964Sjfv /* 734251964Sjfv * Check every 10 usec to see if the address cycle 735251964Sjfv * completed. The MDI Command bit will clear when the 736251964Sjfv * operation is complete 737251964Sjfv */ 738251964Sjfv for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 739251964Sjfv usec_delay(10); 740171384Sjfv 741251964Sjfv command = IXGBE_READ_REG(hw, IXGBE_MSCA); 742251964Sjfv if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 743251964Sjfv break; 744251964Sjfv } 745171384Sjfv 746251964Sjfv if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 747251964Sjfv ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n"); 748251964Sjfv return IXGBE_ERR_PHY; 749171384Sjfv } 750179055Sjfv 751251964Sjfv return IXGBE_SUCCESS; 752171384Sjfv} 753171384Sjfv 754171384Sjfv/** 755171384Sjfv * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register 756251964Sjfv * using SWFW lock- this function is needed in most cases 757171384Sjfv * @hw: pointer to hardware structure 758171384Sjfv * @reg_addr: 32 bit PHY register to write 759171384Sjfv * @device_type: 5 bit device type 760171384Sjfv * @phy_data: Data to write to the PHY register 761171384Sjfv **/ 762171384Sjfvs32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 763230775Sjfv u32 device_type, u16 phy_data) 764171384Sjfv{ 765251964Sjfv s32 status; 766280182Sjfv u32 gssr = hw->phy.phy_semaphore_mask; 767171384Sjfv 768200239Sjfv DEBUGFUNC("ixgbe_write_phy_reg_generic"); 769200239Sjfv 770251964Sjfv if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) { 771320897Serj status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type, 772251964Sjfv phy_data); 773251964Sjfv hw->mac.ops.release_swfw_sync(hw, gssr); 774251964Sjfv } else { 775171384Sjfv status = IXGBE_ERR_SWFW_SYNC; 776171384Sjfv } 777171384Sjfv 778171384Sjfv return status; 779171384Sjfv} 780171384Sjfv 781171384Sjfv/** 782280182Sjfv * ixgbe_setup_phy_link_generic - Set and restart auto-neg 783215911Sjfv * @hw: pointer to hardware structure 784171384Sjfv * 785280182Sjfv * Restart auto-negotiation and PHY and waits for completion. 786171384Sjfv **/ 787179055Sjfvs32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 788171384Sjfv{ 789194875Sjfv s32 status = IXGBE_SUCCESS; 790179055Sjfv u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 791200239Sjfv bool autoneg = FALSE; 792200239Sjfv ixgbe_link_speed speed; 793179055Sjfv 794200239Sjfv DEBUGFUNC("ixgbe_setup_phy_link_generic"); 795179055Sjfv 796200239Sjfv ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 797179055Sjfv 798320897Serj /* Set or unset auto-negotiation 10G advertisement */ 799320897Serj hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 800320897Serj IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 801320897Serj &autoneg_reg); 802179055Sjfv 803320897Serj autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 804320897Serj if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) && 805320897Serj (speed & IXGBE_LINK_SPEED_10GB_FULL)) 806320897Serj autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 807200239Sjfv 808320897Serj hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 809320897Serj IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 810320897Serj autoneg_reg); 811200239Sjfv 812320897Serj hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 813320897Serj IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 814320897Serj &autoneg_reg); 815320897Serj 816280182Sjfv if (hw->mac.type == ixgbe_mac_X550) { 817320897Serj /* Set or unset auto-negotiation 5G advertisement */ 818320897Serj autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE; 819320897Serj if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) && 820320897Serj (speed & IXGBE_LINK_SPEED_5GB_FULL)) 821320897Serj autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE; 822280182Sjfv 823320897Serj /* Set or unset auto-negotiation 2.5G advertisement */ 824320897Serj autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE; 825320897Serj if ((hw->phy.autoneg_advertised & 826320897Serj IXGBE_LINK_SPEED_2_5GB_FULL) && 827320897Serj (speed & IXGBE_LINK_SPEED_2_5GB_FULL)) 828320897Serj autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE; 829280182Sjfv } 830280182Sjfv 831320897Serj /* Set or unset auto-negotiation 1G advertisement */ 832320897Serj autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE; 833320897Serj if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) && 834320897Serj (speed & IXGBE_LINK_SPEED_1GB_FULL)) 835320897Serj autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE; 836200239Sjfv 837320897Serj hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 838320897Serj IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 839320897Serj autoneg_reg); 840200239Sjfv 841320897Serj /* Set or unset auto-negotiation 100M advertisement */ 842320897Serj hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 843320897Serj IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 844320897Serj &autoneg_reg); 845200239Sjfv 846320897Serj autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE | 847320897Serj IXGBE_MII_100BASE_T_ADVERTISE_HALF); 848320897Serj if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) && 849320897Serj (speed & IXGBE_LINK_SPEED_100_FULL)) 850320897Serj autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 851200239Sjfv 852320897Serj hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 853320897Serj IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 854320897Serj autoneg_reg); 855200239Sjfv 856280182Sjfv /* Blocked by MNG FW so don't reset PHY */ 857280182Sjfv if (ixgbe_check_reset_blocked(hw)) 858280182Sjfv return status; 859280182Sjfv 860280182Sjfv /* Restart PHY auto-negotiation. */ 861179055Sjfv hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 862230775Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 863179055Sjfv 864179055Sjfv autoneg_reg |= IXGBE_MII_RESTART; 865179055Sjfv 866179055Sjfv hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 867230775Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 868179055Sjfv 869179055Sjfv return status; 870171384Sjfv} 871171384Sjfv 872171384Sjfv/** 873179055Sjfv * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities 874171384Sjfv * @hw: pointer to hardware structure 875179055Sjfv * @speed: new link speed 876179055Sjfv **/ 877179055Sjfvs32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 878230775Sjfv ixgbe_link_speed speed, 879230775Sjfv bool autoneg_wait_to_complete) 880179055Sjfv{ 881247822Sjfv UNREFERENCED_1PARAMETER(autoneg_wait_to_complete); 882179055Sjfv 883200239Sjfv DEBUGFUNC("ixgbe_setup_phy_link_speed_generic"); 884200239Sjfv 885179055Sjfv /* 886179055Sjfv * Clear autoneg_advertised and set new values based on input link 887179055Sjfv * speed. 888179055Sjfv */ 889179055Sjfv hw->phy.autoneg_advertised = 0; 890179055Sjfv 891185352Sjfv if (speed & IXGBE_LINK_SPEED_10GB_FULL) 892179055Sjfv hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 893185352Sjfv 894280182Sjfv if (speed & IXGBE_LINK_SPEED_5GB_FULL) 895280182Sjfv hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL; 896280182Sjfv 897280182Sjfv if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) 898280182Sjfv hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL; 899280182Sjfv 900185352Sjfv if (speed & IXGBE_LINK_SPEED_1GB_FULL) 901179055Sjfv hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 902179055Sjfv 903190873Sjfv if (speed & IXGBE_LINK_SPEED_100_FULL) 904190873Sjfv hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 905190873Sjfv 906320897Serj if (speed & IXGBE_LINK_SPEED_10_FULL) 907320897Serj hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL; 908320897Serj 909179055Sjfv /* Setup link based on the new speed settings */ 910292674Ssbruno ixgbe_setup_phy_link(hw); 911179055Sjfv 912179055Sjfv return IXGBE_SUCCESS; 913179055Sjfv} 914179055Sjfv 915179055Sjfv/** 916292674Ssbruno * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy 917292674Ssbruno * @hw: pointer to hardware structure 918292674Ssbruno * 919292674Ssbruno * Determines the supported link capabilities by reading the PHY auto 920292674Ssbruno * negotiation register. 921292674Ssbruno **/ 922292674Ssbrunostatic s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw) 923292674Ssbruno{ 924292674Ssbruno s32 status; 925292674Ssbruno u16 speed_ability; 926292674Ssbruno 927292674Ssbruno status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY, 928292674Ssbruno IXGBE_MDIO_PMA_PMD_DEV_TYPE, 929292674Ssbruno &speed_ability); 930292674Ssbruno if (status) 931292674Ssbruno return status; 932292674Ssbruno 933292674Ssbruno if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G) 934292674Ssbruno hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL; 935292674Ssbruno if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G) 936292674Ssbruno hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL; 937292674Ssbruno if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M) 938292674Ssbruno hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL; 939292674Ssbruno 940292674Ssbruno switch (hw->mac.type) { 941292674Ssbruno case ixgbe_mac_X550: 942292674Ssbruno hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL; 943292674Ssbruno hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL; 944292674Ssbruno break; 945292674Ssbruno case ixgbe_mac_X550EM_x: 946320897Serj case ixgbe_mac_X550EM_a: 947292674Ssbruno hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL; 948292674Ssbruno break; 949292674Ssbruno default: 950292674Ssbruno break; 951292674Ssbruno } 952292674Ssbruno 953292674Ssbruno return status; 954292674Ssbruno} 955292674Ssbruno 956292674Ssbruno/** 957190873Sjfv * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities 958190873Sjfv * @hw: pointer to hardware structure 959190873Sjfv * @speed: pointer to link speed 960190873Sjfv * @autoneg: boolean auto-negotiation value 961190873Sjfv **/ 962190873Sjfvs32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 963230775Sjfv ixgbe_link_speed *speed, 964230775Sjfv bool *autoneg) 965190873Sjfv{ 966292674Ssbruno s32 status = IXGBE_SUCCESS; 967190873Sjfv 968200239Sjfv DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic"); 969200239Sjfv 970190873Sjfv *autoneg = TRUE; 971292674Ssbruno if (!hw->phy.speeds_supported) 972292674Ssbruno status = ixgbe_get_copper_speeds_supported(hw); 973190873Sjfv 974292674Ssbruno *speed = hw->phy.speeds_supported; 975190873Sjfv return status; 976190873Sjfv} 977190873Sjfv 978190873Sjfv/** 979179055Sjfv * ixgbe_check_phy_link_tnx - Determine link and speed status 980179055Sjfv * @hw: pointer to hardware structure 981171384Sjfv * 982179055Sjfv * Reads the VS1 register to determine if link is up and the current speed for 983171384Sjfv * the PHY. 984171384Sjfv **/ 985179055Sjfvs32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 986230775Sjfv bool *link_up) 987171384Sjfv{ 988179055Sjfv s32 status = IXGBE_SUCCESS; 989179055Sjfv u32 time_out; 990179055Sjfv u32 max_time_out = 10; 991179055Sjfv u16 phy_link = 0; 992179055Sjfv u16 phy_speed = 0; 993179055Sjfv u16 phy_data = 0; 994179055Sjfv 995200239Sjfv DEBUGFUNC("ixgbe_check_phy_link_tnx"); 996200239Sjfv 997179055Sjfv /* Initialize speed and link to default case */ 998179055Sjfv *link_up = FALSE; 999179055Sjfv *speed = IXGBE_LINK_SPEED_10GB_FULL; 1000179055Sjfv 1001179055Sjfv /* 1002179055Sjfv * Check current speed and link status of the PHY register. 1003179055Sjfv * This is a vendor specific register and may have to 1004179055Sjfv * be changed for other copper PHYs. 1005179055Sjfv */ 1006179055Sjfv for (time_out = 0; time_out < max_time_out; time_out++) { 1007179055Sjfv usec_delay(10); 1008179055Sjfv status = hw->phy.ops.read_reg(hw, 1009230775Sjfv IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS, 1010230775Sjfv IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1011230775Sjfv &phy_data); 1012230775Sjfv phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; 1013179055Sjfv phy_speed = phy_data & 1014230775Sjfv IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; 1015179055Sjfv if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { 1016179055Sjfv *link_up = TRUE; 1017179055Sjfv if (phy_speed == 1018179055Sjfv IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) 1019179055Sjfv *speed = IXGBE_LINK_SPEED_1GB_FULL; 1020179055Sjfv break; 1021179055Sjfv } 1022179055Sjfv } 1023179055Sjfv 1024179055Sjfv return status; 1025171384Sjfv} 1026171384Sjfv 1027171384Sjfv/** 1028280182Sjfv * ixgbe_setup_phy_link_tnx - Set and restart auto-neg 1029200239Sjfv * @hw: pointer to hardware structure 1030200239Sjfv * 1031280182Sjfv * Restart auto-negotiation and PHY and waits for completion. 1032200239Sjfv **/ 1033200239Sjfvs32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) 1034200239Sjfv{ 1035200239Sjfv s32 status = IXGBE_SUCCESS; 1036200239Sjfv u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 1037200239Sjfv bool autoneg = FALSE; 1038200239Sjfv ixgbe_link_speed speed; 1039200239Sjfv 1040200239Sjfv DEBUGFUNC("ixgbe_setup_phy_link_tnx"); 1041200239Sjfv 1042200239Sjfv ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 1043200239Sjfv 1044200239Sjfv if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 1045200239Sjfv /* Set or unset auto-negotiation 10G advertisement */ 1046200239Sjfv hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 1047230775Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1048230775Sjfv &autoneg_reg); 1049200239Sjfv 1050200239Sjfv autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 1051200239Sjfv if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 1052200239Sjfv autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 1053200239Sjfv 1054200239Sjfv hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 1055230775Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1056230775Sjfv autoneg_reg); 1057200239Sjfv } 1058200239Sjfv 1059200239Sjfv if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 1060200239Sjfv /* Set or unset auto-negotiation 1G advertisement */ 1061200239Sjfv hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1062230775Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1063230775Sjfv &autoneg_reg); 1064200239Sjfv 1065200239Sjfv autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1066200239Sjfv if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 1067200239Sjfv autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1068200239Sjfv 1069200239Sjfv hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1070230775Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1071230775Sjfv autoneg_reg); 1072200239Sjfv } 1073200239Sjfv 1074200239Sjfv if (speed & IXGBE_LINK_SPEED_100_FULL) { 1075200239Sjfv /* Set or unset auto-negotiation 100M advertisement */ 1076200239Sjfv hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 1077230775Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1078230775Sjfv &autoneg_reg); 1079200239Sjfv 1080200239Sjfv autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE; 1081200239Sjfv if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 1082200239Sjfv autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 1083200239Sjfv 1084200239Sjfv hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 1085230775Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1086230775Sjfv autoneg_reg); 1087200239Sjfv } 1088200239Sjfv 1089280182Sjfv /* Blocked by MNG FW so don't reset PHY */ 1090280182Sjfv if (ixgbe_check_reset_blocked(hw)) 1091280182Sjfv return status; 1092280182Sjfv 1093280182Sjfv /* Restart PHY auto-negotiation. */ 1094200239Sjfv hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 1095230775Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 1096200239Sjfv 1097200239Sjfv autoneg_reg |= IXGBE_MII_RESTART; 1098200239Sjfv 1099200239Sjfv hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 1100230775Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 1101200239Sjfv 1102200239Sjfv return status; 1103200239Sjfv} 1104200239Sjfv 1105200239Sjfv/** 1106179055Sjfv * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version 1107171384Sjfv * @hw: pointer to hardware structure 1108179055Sjfv * @firmware_version: pointer to the PHY Firmware Version 1109171384Sjfv **/ 1110179055Sjfvs32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, 1111230775Sjfv u16 *firmware_version) 1112171384Sjfv{ 1113280182Sjfv s32 status; 1114179055Sjfv 1115200239Sjfv DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx"); 1116200239Sjfv 1117179055Sjfv status = hw->phy.ops.read_reg(hw, TNX_FW_REV, 1118230775Sjfv IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1119230775Sjfv firmware_version); 1120179055Sjfv 1121179055Sjfv return status; 1122171384Sjfv} 1123171384Sjfv 1124185352Sjfv/** 1125200239Sjfv * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version 1126190873Sjfv * @hw: pointer to hardware structure 1127190873Sjfv * @firmware_version: pointer to the PHY Firmware Version 1128190873Sjfv **/ 1129200239Sjfvs32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, 1130230775Sjfv u16 *firmware_version) 1131190873Sjfv{ 1132280182Sjfv s32 status; 1133190873Sjfv 1134200239Sjfv DEBUGFUNC("ixgbe_get_phy_firmware_version_generic"); 1135200239Sjfv 1136190873Sjfv status = hw->phy.ops.read_reg(hw, AQ_FW_REV, 1137230775Sjfv IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1138230775Sjfv firmware_version); 1139190873Sjfv 1140190873Sjfv return status; 1141190873Sjfv} 1142190873Sjfv 1143190873Sjfv/** 1144185352Sjfv * ixgbe_reset_phy_nl - Performs a PHY reset 1145185352Sjfv * @hw: pointer to hardware structure 1146185352Sjfv **/ 1147185352Sjfvs32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) 1148185352Sjfv{ 1149185352Sjfv u16 phy_offset, control, eword, edata, block_crc; 1150185352Sjfv bool end_data = FALSE; 1151185352Sjfv u16 list_offset, data_offset; 1152185352Sjfv u16 phy_data = 0; 1153185352Sjfv s32 ret_val = IXGBE_SUCCESS; 1154185352Sjfv u32 i; 1155185352Sjfv 1156200239Sjfv DEBUGFUNC("ixgbe_reset_phy_nl"); 1157200239Sjfv 1158280182Sjfv /* Blocked by MNG FW so bail */ 1159280182Sjfv if (ixgbe_check_reset_blocked(hw)) 1160280182Sjfv goto out; 1161280182Sjfv 1162185352Sjfv hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1163230775Sjfv IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 1164185352Sjfv 1165185352Sjfv /* reset the PHY and poll for completion */ 1166185352Sjfv hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1167230775Sjfv IXGBE_MDIO_PHY_XS_DEV_TYPE, 1168230775Sjfv (phy_data | IXGBE_MDIO_PHY_XS_RESET)); 1169185352Sjfv 1170185352Sjfv for (i = 0; i < 100; i++) { 1171185352Sjfv hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1172230775Sjfv IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 1173185352Sjfv if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0) 1174185352Sjfv break; 1175185352Sjfv msec_delay(10); 1176185352Sjfv } 1177185352Sjfv 1178185352Sjfv if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) { 1179185352Sjfv DEBUGOUT("PHY reset did not complete.\n"); 1180185352Sjfv ret_val = IXGBE_ERR_PHY; 1181185352Sjfv goto out; 1182185352Sjfv } 1183185352Sjfv 1184185352Sjfv /* Get init offsets */ 1185185352Sjfv ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 1186230775Sjfv &data_offset); 1187185352Sjfv if (ret_val != IXGBE_SUCCESS) 1188185352Sjfv goto out; 1189185352Sjfv 1190185352Sjfv ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); 1191185352Sjfv data_offset++; 1192185352Sjfv while (!end_data) { 1193185352Sjfv /* 1194185352Sjfv * Read control word from PHY init contents offset 1195185352Sjfv */ 1196185352Sjfv ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); 1197251964Sjfv if (ret_val) 1198251964Sjfv goto err_eeprom; 1199185352Sjfv control = (eword & IXGBE_CONTROL_MASK_NL) >> 1200230775Sjfv IXGBE_CONTROL_SHIFT_NL; 1201185352Sjfv edata = eword & IXGBE_DATA_MASK_NL; 1202185352Sjfv switch (control) { 1203185352Sjfv case IXGBE_DELAY_NL: 1204185352Sjfv data_offset++; 1205185352Sjfv DEBUGOUT1("DELAY: %d MS\n", edata); 1206185352Sjfv msec_delay(edata); 1207185352Sjfv break; 1208185352Sjfv case IXGBE_DATA_NL: 1209230775Sjfv DEBUGOUT("DATA:\n"); 1210185352Sjfv data_offset++; 1211251964Sjfv ret_val = hw->eeprom.ops.read(hw, data_offset, 1212251964Sjfv &phy_offset); 1213251964Sjfv if (ret_val) 1214251964Sjfv goto err_eeprom; 1215251964Sjfv data_offset++; 1216185352Sjfv for (i = 0; i < edata; i++) { 1217251964Sjfv ret_val = hw->eeprom.ops.read(hw, data_offset, 1218251964Sjfv &eword); 1219251964Sjfv if (ret_val) 1220251964Sjfv goto err_eeprom; 1221185352Sjfv hw->phy.ops.write_reg(hw, phy_offset, 1222230775Sjfv IXGBE_TWINAX_DEV, eword); 1223185352Sjfv DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword, 1224230775Sjfv phy_offset); 1225185352Sjfv data_offset++; 1226185352Sjfv phy_offset++; 1227185352Sjfv } 1228185352Sjfv break; 1229185352Sjfv case IXGBE_CONTROL_NL: 1230185352Sjfv data_offset++; 1231230775Sjfv DEBUGOUT("CONTROL:\n"); 1232185352Sjfv if (edata == IXGBE_CONTROL_EOL_NL) { 1233185352Sjfv DEBUGOUT("EOL\n"); 1234185352Sjfv end_data = TRUE; 1235185352Sjfv } else if (edata == IXGBE_CONTROL_SOL_NL) { 1236185352Sjfv DEBUGOUT("SOL\n"); 1237185352Sjfv } else { 1238185352Sjfv DEBUGOUT("Bad control value\n"); 1239185352Sjfv ret_val = IXGBE_ERR_PHY; 1240185352Sjfv goto out; 1241185352Sjfv } 1242185352Sjfv break; 1243185352Sjfv default: 1244185352Sjfv DEBUGOUT("Bad control type\n"); 1245185352Sjfv ret_val = IXGBE_ERR_PHY; 1246185352Sjfv goto out; 1247185352Sjfv } 1248185352Sjfv } 1249185352Sjfv 1250185352Sjfvout: 1251185352Sjfv return ret_val; 1252251964Sjfv 1253251964Sjfverr_eeprom: 1254251964Sjfv ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1255251964Sjfv "eeprom read at offset %d failed", data_offset); 1256251964Sjfv return IXGBE_ERR_PHY; 1257185352Sjfv} 1258185352Sjfv 1259185352Sjfv/** 1260230775Sjfv * ixgbe_identify_module_generic - Identifies module type 1261230775Sjfv * @hw: pointer to hardware structure 1262230775Sjfv * 1263230775Sjfv * Determines HW type and calls appropriate function. 1264230775Sjfv **/ 1265230775Sjfvs32 ixgbe_identify_module_generic(struct ixgbe_hw *hw) 1266230775Sjfv{ 1267230775Sjfv s32 status = IXGBE_ERR_SFP_NOT_PRESENT; 1268230775Sjfv 1269230775Sjfv DEBUGFUNC("ixgbe_identify_module_generic"); 1270230775Sjfv 1271230775Sjfv switch (hw->mac.ops.get_media_type(hw)) { 1272230775Sjfv case ixgbe_media_type_fiber: 1273230775Sjfv status = ixgbe_identify_sfp_module_generic(hw); 1274230775Sjfv break; 1275230775Sjfv 1276280182Sjfv case ixgbe_media_type_fiber_qsfp: 1277280182Sjfv status = ixgbe_identify_qsfp_module_generic(hw); 1278280182Sjfv break; 1279230775Sjfv 1280230775Sjfv default: 1281230775Sjfv hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1282230775Sjfv status = IXGBE_ERR_SFP_NOT_PRESENT; 1283230775Sjfv break; 1284230775Sjfv } 1285230775Sjfv 1286230775Sjfv return status; 1287230775Sjfv} 1288230775Sjfv 1289230775Sjfv/** 1290185352Sjfv * ixgbe_identify_sfp_module_generic - Identifies SFP modules 1291185352Sjfv * @hw: pointer to hardware structure 1292185352Sjfv * 1293185352Sjfv * Searches for and identifies the SFP module and assigns appropriate PHY type. 1294185352Sjfv **/ 1295185352Sjfvs32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) 1296185352Sjfv{ 1297185352Sjfv s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1298185352Sjfv u32 vendor_oui = 0; 1299190873Sjfv enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1300185352Sjfv u8 identifier = 0; 1301185352Sjfv u8 comp_codes_1g = 0; 1302185352Sjfv u8 comp_codes_10g = 0; 1303190873Sjfv u8 oui_bytes[3] = {0, 0, 0}; 1304194875Sjfv u8 cable_tech = 0; 1305205720Sjfv u8 cable_spec = 0; 1306190873Sjfv u16 enforce_sfp = 0; 1307185352Sjfv 1308200239Sjfv DEBUGFUNC("ixgbe_identify_sfp_module_generic"); 1309200239Sjfv 1310194875Sjfv if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) { 1311194875Sjfv hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1312194875Sjfv status = IXGBE_ERR_SFP_NOT_PRESENT; 1313194875Sjfv goto out; 1314215911Sjfv } 1315194875Sjfv 1316280182Sjfv /* LAN ID is needed for I2C access */ 1317280182Sjfv hw->mac.ops.set_lan_id(hw); 1318280182Sjfv 1319215911Sjfv status = hw->phy.ops.read_i2c_eeprom(hw, 1320230775Sjfv IXGBE_SFF_IDENTIFIER, 1321230775Sjfv &identifier); 1322185352Sjfv 1323247822Sjfv if (status != IXGBE_SUCCESS) 1324215911Sjfv goto err_read_i2c_eeprom; 1325185352Sjfv 1326194875Sjfv if (identifier != IXGBE_SFF_IDENTIFIER_SFP) { 1327194875Sjfv hw->phy.type = ixgbe_phy_sfp_unsupported; 1328194875Sjfv status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1329194875Sjfv } else { 1330215911Sjfv status = hw->phy.ops.read_i2c_eeprom(hw, 1331230775Sjfv IXGBE_SFF_1GBE_COMP_CODES, 1332230775Sjfv &comp_codes_1g); 1333185352Sjfv 1334247822Sjfv if (status != IXGBE_SUCCESS) 1335215911Sjfv goto err_read_i2c_eeprom; 1336215911Sjfv 1337215911Sjfv status = hw->phy.ops.read_i2c_eeprom(hw, 1338230775Sjfv IXGBE_SFF_10GBE_COMP_CODES, 1339230775Sjfv &comp_codes_10g); 1340215911Sjfv 1341247822Sjfv if (status != IXGBE_SUCCESS) 1342215911Sjfv goto err_read_i2c_eeprom; 1343215911Sjfv status = hw->phy.ops.read_i2c_eeprom(hw, 1344230775Sjfv IXGBE_SFF_CABLE_TECHNOLOGY, 1345230775Sjfv &cable_tech); 1346215911Sjfv 1347247822Sjfv if (status != IXGBE_SUCCESS) 1348215911Sjfv goto err_read_i2c_eeprom; 1349215911Sjfv 1350185352Sjfv /* ID Module 1351185352Sjfv * ========= 1352185352Sjfv * 0 SFP_DA_CU 1353185352Sjfv * 1 SFP_SR 1354185352Sjfv * 2 SFP_LR 1355190873Sjfv * 3 SFP_DA_CORE0 - 82599-specific 1356190873Sjfv * 4 SFP_DA_CORE1 - 82599-specific 1357190873Sjfv * 5 SFP_SR/LR_CORE0 - 82599-specific 1358190873Sjfv * 6 SFP_SR/LR_CORE1 - 82599-specific 1359205720Sjfv * 7 SFP_act_lmt_DA_CORE0 - 82599-specific 1360205720Sjfv * 8 SFP_act_lmt_DA_CORE1 - 82599-specific 1361215911Sjfv * 9 SFP_1g_cu_CORE0 - 82599-specific 1362215911Sjfv * 10 SFP_1g_cu_CORE1 - 82599-specific 1363238149Sjfv * 11 SFP_1g_sx_CORE0 - 82599-specific 1364238149Sjfv * 12 SFP_1g_sx_CORE1 - 82599-specific 1365185352Sjfv */ 1366190873Sjfv if (hw->mac.type == ixgbe_mac_82598EB) { 1367194875Sjfv if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1368190873Sjfv hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 1369190873Sjfv else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1370190873Sjfv hw->phy.sfp_type = ixgbe_sfp_type_sr; 1371190873Sjfv else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1372190873Sjfv hw->phy.sfp_type = ixgbe_sfp_type_lr; 1373190873Sjfv else 1374190873Sjfv hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1375280182Sjfv } else { 1376205720Sjfv if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) { 1377190873Sjfv if (hw->bus.lan_id == 0) 1378190873Sjfv hw->phy.sfp_type = 1379230775Sjfv ixgbe_sfp_type_da_cu_core0; 1380190873Sjfv else 1381190873Sjfv hw->phy.sfp_type = 1382230775Sjfv ixgbe_sfp_type_da_cu_core1; 1383205720Sjfv } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) { 1384205720Sjfv hw->phy.ops.read_i2c_eeprom( 1385205720Sjfv hw, IXGBE_SFF_CABLE_SPEC_COMP, 1386205720Sjfv &cable_spec); 1387205720Sjfv if (cable_spec & 1388215911Sjfv IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) { 1389205720Sjfv if (hw->bus.lan_id == 0) 1390205720Sjfv hw->phy.sfp_type = 1391205720Sjfv ixgbe_sfp_type_da_act_lmt_core0; 1392205720Sjfv else 1393205720Sjfv hw->phy.sfp_type = 1394205720Sjfv ixgbe_sfp_type_da_act_lmt_core1; 1395215911Sjfv } else { 1396190873Sjfv hw->phy.sfp_type = 1397230775Sjfv ixgbe_sfp_type_unknown; 1398215911Sjfv } 1399205720Sjfv } else if (comp_codes_10g & 1400205720Sjfv (IXGBE_SFF_10GBASESR_CAPABLE | 1401215911Sjfv IXGBE_SFF_10GBASELR_CAPABLE)) { 1402190873Sjfv if (hw->bus.lan_id == 0) 1403190873Sjfv hw->phy.sfp_type = 1404230775Sjfv ixgbe_sfp_type_srlr_core0; 1405190873Sjfv else 1406190873Sjfv hw->phy.sfp_type = 1407230775Sjfv ixgbe_sfp_type_srlr_core1; 1408215911Sjfv } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) { 1409215911Sjfv if (hw->bus.lan_id == 0) 1410215911Sjfv hw->phy.sfp_type = 1411215911Sjfv ixgbe_sfp_type_1g_cu_core0; 1412215911Sjfv else 1413215911Sjfv hw->phy.sfp_type = 1414215911Sjfv ixgbe_sfp_type_1g_cu_core1; 1415238149Sjfv } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) { 1416238149Sjfv if (hw->bus.lan_id == 0) 1417238149Sjfv hw->phy.sfp_type = 1418238149Sjfv ixgbe_sfp_type_1g_sx_core0; 1419238149Sjfv else 1420238149Sjfv hw->phy.sfp_type = 1421238149Sjfv ixgbe_sfp_type_1g_sx_core1; 1422282289Serj } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) { 1423282289Serj if (hw->bus.lan_id == 0) 1424282289Serj hw->phy.sfp_type = 1425282289Serj ixgbe_sfp_type_1g_lx_core0; 1426282289Serj else 1427282289Serj hw->phy.sfp_type = 1428282289Serj ixgbe_sfp_type_1g_lx_core1; 1429205720Sjfv } else { 1430190873Sjfv hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1431205720Sjfv } 1432190873Sjfv } 1433185352Sjfv 1434190873Sjfv if (hw->phy.sfp_type != stored_sfp_type) 1435190873Sjfv hw->phy.sfp_setup_needed = TRUE; 1436190873Sjfv 1437185352Sjfv /* Determine if the SFP+ PHY is dual speed or not. */ 1438194875Sjfv hw->phy.multispeed_fiber = FALSE; 1439190873Sjfv if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1440190873Sjfv (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1441190873Sjfv ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1442190873Sjfv (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1443185352Sjfv hw->phy.multispeed_fiber = TRUE; 1444200239Sjfv 1445185352Sjfv /* Determine PHY vendor */ 1446190873Sjfv if (hw->phy.type != ixgbe_phy_nl) { 1447185352Sjfv hw->phy.id = identifier; 1448215911Sjfv status = hw->phy.ops.read_i2c_eeprom(hw, 1449230775Sjfv IXGBE_SFF_VENDOR_OUI_BYTE0, 1450230775Sjfv &oui_bytes[0]); 1451215911Sjfv 1452247822Sjfv if (status != IXGBE_SUCCESS) 1453215911Sjfv goto err_read_i2c_eeprom; 1454215911Sjfv 1455215911Sjfv status = hw->phy.ops.read_i2c_eeprom(hw, 1456230775Sjfv IXGBE_SFF_VENDOR_OUI_BYTE1, 1457230775Sjfv &oui_bytes[1]); 1458215911Sjfv 1459247822Sjfv if (status != IXGBE_SUCCESS) 1460215911Sjfv goto err_read_i2c_eeprom; 1461215911Sjfv 1462215911Sjfv status = hw->phy.ops.read_i2c_eeprom(hw, 1463230775Sjfv IXGBE_SFF_VENDOR_OUI_BYTE2, 1464230775Sjfv &oui_bytes[2]); 1465185352Sjfv 1466247822Sjfv if (status != IXGBE_SUCCESS) 1467215911Sjfv goto err_read_i2c_eeprom; 1468215911Sjfv 1469185352Sjfv vendor_oui = 1470215911Sjfv ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1471215911Sjfv (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1472215911Sjfv (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1473185352Sjfv 1474185352Sjfv switch (vendor_oui) { 1475185352Sjfv case IXGBE_SFF_VENDOR_OUI_TYCO: 1476194875Sjfv if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1477205720Sjfv hw->phy.type = 1478230775Sjfv ixgbe_phy_sfp_passive_tyco; 1479185352Sjfv break; 1480185352Sjfv case IXGBE_SFF_VENDOR_OUI_FTL: 1481205720Sjfv if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1482205720Sjfv hw->phy.type = ixgbe_phy_sfp_ftl_active; 1483205720Sjfv else 1484205720Sjfv hw->phy.type = ixgbe_phy_sfp_ftl; 1485185352Sjfv break; 1486185352Sjfv case IXGBE_SFF_VENDOR_OUI_AVAGO: 1487185352Sjfv hw->phy.type = ixgbe_phy_sfp_avago; 1488185352Sjfv break; 1489190873Sjfv case IXGBE_SFF_VENDOR_OUI_INTEL: 1490190873Sjfv hw->phy.type = ixgbe_phy_sfp_intel; 1491190873Sjfv break; 1492185352Sjfv default: 1493320897Serj if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1494320897Serj hw->phy.type = 1495320897Serj ixgbe_phy_sfp_passive_unknown; 1496320897Serj else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1497320897Serj hw->phy.type = 1498320897Serj ixgbe_phy_sfp_active_unknown; 1499320897Serj else 1500320897Serj hw->phy.type = ixgbe_phy_sfp_unknown; 1501185352Sjfv break; 1502185352Sjfv } 1503185352Sjfv } 1504190873Sjfv 1505205720Sjfv /* Allow any DA cable vendor */ 1506205720Sjfv if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE | 1507320897Serj IXGBE_SFF_DA_ACTIVE_CABLE)) { 1508194875Sjfv status = IXGBE_SUCCESS; 1509194875Sjfv goto out; 1510194875Sjfv } 1511194875Sjfv 1512215911Sjfv /* Verify supported 1G SFP modules */ 1513215911Sjfv if (comp_codes_10g == 0 && 1514215911Sjfv !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1515238149Sjfv hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1516282289Serj hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1517282289Serj hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1518251964Sjfv hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1519238149Sjfv hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1520190873Sjfv hw->phy.type = ixgbe_phy_sfp_unsupported; 1521190873Sjfv status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1522190873Sjfv goto out; 1523190873Sjfv } 1524194875Sjfv 1525194875Sjfv /* Anything else 82598-based is supported */ 1526194875Sjfv if (hw->mac.type == ixgbe_mac_82598EB) { 1527190873Sjfv status = IXGBE_SUCCESS; 1528190873Sjfv goto out; 1529190873Sjfv } 1530190873Sjfv 1531190873Sjfv ixgbe_get_device_caps(hw, &enforce_sfp); 1532215911Sjfv if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) && 1533251964Sjfv !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1534251964Sjfv hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1535282289Serj hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1536282289Serj hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1537251964Sjfv hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1538251964Sjfv hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1539190873Sjfv /* Make sure we're a supported PHY type */ 1540190873Sjfv if (hw->phy.type == ixgbe_phy_sfp_intel) { 1541190873Sjfv status = IXGBE_SUCCESS; 1542190873Sjfv } else { 1543247056Sdes if (hw->allow_unsupported_sfp == TRUE) { 1544320897Serj EWARN(hw, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n"); 1545247056Sdes status = IXGBE_SUCCESS; 1546247056Sdes } else { 1547247056Sdes DEBUGOUT("SFP+ module not supported\n"); 1548247056Sdes hw->phy.type = 1549247056Sdes ixgbe_phy_sfp_unsupported; 1550247056Sdes status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1551247056Sdes } 1552190873Sjfv } 1553190873Sjfv } else { 1554190873Sjfv status = IXGBE_SUCCESS; 1555190873Sjfv } 1556185352Sjfv } 1557185352Sjfv 1558185352Sjfvout: 1559185352Sjfv return status; 1560215911Sjfv 1561215911Sjfverr_read_i2c_eeprom: 1562215911Sjfv hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1563215911Sjfv if (hw->phy.type != ixgbe_phy_nl) { 1564215911Sjfv hw->phy.id = 0; 1565215911Sjfv hw->phy.type = ixgbe_phy_unknown; 1566215911Sjfv } 1567215911Sjfv return IXGBE_ERR_SFP_NOT_PRESENT; 1568185352Sjfv} 1569185352Sjfv 1570280182Sjfv/** 1571280182Sjfv * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type 1572280182Sjfv * @hw: pointer to hardware structure 1573280182Sjfv * 1574280182Sjfv * Determines physical layer capabilities of the current SFP. 1575280182Sjfv */ 1576320897Serju64 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw) 1577280182Sjfv{ 1578320897Serj u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1579280182Sjfv u8 comp_codes_10g = 0; 1580280182Sjfv u8 comp_codes_1g = 0; 1581230775Sjfv 1582280182Sjfv DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic"); 1583230775Sjfv 1584280182Sjfv hw->phy.ops.identify_sfp(hw); 1585280182Sjfv if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1586280182Sjfv return physical_layer; 1587280182Sjfv 1588280182Sjfv switch (hw->phy.type) { 1589280182Sjfv case ixgbe_phy_sfp_passive_tyco: 1590280182Sjfv case ixgbe_phy_sfp_passive_unknown: 1591280182Sjfv case ixgbe_phy_qsfp_passive_unknown: 1592280182Sjfv physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1593280182Sjfv break; 1594280182Sjfv case ixgbe_phy_sfp_ftl_active: 1595280182Sjfv case ixgbe_phy_sfp_active_unknown: 1596280182Sjfv case ixgbe_phy_qsfp_active_unknown: 1597280182Sjfv physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA; 1598280182Sjfv break; 1599280182Sjfv case ixgbe_phy_sfp_avago: 1600280182Sjfv case ixgbe_phy_sfp_ftl: 1601280182Sjfv case ixgbe_phy_sfp_intel: 1602280182Sjfv case ixgbe_phy_sfp_unknown: 1603280182Sjfv hw->phy.ops.read_i2c_eeprom(hw, 1604280182Sjfv IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g); 1605280182Sjfv hw->phy.ops.read_i2c_eeprom(hw, 1606280182Sjfv IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g); 1607280182Sjfv if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1608280182Sjfv physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1609280182Sjfv else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1610280182Sjfv physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1611280182Sjfv else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) 1612280182Sjfv physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T; 1613280182Sjfv else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) 1614280182Sjfv physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX; 1615280182Sjfv break; 1616280182Sjfv case ixgbe_phy_qsfp_intel: 1617280182Sjfv case ixgbe_phy_qsfp_unknown: 1618280182Sjfv hw->phy.ops.read_i2c_eeprom(hw, 1619280182Sjfv IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g); 1620280182Sjfv if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1621280182Sjfv physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1622280182Sjfv else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1623280182Sjfv physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1624280182Sjfv break; 1625280182Sjfv default: 1626280182Sjfv break; 1627280182Sjfv } 1628280182Sjfv 1629280182Sjfv return physical_layer; 1630280182Sjfv} 1631280182Sjfv 1632185352Sjfv/** 1633280182Sjfv * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules 1634280182Sjfv * @hw: pointer to hardware structure 1635280182Sjfv * 1636280182Sjfv * Searches for and identifies the QSFP module and assigns appropriate PHY type 1637280182Sjfv **/ 1638280182Sjfvs32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw) 1639280182Sjfv{ 1640280182Sjfv s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1641280182Sjfv u32 vendor_oui = 0; 1642280182Sjfv enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1643280182Sjfv u8 identifier = 0; 1644280182Sjfv u8 comp_codes_1g = 0; 1645280182Sjfv u8 comp_codes_10g = 0; 1646280182Sjfv u8 oui_bytes[3] = {0, 0, 0}; 1647280182Sjfv u16 enforce_sfp = 0; 1648280182Sjfv u8 connector = 0; 1649280182Sjfv u8 cable_length = 0; 1650280182Sjfv u8 device_tech = 0; 1651280182Sjfv bool active_cable = FALSE; 1652280182Sjfv 1653280182Sjfv DEBUGFUNC("ixgbe_identify_qsfp_module_generic"); 1654280182Sjfv 1655280182Sjfv if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) { 1656280182Sjfv hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1657280182Sjfv status = IXGBE_ERR_SFP_NOT_PRESENT; 1658280182Sjfv goto out; 1659280182Sjfv } 1660280182Sjfv 1661282289Serj /* LAN ID is needed for I2C access */ 1662282289Serj hw->mac.ops.set_lan_id(hw); 1663282289Serj 1664280182Sjfv status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER, 1665280182Sjfv &identifier); 1666280182Sjfv 1667280182Sjfv if (status != IXGBE_SUCCESS) 1668280182Sjfv goto err_read_i2c_eeprom; 1669280182Sjfv 1670280182Sjfv if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) { 1671280182Sjfv hw->phy.type = ixgbe_phy_sfp_unsupported; 1672280182Sjfv status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1673280182Sjfv goto out; 1674280182Sjfv } 1675280182Sjfv 1676280182Sjfv hw->phy.id = identifier; 1677280182Sjfv 1678280182Sjfv status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP, 1679280182Sjfv &comp_codes_10g); 1680280182Sjfv 1681280182Sjfv if (status != IXGBE_SUCCESS) 1682280182Sjfv goto err_read_i2c_eeprom; 1683280182Sjfv 1684280182Sjfv status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP, 1685280182Sjfv &comp_codes_1g); 1686280182Sjfv 1687280182Sjfv if (status != IXGBE_SUCCESS) 1688280182Sjfv goto err_read_i2c_eeprom; 1689280182Sjfv 1690280182Sjfv if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) { 1691280182Sjfv hw->phy.type = ixgbe_phy_qsfp_passive_unknown; 1692280182Sjfv if (hw->bus.lan_id == 0) 1693280182Sjfv hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0; 1694280182Sjfv else 1695280182Sjfv hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1; 1696280182Sjfv } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1697280182Sjfv IXGBE_SFF_10GBASELR_CAPABLE)) { 1698280182Sjfv if (hw->bus.lan_id == 0) 1699280182Sjfv hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0; 1700280182Sjfv else 1701280182Sjfv hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1; 1702280182Sjfv } else { 1703280182Sjfv if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE) 1704280182Sjfv active_cable = TRUE; 1705280182Sjfv 1706280182Sjfv if (!active_cable) { 1707280182Sjfv /* check for active DA cables that pre-date 1708280182Sjfv * SFF-8436 v3.6 */ 1709280182Sjfv hw->phy.ops.read_i2c_eeprom(hw, 1710280182Sjfv IXGBE_SFF_QSFP_CONNECTOR, 1711280182Sjfv &connector); 1712280182Sjfv 1713280182Sjfv hw->phy.ops.read_i2c_eeprom(hw, 1714280182Sjfv IXGBE_SFF_QSFP_CABLE_LENGTH, 1715280182Sjfv &cable_length); 1716280182Sjfv 1717280182Sjfv hw->phy.ops.read_i2c_eeprom(hw, 1718280182Sjfv IXGBE_SFF_QSFP_DEVICE_TECH, 1719280182Sjfv &device_tech); 1720280182Sjfv 1721280182Sjfv if ((connector == 1722280182Sjfv IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) && 1723280182Sjfv (cable_length > 0) && 1724280182Sjfv ((device_tech >> 4) == 1725280182Sjfv IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL)) 1726280182Sjfv active_cable = TRUE; 1727280182Sjfv } 1728280182Sjfv 1729280182Sjfv if (active_cable) { 1730280182Sjfv hw->phy.type = ixgbe_phy_qsfp_active_unknown; 1731280182Sjfv if (hw->bus.lan_id == 0) 1732280182Sjfv hw->phy.sfp_type = 1733280182Sjfv ixgbe_sfp_type_da_act_lmt_core0; 1734280182Sjfv else 1735280182Sjfv hw->phy.sfp_type = 1736280182Sjfv ixgbe_sfp_type_da_act_lmt_core1; 1737280182Sjfv } else { 1738280182Sjfv /* unsupported module type */ 1739280182Sjfv hw->phy.type = ixgbe_phy_sfp_unsupported; 1740280182Sjfv status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1741280182Sjfv goto out; 1742280182Sjfv } 1743280182Sjfv } 1744280182Sjfv 1745280182Sjfv if (hw->phy.sfp_type != stored_sfp_type) 1746280182Sjfv hw->phy.sfp_setup_needed = TRUE; 1747280182Sjfv 1748280182Sjfv /* Determine if the QSFP+ PHY is dual speed or not. */ 1749280182Sjfv hw->phy.multispeed_fiber = FALSE; 1750280182Sjfv if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1751280182Sjfv (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1752280182Sjfv ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1753280182Sjfv (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1754280182Sjfv hw->phy.multispeed_fiber = TRUE; 1755280182Sjfv 1756280182Sjfv /* Determine PHY vendor for optical modules */ 1757280182Sjfv if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1758280182Sjfv IXGBE_SFF_10GBASELR_CAPABLE)) { 1759280182Sjfv status = hw->phy.ops.read_i2c_eeprom(hw, 1760280182Sjfv IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0, 1761280182Sjfv &oui_bytes[0]); 1762280182Sjfv 1763280182Sjfv if (status != IXGBE_SUCCESS) 1764280182Sjfv goto err_read_i2c_eeprom; 1765280182Sjfv 1766280182Sjfv status = hw->phy.ops.read_i2c_eeprom(hw, 1767280182Sjfv IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1, 1768280182Sjfv &oui_bytes[1]); 1769280182Sjfv 1770280182Sjfv if (status != IXGBE_SUCCESS) 1771280182Sjfv goto err_read_i2c_eeprom; 1772280182Sjfv 1773280182Sjfv status = hw->phy.ops.read_i2c_eeprom(hw, 1774280182Sjfv IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2, 1775280182Sjfv &oui_bytes[2]); 1776280182Sjfv 1777280182Sjfv if (status != IXGBE_SUCCESS) 1778280182Sjfv goto err_read_i2c_eeprom; 1779280182Sjfv 1780280182Sjfv vendor_oui = 1781280182Sjfv ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1782280182Sjfv (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1783280182Sjfv (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1784280182Sjfv 1785280182Sjfv if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL) 1786280182Sjfv hw->phy.type = ixgbe_phy_qsfp_intel; 1787280182Sjfv else 1788280182Sjfv hw->phy.type = ixgbe_phy_qsfp_unknown; 1789280182Sjfv 1790280182Sjfv ixgbe_get_device_caps(hw, &enforce_sfp); 1791280182Sjfv if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) { 1792280182Sjfv /* Make sure we're a supported PHY type */ 1793280182Sjfv if (hw->phy.type == ixgbe_phy_qsfp_intel) { 1794280182Sjfv status = IXGBE_SUCCESS; 1795280182Sjfv } else { 1796280182Sjfv if (hw->allow_unsupported_sfp == TRUE) { 1797320897Serj EWARN(hw, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n"); 1798280182Sjfv status = IXGBE_SUCCESS; 1799280182Sjfv } else { 1800280182Sjfv DEBUGOUT("QSFP module not supported\n"); 1801280182Sjfv hw->phy.type = 1802280182Sjfv ixgbe_phy_sfp_unsupported; 1803280182Sjfv status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1804280182Sjfv } 1805280182Sjfv } 1806280182Sjfv } else { 1807280182Sjfv status = IXGBE_SUCCESS; 1808280182Sjfv } 1809280182Sjfv } 1810280182Sjfv 1811280182Sjfvout: 1812280182Sjfv return status; 1813280182Sjfv 1814280182Sjfverr_read_i2c_eeprom: 1815280182Sjfv hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1816280182Sjfv hw->phy.id = 0; 1817280182Sjfv hw->phy.type = ixgbe_phy_unknown; 1818280182Sjfv 1819280182Sjfv return IXGBE_ERR_SFP_NOT_PRESENT; 1820280182Sjfv} 1821280182Sjfv 1822280182Sjfv/** 1823185352Sjfv * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence 1824185352Sjfv * @hw: pointer to hardware structure 1825185352Sjfv * @list_offset: offset to the SFP ID list 1826185352Sjfv * @data_offset: offset to the SFP data block 1827185352Sjfv * 1828185352Sjfv * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if 1829185352Sjfv * so it returns the offsets to the phy init sequence block. 1830185352Sjfv **/ 1831185352Sjfvs32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 1832230775Sjfv u16 *list_offset, 1833230775Sjfv u16 *data_offset) 1834185352Sjfv{ 1835185352Sjfv u16 sfp_id; 1836205720Sjfv u16 sfp_type = hw->phy.sfp_type; 1837185352Sjfv 1838200239Sjfv DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets"); 1839200239Sjfv 1840185352Sjfv if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 1841185352Sjfv return IXGBE_ERR_SFP_NOT_SUPPORTED; 1842185352Sjfv 1843185352Sjfv if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1844185352Sjfv return IXGBE_ERR_SFP_NOT_PRESENT; 1845185352Sjfv 1846185352Sjfv if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && 1847185352Sjfv (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) 1848185352Sjfv return IXGBE_ERR_SFP_NOT_SUPPORTED; 1849185352Sjfv 1850215911Sjfv /* 1851215911Sjfv * Limiting active cables and 1G Phys must be initialized as 1852215911Sjfv * SR modules 1853215911Sjfv */ 1854215911Sjfv if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 || 1855282289Serj sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1856238149Sjfv sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1857238149Sjfv sfp_type == ixgbe_sfp_type_1g_sx_core0) 1858205720Sjfv sfp_type = ixgbe_sfp_type_srlr_core0; 1859215911Sjfv else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 || 1860282289Serj sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1861238149Sjfv sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1862238149Sjfv sfp_type == ixgbe_sfp_type_1g_sx_core1) 1863205720Sjfv sfp_type = ixgbe_sfp_type_srlr_core1; 1864205720Sjfv 1865185352Sjfv /* Read offset to PHY init contents */ 1866251964Sjfv if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) { 1867251964Sjfv ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1868251964Sjfv "eeprom read at offset %d failed", 1869251964Sjfv IXGBE_PHY_INIT_OFFSET_NL); 1870251964Sjfv return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1871251964Sjfv } 1872185352Sjfv 1873185352Sjfv if ((!*list_offset) || (*list_offset == 0xFFFF)) 1874190873Sjfv return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1875185352Sjfv 1876185352Sjfv /* Shift offset to first ID word */ 1877185352Sjfv (*list_offset)++; 1878185352Sjfv 1879185352Sjfv /* 1880185352Sjfv * Find the matching SFP ID in the EEPROM 1881185352Sjfv * and program the init sequence 1882185352Sjfv */ 1883251964Sjfv if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1884251964Sjfv goto err_phy; 1885185352Sjfv 1886185352Sjfv while (sfp_id != IXGBE_PHY_INIT_END_NL) { 1887205720Sjfv if (sfp_id == sfp_type) { 1888185352Sjfv (*list_offset)++; 1889251964Sjfv if (hw->eeprom.ops.read(hw, *list_offset, data_offset)) 1890251964Sjfv goto err_phy; 1891185352Sjfv if ((!*data_offset) || (*data_offset == 0xFFFF)) { 1892185352Sjfv DEBUGOUT("SFP+ module not supported\n"); 1893185352Sjfv return IXGBE_ERR_SFP_NOT_SUPPORTED; 1894185352Sjfv } else { 1895185352Sjfv break; 1896185352Sjfv } 1897185352Sjfv } else { 1898185352Sjfv (*list_offset) += 2; 1899185352Sjfv if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1900251964Sjfv goto err_phy; 1901185352Sjfv } 1902185352Sjfv } 1903185352Sjfv 1904185352Sjfv if (sfp_id == IXGBE_PHY_INIT_END_NL) { 1905185352Sjfv DEBUGOUT("No matching SFP+ module found\n"); 1906185352Sjfv return IXGBE_ERR_SFP_NOT_SUPPORTED; 1907185352Sjfv } 1908185352Sjfv 1909185352Sjfv return IXGBE_SUCCESS; 1910251964Sjfv 1911251964Sjfverr_phy: 1912251964Sjfv ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1913251964Sjfv "eeprom read at offset %d failed", *list_offset); 1914251964Sjfv return IXGBE_ERR_PHY; 1915185352Sjfv} 1916185352Sjfv 1917190873Sjfv/** 1918190873Sjfv * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface 1919190873Sjfv * @hw: pointer to hardware structure 1920190873Sjfv * @byte_offset: EEPROM byte offset to read 1921190873Sjfv * @eeprom_data: value read 1922190873Sjfv * 1923190873Sjfv * Performs byte read operation to SFP module's EEPROM over I2C interface. 1924190873Sjfv **/ 1925190873Sjfvs32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1926230775Sjfv u8 *eeprom_data) 1927190873Sjfv{ 1928190873Sjfv DEBUGFUNC("ixgbe_read_i2c_eeprom_generic"); 1929190873Sjfv 1930190873Sjfv return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1931230775Sjfv IXGBE_I2C_EEPROM_DEV_ADDR, 1932230775Sjfv eeprom_data); 1933190873Sjfv} 1934190873Sjfv 1935190873Sjfv/** 1936247822Sjfv * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface 1937247822Sjfv * @hw: pointer to hardware structure 1938247822Sjfv * @byte_offset: byte offset at address 0xA2 1939247822Sjfv * @eeprom_data: value read 1940247822Sjfv * 1941247822Sjfv * Performs byte read operation to SFP module's SFF-8472 data over I2C 1942247822Sjfv **/ 1943247822Sjfvstatic s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 1944247822Sjfv u8 *sff8472_data) 1945247822Sjfv{ 1946247822Sjfv return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1947247822Sjfv IXGBE_I2C_EEPROM_DEV_ADDR2, 1948247822Sjfv sff8472_data); 1949247822Sjfv} 1950247822Sjfv 1951247822Sjfv/** 1952190873Sjfv * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface 1953190873Sjfv * @hw: pointer to hardware structure 1954190873Sjfv * @byte_offset: EEPROM byte offset to write 1955190873Sjfv * @eeprom_data: value to write 1956190873Sjfv * 1957190873Sjfv * Performs byte write operation to SFP module's EEPROM over I2C interface. 1958190873Sjfv **/ 1959190873Sjfvs32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1960230775Sjfv u8 eeprom_data) 1961190873Sjfv{ 1962190873Sjfv DEBUGFUNC("ixgbe_write_i2c_eeprom_generic"); 1963190873Sjfv 1964190873Sjfv return hw->phy.ops.write_i2c_byte(hw, byte_offset, 1965230775Sjfv IXGBE_I2C_EEPROM_DEV_ADDR, 1966230775Sjfv eeprom_data); 1967190873Sjfv} 1968190873Sjfv 1969190873Sjfv/** 1970280182Sjfv * ixgbe_is_sfp_probe - Returns TRUE if SFP is being detected 1971280182Sjfv * @hw: pointer to hardware structure 1972280182Sjfv * @offset: eeprom offset to be read 1973280182Sjfv * @addr: I2C address to be read 1974280182Sjfv */ 1975280182Sjfvstatic bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr) 1976280182Sjfv{ 1977280182Sjfv if (addr == IXGBE_I2C_EEPROM_DEV_ADDR && 1978280182Sjfv offset == IXGBE_SFF_IDENTIFIER && 1979280182Sjfv hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1980280182Sjfv return TRUE; 1981280182Sjfv return FALSE; 1982280182Sjfv} 1983280182Sjfv 1984280182Sjfv/** 1985282289Serj * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C 1986190873Sjfv * @hw: pointer to hardware structure 1987190873Sjfv * @byte_offset: byte offset to read 1988190873Sjfv * @data: value read 1989282289Serj * @lock: TRUE if to take and release semaphore 1990190873Sjfv * 1991190873Sjfv * Performs byte read operation to SFP module's EEPROM over I2C interface at 1992230775Sjfv * a specified device address. 1993190873Sjfv **/ 1994282289Serjstatic s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, 1995282289Serj u8 dev_addr, u8 *data, bool lock) 1996190873Sjfv{ 1997280182Sjfv s32 status; 1998194875Sjfv u32 max_retry = 10; 1999190873Sjfv u32 retry = 0; 2000280182Sjfv u32 swfw_mask = hw->phy.phy_semaphore_mask; 2001190873Sjfv bool nack = 1; 2002230775Sjfv *data = 0; 2003190873Sjfv 2004190873Sjfv DEBUGFUNC("ixgbe_read_i2c_byte_generic"); 2005190873Sjfv 2006282289Serj if (hw->mac.type >= ixgbe_mac_X550) 2007282289Serj max_retry = 3; 2008280182Sjfv if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr)) 2009280182Sjfv max_retry = IXGBE_SFP_DETECT_RETRIES; 2010190873Sjfv 2011190873Sjfv do { 2012282289Serj if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 2013280182Sjfv return IXGBE_ERR_SWFW_SYNC; 2014194875Sjfv 2015190873Sjfv ixgbe_i2c_start(hw); 2016190873Sjfv 2017190873Sjfv /* Device Address and write indication */ 2018190873Sjfv status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 2019190873Sjfv if (status != IXGBE_SUCCESS) 2020190873Sjfv goto fail; 2021190873Sjfv 2022190873Sjfv status = ixgbe_get_i2c_ack(hw); 2023190873Sjfv if (status != IXGBE_SUCCESS) 2024190873Sjfv goto fail; 2025190873Sjfv 2026190873Sjfv status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 2027190873Sjfv if (status != IXGBE_SUCCESS) 2028190873Sjfv goto fail; 2029190873Sjfv 2030190873Sjfv status = ixgbe_get_i2c_ack(hw); 2031190873Sjfv if (status != IXGBE_SUCCESS) 2032190873Sjfv goto fail; 2033190873Sjfv 2034190873Sjfv ixgbe_i2c_start(hw); 2035190873Sjfv 2036190873Sjfv /* Device Address and read indication */ 2037190873Sjfv status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 2038190873Sjfv if (status != IXGBE_SUCCESS) 2039190873Sjfv goto fail; 2040190873Sjfv 2041190873Sjfv status = ixgbe_get_i2c_ack(hw); 2042190873Sjfv if (status != IXGBE_SUCCESS) 2043190873Sjfv goto fail; 2044190873Sjfv 2045190873Sjfv status = ixgbe_clock_in_i2c_byte(hw, data); 2046190873Sjfv if (status != IXGBE_SUCCESS) 2047190873Sjfv goto fail; 2048190873Sjfv 2049190873Sjfv status = ixgbe_clock_out_i2c_bit(hw, nack); 2050190873Sjfv if (status != IXGBE_SUCCESS) 2051190873Sjfv goto fail; 2052190873Sjfv 2053190873Sjfv ixgbe_i2c_stop(hw); 2054282289Serj if (lock) 2055282289Serj hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2056280182Sjfv return IXGBE_SUCCESS; 2057190873Sjfv 2058190873Sjfvfail: 2059247822Sjfv ixgbe_i2c_bus_clear(hw); 2060282289Serj if (lock) { 2061282289Serj hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2062282289Serj msec_delay(100); 2063282289Serj } 2064190873Sjfv retry++; 2065190873Sjfv if (retry < max_retry) 2066190873Sjfv DEBUGOUT("I2C byte read error - Retrying.\n"); 2067190873Sjfv else 2068190873Sjfv DEBUGOUT("I2C byte read error.\n"); 2069190873Sjfv 2070190873Sjfv } while (retry < max_retry); 2071190873Sjfv 2072190873Sjfv return status; 2073190873Sjfv} 2074190873Sjfv 2075190873Sjfv/** 2076282289Serj * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C 2077190873Sjfv * @hw: pointer to hardware structure 2078282289Serj * @byte_offset: byte offset to read 2079282289Serj * @data: value read 2080282289Serj * 2081282289Serj * Performs byte read operation to SFP module's EEPROM over I2C interface at 2082282289Serj * a specified device address. 2083282289Serj **/ 2084282289Serjs32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 2085282289Serj u8 dev_addr, u8 *data) 2086282289Serj{ 2087282289Serj return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2088282289Serj data, TRUE); 2089282289Serj} 2090282289Serj 2091282289Serj/** 2092282289Serj * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C 2093282289Serj * @hw: pointer to hardware structure 2094282289Serj * @byte_offset: byte offset to read 2095282289Serj * @data: value read 2096282289Serj * 2097282289Serj * Performs byte read operation to SFP module's EEPROM over I2C interface at 2098282289Serj * a specified device address. 2099282289Serj **/ 2100282289Serjs32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 2101282289Serj u8 dev_addr, u8 *data) 2102282289Serj{ 2103282289Serj return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2104282289Serj data, FALSE); 2105282289Serj} 2106282289Serj 2107282289Serj/** 2108282289Serj * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C 2109282289Serj * @hw: pointer to hardware structure 2110190873Sjfv * @byte_offset: byte offset to write 2111190873Sjfv * @data: value to write 2112282289Serj * @lock: TRUE if to take and release semaphore 2113190873Sjfv * 2114190873Sjfv * Performs byte write operation to SFP module's EEPROM over I2C interface at 2115190873Sjfv * a specified device address. 2116190873Sjfv **/ 2117282289Serjstatic s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, 2118282289Serj u8 dev_addr, u8 data, bool lock) 2119190873Sjfv{ 2120282289Serj s32 status; 2121190873Sjfv u32 max_retry = 1; 2122190873Sjfv u32 retry = 0; 2123280182Sjfv u32 swfw_mask = hw->phy.phy_semaphore_mask; 2124190873Sjfv 2125190873Sjfv DEBUGFUNC("ixgbe_write_i2c_byte_generic"); 2126190873Sjfv 2127282289Serj if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 2128282289Serj IXGBE_SUCCESS) 2129282289Serj return IXGBE_ERR_SWFW_SYNC; 2130190873Sjfv 2131190873Sjfv do { 2132190873Sjfv ixgbe_i2c_start(hw); 2133190873Sjfv 2134190873Sjfv status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 2135190873Sjfv if (status != IXGBE_SUCCESS) 2136190873Sjfv goto fail; 2137190873Sjfv 2138190873Sjfv status = ixgbe_get_i2c_ack(hw); 2139190873Sjfv if (status != IXGBE_SUCCESS) 2140190873Sjfv goto fail; 2141190873Sjfv 2142190873Sjfv status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 2143190873Sjfv if (status != IXGBE_SUCCESS) 2144190873Sjfv goto fail; 2145190873Sjfv 2146190873Sjfv status = ixgbe_get_i2c_ack(hw); 2147190873Sjfv if (status != IXGBE_SUCCESS) 2148190873Sjfv goto fail; 2149190873Sjfv 2150190873Sjfv status = ixgbe_clock_out_i2c_byte(hw, data); 2151190873Sjfv if (status != IXGBE_SUCCESS) 2152190873Sjfv goto fail; 2153190873Sjfv 2154190873Sjfv status = ixgbe_get_i2c_ack(hw); 2155190873Sjfv if (status != IXGBE_SUCCESS) 2156190873Sjfv goto fail; 2157190873Sjfv 2158190873Sjfv ixgbe_i2c_stop(hw); 2159282289Serj if (lock) 2160282289Serj hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2161280182Sjfv return IXGBE_SUCCESS; 2162190873Sjfv 2163190873Sjfvfail: 2164190873Sjfv ixgbe_i2c_bus_clear(hw); 2165190873Sjfv retry++; 2166190873Sjfv if (retry < max_retry) 2167190873Sjfv DEBUGOUT("I2C byte write error - Retrying.\n"); 2168190873Sjfv else 2169190873Sjfv DEBUGOUT("I2C byte write error.\n"); 2170190873Sjfv } while (retry < max_retry); 2171190873Sjfv 2172282289Serj if (lock) 2173282289Serj hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2174190873Sjfv 2175190873Sjfv return status; 2176190873Sjfv} 2177190873Sjfv 2178190873Sjfv/** 2179282289Serj * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C 2180282289Serj * @hw: pointer to hardware structure 2181282289Serj * @byte_offset: byte offset to write 2182282289Serj * @data: value to write 2183282289Serj * 2184282289Serj * Performs byte write operation to SFP module's EEPROM over I2C interface at 2185282289Serj * a specified device address. 2186282289Serj **/ 2187282289Serjs32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 2188282289Serj u8 dev_addr, u8 data) 2189282289Serj{ 2190282289Serj return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2191282289Serj data, TRUE); 2192282289Serj} 2193282289Serj 2194282289Serj/** 2195282289Serj * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C 2196282289Serj * @hw: pointer to hardware structure 2197282289Serj * @byte_offset: byte offset to write 2198282289Serj * @data: value to write 2199282289Serj * 2200282289Serj * Performs byte write operation to SFP module's EEPROM over I2C interface at 2201282289Serj * a specified device address. 2202282289Serj **/ 2203282289Serjs32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 2204282289Serj u8 dev_addr, u8 data) 2205282289Serj{ 2206282289Serj return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2207282289Serj data, FALSE); 2208282289Serj} 2209282289Serj 2210282289Serj/** 2211190873Sjfv * ixgbe_i2c_start - Sets I2C start condition 2212190873Sjfv * @hw: pointer to hardware structure 2213190873Sjfv * 2214190873Sjfv * Sets I2C start condition (High -> Low on SDA while SCL is High) 2215280182Sjfv * Set bit-bang mode on X550 hardware. 2216190873Sjfv **/ 2217190873Sjfvstatic void ixgbe_i2c_start(struct ixgbe_hw *hw) 2218190873Sjfv{ 2219280182Sjfv u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2220190873Sjfv 2221190873Sjfv DEBUGFUNC("ixgbe_i2c_start"); 2222190873Sjfv 2223280182Sjfv i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw); 2224280182Sjfv 2225190873Sjfv /* Start condition must begin with data and clock high */ 2226190873Sjfv ixgbe_set_i2c_data(hw, &i2cctl, 1); 2227190873Sjfv ixgbe_raise_i2c_clk(hw, &i2cctl); 2228190873Sjfv 2229190873Sjfv /* Setup time for start condition (4.7us) */ 2230190873Sjfv usec_delay(IXGBE_I2C_T_SU_STA); 2231190873Sjfv 2232190873Sjfv ixgbe_set_i2c_data(hw, &i2cctl, 0); 2233190873Sjfv 2234190873Sjfv /* Hold time for start condition (4us) */ 2235190873Sjfv usec_delay(IXGBE_I2C_T_HD_STA); 2236190873Sjfv 2237190873Sjfv ixgbe_lower_i2c_clk(hw, &i2cctl); 2238190873Sjfv 2239190873Sjfv /* Minimum low period of clock is 4.7 us */ 2240190873Sjfv usec_delay(IXGBE_I2C_T_LOW); 2241190873Sjfv 2242190873Sjfv} 2243190873Sjfv 2244190873Sjfv/** 2245190873Sjfv * ixgbe_i2c_stop - Sets I2C stop condition 2246190873Sjfv * @hw: pointer to hardware structure 2247190873Sjfv * 2248190873Sjfv * Sets I2C stop condition (Low -> High on SDA while SCL is High) 2249280182Sjfv * Disables bit-bang mode and negates data output enable on X550 2250280182Sjfv * hardware. 2251190873Sjfv **/ 2252190873Sjfvstatic void ixgbe_i2c_stop(struct ixgbe_hw *hw) 2253190873Sjfv{ 2254280182Sjfv u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2255280182Sjfv u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2256280182Sjfv u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2257280182Sjfv u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw); 2258190873Sjfv 2259190873Sjfv DEBUGFUNC("ixgbe_i2c_stop"); 2260190873Sjfv 2261190873Sjfv /* Stop condition must begin with data low and clock high */ 2262190873Sjfv ixgbe_set_i2c_data(hw, &i2cctl, 0); 2263190873Sjfv ixgbe_raise_i2c_clk(hw, &i2cctl); 2264190873Sjfv 2265190873Sjfv /* Setup time for stop condition (4us) */ 2266190873Sjfv usec_delay(IXGBE_I2C_T_SU_STO); 2267190873Sjfv 2268190873Sjfv ixgbe_set_i2c_data(hw, &i2cctl, 1); 2269190873Sjfv 2270190873Sjfv /* bus free time between stop and start (4.7us)*/ 2271190873Sjfv usec_delay(IXGBE_I2C_T_BUF); 2272280182Sjfv 2273280182Sjfv if (bb_en_bit || data_oe_bit || clk_oe_bit) { 2274280182Sjfv i2cctl &= ~bb_en_bit; 2275280182Sjfv i2cctl |= data_oe_bit | clk_oe_bit; 2276280182Sjfv IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2277280182Sjfv IXGBE_WRITE_FLUSH(hw); 2278280182Sjfv } 2279190873Sjfv} 2280190873Sjfv 2281190873Sjfv/** 2282190873Sjfv * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C 2283190873Sjfv * @hw: pointer to hardware structure 2284190873Sjfv * @data: data byte to clock in 2285190873Sjfv * 2286190873Sjfv * Clocks in one byte data via I2C data/clock 2287190873Sjfv **/ 2288190873Sjfvstatic s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data) 2289190873Sjfv{ 2290190873Sjfv s32 i; 2291190873Sjfv bool bit = 0; 2292190873Sjfv 2293190873Sjfv DEBUGFUNC("ixgbe_clock_in_i2c_byte"); 2294190873Sjfv 2295280182Sjfv *data = 0; 2296190873Sjfv for (i = 7; i >= 0; i--) { 2297230775Sjfv ixgbe_clock_in_i2c_bit(hw, &bit); 2298215911Sjfv *data |= bit << i; 2299190873Sjfv } 2300190873Sjfv 2301230775Sjfv return IXGBE_SUCCESS; 2302190873Sjfv} 2303190873Sjfv 2304190873Sjfv/** 2305190873Sjfv * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C 2306190873Sjfv * @hw: pointer to hardware structure 2307190873Sjfv * @data: data byte clocked out 2308190873Sjfv * 2309190873Sjfv * Clocks out one byte data via I2C data/clock 2310190873Sjfv **/ 2311190873Sjfvstatic s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data) 2312190873Sjfv{ 2313190873Sjfv s32 status = IXGBE_SUCCESS; 2314190873Sjfv s32 i; 2315190873Sjfv u32 i2cctl; 2316280182Sjfv bool bit; 2317190873Sjfv 2318190873Sjfv DEBUGFUNC("ixgbe_clock_out_i2c_byte"); 2319190873Sjfv 2320190873Sjfv for (i = 7; i >= 0; i--) { 2321190873Sjfv bit = (data >> i) & 0x1; 2322190873Sjfv status = ixgbe_clock_out_i2c_bit(hw, bit); 2323190873Sjfv 2324190873Sjfv if (status != IXGBE_SUCCESS) 2325190873Sjfv break; 2326190873Sjfv } 2327190873Sjfv 2328190873Sjfv /* Release SDA line (set high) */ 2329280182Sjfv i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2330280182Sjfv i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2331280182Sjfv i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2332280182Sjfv IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2333230775Sjfv IXGBE_WRITE_FLUSH(hw); 2334190873Sjfv 2335190873Sjfv return status; 2336190873Sjfv} 2337190873Sjfv 2338190873Sjfv/** 2339190873Sjfv * ixgbe_get_i2c_ack - Polls for I2C ACK 2340190873Sjfv * @hw: pointer to hardware structure 2341190873Sjfv * 2342190873Sjfv * Clocks in/out one bit via I2C data/clock 2343190873Sjfv **/ 2344190873Sjfvstatic s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw) 2345190873Sjfv{ 2346280182Sjfv u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2347230775Sjfv s32 status = IXGBE_SUCCESS; 2348190873Sjfv u32 i = 0; 2349280182Sjfv u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2350190873Sjfv u32 timeout = 10; 2351190873Sjfv bool ack = 1; 2352190873Sjfv 2353190873Sjfv DEBUGFUNC("ixgbe_get_i2c_ack"); 2354190873Sjfv 2355280182Sjfv if (data_oe_bit) { 2356280182Sjfv i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2357280182Sjfv i2cctl |= data_oe_bit; 2358280182Sjfv IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2359280182Sjfv IXGBE_WRITE_FLUSH(hw); 2360280182Sjfv } 2361230775Sjfv ixgbe_raise_i2c_clk(hw, &i2cctl); 2362190873Sjfv 2363190873Sjfv /* Minimum high period of clock is 4us */ 2364190873Sjfv usec_delay(IXGBE_I2C_T_HIGH); 2365190873Sjfv 2366190873Sjfv /* Poll for ACK. Note that ACK in I2C spec is 2367190873Sjfv * transition from 1 to 0 */ 2368190873Sjfv for (i = 0; i < timeout; i++) { 2369280182Sjfv i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2370280182Sjfv ack = ixgbe_get_i2c_data(hw, &i2cctl); 2371190873Sjfv 2372190873Sjfv usec_delay(1); 2373280182Sjfv if (!ack) 2374190873Sjfv break; 2375190873Sjfv } 2376190873Sjfv 2377280182Sjfv if (ack) { 2378280182Sjfv DEBUGOUT("I2C ack was not received.\n"); 2379190873Sjfv status = IXGBE_ERR_I2C; 2380190873Sjfv } 2381190873Sjfv 2382190873Sjfv ixgbe_lower_i2c_clk(hw, &i2cctl); 2383190873Sjfv 2384190873Sjfv /* Minimum low period of clock is 4.7 us */ 2385190873Sjfv usec_delay(IXGBE_I2C_T_LOW); 2386190873Sjfv 2387190873Sjfv return status; 2388190873Sjfv} 2389190873Sjfv 2390190873Sjfv/** 2391190873Sjfv * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 2392190873Sjfv * @hw: pointer to hardware structure 2393190873Sjfv * @data: read data value 2394190873Sjfv * 2395190873Sjfv * Clocks in one bit via I2C data/clock 2396190873Sjfv **/ 2397190873Sjfvstatic s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data) 2398190873Sjfv{ 2399280182Sjfv u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2400280182Sjfv u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2401190873Sjfv 2402200239Sjfv DEBUGFUNC("ixgbe_clock_in_i2c_bit"); 2403200239Sjfv 2404280182Sjfv if (data_oe_bit) { 2405280182Sjfv i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2406280182Sjfv i2cctl |= data_oe_bit; 2407280182Sjfv IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2408280182Sjfv IXGBE_WRITE_FLUSH(hw); 2409280182Sjfv } 2410230775Sjfv ixgbe_raise_i2c_clk(hw, &i2cctl); 2411190873Sjfv 2412190873Sjfv /* Minimum high period of clock is 4us */ 2413190873Sjfv usec_delay(IXGBE_I2C_T_HIGH); 2414190873Sjfv 2415280182Sjfv i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2416280182Sjfv *data = ixgbe_get_i2c_data(hw, &i2cctl); 2417190873Sjfv 2418190873Sjfv ixgbe_lower_i2c_clk(hw, &i2cctl); 2419190873Sjfv 2420190873Sjfv /* Minimum low period of clock is 4.7 us */ 2421190873Sjfv usec_delay(IXGBE_I2C_T_LOW); 2422190873Sjfv 2423230775Sjfv return IXGBE_SUCCESS; 2424190873Sjfv} 2425190873Sjfv 2426190873Sjfv/** 2427190873Sjfv * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 2428190873Sjfv * @hw: pointer to hardware structure 2429190873Sjfv * @data: data value to write 2430190873Sjfv * 2431190873Sjfv * Clocks out one bit via I2C data/clock 2432190873Sjfv **/ 2433190873Sjfvstatic s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data) 2434190873Sjfv{ 2435190873Sjfv s32 status; 2436280182Sjfv u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2437190873Sjfv 2438200239Sjfv DEBUGFUNC("ixgbe_clock_out_i2c_bit"); 2439200239Sjfv 2440190873Sjfv status = ixgbe_set_i2c_data(hw, &i2cctl, data); 2441190873Sjfv if (status == IXGBE_SUCCESS) { 2442230775Sjfv ixgbe_raise_i2c_clk(hw, &i2cctl); 2443190873Sjfv 2444190873Sjfv /* Minimum high period of clock is 4us */ 2445190873Sjfv usec_delay(IXGBE_I2C_T_HIGH); 2446190873Sjfv 2447190873Sjfv ixgbe_lower_i2c_clk(hw, &i2cctl); 2448190873Sjfv 2449190873Sjfv /* Minimum low period of clock is 4.7 us. 2450190873Sjfv * This also takes care of the data hold time. 2451190873Sjfv */ 2452190873Sjfv usec_delay(IXGBE_I2C_T_LOW); 2453190873Sjfv } else { 2454190873Sjfv status = IXGBE_ERR_I2C; 2455251964Sjfv ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2456251964Sjfv "I2C data was not set to %X\n", data); 2457190873Sjfv } 2458190873Sjfv 2459190873Sjfv return status; 2460190873Sjfv} 2461280182Sjfv 2462190873Sjfv/** 2463190873Sjfv * ixgbe_raise_i2c_clk - Raises the I2C SCL clock 2464190873Sjfv * @hw: pointer to hardware structure 2465190873Sjfv * @i2cctl: Current value of I2CCTL register 2466190873Sjfv * 2467190873Sjfv * Raises the I2C clock line '0'->'1' 2468280182Sjfv * Negates the I2C clock output enable on X550 hardware. 2469190873Sjfv **/ 2470230775Sjfvstatic void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2471190873Sjfv{ 2472280182Sjfv u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2473238149Sjfv u32 i = 0; 2474238149Sjfv u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT; 2475238149Sjfv u32 i2cctl_r = 0; 2476238149Sjfv 2477200239Sjfv DEBUGFUNC("ixgbe_raise_i2c_clk"); 2478200239Sjfv 2479280182Sjfv if (clk_oe_bit) { 2480280182Sjfv *i2cctl |= clk_oe_bit; 2481280182Sjfv IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2482280182Sjfv } 2483280182Sjfv 2484238149Sjfv for (i = 0; i < timeout; i++) { 2485280182Sjfv *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw); 2486190873Sjfv 2487280182Sjfv IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2488238149Sjfv IXGBE_WRITE_FLUSH(hw); 2489238149Sjfv /* SCL rise time (1000ns) */ 2490238149Sjfv usec_delay(IXGBE_I2C_T_RISE); 2491190873Sjfv 2492280182Sjfv i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2493280182Sjfv if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw)) 2494238149Sjfv break; 2495238149Sjfv } 2496190873Sjfv} 2497190873Sjfv 2498190873Sjfv/** 2499190873Sjfv * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock 2500190873Sjfv * @hw: pointer to hardware structure 2501190873Sjfv * @i2cctl: Current value of I2CCTL register 2502190873Sjfv * 2503190873Sjfv * Lowers the I2C clock line '1'->'0' 2504280182Sjfv * Asserts the I2C clock output enable on X550 hardware. 2505190873Sjfv **/ 2506190873Sjfvstatic void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2507190873Sjfv{ 2508200239Sjfv DEBUGFUNC("ixgbe_lower_i2c_clk"); 2509200239Sjfv 2510280182Sjfv *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw)); 2511280182Sjfv *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2512190873Sjfv 2513280182Sjfv IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2514230775Sjfv IXGBE_WRITE_FLUSH(hw); 2515190873Sjfv 2516190873Sjfv /* SCL fall time (300ns) */ 2517190873Sjfv usec_delay(IXGBE_I2C_T_FALL); 2518190873Sjfv} 2519190873Sjfv 2520190873Sjfv/** 2521190873Sjfv * ixgbe_set_i2c_data - Sets the I2C data bit 2522190873Sjfv * @hw: pointer to hardware structure 2523190873Sjfv * @i2cctl: Current value of I2CCTL register 2524190873Sjfv * @data: I2C data value (0 or 1) to set 2525190873Sjfv * 2526190873Sjfv * Sets the I2C data bit 2527280182Sjfv * Asserts the I2C data output enable on X550 hardware. 2528190873Sjfv **/ 2529190873Sjfvstatic s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data) 2530190873Sjfv{ 2531280182Sjfv u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2532190873Sjfv s32 status = IXGBE_SUCCESS; 2533190873Sjfv 2534200239Sjfv DEBUGFUNC("ixgbe_set_i2c_data"); 2535200239Sjfv 2536190873Sjfv if (data) 2537280182Sjfv *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2538190873Sjfv else 2539280182Sjfv *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw)); 2540280182Sjfv *i2cctl &= ~data_oe_bit; 2541190873Sjfv 2542280182Sjfv IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2543230775Sjfv IXGBE_WRITE_FLUSH(hw); 2544190873Sjfv 2545190873Sjfv /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 2546190873Sjfv usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); 2547190873Sjfv 2548280182Sjfv if (!data) /* Can't verify data in this case */ 2549280182Sjfv return IXGBE_SUCCESS; 2550280182Sjfv if (data_oe_bit) { 2551280182Sjfv *i2cctl |= data_oe_bit; 2552280182Sjfv IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2553280182Sjfv IXGBE_WRITE_FLUSH(hw); 2554280182Sjfv } 2555280182Sjfv 2556190873Sjfv /* Verify data was set correctly */ 2557280182Sjfv *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2558280182Sjfv if (data != ixgbe_get_i2c_data(hw, i2cctl)) { 2559190873Sjfv status = IXGBE_ERR_I2C; 2560251964Sjfv ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2561251964Sjfv "Error - I2C data was not set to %X.\n", 2562251964Sjfv data); 2563190873Sjfv } 2564190873Sjfv 2565190873Sjfv return status; 2566190873Sjfv} 2567190873Sjfv 2568190873Sjfv/** 2569190873Sjfv * ixgbe_get_i2c_data - Reads the I2C SDA data bit 2570190873Sjfv * @hw: pointer to hardware structure 2571190873Sjfv * @i2cctl: Current value of I2CCTL register 2572190873Sjfv * 2573190873Sjfv * Returns the I2C data bit value 2574280182Sjfv * Negates the I2C data output enable on X550 hardware. 2575190873Sjfv **/ 2576280182Sjfvstatic bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl) 2577190873Sjfv{ 2578280182Sjfv u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2579190873Sjfv bool data; 2580190873Sjfv 2581200239Sjfv DEBUGFUNC("ixgbe_get_i2c_data"); 2582200239Sjfv 2583280182Sjfv if (data_oe_bit) { 2584280182Sjfv *i2cctl |= data_oe_bit; 2585280182Sjfv IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2586280182Sjfv IXGBE_WRITE_FLUSH(hw); 2587280182Sjfv usec_delay(IXGBE_I2C_T_FALL); 2588280182Sjfv } 2589280182Sjfv 2590280182Sjfv if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw)) 2591190873Sjfv data = 1; 2592190873Sjfv else 2593190873Sjfv data = 0; 2594190873Sjfv 2595190873Sjfv return data; 2596190873Sjfv} 2597190873Sjfv 2598190873Sjfv/** 2599190873Sjfv * ixgbe_i2c_bus_clear - Clears the I2C bus 2600190873Sjfv * @hw: pointer to hardware structure 2601190873Sjfv * 2602190873Sjfv * Clears the I2C bus by sending nine clock pulses. 2603190873Sjfv * Used when data line is stuck low. 2604190873Sjfv **/ 2605190873Sjfvvoid ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) 2606190873Sjfv{ 2607280182Sjfv u32 i2cctl; 2608190873Sjfv u32 i; 2609190873Sjfv 2610190873Sjfv DEBUGFUNC("ixgbe_i2c_bus_clear"); 2611190873Sjfv 2612190873Sjfv ixgbe_i2c_start(hw); 2613280182Sjfv i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2614190873Sjfv 2615190873Sjfv ixgbe_set_i2c_data(hw, &i2cctl, 1); 2616190873Sjfv 2617190873Sjfv for (i = 0; i < 9; i++) { 2618190873Sjfv ixgbe_raise_i2c_clk(hw, &i2cctl); 2619190873Sjfv 2620190873Sjfv /* Min high period of clock is 4us */ 2621190873Sjfv usec_delay(IXGBE_I2C_T_HIGH); 2622190873Sjfv 2623190873Sjfv ixgbe_lower_i2c_clk(hw, &i2cctl); 2624190873Sjfv 2625190873Sjfv /* Min low period of clock is 4.7us*/ 2626190873Sjfv usec_delay(IXGBE_I2C_T_LOW); 2627190873Sjfv } 2628190873Sjfv 2629190873Sjfv ixgbe_i2c_start(hw); 2630190873Sjfv 2631190873Sjfv /* Put the i2c bus back to default state */ 2632190873Sjfv ixgbe_i2c_stop(hw); 2633190873Sjfv} 2634205720Sjfv 2635205720Sjfv/** 2636238149Sjfv * ixgbe_tn_check_overtemp - Checks if an overtemp occurred. 2637205720Sjfv * @hw: pointer to hardware structure 2638205720Sjfv * 2639205720Sjfv * Checks if the LASI temp alarm status was triggered due to overtemp 2640205720Sjfv **/ 2641205720Sjfvs32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw) 2642205720Sjfv{ 2643205720Sjfv s32 status = IXGBE_SUCCESS; 2644205720Sjfv u16 phy_data = 0; 2645205720Sjfv 2646205720Sjfv DEBUGFUNC("ixgbe_tn_check_overtemp"); 2647205720Sjfv 2648205720Sjfv if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM) 2649205720Sjfv goto out; 2650205720Sjfv 2651205720Sjfv /* Check that the LASI temp alarm status was triggered */ 2652205720Sjfv hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG, 2653205720Sjfv IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data); 2654205720Sjfv 2655205720Sjfv if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM)) 2656205720Sjfv goto out; 2657205720Sjfv 2658205720Sjfv status = IXGBE_ERR_OVERTEMP; 2659251964Sjfv ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature"); 2660205720Sjfvout: 2661205720Sjfv return status; 2662205720Sjfv} 2663280182Sjfv 2664280182Sjfv/** 2665280182Sjfv * ixgbe_set_copper_phy_power - Control power for copper phy 2666280182Sjfv * @hw: pointer to hardware structure 2667280182Sjfv * @on: TRUE for on, FALSE for off 2668280182Sjfv */ 2669280182Sjfvs32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on) 2670280182Sjfv{ 2671280182Sjfv u32 status; 2672280182Sjfv u16 reg; 2673280182Sjfv 2674295093Ssmh if (!on && ixgbe_mng_present(hw)) 2675295093Ssmh return 0; 2676295093Ssmh 2677280182Sjfv status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2678280182Sjfv IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2679280182Sjfv ®); 2680280182Sjfv if (status) 2681280182Sjfv return status; 2682280182Sjfv 2683280182Sjfv if (on) { 2684280182Sjfv reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2685280182Sjfv } else { 2686280182Sjfv if (ixgbe_check_reset_blocked(hw)) 2687280182Sjfv return 0; 2688280182Sjfv reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2689280182Sjfv } 2690280182Sjfv 2691280182Sjfv status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2692280182Sjfv IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2693280182Sjfv reg); 2694280182Sjfv return status; 2695280182Sjfv} 2696