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32******************************************************************************/
33/*$FreeBSD: stable/11/sys/dev/ixgbe/ixgbe_api.h 320897 2017-07-11 21:25:07Z erj $*/
34
35#ifndef _IXGBE_API_H_
36#define _IXGBE_API_H_
37
38#include "ixgbe_type.h"
39
40void ixgbe_dcb_get_rtrup2tc(struct ixgbe_hw *hw, u8 *map);
41
42s32 ixgbe_init_shared_code(struct ixgbe_hw *hw);
43
44extern s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw);
45extern s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw);
46extern s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw);
47extern s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw);
48extern s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw);
49extern s32 ixgbe_init_ops_X550EM_x(struct ixgbe_hw *hw);
50extern s32 ixgbe_init_ops_X550EM_a(struct ixgbe_hw *hw);
51
52s32 ixgbe_set_mac_type(struct ixgbe_hw *hw);
53s32 ixgbe_init_hw(struct ixgbe_hw *hw);
54s32 ixgbe_reset_hw(struct ixgbe_hw *hw);
55s32 ixgbe_start_hw(struct ixgbe_hw *hw);
56void ixgbe_enable_relaxed_ordering(struct ixgbe_hw *hw);
57s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw);
58enum ixgbe_media_type ixgbe_get_media_type(struct ixgbe_hw *hw);
59s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr);
60s32 ixgbe_get_bus_info(struct ixgbe_hw *hw);
61u32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw);
62u32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw);
63s32 ixgbe_stop_adapter(struct ixgbe_hw *hw);
64s32 ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num);
65s32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size);
66
67s32 ixgbe_identify_phy(struct ixgbe_hw *hw);
68s32 ixgbe_reset_phy(struct ixgbe_hw *hw);
69s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
70		       u16 *phy_data);
71s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
72			u16 phy_data);
73
74s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw);
75s32 ixgbe_setup_internal_phy(struct ixgbe_hw *hw);
76s32 ixgbe_check_phy_link(struct ixgbe_hw *hw,
77			 ixgbe_link_speed *speed,
78			 bool *link_up);
79s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw,
80			       ixgbe_link_speed speed,
81			       bool autoneg_wait_to_complete);
82s32 ixgbe_set_phy_power(struct ixgbe_hw *, bool on);
83void ixgbe_disable_tx_laser(struct ixgbe_hw *hw);
84void ixgbe_enable_tx_laser(struct ixgbe_hw *hw);
85void ixgbe_flap_tx_laser(struct ixgbe_hw *hw);
86s32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed,
87		     bool autoneg_wait_to_complete);
88s32 ixgbe_setup_mac_link(struct ixgbe_hw *hw, ixgbe_link_speed speed,
89			 bool autoneg_wait_to_complete);
90s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
91		     bool *link_up, bool link_up_wait_to_complete);
92s32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
93				bool *autoneg);
94s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index);
95s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index);
96s32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index);
97s32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index);
98
99s32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw);
100s32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data);
101s32 ixgbe_write_eeprom_buffer(struct ixgbe_hw *hw, u16 offset,
102			      u16 words, u16 *data);
103s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data);
104s32 ixgbe_read_eeprom_buffer(struct ixgbe_hw *hw, u16 offset,
105			     u16 words, u16 *data);
106
107s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val);
108s32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw);
109
110s32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq);
111s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
112		  u32 enable_addr);
113s32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index);
114s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
115s32 ixgbe_set_vmdq_san_mac(struct ixgbe_hw *hw, u32 vmdq);
116s32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
117s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw);
118u32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw);
119s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list,
120			      u32 addr_count, ixgbe_mc_addr_itr func);
121s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list,
122			      u32 mc_addr_count, ixgbe_mc_addr_itr func,
123			      bool clear);
124void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr_list, u32 vmdq);
125s32 ixgbe_enable_mc(struct ixgbe_hw *hw);
126s32 ixgbe_disable_mc(struct ixgbe_hw *hw);
127s32 ixgbe_clear_vfta(struct ixgbe_hw *hw);
128s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan,
129		   u32 vind, bool vlan_on, bool vlvf_bypass);
130s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind,
131		   bool vlan_on, u32 *vfta_delta, u32 vfta,
132		   bool vlvf_bypass);
133s32 ixgbe_fc_enable(struct ixgbe_hw *hw);
134s32 ixgbe_setup_fc(struct ixgbe_hw *hw);
135s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build,
136			 u8 ver, u16 len, char *driver_ver);
137void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr);
138s32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw,
139				   u16 *firmware_version);
140s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val);
141s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val);
142s32 ixgbe_init_uta_tables(struct ixgbe_hw *hw);
143s32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data);
144u64 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw);
145s32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval);
146s32 ixgbe_disable_sec_rx_path(struct ixgbe_hw *hw);
147s32 ixgbe_enable_sec_rx_path(struct ixgbe_hw *hw);
148s32 ixgbe_mng_fw_enabled(struct ixgbe_hw *hw);
149s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
150s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl);
151s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl,
152					bool cloud_mode);
153void ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
154					   union ixgbe_atr_hash_dword input,
155					   union ixgbe_atr_hash_dword common,
156					   u8 queue);
157s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
158				    union ixgbe_atr_input *input_mask, bool cloud_mode);
159s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
160					  union ixgbe_atr_input *input,
161					  u16 soft_id, u8 queue, bool cloud_mode);
162s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
163					  union ixgbe_atr_input *input,
164					  u16 soft_id);
165s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
166					union ixgbe_atr_input *input,
167					union ixgbe_atr_input *mask,
168					u16 soft_id,
169					u8 queue,
170					bool cloud_mode);
171void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
172					  union ixgbe_atr_input *mask);
173u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
174				     union ixgbe_atr_hash_dword common);
175bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw);
176s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,
177			u8 *data);
178s32 ixgbe_read_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
179				 u8 dev_addr, u8 *data);
180s32 ixgbe_read_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val);
181s32 ixgbe_read_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val);
182s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,
183			 u8 data);
184void ixgbe_set_fdir_drop_queue_82599(struct ixgbe_hw *hw, u8 dropqueue);
185s32 ixgbe_write_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
186				  u8 dev_addr, u8 data);
187s32 ixgbe_write_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val);
188s32 ixgbe_write_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val);
189s32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 eeprom_data);
190s32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr);
191s32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr);
192s32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps);
193s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u32 mask);
194void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u32 mask);
195void ixgbe_init_swfw_semaphore(struct ixgbe_hw *hw);
196s32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix,
197			 u16 *wwpn_prefix);
198s32 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs);
199s32 ixgbe_bypass_rw(struct ixgbe_hw *hw, u32 cmd, u32 *status);
200s32 ixgbe_bypass_set(struct ixgbe_hw *hw, u32 cmd, u32 event, u32 action);
201s32 ixgbe_bypass_rd_eep(struct ixgbe_hw *hw, u32 addr, u8 *value);
202bool ixgbe_bypass_valid_rd(struct ixgbe_hw *hw, u32 in_reg, u32 out_reg);
203s32 ixgbe_dmac_config(struct ixgbe_hw *hw);
204s32 ixgbe_dmac_update_tcs(struct ixgbe_hw *hw);
205s32 ixgbe_dmac_config_tcs(struct ixgbe_hw *hw);
206s32 ixgbe_setup_eee(struct ixgbe_hw *hw, bool enable_eee);
207void ixgbe_set_source_address_pruning(struct ixgbe_hw *hw, bool enable,
208				      unsigned int vf);
209void ixgbe_set_ethertype_anti_spoofing(struct ixgbe_hw *hw, bool enable,
210				       int vf);
211s32 ixgbe_read_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr,
212			u32 device_type, u32 *phy_data);
213s32 ixgbe_write_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr,
214			u32 device_type, u32 phy_data);
215void ixgbe_disable_mdd(struct ixgbe_hw *hw);
216void ixgbe_enable_mdd(struct ixgbe_hw *hw);
217void ixgbe_mdd_event(struct ixgbe_hw *hw, u32 *vf_bitmap);
218void ixgbe_restore_mdd_vf(struct ixgbe_hw *hw, u32 vf);
219s32 ixgbe_enter_lplu(struct ixgbe_hw *hw);
220s32 ixgbe_handle_lasi(struct ixgbe_hw *hw);
221void ixgbe_set_rate_select_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed);
222void ixgbe_disable_rx(struct ixgbe_hw *hw);
223void ixgbe_enable_rx(struct ixgbe_hw *hw);
224s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
225			u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm);
226
227#endif /* _IXGBE_API_H_ */
228