1/******************************************************************************* 2 3 Copyright (c) 2001-2004, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32*******************************************************************************/ 33 34/*$FreeBSD$*/ 35 36/* ixgb_hw.c 37 * Shared functions for accessing and configuring the adapter 38 */ 39 40#include <dev/ixgb/ixgb_hw.h> 41#include <dev/ixgb/ixgb_ids.h> 42 43/* Local function prototypes */ 44 45static uint32_t ixgb_hash_mc_addr(struct ixgb_hw *hw, 46 uint8_t *mc_addr); 47 48static void ixgb_mta_set(struct ixgb_hw *hw, 49 uint32_t hash_value); 50 51static void ixgb_get_bus_info(struct ixgb_hw *hw); 52 53static boolean_t ixgb_link_reset(struct ixgb_hw *hw); 54 55static void ixgb_optics_reset(struct ixgb_hw *hw); 56 57static ixgb_phy_type ixgb_identify_phy(struct ixgb_hw *hw); 58 59uint32_t ixgb_mac_reset (struct ixgb_hw* hw); 60 61uint32_t ixgb_mac_reset (struct ixgb_hw* hw) 62{ 63 uint32_t ctrl_reg; 64 65 /* Setup up hardware to known state with RESET. 66 * SWDPIN settings as per Kemano EPS. 67 */ 68 ctrl_reg = IXGB_CTRL0_RST | 69 IXGB_CTRL0_SDP3_DIR | /* All pins are Output=1 */ 70 IXGB_CTRL0_SDP2_DIR | 71 IXGB_CTRL0_SDP1_DIR | 72 IXGB_CTRL0_SDP0_DIR | 73 IXGB_CTRL0_SDP3 | /* Initial value 1101 */ 74 IXGB_CTRL0_SDP2 | 75 IXGB_CTRL0_SDP0; 76 77#ifdef HP_ZX1 78 /* Workaround for 82597EX reset errata */ 79 IXGB_WRITE_REG_IO(hw, CTRL0, ctrl_reg); 80#else 81 IXGB_WRITE_REG(hw, CTRL0, ctrl_reg); 82#endif 83 84 /* Delay a few ms just to allow the reset to complete */ 85 msec_delay(IXGB_DELAY_AFTER_RESET); 86 ctrl_reg = IXGB_READ_REG(hw, CTRL0); 87#if DBG 88 /* Make sure the self-clearing global reset bit did self clear */ 89 ASSERT(!(ctrl_reg & IXGB_CTRL0_RST)); 90#endif 91 92 if (hw->phy_type == ixgb_phy_type_txn17401) { 93 /* Now reset the optics. This reset is required to ensure link with 94 * the Kemano 003 optical module (TXN17401), as per instructions from 95 * the board designer. 96 */ 97 ixgb_optics_reset(hw); 98 } 99 100 return ctrl_reg; 101} 102 103 104/****************************************************************************** 105 * Reset the transmit and receive units; mask and clear all interrupts. 106 * 107 * hw - Struct containing variables accessed by shared code 108 *****************************************************************************/ 109boolean_t 110ixgb_adapter_stop(struct ixgb_hw *hw) 111{ 112 uint32_t ctrl_reg; 113 uint32_t icr_reg; 114 115 DEBUGFUNC("ixgb_adapter_stop"); 116 117 /* If we are stopped or resetting exit gracefully and wait to be 118 * started again before accessing the hardware. 119 */ 120 if(hw->adapter_stopped) { 121 DEBUGOUT("Exiting because the adapter is already stopped!!!\n"); 122 return FALSE; 123 } 124 125 /* Set the Adapter Stopped flag so other driver functions stop 126 * touching the Hardware. 127 */ 128 hw->adapter_stopped = TRUE; 129 130 /* Clear interrupt mask to stop board from generating interrupts */ 131 DEBUGOUT("Masking off all interrupts\n"); 132 IXGB_WRITE_REG(hw, IMC, 0xFFFFFFFF); 133 134 /* Disable the Transmit and Receive units. Then delay to allow 135 * any pending transactions to complete before we hit the MAC with 136 * the global reset. 137 */ 138 IXGB_WRITE_REG(hw, RCTL, IXGB_READ_REG(hw, RCTL) & ~IXGB_RCTL_RXEN); 139 IXGB_WRITE_REG(hw, TCTL, IXGB_READ_REG(hw, TCTL) & ~IXGB_TCTL_TXEN); 140 msec_delay(IXGB_DELAY_BEFORE_RESET); 141 142 /* Issue a global reset to the MAC. This will reset the chip's 143 * transmit, receive, DMA, and link units. It will not effect 144 * the current PCI configuration. The global reset bit is self- 145 * clearing, and should clear within a microsecond. 146 */ 147 DEBUGOUT("Issuing a global reset to MAC\n"); 148 149 ctrl_reg = ixgb_mac_reset(hw); 150 151 /* Clear interrupt mask to stop board from generating interrupts */ 152 DEBUGOUT("Masking off all interrupts\n"); 153 IXGB_WRITE_REG(hw, IMC, 0xffffffff); 154 155 /* Clear any pending interrupt events. */ 156 icr_reg = IXGB_READ_REG(hw, ICR); 157 158 return (ctrl_reg & IXGB_CTRL0_RST); 159} 160 161 162/****************************************************************************** 163 * Identifies the vendor of the optics module on the adapter. The SR adapters 164 * support two different types of XPAK optics, so it is necessary to determine 165 * which optics are present before applying any optics-specific workarounds. 166 * 167 * hw - Struct containing variables accessed by shared code. 168 * 169 * Returns: the vendor of the XPAK optics module. 170 *****************************************************************************/ 171static ixgb_xpak_vendor 172ixgb_identify_xpak_vendor(struct ixgb_hw *hw) 173{ 174 uint32_t i; 175 uint16_t vendor_name[5]; 176 ixgb_xpak_vendor xpak_vendor; 177 178 DEBUGFUNC("ixgb_identify_xpak_vendor"); 179 180 /* Read the first few bytes of the vendor string from the XPAK NVR 181 * registers. These are standard XENPAK/XPAK registers, so all XPAK 182 * devices should implement them. */ 183 for (i = 0; i < 5; i++) { 184 vendor_name[i] = ixgb_read_phy_reg( hw, 185 MDIO_PMA_PMD_XPAK_VENDOR_NAME + i, 186 IXGB_PHY_ADDRESS, 187 MDIO_PMA_PMD_DID ); 188 } 189 190 /* Determine the actual vendor */ 191 if (vendor_name[0] == 'I' && 192 vendor_name[1] == 'N' && 193 vendor_name[2] == 'T' && 194 vendor_name[3] == 'E' && 195 vendor_name[4] == 'L') { 196 xpak_vendor = ixgb_xpak_vendor_intel; 197 } 198 else { 199 xpak_vendor = ixgb_xpak_vendor_infineon; 200 } 201 202 return (xpak_vendor); 203} 204 205 206/****************************************************************************** 207 * Determine the physical layer module on the adapter. 208 * 209 * hw - Struct containing variables accessed by shared code. The device_id 210 * field must be (correctly) populated before calling this routine. 211 * 212 * Returns: the phy type of the adapter. 213 *****************************************************************************/ 214static ixgb_phy_type 215ixgb_identify_phy(struct ixgb_hw *hw) 216{ 217 ixgb_phy_type phy_type; 218 ixgb_xpak_vendor xpak_vendor; 219 220 DEBUGFUNC("ixgb_identify_phy"); 221 222 /* Infer the transceiver/phy type from the device id */ 223 switch (hw->device_id) { 224 case IXGB_DEVICE_ID_82597EX: 225 DEBUGOUT("Identified TXN17401 optics\n"); 226 phy_type = ixgb_phy_type_txn17401; 227 break; 228 229 case IXGB_DEVICE_ID_82597EX_SR: 230 /* The SR adapters carry two different types of XPAK optics 231 * modules; read the vendor identifier to determine the exact 232 * type of optics. */ 233 xpak_vendor = ixgb_identify_xpak_vendor(hw); 234 if (xpak_vendor == ixgb_xpak_vendor_intel) { 235 DEBUGOUT("Identified TXN17201 optics\n"); 236 phy_type = ixgb_phy_type_txn17201; 237 } 238 else { 239 DEBUGOUT("Identified G6005 optics\n"); 240 phy_type = ixgb_phy_type_g6005; 241 } 242 break; 243 244 245 default: 246 DEBUGOUT("Unknown physical layer module\n"); 247 phy_type = ixgb_phy_type_unknown; 248 break; 249 } 250 251 return (phy_type); 252} 253 254/****************************************************************************** 255 * Performs basic configuration of the adapter. 256 * 257 * hw - Struct containing variables accessed by shared code 258 * 259 * Resets the controller. 260 * Reads and validates the EEPROM. 261 * Initializes the receive address registers. 262 * Initializes the multicast table. 263 * Clears all on-chip counters. 264 * Calls routine to setup flow control settings. 265 * Leaves the transmit and receive units disabled and uninitialized. 266 * 267 * Returns: 268 * TRUE if successful, 269 * FALSE if unrecoverable problems were encountered. 270 *****************************************************************************/ 271boolean_t 272ixgb_init_hw(struct ixgb_hw *hw) 273{ 274 uint32_t i; 275 uint32_t ctrl_reg; 276 boolean_t status; 277 278 DEBUGFUNC("ixgb_init_hw"); 279 280 /* Issue a global reset to the MAC. This will reset the chip's 281 * transmit, receive, DMA, and link units. It will not effect 282 * the current PCI configuration. The global reset bit is self- 283 * clearing, and should clear within a microsecond. 284 */ 285 DEBUGOUT("Issuing a global reset to MAC\n"); 286 287 ctrl_reg = ixgb_mac_reset(hw); 288 289 DEBUGOUT("Issuing an EE reset to MAC\n"); 290#ifdef HP_ZX1 291 /* Workaround for 82597EX reset errata */ 292 IXGB_WRITE_REG_IO(hw, CTRL1, IXGB_CTRL1_EE_RST); 293#else 294 IXGB_WRITE_REG(hw, CTRL1, IXGB_CTRL1_EE_RST); 295#endif 296 297 /* Delay a few ms just to allow the reset to complete */ 298 msec_delay(IXGB_DELAY_AFTER_EE_RESET); 299 300 if (ixgb_get_eeprom_data(hw) == FALSE) { 301 return(FALSE); 302 } 303 304 /* Use the device id to determine the type of phy/transceiver. */ 305 hw->device_id = ixgb_get_ee_device_id(hw); 306 hw->phy_type = ixgb_identify_phy(hw); 307 308 /* Setup the receive addresses. 309 * Receive Address Registers (RARs 0 - 15). 310 */ 311 ixgb_init_rx_addrs(hw); 312 313 /* 314 * Check that a valid MAC address has been set. 315 * If it is not valid, we fail hardware init. 316 */ 317 if (!mac_addr_valid(hw->curr_mac_addr)) { 318 DEBUGOUT("MAC address invalid after ixgb_init_rx_addrs\n"); 319 return(FALSE); 320 } 321 322 /* tell the routines in this file they can access hardware again */ 323 hw->adapter_stopped = FALSE; 324 325 /* Fill in the bus_info structure */ 326 ixgb_get_bus_info(hw); 327 328 /* Zero out the Multicast HASH table */ 329 DEBUGOUT("Zeroing the MTA\n"); 330 for(i = 0; i < IXGB_MC_TBL_SIZE; i++) 331 IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0); 332 333 /* Zero out the VLAN Filter Table Array */ 334 ixgb_clear_vfta(hw); 335 336 /* Zero all of the hardware counters */ 337 ixgb_clear_hw_cntrs(hw); 338 339 /* Call a subroutine to setup flow control. */ 340 status = ixgb_setup_fc(hw); 341 342 /* 82597EX errata: Call check-for-link in case lane deskew is locked */ 343 ixgb_check_for_link(hw); 344 345 return (status); 346} 347 348/****************************************************************************** 349 * Initializes receive address filters. 350 * 351 * hw - Struct containing variables accessed by shared code 352 * 353 * Places the MAC address in receive address register 0 and clears the rest 354 * of the receive addresss registers. Clears the multicast table. Assumes 355 * the receiver is in reset when the routine is called. 356 *****************************************************************************/ 357void 358ixgb_init_rx_addrs(struct ixgb_hw *hw) 359{ 360 uint32_t i; 361 362 DEBUGFUNC("ixgb_init_rx_addrs"); 363 364 /* 365 * If the current mac address is valid, assume it is a software override 366 * to the permanent address. 367 * Otherwise, use the permanent address from the eeprom. 368 */ 369 if (!mac_addr_valid(hw->curr_mac_addr)) { 370 371 /* Get the MAC address from the eeprom for later reference */ 372 ixgb_get_ee_mac_addr(hw, hw->curr_mac_addr); 373 374 DEBUGOUT3(" Keeping Permanent MAC Addr =%.2X %.2X %.2X ", 375 hw->curr_mac_addr[0], 376 hw->curr_mac_addr[1], 377 hw->curr_mac_addr[2]); 378 DEBUGOUT3("%.2X %.2X %.2X\n", 379 hw->curr_mac_addr[3], 380 hw->curr_mac_addr[4], 381 hw->curr_mac_addr[5]); 382 } else { 383 384 /* Setup the receive address. */ 385 DEBUGOUT("Overriding MAC Address in RAR[0]\n"); 386 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ", 387 hw->curr_mac_addr[0], 388 hw->curr_mac_addr[1], 389 hw->curr_mac_addr[2]); 390 DEBUGOUT3("%.2X %.2X %.2X\n", 391 hw->curr_mac_addr[3], 392 hw->curr_mac_addr[4], 393 hw->curr_mac_addr[5]); 394 395 396 ixgb_rar_set(hw, hw->curr_mac_addr, 0); 397 } 398 399 /* Zero out the other 15 receive addresses. */ 400 DEBUGOUT("Clearing RAR[1-15]\n"); 401 for(i = 1; i < IXGB_RAR_ENTRIES; i++) { 402 IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 403 IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 404 } 405 406 return; 407} 408 409/****************************************************************************** 410 * Updates the MAC's list of multicast addresses. 411 * 412 * hw - Struct containing variables accessed by shared code 413 * mc_addr_list - the list of new multicast addresses 414 * mc_addr_count - number of addresses 415 * pad - number of bytes between addresses in the list 416 * 417 * The given list replaces any existing list. Clears the last 15 receive 418 * address registers and the multicast table. Uses receive address registers 419 * for the first 15 multicast addresses, and hashes the rest into the 420 * multicast table. 421 *****************************************************************************/ 422void 423ixgb_mc_addr_list_update(struct ixgb_hw *hw, 424 uint8_t *mc_addr_list, 425 uint32_t mc_addr_count, 426 uint32_t pad) 427{ 428 uint32_t hash_value; 429 uint32_t i; 430 uint32_t rar_used_count = 1; /* RAR[0] is used for our MAC address */ 431 432 DEBUGFUNC("ixgb_mc_addr_list_update"); 433 434 /* Set the new number of MC addresses that we are being requested to use. */ 435 hw->num_mc_addrs = mc_addr_count; 436 437 /* Clear RAR[1-15] */ 438 DEBUGOUT(" Clearing RAR[1-15]\n"); 439 for(i = rar_used_count; i < IXGB_RAR_ENTRIES; i++) { 440 IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 441 IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 442 } 443 444 /* Clear the MTA */ 445 DEBUGOUT(" Clearing MTA\n"); 446 for(i = 0; i < IXGB_MC_TBL_SIZE; i++) { 447 IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0); 448 } 449 450 /* Add the new addresses */ 451 for(i = 0; i < mc_addr_count; i++) { 452 DEBUGOUT(" Adding the multicast addresses:\n"); 453 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i, 454 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad)], 455 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + 1], 456 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + 2], 457 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + 3], 458 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + 4], 459 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + 5]); 460 461 /* Place this multicast address in the RAR if there is room, * 462 * else put it in the MTA 463 */ 464 if(rar_used_count < IXGB_RAR_ENTRIES) { 465 ixgb_rar_set(hw, 466 mc_addr_list + (i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad)), 467 rar_used_count); 468 DEBUGOUT1("Added a multicast address to RAR[%d]\n", i); 469 rar_used_count++; 470 } else { 471 hash_value = ixgb_hash_mc_addr(hw, 472 mc_addr_list + 473 (i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad))); 474 475 DEBUGOUT1(" Hash value = 0x%03X\n", hash_value); 476 477 ixgb_mta_set(hw, hash_value); 478 } 479 } 480 481 DEBUGOUT("MC Update Complete\n"); 482 return; 483} 484 485/****************************************************************************** 486 * Hashes an address to determine its location in the multicast table 487 * 488 * hw - Struct containing variables accessed by shared code 489 * mc_addr - the multicast address to hash 490 * 491 * Returns: 492 * The hash value 493 *****************************************************************************/ 494static uint32_t 495ixgb_hash_mc_addr(struct ixgb_hw *hw, 496 uint8_t *mc_addr) 497{ 498 uint32_t hash_value = 0; 499 500 DEBUGFUNC("ixgb_hash_mc_addr"); 501 502 /* The portion of the address that is used for the hash table is 503 * determined by the mc_filter_type setting. 504 */ 505 switch (hw->mc_filter_type) { 506 /* [0] [1] [2] [3] [4] [5] 507 * 01 AA 00 12 34 56 508 * LSB MSB - According to H/W docs */ 509 case 0: 510 /* [47:36] i.e. 0x563 for above example address */ 511 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4)); 512 break; 513 case 1: /* [46:35] i.e. 0xAC6 for above example address */ 514 hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5)); 515 break; 516 case 2: /* [45:34] i.e. 0x5D8 for above example address */ 517 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6)); 518 break; 519 case 3: /* [43:32] i.e. 0x634 for above example address */ 520 hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8)); 521 break; 522 default: 523 /* Invalid mc_filter_type, what should we do? */ 524 DEBUGOUT("MC filter type param set incorrectly\n"); 525 ASSERT(0); 526 break; 527 } 528 529 hash_value &= 0xFFF; 530 return (hash_value); 531} 532 533/****************************************************************************** 534 * Sets the bit in the multicast table corresponding to the hash value. 535 * 536 * hw - Struct containing variables accessed by shared code 537 * hash_value - Multicast address hash value 538 *****************************************************************************/ 539static void 540ixgb_mta_set(struct ixgb_hw *hw, 541 uint32_t hash_value) 542{ 543 uint32_t hash_bit, hash_reg; 544 uint32_t mta_reg; 545 546 /* The MTA is a register array of 128 32-bit registers. 547 * It is treated like an array of 4096 bits. We want to set 548 * bit BitArray[hash_value]. So we figure out what register 549 * the bit is in, read it, OR in the new bit, then write 550 * back the new value. The register is determined by the 551 * upper 7 bits of the hash value and the bit within that 552 * register are determined by the lower 5 bits of the value. 553 */ 554 hash_reg = (hash_value >> 5) & 0x7F; 555 hash_bit = hash_value & 0x1F; 556 557 mta_reg = IXGB_READ_REG_ARRAY(hw, MTA, hash_reg); 558 559 mta_reg |= (1 << hash_bit); 560 561 IXGB_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta_reg); 562 563 return; 564} 565 566/****************************************************************************** 567 * Puts an ethernet address into a receive address register. 568 * 569 * hw - Struct containing variables accessed by shared code 570 * addr - Address to put into receive address register 571 * index - Receive address register to write 572 *****************************************************************************/ 573void 574ixgb_rar_set(struct ixgb_hw *hw, 575 uint8_t *addr, 576 uint32_t index) 577{ 578 uint32_t rar_low, rar_high; 579 580 DEBUGFUNC("ixgb_rar_set"); 581 582 /* HW expects these in little endian so we reverse the byte order 583 * from network order (big endian) to little endian 584 */ 585 rar_low = ((uint32_t) addr[0] | 586 ((uint32_t) addr[1] << 8) | 587 ((uint32_t) addr[2] << 16) | 588 ((uint32_t) addr[3] << 24)); 589 590 rar_high = ((uint32_t) addr[4] | 591 ((uint32_t) addr[5] << 8) | 592 IXGB_RAH_AV); 593 594 IXGB_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); 595 IXGB_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); 596 return; 597} 598 599/****************************************************************************** 600 * Writes a value to the specified offset in the VLAN filter table. 601 * 602 * hw - Struct containing variables accessed by shared code 603 * offset - Offset in VLAN filer table to write 604 * value - Value to write into VLAN filter table 605 *****************************************************************************/ 606void 607ixgb_write_vfta(struct ixgb_hw *hw, 608 uint32_t offset, 609 uint32_t value) 610{ 611 IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, value); 612 return; 613} 614 615/****************************************************************************** 616 * Clears the VLAN filer table 617 * 618 * hw - Struct containing variables accessed by shared code 619 *****************************************************************************/ 620void 621ixgb_clear_vfta(struct ixgb_hw *hw) 622{ 623 uint32_t offset; 624 625 for(offset = 0; offset < IXGB_VLAN_FILTER_TBL_SIZE; offset++) 626 IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, 0); 627 return; 628} 629 630/****************************************************************************** 631 * Configures the flow control settings based on SW configuration. 632 * 633 * hw - Struct containing variables accessed by shared code 634 *****************************************************************************/ 635 636boolean_t 637ixgb_setup_fc(struct ixgb_hw *hw) 638{ 639 uint32_t ctrl_reg; 640 uint32_t pap_reg = 0; /* by default, assume no pause time */ 641 boolean_t status = TRUE; 642 643 DEBUGFUNC("ixgb_setup_fc"); 644 645 /* Get the current control reg 0 settings */ 646 ctrl_reg = IXGB_READ_REG(hw, CTRL0); 647 648 /* Clear the Receive Pause Enable and Transmit Pause Enable bits */ 649 ctrl_reg &= ~(IXGB_CTRL0_RPE | IXGB_CTRL0_TPE); 650 651 /* The possible values of the "flow_control" parameter are: 652 * 0: Flow control is completely disabled 653 * 1: Rx flow control is enabled (we can receive pause frames 654 * but not send pause frames). 655 * 2: Tx flow control is enabled (we can send pause frames 656 * but we do not support receiving pause frames). 657 * 3: Both Rx and TX flow control (symmetric) are enabled. 658 * other: Invalid. 659 */ 660 switch (hw->fc.type) { 661 case ixgb_fc_none: /* 0 */ 662 /* Set CMDC bit to disable Rx Flow control*/ 663 ctrl_reg |= (IXGB_CTRL0_CMDC); 664 break; 665 case ixgb_fc_rx_pause: /* 1 */ 666 /* RX Flow control is enabled, and TX Flow control is 667 * disabled. 668 */ 669 ctrl_reg |= (IXGB_CTRL0_RPE); 670 break; 671 case ixgb_fc_tx_pause: /* 2 */ 672 /* TX Flow control is enabled, and RX Flow control is 673 * disabled, by a software over-ride. 674 */ 675 ctrl_reg |= (IXGB_CTRL0_TPE); 676 pap_reg = hw->fc.pause_time; 677 break; 678 case ixgb_fc_full: /* 3 */ 679 /* Flow control (both RX and TX) is enabled by a software 680 * over-ride. 681 */ 682 ctrl_reg |= (IXGB_CTRL0_RPE | IXGB_CTRL0_TPE); 683 pap_reg = hw->fc.pause_time; 684 break; 685 default: 686 /* We should never get here. The value should be 0-3. */ 687 DEBUGOUT("Flow control param set incorrectly\n"); 688 ASSERT(0); 689 break; 690 } 691 692 /* Write the new settings */ 693 IXGB_WRITE_REG(hw, CTRL0, ctrl_reg); 694 695 if (pap_reg != 0) { 696 IXGB_WRITE_REG(hw, PAP, pap_reg); 697 } 698 699 /* Set the flow control receive threshold registers. Normally, 700 * these registers will be set to a default threshold that may be 701 * adjusted later by the driver's runtime code. However, if the 702 * ability to transmit pause frames in not enabled, then these 703 * registers will be set to 0. 704 */ 705 if(!(hw->fc.type & ixgb_fc_tx_pause)) { 706 IXGB_WRITE_REG(hw, FCRTL, 0); 707 IXGB_WRITE_REG(hw, FCRTH, 0); 708 } else { 709 /* We need to set up the Receive Threshold high and low water 710 * marks as well as (optionally) enabling the transmission of XON frames. 711 */ 712 if(hw->fc.send_xon) { 713 IXGB_WRITE_REG(hw, FCRTL, 714 (hw->fc.low_water | IXGB_FCRTL_XONE)); 715 } else { 716 IXGB_WRITE_REG(hw, FCRTL, hw->fc.low_water); 717 } 718 IXGB_WRITE_REG(hw, FCRTH, hw->fc.high_water); 719 } 720 return (status); 721} 722 723/****************************************************************************** 724 * Reads a word from a device over the Management Data Interface (MDI) bus. 725 * This interface is used to manage Physical layer devices. 726 * 727 * hw - Struct containing variables accessed by hw code 728 * reg_address - Offset of device register being read. 729 * phy_address - Address of device on MDI. 730 * 731 * Returns: Data word (16 bits) from MDI device. 732 * 733 * The 82597EX has support for several MDI access methods. This routine 734 * uses the new protocol MDI Single Command and Address Operation. 735 * This requires that first an address cycle command is sent, followed by a 736 * read command. 737 *****************************************************************************/ 738uint16_t 739ixgb_read_phy_reg(struct ixgb_hw *hw, 740 uint32_t reg_address, 741 uint32_t phy_address, 742 uint32_t device_type) 743{ 744 uint32_t i; 745 uint32_t data; 746 uint32_t command = 0; 747 748 ASSERT(reg_address <= IXGB_MAX_PHY_REG_ADDRESS); 749 ASSERT(phy_address <= IXGB_MAX_PHY_ADDRESS); 750 ASSERT(device_type <= IXGB_MAX_PHY_DEV_TYPE); 751 752 /* Setup and write the address cycle command */ 753 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) | 754 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) | 755 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) | 756 (IXGB_MSCA_ADDR_CYCLE | IXGB_MSCA_MDI_COMMAND)); 757 758 IXGB_WRITE_REG(hw, MSCA, command); 759 760 /************************************************************** 761 ** Check every 10 usec to see if the address cycle completed 762 ** The COMMAND bit will clear when the operation is complete. 763 ** This may take as long as 64 usecs (we'll wait 100 usecs max) 764 ** from the CPU Write to the Ready bit assertion. 765 **************************************************************/ 766 767 for (i = 0; i < 10; i++) 768 { 769 usec_delay(10); 770 771 command = IXGB_READ_REG(hw, MSCA); 772 773 if ((command & IXGB_MSCA_MDI_COMMAND) == 0) 774 break; 775 } 776 777 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0); 778 779 /* Address cycle complete, setup and write the read command */ 780 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) | 781 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) | 782 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) | 783 (IXGB_MSCA_READ | IXGB_MSCA_MDI_COMMAND)); 784 785 IXGB_WRITE_REG(hw, MSCA, command); 786 787 /************************************************************** 788 ** Check every 10 usec to see if the read command completed 789 ** The COMMAND bit will clear when the operation is complete. 790 ** The read may take as long as 64 usecs (we'll wait 100 usecs max) 791 ** from the CPU Write to the Ready bit assertion. 792 **************************************************************/ 793 794 for (i = 0; i < 10; i++) 795 { 796 usec_delay(10); 797 798 command = IXGB_READ_REG(hw, MSCA); 799 800 if ((command & IXGB_MSCA_MDI_COMMAND) == 0) 801 break; 802 } 803 804 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0); 805 806 /* Operation is complete, get the data from the MDIO Read/Write Data 807 * register and return. 808 */ 809 data = IXGB_READ_REG(hw, MSRWD); 810 data >>= IXGB_MSRWD_READ_DATA_SHIFT; 811 return((uint16_t) data); 812} 813 814/****************************************************************************** 815 * Writes a word to a device over the Management Data Interface (MDI) bus. 816 * This interface is used to manage Physical layer devices. 817 * 818 * hw - Struct containing variables accessed by hw code 819 * reg_address - Offset of device register being read. 820 * phy_address - Address of device on MDI. 821 * device_type - Also known as the Device ID or DID. 822 * data - 16-bit value to be written 823 * 824 * Returns: void. 825 * 826 * The 82597EX has support for several MDI access methods. This routine 827 * uses the new protocol MDI Single Command and Address Operation. 828 * This requires that first an address cycle command is sent, followed by a 829 * write command. 830 *****************************************************************************/ 831void 832ixgb_write_phy_reg(struct ixgb_hw *hw, 833 uint32_t reg_address, 834 uint32_t phy_address, 835 uint32_t device_type, 836 uint16_t data) 837{ 838 uint32_t i; 839 uint32_t command = 0; 840 841 ASSERT(reg_address <= IXGB_MAX_PHY_REG_ADDRESS); 842 ASSERT(phy_address <= IXGB_MAX_PHY_ADDRESS); 843 ASSERT(device_type <= IXGB_MAX_PHY_DEV_TYPE); 844 845 /* Put the data in the MDIO Read/Write Data register */ 846 IXGB_WRITE_REG(hw, MSRWD, (uint32_t)data); 847 848 /* Setup and write the address cycle command */ 849 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) | 850 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) | 851 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) | 852 (IXGB_MSCA_ADDR_CYCLE | IXGB_MSCA_MDI_COMMAND)); 853 854 IXGB_WRITE_REG(hw, MSCA, command); 855 856 /************************************************************** 857 ** Check every 10 usec to see if the address cycle completed 858 ** The COMMAND bit will clear when the operation is complete. 859 ** This may take as long as 64 usecs (we'll wait 100 usecs max) 860 ** from the CPU Write to the Ready bit assertion. 861 **************************************************************/ 862 863 for (i = 0; i < 10; i++) 864 { 865 usec_delay(10); 866 867 command = IXGB_READ_REG(hw, MSCA); 868 869 if ((command & IXGB_MSCA_MDI_COMMAND) == 0) 870 break; 871 } 872 873 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0); 874 875 /* Address cycle complete, setup and write the write command */ 876 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) | 877 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) | 878 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) | 879 (IXGB_MSCA_WRITE | IXGB_MSCA_MDI_COMMAND)); 880 881 IXGB_WRITE_REG(hw, MSCA, command); 882 883 /************************************************************** 884 ** Check every 10 usec to see if the read command completed 885 ** The COMMAND bit will clear when the operation is complete. 886 ** The write may take as long as 64 usecs (we'll wait 100 usecs max) 887 ** from the CPU Write to the Ready bit assertion. 888 **************************************************************/ 889 890 for (i = 0; i < 10; i++) 891 { 892 usec_delay(10); 893 894 command = IXGB_READ_REG(hw, MSCA); 895 896 if ((command & IXGB_MSCA_MDI_COMMAND) == 0) 897 break; 898 } 899 900 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0); 901 902 /* Operation is complete, return. */ 903} 904 905 906/****************************************************************************** 907 * Checks to see if the link status of the hardware has changed. 908 * 909 * hw - Struct containing variables accessed by hw code 910 * 911 * Called by any function that needs to check the link status of the adapter. 912 *****************************************************************************/ 913void 914ixgb_check_for_link(struct ixgb_hw *hw) 915{ 916 uint32_t status_reg; 917 uint32_t xpcss_reg; 918 919 DEBUGFUNC("ixgb_check_for_link"); 920 921 xpcss_reg = IXGB_READ_REG(hw, XPCSS); 922 status_reg = IXGB_READ_REG(hw, STATUS); 923 924 if ((xpcss_reg & IXGB_XPCSS_ALIGN_STATUS) && 925 (status_reg & IXGB_STATUS_LU)) { 926 hw->link_up = TRUE; 927 } else if (!(xpcss_reg & IXGB_XPCSS_ALIGN_STATUS) && 928 (status_reg & IXGB_STATUS_LU)) { 929 DEBUGOUT("XPCSS Not Aligned while Status:LU is set.\n"); 930 hw->link_up = ixgb_link_reset(hw); 931 } else { 932 /* 933 * 82597EX errata. Since the lane deskew problem may prevent 934 * link, reset the link before reporting link down. 935 */ 936 hw->link_up = ixgb_link_reset(hw); 937 } 938 /* Anything else for 10 Gig?? */ 939} 940 941/****************************************************************************** 942 * Check for a bad link condition that may have occurred. 943 * The indication is that the RFC / LFC registers may be incrementing 944 * continually. A full adapter reset is required to recover. 945 * 946 * hw - Struct containing variables accessed by hw code 947 * 948 * Called by any function that needs to check the link status of the adapter. 949 *****************************************************************************/ 950boolean_t ixgb_check_for_bad_link(struct ixgb_hw *hw) 951{ 952 uint32_t newLFC, newRFC; 953 boolean_t bad_link_returncode = FALSE; 954 955 if (hw->phy_type == ixgb_phy_type_txn17401) { 956 newLFC = IXGB_READ_REG(hw, LFC); 957 newRFC = IXGB_READ_REG(hw, RFC); 958 if ((hw->lastLFC + 250 < newLFC) || (hw->lastRFC + 250 < newRFC)) { 959 DEBUGOUT("BAD LINK! too many LFC/RFC since last check\n"); 960 bad_link_returncode = TRUE; 961 } 962 hw->lastLFC = newLFC; 963 hw->lastRFC = newRFC; 964 } 965 966 return bad_link_returncode; 967} 968 969 970/****************************************************************************** 971 * Clears all hardware statistics counters. 972 * 973 * hw - Struct containing variables accessed by shared code 974 *****************************************************************************/ 975void 976ixgb_clear_hw_cntrs(struct ixgb_hw *hw) 977{ 978 volatile uint32_t temp_reg; 979 980 DEBUGFUNC("ixgb_clear_hw_cntrs"); 981 982 /* if we are stopped or resetting exit gracefully */ 983 if(hw->adapter_stopped) { 984 DEBUGOUT("Exiting because the adapter is stopped!!!\n"); 985 return; 986 } 987 988 temp_reg = IXGB_READ_REG(hw, TPRL); 989 temp_reg = IXGB_READ_REG(hw, TPRH); 990 temp_reg = IXGB_READ_REG(hw, GPRCL); 991 temp_reg = IXGB_READ_REG(hw, GPRCH); 992 temp_reg = IXGB_READ_REG(hw, BPRCL); 993 temp_reg = IXGB_READ_REG(hw, BPRCH); 994 temp_reg = IXGB_READ_REG(hw, MPRCL); 995 temp_reg = IXGB_READ_REG(hw, MPRCH); 996 temp_reg = IXGB_READ_REG(hw, UPRCL); 997 temp_reg = IXGB_READ_REG(hw, UPRCH); 998 temp_reg = IXGB_READ_REG(hw, VPRCL); 999 temp_reg = IXGB_READ_REG(hw, VPRCH); 1000 temp_reg = IXGB_READ_REG(hw, JPRCL); 1001 temp_reg = IXGB_READ_REG(hw, JPRCH); 1002 temp_reg = IXGB_READ_REG(hw, GORCL); 1003 temp_reg = IXGB_READ_REG(hw, GORCH); 1004 temp_reg = IXGB_READ_REG(hw, TORL); 1005 temp_reg = IXGB_READ_REG(hw, TORH); 1006 temp_reg = IXGB_READ_REG(hw, RNBC); 1007 temp_reg = IXGB_READ_REG(hw, RUC); 1008 temp_reg = IXGB_READ_REG(hw, ROC); 1009 temp_reg = IXGB_READ_REG(hw, RLEC); 1010 temp_reg = IXGB_READ_REG(hw, CRCERRS); 1011 temp_reg = IXGB_READ_REG(hw, ICBC); 1012 temp_reg = IXGB_READ_REG(hw, ECBC); 1013 temp_reg = IXGB_READ_REG(hw, MPC); 1014 temp_reg = IXGB_READ_REG(hw, TPTL); 1015 temp_reg = IXGB_READ_REG(hw, TPTH); 1016 temp_reg = IXGB_READ_REG(hw, GPTCL); 1017 temp_reg = IXGB_READ_REG(hw, GPTCH); 1018 temp_reg = IXGB_READ_REG(hw, BPTCL); 1019 temp_reg = IXGB_READ_REG(hw, BPTCH); 1020 temp_reg = IXGB_READ_REG(hw, MPTCL); 1021 temp_reg = IXGB_READ_REG(hw, MPTCH); 1022 temp_reg = IXGB_READ_REG(hw, UPTCL); 1023 temp_reg = IXGB_READ_REG(hw, UPTCH); 1024 temp_reg = IXGB_READ_REG(hw, VPTCL); 1025 temp_reg = IXGB_READ_REG(hw, VPTCH); 1026 temp_reg = IXGB_READ_REG(hw, JPTCL); 1027 temp_reg = IXGB_READ_REG(hw, JPTCH); 1028 temp_reg = IXGB_READ_REG(hw, GOTCL); 1029 temp_reg = IXGB_READ_REG(hw, GOTCH); 1030 temp_reg = IXGB_READ_REG(hw, TOTL); 1031 temp_reg = IXGB_READ_REG(hw, TOTH); 1032 temp_reg = IXGB_READ_REG(hw, DC); 1033 temp_reg = IXGB_READ_REG(hw, PLT64C); 1034 temp_reg = IXGB_READ_REG(hw, TSCTC); 1035 temp_reg = IXGB_READ_REG(hw, TSCTFC); 1036 temp_reg = IXGB_READ_REG(hw, IBIC); 1037 temp_reg = IXGB_READ_REG(hw, RFC); 1038 temp_reg = IXGB_READ_REG(hw, LFC); 1039 temp_reg = IXGB_READ_REG(hw, PFRC); 1040 temp_reg = IXGB_READ_REG(hw, PFTC); 1041 temp_reg = IXGB_READ_REG(hw, MCFRC); 1042 temp_reg = IXGB_READ_REG(hw, MCFTC); 1043 temp_reg = IXGB_READ_REG(hw, XONRXC); 1044 temp_reg = IXGB_READ_REG(hw, XONTXC); 1045 temp_reg = IXGB_READ_REG(hw, XOFFRXC); 1046 temp_reg = IXGB_READ_REG(hw, XOFFTXC); 1047 temp_reg = IXGB_READ_REG(hw, RJC); 1048 return; 1049} 1050 1051 1052/****************************************************************************** 1053 * Turns on the software controllable LED 1054 * 1055 * hw - Struct containing variables accessed by shared code 1056 *****************************************************************************/ 1057void 1058ixgb_led_on(struct ixgb_hw *hw) 1059{ 1060 uint32_t ctrl0_reg = IXGB_READ_REG(hw, CTRL0); 1061 1062 /* To turn on the LED, clear software-definable pin 0 (SDP0). */ 1063 ctrl0_reg &= ~IXGB_CTRL0_SDP0; 1064 IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg); 1065 return; 1066} 1067 1068/****************************************************************************** 1069 * Turns off the software controllable LED 1070 * 1071 * hw - Struct containing variables accessed by shared code 1072 *****************************************************************************/ 1073void 1074ixgb_led_off(struct ixgb_hw *hw) 1075{ 1076 uint32_t ctrl0_reg = IXGB_READ_REG(hw, CTRL0); 1077 1078 /* To turn off the LED, set software-definable pin 0 (SDP0). */ 1079 ctrl0_reg |= IXGB_CTRL0_SDP0; 1080 IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg); 1081 return; 1082} 1083 1084 1085/****************************************************************************** 1086 * Gets the current PCI bus type, speed, and width of the hardware 1087 * 1088 * hw - Struct containing variables accessed by shared code 1089 *****************************************************************************/ 1090static void 1091ixgb_get_bus_info(struct ixgb_hw *hw) 1092{ 1093 uint32_t status_reg; 1094 1095 status_reg = IXGB_READ_REG(hw, STATUS); 1096 1097 hw->bus.type = (status_reg & IXGB_STATUS_PCIX_MODE) ? 1098 ixgb_bus_type_pcix : ixgb_bus_type_pci; 1099 1100 if (hw->bus.type == ixgb_bus_type_pci) { 1101 hw->bus.speed = (status_reg & IXGB_STATUS_PCI_SPD) ? 1102 ixgb_bus_speed_66 : ixgb_bus_speed_33; 1103 } else { 1104 switch (status_reg & IXGB_STATUS_PCIX_SPD_MASK) { 1105 case IXGB_STATUS_PCIX_SPD_66: 1106 hw->bus.speed = ixgb_bus_speed_66; 1107 break; 1108 case IXGB_STATUS_PCIX_SPD_100: 1109 hw->bus.speed = ixgb_bus_speed_100; 1110 break; 1111 case IXGB_STATUS_PCIX_SPD_133: 1112 hw->bus.speed = ixgb_bus_speed_133; 1113 break; 1114 default: 1115 hw->bus.speed = ixgb_bus_speed_reserved; 1116 break; 1117 } 1118 } 1119 1120 hw->bus.width = (status_reg & IXGB_STATUS_BUS64) ? 1121 ixgb_bus_width_64 : ixgb_bus_width_32; 1122 1123 return; 1124} 1125 1126 1127 1128/****************************************************************************** 1129 * Tests a MAC address to ensure it is a valid Individual Address 1130 * 1131 * mac_addr - pointer to MAC address. 1132 * 1133 *****************************************************************************/ 1134boolean_t 1135mac_addr_valid(uint8_t *mac_addr) 1136{ 1137 boolean_t is_valid = TRUE; 1138 DEBUGFUNC("mac_addr_valid"); 1139 1140 1141 /* Make sure it is not a multicast address */ 1142 if (IS_MULTICAST(mac_addr)) { 1143 DEBUGOUT("MAC address is multicast\n"); 1144 is_valid = FALSE; 1145 } 1146 /* Not a broadcast address */ 1147 else if (IS_BROADCAST(mac_addr)) { 1148 DEBUGOUT("MAC address is broadcast\n"); 1149 is_valid = FALSE; 1150 } 1151 /* Reject the zero address */ 1152 else if (mac_addr[0] == 0 && 1153 mac_addr[1] == 0 && 1154 mac_addr[2] == 0 && 1155 mac_addr[3] == 0 && 1156 mac_addr[4] == 0 && 1157 mac_addr[5] == 0) { 1158 DEBUGOUT("MAC address is all zeros\n"); 1159 is_valid = FALSE; 1160 } 1161 return (is_valid); 1162} 1163 1164/****************************************************************************** 1165 * Resets the 10GbE link. Waits the settle time and returns the state of 1166 * the link. 1167 * 1168 * hw - Struct containing variables accessed by shared code 1169 *****************************************************************************/ 1170boolean_t 1171ixgb_link_reset(struct ixgb_hw *hw) 1172{ 1173 boolean_t link_status = FALSE; 1174 uint8_t wait_retries = MAX_RESET_ITERATIONS; 1175 uint8_t lrst_retries = MAX_RESET_ITERATIONS; 1176 1177 1178 do { 1179 /* Reset the link */ 1180 IXGB_WRITE_REG(hw, CTRL0, IXGB_READ_REG(hw, CTRL0) | IXGB_CTRL0_LRST); 1181 1182 /* Wait for link-up and lane re-alignment */ 1183 do { 1184 usec_delay(IXGB_DELAY_USECS_AFTER_LINK_RESET); 1185 link_status = ((IXGB_READ_REG(hw, STATUS) & IXGB_STATUS_LU) && 1186 (IXGB_READ_REG(hw, XPCSS) & IXGB_XPCSS_ALIGN_STATUS)) ? 1187 TRUE : FALSE; 1188 } while (!link_status && -- wait_retries); 1189 1190 } while (!link_status && --lrst_retries); 1191 1192 return link_status; 1193} 1194 1195 1196 1197/****************************************************************************** 1198 * Resets the 10GbE optics module. 1199 * 1200 * hw - Struct containing variables accessed by shared code 1201 *****************************************************************************/ 1202void 1203ixgb_optics_reset(struct ixgb_hw *hw) 1204{ 1205 if (hw->phy_type == ixgb_phy_type_txn17401) { 1206 uint16_t mdio_reg; 1207 1208 ixgb_write_phy_reg( hw, 1209 MDIO_PMA_PMD_CR1, 1210 IXGB_PHY_ADDRESS, 1211 MDIO_PMA_PMD_DID, 1212 MDIO_PMA_PMD_CR1_RESET); 1213 1214 mdio_reg = ixgb_read_phy_reg( hw, 1215 MDIO_PMA_PMD_CR1, 1216 IXGB_PHY_ADDRESS, 1217 MDIO_PMA_PMD_DID); 1218 } 1219 1220 return; 1221} 1222 1223