1/******************************************************************************* 2 3Copyright (c) 2001-2004, Intel Corporation 4All rights reserved. 5 6Redistribution and use in source and binary forms, with or without 7modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30POSSIBILITY OF SUCH DAMAGE. 31 32***************************************************************************/ 33/*$FreeBSD$*/ 34 35#ifndef _IXGB_H_DEFINED_ 36#define _IXGB_H_DEFINED_ 37 38 39#include <sys/param.h> 40#include <sys/systm.h> 41#include <sys/mbuf.h> 42#include <sys/protosw.h> 43#include <sys/socket.h> 44#include <sys/malloc.h> 45#include <sys/module.h> 46#include <sys/kernel.h> 47#include <sys/sockio.h> 48 49#include <net/if.h> 50#include <net/if_var.h> 51#include <net/if_arp.h> 52#include <net/ethernet.h> 53#include <net/if_dl.h> 54#include <net/if_media.h> 55#include <net/if_types.h> 56 57#include <net/bpf.h> 58#include <net/if_types.h> 59#include <net/if_vlan_var.h> 60 61#include <netinet/in_systm.h> 62#include <netinet/in.h> 63#include <netinet/ip.h> 64#include <netinet/tcp.h> 65#include <netinet/udp.h> 66 67#include <sys/bus.h> 68#include <machine/bus.h> 69#include <sys/rman.h> 70#include <machine/resource.h> 71#if __FreeBSD_version >= 502000 72#include <dev/pci/pcivar.h> 73#include <dev/pci/pcireg.h> 74#else 75#include <pci/pcivar.h> 76#include <pci/pcireg.h> 77#endif 78#include <sys/proc.h> 79#include <sys/sysctl.h> 80#include <sys/endian.h> 81 82#include <dev/ixgb/ixgb_hw.h> 83#include <dev/ixgb/ixgb_ee.h> 84#include <dev/ixgb/ixgb_ids.h> 85 86/* Tunables */ 87 88/* 89 * TxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 90 * number of transmit descriptors allocated by the driver. Increasing this 91 * value allows the driver to queue more transmits. Each descriptor is 16 92 * bytes. 93 */ 94#define IXGB_MAX_TXD 256 95 96/* 97 * RxDescriptors Valid Range: 64-4096 Default Value: 1024 This value is the 98 * number of receive descriptors allocated by the driver. Increasing this 99 * value allows the driver to buffer more incoming packets. Each descriptor 100 * is 16 bytes. A receive buffer is also allocated for each descriptor. The 101 * maximum MTU size is 16110. 102 * 103 */ 104#define IXGB_MAX_RXD 1024 105 106/* 107 * TxIntDelay Valid Range: 0-65535 (0=off) Default Value: 32 This value 108 * delays the generation of transmit interrupts in units of 1.024 109 * microseconds. Transmit interrupt reduction can improve CPU efficiency if 110 * properly tuned for specific network traffic. If the system is reporting 111 * dropped transmits, this value may be set too high causing the driver to 112 * run out of available transmit descriptors. 113 */ 114#define TIDV 32 115 116/* 117 * RxIntDelay Valid Range: 0-65535 (0=off) Default Value: 72 This value 118 * delays the generation of receive interrupts in units of 1.024 119 * microseconds. Receive interrupt reduction can improve CPU efficiency if 120 * properly tuned for specific network traffic. Increasing this value adds 121 * extra latency to frame reception and can end up decreasing the throughput 122 * of TCP traffic. If the system is reporting dropped receives, this value 123 * may be set too high, causing the driver to run out of available receive 124 * descriptors. 125 * 126 */ 127#define RDTR 72 128 129 130/* 131 * This parameter controls the maximum no of times the driver will loop in 132 * the isr. Minimum Value = 1 133 */ 134#define IXGB_MAX_INTR 3 135 136 137/* 138 * Inform the stack about transmit checksum offload capabilities. 139 */ 140#define IXGB_CHECKSUM_FEATURES (CSUM_TCP | CSUM_UDP) 141 142/* 143 * This parameter controls the duration of transmit watchdog timer. 144 */ 145#define IXGB_TX_TIMEOUT 5 /* set to 5 seconds */ 146 147/* 148 * This parameter controls when the driver calls the routine to reclaim 149 * transmit descriptors. 150 */ 151#define IXGB_TX_CLEANUP_THRESHOLD IXGB_MAX_TXD / 8 152 153/* 154 * Flow Control Types. 155 * 1. ixgb_fc_none - Flow Control Disabled 156 * 2. ixgb_fc_rx_pause - Flow Control Receive Only 157 * 3. ixgb_fc_tx_pause - Flow Control Transmit Only 158 * 4. ixgb_fc_full - Flow Control Enabled 159 */ 160#define FLOW_CONTROL_NONE ixgb_fc_none 161#define FLOW_CONTROL_RX_PAUSE ixgb_fc_rx_pause 162#define FLOW_CONTROL_TX_PAUSE ixgb_fc_tx_pause 163#define FLOW_CONTROL_FULL ixgb_fc_full 164 165/* 166 * Set the flow control type. Assign one of the above flow control types to be enabled. 167 * Default Value: FLOW_CONTROL_FULL 168 */ 169#define FLOW_CONTROL FLOW_CONTROL_FULL 170 171/* 172 * Receive Flow control low threshold (when we send a resume frame) (FCRTL) 173 * Valid Range: 64 - 262,136 (0x40 - 0x3FFF8, 8 byte granularity) must be 174 * less than high threshold by at least 8 bytes Default Value: 163,840 175 * (0x28000) 176 */ 177#define FCRTL 0x28000 178 179/* 180 * Receive Flow control high threshold (when we send a pause frame) (FCRTH) 181 * Valid Range: 1,536 - 262,136 (0x600 - 0x3FFF8, 8 byte granularity) Default 182 * Value: 196,608 (0x30000) 183 */ 184#define FCRTH 0x30000 185 186/* 187 * Flow control request timeout (how long to pause the link partner's tx) 188 * (PAP 15:0) Valid Range: 1 - 65535 Default Value: 256 (0x100) 189 */ 190#define FCPAUSE 0x100 191 192/* Tunables -- End */ 193 194 195#define IXGB_VENDOR_ID 0x8086 196#define IXGB_MMBA 0x0010 /* Mem base address */ 197#define IXGB_ROUNDUP(size, unit) (((size) + (unit) - 1) & ~((unit) - 1)) 198 199#define IOCTL_CMD_TYPE u_long 200#define MAX_NUM_MULTICAST_ADDRESSES 128 201#define PCI_ANY_ID (~0U) 202#define ETHER_ALIGN 2 203 204/* Defines for printing debug information */ 205#define DEBUG_INIT 0 206#define DEBUG_IOCTL 0 207#define DEBUG_HW 0 208#define _SV_ 0 209 210#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 211#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 212#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 213#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 214#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 215#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 216#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 217#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 218#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 219 220 221/* Supported RX Buffer Sizes */ 222#define IXGB_RXBUFFER_2048 2048 223#define IXGB_RXBUFFER_4096 4096 224#define IXGB_RXBUFFER_8192 8192 225#define IXGB_RXBUFFER_16384 16384 226 227#define IXGB_MAX_SCATTER 100 228 229/* 230 * ****************************************************************************** 231 * vendor_info_array 232 * 233 * This array contains the list of Subvendor/Subdevice IDs on which the driver 234 * should load. 235 * 236***************************************************************************** 237 */ 238typedef struct _ixgb_vendor_info_t { 239 unsigned int vendor_id; 240 unsigned int device_id; 241 unsigned int subvendor_id; 242 unsigned int subdevice_id; 243 unsigned int index; 244} ixgb_vendor_info_t; 245 246 247struct ixgb_buffer { 248 struct mbuf *m_head; 249 bus_dmamap_t map; /* bus_dma map for packet */ 250}; 251 252/* 253 * Bus dma allocation structure used by ixgb_dma_malloc and ixgb_dma_free. 254 */ 255struct ixgb_dma_alloc { 256 bus_addr_t dma_paddr; 257 caddr_t dma_vaddr; 258 bus_dma_tag_t dma_tag; 259 bus_dmamap_t dma_map; 260 bus_dma_segment_t dma_seg; 261 bus_size_t dma_size; 262 int dma_nseg; 263}; 264 265typedef enum _XSUM_CONTEXT_T { 266 OFFLOAD_NONE, 267 OFFLOAD_TCP_IP, 268 OFFLOAD_UDP_IP 269} XSUM_CONTEXT_T; 270 271/* Our adapter structure */ 272struct adapter { 273 struct ifnet *ifp; 274 struct adapter *next; 275 struct adapter *prev; 276 struct ixgb_hw hw; 277 278 /* FreeBSD operating-system-specific structures */ 279 struct ixgb_osdep osdep; 280 struct device *dev; 281 struct resource *res_memory; 282 struct resource *res_ioport; 283 struct resource *res_interrupt; 284 void *int_handler_tag; 285 struct ifmedia media; 286 struct callout timer; 287 int io_rid; 288 int tx_timer; 289 struct mtx mtx; 290 291 /* Info about the board itself */ 292 u_int32_t part_num; 293 u_int8_t link_active; 294 u_int16_t link_speed; 295 u_int16_t link_duplex; 296 u_int32_t tx_int_delay; 297 u_int32_t tx_abs_int_delay; 298 u_int32_t rx_int_delay; 299 u_int32_t rx_abs_int_delay; 300 301 int raidc; 302 303 XSUM_CONTEXT_T active_checksum_context; 304 305 /* 306 * Transmit definitions 307 * 308 * We have an array of num_tx_desc descriptors (handled by the 309 * controller) paired with an array of tx_buffers (at 310 * tx_buffer_area). The index of the next available descriptor is 311 * next_avail_tx_desc. The number of remaining tx_desc is 312 * num_tx_desc_avail. 313 */ 314 struct ixgb_dma_alloc txdma; /* bus_dma glue for tx desc */ 315 struct ixgb_tx_desc *tx_desc_base; 316 u_int32_t next_avail_tx_desc; 317 u_int32_t oldest_used_tx_desc; 318 volatile u_int16_t num_tx_desc_avail; 319 u_int16_t num_tx_desc; 320 u_int32_t txd_cmd; 321 struct ixgb_buffer *tx_buffer_area; 322 bus_dma_tag_t txtag; /* dma tag for tx */ 323 324 /* 325 * Receive definitions 326 * 327 * we have an array of num_rx_desc rx_desc (handled by the controller), 328 * and paired with an array of rx_buffers (at rx_buffer_area). The 329 * next pair to check on receive is at offset next_rx_desc_to_check 330 */ 331 struct ixgb_dma_alloc rxdma; /* bus_dma glue for rx desc */ 332 struct ixgb_rx_desc *rx_desc_base; 333 u_int32_t next_rx_desc_to_check; 334 u_int16_t num_rx_desc; 335 u_int32_t rx_buffer_len; 336 struct ixgb_buffer *rx_buffer_area; 337 bus_dma_tag_t rxtag; /* dma tag for Rx */ 338 u_int32_t next_rx_desc_to_use; 339 340 341 /* Jumbo frame */ 342 struct mbuf *fmp; 343 struct mbuf *lmp; 344 345 struct sysctl_ctx_list sysctl_ctx; 346 struct sysctl_oid *sysctl_tree; 347 348 /* Multicast array memory */ 349 u_int8_t *mta; 350 /* Misc stats maintained by the driver */ 351 unsigned long dropped_pkts; 352 unsigned long mbuf_alloc_failed; 353 unsigned long mbuf_cluster_failed; 354 unsigned long no_tx_desc_avail1; 355 unsigned long no_tx_desc_avail2; 356 unsigned long no_tx_map_avail; 357 unsigned long no_tx_dma_setup; 358 359 boolean_t in_detach; 360 361 /* Board specific private data */ 362#ifdef _SV_ 363 struct ixgb_sv_stats { 364 uint64_t icr_rxdmt0; 365 uint64_t icr_rxo; 366 uint64_t icr_rxt0; 367 uint64_t icr_TXDW; 368 } sv_stats; 369 unsigned long no_pkts_avail; 370 unsigned long clean_tx_interrupts; 371#endif 372 373 struct ixgb_hw_stats stats; 374}; 375 376#define IXGB_LOCK_INIT(_sc, _name) \ 377 mtx_init(&(_sc)->mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 378#define IXGB_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx) 379#define IXGB_LOCK(_sc) mtx_lock(&(_sc)->mtx) 380#define IXGB_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx) 381#define IXGB_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED) 382 383#endif /* _IXGB_H_DEFINED_ */ 384